diff options
| -rw-r--r-- | arch/sh/mm/tlb-pteaex.c | 28 | ||||
| -rw-r--r-- | arch/sh/mm/tlb-sh3.c | 19 | ||||
| -rw-r--r-- | arch/sh/mm/tlb-sh4.c | 28 | ||||
| -rw-r--r-- | arch/sh/mm/tlbflush_32.c | 28 |
4 files changed, 75 insertions, 28 deletions
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c index bdd0982b56e..b71db6af806 100644 --- a/arch/sh/mm/tlb-pteaex.c +++ b/arch/sh/mm/tlb-pteaex.c @@ -77,3 +77,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); back_to_cached(); } + +void local_flush_tlb_all(void) +{ + unsigned long flags, status; + int i; + + /* + * Flush all the TLB. + */ + local_irq_save(flags); + jump_to_uncached(); + + status = __raw_readl(MMUCR); + status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); + + if (status == 0) + status = MMUCR_URB_NENTRIES; + + for (i = 0; i < status; i++) + __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); + + for (i = 0; i < 4; i++) + __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); + + back_to_cached(); + ctrl_barrier(); + local_irq_restore(flags); +} diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c index 4f5f7cbdd50..7a940dbfc2e 100644 --- a/arch/sh/mm/tlb-sh3.c +++ b/arch/sh/mm/tlb-sh3.c @@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) for (i = 0; i < ways; i++) __raw_writel(data, addr + (i << 8)); } + +void local_flush_tlb_all(void) +{ + unsigned long flags, status; + + /* + * Flush all the TLB. + * + * Write to the MMU control register's bit: + * TF-bit for SH-3, TI-bit for SH-4. + * It's same position, bit #2. + */ + local_irq_save(flags); + status = __raw_readl(MMUCR); + status |= 0x04; + __raw_writel(status, MMUCR); + ctrl_barrier(); + local_irq_restore(flags); +} diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index ccac77f504a..cfdf7930d29 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c @@ -80,3 +80,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) __raw_writel(data, addr); back_to_cached(); } + +void local_flush_tlb_all(void) +{ + unsigned long flags, status; + int i; + + /* + * Flush all the TLB. + */ + local_irq_save(flags); + jump_to_uncached(); + + status = __raw_readl(MMUCR); + status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); + + if (status == 0) + status = MMUCR_URB_NENTRIES; + + for (i = 0; i < status; i++) + __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); + + for (i = 0; i < 4; i++) + __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); + + back_to_cached(); + ctrl_barrier(); + local_irq_restore(flags); +} diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c index 77dc5efa712..3fbe03ce8fe 100644 --- a/arch/sh/mm/tlbflush_32.c +++ b/arch/sh/mm/tlbflush_32.c @@ -119,31 +119,3 @@ void local_flush_tlb_mm(struct mm_struct *mm) local_irq_restore(flags); } } - -void local_flush_tlb_all(void) -{ - unsigned long flags, status; - int i; - - /* - * Flush all the TLB. - */ - local_irq_save(flags); - jump_to_uncached(); - - status = __raw_readl(MMUCR); - status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); - - if (status == 0) - status = MMUCR_URB_NENTRIES; - - for (i = 0; i < status; i++) - __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); - - for (i = 0; i < 4; i++) - __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); - - back_to_cached(); - ctrl_barrier(); - local_irq_restore(flags); -} |