diff options
| -rw-r--r-- | arch/x86/mm/pageattr-test.c | 4 | ||||
| -rw-r--r-- | arch/x86/mm/pageattr.c | 9 | ||||
| -rw-r--r-- | include/asm-x86/pgtable.h | 6 |
3 files changed, 13 insertions, 6 deletions
diff --git a/arch/x86/mm/pageattr-test.c b/arch/x86/mm/pageattr-test.c index 6cc106b388a..d7a93008cc1 100644 --- a/arch/x86/mm/pageattr-test.c +++ b/arch/x86/mm/pageattr-test.c @@ -16,14 +16,12 @@ enum { NTEST = 400, + LOWEST_LEVEL = PG_LEVEL_4K, #ifdef CONFIG_X86_64 - LOWEST_LEVEL = 4, LPS = (1 << PMD_SHIFT), #elif defined(CONFIG_X86_PAE) - LOWEST_LEVEL = 4, LPS = (1 << PMD_SHIFT), #else - LOWEST_LEVEL = 4, /* lookup_address lies here */ LPS = (1 << 22), #endif GPS = (1<<30) diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index a270f9ccebf..4589a1382fa 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -28,6 +28,8 @@ pte_t *lookup_address(unsigned long address, int *level) pud_t *pud; pmd_t *pmd; + *level = PG_LEVEL_NONE; + if (pgd_none(*pgd)) return NULL; pud = pud_offset(pgd, address); @@ -36,11 +38,12 @@ pte_t *lookup_address(unsigned long address, int *level) pmd = pmd_offset(pud, address); if (pmd_none(*pmd)) return NULL; - *level = 3; + + *level = PG_LEVEL_2M; if (pmd_large(*pmd)) return (pte_t *)pmd; - *level = 4; + *level = PG_LEVEL_4K; return pte_offset_kernel(pmd, address); } @@ -145,7 +148,7 @@ repeat: address < (unsigned long)&_etext && (pgprot_val(prot) & _PAGE_NX)); - if (level == 4) { + if (level == PG_LEVEL_4K) { set_pte_atomic(kpte, mk_pte(page, canon_pgprot(prot))); } else { err = split_large_page(kpte, address); diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h index 4409dabe31c..7aa34c8eb22 100644 --- a/include/asm-x86/pgtable.h +++ b/include/asm-x86/pgtable.h @@ -234,6 +234,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #ifndef __ASSEMBLY__ +enum { + PG_LEVEL_NONE, + PG_LEVEL_4K, + PG_LEVEL_2M, +}; + /* * Helper function that returns the kernel pagetable entry controlling * the virtual address 'address'. NULL means no pagetable entry present. |