diff options
22 files changed, 1520 insertions, 226 deletions
diff --git a/Documentation/devicetree/bindings/video/exynos7-decon.txt b/Documentation/devicetree/bindings/video/exynos7-decon.txt new file mode 100644 index 00000000000..f5f9c8d4a55 --- /dev/null +++ b/Documentation/devicetree/bindings/video/exynos7-decon.txt @@ -0,0 +1,68 @@ +Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) + +DECON (Display and Enhancement Controller) is the Display Controller for the +Exynos7 series of SoCs which transfers the image data from a video memory +buffer to an external LCD interface. + +Required properties: +- compatible: value should be "samsung,exynos7-decon"; + +- reg: physical base address and length of the DECON registers set. + +- interrupt-parent: should be the phandle of the decon controller's + parent interrupt controller. + +- interrupts: should contain a list of all DECON IP block interrupts in the + order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier + format depends on the interrupt controller used. + +- interrupt-names: should contain the interrupt names: "fifo", "vsync", + "lcd_sys", in the same order as they were listed in the interrupts + property. + +- pinctrl-0: pin control group to be used for this controller. + +- pinctrl-names: must contain a "default" entry. + +- clocks: must include clock specifiers corresponding to entries in the + clock-names property. + +- clock-names: list of clock names sorted in the same order as the clocks + property. Must contain "pclk_decon0", "aclk_decon0", + "decon0_eclk", "decon0_vclk". +- i80-if-timings: timing configuration for lcd i80 interface support. + +Optional Properties: +- samsung,power-domain: a phandle to DECON power domain node. +- display-timings: timing settings for DECON, as described in document [1]. + Can be used in case timings cannot be provided otherwise + or to override timings provided by the panel. + +[1]: Documentation/devicetree/bindings/video/display-timing.txt + +Example: + +SoC specific DT entry: + + decon@13930000 { + compatible = "samsung,exynos7-decon"; + interrupt-parent = <&combiner>; + reg = <0x13930000 0x1000>; + interrupt-names = "lcd_sys", "vsync", "fifo"; + interrupts = <0 188 0>, <0 189 0>, <0 190 0>; + clocks = <&clock_disp PCLK_DECON_INT>, + <&clock_disp ACLK_DECON_INT>, + <&clock_disp SCLK_DECON_INT_ECLK>, + <&clock_disp SCLK_DECON_INT_EXTCLKPLL>; + clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk", + "decon0_vclk"; + status = "disabled"; + }; + +Board specific DT entry: + + decon@13930000 { + pinctrl-0 = <&lcd_clk &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt b/Documentation/devicetree/bindings/video/exynos_mixer.txt index 08b394b1edb..3e38128f866 100644 --- a/Documentation/devicetree/bindings/video/exynos_mixer.txt +++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt @@ -15,6 +15,7 @@ Required properties: a) mixer: Gate of Mixer IP bus clock. b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of mixer mux. + c) hdmi: Gate of HDMI IP bus clock, needed together with sclk_hdmi. Example: diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index c072999b7e0..a5e74612100 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -12,16 +12,9 @@ config DRM_EXYNOS If M is selected the module will be called exynosdrm. config DRM_EXYNOS_IOMMU - bool "EXYNOS DRM IOMMU Support" + bool depends on DRM_EXYNOS && EXYNOS_IOMMU && ARM_DMA_USE_IOMMU - help - Choose this option if you want to use IOMMU feature for DRM. - -config DRM_EXYNOS_DMABUF - bool "EXYNOS DRM DMABUF" - depends on DRM_EXYNOS - help - Choose this option if you want to use DMABUF feature for DRM. + default y config DRM_EXYNOS_FIMD bool "Exynos DRM FIMD" @@ -31,9 +24,16 @@ config DRM_EXYNOS_FIMD help Choose this option if you want to use Exynos FIMD for DRM. +config DRM_EXYNOS7_DECON + bool "Exynos DRM DECON" + depends on DRM_EXYNOS + select FB_MODE_HELPERS + help + Choose this option if you want to use Exynos DECON for DRM. + config DRM_EXYNOS_DPI bool "EXYNOS DRM parallel output support" - depends on DRM_EXYNOS_FIMD + depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) select DRM_PANEL default n help @@ -41,7 +41,7 @@ config DRM_EXYNOS_DPI config DRM_EXYNOS_DSI bool "EXYNOS DRM MIPI-DSI driver support" - depends on DRM_EXYNOS_FIMD + depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) select DRM_MIPI_DSI select DRM_PANEL default n @@ -50,7 +50,7 @@ config DRM_EXYNOS_DSI config DRM_EXYNOS_DP bool "EXYNOS DRM DP driver support" - depends on DRM_EXYNOS_FIMD && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) + depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) default DRM_EXYNOS select DRM_PANEL help diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile index 33ae3652b8d..cc90679cfc0 100644 --- a/drivers/gpu/drm/exynos/Makefile +++ b/drivers/gpu/drm/exynos/Makefile @@ -6,11 +6,11 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/exynos exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o \ exynos_drm_crtc.o exynos_drm_fbdev.o exynos_drm_fb.o \ exynos_drm_buf.o exynos_drm_gem.o exynos_drm_core.o \ - exynos_drm_plane.o + exynos_drm_plane.o exynos_drm_dmabuf.o exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o -exynosdrm-$(CONFIG_DRM_EXYNOS_DMABUF) += exynos_drm_dmabuf.o exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o +exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c new file mode 100644 index 00000000000..63f02e2380a --- /dev/null +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -0,0 +1,990 @@ +/* drivers/gpu/drm/exynos/exynos7_drm_decon.c + * + * Copyright (C) 2014 Samsung Electronics Co.Ltd + * Authors: + * Akshu Agarwal <akshua@gmail.com> + * Ajay Kumar <ajaykumar.rs@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include <drm/drmP.h> +#include <drm/exynos_drm.h> + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +#include <video/of_display_timing.h> +#include <video/of_videomode.h> +#include <video/exynos7_decon.h> + +#include "exynos_drm_crtc.h" +#include "exynos_drm_drv.h" +#include "exynos_drm_fbdev.h" +#include "exynos_drm_iommu.h" + +/* + * DECON stands for Display and Enhancement controller. + */ + +#define DECON_DEFAULT_FRAMERATE 60 +#define MIN_FB_WIDTH_FOR_16WORD_BURST 128 + +#define WINDOWS_NR 2 + +struct decon_win_data { + unsigned int ovl_x; + unsigned int ovl_y; + unsigned int offset_x; + unsigned int offset_y; + unsigned int ovl_width; + unsigned int ovl_height; + unsigned int fb_width; + unsigned int fb_height; + unsigned int bpp; + unsigned int pixel_format; + dma_addr_t dma_addr; + bool enabled; + bool resume; +}; + +struct decon_context { + struct device *dev; + struct drm_device *drm_dev; + struct exynos_drm_crtc *crtc; + struct clk *pclk; + struct clk *aclk; + struct clk *eclk; + struct clk *vclk; + void __iomem *regs; + struct decon_win_data win_data[WINDOWS_NR]; + unsigned int default_win; + unsigned long irq_flags; + bool i80_if; + bool suspended; + int pipe; + wait_queue_head_t wait_vsync_queue; + atomic_t wait_vsync_event; + + struct exynos_drm_panel_info panel; + struct exynos_drm_display *display; +}; + +static const struct of_device_id decon_driver_dt_match[] = { + {.compatible = "samsung,exynos7-decon"}, + {}, +}; +MODULE_DEVICE_TABLE(of, decon_driver_dt_match); + +static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) +{ + struct decon_context *ctx = crtc->ctx; + + if (ctx->suspended) + return; + + atomic_set(&ctx->wait_vsync_event, 1); + + /* + * wait for DECON to signal VSYNC interrupt or return after + * timeout which is set to 50ms (refresh rate of 20). + */ + if (!wait_event_timeout(ctx->wait_vsync_queue, + !atomic_read(&ctx->wait_vsync_event), + HZ/20)) + DRM_DEBUG_KMS("vblank wait timed out.\n"); +} + +static void decon_clear_channel(struct decon_context *ctx) +{ + int win, ch_enabled = 0; + + DRM_DEBUG_KMS("%s\n", __FILE__); + + /* Check if any channel is enabled. */ + for (win = 0; win < WINDOWS_NR; win++) { + u32 val = readl(ctx->regs + WINCON(win)); + + if (val & WINCONx_ENWIN) { + val &= ~WINCONx_ENWIN; + writel(val, ctx->regs + WINCON(win)); + ch_enabled = 1; + } + } + + /* Wait for vsync, as disable channel takes effect at next vsync */ + if (ch_enabled) { + unsigned int state = ctx->suspended; + + ctx->suspended = 0; + decon_wait_for_vblank(ctx->crtc); + ctx->suspended = state; + } +} + +static int decon_ctx_initialize(struct decon_context *ctx, + struct drm_device *drm_dev) +{ + struct exynos_drm_private *priv = drm_dev->dev_private; + + ctx->drm_dev = drm_dev; + ctx->pipe = priv->pipe++; + + /* attach this sub driver to iommu mapping if supported. */ + if (is_drm_iommu_supported(ctx->drm_dev)) { + int ret; + + /* + * If any channel is already active, iommu will throw + * a PAGE FAULT when enabled. So clear any channel if enabled. + */ + decon_clear_channel(ctx); + ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev); + if (ret) { + DRM_ERROR("drm_iommu_attach failed.\n"); + return ret; + } + } + + return 0; +} + +static void decon_ctx_remove(struct decon_context *ctx) +{ + /* detach this sub driver from iommu mapping if supported. */ + if (is_drm_iommu_supported(ctx->drm_dev)) + drm_iommu_detach_device(ctx->drm_dev, ctx->dev); +} + +static u32 decon_calc_clkdiv(struct decon_context *ctx, + const struct drm_display_mode *mode) +{ + unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; + u32 clkdiv; + + /* Find the clock divider value that gets us closest to ideal_clk */ + clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); + + return (clkdiv < 0x100) ? clkdiv : 0xff; +} + +static bool decon_mode_fixup(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + if (adjusted_mode->vrefresh == 0) + adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE; + + return true; +} + +static void decon_commit(struct exynos_drm_crtc *crtc) +{ + struct decon_context *ctx = crtc->ctx; + struct drm_display_mode *mode = &crtc->base.mode; + u32 val, clkdiv; + + if (ctx->suspended) + return; + + /* nothing to do if we haven't set the mode yet */ + if (mode->htotal == 0 || mode->vtotal == 0) + return; + + if (!ctx->i80_if) { + int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; + /* setup vertical timing values. */ + vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; + vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; + vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; + + val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); + writel(val, ctx->regs + VIDTCON0); + + val = VIDTCON1_VSPW(vsync_len - 1); + writel(val, ctx->regs + VIDTCON1); + + /* setup horizontal timing values. */ + hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; + hbpd = mode->crtc_htotal - mode->crtc_hsync_end; + hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; + + /* setup horizontal timing values. */ + val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); + writel(val, ctx->regs + VIDTCON2); + + val = VIDTCON3_HSPW(hsync_len - 1); + writel(val, ctx->regs + VIDTCON3); + } + + /* setup horizontal and vertical display size. */ + val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | + VIDTCON4_HOZVAL(mode->hdisplay - 1); + writel(val, ctx->regs + VIDTCON4); + + writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); + + /* + * fields of register with prefix '_F' would be updated + * at vsync(same as dma start) + */ + val = VIDCON0_ENVID | VIDCON0_ENVID_F; + writel(val, ctx->regs + VIDCON0); + + clkdiv = decon_calc_clkdiv(ctx, mode); + if (clkdiv > 1) { + val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); + writel(val, ctx->regs + VCLKCON1); + writel(val, ctx->regs + VCLKCON2); + } + + val = readl(ctx->regs + DECON_UPDATE); + val |= DECON_UPDATE_STANDALONE_F; + writel(val, ctx->regs + DECON_UPDATE); +} + +static int decon_enable_vblank(struct exynos_drm_crtc *crtc) +{ + struct decon_context *ctx = crtc->ctx; + u32 val; + + if (ctx->suspended) + return -EPERM; + + if (!test_and_set_bit(0, &ctx->irq_flags)) { + val = readl(ctx->regs + VIDINTCON0); + + val |= VIDINTCON0_INT_ENABLE; + + if (!ctx->i80_if) { + val |= VIDINTCON0_INT_FRAME; + val &= ~VIDINTCON0_FRAMESEL0_MASK; + val |= VIDINTCON0_FRAMESEL0_VSYNC; + } + + writel(val, ctx->regs + VIDINTCON0); + } + + return 0; +} + +static void decon_disable_vblank(struct exynos_drm_crtc *crtc) +{ + struct decon_context *ctx = crtc->ctx; + u32 val; + + if (ctx->suspended) + return; + + if (test_and_clear_bit(0, &ctx->irq_flags)) { + val = readl(ctx->regs + VIDINTCON0); + + val &= ~VIDINTCON0_INT_ENABLE; + if (!ctx->i80_if) + val &= ~VIDINTCON0_INT_FRAME; + + writel(val, ctx->regs + VIDINTCON0); + } +} + +static void decon_win_mode_set(struct exynos_drm_crtc *crtc, + struct exynos_drm_plane *plane) +{ + struct decon_context *ctx = crtc->ctx; + struct decon_win_data *win_data; + int win, padding; + + if (!plane) { + DRM_ERROR("plane is NULL\n"); + return; + } + + win = plane->zpos; + if (win == DEFAULT_ZPOS) + win = ctx->default_win; + + if (win < 0 || win >= WINDOWS_NR) + return; + + + win_data = &ctx->win_data[win]; + + padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; + win_data->offset_x = plane->fb_x; + win_data->offset_y = plane->fb_y; + win_data->fb_width = plane->fb_width + padding; + win_data->fb_height = plane->fb_height; + win_data->ovl_x = plane->crtc_x; + win_data->ovl_y = plane->crtc_y; + win_data->ovl_width = plane->crtc_width; + win_data->ovl_height = plane->crtc_height; + win_data->dma_addr = plane->dma_addr[0]; + win_data->bpp = plane->bpp; + win_data->pixel_format = plane->pixel_format; + + DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", + win_data->offset_x, win_data->offset_y); + DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", + win_data->ovl_width, win_data->ovl_height); + DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); + DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", + plane->fb_width, plane->crtc_width); +} + +static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win) +{ + struct decon_win_data *win_data = &ctx->win_data[win]; + unsigned long val; + + val = readl(ctx->regs + WINCON(win)); + val &= ~WINCONx_BPPMODE_MASK; + + switch (win_data->pixel_format) { + case DRM_FORMAT_RGB565: + val |= WINCONx_BPPMODE_16BPP_565; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_XRGB8888: + val |= WINCONx_BPPMODE_24BPP_xRGB; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_XBGR8888: + val |= WINCONx_BPPMODE_24BPP_xBGR; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_RGBX8888: + val |= WINCONx_BPPMODE_24BPP_RGBx; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_BGRX8888: + val |= WINCONx_BPPMODE_24BPP_BGRx; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_ARGB8888: + val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | + WINCONx_ALPHA_SEL; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_ABGR8888: + val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | + WINCONx_ALPHA_SEL; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_RGBA8888: + val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | + WINCONx_ALPHA_SEL; + val |= WINCONx_BURSTLEN_16WORD; + break; + case DRM_FORMAT_BGRA8888: + val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | + WINCONx_ALPHA_SEL; + val |= WINCONx_BURSTLEN_16WORD; + break; + default: + DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); + + val |= WINCONx_BPPMODE_24BPP_xRGB; + val |= WINCONx_BURSTLEN_16WORD; + break; + } + + DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); + + /* + * In case of exynos, setting dma-burst to 16Word causes permanent + * tearing for very small buffers, e.g. cursor buffer. Burst Mode + * switching which is based on plane size is not recommended as + * plane size varies a lot towards the end of the screen and rapid + * movement causes unstable DMA which results into iommu crash/tear. + */ + + if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) { + val &= ~WINCONx_BURSTLEN_MASK; + val |= WINCONx_BURSTLEN_8WORD; + } + + writel(val, ctx->regs + WINCON(win)); +} + +static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) +{ + unsigned int keycon0 = 0, keycon1 = 0; + + keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | + WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); + + keycon1 = WxKEYCON1_COLVAL(0xffffffff); + + writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); + writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); +} + +/** + * shadow_protect_win() - disable updating values from shadow registers at vsync + * + * @win: window to protect registers for + * @protect: 1 to protect (disable updates) + */ +static void decon_shadow_protect_win(struct decon_context *ctx, + int win, bool protect) +{ + u32 bits, val; + + bits = SHADOWCON_WINx_PROTECT(win); + + val = readl(ctx->regs + SHADOWCON); + if (protect) + val |= bits; + else + val &= ~bits; + writel(val, ctx->regs + SHADOWCON); +} + +static void decon_win_commit(struct exynos_drm_crtc *crtc, int zpos) +{ + struct decon_context *ctx = crtc->ctx; + struct drm_display_mode *mode = &crtc->base.mode; + struct decon_win_data *win_data; + int win = zpos; + unsigned long val, alpha; + unsigned int last_x; + unsigned int last_y; + + if (ctx->suspended) + return; + + if (win == DEFAULT_ZPOS) + win = ctx->default_win; + + if (win < 0 || win >= WINDOWS_NR) + return; + + win_data = &ctx->win_data[win]; + + /* If suspended, enable this on resume */ + if (ctx->suspended) { + win_data->resume = true; + return; + } + + /* + * SHADOWCON/PRTCON register is used for enabling timing. + * + * for example, once only width value of a register is set, + * if the dma is started then decon hardware could malfunction so + * with protect window setting, the register fields with prefix '_F' + * wouldn't be updated at vsync also but updated once unprotect window + * is set. + */ + + /* protect windows */ + decon_shadow_protect_win(ctx, win, true); + + /* buffer start address */ + val = (unsigned long)win_data->dma_addr; + writel(val, ctx->regs + VIDW_BUF_START(win)); + + /* buffer size */ + writel(win_data->fb_width, ctx->regs + VIDW_WHOLE_X(win)); + writel(win_data->fb_height, ctx->regs + VIDW_WHOLE_Y(win)); + + /* offset from the start of the buffer to read */ + writel(win_data->offset_x, ctx->regs + VIDW_OFFSET_X(win)); + writel(win_data->offset_y, ctx->regs + VIDW_OFFSET_Y(win)); + + DRM_DEBUG_KMS("start addr = 0x%lx\n", + (unsigned long)win_data->dma_addr); + DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", + win_data->ovl_width, win_data->ovl_height); + + /* + * OSD position. + * In case the window layout goes of LCD layout, DECON fails. + */ + if ((win_data->ovl_x + win_data->ovl_width) > mode->hdisplay) + win_data->ovl_x = mode->hdisplay - win_data->ovl_width; + if ((win_data->ovl_y + win_data->ovl_height) > mode->vdisplay) + win_data->ovl_y = mode->vdisplay - win_data->ovl_height; + + val = VIDOSDxA_TOPLEFT_X(win_data->ovl_x) | + VIDOSDxA_TOPLEFT_Y(win_data->ovl_y); + writel(val, ctx->regs + VIDOSD_A(win)); + + last_x = win_data->ovl_x + win_data->ovl_width; + if (last_x) + last_x--; + last_y = win_data->ovl_y + win_data->ovl_height; + if (last_y) + last_y--; + + val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); + + writel(val, ctx->regs + VIDOSD_B(win)); + + DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", + win_data->ovl_x, win_data->ovl_y, last_x, last_y); + + /* OSD alpha */ + alpha = VIDOSDxC_ALPHA0_R_F(0x0) | + VIDOSDxC_ALPHA0_G_F(0x0) | + VIDOSDxC_ALPHA0_B_F(0x0); + + writel(alpha, ctx->regs + VIDOSD_C(win)); + + alpha = VIDOSDxD_ALPHA1_R_F(0xff) | + VIDOSDxD_ALPHA1_G_F(0xff) | + VIDOSDxD_ALPHA1_B_F(0xff); + + writel(alpha, ctx->regs + VIDOSD_D(win)); + + decon_win_set_pixfmt(ctx, win); + + /* hardware window 0 doesn't support color key. */ + if (win != 0) + decon_win_set_colkey(ctx, win); + + /* wincon */ + val = readl(ctx->regs + WINCON(win)); + val |= WINCONx_TRIPLE_BUF_MODE; + val |= WINCONx_ENWIN; + writel(val, ctx->regs + WINCON(win)); + + /* Enable DMA channel and unprotect windows */ + decon_shadow_protect_win(ctx, win, false); + + val = readl(ctx->regs + DECON_UPDATE); + val |= DECON_UPDATE_STANDALONE_F; + writel(val, ctx->regs + DECON_UPDATE); + + win_data->enabled = true; +} + +static void decon_win_disable(struct exynos_drm_crtc *crtc, int zpos) +{ + struct decon_context *ctx = crtc->ctx; + struct decon_win_data *win_data; + int win = zpos; + u32 val; + + if (win == DEFAULT_ZPOS) + win = ctx->default_win; + + if (win < 0 || win >= WINDOWS_NR) + return; + + win_data = &ctx->win_data[win]; + + if (ctx->suspended) { + /* do not resume this window*/ + win_data->resume = false; + return; + } + + /* protect windows */ + decon_shadow_protect_win(ctx, win, true); + + /* wincon */ + val = readl(ctx->regs + WINCON(win)); + val &= ~WINCONx_ENWIN; + writel(val, ctx->regs + WINCON(win)); + + /* unprotect windows */ + decon_shadow_protect_win(ctx, win, false); + + val = readl(ctx->regs + DECON_UPDATE); + val |= DECON_UPDATE_STANDALONE_F; + writel(val, ctx->regs + DECON_UPDATE); + + win_data->enabled = false; +} + +static void decon_window_suspend(struct decon_context *ctx) +{ + struct decon_win_data *win_data; + int i; + + for (i = 0; i < WINDOWS_NR; i++) { + win_data = &ctx->win_data[i]; + win_data->resume = win_data->enabled; + if (win_data->enabled) + decon_win_disable(ctx->crtc, i); + } +} + +static void decon_window_resume(struct decon_context *ctx) +{ + struct decon_win_data *win_data; + int i; + + for (i = 0; i < WINDOWS_NR; i++) { + win_data = &ctx->win_data[i]; + win_data->enabled = win_data->resume; + win_data->resume = false; + } +} + +static void decon_apply(struct decon_context *ctx) +{ + struct decon_win_data *win_data; + int i; + + for (i = 0; i < WINDOWS_NR; i++) { + win_data = &ctx->win_data[i]; + if (win_data->enabled) + decon_win_commit(ctx->crtc, i); + else + decon_win_disable(ctx->crtc, i); + } + + decon_commit(ctx->crtc); +} + +static void decon_init(struct decon_context *ctx) +{ + u32 val; + + writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); + + val = VIDOUTCON0_DISP_IF_0_ON; + if (!ctx->i80_if) + val |= VIDOUTCON0_RGBIF; + writel(val, ctx->regs + VIDOUTCON0); + + writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); + + if (!ctx->i80_if) + writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); +} + +static int decon_poweron(struct decon_context *ctx) +{ + int ret; + + if (!ctx->suspended) + return 0; + + ctx->suspended = false; + + pm_runtime_get_sync(ctx->dev); + + ret = clk_prepare_enable(ctx->pclk); + if (ret < 0) { + DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); + goto pclk_err; + } + + ret = clk_prepare_enable(ctx->aclk); + if (ret < 0) { + DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); + goto aclk_err; + } + + ret = clk_prepare_enable(ctx->eclk); + if (ret < 0) { + DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); + goto eclk_err; + } + + ret = clk_prepare_enable(ctx->vclk); + if (ret < 0) { + DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); + goto vclk_err; + } + + decon_init(ctx); + + /* if vblank was enabled status, enable it again. */ + if (test_and_clear_bit(0, &ctx->irq_flags)) { + ret = decon_enable_vblank(ctx->crtc); + if (ret) { + DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); + goto err; + } + } + + decon_window_resume(ctx); + + decon_apply(ctx); + + return 0; + +err: + clk_disable_unprepare(ctx->vclk); +vclk_err: + clk_disable_unprepare(ctx->eclk); +eclk_err: + clk_disable_unprepare(ctx->aclk); +aclk_err: + clk_disable_unprepare(ctx->pclk); +pclk_err: + ctx->suspended = true; + return ret; +} + +static int decon_poweroff(struct decon_context *ctx) +{ + if (ctx->suspended) + return 0; + + /* + * We need to make sure that all windows are disabled before we + * suspend that connector. Otherwise we might try to scan from + * a destroyed buffer later. + */ + decon_window_suspend(ctx); + + clk_disable_unprepare(ctx->vclk); + clk_disable_unprepare(ctx->eclk); + clk_disable_unprepare(ctx->aclk); + clk_disable_unprepare(ctx->pclk); + + pm_runtime_put_sync(ctx->dev); + + ctx->suspended = true; + return 0; +} + +static void decon_dpms(struct exynos_drm_crtc *crtc, int mode) +{ + DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); + + switch (mode) { + case DRM_MODE_DPMS_ON: + decon_poweron(crtc->ctx); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + decon_poweroff(crtc->ctx); + break; + default: + DRM_DEBUG_KMS("unspecified mode %d\n", mode); + break; + } +} + +static struct exynos_drm_crtc_ops decon_crtc_ops = { + .dpms = decon_dpms, + .mode_fixup = decon_mode_fixup, + .commit = decon_commit, + .enable_vblank = decon_enable_vblank, + .disable_vblank = decon_disable_vblank, + .wait_for_vblank = decon_wait_for_vblank, + .win_mode_set = decon_win_mode_set, + .win_commit = decon_win_commit, + .win_disable = decon_win_disable, +}; + + +static irqreturn_t decon_irq_handler(int irq, void *dev_id) +{ + struct decon_context *ctx = (struct decon_context *)dev_id; + u32 val, clear_bit; + + val = readl(ctx->regs + VIDINTCON1); + + clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; + if (val & clear_bit) + writel(clear_bit, ctx->regs + VIDINTCON1); + + /* check the crtc is detached already from encoder */ + if (ctx->pipe < 0 || !ctx->drm_dev) + goto out; + + if (!ctx->i80_if) { + drm_handle_vblank(ctx->drm_dev, ctx->pipe); + exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); + + /* set wait vsync event to zero and wake up queue. */ + if (atomic_read(&ctx->wait_vsync_event)) { + atomic_set(&ctx->wait_vsync_event, 0); + wake_up(&ctx->wait_vsync_queue); + } + } +out: + return IRQ_HANDLED; +} + +static int decon_bind(struct device *dev, struct device *master, void *data) +{ + struct decon_context *ctx = dev_get_drvdata(dev); + struct drm_device *drm_dev = data; + int ret; + + ret = decon_ctx_initialize(ctx, drm_dev); + if (ret) { + DRM_ERROR("decon_ctx_initialize failed.\n"); + return ret; + } + + ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, + EXYNOS_DISPLAY_TYPE_LCD, + &decon_crtc_ops, ctx); + if (IS_ERR(ctx->crtc)) { + decon_ctx_remove(ctx); + return PTR_ERR(ctx->crtc); + } + + if (ctx->display) + exynos_drm_create_enc_conn(drm_dev, ctx->display); + + return 0; + +} + +static void decon_unbind(struct device *dev, struct device *master, + void *data) +{ + struct decon_context *ctx = dev_get_drvdata(dev); + + decon_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); + + if (ctx->display) + exynos_dpi_remove(ctx->display); + + decon_ctx_remove(ctx); +} + +static const struct component_ops decon_component_ops = { + .bind = decon_bind, + .unbind = decon_unbind, +}; + +static int decon_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct decon_context *ctx; + struct device_node *i80_if_timings; + struct resource *res; + int ret; + + if (!dev->of_node) + return -ENODEV; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC, + EXYNOS_DISPLAY_TYPE_LCD); + if (ret) + return ret; + + ctx->dev = dev; + ctx->suspended = true; + + i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); + if (i80_if_timings) + ctx->i80_if = true; + of_node_put(i80_if_timings); + + ctx->regs = of_iomap(dev->of_node, 0); + if (IS_ERR(ctx->regs)) { + ret = PTR_ERR(ctx->regs); + goto err_del_component; + } + + ctx->pclk = devm_clk_get(dev, "pclk_decon0"); + if (IS_ERR(ctx->pclk)) { + dev_err(dev, "failed to get bus clock pclk\n"); + ret = PTR_ERR(ctx->pclk); + goto err_iounmap; + } + + ctx->aclk = devm_clk_get(dev, "aclk_decon0"); + if (IS_ERR(ctx->aclk)) { + dev_err(dev, "failed to get bus clock aclk\n"); + ret = PTR_ERR(ctx->aclk); + goto err_iounmap; + } + + ctx->eclk = devm_clk_get(dev, "decon0_eclk"); + if (IS_ERR(ctx->eclk)) { + dev_err(dev, "failed to get eclock\n"); + ret = PTR_ERR(ctx->eclk); + goto err_iounmap; + } + + ctx->vclk = devm_clk_get(dev, "decon0_vclk"); + if (IS_ERR(ctx->vclk)) { + dev_err(dev, "failed to get vclock\n"); + ret = PTR_ERR(ctx->vclk); + goto err_iounmap; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + ctx->i80_if ? "lcd_sys" : "vsync"); + if (!res) { + dev_err(dev, "irq request failed.\n"); + ret = -ENXIO; + goto err_iounmap; + } + + ret = devm_request_irq(dev, res->start, decon_irq_handler, + 0, "drm_decon", ctx); + if (ret) { + dev_err(dev, "irq request failed.\n"); + goto err_iounmap; + } + + init_waitqueue_head(&ctx->wait_vsync_queue); + atomic_set(&ctx->wait_vsync_event, 0); + + platform_set_drvdata(pdev, ctx); + + ctx->display = exynos_dpi_probe(dev); + if (IS_ERR(ctx->display)) { + ret = PTR_ERR(ctx->display); + goto err_iounmap; + } + + pm_runtime_enable(dev); + + ret = component_add(dev, &decon_component_ops); + if (ret) + goto err_disable_pm_runtime; + + return ret; + +err_disable_pm_runtime: + pm_runtime_disable(dev); + +err_iounmap: + iounmap(ctx->regs); + +err_del_component: + exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC); + return ret; +} + +static int decon_remove(struct platform_device *pdev) +{ + struct decon_context *ctx = dev_get_drvdata(&pdev->dev); + + pm_runtime_disable(&pdev->dev); + + iounmap(ctx->regs); + + component_del(&pdev->dev, &decon_component_ops); + exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC); + + return 0; +} + +struct platform_driver decon_driver = { + .probe = decon_probe, + .remove = decon_remove, + .driver = { + .name = "exynos-decon", + .of_match_table = decon_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index 46f149737bc..bf17a60b40e 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -1058,10 +1058,8 @@ static void exynos_dp_phy_exit(struct exynos_dp_device *dp) phy_power_off(dp->phy); } -static void exynos_dp_poweron(struct exynos_drm_display *display) +static void exynos_dp_poweron(struct exynos_dp_device *dp) { - struct exynos_dp_device *dp = display_to_dp(display); - if (dp->dpms_mode == DRM_MODE_DPMS_ON) return; @@ -1076,13 +1074,11 @@ static void exynos_dp_poweron(struct exynos_drm_display *display) exynos_dp_phy_init(dp); exynos_dp_init_dp(dp); enable_irq(dp->irq); - exynos_dp_commit(display); + exynos_dp_commit(&dp->display); } -static void exynos_dp_poweroff(struct exynos_drm_display *display) +static void exynos_dp_poweroff(struct exynos_dp_device *dp) { - struct exynos_dp_device *dp = display_to_dp(display); - if (dp->dpms_mode != DRM_MODE_DPMS_ON) return; @@ -1110,12 +1106,12 @@ static void exynos_dp_dpms(struct exynos_drm_display *display, int mode) switch (mode) { case DRM_MODE_DPMS_ON: - exynos_dp_poweron(display); + exynos_dp_poweron(dp); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - exynos_dp_poweroff(display); + exynos_dp_poweroff(dp); break; default: break; diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.c b/drivers/gpu/drm/exynos/exynos_drm_buf.c index 9c8088462c2..24994ba10e2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_buf.c +++ b/drivers/gpu/drm/exynos/exynos_drm_buf.c @@ -63,11 +63,11 @@ static int lowlevel_buffer_allocate(struct drm_device *dev, return -ENOMEM; } - buf->kvaddr = (void __iomem *)dma_alloc_attrs(dev->dev, + buf->cookie = dma_alloc_attrs(dev->dev, buf->size, &buf->dma_addr, GFP_KERNEL, &buf->dma_attrs); - if (!buf->kvaddr) { + if (!buf->cookie) { DRM_ERROR("failed to allocate buffer.\n"); ret = -ENOMEM; goto err_free; @@ -132,7 +132,7 @@ static void lowlevel_buffer_deallocate(struct drm_device *dev, buf->sgt = NULL; if (!is_drm_iommu_supported(dev)) { - dma_free_attrs(dev->dev, buf->size, buf->kvaddr, + dma_free_attrs(dev->dev, buf->size, buf->cookie, (dma_addr_t)buf->dma_addr, &buf->dma_attrs); drm_free_large(buf->pages); } else diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index a85c451ba39..48ccab7fdf6 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -66,8 +66,6 @@ static void exynos_drm_crtc_commit(struct drm_crtc *crtc) if (exynos_crtc->ops->commit) exynos_crtc->ops->commit(exynos_crtc); - - exynos_plane_dpms(crtc->primary, DRM_MODE_DPMS_ON); } static bool @@ -234,70 +232,12 @@ static void exynos_drm_crtc_destroy(struct drm_crtc *crtc) kfree(exynos_crtc); } -static int exynos_drm_crtc_set_property(struct drm_crtc *crtc, - struct drm_property *property, - uint64_t val) -{ - struct drm_device *dev = crtc->dev; - struct exynos_drm_private *dev_priv = dev->dev_private; - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - - if (property == dev_priv->crtc_mode_property) { - enum exynos_crtc_mode mode = val; - - if (mode == exynos_crtc->mode) - return 0; - - exynos_crtc->mode = mode; - - switch (mode) { - case CRTC_MODE_NORMAL: - exynos_drm_crtc_commit(crtc); - break; - case CRTC_MODE_BLANK: - exynos_plane_dpms(crtc->primary, DRM_MODE_DPMS_OFF); - break; - default: - break; - } - - return 0; - } - - return -EINVAL; -} - static struct drm_crtc_funcs exynos_crtc_funcs = { .set_config = drm_crtc_helper_set_config, .page_flip = exynos_drm_crtc_page_flip, .destroy = exynos_drm_crtc_destroy, - .set_property = exynos_drm_crtc_set_property, -}; - -static const struct drm_prop_enum_list mode_names[] = { - { CRTC_MODE_NORMAL, "normal" }, - { CRTC_MODE_BLANK, "blank" }, }; -static void exynos_drm_crtc_attach_mode_property(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct exynos_drm_private *dev_priv = dev->dev_private; - struct drm_property *prop; - - prop = dev_priv->crtc_mode_property; - if (!prop) { - prop = drm_property_create_enum(dev, 0, "mode", mode_names, - ARRAY_SIZE(mode_names)); - if (!prop) - return; - - dev_priv->crtc_mode_property = prop; - } - - drm_object_attach_property(&crtc->base, prop, 0); -} - struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, int pipe, enum exynos_drm_output_type type, @@ -340,8 +280,6 @@ struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, drm_crtc_helper_add(crtc, &exynos_crtc_helper_funcs); - exynos_drm_crtc_attach_mode_property(crtc); - return exynos_crtc; err_crtc: diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c index 60192ed544f..3833bf8ca02 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.c @@ -279,7 +279,3 @@ err_buf_detach: return ERR_PTR(ret); } - -MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>"); -MODULE_DESCRIPTION("Samsung SoC DRM DMABUF Module"); -MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h index 49acfafb4fd..886de9ff484 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h +++ b/drivers/gpu/drm/exynos/exynos_drm_dmabuf.h @@ -12,14 +12,9 @@ #ifndef _EXYNOS_DRM_DMABUF_H_ #define _EXYNOS_DRM_DMABUF_H_ -#ifdef CONFIG_DRM_EXYNOS_DMABUF struct dma_buf *exynos_dmabuf_prime_export(struct drm_device *drm_dev, struct drm_gem_object *obj, int flags); struct drm_gem_object *exynos_dmabuf_prime_import(struct drm_device *drm_dev, struct dma_buf *dma_buf); -#else -#define exynos_dmabuf_prime_export NULL -#define exynos_dmabuf_prime_import NULL -#endif #endif diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 1bcbe07cecf..90168d7cf66 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -556,6 +556,9 @@ static struct platform_driver *const exynos_drm_kms_drivers[] = { #ifdef CONFIG_DRM_EXYNOS_FIMD &fimd_driver, #endif +#ifdef CONFIG_DRM_EXYNOS7_DECON + &decon_driver, +#endif #ifdef CONFIG_DRM_EXYNOS_DP &dp_driver, #endif @@ -612,6 +615,7 @@ static const char * const strings[] = { "samsung,exynos3", "samsung,exynos4", "samsung,exynos5", + "samsung,exynos7", }; static struct platform_driver exynos_drm_platform_driver = { diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index d490b49f71c..9afd390d467 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -197,11 +197,6 @@ struct exynos_drm_crtc_ops { void (*te_handler)(struct exynos_drm_crtc *crtc); }; -enum exynos_crtc_mode { - CRTC_MODE_NORMAL, /* normal mode */ - CRTC_MODE_BLANK, /* The private plane of crtc is blank */ -}; - /* * Exynos specific crtc structure. * @@ -215,7 +210,6 @@ enum exynos_crtc_mode { * we can refer to the crtc to current hardware interrupt occurred through * this pipe value. * @dpms: store the crtc dpms value - * @mode: store the crtc mode value * @ops: pointer to callbacks for exynos drm specific functionality * @ctx: A pointer to the crtc's implementation specific context */ @@ -224,7 +218,6 @@ struct exynos_drm_crtc { enum exynos_drm_output_type type; unsigned int pipe; unsigned int dpms; - enum exynos_crtc_mode mode; wait_queue_head_t pending_flip_queue; atomic_t pending_flip; struct exynos_drm_crtc_ops *ops; @@ -265,7 +258,6 @@ struct exynos_drm_private { */ struct drm_crtc *crtc[MAX_CRTC]; struct drm_property *plane_zpos_property; - struct drm_property *crtc_mode_property; unsigned long da_start; unsigned long da_space_size; @@ -352,6 +344,7 @@ void exynos_drm_component_del(struct device *dev, enum exynos_drm_device_type dev_type); extern struct platform_driver fimd_driver; +extern struct platform_driver decon_driver; extern struct platform_driver dp_driver; extern struct platform_driver dsi_driver; extern struct platform_driver mixer_driver; diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c index 7e282e3d603..57de0bdc5a3 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c +++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c @@ -102,7 +102,7 @@ static void exynos_drm_encoder_disable(struct drm_encoder *encoder) /* all planes connected to this encoder should be also disabled. */ drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { - if (plane->crtc == encoder->crtc) + if (plane->crtc && (plane->crtc == encoder->crtc)) plane->funcs->disable_plane(plane); } } diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index e12ea90c623..84f8dfe1c5e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -79,9 +79,9 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, struct drm_framebuffer *fb) { struct fb_info *fbi = helper->fbdev; - struct drm_device *dev = helper->dev; struct exynos_drm_gem_buf *buffer; unsigned int size = fb->width * fb->height * (fb->bits_per_pixel >> 3); + unsigned int nr_pages; unsigned long offset; drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->depth); @@ -94,25 +94,14 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, return -EFAULT; } - /* map pages with kernel virtual space. */ + nr_pages = buffer->size >> PAGE_SHIFT; + + buffer->kvaddr = (void __iomem *) vmap(buffer->pages, + nr_pages, VM_MAP, + pgprot_writecombine(PAGE_KERNEL)); if (!buffer->kvaddr) { - if (is_drm_iommu_supported(dev)) { - unsigned int nr_pages = buffer->size >> PAGE_SHIFT; - - buffer->kvaddr = (void __iomem *) vmap(buffer->pages, - nr_pages, VM_MAP, - pgprot_writecombine(PAGE_KERNEL)); - } else { - phys_addr_t dma_addr = buffer->dma_addr; - if (dma_addr) - buffer->kvaddr = (void __iomem *)phys_to_virt(dma_addr); - else - buffer->kvaddr = (void __iomem *)NULL; - } - if (!buffer->kvaddr) { - DRM_ERROR("failed to map pages to kernel space.\n"); - return -EIO; - } + DRM_ERROR("failed to map pages to kernel space.\n"); + return -EIO; } /* buffer count to framebuffer always is 1 at booting time. */ @@ -313,7 +302,7 @@ static void exynos_drm_fbdev_destroy(struct drm_device *dev, struct exynos_drm_gem_obj *exynos_gem_obj = exynos_fbd->exynos_gem_obj; struct drm_framebuffer *fb; - if (is_drm_iommu_supported(dev) && exynos_gem_obj->buffer->kvaddr) + if (exynos_gem_obj->buffer->kvaddr) vunmap(exynos_gem_obj->buffer->kvaddr); /* release drm framebuffer and real buffer */ diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 682806ef4d3..925fc69af1a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -253,9 +253,8 @@ static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win, writel(val, ctx->regs + SHADOWCON); } -static void fimd_clear_channel(struct exynos_drm_crtc *crtc) +static void fimd_clear_channel(struct fimd_context *ctx) { - struct fimd_context *ctx = crtc->ctx; int win, ch_enabled = 0; DRM_DEBUG_KMS("%s\n", __FILE__); @@ -280,7 +279,7 @@ static void fimd_clear_channel(struct exynos_drm_crtc *crtc) unsigned int state = ctx->suspended; ctx->suspended = 0; - fimd_wait_for_vblank(crtc); + fimd_wait_for_vblank(ctx->crtc); ctx->suspended = state; } } @@ -302,7 +301,7 @@ static int fimd_ctx_initialize(struct fimd_context *ctx, * If any channel is already active, iommu will throw * a PAGE FAULT when enabled. So clear any channel if enabled. */ - fimd_clear_channel(ctx->crtc); + fimd_clear_channel(ctx); ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev); if (ret) { DRM_ERROR("drm_iommu_attach failed.\n"); @@ -823,9 +822,8 @@ static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos) win_data->enabled = false; } -static void fimd_window_suspend(struct exynos_drm_crtc *crtc) +static void fimd_window_suspend(struct fimd_context *ctx) { - struct fimd_context *ctx = crtc->ctx; struct fimd_win_data *win_data; int i; @@ -833,13 +831,12 @@ static void fimd_window_suspend(struct exynos_drm_crtc *crtc) win_data = &ctx->win_data[i]; win_data->resume = win_data->enabled; if (win_data->enabled) - fimd_win_disable(crtc, i); + fimd_win_disable(ctx->crtc, i); } } -static void fimd_window_resume(struct exynos_drm_crtc *crtc) +static void fimd_window_resume(struct fimd_context *ctx) { - struct fimd_context *ctx = crtc->ctx; struct fimd_win_data *win_data; int i; @@ -850,26 +847,24 @@ static void fimd_window_resume(struct exynos_drm_crtc *crtc) } } -static void fimd_apply(struct exynos_drm_crtc *crtc) +static void fimd_apply(struct fimd_context *ctx) { - struct fimd_context *ctx = crtc->ctx; struct fimd_win_data *win_data; int i; for (i = 0; i < WINDOWS_NR; i++) { win_data = &ctx->win_data[i]; if (win_data->enabled) - fimd_win_commit(crtc, i); + fimd_win_commit(ctx->crtc, i); else - fimd_win_disable(crtc, i); + fimd_win_disable(ctx->crtc, i); } - fimd_commit(crtc); + fimd_commit(ctx->crtc); } -static int fimd_poweron(struct exynos_drm_crtc *crtc) +static int fimd_poweron(struct fimd_context *ctx) { - struct fimd_context *ctx = crtc->ctx; int ret; if (!ctx->suspended) @@ -893,16 +888,16 @@ static int fimd_poweron(struct exynos_drm_crtc *crtc) /* if vblank was enabled status, enable it again. */ if (test_and_clear_bit(0, &ctx->irq_flags)) { - ret = fimd_enable_vblank(crtc); + ret = fimd_enable_vblank(ctx->crtc); if (ret) { DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); goto enable_vblank_err; } } - fimd_window_resume(crtc); + fimd_window_resume(ctx); - fimd_apply(crtc); + fimd_apply(ctx); return 0; @@ -915,10 +910,8 @@ bus_clk_err: return ret; } -static int fimd_poweroff(struct exynos_drm_crtc *crtc) +static int fimd_poweroff(struct fimd_context *ctx) { - struct fimd_context *ctx = crtc->ctx; - if (ctx->suspended) return 0; @@ -927,7 +920,7 @@ static int fimd_poweroff(struct exynos_drm_crtc *crtc) * suspend that connector. Otherwise we might try to scan from * a destroyed buffer later. */ - fimd_window_suspend(crtc); + fimd_window_suspend(ctx); clk_disable_unprepare(ctx->lcd_clk); clk_disable_unprepare(ctx->bus_clk); @@ -944,12 +937,12 @@ static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode) switch (mode) { case DRM_MODE_DPMS_ON: - fimd_poweron(crtc); + fimd_poweron(crtc->ctx); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - fimd_poweroff(crtc); + fimd_poweroff(crtc->ctx); break; default: DRM_DEBUG_KMS("unspecified mode %d\n", mode); @@ -1065,18 +1058,19 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; int ret; - ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, - EXYNOS_DISPLAY_TYPE_LCD, - &fimd_crtc_ops, ctx); - if (IS_ERR(ctx->crtc)) - return PTR_ERR(ctx->crtc); - ret = fimd_ctx_initialize(ctx, drm_dev); if (ret) { DRM_ERROR("fimd_ctx_initialize failed.\n"); return ret; } + ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, + EXYNOS_DISPLAY_TYPE_LCD, + &fimd_crtc_ops, ctx); + if (IS_ERR(ctx->crtc)) { + fimd_ctx_remove(ctx); + return PTR_ERR(ctx->crtc); + } if (ctx->display) exynos_drm_create_enc_conn(drm_dev, ctx->display); diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h index ec58fe9c40d..308173cb4f0 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.h +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h @@ -22,6 +22,7 @@ /* * exynos drm gem buffer structure. * + * @cookie: cookie returned by dma_alloc_attrs * @kvaddr: kernel virtual address to allocated memory region. * *userptr: user space address. * @dma_addr: bus address(accessed by dma) to allocated memory region. @@ -35,6 +36,7 @@ * VM_PFNMAP or not. */ struct exynos_drm_gem_buf { + void *cookie; void __iomem *kvaddr; unsigned long userptr; dma_addr_t dma_addr; diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 2f43a3c4f7b..a5616872eee 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -144,32 +144,6 @@ void exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc, exynos_crtc->ops->win_mode_set(exynos_crtc, exynos_plane); } -void exynos_plane_dpms(struct drm_plane *plane, int mode) -{ - struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane->crtc); - - if (mode == DRM_MODE_DPMS_ON) { - if (exynos_plane->enabled) - return; - - if (exynos_crtc->ops->win_enable) - exynos_crtc->ops->win_enable(exynos_crtc, - exynos_plane->zpos); - - exynos_plane->enabled = true; - } else { - if (!exynos_plane->enabled) - return; - - if (exynos_crtc->ops->win_disable) - exynos_crtc->ops->win_disable(exynos_crtc, - exynos_plane->zpos); - - exynos_plane->enabled = false; - } -} - int exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, int crtc_x, int crtc_y, @@ -198,7 +172,12 @@ exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, static int exynos_disable_plane(struct drm_plane *plane) { - exynos_plane_dpms(plane, DRM_MODE_DPMS_OFF); + struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); + struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane->crtc); + + if (exynos_crtc->ops->win_disable) + exynos_crtc->ops->win_disable(exynos_crtc, + exynos_plane->zpos); return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h index 59d40755095..9d3c374e7b3 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.h +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h @@ -20,7 +20,6 @@ int exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h); -void exynos_plane_dpms(struct drm_plane *plane, int mode); struct drm_plane *exynos_plane_init(struct drm_device *dev, unsigned long possible_crtcs, enum drm_plane_type type); diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 9c8300edd34..b886972b588 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -97,17 +97,16 @@ static const char fake_edid_info[] = { 0x00, 0x00, 0x00, 0x06 }; -static void vidi_apply(struct exynos_drm_crtc *crtc) +static void vidi_apply(struct vidi_context *ctx) { - struct vidi_context *ctx = crtc->ctx; - struct exynos_drm_crtc_ops *crtc_ops = crtc->ops; + struct exynos_drm_crtc_ops *crtc_ops = ctx->crtc->ops; struct vidi_win_data *win_data; int i; for (i = 0; i < WINDOWS_NR; i++) { win_data = &ctx->win_data[i]; if (win_data->enabled && (crtc_ops && crtc_ops->win_commit)) - crtc_ops->win_commit(crtc, i); + crtc_ops->win_commit(ctx->crtc, i); } } @@ -240,10 +239,8 @@ static void vidi_win_disable(struct exynos_drm_crtc *crtc, int zpos) /* TODO. */ } -static int vidi_power_on(struct exynos_drm_crtc *crtc, bool enable) +static int vidi_power_on(struct vidi_context *ctx, bool enable) { - struct vidi_context *ctx = crtc->ctx; - DRM_DEBUG_KMS("%s\n", __FILE__); if (enable != false && enable != true) @@ -254,9 +251,9 @@ static int vidi_power_on(struct exynos_drm_crtc *crtc, bool enable) /* if vblank was enabled status, enable it again. */ if (test_and_clear_bit(0, &ctx->irq_flags)) - vidi_enable_vblank(crtc); + vidi_enable_vblank(ctx->crtc); - vidi_apply(crtc); + vidi_apply(ctx); } else { ctx->suspended = true; } @@ -274,12 +271,12 @@ static void vidi_dpms(struct exynos_drm_crtc *crtc, int mode) switch (mode) { case DRM_MODE_DPMS_ON: - vidi_power_on(crtc, true); + vidi_power_on(ctx, true); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - vidi_power_on(crtc, false); + vidi_power_on(ctx, false); break; default: DRM_DEBUG_KMS("unspecified mode %d\n", mode); @@ -548,6 +545,8 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; int ret; + vidi_ctx_initialize(ctx, drm_dev); + ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, EXYNOS_DISPLAY_TYPE_VIDI, &vidi_crtc_ops, ctx); @@ -556,8 +555,6 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(ctx->crtc); } - vidi_ctx_initialize(ctx, drm_dev); - ret = exynos_drm_create_enc_conn(drm_dev, &ctx->display); if (ret) { ctx->crtc->base.funcs->destroy(&ctx->crtc->base); diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 98051e8e855..229b3613c60 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -2032,9 +2032,8 @@ static void hdmi_commit(struct exynos_drm_display *display) hdmi_conf_apply(hdata); } -static void hdmi_poweron(struct exynos_drm_display *display) +static void hdmi_poweron(struct hdmi_context *hdata) { - struct hdmi_context *hdata = display_to_hdmi(display); struct hdmi_resources *res = &hdata->res; mutex_lock(&hdata->hdmi_mutex); @@ -2060,12 +2059,11 @@ static void hdmi_poweron(struct exynos_drm_display *display) clk_prepare_enable(res->sclk_hdmi); hdmiphy_poweron(hdata); - hdmi_commit(display); + hdmi_commit(&hdata->display); } -static void hdmi_poweroff(struct exynos_drm_display *display) +static void hdmi_poweroff(struct hdmi_context *hdata) { - struct hdmi_context *hdata = display_to_hdmi(display); struct hdmi_resources *res = &hdata->res; mutex_lock(&hdata->hdmi_mutex); @@ -2109,7 +2107,7 @@ static void hdmi_dpms(struct exynos_drm_display *display, int mode) switch (mode) { case DRM_MODE_DPMS_ON: - hdmi_poweron(display); + hdmi_poweron(hdata); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: @@ -2128,7 +2126,7 @@ static void hdmi_dpms(struct exynos_drm_display *display, int mode) if (funcs && funcs->dpms) (*funcs->dpms)(crtc, mode); - hdmi_poweroff(display); + hdmi_poweroff(hdata); break; default: DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 2fd2e5d4614..3518bc4654c 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -72,6 +72,7 @@ struct mixer_resources { spinlock_t reg_slock; struct clk *mixer; struct clk *vp; + struct clk *hdmi; struct clk *sclk_mixer; struct clk *sclk_hdmi; struct clk *mout_mixer; @@ -580,8 +581,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) /* setup display size */ if (ctx->mxr_ver == MXR_VER_128_0_0_184 && win == MIXER_DEFAULT_WIN) { - val = MXR_MXR_RES_HEIGHT(win_data->fb_height); - val |= MXR_MXR_RES_WIDTH(win_data->fb_width); + val = MXR_MXR_RES_HEIGHT(win_data->mode_height); + val |= MXR_MXR_RES_WIDTH(win_data->mode_width); mixer_reg_write(res, MXR_RESOLUTION, val); } @@ -767,6 +768,12 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx) return -ENODEV; } + mixer_res->hdmi = devm_clk_get(dev, "hdmi"); + if (IS_ERR(mixer_res->hdmi)) { + dev_err(dev, "failed to get clock 'hdmi'\n"); + return PTR_ERR(mixer_res->hdmi); + } + mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); if (IS_ERR(mixer_res->sclk_hdmi)) { dev_err(dev, "failed to get clock 'sclk_hdmi'\n"); @@ -1045,23 +1052,21 @@ static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc) drm_vblank_put(mixer_ctx->drm_dev, mixer_ctx->pipe); } -static void mixer_window_suspend(struct exynos_drm_crtc *crtc) +static void mixer_window_suspend(struct mixer_context *ctx) { - struct mixer_context *ctx = crtc->ctx; struct hdmi_win_data *win_data; int i; for (i = 0; i < MIXER_WIN_NR; i++) { win_data = &ctx->win_data[i]; win_data->resume = win_data->enabled; - mixer_win_disable(crtc, i); + mixer_win_disable(ctx->crtc, i); } - mixer_wait_for_vblank(crtc); + mixer_wait_for_vblank(ctx->crtc); } -static void mixer_window_resume(struct exynos_drm_crtc *crtc) +static void mixer_window_resume(struct mixer_context *ctx) { - struct mixer_context *ctx = crtc->ctx; struct hdmi_win_data *win_data; int i; @@ -1070,13 +1075,12 @@ static void mixer_window_resume(struct exynos_drm_crtc *crtc) win_data->enabled = win_data->resume; win_data->resume = false; if (win_data->enabled) - mixer_win_commit(crtc, i); + mixer_win_commit(ctx->crtc, i); } } -static void mixer_poweron(struct exynos_drm_crtc *crtc) +static void mixer_poweron(struct mixer_context *ctx) { - struct mixer_context *ctx = crtc->ctx; struct mixer_resources *res = &ctx->mixer_res; mutex_lock(&ctx->mixer_mutex); @@ -1090,6 +1094,7 @@ static void mixer_poweron(struct exynos_drm_crtc *crtc) pm_runtime_get_sync(ctx->dev); clk_prepare_enable(res->mixer); + clk_prepare_enable(res->hdmi); if (ctx->vp_enabled) { clk_prepare_enable(res->vp); if (ctx->has_sclk) @@ -1105,12 +1110,11 @@ static void mixer_poweron(struct exynos_drm_crtc *crtc) mixer_reg_write(res, MXR_INT_EN, ctx->int_en); mixer_win_reset(ctx); - mixer_window_resume(crtc); + mixer_window_resume(ctx); } -static void mixer_poweroff(struct exynos_drm_crtc *crtc) +static void mixer_poweroff(struct mixer_context *ctx) { - struct mixer_context *ctx = crtc->ctx; struct mixer_resources *res = &ctx->mixer_res; mutex_lock(&ctx->mixer_mutex); @@ -1121,7 +1125,7 @@ static void mixer_poweroff(struct exynos_drm_crtc *crtc) mutex_unlock(&ctx->mixer_mutex); mixer_stop(ctx); - mixer_window_suspend(crtc); + mixer_window_suspend(ctx); ctx->int_en = mixer_reg_read(res, MXR_INT_EN); @@ -1129,6 +1133,7 @@ static void mixer_poweroff(struct exynos_drm_crtc *crtc) ctx->powered = false; mutex_unlock(&ctx->mixer_mutex); + clk_disable_unprepare(res->hdmi); clk_disable_unprepare(res->mixer); if (ctx->vp_enabled) { clk_disable_unprepare(res->vp); @@ -1143,12 +1148,12 @@ static void mixer_dpms(struct exynos_drm_crtc *crtc, int mode) { switch (mode) { case DRM_MODE_DPMS_ON: - mixer_poweron(crtc); + mixer_poweron(crtc->ctx); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - mixer_poweroff(crtc); + mixer_poweroff(crtc->ctx); break; default: DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode); @@ -1247,18 +1252,19 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) struct drm_device *drm_dev = data; int ret; + ret = mixer_initialize(ctx, drm_dev); + if (ret) + return ret; + ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, EXYNOS_DISPLAY_TYPE_HDMI, &mixer_crtc_ops, ctx); if (IS_ERR(ctx->crtc)) { + mixer_ctx_remove(ctx); ret = PTR_ERR(ctx->crtc); goto free_ctx; } - ret = mixer_initialize(ctx, drm_dev); - if (ret) - goto free_ctx; - return 0; free_ctx: diff --git a/include/video/exynos7_decon.h b/include/video/exynos7_decon.h new file mode 100644 index 00000000000..a62b11b613f --- /dev/null +++ b/include/video/exynos7_decon.h @@ -0,0 +1,349 @@ +/* include/video/exynos7_decon.h + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Ajay Kumar <ajaykumar.rs@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* VIDCON0 */ +#define VIDCON0 0x00 + +#define VIDCON0_SWRESET (1 << 28) +#define VIDCON0_DECON_STOP_STATUS (1 << 2) +#define VIDCON0_ENVID (1 << 1) +#define VIDCON0_ENVID_F (1 << 0) + +/* VIDOUTCON0 */ +#define VIDOUTCON0 0x4 + +#define VIDOUTCON0_DUAL_MASK (0x3 << 24) +#define VIDOUTCON0_DUAL_ON (0x3 << 24) +#define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24) +#define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24) +#define VIDOUTCON0_DUAL_OFF (0x0 << 24) +#define VIDOUTCON0_IF_SHIFT 23 +#define VIDOUTCON0_IF_MASK (0x1 << 23) +#define VIDOUTCON0_RGBIF (0x0 << 23) +#define VIDOUTCON0_I80IF (0x1 << 23) + +/* VIDCON3 */ +#define VIDCON3 0x8 + +/* VIDCON4 */ +#define VIDCON4 0xC +#define VIDCON4_FIFOCNT_START_EN (1 << 0) + +/* VCLKCON0 */ +#define VCLKCON0 0x10 +#define VCLKCON0_CLKVALUP (1 << 8) +#define VCLKCON0_VCLKFREE (1 << 0) + +/* VCLKCON */ +#define VCLKCON1 0x14 +#define VCLKCON1_CLKVAL_NUM_VCLK(val) (((val) & 0xff) << 0) +#define VCLKCON2 0x18 + +/* SHADOWCON */ +#define SHADOWCON 0x30 + +#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) + +/* WINCONx */ +#define WINCON(_win) (0x50 + ((_win) * 4)) + +#define WINCONx_BUFSTATUS (0x3 << 30) +#define WINCONx_BUFSEL_MASK (0x3 << 28) +#define WINCONx_BUFSEL_SHIFT 28 +#define WINCONx_TRIPLE_BUF_MODE (0x1 << 18) +#define WINCONx_DOUBLE_BUF_MODE (0x0 << 18) +#define WINCONx_BURSTLEN_16WORD (0x0 << 11) +#define WINCONx_BURSTLEN_8WORD (0x1 << 11) +#define WINCONx_BURSTLEN_MASK (0x1 << 11) +#define WINCONx_BURSTLEN_SHIFT 11 +#define WINCONx_BLD_PLANE (0 << 8) +#define WINCONx_BLD_PIX (1 << 8) +#define WINCONx_ALPHA_MUL (1 << 7) + +#define WINCONx_BPPMODE_MASK (0xf << 2) +#define WINCONx_BPPMODE_SHIFT 2 +#define WINCONx_BPPMODE_16BPP_565 (0x8 << 2) +#define WINCONx_BPPMODE_24BPP_BGRx (0x7 << 2) +#define WINCONx_BPPMODE_24BPP_RGBx (0x6 << 2) +#define WINCONx_BPPMODE_24BPP_xBGR (0x5 << 2) +#define WINCONx_BPPMODE_24BPP_xRGB (0x4 << 2) +#define WINCONx_BPPMODE_32BPP_BGRA (0x3 << 2) +#define WINCONx_BPPMODE_32BPP_RGBA (0x2 << 2) +#define WINCONx_BPPMODE_32BPP_ABGR (0x1 << 2) +#define WINCONx_BPPMODE_32BPP_ARGB (0x0 << 2) +#define WINCONx_ALPHA_SEL (1 << 1) +#define WINCONx_ENWIN (1 << 0) + +#define WINCON1_ALPHA_MUL_F (1 << 7) +#define WINCON2_ALPHA_MUL_F (1 << 7) +#define WINCON3_ALPHA_MUL_F (1 << 7) +#define WINCON4_ALPHA_MUL_F (1 << 7) + +/* VIDOSDxH: The height for the OSD image(READ ONLY)*/ +#define VIDOSD_H(_x) (0x80 + ((_x) * 4)) + +/* Frame buffer start addresses: VIDWxxADD0n */ +#define VIDW_BUF_START(_win) (0x80 + ((_win) * 0x10)) +#define VIDW_BUF_START1(_win) (0x84 + ((_win) * 0x10)) +#define VIDW_BUF_START2(_win) (0x88 + ((_win) * 0x10)) + +#define VIDW_WHOLE_X(_win) (0x0130 + ((_win) * 8)) +#define VIDW_WHOLE_Y(_win) (0x0134 + ((_win) * 8)) +#define VIDW_OFFSET_X(_win) (0x0170 + ((_win) * 8)) +#define VIDW_OFFSET_Y(_win) (0x0174 + ((_win) * 8)) +#define VIDW_BLKOFFSET(_win) (0x01B0 + ((_win) * 4)) +#define VIDW_BLKSIZE(win) (0x0200 + ((_win) * 4)) + +/* Interrupt controls register */ +#define VIDINTCON2 0x228 + +#define VIDINTCON1_INTEXTRA1_EN (1 << 1) +#define VIDINTCON1_INTEXTRA0_EN (1 << 0) + +/* Interrupt controls and status register */ +#define VIDINTCON3 0x22C + +#define VIDINTCON1_INTEXTRA1_PEND (1 << 1) +#define VIDINTCON1_INTEXTRA0_PEND (1 << 0) + +/* VIDOSDxA ~ VIDOSDxE */ +#define VIDOSD_BASE 0x230 + +#define OSD_STRIDE 0x20 + +#define VIDOSD_A(_win) (VIDOSD_BASE + \ + ((_win) * OSD_STRIDE) + 0x00) +#define VIDOSD_B(_win) (VIDOSD_BASE + \ + ((_win) * OSD_STRIDE) + 0x04) +#define VIDOSD_C(_win) (VIDOSD_BASE + \ + ((_win) * OSD_STRIDE) + 0x08) +#define VIDOSD_D(_win) (VIDOSD_BASE + \ + ((_win) * OSD_STRIDE) + 0x0C) +#define VIDOSD_E(_win) (VIDOSD_BASE + \ + ((_win) * OSD_STRIDE) + 0x10) + +#define VIDOSDxA_TOPLEFT_X_MASK (0x1fff << 13) +#define VIDOSDxA_TOPLEFT_X_SHIFT 13 +#define VIDOSDxA_TOPLEFT_X_LIMIT 0x1fff +#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x1fff) << 13) + +#define VIDOSDxA_TOPLEFT_Y_MASK (0x1fff << 0) +#define VIDOSDxA_TOPLEFT_Y_SHIFT 0 +#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x1fff +#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x1fff) << 0) + +#define VIDOSDxB_BOTRIGHT_X_MASK (0x1fff << 13) +#define VIDOSDxB_BOTRIGHT_X_SHIFT 13 +#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x1fff +#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x1fff) << 13) + +#define VIDOSDxB_BOTRIGHT_Y_MASK (0x1fff << 0) +#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0 +#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x1fff +#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x1fff) << 0) + +#define VIDOSDxC_ALPHA0_R_F(_x) (((_x) & 0xFF) << 16) +#define VIDOSDxC_ALPHA0_G_F(_x) (((_x) & 0xFF) << 8) +#define VIDOSDxC_ALPHA0_B_F(_x) (((_x) & 0xFF) << 0) + +#define VIDOSDxD_ALPHA1_R_F(_x) (((_x) & 0xFF) << 16) +#define VIDOSDxD_ALPHA1_G_F(_x) (((_x) & 0xFF) << 8) +#define VIDOSDxD_ALPHA1_B_F(_x) (((_x) & 0xFF) >> 0) + +/* Window MAP (Color map) */ +#define WINxMAP(_win) (0x340 + ((_win) * 4)) + +#define WINxMAP_MAP (1 << 24) +#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) +#define WINxMAP_MAP_COLOUR_SHIFT 0 +#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff +#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) + +/* Window colour-key control registers */ +#define WKEYCON 0x370 + +#define WKEYCON0 0x00 +#define WKEYCON1 0x04 +#define WxKEYCON0_KEYBL_EN (1 << 26) +#define WxKEYCON0_KEYEN_F (1 << 25) +#define WxKEYCON0_DIRCON (1 << 24) +#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) +#define WxKEYCON0_COMPKEY_SHIFT 0 +#define WxKEYCON0_COMPKEY_LIMIT 0xffffff +#define WxKEYCON0_COMPKEY(_x) ((_x) << 0) +#define WxKEYCON1_COLVAL_MASK (0xffffff << 0) +#define WxKEYCON1_COLVAL_SHIFT 0 +#define WxKEYCON1_COLVAL_LIMIT 0xffffff +#define WxKEYCON1_COLVAL(_x) ((_x) << 0) + +/* color key control register for hardware window 1 ~ 4. */ +#define WKEYCON0_BASE(x) ((WKEYCON + WKEYCON0) + ((x - 1) * 8)) +/* color key value register for hardware window 1 ~ 4. */ +#define WKEYCON1_BASE(x) ((WKEYCON + WKEYCON1) + ((x - 1) * 8)) + +/* Window KEY Alpha value */ +#define WxKEYALPHA(_win) (0x3A0 + (((_win) - 1) * 0x4)) + +#define Wx_KEYALPHA_R_F_SHIFT 16 +#define Wx_KEYALPHA_G_F_SHIFT 8 +#define Wx_KEYALPHA_B_F_SHIFT 0 + +/* Blending equation */ +#define BLENDE(_win) (0x03C0 + ((_win) * 4)) +#define BLENDE_COEF_ZERO 0x0 +#define BLENDE_COEF_ONE 0x1 +#define BLENDE_COEF_ALPHA_A 0x2 +#define BLENDE_COEF_ONE_MINUS_ALPHA_A 0x3 +#define BLENDE_COEF_ALPHA_B 0x4 +#define BLENDE_COEF_ONE_MINUS_ALPHA_B 0x5 +#define BLENDE_COEF_ALPHA0 0x6 +#define BLENDE_COEF_A 0xA +#define BLENDE_COEF_ONE_MINUS_A 0xB +#define BLENDE_COEF_B 0xC +#define BLENDE_COEF_ONE_MINUS_B 0xD +#define BLENDE_Q_FUNC(_v) ((_v) << 18) +#define BLENDE_P_FUNC(_v) ((_v) << 12) +#define BLENDE_B_FUNC(_v) ((_v) << 6) +#define BLENDE_A_FUNC(_v) ((_v) << 0) + +/* Blending equation control */ +#define BLENDCON 0x3D8 +#define BLENDCON_NEW_MASK (1 << 0) +#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) +#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) + +/* Interrupt control register */ +#define VIDINTCON0 0x500 + +#define VIDINTCON0_WAKEUP_MASK (0x3f << 26) +#define VIDINTCON0_INTEXTRAEN (1 << 21) + +#define VIDINTCON0_FRAMESEL0_SHIFT 15 +#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) +#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) +#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) +#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) +#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) + +#define VIDINTCON0_INT_FRAME (1 << 11) + +#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 3) +#define VIDINTCON0_FIFOLEVEL_SHIFT 3 +#define VIDINTCON0_FIFOLEVEL_EMPTY (0x0 << 3) +#define VIDINTCON0_FIFOLEVEL_TO25PC (0x1 << 3) +#define VIDINTCON0_FIFOLEVEL_TO50PC (0x2 << 3) +#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 3) + +#define VIDINTCON0_FIFOSEL_MAIN_EN (1 << 1) +#define VIDINTCON0_INT_FIFO (1 << 1) + +#define VIDINTCON0_INT_ENABLE (1 << 0) + +/* Interrupt controls and status register */ +#define VIDINTCON1 0x504 + +#define VIDINTCON1_INT_EXTRA (1 << 3) +#define VIDINTCON1_INT_I80 (1 << 2) +#define VIDINTCON1_INT_FRAME (1 << 1) +#define VIDINTCON1_INT_FIFO (1 << 0) + +/* VIDCON1 */ +#define VIDCON1(_x) (0x0600 + ((_x) * 0x50)) +#define VIDCON1_LINECNT_GET(_v) (((_v) >> 17) & 0x1fff) +#define VIDCON1_VCLK_MASK (0x3 << 9) +#define VIDCON1_VCLK_HOLD (0x0 << 9) +#define VIDCON1_VCLK_RUN (0x1 << 9) +#define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9) +#define VIDCON1_RGB_ORDER_O_MASK (0x7 << 4) +#define VIDCON1_RGB_ORDER_O_RGB (0x0 << 4) +#define VIDCON1_RGB_ORDER_O_GBR (0x1 << 4) +#define VIDCON1_RGB_ORDER_O_BRG (0x2 << 4) +#define VIDCON1_RGB_ORDER_O_BGR (0x4 << 4) +#define VIDCON1_RGB_ORDER_O_RBG (0x5 << 4) +#define VIDCON1_RGB_ORDER_O_GRB (0x6 << 4) + +/* VIDTCON0 */ +#define VIDTCON0 0x610 + +#define VIDTCON0_VBPD_MASK (0xffff << 16) +#define VIDTCON0_VBPD_SHIFT 16 +#define VIDTCON0_VBPD_LIMIT 0xffff +#define VIDTCON0_VBPD(_x) ((_x) << 16) + +#define VIDTCON0_VFPD_MASK (0xffff << 0) +#define VIDTCON0_VFPD_SHIFT 0 +#define VIDTCON0_VFPD_LIMIT 0xffff +#define VIDTCON0_VFPD(_x) ((_x) << 0) + +/* VIDTCON1 */ +#define VIDTCON1 0x614 + +#define VIDTCON1_VSPW_MASK (0xffff << 16) +#define VIDTCON1_VSPW_SHIFT 16 +#define VIDTCON1_VSPW_LIMIT 0xffff +#define VIDTCON1_VSPW(_x) ((_x) << 16) + +/* VIDTCON2 */ +#define VIDTCON2 0x618 + +#define VIDTCON2_HBPD_MASK (0xffff << 16) +#define VIDTCON2_HBPD_SHIFT 16 +#define VIDTCON2_HBPD_LIMIT 0xffff +#define VIDTCON2_HBPD(_x) ((_x) << 16) + +#define VIDTCON2_HFPD_MASK (0xffff << 0) +#define VIDTCON2_HFPD_SHIFT 0 +#define VIDTCON2_HFPD_LIMIT 0xffff +#define VIDTCON2_HFPD(_x) ((_x) << 0) + +/* VIDTCON3 */ +#define VIDTCON3 0x61C + +#define VIDTCON3_HSPW_MASK (0xffff << 16) +#define VIDTCON3_HSPW_SHIFT 16 +#define VIDTCON3_HSPW_LIMIT 0xffff +#define VIDTCON3_HSPW(_x) ((_x) << 16) + +/* VIDTCON4 */ +#define VIDTCON4 0x620 + +#define VIDTCON4_LINEVAL_MASK (0xfff << 16) +#define VIDTCON4_LINEVAL_SHIFT 16 +#define VIDTCON4_LINEVAL_LIMIT 0xfff +#define VIDTCON4_LINEVAL(_x) (((_x) & 0xfff) << 16) + +#define VIDTCON4_HOZVAL_MASK (0xfff << 0) +#define VIDTCON4_HOZVAL_SHIFT 0 +#define VIDTCON4_HOZVAL_LIMIT 0xfff +#define VIDTCON4_HOZVAL(_x) (((_x) & 0xfff) << 0) + +/* LINECNT OP THRSHOLD*/ +#define LINECNT_OP_THRESHOLD 0x630 + +/* CRCCTRL */ +#define CRCCTRL 0x6C8 +#define CRCCTRL_CRCCLKEN (0x1 << 2) +#define CRCCTRL_CRCSTART_F (0x1 << 1) +#define CRCCTRL_CRCEN (0x1 << 0) + +/* DECON_CMU */ +#define DECON_CMU 0x704 + +#define DECON_CMU_ALL_CLKGATE_ENABLE 0x3 +#define DECON_CMU_SE_CLKGATE_ENABLE (0x1 << 2) +#define DECON_CMU_SFR_CLKGATE_ENABLE (0x1 << 1) +#define DECON_CMU_MEM_CLKGATE_ENABLE (0x1 << 0) + +/* DECON_UPDATE */ +#define DECON_UPDATE 0x710 + +#define DECON_UPDATE_SLAVE_SYNC (1 << 4) +#define DECON_UPDATE_STANDALONE_F (1 << 0) |