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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_perf.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.h4
-rw-r--r--drivers/gpu/drm/nouveau/nva3_pm.c25
3 files changed, 28 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index 69a528d106e..ea6acf1c4a7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -83,7 +83,7 @@ nouveau_perf_entry(struct drm_device *dev, int idx,
return NULL;
}
-static u8 *
+u8 *
nouveau_perf_rammap(struct drm_device *dev, u32 freq,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h
index 3f82dfea61d..07cac72c72b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h
@@ -61,8 +61,10 @@ int nouveau_voltage_gpio_set(struct drm_device *, int voltage);
/* nouveau_perf.c */
void nouveau_perf_init(struct drm_device *);
void nouveau_perf_fini(struct drm_device *);
-u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
+u8 *nouveau_perf_rammap(struct drm_device *, u32 freq, u8 *ver,
+ u8 *hdr, u8 *cnt, u8 *len);
u8 *nouveau_perf_ramcfg(struct drm_device *, u32 freq, u8 *ver, u8 *len);
+u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
/* nouveau_mem.c */
void nouveau_mem_timing_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index 3d397845dca..86d0de08478 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -354,8 +354,11 @@ mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
static void
mclk_clock_set(struct nouveau_mem_exec_func *exec)
{
- struct nva3_pm_state *info = exec->priv;
struct drm_device *dev = exec->dev;
+ struct nva3_pm_state *info = exec->priv;
+ struct nouveau_pm_level *perflvl = info->perflvl;
+ u32 freq = perflvl->memory;
+ u8 *rammap, *ramcfg, ver, hdr, cnt, len;
nv_wr32(dev, 0x004018, 0x00001000);
@@ -365,6 +368,26 @@ mclk_clock_set(struct nouveau_mem_exec_func *exec)
nv_wr32(dev, 0x004018, 0x1000d000);
else
nv_wr32(dev, 0x004018, 0x10005000);
+
+ rammap = nouveau_perf_rammap(dev, freq, &ver, &hdr, &cnt, &len);
+ if (rammap && ver == 0x10 && hdr >= 5) {
+ ramcfg = nouveau_perf_ramcfg(dev, freq, &ver, &len);
+ if (ramcfg && (rammap[4] & 0x08)) {
+ u32 unk5a0 = (ROM16(ramcfg[5]) << 8) | ramcfg[5];
+ u32 unk5a4 = ROM16(ramcfg[7]);
+ u32 unk804 = (ramcfg[9] & 0xf0) << 16 |
+ (ramcfg[3] & 0x0f) << 16 |
+ (ramcfg[9] & 0x0f) |
+ 0x80000000;
+ nv_wr32(dev, 0x1005a0, unk5a0);
+ nv_wr32(dev, 0x1005a4, unk5a4);
+ nv_wr32(dev, 0x10f804, unk804);
+ nv_mask(dev, 0x10053c, 0x00001000, 0x00000000);
+ } else {
+ nv_mask(dev, 0x10053c, 0x00001000, 0x00001000);
+ nv_mask(dev, 0x10f804, 0x80000000, 0x00000000);
+ }
+ }
}
static void