diff options
| -rw-r--r-- | arch/arm/mach-u300/include/mach/hardware.h | 5 | ||||
| -rw-r--r-- | arch/arm/mach-u300/include/mach/io.h | 20 | ||||
| -rw-r--r-- | arch/arm/mach-u300/include/mach/irqs.h | 114 | ||||
| -rw-r--r-- | arch/arm/mach-u300/include/mach/syscon.h | 644 | ||||
| -rw-r--r-- | arch/arm/mach-u300/include/mach/u300-regs.h | 187 |
5 files changed, 970 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h new file mode 100644 index 00000000000..b99d4ce0ac2 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/hardware.h @@ -0,0 +1,5 @@ +/* + * arch/arm/mach-u300/include/mach/hardware.h + */ +#include <asm/sizes.h> +#include <mach/u300-regs.h> diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h new file mode 100644 index 00000000000..5d6b4c13b3a --- /dev/null +++ b/arch/arm/mach-u300/include/mach/io.h @@ -0,0 +1,20 @@ +/* + * + * arch/arm/mach-u300/include/mach/io.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Dummy IO map for being able to use writew()/readw(), + * writel()/readw() and similar accessor functions. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ +#ifndef __MACH_IO_H +#define __MACH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h new file mode 100644 index 00000000000..a6867b12773 --- /dev/null +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -0,0 +1,114 @@ +/* + * + * arch/arm/mach-u300/include/mach/irqs.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * IRQ channel definitions for the U300 platforms. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define IRQ_U300_INTCON0_START 0 +#define IRQ_U300_INTCON1_START 32 +/* These are on INTCON0 - 30 lines */ +#define IRQ_U300_IRQ0_EXT 0 +#define IRQ_U300_IRQ1_EXT 1 +#define IRQ_U300_DMA 2 +#define IRQ_U300_VIDEO_ENC_0 3 +#define IRQ_U300_VIDEO_ENC_1 4 +#define IRQ_U300_AAIF_RX 5 +#define IRQ_U300_AAIF_TX 6 +#define IRQ_U300_AAIF_VGPIO 7 +#define IRQ_U300_AAIF_WAKEUP 8 +#define IRQ_U300_PCM_I2S0_FRAME 9 +#define IRQ_U300_PCM_I2S0_FIFO 10 +#define IRQ_U300_PCM_I2S1_FRAME 11 +#define IRQ_U300_PCM_I2S1_FIFO 12 +#define IRQ_U300_XGAM_GAMCON 13 +#define IRQ_U300_XGAM_CDI 14 +#define IRQ_U300_XGAM_CDICON 15 +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) +/* MMIACC not used on the DB3210 or DB3350 chips */ +#define IRQ_U300_XGAM_MMIACC 16 +#endif +#define IRQ_U300_XGAM_PDI 17 +#define IRQ_U300_XGAM_PDICON 18 +#define IRQ_U300_XGAM_GAMEACC 19 +#define IRQ_U300_XGAM_MCIDCT 20 +#define IRQ_U300_APEX 21 +#define IRQ_U300_UART0 22 +#define IRQ_U300_SPI 23 +#define IRQ_U300_TIMER_APP_OS 24 +#define IRQ_U300_TIMER_APP_DD 25 +#define IRQ_U300_TIMER_APP_GP1 26 +#define IRQ_U300_TIMER_APP_GP2 27 +#define IRQ_U300_TIMER_OS 28 +#define IRQ_U300_TIMER_MS 29 +#define IRQ_U300_KEYPAD_KEYBF 30 +#define IRQ_U300_KEYPAD_KEYBR 31 +/* These are on INTCON1 - 32 lines */ +#define IRQ_U300_GPIO_PORT0 32 +#define IRQ_U300_GPIO_PORT1 33 +#define IRQ_U300_GPIO_PORT2 34 + +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ + defined(CONFIG_MACH_U300_BS335) +/* These are for DB3150, DB3200 and DB3350 */ +#define IRQ_U300_WDOG 35 +#define IRQ_U300_EVHIST 36 +#define IRQ_U300_MSPRO 37 +#define IRQ_U300_MMCSD_MCIINTR0 38 +#define IRQ_U300_MMCSD_MCIINTR1 39 +#define IRQ_U300_I2C0 40 +#define IRQ_U300_I2C1 41 +#define IRQ_U300_RTC 42 +#define IRQ_U300_NFIF 43 +#define IRQ_U300_NFIF2 44 +#endif + +/* DB3150 and DB3200 have only 45 IRQs */ +#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) +#define U300_NR_IRQS 45 +#endif + +/* The DB3350-specific interrupt lines */ +#ifdef CONFIG_MACH_U300_BS335 +#define IRQ_U300_ISP_F0 45 +#define IRQ_U300_ISP_F1 46 +#define IRQ_U300_ISP_F2 47 +#define IRQ_U300_ISP_F3 48 +#define IRQ_U300_ISP_F4 49 +#define IRQ_U300_GPIO_PORT3 50 +#define IRQ_U300_SYSCON_PLL_LOCK 51 +#define IRQ_U300_UART1 52 +#define IRQ_U300_GPIO_PORT4 53 +#define IRQ_U300_GPIO_PORT5 54 +#define IRQ_U300_GPIO_PORT6 55 +#define U300_NR_IRQS 56 +#endif + +/* The DB3210-specific interrupt lines */ +#ifdef CONFIG_MACH_U300_BS365 +#define IRQ_U300_GPIO_PORT3 35 +#define IRQ_U300_GPIO_PORT4 36 +#define IRQ_U300_WDOG 37 +#define IRQ_U300_EVHIST 38 +#define IRQ_U300_MSPRO 39 +#define IRQ_U300_MMCSD_MCIINTR0 40 +#define IRQ_U300_MMCSD_MCIINTR1 41 +#define IRQ_U300_I2C0 42 +#define IRQ_U300_I2C1 43 +#define IRQ_U300_RTC 44 +#define IRQ_U300_NFIF 45 +#define IRQ_U300_NFIF2 46 +#define IRQ_U300_SYSCON_PLL_LOCK 47 +#define U300_NR_IRQS 48 +#endif + +#define NR_IRQS U300_NR_IRQS + +#endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h new file mode 100644 index 00000000000..1c90d1b1ccb --- /dev/null +++ b/arch/arm/mach-u300/include/mach/syscon.h @@ -0,0 +1,644 @@ +/* + * + * arch/arm/mach-u300/include/mach/syscon.h + * + * + * Copyright (C) 2008 ST-Ericsson AB + * + * Author: Rickard Andersson <rickard.andersson@stericsson.com> + */ + +#ifndef __MACH_SYSCON_H +#define __MACH_SYSCON_H + +/* + * All register defines for SYSCON registers that concerns individual + * block clocks and reset lines are registered here. This is because + * we don't want any other file to try to fool around with this stuff. + */ + +/* APP side SYSCON registers */ +/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */ +/* CLK Control Register 16bit (R/W) */ +#define U300_SYSCON_CCR (0x0000) +#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) +#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) +#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) +/* CLK Status Register 16bit (R/W) */ +#define U300_SYSCON_CSR (0x0004) +#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) +#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) +/* Reset lines for SLOW devices 16bit (R/W) */ +#define U300_SYSCON_RSR (0x0014) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) +#endif +#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) +#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) +#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) +#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) +#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) +#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) +#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) +#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) +#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) +/* Reset lines for FAST devices 16bit (R/W) */ +#define U300_SYSCON_RFR (0x0018) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) +#endif +#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) +#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) +#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) +#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) +#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) +#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) +#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) +/* Reset lines for the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_RRR (0x001c) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) +#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) +#endif +#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) +#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) +#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) +#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) +#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) +#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) +#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) +#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) +#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) +#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) +#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) +/* Clock enable for SLOW peripherals 16bit (R/W) */ +#define U300_SYSCON_CESR (0x0020) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) +#endif +#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) +#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) +#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) +#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) +#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) +#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) +#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) +#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) +/* Clock enable for FAST peripherals 16bit (R/W) */ +#define U300_SYSCON_CEFR (0x0024) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) +#endif +#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) +#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) +#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) +#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) +#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) +#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) +#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) +#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) +#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) +/* Clock enable for the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_CERR (0x0028) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) +#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) +#endif +#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) +#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) +#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) +#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) +#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) +#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) +#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) +#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) +#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) +#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) +#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) +#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) +/* Single block clock enable 16bit (-/W) */ +#define U300_SYSCON_SBCER (0x002c) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) +#endif +#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) +#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) +#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) +#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) +#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) +#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) +#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) +#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) +#endif +#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) +#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) +#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) +#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) +#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) +#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) +#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) +#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) +#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) +#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) +#endif +#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) +#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) +#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) +#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) +#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) +#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) +#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) +#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) +#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) +#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) +#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) +#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) +/* Single block clock disable 16bit (-/W) */ +#define U300_SYSCON_SBCDR (0x0030) +/* Same values as above for SBCER */ +/* Clock force SLOW peripherals 16bit (R/W) */ +#define U300_SYSCON_CFSR (0x003c) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) +#endif +#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) +#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) +#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) +#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) +#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) +#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) +#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) +#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) +/* Clock force FAST peripherals 16bit (R/W) */ +#define U300_SYSCON_CFFR (0x40) +/* Values not defined. Define if you want to use them. */ +/* Clock force the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_CFRR (0x44) +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) +#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) +#endif +#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) +#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) +#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) +#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) +#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) +#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) +#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) +#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) +#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) +#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) +#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) +#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) +/* PLL208 Frequency Control 16bit (R/W) */ +#define U300_SYSCON_PFCR (0x48) +#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) +/* Power Management Control 16bit (R/W) */ +#define U300_SYSCON_PMCR (0x50) +#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) +#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) +/* + * All other clocking registers moved to clock.c! + */ +/* Reset Out 16bit (R/W) */ +#define U300_SYSCON_RCR (0x6c) +#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) +/* EMIF Slew Rate Control 16bit (R/W) */ +#define U300_SYSCON_SRCLR (0x70) +#define U300_SYSCON_SRCLR_MASK (0x03FF) +#define U300_SYSCON_SRCLR_VALUE (0x03FF) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) +/* EMIF Clock Control Register 16bit (R/W) */ +#define U300_SYSCON_ECCR (0x0078) +#define U300_SYSCON_ECCR_MASK (0x000F) +#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) +#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) +#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) +#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) +/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ +#define U300_SYSCON_PMC1LR (0x007C) +#define U300_SYSCON_PMC1LR_MASK (0xFFFF) +#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) +#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) +#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) +#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) +#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) +#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) +#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) +#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) +#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) +#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) +#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) +#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) +#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) +#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) +#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) +#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) +#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) +#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) +/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ +#define U300_SYSCON_PMC1HR (0x007E) +#define U300_SYSCON_PMC1HR_MASK (0xFFFF) +#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) +#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) +#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) +#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) +#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) +#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) +#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) +#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) +#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) +#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) +#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) +#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) +/* Step one for killing the applications system 16bit (-/W) */ +#define U300_SYSCON_KA1R (0x0080) +#define U300_SYSCON_KA1R_MASK (0xFFFF) +#define U300_SYSCON_KA1R_VALUE (0xFFFF) +/* Step two for killing the application system 16bit (-/W) */ +#define U300_SYSCON_KA2R (0x0084) +#define U300_SYSCON_KA2R_MASK (0xFFFF) +#define U300_SYSCON_KA2R_VALUE (0xFFFF) +/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ +#define U300_SYSCON_MMF0R (0x90) +#define U300_SYSCON_MMF0R_MASK (0x00FF) +#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) +#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) +/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ +#define U300_SYSCON_MMF1R (0x94) +#define U300_SYSCON_MMF1R_MASK (0x00FF) +#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) +#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) +/* AAIF control register 16 bit (R/W) */ +#define U300_SYSCON_AAIFCR (0x98) +#define U300_SYSCON_AAIFCR_MASK (0x0003) +#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003) +#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000) +#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001) +#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002) +#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003) +/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ +#define U300_SYSCON_MMCR (0x9C) +#define U300_SYSCON_MMCR_MASK (0x0003) +#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) +#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) + +/* TODO: More SYSCON registers missing */ +#define U300_SYSCON_PMC3R (0x10c) +#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) +#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) +#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) +#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) +/* TODO: Missing other configs, I just added the SPI stuff */ + +/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ +#define U300_SYSCON_S0CCR (0x120) +#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) +#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ +#define U300_SYSCON_S1CCR (0x124) +#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) +#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ +#define U300_SYSCON_S2CCR (0x128) +#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) +#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) +#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */ +#define U300_SYSCON_MCR (0x12c) +#define U300_SYSCON_MCR_FIELD_MASK (0x00FF) +#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0) +#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000) +#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040) +#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0) +#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030) +#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000) +#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010) +#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020) +#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030) +#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008) +#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C) +#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002) +#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001) +/* Clock activity observability register 0 */ +#define U300_SYSCON_C0OAR (0x140) +#define U300_SYSCON_C0OAR_MASK (0xFFFF) +#define U300_SYSCON_C0OAR_VALUE (0xFFFF) +#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) +#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) +#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) +#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) +#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) +#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) +#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) +#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) +#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) +#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) +#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) +#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) +#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) +#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) +#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) +#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) +/* Clock activity observability register 1 */ +#define U300_SYSCON_C1OAR (0x144) +#define U300_SYSCON_C1OAR_MASK (0x3FFE) +#define U300_SYSCON_C1OAR_VALUE (0x3FFE) +#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) +#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) +#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) +#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) +#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) +#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) +#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) +#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) +#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) +#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) +#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) +#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) +#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) +/* Clock activity observability register 2 */ +#define U300_SYSCON_C2OAR (0x148) +#define U300_SYSCON_C2OAR_MASK (0x0FFF) +#define U300_SYSCON_C2OAR_VALUE (0x0FFF) +#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) +#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) +#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) +#define U300_SYSCON_C2OAR_VC_CLK (0x0100) +#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) +#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) +#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) +#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) +#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) +#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) +#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) +#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) + +/* Chip ID register 16bit (R/-) */ +#define U300_SYSCON_CIDR (0x400) +/* Video IRQ clear 16bit (R/W) */ +#define U300_SYSCON_VICR (0x404) +#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002) +#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001) +/* SMCR */ +#define U300_SYSCON_SMCR (0x4d0) +#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) +#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) +#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) +#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) +/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ +#define U300_SYSCON_CSDR (0x4f0) +#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) +/* PRINT_CONTROL Print Control 16bit (R/-) */ +#define U300_SYSCON_PCR (0x4f8) +#define U300_SYSCON_PCR_SERV_IND (0x0001) +/* BOOT_CONTROL 16bit (R/-) */ +#define U300_SYSCON_BCR (0x4fc) +#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) +#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) +#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) +#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) + + +/* CPU clock defines */ +/** + * CPU high frequency in MHz + */ +#define SYSCON_CPU_CLOCK_HIGH 208 +/** + * CPU medium frequency in MHz + */ +#define SYSCON_CPU_CLOCK_MEDIUM 104 +/** + * CPU low frequency in MHz + */ +#define SYSCON_CPU_CLOCK_LOW 13 + +/* EMIF clock defines */ +/** + * EMIF high frequency in MHz + */ +#define SYSCON_EMIF_CLOCK_HIGH 104 +/** + * EMIF medium frequency in MHz + */ +#define SYSCON_EMIF_CLOCK_MEDIUM 104 +/** + * EMIF low frequency in MHz + */ +#define SYSCON_EMIF_CLOCK_LOW 13 + +/* AHB clock defines */ +/** + * AHB high frequency in MHz + */ +#define SYSCON_AHB_CLOCK_HIGH 52 +/** + * AHB medium frequency in MHz + */ +#define SYSCON_AHB_CLOCK_MEDIUM 52 +/** + * AHB low frequency in MHz + */ +#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */ + +enum syscon_busmaster { + SYSCON_BM_DMAC, + SYSCON_BM_XGAM, + SYSCON_BM_VIDEO_ENC +}; + +/* + * Note that this array must match the order of the array "clk_reg" + * in syscon.c + */ +enum syscon_clk { + SYSCON_CLKCONTROL_SLOW_BRIDGE, + SYSCON_CLKCONTROL_UART, + SYSCON_CLKCONTROL_BTR, + SYSCON_CLKCONTROL_EH, + SYSCON_CLKCONTROL_GPIO, + SYSCON_CLKCONTROL_KEYPAD, + SYSCON_CLKCONTROL_APP_TIMER, + SYSCON_CLKCONTROL_ACC_TIMER, + SYSCON_CLKCONTROL_FAST_BRIDGE, + SYSCON_CLKCONTROL_I2C0, + SYSCON_CLKCONTROL_I2C1, + SYSCON_CLKCONTROL_I2S0, + SYSCON_CLKCONTROL_I2S1, + SYSCON_CLKCONTROL_MMC, + SYSCON_CLKCONTROL_SPI, + SYSCON_CLKCONTROL_I2S0_CORE, + SYSCON_CLKCONTROL_I2S1_CORE, + SYSCON_CLKCONTROL_AAIF, + SYSCON_CLKCONTROL_AHB, + SYSCON_CLKCONTROL_APEX, + SYSCON_CLKCONTROL_CPU, + SYSCON_CLKCONTROL_DMA, + SYSCON_CLKCONTROL_EMIF, + SYSCON_CLKCONTROL_NAND_IF, + SYSCON_CLKCONTROL_VIDEO_ENC, + SYSCON_CLKCONTROL_XGAM, + SYSCON_CLKCONTROL_SEMI, + SYSCON_CLKCONTROL_AHB_SUBSYS, + SYSCON_CLKCONTROL_MSPRO +}; + +enum syscon_sysclk_mode { + SYSCON_SYSCLK_DISABLED, + SYSCON_SYSCLK_M_CLK, + SYSCON_SYSCLK_ACC_FSM, + SYSCON_SYSCLK_PLL60_48, + SYSCON_SYSCLK_PLL60_60, + SYSCON_SYSCLK_ACC_PLL208, + SYSCON_SYSCLK_APP_PLL13, + SYSCON_SYSCLK_APP_FSM, + SYSCON_SYSCLK_RTC, + SYSCON_SYSCLK_APP_PLL208 +}; + +enum syscon_sysclk_req { + SYSCON_SYSCLKREQ_DISABLED, + SYSCON_SYSCLKREQ_ACTIVE_LOW +}; + +enum syscon_clk_mode { + SYSCON_CLKMODE_OFF, + SYSCON_CLKMODE_DEFAULT, + SYSCON_CLKMODE_LOW, + SYSCON_CLKMODE_MEDIUM, + SYSCON_CLKMODE_HIGH, + SYSCON_CLKMODE_PERMANENT, + SYSCON_CLKMODE_ON, +}; + +enum syscon_call_mode { + SYSCON_CLKCALL_NOWAIT, + SYSCON_CLKCALL_WAIT, +}; + +int syscon_dc_on(bool keep_power_on); +int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster, + bool active); +bool syscon_get_busmaster_active_state(void); +int syscon_set_sleep_mask(enum syscon_clk, + bool sleep_ctrl); +int syscon_config_sysclk(u32 sysclk, + enum syscon_sysclk_mode sysclkmode, + bool inverse, + u32 divisor, + enum syscon_sysclk_req sysclkreq); +bool syscon_can_turn_off_semi_clock(void); + +/* This function is restricted to core.c */ +int syscon_request_normal_power(bool req); + +/* This function is restricted to be used by platform_speed.c */ +int syscon_speed_request(enum syscon_call_mode wait_mode, + enum syscon_clk_mode req_clk_mode); +#endif /* __MACH_SYSCON_H */ diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h new file mode 100644 index 00000000000..88333dfb19f --- /dev/null +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -0,0 +1,187 @@ +/* + * + * arch/arm/mach-u300/include/mach/u300-regs.h + * + * + * Copyright (C) 2006-2009 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Basic register address definitions in physical memory and + * some block defintions for core devices like the timer. + * Author: Linus Walleij <linus.walleij@stericsson.com> + */ + +#ifndef __MACH_U300_REGS_H +#define __MACH_U300_REGS_H + +/* + * These are the large blocks of memory allocated for I/O. + * the defines are used for setting up the I/O memory mapping. + */ + +/* NAND Flash CS0 */ +#define U300_NAND_CS0_PHYS_BASE 0x80000000 +#define U300_NAND_CS0_VIRT_BASE 0xff040000 + +/* NFIF */ +#define U300_NAND_IF_PHYS_BASE 0x9f800000 +#define U300_NAND_IF_VIRT_BASE 0xff030000 + +/* AHB Peripherals */ +#define U300_AHB_PER_PHYS_BASE 0xa0000000 +#define U300_AHB_PER_VIRT_BASE 0xff010000 + +/* FAST Peripherals */ +#define U300_FAST_PER_PHYS_BASE 0xc0000000 +#define U300_FAST_PER_VIRT_BASE 0xff020000 + +/* SLOW Peripherals */ +#define U300_SLOW_PER_PHYS_BASE 0xc0010000 +#define U300_SLOW_PER_VIRT_BASE 0xff000000 + +/* Boot ROM */ +#define U300_BOOTROM_PHYS_BASE 0xffff0000 +#define U300_BOOTROM_VIRT_BASE 0xffff0000 + +/* SEMI config base */ +#ifdef CONFIG_MACH_U300_BS335 +#define U300_SEMI_CONFIG_BASE 0x2FFE0000 +#else +#define U300_SEMI_CONFIG_BASE 0x30000000 +#endif + +/* + * All the following peripherals are specified at their PHYSICAL address, + * so if you need to access them (in the kernel), you MUST use the macros + * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST() + * etc. + */ + +/* + * AHB peripherals + */ + +/* AHB Peripherals Bridge Controller */ +#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) + +/* Vectored Interrupt Controller 0, servicing 32 interrupts */ +#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) +#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000) + +/* Vectored Interrupt Controller 1, servicing 32 interrupts */ +#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) +#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000) + +/* Memory Stick Pro (MSPRO) controller */ +#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) + +/* EMIF Configuration Area */ +#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) + + +/* + * FAST peripherals + */ + +/* FAST bridge control */ +#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) + +/* MMC/SD controller */ +#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) + +/* PCM I2S0 controller */ +#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) + +/* PCM I2S1 controller */ +#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) + +/* I2C0 controller */ +#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) + +/* I2C1 controller */ +#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) + +/* SPI controller */ +#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) + +#ifdef CONFIG_MACH_U300_BS335 +/* Fast UART1 on U335 only */ +#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) +#endif + +/* + * SLOW peripherals + */ + +/* SLOW bridge control */ +#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) + +/* SYSCON */ +#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) +#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000) + +/* Watchdog */ +#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) + +/* UART0 */ +#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) + +/* APP side special timer */ +#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) +#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000) + +/* Keypad */ +#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) + +/* GPIO */ +#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) + +/* RTC */ +#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) + +/* Bus tracer */ +#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) + +/* Event handler (hardware queue) */ +#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) + +/* Genric Timer */ +#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) + +/* PPM */ +#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) + + +/* + * REST peripherals + */ + +/* ISP (image signal processor) is only available in U335 */ +#ifdef CONFIG_MACH_U300_BS335 +#define U300_ISP_BASE (0xA0008000) +#endif + +/* DMA Controller base */ +#define U300_DMAC_BASE (0xC0020000) + +/* MSL Base */ +#define U300_MSL_BASE (0xc0022000) + +/* APEX Base */ +#define U300_APEX_BASE (0xc0030000) + +/* Video Encoder Base */ +#ifdef CONFIG_MACH_U300_BS335 +#define U300_VIDEOENC_BASE (0xc0080000) +#else +#define U300_VIDEOENC_BASE (0xc0040000) +#endif + +/* XGAM Base */ +#define U300_XGAM_BASE (0xd0000000) + +/* + * Virtual accessor macros for static devices + */ + + +#endif |