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-rw-r--r--Documentation/devicetree/bindings/clock/altr_socfpga.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt17
2 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 0045433eae1..5dfd145d3cc 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
and the bit index.
- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
and width.
+- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
+ the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
+ value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
+ hold/delay times that is needed for the SD/MMC CIU clock. The values of both
+ can be 0-315 degrees, in 45 degree increments.
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 7c52c29d99f..700e7aac371 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -44,6 +44,23 @@ For example:
clocks by index. The names should reflect the clock output signal
names for the device.
+clock-indices: If the identifyng number for the clocks in the node
+ is not linear from zero, then the this mapping allows
+ the mapping of identifiers into the clock-output-names
+ array.
+
+For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
+
+ oscillator {
+ compatible = "myclocktype";
+ #clock-cells = <1>;
+ clock-indices = <1>, <3>;
+ clock-output-names = "clka", "clkb";
+ }
+
+ This ensures we do not have any empty nodes in clock-output-names
+
+
==Clock consumers==
Required properties: