diff options
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 87 |
1 files changed, 8 insertions, 79 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 071dce78959..245058b3b0e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -165,12 +165,9 @@ config TRACE_IRQFLAGS_SUPPORT bool default y -config RWSEM_GENERIC_SPINLOCK - bool - default y - config RWSEM_XCHGADD_ALGORITHM bool + default y config ARCH_HAS_ILOG2_U32 bool @@ -178,13 +175,6 @@ config ARCH_HAS_ILOG2_U32 config ARCH_HAS_ILOG2_U64 bool -config ARCH_HAS_CPUFREQ - bool - help - Internal node to signify that the ARCH has CPUFREQ support - and that the relevant menu configurations are displayed for - it. - config ARCH_HAS_BANDGAP bool @@ -321,7 +311,6 @@ config ARCH_MULTIPLATFORM config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" - select ARCH_HAS_CPUFREQ select ARM_AMBA select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR @@ -480,6 +469,7 @@ config ARCH_IOP13XX select PCI select PLAT_IOP select VMSPLIT_1G + select SPARSE_IRQ help Support for Intel's IOP13XX (XScale) family of processors. @@ -540,7 +530,6 @@ config ARCH_DOVE config ARCH_KIRKWOOD bool "Marvell Kirkwood" - select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CPU_FEROCEON select GENERIC_CLOCKEVENTS @@ -639,7 +628,6 @@ config ARCH_LPC32XX config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU - select ARCH_HAS_CPUFREQ select ARCH_MTD_XIP select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM @@ -709,7 +697,6 @@ config ARCH_RPC config ARCH_SA1100 bool "SA1100-based" - select ARCH_HAS_CPUFREQ select ARCH_MTD_XIP select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE @@ -727,7 +714,6 @@ config ARCH_SA1100 config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" - select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ATAGS select CLKDEV_LOOKUP @@ -748,7 +734,6 @@ config ARCH_S3C24XX config ARCH_S3C64XX bool "Samsung S3C64XX" - select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select ARM_AMBA select ARM_VIC @@ -811,7 +796,6 @@ config ARCH_S5PC100 config ARCH_S5PV210 bool "Samsung S5PV210/S5PC110" - select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE select ATAGS @@ -847,7 +831,6 @@ config ARCH_DAVINCI config ARCH_OMAP1 bool "TI OMAP1" depends on MMU - select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP select ARCH_REQUIRE_GPIOLIB @@ -1011,8 +994,6 @@ source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-sa1100/Kconfig" -source "arch/arm/plat-samsung/Kconfig" - source "arch/arm/mach-socfpga/Kconfig" source "arch/arm/mach-spear/Kconfig" @@ -1030,6 +1011,7 @@ source "arch/arm/mach-s5pc100/Kconfig" source "arch/arm/mach-s5pv210/Kconfig" source "arch/arm/mach-exynos/Kconfig" +source "arch/arm/plat-samsung/Kconfig" source "arch/arm/mach-shmobile/Kconfig" @@ -1088,11 +1070,6 @@ source "arch/arm/firmware/Kconfig" source arch/arm/mm/Kconfig -config ARM_NR_BANKS - int - default 16 if ARCH_EP93XX - default 8 - config IWMMXT bool "Enable iWMMXt support" depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B @@ -1213,19 +1190,6 @@ config ARM_ERRATA_742231 register of the Cortex-A9 which reduces the linefill issuing capabilities of the processor. -config PL310_ERRATA_588369 - bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" - depends on CACHE_L2X0 - help - The PL310 L2 cache controller implements three types of Clean & - Invalidate maintenance operations: by Physical Address - (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). - They are architecturally defined to behave as the execution of a - clean operation followed immediately by an invalidate operation, - both performing to the same memory location. This functionality - is not correctly implemented in PL310 as clean lines are not - invalidated as a result of these operations. - config ARM_ERRATA_643719 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" depends on CPU_V7 && SMP @@ -1248,17 +1212,6 @@ config ARM_ERRATA_720789 tables. The workaround changes the TLB flushing routines to invalidate entries regardless of the ASID. -config PL310_ERRATA_727915 - bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" - depends on CACHE_L2X0 - help - PL310 implements the Clean & Invalidate by Way L2 cache maintenance - operation (offset 0x7FC). This operation runs in background so that - PL310 can handle normal accesses while it is in progress. Under very - rare circumstances, due to this erratum, write data can be lost when - PL310 treats a cacheable write transaction during a Clean & - Invalidate by Way operation. - config ARM_ERRATA_743622 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" depends on CPU_V7 @@ -1284,21 +1237,6 @@ config ARM_ERRATA_751472 operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. -config PL310_ERRATA_753970 - bool "PL310 errata: cache sync operation may be faulty" - depends on CACHE_PL310 - help - This option enables the workaround for the 753970 PL310 (r3p0) erratum. - - Under some condition the effect of cache sync operation on - the store buffer still remains when the operation completes. - This means that the store buffer is always asked to drain and - this prevents it from merging any further writes. The workaround - is to replace the normal offset of cache sync operation (0x730) - by another offset targeting an unmapped PL310 register 0x740. - This has the same effect as the cache sync operation: store buffer - drain and waiting for all buffers empty. - config ARM_ERRATA_754322 bool "ARM errata: possible faulty MMU translations following an ASID switch" depends on CPU_V7 @@ -1347,18 +1285,6 @@ config ARM_ERRATA_764369 relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. -config PL310_ERRATA_769419 - bool "PL310 errata: no automatic Store Buffer drain" - depends on CACHE_L2X0 - help - On revisions of the PL310 prior to r3p2, the Store Buffer does - not automatically drain. This can cause normal, non-cacheable - writes to be retained when the memory system is idle, leading - to suboptimal I/O performance for drivers using coherent DMA. - This option adds a write barrier to the cpu_idle loop so that, - on systems with an outer cache, the store buffer is drained - explicitly. - config ARM_ERRATA_775420 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" depends on CPU_V7 @@ -2167,9 +2093,7 @@ endmenu menu "CPU Power Management" -if ARCH_HAS_CPUFREQ source "drivers/cpufreq/Kconfig" -endif source "drivers/cpuidle/Kconfig" @@ -2278,6 +2202,11 @@ config ARCH_SUSPEND_POSSIBLE config ARM_CPU_SUSPEND def_bool PM_SLEEP +config ARCH_HIBERNATION_POSSIBLE + bool + depends on MMU + default y if ARCH_SUSPEND_POSSIBLE + endmenu source "net/Kconfig" |