diff options
Diffstat (limited to 'arch/arm/lib')
48 files changed, 206 insertions, 50 deletions
diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S index 55e57a1c2e6..1154d924080 100644 --- a/arch/arm/lib/ashldi3.S +++ b/arch/arm/lib/ashldi3.S @@ -47,3 +47,5 @@ ENTRY(__aeabi_llsl) mov al, al, lsl r2 mov pc, lr +ENDPROC(__ashldi3) +ENDPROC(__aeabi_llsl) diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S index 0b31398f89b..9f8b35572f8 100644 --- a/arch/arm/lib/ashrdi3.S +++ b/arch/arm/lib/ashrdi3.S @@ -47,3 +47,5 @@ ENTRY(__aeabi_lasr) mov ah, ah, asr r2 mov pc, lr +ENDPROC(__ashrdi3) +ENDPROC(__aeabi_lasr) diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S index 84dc890d2bf..b0951d0e8b2 100644 --- a/arch/arm/lib/backtrace.S +++ b/arch/arm/lib/backtrace.S @@ -30,6 +30,8 @@ ENTRY(c_backtrace) #if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK) mov pc, lr +ENDPROC(__backtrace) +ENDPROC(c_backtrace) #else stmfd sp!, {r4 - r8, lr} @ Save an extra register so we have a location... movs frame, r0 @ if frame pointer is zero @@ -103,6 +105,8 @@ for_each_frame: tst frame, mask @ Check for address exceptions mov r1, frame bl printk no_frame: ldmfd sp!, {r4 - r8, pc} +ENDPROC(__backtrace) +ENDPROC(c_backtrace) .section __ex_table,"a" .align 3 diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S index 389567c2409..80f3115cbee 100644 --- a/arch/arm/lib/changebit.S +++ b/arch/arm/lib/changebit.S @@ -19,3 +19,5 @@ ENTRY(_change_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_change_bit_le) bitop eor +ENDPROC(_change_bit_be) +ENDPROC(_change_bit_le) diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S index ecb28dcdaf7..4d6bc71231f 100644 --- a/arch/arm/lib/clear_user.S +++ b/arch/arm/lib/clear_user.S @@ -41,9 +41,10 @@ USER( strplt r2, [r0], #4) USER( strnebt r2, [r0], #1) USER( strnebt r2, [r0], #1) tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1 -USER( strnebt r2, [r0], #1) +USER( strnebt r2, [r0]) mov r0, #0 ldmfd sp!, {r1, pc} +ENDPROC(__clear_user) .section .fixup,"ax" .align 0 diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S index 34751653302..1a63e43a1df 100644 --- a/arch/arm/lib/clearbit.S +++ b/arch/arm/lib/clearbit.S @@ -20,3 +20,5 @@ ENTRY(_clear_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_clear_bit_le) bitop bic +ENDPROC(_clear_bit_be) +ENDPROC(_clear_bit_le) diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S index 6b7363ce749..56799a165cc 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S @@ -87,6 +87,8 @@ ENTRY(__copy_from_user) #include "copy_template.S" +ENDPROC(__copy_from_user) + .section .fixup,"ax" .align 0 copy_abort_preamble diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S index 666c99cc074..6ae04db1ca4 100644 --- a/arch/arm/lib/copy_page.S +++ b/arch/arm/lib/copy_page.S @@ -44,3 +44,4 @@ ENTRY(copy_page) PLD( ldmeqia r1!, {r3, r4, ip, lr} ) PLD( beq 2b ) ldmfd sp!, {r4, pc} @ 3 +ENDPROC(copy_page) diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S index cab355c0c1f..139cce64605 100644 --- a/arch/arm/lib/copy_template.S +++ b/arch/arm/lib/copy_template.S @@ -13,14 +13,6 @@ */ /* - * This can be used to enable code to cacheline align the source pointer. - * Experiments on tested architectures (StrongARM and XScale) didn't show - * this a worthwhile thing to do. That might be different in the future. - */ -//#define CALGN(code...) code -#define CALGN(code...) - -/* * Theory of operation * ------------------- * @@ -82,7 +74,7 @@ stmfd sp!, {r5 - r8} blt 5f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( rsb r3, ip, #32 ) CALGN( sbcnes r4, r3, r2 ) @ C is always set here CALGN( bcs 2f ) @@ -168,7 +160,7 @@ subs r2, r2, #28 blt 14f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( rsb ip, ip, #32 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S index 5224d94688d..22f968bbdff 100644 --- a/arch/arm/lib/copy_to_user.S +++ b/arch/arm/lib/copy_to_user.S @@ -90,6 +90,8 @@ ENTRY(__copy_to_user) #include "copy_template.S" +ENDPROC(__copy_to_user) + .section .fixup,"ax" .align 0 copy_abort_preamble diff --git a/arch/arm/lib/csumipv6.S b/arch/arm/lib/csumipv6.S index 9621469beec..3ac6ef01bc4 100644 --- a/arch/arm/lib/csumipv6.S +++ b/arch/arm/lib/csumipv6.S @@ -29,4 +29,5 @@ ENTRY(__csum_ipv6_magic) adcs r0, r0, r2 adcs r0, r0, #0 ldmfd sp!, {pc} +ENDPROC(__csum_ipv6_magic) diff --git a/arch/arm/lib/csumpartial.S b/arch/arm/lib/csumpartial.S index a78dae5a7b2..31d3cb34740 100644 --- a/arch/arm/lib/csumpartial.S +++ b/arch/arm/lib/csumpartial.S @@ -139,3 +139,4 @@ ENTRY(csum_partial) tst len, #0x1c bne 4b b .Lless4 +ENDPROC(csum_partial) diff --git a/arch/arm/lib/csumpartialcopy.S b/arch/arm/lib/csumpartialcopy.S index 21effe0dbf9..d03fc71fc88 100644 --- a/arch/arm/lib/csumpartialcopy.S +++ b/arch/arm/lib/csumpartialcopy.S @@ -18,13 +18,11 @@ */ .macro save_regs - mov ip, sp - stmfd sp!, {r1, r4 - r8, fp, ip, lr, pc} - sub fp, ip, #4 + stmfd sp!, {r1, r4 - r8, lr} .endm .macro load_regs - ldmfd sp, {r1, r4 - r8, fp, sp, pc} + ldmfd sp!, {r1, r4 - r8, pc} .endm .macro load1b, reg1 @@ -50,5 +48,6 @@ .endm #define FN_ENTRY ENTRY(csum_partial_copy_nocheck) +#define FN_EXIT ENDPROC(csum_partial_copy_nocheck) #include "csumpartialcopygeneric.S" diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S index c50e8f5285d..d620a5f22a0 100644 --- a/arch/arm/lib/csumpartialcopygeneric.S +++ b/arch/arm/lib/csumpartialcopygeneric.S @@ -329,3 +329,4 @@ FN_ENTRY adcs sum, sum, r4, push #24 mov r5, r4, get_byte_1 b .Lexit +FN_EXIT diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S index c3b93e22ea2..14677fb4b0c 100644 --- a/arch/arm/lib/csumpartialcopyuser.S +++ b/arch/arm/lib/csumpartialcopyuser.S @@ -18,13 +18,11 @@ .text .macro save_regs - mov ip, sp - stmfd sp!, {r1 - r2, r4 - r8, fp, ip, lr, pc} - sub fp, ip, #4 + stmfd sp!, {r1, r2, r4 - r8, lr} .endm .macro load_regs - ldmfd sp, {r1, r2, r4-r8, fp, sp, pc} + ldmfd sp!, {r1, r2, r4 - r8, pc} .endm .macro load1b, reg1 @@ -82,6 +80,7 @@ */ #define FN_ENTRY ENTRY(csum_partial_copy_from_user) +#define FN_EXIT ENDPROC(csum_partial_copy_from_user) #include "csumpartialcopygeneric.S" diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay.S index 930a7025922..8d6a8762ab8 100644 --- a/arch/arm/lib/delay.S +++ b/arch/arm/lib/delay.S @@ -60,3 +60,6 @@ ENTRY(__delay) #endif bhi __delay mov pc, lr +ENDPROC(__udelay) +ENDPROC(__const_udelay) +ENDPROC(__delay) diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S index 58eef660762..1425e789ba8 100644 --- a/arch/arm/lib/div64.S +++ b/arch/arm/lib/div64.S @@ -198,3 +198,4 @@ ENTRY(__do_div64) mov xh, #0 ldr pc, [sp], #8 +ENDPROC(__do_div64) diff --git a/arch/arm/lib/ecard.S b/arch/arm/lib/ecard.S index c55aaa2a208..8678eb2b7a6 100644 --- a/arch/arm/lib/ecard.S +++ b/arch/arm/lib/ecard.S @@ -12,7 +12,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/hardware.h> +#include <mach/hardware.h> #define CPSR2SPSR(rt) \ mrs rt, cpsr; \ diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S index a5ca0248aa4..8c4defc4f3c 100644 --- a/arch/arm/lib/findbit.S +++ b/arch/arm/lib/findbit.S @@ -33,6 +33,7 @@ ENTRY(_find_first_zero_bit_le) blo 1b 3: mov r0, r1 @ no free bits mov pc, lr +ENDPROC(_find_first_zero_bit_le) /* * Purpose : Find next 'zero' bit @@ -50,6 +51,7 @@ ENTRY(_find_next_zero_bit_le) orr r2, r2, #7 @ if zero, then no bits here add r2, r2, #1 @ align bit pointer b 2b @ loop for next bit +ENDPROC(_find_next_zero_bit_le) /* * Purpose : Find a 'one' bit @@ -67,6 +69,7 @@ ENTRY(_find_first_bit_le) blo 1b 3: mov r0, r1 @ no free bits mov pc, lr +ENDPROC(_find_first_bit_le) /* * Purpose : Find next 'one' bit @@ -83,6 +86,7 @@ ENTRY(_find_next_bit_le) orr r2, r2, #7 @ if zero, then no bits here add r2, r2, #1 @ align bit pointer b 2b @ loop for next bit +ENDPROC(_find_next_bit_le) #ifdef __ARMEB__ @@ -99,6 +103,7 @@ ENTRY(_find_first_zero_bit_be) blo 1b 3: mov r0, r1 @ no free bits mov pc, lr +ENDPROC(_find_first_zero_bit_be) ENTRY(_find_next_zero_bit_be) teq r1, #0 @@ -113,6 +118,7 @@ ENTRY(_find_next_zero_bit_be) orr r2, r2, #7 @ if zero, then no bits here add r2, r2, #1 @ align bit pointer b 2b @ loop for next bit +ENDPROC(_find_next_zero_bit_be) ENTRY(_find_first_bit_be) teq r1, #0 @@ -127,6 +133,7 @@ ENTRY(_find_first_bit_be) blo 1b 3: mov r0, r1 @ no free bits mov pc, lr +ENDPROC(_find_first_bit_be) ENTRY(_find_next_bit_be) teq r1, #0 @@ -140,6 +147,7 @@ ENTRY(_find_next_bit_be) orr r2, r2, #7 @ if zero, then no bits here add r2, r2, #1 @ align bit pointer b 2b @ loop for next bit +ENDPROC(_find_next_bit_be) #endif diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index 1dd8ea4f9a9..6763088b760 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S @@ -20,22 +20,22 @@ * r2, r3 contains the zero-extended value * lr corrupted * - * No other registers must be altered. (see include/asm-arm/uaccess.h + * No other registers must be altered. (see <asm/uaccess.h> * for specific ASM register usage). * * Note that ADDR_LIMIT is either 0 or 0xc0000000. * Note also that it is intended that __get_user_bad is not global. */ +#include <linux/linkage.h> #include <asm/errno.h> - .global __get_user_1 -__get_user_1: +ENTRY(__get_user_1) 1: ldrbt r2, [r0] mov r0, #0 mov pc, lr +ENDPROC(__get_user_1) - .global __get_user_2 -__get_user_2: +ENTRY(__get_user_2) 2: ldrbt r2, [r0], #1 3: ldrbt r3, [r0] #ifndef __ARMEB__ @@ -45,17 +45,19 @@ __get_user_2: #endif mov r0, #0 mov pc, lr +ENDPROC(__get_user_2) - .global __get_user_4 -__get_user_4: +ENTRY(__get_user_4) 4: ldrt r2, [r0] mov r0, #0 mov pc, lr +ENDPROC(__get_user_4) __get_user_bad: mov r2, #0 mov r0, #-EFAULT mov pc, lr +ENDPROC(__get_user_bad) .section __ex_table, "a" .long 1b, __get_user_bad diff --git a/arch/arm/lib/io-readsb.S b/arch/arm/lib/io-readsb.S index fb966ad0276..9f4238987fe 100644 --- a/arch/arm/lib/io-readsb.S +++ b/arch/arm/lib/io-readsb.S @@ -120,3 +120,4 @@ ENTRY(__raw_readsb) strgtb r3, [r1] ldmfd sp!, {r4 - r6, pc} +ENDPROC(__raw_readsb) diff --git a/arch/arm/lib/io-readsl.S b/arch/arm/lib/io-readsl.S index 75a9121cb23..5fb97e7f9f4 100644 --- a/arch/arm/lib/io-readsl.S +++ b/arch/arm/lib/io-readsl.S @@ -76,3 +76,4 @@ ENTRY(__raw_readsl) 8: mov r3, ip, get_byte_0 strb r3, [r1, #0] mov pc, lr +ENDPROC(__raw_readsl) diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S index 4ef90418514..9aaf7c72065 100644 --- a/arch/arm/lib/io-readsw-armv3.S +++ b/arch/arm/lib/io-readsw-armv3.S @@ -9,7 +9,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/hardware.h> +#include <mach/hardware.h> .Linsw_bad_alignment: adr r0, .Linsw_bad_align_msg diff --git a/arch/arm/lib/io-readsw-armv4.S b/arch/arm/lib/io-readsw-armv4.S index 4db1c5f0b21..1f393d42593 100644 --- a/arch/arm/lib/io-readsw-armv4.S +++ b/arch/arm/lib/io-readsw-armv4.S @@ -128,3 +128,4 @@ ENTRY(__raw_readsw) _BE_ONLY_( movne ip, ip, lsr #24 ) strneb ip, [r1] ldmfd sp!, {r4, pc} +ENDPROC(__raw_readsw) diff --git a/arch/arm/lib/io-writesb.S b/arch/arm/lib/io-writesb.S index 7eba2b6cc69..68b92f4acae 100644 --- a/arch/arm/lib/io-writesb.S +++ b/arch/arm/lib/io-writesb.S @@ -91,3 +91,4 @@ ENTRY(__raw_writesb) strgtb r3, [r0] ldmfd sp!, {r4, r5, pc} +ENDPROC(__raw_writesb) diff --git a/arch/arm/lib/io-writesl.S b/arch/arm/lib/io-writesl.S index f8f14dd227c..8d3b7813725 100644 --- a/arch/arm/lib/io-writesl.S +++ b/arch/arm/lib/io-writesl.S @@ -64,3 +64,4 @@ ENTRY(__raw_writesl) str ip, [r0] bne 6b mov pc, lr +ENDPROC(__raw_writesl) diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S index 1607a29f49b..cd34503e424 100644 --- a/arch/arm/lib/io-writesw-armv3.S +++ b/arch/arm/lib/io-writesw-armv3.S @@ -9,7 +9,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/hardware.h> +#include <mach/hardware.h> .Loutsw_bad_alignment: adr r0, .Loutsw_bad_align_msg diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S index c8e85bd653b..d6585612c86 100644 --- a/arch/arm/lib/io-writesw-armv4.S +++ b/arch/arm/lib/io-writesw-armv4.S @@ -94,3 +94,4 @@ ENTRY(__raw_writesw) 3: movne ip, r3, lsr #8 strneh ip, [r0] mov pc, lr +ENDPROC(__raw_writesw) diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S index 4e492f4b3f0..67964bcfc85 100644 --- a/arch/arm/lib/lib1funcs.S +++ b/arch/arm/lib/lib1funcs.S @@ -230,6 +230,8 @@ ENTRY(__aeabi_uidiv) mov r0, r0, lsr r2 mov pc, lr +ENDPROC(__udivsi3) +ENDPROC(__aeabi_uidiv) ENTRY(__umodsi3) @@ -245,6 +247,7 @@ ENTRY(__umodsi3) mov pc, lr +ENDPROC(__umodsi3) ENTRY(__divsi3) ENTRY(__aeabi_idiv) @@ -284,6 +287,8 @@ ENTRY(__aeabi_idiv) rsbmi r0, r0, #0 mov pc, lr +ENDPROC(__divsi3) +ENDPROC(__aeabi_idiv) ENTRY(__modsi3) @@ -305,6 +310,8 @@ ENTRY(__modsi3) rsbmi r0, r0, #0 mov pc, lr +ENDPROC(__modsi3) + #ifdef CONFIG_AEABI ENTRY(__aeabi_uidivmod) @@ -316,6 +323,8 @@ ENTRY(__aeabi_uidivmod) sub r1, r1, r3 mov pc, lr +ENDPROC(__aeabi_uidivmod) + ENTRY(__aeabi_idivmod) stmfd sp!, {r0, r1, ip, lr} @@ -325,6 +334,8 @@ ENTRY(__aeabi_idivmod) sub r1, r1, r3 mov pc, lr +ENDPROC(__aeabi_idivmod) + #endif Ldiv0: diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S index a86dbdd59cc..99ea338bf87 100644 --- a/arch/arm/lib/lshrdi3.S +++ b/arch/arm/lib/lshrdi3.S @@ -47,3 +47,5 @@ ENTRY(__aeabi_llsr) mov ah, ah, lsr r2 mov pc, lr +ENDPROC(__lshrdi3) +ENDPROC(__aeabi_llsr) diff --git a/arch/arm/lib/memchr.S b/arch/arm/lib/memchr.S index e7ab1ea8eba..1da86991d70 100644 --- a/arch/arm/lib/memchr.S +++ b/arch/arm/lib/memchr.S @@ -23,3 +23,4 @@ ENTRY(memchr) sub r0, r0, #1 2: movne r0, #0 mov pc, lr +ENDPROC(memchr) diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index 7e71d6708a8..e0d002641d3 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -57,3 +57,4 @@ ENTRY(memcpy) #include "copy_template.S" +ENDPROC(memcpy) diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index ef7fddc14ac..12549187088 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -13,14 +13,6 @@ #include <linux/linkage.h> #include <asm/assembler.h> -/* - * This can be used to enable code to cacheline align the source pointer. - * Experiments on tested architectures (StrongARM and XScale) didn't show - * this a worthwhile thing to do. That might be different in the future. - */ -//#define CALGN(code...) code -#define CALGN(code...) - .text /* @@ -55,11 +47,12 @@ ENTRY(memmove) stmfd sp!, {r5 - r8} blt 5f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( bcs 2f ) CALGN( adr r4, 6f ) CALGN( subs r2, r2, ip ) @ C is set here + CALGN( rsb ip, ip, #32 ) CALGN( add pc, r4, ip ) PLD( pld [r1, #-4] ) @@ -138,8 +131,7 @@ ENTRY(memmove) subs r2, r2, #28 blt 14f - CALGN( ands ip, r1, #31 ) - CALGN( rsb ip, ip, #32 ) + CALGN( ands ip, r0, #31 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) @@ -204,3 +196,4 @@ ENTRY(memmove) 18: backward_copy_shift push=24 pull=8 +ENDPROC(memmove) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 95b110b07a8..761eefa7624 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -39,6 +39,9 @@ ENTRY(memset) mov r3, r1 cmp r2, #16 blt 4f + +#if ! CALGN(1)+0 + /* * We need an extra register for this loop - save the return address and * use the LR @@ -64,6 +67,49 @@ ENTRY(memset) stmneia r0!, {r1, r3, ip, lr} ldr lr, [sp], #4 +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + mov ip, r1 + mov lr, r1 + + cmp r2, #96 + tstgt r0, #31 + ble 3f + + and ip, r0, #31 + rsb ip, ip, #32 + sub r2, r2, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + tst ip, #(1 << 30) + mov ip, r1 + strne r1, [r0], #4 + +3: subs r2, r2, #64 + stmgeia r0!, {r1, r3-r7, ip, lr} + stmgeia r0!, {r1, r3-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r2, #32 + stmneia r0!, {r1, r3-r7, ip, lr} + tst r2, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + 4: tst r2, #8 stmneia r0!, {r1, r3} tst r2, #4 @@ -78,3 +124,4 @@ ENTRY(memset) tst r2, #1 strneb r1, [r0], #1 mov pc, lr +ENDPROC(memset) diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S index abf2508e822..3fbdef5f802 100644 --- a/arch/arm/lib/memzero.S +++ b/arch/arm/lib/memzero.S @@ -39,6 +39,9 @@ ENTRY(__memzero) */ cmp r1, #16 @ 1 we can skip this chunk if we blt 4f @ 1 have < 16 bytes + +#if ! CALGN(1)+0 + /* * We need an extra register for this loop - save the return address and * use the LR @@ -64,6 +67,47 @@ ENTRY(__memzero) stmneia r0!, {r2, r3, ip, lr} @ 4 ldr lr, [sp], #4 @ 1 +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r2 + mov r5, r2 + mov r6, r2 + mov r7, r2 + mov ip, r2 + mov lr, r2 + + cmp r1, #96 + andgts ip, r0, #31 + ble 3f + + rsb ip, ip, #32 + sub r1, r1, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + movs ip, ip, lsl #2 + strcs r2, [r0], #4 + +3: subs r1, r1, #64 + stmgeia r0!, {r2-r7, ip, lr} + stmgeia r0!, {r2-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r1, #32 + stmneia r0!, {r2-r7, ip, lr} + tst r1, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + 4: tst r1, #8 @ 1 8 bytes or more? stmneia r0!, {r2, r3} @ 2 tst r1, #4 @ 1 4 bytes or more? @@ -78,3 +122,4 @@ ENTRY(__memzero) tst r1, #1 @ 1 a byte left over strneb r2, [r0], #1 @ 1 mov pc, lr @ 1 +ENDPROC(__memzero) diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S index d89c6061579..36c91b4957e 100644 --- a/arch/arm/lib/muldi3.S +++ b/arch/arm/lib/muldi3.S @@ -43,3 +43,5 @@ ENTRY(__aeabi_lmul) adc xh, xh, ip, lsr #16 mov pc, lr +ENDPROC(__muldi3) +ENDPROC(__aeabi_lmul) diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index 8620afe54f7..864f3c1c4f1 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S @@ -20,22 +20,22 @@ * Outputs: r0 is the error code * lr corrupted * - * No other registers must be altered. (see include/asm-arm/uaccess.h + * No other registers must be altered. (see <asm/uaccess.h> * for specific ASM register usage). * * Note that ADDR_LIMIT is either 0 or 0xc0000000 * Note also that it is intended that __put_user_bad is not global. */ +#include <linux/linkage.h> #include <asm/errno.h> - .global __put_user_1 -__put_user_1: +ENTRY(__put_user_1) 1: strbt r2, [r0] mov r0, #0 mov pc, lr +ENDPROC(__put_user_1) - .global __put_user_2 -__put_user_2: +ENTRY(__put_user_2) mov ip, r2, lsr #8 #ifndef __ARMEB__ 2: strbt r2, [r0], #1 @@ -46,23 +46,25 @@ __put_user_2: #endif mov r0, #0 mov pc, lr +ENDPROC(__put_user_2) - .global __put_user_4 -__put_user_4: +ENTRY(__put_user_4) 4: strt r2, [r0] mov r0, #0 mov pc, lr +ENDPROC(__put_user_4) - .global __put_user_8 -__put_user_8: +ENTRY(__put_user_8) 5: strt r2, [r0], #4 6: strt r3, [r0] mov r0, #0 mov pc, lr +ENDPROC(__put_user_8) __put_user_bad: mov r0, #-EFAULT mov pc, lr +ENDPROC(__put_user_bad) .section __ex_table, "a" .long 1b, __put_user_bad diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S index 83bc23d5b03..1dd7176c4b2 100644 --- a/arch/arm/lib/setbit.S +++ b/arch/arm/lib/setbit.S @@ -20,3 +20,5 @@ ENTRY(_set_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_set_bit_le) bitop orr +ENDPROC(_set_bit_be) +ENDPROC(_set_bit_le) diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S index ff6ece487ff..a16fb208c84 100644 --- a/arch/arm/lib/sha1.S +++ b/arch/arm/lib/sha1.S @@ -29,7 +29,7 @@ ENTRY(sha_transform) stmfd sp!, {r4 - r8, lr} @ for (i = 0; i < 16; i++) - @ W[i] = be32_to_cpu(in[i]); */ + @ W[i] = be32_to_cpu(in[i]); #ifdef __ARMEB__ mov r4, r0 @@ -185,6 +185,8 @@ ENTRY(sha_transform) ldmfd sp!, {r4 - r8, pc} +ENDPROC(sha_transform) + .L_sha_K: .word 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 @@ -204,3 +206,4 @@ ENTRY(sha_init) stmia r0, {r1, r2, r3, ip, lr} ldr pc, [sp], #4 +ENDPROC(sha_init) diff --git a/arch/arm/lib/strchr.S b/arch/arm/lib/strchr.S index 9f18d6fdee6..d8f2a1c1aea 100644 --- a/arch/arm/lib/strchr.S +++ b/arch/arm/lib/strchr.S @@ -24,3 +24,4 @@ ENTRY(strchr) movne r0, #0 subeq r0, r0, #1 mov pc, lr +ENDPROC(strchr) diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S index 36e3741a377..330373c26dd 100644 --- a/arch/arm/lib/strncpy_from_user.S +++ b/arch/arm/lib/strncpy_from_user.S @@ -31,6 +31,7 @@ USER( ldrplbt r3, [r1], #1) sub r1, r1, #1 @ take NUL character out of count 2: sub r0, r1, ip mov pc, lr +ENDPROC(__strncpy_from_user) .section .fixup,"ax" .align 0 diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S index 18d8fa4f925..90bb9d02083 100644 --- a/arch/arm/lib/strnlen_user.S +++ b/arch/arm/lib/strnlen_user.S @@ -31,6 +31,7 @@ USER( ldrbt r3, [r0], #1) add r0, r0, #1 2: sub r0, r0, r2 mov pc, lr +ENDPROC(__strnlen_user) .section .fixup,"ax" .align 0 diff --git a/arch/arm/lib/strrchr.S b/arch/arm/lib/strrchr.S index 538df220aa4..302f20cd242 100644 --- a/arch/arm/lib/strrchr.S +++ b/arch/arm/lib/strrchr.S @@ -23,3 +23,4 @@ ENTRY(strrchr) bne 1b mov r0, r3 mov pc, lr +ENDPROC(strrchr) diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S index b25dcd2be53..5c98dc567f0 100644 --- a/arch/arm/lib/testchangebit.S +++ b/arch/arm/lib/testchangebit.S @@ -16,3 +16,5 @@ ENTRY(_test_and_change_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_test_and_change_bit_le) testop eor, strb +ENDPROC(_test_and_change_bit_be) +ENDPROC(_test_and_change_bit_le) diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S index 2dcc4b16b68..543d7094d18 100644 --- a/arch/arm/lib/testclearbit.S +++ b/arch/arm/lib/testclearbit.S @@ -16,3 +16,5 @@ ENTRY(_test_and_clear_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_test_and_clear_bit_le) testop bicne, strneb +ENDPROC(_test_and_clear_bit_be) +ENDPROC(_test_and_clear_bit_le) diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S index 9011c969761..0b3f390401c 100644 --- a/arch/arm/lib/testsetbit.S +++ b/arch/arm/lib/testsetbit.S @@ -16,3 +16,5 @@ ENTRY(_test_and_set_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_test_and_set_bit_le) testop orreq, streqb +ENDPROC(_test_and_set_bit_be) +ENDPROC(_test_and_set_bit_le) diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S index b48bd6d5fd8..ffdd27498ce 100644 --- a/arch/arm/lib/uaccess.S +++ b/arch/arm/lib/uaccess.S @@ -277,6 +277,7 @@ USER( strgebt r3, [r0], #1) @ May fault ldrgtb r3, [r1], #0 USER( strgtbt r3, [r0], #1) @ May fault b .Lc2u_finished +ENDPROC(__copy_to_user) .section .fixup,"ax" .align 0 @@ -542,6 +543,7 @@ USER( ldrgebt r3, [r1], #1) @ May fault USER( ldrgtbt r3, [r1], #1) @ May fault strgtb r3, [r0], #1 b .Lcfu_finished +ENDPROC(__copy_from_user) .section .fixup,"ax" .align 0 diff --git a/arch/arm/lib/ucmpdi2.S b/arch/arm/lib/ucmpdi2.S index f76de07ac18..f0df6a91db0 100644 --- a/arch/arm/lib/ucmpdi2.S +++ b/arch/arm/lib/ucmpdi2.S @@ -33,6 +33,8 @@ ENTRY(__ucmpdi2) movhi r0, #2 mov pc, lr +ENDPROC(__ucmpdi2) + #ifdef CONFIG_AEABI ENTRY(__aeabi_ulcmp) @@ -44,5 +46,7 @@ ENTRY(__aeabi_ulcmp) movhi r0, #1 mov pc, lr +ENDPROC(__aeabi_ulcmp) + #endif |