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-rw-r--r--arch/arm/mach-clps7500/include/mach/irq.h2
-rw-r--r--arch/arm/mach-clps7500/include/mach/memory.h8
-rw-r--r--arch/arm/mach-clps7500/include/mach/system.h2
3 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/mach-clps7500/include/mach/irq.h b/arch/arm/mach-clps7500/include/mach/irq.h
index e8da3c58df7..d02fcf28ee0 100644
--- a/arch/arm/mach-clps7500/include/mach/irq.h
+++ b/arch/arm/mach-clps7500/include/mach/irq.h
@@ -10,8 +10,8 @@
* 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code
*/
+#include <linux/io.h>
#include <asm/hardware/iomd.h>
-#include <asm/io.h>
static inline int fixup_irq(unsigned int irq)
{
diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h
index 3326aa99d3e..87b32db470c 100644
--- a/arch/arm/mach-clps7500/include/mach/memory.h
+++ b/arch/arm/mach-clps7500/include/mach/memory.h
@@ -32,4 +32,12 @@
#define FLUSH_BASE_PHYS 0x00000000
#define FLUSH_BASE 0xdf000000
+/*
+ * Sparsemem support. Each section is a maximum of 64MB. The sections
+ * are offset by 128MB and can cover 128MB, so that gives us a maximum
+ * of 29 physmem bits.
+ */
+#define MAX_PHYSMEM_BITS 29
+#define SECTION_SIZE_BITS 26
+
#endif
diff --git a/arch/arm/mach-clps7500/include/mach/system.h b/arch/arm/mach-clps7500/include/mach/system.h
index 624fc2830ae..6d325fbe8b0 100644
--- a/arch/arm/mach-clps7500/include/mach/system.h
+++ b/arch/arm/mach-clps7500/include/mach/system.h
@@ -6,8 +6,8 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
+#include <linux/io.h>
#include <asm/hardware/iomd.h>
-#include <asm/io.h>
static inline void arch_idle(void)
{