diff options
Diffstat (limited to 'arch/arm/mach-davinci')
45 files changed, 7962 insertions, 418 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index be747f5c6cd..40866c643f1 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -6,6 +6,9 @@ config AINTC config CP_INTC bool +config ARCH_DAVINCI_DMx + bool + menu "TI DaVinci Implementations" comment "DaVinci Core Type" @@ -13,20 +16,41 @@ comment "DaVinci Core Type" config ARCH_DAVINCI_DM644x bool "DaVinci 644x based system" select AINTC + select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM355 bool "DaVinci 355 based system" select AINTC + select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM646x bool "DaVinci 646x based system" select AINTC + select ARCH_DAVINCI_DMx + +config ARCH_DAVINCI_DA830 + bool "DA830/OMAP-L137 based system" + select CP_INTC + select ARCH_DAVINCI_DA8XX + +config ARCH_DAVINCI_DA850 + bool "DA850/OMAP-L138 based system" + select CP_INTC + select ARCH_DAVINCI_DA8XX + +config ARCH_DAVINCI_DA8XX + bool + +config ARCH_DAVINCI_DM365 + bool "DaVinci 365 based system" + select AINTC + select ARCH_DAVINCI_DMx comment "DaVinci Board Type" config MACH_DAVINCI_EVM bool "TI DM644x EVM" - default y + default ARCH_DAVINCI_DM644x depends on ARCH_DAVINCI_DM644x help Configure this option to specify the whether the board used @@ -41,6 +65,7 @@ config MACH_SFFSDR config MACH_DAVINCI_DM355_EVM bool "TI DM355 EVM" + default ARCH_DAVINCI_DM355 depends on ARCH_DAVINCI_DM355 help Configure this option to specify the whether the board used @@ -55,11 +80,33 @@ config MACH_DM355_LEOPARD config MACH_DAVINCI_DM6467_EVM bool "TI DM6467 EVM" + default ARCH_DAVINCI_DM646x depends on ARCH_DAVINCI_DM646x help Configure this option to specify the whether the board used for development is a DM6467 EVM +config MACH_DAVINCI_DM365_EVM + bool "TI DM365 EVM" + default ARCH_DAVINCI_DM365 + depends on ARCH_DAVINCI_DM365 + help + Configure this option to specify whether the board used + for development is a DM365 EVM + +config MACH_DAVINCI_DA830_EVM + bool "TI DA830/OMAP-L137 Reference Platform" + default ARCH_DAVINCI_DA830 + depends on ARCH_DAVINCI_DA830 + help + Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + +config MACH_DAVINCI_DA850_EVM + bool "TI DA850/OMAP-L138 Reference Platform" + default ARCH_DAVINCI_DA850 + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. config DAVINCI_MUX bool "DAVINCI multiplexing support" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 059ab78084b..2e11e847313 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,14 +5,17 @@ # Common objects obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o devices.o dma.o usb.o common.o sram.o + gpio.o dma.o usb.o common.o sram.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific -obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o -obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o -obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o +obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o @@ -23,3 +26,6 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o +obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o +obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o +obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index e1dd366f836..db97ef2c647 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot @@ -1,3 +1,13 @@ +ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) +ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) +$(error Cannot enable DaVinci and DA8XX platforms concurrently) +else + zreladdr-y := 0xc0008000 +params_phys-y := 0xc0000100 +initrd_phys-y := 0xc0800000 +endif +else zreladdr-y := 0x80008000 params_phys-y := 0x80000100 initrd_phys-y := 0x80800000 +endif diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c new file mode 100644 index 00000000000..bfbb63936f3 --- /dev/null +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -0,0 +1,157 @@ +/* + * TI DA830/OMAP L137 EVM board + * + * Author: Mark A. Greer <mgreer@mvista.com> + * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/cp_intc.h> +#include <mach/da8xx.h> +#include <mach/asp.h> + +#define DA830_EVM_PHY_MASK 0x0 +#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +static struct at24_platform_data da830_evm_i2c_eeprom_info = { + .byte_len = SZ_256K / 8, + .page_size = 64, + .flags = AT24_FLAG_ADDR16, + .setup = davinci_get_mac_addr, + .context = (void *)0x7f00, +}; + +static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { + { + I2C_BOARD_INFO("24c256", 0x50), + .platform_data = &da830_evm_i2c_eeprom_info, + }, + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + } +}; + +static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +static struct davinci_uart_config da830_evm_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static u8 da830_iis_serializer_direction[] = { + RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data da830_evm_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = da830_iis_serializer_direction, + .eventq_no = EVENTQ_0, + .version = MCASP_VERSION_2, + .txnumevt = 1, + .rxnumevt = 1, +}; + +static __init void da830_evm_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + int ret; + + ret = da8xx_register_edma(); + if (ret) + pr_warning("da830_evm_init: edma registration failed: %d\n", + ret); + + ret = da8xx_pinmux_setup(da830_i2c0_pins); + if (ret) + pr_warning("da830_evm_init: i2c0 mux setup failed: %d\n", + ret); + + ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); + if (ret) + pr_warning("da830_evm_init: i2c0 registration failed: %d\n", + ret); + + soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->rmii_en = 1; + + ret = da8xx_pinmux_setup(da830_cpgmac_pins); + if (ret) + pr_warning("da830_evm_init: cpgmac mux setup failed: %d\n", + ret); + + ret = da8xx_register_emac(); + if (ret) + pr_warning("da830_evm_init: emac registration failed: %d\n", + ret); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("da830_evm_init: watchdog registration failed: %d\n", + ret); + + davinci_serial_init(&da830_evm_uart_config); + i2c_register_board_info(1, da830_evm_i2c_devices, + ARRAY_SIZE(da830_evm_i2c_devices)); + + ret = da8xx_pinmux_setup(da830_mcasp1_pins); + if (ret) + pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", + ret); + + da8xx_init_mcasp(1, &da830_evm_snd_data); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init da830_evm_console_init(void) +{ + return add_preferred_console("ttyS", 2, "115200"); +} +console_initcall(da830_evm_console_init); +#endif + +static __init void da830_evm_irq_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ, + soc_info->intc_irq_prios); +} + +static void __init da830_evm_map_io(void) +{ + da830_init(); +} + +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP L137 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = da830_evm_map_io, + .init_irq = da830_evm_irq_init, + .timer = &davinci_timer, + .init_machine = da830_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c new file mode 100644 index 00000000000..c759d72494e --- /dev/null +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -0,0 +1,415 @@ +/* + * TI DA850/OMAP-L138 EVM board + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/board-da830-evm.c + * Original Copyrights follow: + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/cp_intc.h> +#include <mach/da8xx.h> +#include <mach/nand.h> + +#define DA850_EVM_PHY_MASK 0x1 +#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ + +#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) +#define DA850_LCD_PWR_PIN GPIO_TO_PIN(8, 10) + +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) + +static struct mtd_partition da850_evm_norflash_partition[] = { + { + .name = "NOR filesystem", + .offset = 0, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct physmap_flash_data da850_evm_norflash_data = { + .width = 2, + .parts = da850_evm_norflash_partition, + .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition), +}; + +static struct resource da850_evm_norflash_resource[] = { + { + .start = DA8XX_AEMIF_CS2_BASE, + .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da850_evm_norflash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &da850_evm_norflash_data, + }, + .num_resources = 1, + .resource = da850_evm_norflash_resource, +}; + +/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash + * (128K blocks). It may be used instead of the (default) SPI flash + * to boot, using TI's tools to install the secondary boot loader + * (UBL) and U-Boot. + */ +struct mtd_partition da850_evm_nandflash_partition[] = { + { + .name = "u-boot env", + .offset = 0, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "UBL", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot", + .offset = MTDPART_OFS_APPEND, + .size = 4 * SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = 0x200000, + .size = SZ_2M, + .mask_flags = 0, + }, + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata da850_evm_nandflash_data = { + .parts = da850_evm_nandflash_partition, + .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource da850_evm_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da850_evm_nandflash_device = { + .name = "davinci_nand", + .id = 1, + .dev = { + .platform_data = &da850_evm_nandflash_data, + }, + .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), + .resource = da850_evm_nandflash_resource, +}; + +static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + } +}; + +static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +static struct davinci_uart_config da850_evm_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static struct platform_device *da850_evm_devices[] __initdata = { + &da850_evm_nandflash_device, + &da850_evm_norflash_device, +}; + +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, + RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data da850_evm_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 1, + .rxnumevt = 1, +}; + +static int da850_evm_mmc_get_ro(int index) +{ + return gpio_get_value(DA850_MMCSD_WP_PIN); +} + +static int da850_evm_mmc_get_cd(int index) +{ + return !gpio_get_value(DA850_MMCSD_CD_PIN); +} + +static struct davinci_mmc_config da850_mmc_config = { + .get_ro = da850_evm_mmc_get_ro, + .get_cd = da850_evm_mmc_get_cd, + .wires = 4, + .version = MMC_CTLR_VERSION_2, +}; + +static int da850_lcd_hw_init(void) +{ + int status; + + status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n"); + if (status < 0) + return status; + + status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n"); + if (status < 0) { + gpio_free(DA850_LCD_BL_PIN); + return status; + } + + gpio_direction_output(DA850_LCD_BL_PIN, 0); + gpio_direction_output(DA850_LCD_PWR_PIN, 0); + + /* disable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 0); + + /* disable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 0); + + /* enable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 1); + + /* enable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 1); + + return 0; +} + +#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 +#define DA8XX_AEMIF_ASIZE_16BIT 0x1 + +static void __init da850_evm_init_nor(void) +{ + void __iomem *aemif_addr; + + aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); + + /* Configure data bus width of CS2 to 16 bit */ + writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | + DA8XX_AEMIF_ASIZE_16BIT, + aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); + + iounmap(aemif_addr); +} + +#if defined(CONFIG_MTD_PHYSMAP) || \ + defined(CONFIG_MTD_PHYSMAP_MODULE) +#define HAS_NOR 1 +#else +#define HAS_NOR 0 +#endif + +#if defined(CONFIG_MMC_DAVINCI) || \ + defined(CONFIG_MMC_DAVINCI_MODULE) +#define HAS_MMC 1 +#else +#define HAS_MMC 0 +#endif + +static __init void da850_evm_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + int ret; + + ret = da8xx_pinmux_setup(da850_nand_pins); + if (ret) + pr_warning("da850_evm_init: nand mux setup failed: %d\n", + ret); + + ret = da8xx_pinmux_setup(da850_nor_pins); + if (ret) + pr_warning("da850_evm_init: nor mux setup failed: %d\n", + ret); + + da850_evm_init_nor(); + + platform_add_devices(da850_evm_devices, + ARRAY_SIZE(da850_evm_devices)); + + ret = da8xx_register_edma(); + if (ret) + pr_warning("da850_evm_init: edma registration failed: %d\n", + ret); + + ret = da8xx_pinmux_setup(da850_i2c0_pins); + if (ret) + pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n", + ret); + + ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); + if (ret) + pr_warning("da850_evm_init: i2c0 registration failed: %d\n", + ret); + + soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->rmii_en = 0; + + ret = da8xx_pinmux_setup(da850_cpgmac_pins); + if (ret) + pr_warning("da850_evm_init: cpgmac mux setup failed: %d\n", + ret); + + ret = da8xx_register_emac(); + if (ret) + pr_warning("da850_evm_init: emac registration failed: %d\n", + ret); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("da830_evm_init: watchdog registration failed: %d\n", + ret); + + if (HAS_MMC) { + if (HAS_NOR) + pr_warning("WARNING: both NOR Flash and MMC/SD are " + "enabled, but they share AEMIF pins.\n" + "\tDisable one of them.\n"); + + ret = da8xx_pinmux_setup(da850_mmcsd0_pins); + if (ret) + pr_warning("da850_evm_init: mmcsd0 mux setup failed:" + " %d\n", ret); + + ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); + if (ret) + pr_warning("da850_evm_init: can not open GPIO %d\n", + DA850_MMCSD_CD_PIN); + gpio_direction_input(DA850_MMCSD_CD_PIN); + + ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); + if (ret) + pr_warning("da850_evm_init: can not open GPIO %d\n", + DA850_MMCSD_WP_PIN); + gpio_direction_input(DA850_MMCSD_WP_PIN); + + ret = da8xx_register_mmcsd0(&da850_mmc_config); + if (ret) + pr_warning("da850_evm_init: mmcsd0 registration failed:" + " %d\n", ret); + } + + davinci_serial_init(&da850_evm_uart_config); + + i2c_register_board_info(1, da850_evm_i2c_devices, + ARRAY_SIZE(da850_evm_i2c_devices)); + + /* + * shut down uart 0 and 1; they are not used on the board and + * accessing them causes endless "too much work in irq53" messages + * with arago fs + */ + __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); + __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); + + ret = da8xx_pinmux_setup(da850_mcasp_pins); + if (ret) + pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", + ret); + + da8xx_init_mcasp(0, &da850_evm_snd_data); + + ret = da8xx_pinmux_setup(da850_lcdcntl_pins); + if (ret) + pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", + ret); + + ret = da850_lcd_hw_init(); + if (ret) + pr_warning("da850_evm_init: lcd initialization failed: %d\n", + ret); + + ret = da8xx_register_lcdc(); + if (ret) + pr_warning("da850_evm_init: lcdc registration failed: %d\n", + ret); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init da850_evm_console_init(void) +{ + return add_preferred_console("ttyS", 2, "115200"); +} +console_initcall(da850_evm_console_init); +#endif + +static __init void da850_evm_irq_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ, + soc_info->intc_irq_prios); +} + +static void __init da850_evm_map_io(void) +{ + da850_init(); +} + +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = da850_evm_map_io, + .init_irq = da850_evm_irq_init, + .timer = &davinci_timer, + .init_machine = da850_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index d6ab64ccd49..77e80679882 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -20,6 +20,8 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/clk.h> +#include <linux/videodev2.h> +#include <media/tvp514x.h> #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> @@ -117,6 +119,8 @@ static struct davinci_i2c_platform_data i2c_pdata = { .bus_delay = 0 /* usec */, }; +static struct snd_platform_data dm355_evm_snd_data; + static int dm355evm_mmc_gpios = -EINVAL; static void dm355evm_mmcsd_gpios(unsigned gpio) @@ -134,11 +138,11 @@ static void dm355evm_mmcsd_gpios(unsigned gpio) } static struct i2c_board_info dm355evm_i2c_info[] = { - { I2C_BOARD_INFO("dm355evm_msp", 0x25), + { I2C_BOARD_INFO("dm355evm_msp", 0x25), .platform_data = dm355evm_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ + }, + /* { plus irq }, */ + { I2C_BOARD_INFO("tlv320aic33", 0x1b), }, }; static void __init evm_init_i2c(void) @@ -177,6 +181,72 @@ static struct platform_device dm355evm_dm9000 = { .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), }; +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1 +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) +/* Inputs available at the TVP5146 */ +static struct v4l2_input tvp5146_inputs[] = { + { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + { + .index = 1, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, +}; + +/* + * this is the route info for connecting each input to decoder + * ouput that goes to vpfe. There is a one to one correspondence + * with tvp5146_inputs + */ +static struct vpfe_route tvp5146_routes[] = { + { + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, + { + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, +}; + +static struct vpfe_subdev_info vpfe_sub_devs[] = { + { + .name = "tvp5146", + .grp_id = 0, + .num_inputs = ARRAY_SIZE(tvp5146_inputs), + .inputs = tvp5146_inputs, + .routes = tvp5146_routes, + .can_route = 1, + .ccdc_if_params = { + .if_type = VPFE_BT656, + .hdpol = VPFE_PINPOL_POSITIVE, + .vdpol = VPFE_PINPOL_POSITIVE, + }, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + } +}; + +static struct vpfe_config vpfe_cfg = { + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), + .sub_devs = vpfe_sub_devs, + .card_name = "DM355 EVM", + .ccdc = "DM355 CCDC", +}; + static struct platform_device *davinci_evm_devices[] __initdata = { &dm355evm_dm9000, &davinci_nand_device, @@ -188,6 +258,8 @@ static struct davinci_uart_config uart_config __initdata = { static void __init dm355_evm_map_io(void) { + /* setup input configuration for VPFE input devices */ + dm355_set_vpfe_config(&vpfe_cfg); dm355_init(); } @@ -279,6 +351,9 @@ static __init void dm355_evm_init(void) dm355_init_spi0(BIT(0), dm355_evm_spi_info, ARRAY_SIZE(dm355_evm_spi_info)); + + /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ + dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); } static __init void dm355_evm_irq_init(void) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c new file mode 100644 index 00000000000..a1d5e7dac74 --- /dev/null +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -0,0 +1,492 @@ +/* + * TI DaVinci DM365 EVM board support + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/i2c/at24.h> +#include <linux/leds.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/mux.h> +#include <mach/hardware.h> +#include <mach/dm365.h> +#include <mach/psc.h> +#include <mach/common.h> +#include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/common.h> +#include <mach/mmc.h> +#include <mach/nand.h> + + +static inline int have_imager(void) +{ + /* REVISIT when it's supported, trigger via Kconfig */ + return 0; +} + +static inline int have_tvp7002(void) +{ + /* REVISIT when it's supported, trigger via Kconfig */ + return 0; +} + + +#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 +#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 +#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 + +#define DM365_EVM_PHY_MASK (0x2) +#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ + +/* + * A MAX-II CPLD is used for various board control functions. + */ +#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) + +#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ +#define CPLD_TEST CPLD_OFFSET(0,1) +#define CPLD_LEDS CPLD_OFFSET(0,2) +#define CPLD_MUX CPLD_OFFSET(0,3) +#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ +#define CPLD_POWER CPLD_OFFSET(1,1) +#define CPLD_VIDEO CPLD_OFFSET(1,2) +#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ + +#define CPLD_DILC_OUT CPLD_OFFSET(2,0) +#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ + +#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) +#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) +#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) +#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) +#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) +#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) +#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) +#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) +#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) + +#define CPLD_RESETS CPLD_OFFSET(4,3) + +#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) +#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) +#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) +#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) +#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) +#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) + +static void __iomem *cpld; + + +/* NOTE: this is geared for the standard config, with a socketed + * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you + * swap chips with a different block size, partitioning will + * need to be changed. This NAND chip MT29F16G08FAA is the default + * NAND shipped with the Spectrum Digital DM365 EVM + */ +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition davinci_nand_partitions[] = { + { + /* UBL (a few copies) plus U-Boot */ + .name = "bootloader", + .offset = 0, + .size = 28 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot environment */ + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 2 * NAND_BLOCK_SIZE, + .mask_flags = 0, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "filesystem1", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512M, + .mask_flags = 0, + }, { + .name = "filesystem2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* two blocks with bad block table (and mirror) at the end */ +}; + +static struct davinci_nand_pdata davinci_nand_data = { + .mask_chipsel = BIT(14), + .parts = davinci_nand_partitions, + .nr_parts = ARRAY_SIZE(davinci_nand_partitions), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource davinci_nand_resources[] = { + { + .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, + .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DM365_ASYNC_EMIF_CONTROL_BASE, + .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_nand_device = { + .name = "davinci_nand", + .id = 0, + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + .dev = { + .platform_data = &davinci_nand_data, + }, +}; + +static struct at24_platform_data eeprom_info = { + .byte_len = (256*1024) / 8, + .page_size = 64, + .flags = AT24_FLAG_ADDR16, + .setup = davinci_get_mac_addr, + .context = (void *)0x7f00, +}; + +static struct i2c_board_info i2c_info[] = { + { + I2C_BOARD_INFO("24c256", 0x50), + .platform_data = &eeprom_info, + }, +}; + +static struct davinci_i2c_platform_data i2c_pdata = { + .bus_freq = 400 /* kHz */, + .bus_delay = 0 /* usec */, +}; + +static int cpld_mmc_get_cd(int module) +{ + if (!cpld) + return -ENXIO; + + /* low == card present */ + return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); +} + +static int cpld_mmc_get_ro(int module) +{ + if (!cpld) + return -ENXIO; + + /* high == card's write protect switch active */ + return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); +} + +static struct davinci_mmc_config dm365evm_mmc_config = { + .get_cd = cpld_mmc_get_cd, + .get_ro = cpld_mmc_get_ro, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_2, +}; + +static void dm365evm_emac_configure(void) +{ + /* + * EMAC pins are multiplexed with GPIO and UART + * Further details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 + */ + davinci_cfg_reg(DM365_EMAC_TX_EN); + davinci_cfg_reg(DM365_EMAC_TX_CLK); + davinci_cfg_reg(DM365_EMAC_COL); + davinci_cfg_reg(DM365_EMAC_TXD3); + davinci_cfg_reg(DM365_EMAC_TXD2); + davinci_cfg_reg(DM365_EMAC_TXD1); + davinci_cfg_reg(DM365_EMAC_TXD0); + davinci_cfg_reg(DM365_EMAC_RXD3); + davinci_cfg_reg(DM365_EMAC_RXD2); + davinci_cfg_reg(DM365_EMAC_RXD1); + davinci_cfg_reg(DM365_EMAC_RXD0); + davinci_cfg_reg(DM365_EMAC_RX_CLK); + davinci_cfg_reg(DM365_EMAC_RX_DV); + davinci_cfg_reg(DM365_EMAC_RX_ER); + davinci_cfg_reg(DM365_EMAC_CRS); + davinci_cfg_reg(DM365_EMAC_MDIO); + davinci_cfg_reg(DM365_EMAC_MDCLK); + + /* + * EMAC interrupts are multiplexed with GPIO interrupts + * Details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 + */ + davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); + davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); + davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); + davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); +} + +static void dm365evm_mmc_configure(void) +{ + /* + * MMC/SD pins are multiplexed with GPIO and EMIF + * Further details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 + */ + davinci_cfg_reg(DM365_SD1_CLK); + davinci_cfg_reg(DM365_SD1_CMD); + davinci_cfg_reg(DM365_SD1_DATA3); + davinci_cfg_reg(DM365_SD1_DATA2); + davinci_cfg_reg(DM365_SD1_DATA1); + davinci_cfg_reg(DM365_SD1_DATA0); +} + +static void __init evm_init_i2c(void) +{ + davinci_init_i2c(&i2c_pdata); + i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); +} + +static struct platform_device *dm365_evm_nand_devices[] __initdata = { + &davinci_nand_device, +}; + +static inline int have_leds(void) +{ +#ifdef CONFIG_LEDS_CLASS + return 1; +#else + return 0; +#endif +} + +struct cpld_led { + struct led_classdev cdev; + u8 mask; +}; + +static const struct { + const char *name; + const char *trigger; +} cpld_leds[] = { + { "dm365evm::ds2", }, + { "dm365evm::ds3", }, + { "dm365evm::ds4", }, + { "dm365evm::ds5", }, + { "dm365evm::ds6", "nand-disk", }, + { "dm365evm::ds7", "mmc1", }, + { "dm365evm::ds8", "mmc0", }, + { "dm365evm::ds9", "heartbeat", }, +}; + +static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) +{ + struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); + u8 reg = __raw_readb(cpld + CPLD_LEDS); + + if (b != LED_OFF) + reg &= ~led->mask; + else + reg |= led->mask; + __raw_writeb(reg, cpld + CPLD_LEDS); +} + +static enum led_brightness cpld_led_get(struct led_classdev *cdev) +{ + struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); + u8 reg = __raw_readb(cpld + CPLD_LEDS); + + return (reg & led->mask) ? LED_OFF : LED_FULL; +} + +static int __init cpld_leds_init(void) +{ + int i; + + if (!have_leds() || !cpld) + return 0; + + /* setup LEDs */ + __raw_writeb(0xff, cpld + CPLD_LEDS); + for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { + struct cpld_led *led; + + led = kzalloc(sizeof(*led), GFP_KERNEL); + if (!led) + break; + + led->cdev.name = cpld_leds[i].name; + led->cdev.brightness_set = cpld_led_set; + led->cdev.brightness_get = cpld_led_get; + led->cdev.default_trigger = cpld_leds[i].trigger; + led->mask = BIT(i); + + if (led_classdev_register(NULL, &led->cdev) < 0) { + kfree(led); + break; + } + } + + return 0; +} +/* run after subsys_initcall() for LEDs */ +fs_initcall(cpld_leds_init); + + +static void __init evm_init_cpld(void) +{ + u8 mux, resets; + const char *label; + struct clk *aemif_clk; + + /* Make sure we can configure the CPLD through CS1. Then + * leave it on for later access to MMC and LED registers. + */ + aemif_clk = clk_get(NULL, "aemif"); + if (IS_ERR(aemif_clk)) + return; + clk_enable(aemif_clk); + + if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, + "cpld") == NULL) + goto fail; + cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); + if (!cpld) { + release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, + SECTION_SIZE); +fail: + pr_err("ERROR: can't map CPLD\n"); + clk_disable(aemif_clk); + return; + } + + /* External muxing for some signals */ + mux = 0; + + /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). + * NOTE: SW4 bus width setting must match! + */ + if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { + /* external keypad mux */ + mux |= BIT(7); + + platform_add_devices(dm365_evm_nand_devices, + ARRAY_SIZE(dm365_evm_nand_devices)); + } else { + /* no OneNAND support yet */ + } + + /* Leave external chips in reset when unused. */ + resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); + + /* Static video input config with SN74CBT16214 1-of-3 mux: + * - port b1 == tvp7002 (mux lowbits == 1 or 6) + * - port b2 == imager (mux lowbits == 2 or 7) + * - port b3 == tvp5146 (mux lowbits == 5) + * + * Runtime switching could work too, with limitations. + */ + if (have_imager()) { + label = "HD imager"; + mux |= 1; + + /* externally mux MMC1/ENET/AIC33 to imager */ + mux |= BIT(6) | BIT(5) | BIT(3); + } else { + struct davinci_soc_info *soc_info = &davinci_soc_info; + + /* we can use MMC1 ... */ + dm365evm_mmc_configure(); + davinci_setup_mmc(1, &dm365evm_mmc_config); + + /* ... and ENET ... */ + dm365evm_emac_configure(); + soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; + resets &= ~BIT(3); + + /* ... and AIC33 */ + resets &= ~BIT(1); + + if (have_tvp7002()) { + mux |= 2; + resets &= ~BIT(2); + label = "tvp7002 HD"; + } else { + /* default to tvp5146 */ + mux |= 5; + resets &= ~BIT(0); + label = "tvp5146 SD"; + } + } + __raw_writeb(mux, cpld + CPLD_MUX); + __raw_writeb(resets, cpld + CPLD_RESETS); + pr_info("EVM: %s video input\n", label); + + /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ +} + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), +}; + +static void __init dm365_evm_map_io(void) +{ + dm365_init(); +} + +static __init void dm365_evm_init(void) +{ + evm_init_i2c(); + davinci_serial_init(&uart_config); + + dm365evm_emac_configure(); + dm365evm_mmc_configure(); + + davinci_setup_mmc(0, &dm365evm_mmc_config); + + /* maybe setup mmc1/etc ... _after_ mmc0 */ + evm_init_cpld(); +} + +static __init void dm365_evm_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (0x80000100), + .map_io = dm365_evm_map_io, + .init_irq = dm365_evm_irq_init, + .timer = &davinci_timer, + .init_machine = dm365_evm_init, +MACHINE_END + diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 56c8cd01de9..1213a0087ad 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -28,6 +28,9 @@ #include <linux/io.h> #include <linux/phy.h> #include <linux/clk.h> +#include <linux/videodev2.h> + +#include <media/tvp514x.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -194,6 +197,72 @@ static struct platform_device davinci_fb_device = { .num_resources = 0, }; +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1 +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) +/* Inputs available at the TVP5146 */ +static struct v4l2_input tvp5146_inputs[] = { + { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + { + .index = 1, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, +}; + +/* + * this is the route info for connecting each input to decoder + * ouput that goes to vpfe. There is a one to one correspondence + * with tvp5146_inputs + */ +static struct vpfe_route tvp5146_routes[] = { + { + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, + { + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + }, +}; + +static struct vpfe_subdev_info vpfe_sub_devs[] = { + { + .name = "tvp5146", + .grp_id = 0, + .num_inputs = ARRAY_SIZE(tvp5146_inputs), + .inputs = tvp5146_inputs, + .routes = tvp5146_routes, + .can_route = 1, + .ccdc_if_params = { + .if_type = VPFE_BT656, + .hdpol = VPFE_PINPOL_POSITIVE, + .vdpol = VPFE_PINPOL_POSITIVE, + }, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + }, +}; + +static struct vpfe_config vpfe_cfg = { + .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), + .sub_devs = vpfe_sub_devs, + .card_name = "DM6446 EVM", + .ccdc = "DM6446 CCDC", +}; + static struct platform_device rtc_dev = { .name = "rtc_davinci_evm", .id = -1, @@ -225,6 +294,8 @@ static struct platform_device ide_dev = { }, }; +static struct snd_platform_data dm644x_evm_snd_data; + /*----------------------------------------------------------------------*/ /* @@ -557,10 +628,9 @@ static struct i2c_board_info __initdata i2c_info[] = { I2C_BOARD_INFO("24c256", 0x50), .platform_data = &eeprom_info, }, - /* ALSO: - * - tvl320aic33 audio codec (0x1b) - * - tvp5146 video decoder (0x5d) - */ + { + I2C_BOARD_INFO("tlv320aic33", 0x1b), + }, }; /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), @@ -590,6 +660,8 @@ static struct davinci_uart_config uart_config __initdata = { static void __init davinci_evm_map_io(void) { + /* setup input configuration for VPFE input devices */ + dm644x_set_vpfe_config(&vpfe_cfg); dm644x_init(); } @@ -666,6 +738,7 @@ static __init void davinci_evm_init(void) davinci_setup_mmc(0, &dm6446evm_mmc_config); davinci_serial_init(&uart_config); + dm644x_init_asp(&dm644x_evm_snd_data); soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 8657e72debc..24e0e13b149 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -34,6 +34,8 @@ #include <linux/i2c/pcf857x.h> #include <linux/etherdevice.h> +#include <media/tvp514x.h> + #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -48,13 +50,89 @@ #include <mach/mmc.h> #include <mach/emac.h> +#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ + defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) +#define HAS_ATA 1 +#else +#define HAS_ATA 0 +#endif + +/* CPLD Register 0 bits to control ATA */ +#define DM646X_EVM_ATA_RST BIT(0) +#define DM646X_EVM_ATA_PWD BIT(1) + #define DM646X_EVM_PHY_MASK (0x2) #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ +#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38) +#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c) +#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8)) +#define VCH2CLK_SYSCLK8 (BIT(9)) +#define VCH2CLK_AUXCLK (BIT(9) | BIT(8)) +#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12)) +#define VCH3CLK_SYSCLK8 (BIT(13)) +#define VCH3CLK_AUXCLK (BIT(14) | BIT(13)) + +#define VIDCH2CLK (BIT(10)) +#define VIDCH3CLK (BIT(11)) +#define VIDCH1CLK (BIT(4)) +#define TVP7002_INPUT (BIT(4)) +#define TVP5147_INPUT (~BIT(4)) +#define VPIF_INPUT_ONE_CHANNEL (BIT(5)) +#define VPIF_INPUT_TWO_CHANNEL (~BIT(5)) +#define TVP5147_CH0 "tvp514x-0" +#define TVP5147_CH1 "tvp514x-1" + +static void __iomem *vpif_vidclkctl_reg; +static void __iomem *vpif_vsclkdis_reg; +/* spin lock for updating above registers */ +static spinlock_t vpif_reg_lock; + static struct davinci_uart_config uart_config __initdata = { .enabled_uarts = (1 << 0), }; +/* CPLD Register 0 Client: used for I/O Control */ +static int cpld_reg0_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + if (HAS_ATA) { + u8 data; + struct i2c_msg msg[2] = { + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &data, + }, + { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = &data, + }, + }; + + /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */ + i2c_transfer(client->adapter, msg, 1); + data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD); + i2c_transfer(client->adapter, msg + 1, 1); + } + + return 0; +} + +static const struct i2c_device_id cpld_reg_ids[] = { + { "cpld_reg0", 0, }, + { }, +}; + +static struct i2c_driver dm6467evm_cpld_driver = { + .driver.name = "cpld_reg0", + .id_table = cpld_reg_ids, + .probe = cpld_reg0_probe, +}; + /* LEDS */ static struct gpio_led evm_leds[] = { @@ -206,6 +284,69 @@ static struct at24_platform_data eeprom_info = { .context = (void *)0x7f00, }; +static u8 dm646x_iis_serializer_direction[] = { + TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static u8 dm646x_dit_serializer_direction[] = { + TX_MODE, +}; + +static struct snd_platform_data dm646x_evm_snd_data[] = { + { + .tx_dma_offset = 0x400, + .rx_dma_offset = 0x400, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = dm646x_iis_serializer_direction, + .eventq_no = EVENTQ_0, + }, + { + .tx_dma_offset = 0x400, + .rx_dma_offset = 0, + .op_mode = DAVINCI_MCASP_DIT_MODE, + .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), + .tdm_slots = 32, + .serial_dir = dm646x_dit_serializer_direction, + .eventq_no = EVENTQ_0, + }, +}; + +static struct i2c_client *cpld_client; + +static int cpld_video_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + cpld_client = client; + return 0; +} + +static int __devexit cpld_video_remove(struct i2c_client *client) +{ + cpld_client = NULL; + return 0; +} + +static const struct i2c_device_id cpld_video_id[] = { + { "cpld_video", 0 }, + { } +}; + +static struct i2c_driver cpld_video_driver = { + .driver = { + .name = "cpld_video", + }, + .probe = cpld_video_probe, + .remove = cpld_video_remove, + .id_table = cpld_video_id, +}; + +static void evm_init_cpld(void) +{ + i2c_add_driver(&cpld_video_driver); +} + static struct i2c_board_info __initdata i2c_info[] = { { I2C_BOARD_INFO("24c256", 0x50), @@ -215,6 +356,15 @@ static struct i2c_board_info __initdata i2c_info[] = { I2C_BOARD_INFO("pcf8574a", 0x38), .platform_data = &pcf_data, }, + { + I2C_BOARD_INFO("cpld_reg0", 0x3a), + }, + { + I2C_BOARD_INFO("tlv320aic33", 0x18), + }, + { + I2C_BOARD_INFO("cpld_video", 0x3b), + }, }; static struct davinci_i2c_platform_data i2c_pdata = { @@ -222,10 +372,265 @@ static struct davinci_i2c_platform_data i2c_pdata = { .bus_delay = 0 /* usec */, }; +static int set_vpif_clock(int mux_mode, int hd) +{ + unsigned long flags; + unsigned int value; + int val = 0; + int err = 0; + + if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client) + return -ENXIO; + + /* disable the clock */ + spin_lock_irqsave(&vpif_reg_lock, flags); + value = __raw_readl(vpif_vsclkdis_reg); + value |= (VIDCH3CLK | VIDCH2CLK); + __raw_writel(value, vpif_vsclkdis_reg); + spin_unlock_irqrestore(&vpif_reg_lock, flags); + + val = i2c_smbus_read_byte(cpld_client); + if (val < 0) + return val; + + if (mux_mode == 1) + val &= ~0x40; + else + val |= 0x40; + + err = i2c_smbus_write_byte(cpld_client, val); + if (err) + return err; + + value = __raw_readl(vpif_vidclkctl_reg); + value &= ~(VCH2CLK_MASK); + value &= ~(VCH3CLK_MASK); + + if (hd >= 1) + value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8); + else + value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK); + + __raw_writel(value, vpif_vidclkctl_reg); + + spin_lock_irqsave(&vpif_reg_lock, flags); + value = __raw_readl(vpif_vsclkdis_reg); + /* enable the clock */ + value &= ~(VIDCH3CLK | VIDCH2CLK); + __raw_writel(value, vpif_vsclkdis_reg); + spin_unlock_irqrestore(&vpif_reg_lock, flags); + + return 0; +} + +static struct vpif_subdev_info dm646x_vpif_subdev[] = { + { + .name = "adv7343", + .board_info = { + I2C_BOARD_INFO("adv7343", 0x2a), + }, + }, + { + .name = "ths7303", + .board_info = { + I2C_BOARD_INFO("ths7303", 0x2c), + }, + }, +}; + +static const char *output[] = { + "Composite", + "Component", + "S-Video", +}; + +static struct vpif_display_config dm646x_vpif_display_config = { + .set_clock = set_vpif_clock, + .subdevinfo = dm646x_vpif_subdev, + .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), + .output = output, + .output_count = ARRAY_SIZE(output), + .card_name = "DM646x EVM", +}; + +/** + * setup_vpif_input_path() + * @channel: channel id (0 - CH0, 1 - CH1) + * @sub_dev_name: ptr sub device name + * + * This will set vpif input to capture data from tvp514x or + * tvp7002. + */ +static int setup_vpif_input_path(int channel, const char *sub_dev_name) +{ + int err = 0; + int val; + + /* for channel 1, we don't do anything */ + if (channel != 0) + return 0; + + if (!cpld_client) + return -ENXIO; + + val = i2c_smbus_read_byte(cpld_client); + if (val < 0) + return val; + + if (!strcmp(sub_dev_name, TVP5147_CH0) || + !strcmp(sub_dev_name, TVP5147_CH1)) + val &= TVP5147_INPUT; + else + val |= TVP7002_INPUT; + + err = i2c_smbus_write_byte(cpld_client, val); + if (err) + return err; + return 0; +} + +/** + * setup_vpif_input_channel_mode() + * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel + * + * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147) + */ +static int setup_vpif_input_channel_mode(int mux_mode) +{ + unsigned long flags; + int err = 0; + int val; + u32 value; + + if (!vpif_vsclkdis_reg || !cpld_client) + return -ENXIO; + + val = i2c_smbus_read_byte(cpld_client); + if (val < 0) + return val; + + spin_lock_irqsave(&vpif_reg_lock, flags); + value = __raw_readl(vpif_vsclkdis_reg); + if (mux_mode) { + val &= VPIF_INPUT_TWO_CHANNEL; + value |= VIDCH1CLK; + } else { + val |= VPIF_INPUT_ONE_CHANNEL; + value &= ~VIDCH1CLK; + } + __raw_writel(value, vpif_vsclkdis_reg); + spin_unlock_irqrestore(&vpif_reg_lock, flags); + + err = i2c_smbus_write_byte(cpld_client, val); + if (err) + return err; + + return 0; +} + +static struct tvp514x_platform_data tvp5146_pdata = { + .clk_polarity = 0, + .hs_polarity = 1, + .vs_polarity = 1 +}; + +#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) + +static struct vpif_subdev_info vpif_capture_sdev_info[] = { + { + .name = TVP5147_CH0, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5d), + .platform_data = &tvp5146_pdata, + }, + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .can_route = 1, + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, + { + .name = TVP5147_CH1, + .board_info = { + I2C_BOARD_INFO("tvp5146", 0x5c), + .platform_data = &tvp5146_pdata, + }, + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .can_route = 1, + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, + }, +}; + +static const struct vpif_input dm6467_ch0_inputs[] = { + { + .input = { + .index = 0, + .name = "Composite", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + .subdev_name = TVP5147_CH0, + }, +}; + +static const struct vpif_input dm6467_ch1_inputs[] = { + { + .input = { + .index = 0, + .name = "S-Video", + .type = V4L2_INPUT_TYPE_CAMERA, + .std = TVP514X_STD_ALL, + }, + .subdev_name = TVP5147_CH1, + }, +}; + +static struct vpif_capture_config dm646x_vpif_capture_cfg = { + .setup_input_path = setup_vpif_input_path, + .setup_input_channel_mode = setup_vpif_input_channel_mode, + .subdev_info = vpif_capture_sdev_info, + .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info), + .chan_config[0] = { + .inputs = dm6467_ch0_inputs, + .input_count = ARRAY_SIZE(dm6467_ch0_inputs), + }, + .chan_config[1] = { + .inputs = dm6467_ch1_inputs, + .input_count = ARRAY_SIZE(dm6467_ch1_inputs), + }, +}; + +static void __init evm_init_video(void) +{ + vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4); + vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4); + if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) { + pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n"); + return; + } + spin_lock_init(&vpif_reg_lock); + + dm646x_setup_vpif(&dm646x_vpif_display_config, + &dm646x_vpif_capture_cfg); +} + static void __init evm_init_i2c(void) { davinci_init_i2c(&i2c_pdata); + i2c_add_driver(&dm6467evm_cpld_driver); i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); + evm_init_cpld(); + evm_init_video(); } static void __init davinci_map_io(void) @@ -239,6 +644,11 @@ static __init void evm_init(void) evm_init_i2c(); davinci_serial_init(&uart_config); + dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); + dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + + if (HAS_ATA) + dm646x_init_ide(); soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 39bf321d70a..83d54d50b5e 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -227,7 +227,10 @@ static void __init clk_pll_init(struct clk *clk) if (ctrl & PLLCTL_PLLEN) { bypass = 0; mult = __raw_readl(pll->base + PLLM); - mult = (mult & PLLM_PLLM_MASK) + 1; + if (cpu_is_davinci_dm365()) + mult = 2 * (mult & PLLM_PLLM_MASK); + else + mult = (mult & PLLM_PLLM_MASK) + 1; } else bypass = 1; diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c new file mode 100644 index 00000000000..19b2748357f --- /dev/null +++ b/arch/arm/mach-davinci/da830.c @@ -0,0 +1,1205 @@ +/* + * TI DA830/OMAP L137 chip specific setup + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/clock.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/time.h> +#include <mach/da8xx.h> +#include <mach/asp.h> + +#include "clock.h" +#include "mux.h" + +/* Offsets of the 8 compare registers on the da830 */ +#define DA830_CMP12_0 0x60 +#define DA830_CMP12_1 0x64 +#define DA830_CMP12_2 0x68 +#define DA830_CMP12_3 0x6c +#define DA830_CMP12_4 0x70 +#define DA830_CMP12_5 0x74 +#define DA830_CMP12_6 0x78 +#define DA830_CMP12_7 0x7c + +#define DA830_REF_FREQ 24000000 + +static struct pll_data pll0_data = { + .num = 1, + .phys_base = DA8XX_PLL0_BASE, + .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DA830_REF_FREQ, +}; + +static struct clk pll0_clk = { + .name = "pll0", + .parent = &ref_clk, + .pll_data = &pll0_data, + .flags = CLK_PLL, +}; + +static struct clk pll0_aux_clk = { + .name = "pll0_aux_clk", + .parent = &pll0_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll0_sysclk2 = { + .name = "pll0_sysclk2", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll0_sysclk3 = { + .name = "pll0_sysclk3", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll0_sysclk4 = { + .name = "pll0_sysclk4", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll0_sysclk5 = { + .name = "pll0_sysclk5", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll0_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll0_sysclk7 = { + .name = "pll0_sysclk7", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk i2c0_clk = { + .name = "i2c0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_0_clk = { + .name = "timer0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_1_clk = { + .name = "timer1", + .parent = &pll0_aux_clk, +}; + +static struct clk arm_rom_clk = { + .name = "arm_rom", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk scr0_ss_clk = { + .name = "scr0_ss", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SCR0_SS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk scr1_ss_clk = { + .name = "scr1_ss", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SCR1_SS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk scr2_ss_clk = { + .name = "scr2_ss", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SCR2_SS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk dmax_clk = { + .name = "dmax", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_DMAX, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc_clk = { + .name = "tpcc", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPCC, + .flags = ALWAYS_ENABLED | CLK_PSC, +}; + +static struct clk tptc0_clk = { + .name = "tptc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tptc1_clk = { + .name = "tptc1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk mmcsd_clk = { + .name = "mmcsd", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_MMC_SD, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART1, + .psc_ctlr = 1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART2, + .psc_ctlr = 1, +}; + +static struct clk spi0_clk = { + .name = "spi0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_SPI0, +}; + +static struct clk spi1_clk = { + .name = "spi1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_SPI1, + .psc_ctlr = 1, +}; + +static struct clk ecap0_clk = { + .name = "ecap0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_ECAP, + .psc_ctlr = 1, +}; + +static struct clk ecap1_clk = { + .name = "ecap1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_ECAP, + .psc_ctlr = 1, +}; + +static struct clk ecap2_clk = { + .name = "ecap2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_ECAP, + .psc_ctlr = 1, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_PWM, + .psc_ctlr = 1, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_PWM, + .psc_ctlr = 1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_PWM, + .psc_ctlr = 1, +}; + +static struct clk eqep0_clk = { + .name = "eqep0", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_EQEP, + .psc_ctlr = 1, +}; + +static struct clk eqep1_clk = { + .name = "eqep1", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_EQEP, + .psc_ctlr = 1, +}; + +static struct clk lcdc_clk = { + .name = "lcdc", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_LCDC, + .psc_ctlr = 1, +}; + +static struct clk mcasp0_clk = { + .name = "mcasp0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_McASP0, + .psc_ctlr = 1, +}; + +static struct clk mcasp1_clk = { + .name = "mcasp1", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_McASP1, + .psc_ctlr = 1, +}; + +static struct clk mcasp2_clk = { + .name = "mcasp2", + .parent = &pll0_sysclk2, + .lpsc = DA830_LPSC1_McASP2, + .psc_ctlr = 1, +}; + +static struct clk usb20_clk = { + .name = "usb20", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_USB20, + .psc_ctlr = 1, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll0_sysclk3, + .lpsc = DA8XX_LPSC0_EMIF25, + .flags = ALWAYS_ENABLED, +}; + +static struct clk aintc_clk = { + .name = "aintc", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_AINTC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk secu_mgr_clk = { + .name = "secu_mgr", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_SECU_MGR, + .flags = ALWAYS_ENABLED, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_CPGMAC, + .psc_ctlr = 1, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_GPIO, + .psc_ctlr = 1, +}; + +static struct clk i2c1_clk = { + .name = "i2c1", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_I2C, + .psc_ctlr = 1, +}; + +static struct clk usb11_clk = { + .name = "usb11", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_USB11, + .psc_ctlr = 1, +}; + +static struct clk emif3_clk = { + .name = "emif3", + .parent = &pll0_sysclk5, + .lpsc = DA8XX_LPSC1_EMIF3C, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll0_sysclk6, + .lpsc = DA8XX_LPSC0_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk rmii_clk = { + .name = "rmii", + .parent = &pll0_sysclk7, +}; + +static struct davinci_clk da830_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll0", &pll0_clk), + CLK(NULL, "pll0_aux", &pll0_aux_clk), + CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), + CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), + CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), + CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), + CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), + CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), + CLK("i2c_davinci.1", NULL, &i2c0_clk), + CLK(NULL, "timer0", &timerp64_0_clk), + CLK("watchdog", NULL, &timerp64_1_clk), + CLK(NULL, "arm_rom", &arm_rom_clk), + CLK(NULL, "scr0_ss", &scr0_ss_clk), + CLK(NULL, "scr1_ss", &scr1_ss_clk), + CLK(NULL, "scr2_ss", &scr2_ss_clk), + CLK(NULL, "dmax", &dmax_clk), + CLK(NULL, "tpcc", &tpcc_clk), + CLK(NULL, "tptc0", &tptc0_clk), + CLK(NULL, "tptc1", &tptc1_clk), + CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK("dm_spi.0", NULL, &spi0_clk), + CLK("dm_spi.1", NULL, &spi1_clk), + CLK(NULL, "ecap0", &ecap0_clk), + CLK(NULL, "ecap1", &ecap1_clk), + CLK(NULL, "ecap2", &ecap2_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK("eqep.0", NULL, &eqep0_clk), + CLK("eqep.1", NULL, &eqep1_clk), + CLK("da830_lcdc", NULL, &lcdc_clk), + CLK("davinci-mcasp.0", NULL, &mcasp0_clk), + CLK("davinci-mcasp.1", NULL, &mcasp1_clk), + CLK("davinci-mcasp.2", NULL, &mcasp2_clk), + CLK("musb_hdrc", NULL, &usb20_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "aintc", &aintc_clk), + CLK(NULL, "secu_mgr", &secu_mgr_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK("i2c_davinci.2", NULL, &i2c1_clk), + CLK(NULL, "usb11", &usb11_clk), + CLK(NULL, "emif3", &emif3_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "rmii", &rmii_clk), + CLK(NULL, NULL, NULL), +}; + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da830_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false) + MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false) + MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false) + MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false) + MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false) + MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false) + MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false) + MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false) + MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false) + MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false) + MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false) + MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false) + MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false) + MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false) + MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false) + MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false) + MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false) + MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false) + MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false) + MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false) + MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false) + MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false) + MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false) + MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false) + MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false) + MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false) + MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false) + MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false) + MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false) + MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false) + MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false) + MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false) + MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false) + MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false) + MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false) + MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false) + MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false) + MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false) + MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false) + MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false) + MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false) + MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false) + MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false) + MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false) + MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false) + MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false) + MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false) + MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false) + MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false) + MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false) + MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false) + MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false) + MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false) + MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false) + MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false) + MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false) + MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false) + MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false) + MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false) + MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false) + MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false) + MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false) + MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false) + MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false) + MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false) + MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false) + MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false) + MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false) + MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false) + MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false) + MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false) + MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false) + MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false) + MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false) + MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false) + MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false) + MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false) + MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false) + MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false) + MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false) + MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false) + MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false) + MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false) + MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false) + MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false) + MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false) + MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false) + MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false) + MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false) + MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false) + MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false) + MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false) + MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false) + MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false) + MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false) + MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false) + MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false) + MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false) + MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false) + MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false) + MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false) + MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false) + MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false) + MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false) + MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false) + MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false) + MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false) + MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false) + MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false) + MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false) + MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false) + MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false) + MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false) + MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false) + MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false) + MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false) + MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false) + MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false) + MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false) + MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false) + MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false) + MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false) + MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false) + MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false) + MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false) + MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false) + MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false) + MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false) + MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false) + MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false) + MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false) + MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false) + MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false) + MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false) + MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false) + MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false) + MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false) + MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false) + MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false) + MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false) + MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false) + MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false) + MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false) + MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false) + MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false) +#endif +}; + +const short da830_emif25_pins[] __initdata = { + DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, + DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, + DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, + DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, + DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, + DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, + DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, + DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, + DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, + DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, + -1 +}; + +const short da830_spi0_pins[] __initdata = { + DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + -1 +}; + +const short da830_spi1_pins[] __initdata = { + DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, + DA830_NSPI1_SCS_0, + -1 +}; + +const short da830_mmc_sd_pins[] __initdata = { + DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, + DA830_MMCSD_CMD, + -1 +}; + +const short da830_uart0_pins[] __initdata = { + DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, + -1 +}; + +const short da830_uart1_pins[] __initdata = { + DA830_UART1_RXD, DA830_UART1_TXD, + -1 +}; + +const short da830_uart2_pins[] __initdata = { + DA830_UART2_RXD, DA830_UART2_TXD, + -1 +}; + +const short da830_usb20_pins[] __initdata = { + DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, + -1 +}; + +const short da830_usb11_pins[] __initdata = { + DA830_USB_REFCLKIN, + -1 +}; + +const short da830_uhpi_pins[] __initdata = { + DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, + DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, + DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, + DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, + DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, + DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, DA830_NUHPI_HRDY, + -1 +}; + +const short da830_cpgmac_pins[] __initdata = { + DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, + DA830_MDIO_D, + -1 +}; + +const short da830_emif3c_pins[] __initdata = { + DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, + DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, + DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, + DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, + DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, + DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, + DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, + DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, + DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, + DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, + DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, + DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, + DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, + DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, + -1 +}; + +const short da830_mcasp0_pins[] __initdata = { + DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, + DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, + DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, + DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, + DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, + DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, + -1 +}; + +const short da830_mcasp1_pins[] __initdata = { + DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, + DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, + DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, + DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, + DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, + -1 +}; + +const short da830_mcasp2_pins[] __initdata = { + DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, + DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, + DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, + -1 +}; + +const short da830_i2c0_pins[] __initdata = { + DA830_I2C0_SDA, DA830_I2C0_SCL, + -1 +}; + +const short da830_i2c1_pins[] __initdata = { + DA830_I2C1_SCL, DA830_I2C1_SDA, + -1 +}; + +const short da830_lcdcntl_pins[] __initdata = { + DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, + DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, + DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, + DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, + DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + -1 +}; + +const short da830_pwm_pins[] __initdata = { + DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, + DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, + DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, + -1 +}; + +const short da830_ecap0_pins[] __initdata = { + DA830_ECAP0_APWM0, + -1 +}; + +const short da830_ecap1_pins[] __initdata = { + DA830_ECAP1_APWM1, + -1 +}; + +const short da830_ecap2_pins[] __initdata = { + DA830_ECAP2_APWM2, + -1 +}; + +const short da830_eqep0_pins[] __initdata = { + DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, + -1 +}; + +const short da830_eqep1_pins[] __initdata = { + DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, + -1 +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { + [IRQ_DA8XX_COMMTX] = 7, + [IRQ_DA8XX_COMMRX] = 7, + [IRQ_DA8XX_NINT] = 7, + [IRQ_DA8XX_EVTOUT0] = 7, + [IRQ_DA8XX_EVTOUT1] = 7, + [IRQ_DA8XX_EVTOUT2] = 7, + [IRQ_DA8XX_EVTOUT3] = 7, + [IRQ_DA8XX_EVTOUT4] = 7, + [IRQ_DA8XX_EVTOUT5] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT7] = 7, + [IRQ_DA8XX_CCINT0] = 7, + [IRQ_DA8XX_CCERRINT] = 7, + [IRQ_DA8XX_TCERRINT0] = 7, + [IRQ_DA8XX_AEMIFINT] = 7, + [IRQ_DA8XX_I2CINT0] = 7, + [IRQ_DA8XX_MMCSDINT0] = 7, + [IRQ_DA8XX_MMCSDINT1] = 7, + [IRQ_DA8XX_ALLINT0] = 7, + [IRQ_DA8XX_RTC] = 7, + [IRQ_DA8XX_SPINT0] = 7, + [IRQ_DA8XX_TINT12_0] = 7, + [IRQ_DA8XX_TINT34_0] = 7, + [IRQ_DA8XX_TINT12_1] = 7, + [IRQ_DA8XX_TINT34_1] = 7, + [IRQ_DA8XX_UARTINT0] = 7, + [IRQ_DA8XX_KEYMGRINT] = 7, + [IRQ_DA8XX_SECINT] = 7, + [IRQ_DA8XX_SECKEYERR] = 7, + [IRQ_DA830_MPUERR] = 7, + [IRQ_DA830_IOPUERR] = 7, + [IRQ_DA830_BOOTCFGERR] = 7, + [IRQ_DA8XX_CHIPINT0] = 7, + [IRQ_DA8XX_CHIPINT1] = 7, + [IRQ_DA8XX_CHIPINT2] = 7, + [IRQ_DA8XX_CHIPINT3] = 7, + [IRQ_DA8XX_TCERRINT1] = 7, + [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C0_RX_PULSE] = 7, + [IRQ_DA8XX_C0_TX_PULSE] = 7, + [IRQ_DA8XX_C0_MISC_PULSE] = 7, + [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C1_RX_PULSE] = 7, + [IRQ_DA8XX_C1_TX_PULSE] = 7, + [IRQ_DA8XX_C1_MISC_PULSE] = 7, + [IRQ_DA8XX_MEMERR] = 7, + [IRQ_DA8XX_GPIO0] = 7, + [IRQ_DA8XX_GPIO1] = 7, + [IRQ_DA8XX_GPIO2] = 7, + [IRQ_DA8XX_GPIO3] = 7, + [IRQ_DA8XX_GPIO4] = 7, + [IRQ_DA8XX_GPIO5] = 7, + [IRQ_DA8XX_GPIO6] = 7, + [IRQ_DA8XX_GPIO7] = 7, + [IRQ_DA8XX_GPIO8] = 7, + [IRQ_DA8XX_I2CINT1] = 7, + [IRQ_DA8XX_LCDINT] = 7, + [IRQ_DA8XX_UARTINT1] = 7, + [IRQ_DA8XX_MCASPINT] = 7, + [IRQ_DA8XX_ALLINT1] = 7, + [IRQ_DA8XX_SPINT1] = 7, + [IRQ_DA8XX_UHPI_INT1] = 7, + [IRQ_DA8XX_USB_INT] = 7, + [IRQ_DA8XX_IRQN] = 7, + [IRQ_DA8XX_RWAKEUP] = 7, + [IRQ_DA8XX_UARTINT2] = 7, + [IRQ_DA8XX_DFTSSINT] = 7, + [IRQ_DA8XX_EHRPWM0] = 7, + [IRQ_DA8XX_EHRPWM0TZ] = 7, + [IRQ_DA8XX_EHRPWM1] = 7, + [IRQ_DA8XX_EHRPWM1TZ] = 7, + [IRQ_DA830_EHRPWM2] = 7, + [IRQ_DA830_EHRPWM2TZ] = 7, + [IRQ_DA8XX_ECAP0] = 7, + [IRQ_DA8XX_ECAP1] = 7, + [IRQ_DA8XX_ECAP2] = 7, + [IRQ_DA830_EQEP0] = 7, + [IRQ_DA830_EQEP1] = 7, + [IRQ_DA830_T12CMPINT0_0] = 7, + [IRQ_DA830_T12CMPINT1_0] = 7, + [IRQ_DA830_T12CMPINT2_0] = 7, + [IRQ_DA830_T12CMPINT3_0] = 7, + [IRQ_DA830_T12CMPINT4_0] = 7, + [IRQ_DA830_T12CMPINT5_0] = 7, + [IRQ_DA830_T12CMPINT6_0] = 7, + [IRQ_DA830_T12CMPINT7_0] = 7, + [IRQ_DA830_T12CMPINT0_1] = 7, + [IRQ_DA830_T12CMPINT1_1] = 7, + [IRQ_DA830_T12CMPINT2_1] = 7, + [IRQ_DA830_T12CMPINT3_1] = 7, + [IRQ_DA830_T12CMPINT4_1] = 7, + [IRQ_DA830_T12CMPINT5_1] = 7, + [IRQ_DA830_T12CMPINT6_1] = 7, + [IRQ_DA830_T12CMPINT7_1] = 7, + [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, +}; + +static struct map_desc da830_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +static void __iomem *da830_psc_bases[] = { + IO_ADDRESS(DA8XX_PSC0_BASE), + IO_ADDRESS(DA8XX_PSC1_BASE), +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da830_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7df, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA830, + .name = "da830/omap l137", + }, +}; + +static struct davinci_timer_instance da830_timer_instance[2] = { + { + .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_0, + .top_irq = IRQ_DA8XX_TINT34_0, + .cmp_off = DA830_CMP12_0, + .cmp_irq = IRQ_DA830_T12CMPINT0_0, + }, + { + .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_1, + .top_irq = IRQ_DA8XX_TINT34_1, + .cmp_off = DA830_CMP12_0, + .cmp_irq = IRQ_DA830_T12CMPINT0_1, + }, +}; + +/* + * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource + * T0_TOP: Timer 0, top : Used by DSP + * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + */ +static struct davinci_timer_info da830_timer_info = { + .timers = da830_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_BOT, +}; + +static struct davinci_soc_info davinci_soc_info_da830 = { + .io_desc = da830_io_desc, + .io_desc_num = ARRAY_SIZE(da830_io_desc), + .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), + .ids = da830_ids, + .ids_num = ARRAY_SIZE(da830_ids), + .cpu_clks = da830_clks, + .psc_bases = da830_psc_bases, + .psc_bases_num = ARRAY_SIZE(da830_psc_bases), + .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), + .pinmux_pins = da830_pins, + .pinmux_pins_num = ARRAY_SIZE(da830_pins), + .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_irq_prios = da830_default_priorities, + .intc_irq_num = DA830_N_CP_INTC_IRQ, + .timer_info = &da830_timer_info, + .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_num = 128, + .gpio_irq = IRQ_DA8XX_GPIO0, + .serial_dev = &da8xx_serial_device, + .emac_pdata = &da8xx_emac_pdata, +}; + +void __init da830_init(void) +{ + davinci_common_init(&davinci_soc_info_da830); +} diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c new file mode 100644 index 00000000000..192d719a47d --- /dev/null +++ b/arch/arm/mach-davinci/da850.c @@ -0,0 +1,820 @@ +/* + * TI DA850/OMAP-L138 chip specific setup + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/da830.c + * Original Copyrights follow: + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/clock.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/time.h> +#include <mach/da8xx.h> + +#include "clock.h" +#include "mux.h" + +#define DA850_PLL1_BASE 0x01e1a000 +#define DA850_TIMER64P2_BASE 0x01f0c000 +#define DA850_TIMER64P3_BASE 0x01f0d000 + +#define DA850_REF_FREQ 24000000 + +static struct pll_data pll0_data = { + .num = 1, + .phys_base = DA8XX_PLL0_BASE, + .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DA850_REF_FREQ, +}; + +static struct clk pll0_clk = { + .name = "pll0", + .parent = &ref_clk, + .pll_data = &pll0_data, + .flags = CLK_PLL, +}; + +static struct clk pll0_aux_clk = { + .name = "pll0_aux_clk", + .parent = &pll0_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll0_sysclk2 = { + .name = "pll0_sysclk2", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll0_sysclk3 = { + .name = "pll0_sysclk3", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll0_sysclk4 = { + .name = "pll0_sysclk4", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll0_sysclk5 = { + .name = "pll0_sysclk5", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll0_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll0_sysclk7 = { + .name = "pll0_sysclk7", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct pll_data pll1_data = { + .num = 2, + .phys_base = DA850_PLL1_BASE, + .flags = PLL_HAS_POSTDIV, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .pll_data = &pll1_data, + .flags = CLK_PLL, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_sysclk6 = { + .name = "pll0_sysclk6", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll1_sysclk7 = { + .name = "pll1_sysclk7", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk i2c0_clk = { + .name = "i2c0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_0_clk = { + .name = "timer0", + .parent = &pll0_aux_clk, +}; + +static struct clk timerp64_1_clk = { + .name = "timer1", + .parent = &pll0_aux_clk, +}; + +static struct clk arm_rom_clk = { + .name = "arm_rom", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc0_clk = { + .name = "tpcc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPCC, + .flags = ALWAYS_ENABLED | CLK_PSC, +}; + +static struct clk tptc0_clk = { + .name = "tptc0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tptc1_clk = { + .name = "tptc1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk tpcc1_clk = { + .name = "tpcc1", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_TPCC1, + .flags = CLK_PSC | ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk tptc2_clk = { + .name = "tptc2", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_TPTC2, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART1, + .psc_ctlr = 1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_UART2, + .psc_ctlr = 1, +}; + +static struct clk aintc_clk = { + .name = "aintc", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC0_AINTC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_GPIO, + .psc_ctlr = 1, +}; + +static struct clk i2c1_clk = { + .name = "i2c1", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_I2C, + .psc_ctlr = 1, +}; + +static struct clk emif3_clk = { + .name = "emif3", + .parent = &pll0_sysclk5, + .lpsc = DA8XX_LPSC1_EMIF3C, + .flags = ALWAYS_ENABLED, + .psc_ctlr = 1, +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll0_sysclk6, + .lpsc = DA8XX_LPSC0_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk rmii_clk = { + .name = "rmii", + .parent = &pll0_sysclk7, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll0_sysclk4, + .lpsc = DA8XX_LPSC1_CPGMAC, + .psc_ctlr = 1, +}; + +static struct clk mcasp_clk = { + .name = "mcasp", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_McASP0, + .psc_ctlr = 1, +}; + +static struct clk lcdc_clk = { + .name = "lcdc", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_LCDC, + .psc_ctlr = 1, +}; + +static struct clk mmcsd_clk = { + .name = "mmcsd", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC0_MMC_SD, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll0_sysclk3, + .lpsc = DA8XX_LPSC0_EMIF25, + .flags = ALWAYS_ENABLED, +}; + +static struct davinci_clk da850_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll0", &pll0_clk), + CLK(NULL, "pll0_aux", &pll0_aux_clk), + CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), + CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), + CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), + CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), + CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), + CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), + CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), + CLK("i2c_davinci.1", NULL, &i2c0_clk), + CLK(NULL, "timer0", &timerp64_0_clk), + CLK("watchdog", NULL, &timerp64_1_clk), + CLK(NULL, "arm_rom", &arm_rom_clk), + CLK(NULL, "tpcc0", &tpcc0_clk), + CLK(NULL, "tptc0", &tptc0_clk), + CLK(NULL, "tptc1", &tptc1_clk), + CLK(NULL, "tpcc1", &tpcc1_clk), + CLK(NULL, "tptc2", &tptc2_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK(NULL, "aintc", &aintc_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK("i2c_davinci.2", NULL, &i2c1_clk), + CLK(NULL, "emif3", &emif3_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "rmii", &rmii_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci-mcasp.0", NULL, &mcasp_clk), + CLK("da8xx_lcdc.0", NULL, &lcdc_clk), + CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, NULL, NULL), +}; + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config da850_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + /* UART0 function */ + MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) + MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) + MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) + MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) + /* UART1 function */ + MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) + MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) + /* UART2 function */ + MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) + MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) + /* I2C1 function */ + MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) + MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) + /* I2C0 function */ + MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) + MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) + /* EMAC function */ + MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) + MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) + MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) + MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) + MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) + MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) + MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) + MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) + MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) + MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) + MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) + MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) + MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) + MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) + MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) + MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) + MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) + /* McASP function */ + MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) + MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) + MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) + MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) + MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) + MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) + MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) + MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) + MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) + MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) + MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) + MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) + MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) + MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) + MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) + MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) + MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) + MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) + MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) + MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) + MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) + MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) + MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) + /* LCD function */ + MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) + MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) + MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) + MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) + MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) + MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) + /* MMC/SD0 function */ + MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) + /* EMIF2.5/EMIFA function */ + MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) + MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) + MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) + MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) + MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) + MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) + MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) + /* GPIO function */ + MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) + MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false) + MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) + MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) +#endif +}; + +const short da850_uart0_pins[] __initdata = { + DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD, + -1 +}; + +const short da850_uart1_pins[] __initdata = { + DA850_UART1_RXD, DA850_UART1_TXD, + -1 +}; + +const short da850_uart2_pins[] __initdata = { + DA850_UART2_RXD, DA850_UART2_TXD, + -1 +}; + +const short da850_i2c0_pins[] __initdata = { + DA850_I2C0_SDA, DA850_I2C0_SCL, + -1 +}; + +const short da850_i2c1_pins[] __initdata = { + DA850_I2C1_SCL, DA850_I2C1_SDA, + -1 +}; + +const short da850_cpgmac_pins[] __initdata = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +const short da850_mcasp_pins[] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, + DA850_AXR_11, DA850_AXR_12, + -1 +}; + +const short da850_lcdcntl_pins[] __initdata = { + DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4, + DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8, + DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12, + DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK, + DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15, + DA850_GPIO8_10, + -1 +}; + +const short da850_mmcsd0_pins[] __initdata = { + DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, + DA850_GPIO4_0, DA850_GPIO4_1, + -1 +}; + +const short da850_nand_pins[] __initdata = { + DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4, + DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0, + DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, + DA850_NEMA_WE, DA850_NEMA_OE, + -1 +}; + +const short da850_nor_pins[] __initdata = { + DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, + DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, + DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, + DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, + DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, + DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, + DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, + DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, + DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, + DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, + DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, + DA850_EMA_A_22, DA850_EMA_A_23, + -1 +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { + [IRQ_DA8XX_COMMTX] = 7, + [IRQ_DA8XX_COMMRX] = 7, + [IRQ_DA8XX_NINT] = 7, + [IRQ_DA8XX_EVTOUT0] = 7, + [IRQ_DA8XX_EVTOUT1] = 7, + [IRQ_DA8XX_EVTOUT2] = 7, + [IRQ_DA8XX_EVTOUT3] = 7, + [IRQ_DA8XX_EVTOUT4] = 7, + [IRQ_DA8XX_EVTOUT5] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT6] = 7, + [IRQ_DA8XX_EVTOUT7] = 7, + [IRQ_DA8XX_CCINT0] = 7, + [IRQ_DA8XX_CCERRINT] = 7, + [IRQ_DA8XX_TCERRINT0] = 7, + [IRQ_DA8XX_AEMIFINT] = 7, + [IRQ_DA8XX_I2CINT0] = 7, + [IRQ_DA8XX_MMCSDINT0] = 7, + [IRQ_DA8XX_MMCSDINT1] = 7, + [IRQ_DA8XX_ALLINT0] = 7, + [IRQ_DA8XX_RTC] = 7, + [IRQ_DA8XX_SPINT0] = 7, + [IRQ_DA8XX_TINT12_0] = 7, + [IRQ_DA8XX_TINT34_0] = 7, + [IRQ_DA8XX_TINT12_1] = 7, + [IRQ_DA8XX_TINT34_1] = 7, + [IRQ_DA8XX_UARTINT0] = 7, + [IRQ_DA8XX_KEYMGRINT] = 7, + [IRQ_DA8XX_SECINT] = 7, + [IRQ_DA8XX_SECKEYERR] = 7, + [IRQ_DA850_MPUADDRERR0] = 7, + [IRQ_DA850_MPUPROTERR0] = 7, + [IRQ_DA850_IOPUADDRERR0] = 7, + [IRQ_DA850_IOPUPROTERR0] = 7, + [IRQ_DA850_IOPUADDRERR1] = 7, + [IRQ_DA850_IOPUPROTERR1] = 7, + [IRQ_DA850_IOPUADDRERR2] = 7, + [IRQ_DA850_IOPUPROTERR2] = 7, + [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7, + [IRQ_DA850_BOOTCFG_PROT_ERR] = 7, + [IRQ_DA850_MPUADDRERR1] = 7, + [IRQ_DA850_MPUPROTERR1] = 7, + [IRQ_DA850_IOPUADDRERR3] = 7, + [IRQ_DA850_IOPUPROTERR3] = 7, + [IRQ_DA850_IOPUADDRERR4] = 7, + [IRQ_DA850_IOPUPROTERR4] = 7, + [IRQ_DA850_IOPUADDRERR5] = 7, + [IRQ_DA850_IOPUPROTERR5] = 7, + [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7, + [IRQ_DA8XX_CHIPINT0] = 7, + [IRQ_DA8XX_CHIPINT1] = 7, + [IRQ_DA8XX_CHIPINT2] = 7, + [IRQ_DA8XX_CHIPINT3] = 7, + [IRQ_DA8XX_TCERRINT1] = 7, + [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C0_RX_PULSE] = 7, + [IRQ_DA8XX_C0_TX_PULSE] = 7, + [IRQ_DA8XX_C0_MISC_PULSE] = 7, + [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, + [IRQ_DA8XX_C1_RX_PULSE] = 7, + [IRQ_DA8XX_C1_TX_PULSE] = 7, + [IRQ_DA8XX_C1_MISC_PULSE] = 7, + [IRQ_DA8XX_MEMERR] = 7, + [IRQ_DA8XX_GPIO0] = 7, + [IRQ_DA8XX_GPIO1] = 7, + [IRQ_DA8XX_GPIO2] = 7, + [IRQ_DA8XX_GPIO3] = 7, + [IRQ_DA8XX_GPIO4] = 7, + [IRQ_DA8XX_GPIO5] = 7, + [IRQ_DA8XX_GPIO6] = 7, + [IRQ_DA8XX_GPIO7] = 7, + [IRQ_DA8XX_GPIO8] = 7, + [IRQ_DA8XX_I2CINT1] = 7, + [IRQ_DA8XX_LCDINT] = 7, + [IRQ_DA8XX_UARTINT1] = 7, + [IRQ_DA8XX_MCASPINT] = 7, + [IRQ_DA8XX_ALLINT1] = 7, + [IRQ_DA8XX_SPINT1] = 7, + [IRQ_DA8XX_UHPI_INT1] = 7, + [IRQ_DA8XX_USB_INT] = 7, + [IRQ_DA8XX_IRQN] = 7, + [IRQ_DA8XX_RWAKEUP] = 7, + [IRQ_DA8XX_UARTINT2] = 7, + [IRQ_DA8XX_DFTSSINT] = 7, + [IRQ_DA8XX_EHRPWM0] = 7, + [IRQ_DA8XX_EHRPWM0TZ] = 7, + [IRQ_DA8XX_EHRPWM1] = 7, + [IRQ_DA8XX_EHRPWM1TZ] = 7, + [IRQ_DA850_SATAINT] = 7, + [IRQ_DA850_TINT12_2] = 7, + [IRQ_DA850_TINT34_2] = 7, + [IRQ_DA850_TINTALL_2] = 7, + [IRQ_DA8XX_ECAP0] = 7, + [IRQ_DA8XX_ECAP1] = 7, + [IRQ_DA8XX_ECAP2] = 7, + [IRQ_DA850_MMCSDINT0_1] = 7, + [IRQ_DA850_MMCSDINT1_1] = 7, + [IRQ_DA850_T12CMPINT0_2] = 7, + [IRQ_DA850_T12CMPINT1_2] = 7, + [IRQ_DA850_T12CMPINT2_2] = 7, + [IRQ_DA850_T12CMPINT3_2] = 7, + [IRQ_DA850_T12CMPINT4_2] = 7, + [IRQ_DA850_T12CMPINT5_2] = 7, + [IRQ_DA850_T12CMPINT6_2] = 7, + [IRQ_DA850_T12CMPINT7_2] = 7, + [IRQ_DA850_T12CMPINT0_3] = 7, + [IRQ_DA850_T12CMPINT1_3] = 7, + [IRQ_DA850_T12CMPINT2_3] = 7, + [IRQ_DA850_T12CMPINT3_3] = 7, + [IRQ_DA850_T12CMPINT4_3] = 7, + [IRQ_DA850_T12CMPINT5_3] = 7, + [IRQ_DA850_T12CMPINT6_3] = 7, + [IRQ_DA850_T12CMPINT7_3] = 7, + [IRQ_DA850_RPIINT] = 7, + [IRQ_DA850_VPIFINT] = 7, + [IRQ_DA850_CCINT1] = 7, + [IRQ_DA850_CCERRINT1] = 7, + [IRQ_DA850_TCERRINT2] = 7, + [IRQ_DA850_TINT12_3] = 7, + [IRQ_DA850_TINT34_3] = 7, + [IRQ_DA850_TINTALL_3] = 7, + [IRQ_DA850_MCBSP0RINT] = 7, + [IRQ_DA850_MCBSP0XINT] = 7, + [IRQ_DA850_MCBSP1RINT] = 7, + [IRQ_DA850_MCBSP1XINT] = 7, + [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, +}; + +static struct map_desc da850_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = DA8XX_CP_INTC_VIRT, + .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), + .length = DA8XX_CP_INTC_SIZE, + .type = MT_DEVICE + }, +}; + +static void __iomem *da850_psc_bases[] = { + IO_ADDRESS(DA8XX_PSC0_BASE), + IO_ADDRESS(DA8XX_PSC1_BASE), +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id da850_ids[] = { + { + .variant = 0x0, + .part_no = 0xb7d1, + .manufacturer = 0x017, /* 0x02f >> 1 */ + .cpu_id = DAVINCI_CPU_ID_DA850, + .name = "da850/omap-l138", + }, +}; + +static struct davinci_timer_instance da850_timer_instance[4] = { + { + .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_0, + .top_irq = IRQ_DA8XX_TINT34_0, + }, + { + .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), + .bottom_irq = IRQ_DA8XX_TINT12_1, + .top_irq = IRQ_DA8XX_TINT34_1, + }, + { + .base = IO_ADDRESS(DA850_TIMER64P2_BASE), + .bottom_irq = IRQ_DA850_TINT12_2, + .top_irq = IRQ_DA850_TINT34_2, + }, + { + .base = IO_ADDRESS(DA850_TIMER64P3_BASE), + .bottom_irq = IRQ_DA850_TINT12_3, + .top_irq = IRQ_DA850_TINT34_3, + }, +}; + +/* + * T0_BOT: Timer 0, bottom : Used for clock_event + * T0_TOP: Timer 0, top : Used for clocksource + * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer + */ +static struct davinci_timer_info da850_timer_info = { + .timers = da850_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct davinci_soc_info davinci_soc_info_da850 = { + .io_desc = da850_io_desc, + .io_desc_num = ARRAY_SIZE(da850_io_desc), + .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), + .ids = da850_ids, + .ids_num = ARRAY_SIZE(da850_ids), + .cpu_clks = da850_clks, + .psc_bases = da850_psc_bases, + .psc_bases_num = ARRAY_SIZE(da850_psc_bases), + .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), + .pinmux_pins = da850_pins, + .pinmux_pins_num = ARRAY_SIZE(da850_pins), + .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_irq_prios = da850_default_priorities, + .intc_irq_num = DA850_N_CP_INTC_IRQ, + .timer_info = &da850_timer_info, + .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), + .gpio_num = 144, + .gpio_irq = IRQ_DA8XX_GPIO0, + .serial_dev = &da8xx_serial_device, + .emac_pdata = &da8xx_emac_pdata, +}; + +void __init da850_init(void) +{ + davinci_common_init(&davinci_soc_info_da850); +} diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c new file mode 100644 index 00000000000..58ad5b66fd6 --- /dev/null +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -0,0 +1,450 @@ +/* + * DA8XX/OMAP L1XX platform device data + * + * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com> + * Derived from code that was: + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/serial_8250.h> + +#include <mach/cputype.h> +#include <mach/common.h> +#include <mach/time.h> +#include <mach/da8xx.h> +#include <video/da8xx-fb.h> + +#include "clock.h" + +#define DA8XX_TPCC_BASE 0x01c00000 +#define DA8XX_TPTC0_BASE 0x01c08000 +#define DA8XX_TPTC1_BASE 0x01c08400 +#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ +#define DA8XX_I2C0_BASE 0x01c22000 +#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 +#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 +#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 +#define DA8XX_EMAC_MDIO_BASE 0x01e24000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_I2C1_BASE 0x01e28000 + +#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 +#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 +#define DA8XX_EMAC_RAM_OFFSET 0x0000 +#define DA8XX_MDIO_REG_OFFSET 0x4000 +#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K + +static struct plat_serial8250_port da8xx_serial_pdata[] = { + { + .mapbase = DA8XX_UART0_BASE, + .irq = IRQ_DA8XX_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DA8XX_UART1_BASE, + .irq = IRQ_DA8XX_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DA8XX_UART2_BASE, + .irq = IRQ_DA8XX_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0, + }, +}; + +struct platform_device da8xx_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = da8xx_serial_pdata, + }, +}; + +static const s8 da8xx_dma_chan_no_event[] = { + 20, 21, + -1 +}; + +static const s8 da8xx_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1} +}; + +static const s8 da8xx_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1} +}; + +static struct edma_soc_info da8xx_edma_info[] = { + { + .n_channel = 32, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = da8xx_dma_chan_no_event, + .queue_tc_mapping = da8xx_queue_tc_mapping, + .queue_priority_mapping = da8xx_queue_priority_mapping, + }, +}; + +static struct resource da8xx_edma_resources[] = { + { + .name = "edma_cc0", + .start = DA8XX_TPCC_BASE, + .end = DA8XX_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = DA8XX_TPTC0_BASE, + .end = DA8XX_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = DA8XX_TPTC1_BASE, + .end = DA8XX_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_DA8XX_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_DA8XX_CCERRINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_edma_device = { + .name = "edma", + .id = -1, + .dev = { + .platform_data = da8xx_edma_info, + }, + .num_resources = ARRAY_SIZE(da8xx_edma_resources), + .resource = da8xx_edma_resources, +}; + +int __init da8xx_register_edma(void) +{ + return platform_device_register(&da8xx_edma_device); +} + +static struct resource da8xx_i2c_resources0[] = { + { + .start = DA8XX_I2C0_BASE, + .end = DA8XX_I2C0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_I2CINT0, + .end = IRQ_DA8XX_I2CINT0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_i2c_device0 = { + .name = "i2c_davinci", + .id = 1, + .num_resources = ARRAY_SIZE(da8xx_i2c_resources0), + .resource = da8xx_i2c_resources0, +}; + +static struct resource da8xx_i2c_resources1[] = { + { + .start = DA8XX_I2C1_BASE, + .end = DA8XX_I2C1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_I2CINT1, + .end = IRQ_DA8XX_I2CINT1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da8xx_i2c_device1 = { + .name = "i2c_davinci", + .id = 2, + .num_resources = ARRAY_SIZE(da8xx_i2c_resources1), + .resource = da8xx_i2c_resources1, +}; + +int __init da8xx_register_i2c(int instance, + struct davinci_i2c_platform_data *pdata) +{ + struct platform_device *pdev; + + if (instance == 0) + pdev = &da8xx_i2c_device0; + else if (instance == 1) + pdev = &da8xx_i2c_device1; + else + return -EINVAL; + + pdev->dev.platform_data = pdata; + return platform_device_register(pdev); +} + +static struct resource da8xx_watchdog_resources[] = { + { + .start = DA8XX_WDOG_BASE, + .end = DA8XX_WDOG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device davinci_wdt_device = { + .name = "watchdog", + .id = -1, + .num_resources = ARRAY_SIZE(da8xx_watchdog_resources), + .resource = da8xx_watchdog_resources, +}; + +int __init da8xx_register_watchdog(void) +{ + return platform_device_register(&davinci_wdt_device); +} + +static struct resource da8xx_emac_resources[] = { + { + .start = DA8XX_EMAC_CPPI_PORT_BASE, + .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_C0_RX_THRESH_PULSE, + .end = IRQ_DA8XX_C0_RX_THRESH_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_RX_PULSE, + .end = IRQ_DA8XX_C0_RX_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_TX_PULSE, + .end = IRQ_DA8XX_C0_TX_PULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DA8XX_C0_MISC_PULSE, + .end = IRQ_DA8XX_C0_MISC_PULSE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct emac_platform_data da8xx_emac_pdata = { + .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, + .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, + .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, + .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, + .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, + .version = EMAC_VERSION_2, +}; + +static struct platform_device da8xx_emac_device = { + .name = "davinci_emac", + .id = 1, + .dev = { + .platform_data = &da8xx_emac_pdata, + }, + .num_resources = ARRAY_SIZE(da8xx_emac_resources), + .resource = da8xx_emac_resources, +}; + +static struct resource da830_mcasp1_resources[] = { + { + .name = "mcasp1", + .start = DAVINCI_DA830_MCASP1_REG_BASE, + .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .start = DAVINCI_DA830_DMA_MCASP1_AXEVT, + .end = DAVINCI_DA830_DMA_MCASP1_AXEVT, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .start = DAVINCI_DA830_DMA_MCASP1_AREVT, + .end = DAVINCI_DA830_DMA_MCASP1_AREVT, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da830_mcasp1_device = { + .name = "davinci-mcasp", + .id = 1, + .num_resources = ARRAY_SIZE(da830_mcasp1_resources), + .resource = da830_mcasp1_resources, +}; + +static struct resource da850_mcasp_resources[] = { + { + .name = "mcasp", + .start = DAVINCI_DA8XX_MCASP0_REG_BASE, + .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, + .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, + .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da850_mcasp_device = { + .name = "davinci-mcasp", + .id = 0, + .num_resources = ARRAY_SIZE(da850_mcasp_resources), + .resource = da850_mcasp_resources, +}; + +int __init da8xx_register_emac(void) +{ + return platform_device_register(&da8xx_emac_device); +} + +void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata) +{ + /* DA830/OMAP-L137 has 3 instances of McASP */ + if (cpu_is_davinci_da830() && id == 1) { + da830_mcasp1_device.dev.platform_data = pdata; + platform_device_register(&da830_mcasp1_device); + } else if (cpu_is_davinci_da850()) { + da850_mcasp_device.dev.platform_data = pdata; + platform_device_register(&da850_mcasp_device); + } +} + +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static struct da8xx_lcdc_platform_data da850_evm_lcdc_pdata = { + .manu_name = "sharp", + .controller_data = &lcd_cfg, + .type = "Sharp_LK043T1DG01", +}; + +static struct resource da8xx_lcdc_resources[] = { + [0] = { /* registers */ + .start = DA8XX_LCD_CNTRL_BASE, + .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { /* interrupt */ + .start = IRQ_DA8XX_LCDINT, + .end = IRQ_DA8XX_LCDINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device da850_lcdc_device = { + .name = "da8xx_lcdc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), + .resource = da8xx_lcdc_resources, + .dev = { + .platform_data = &da850_evm_lcdc_pdata, + } +}; + +int __init da8xx_register_lcdc(void) +{ + return platform_device_register(&da850_lcdc_device); +} + +static struct resource da8xx_mmcsd0_resources[] = { + { /* registers */ + .start = DA8XX_MMCSD0_BASE, + .end = DA8XX_MMCSD0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DA8XX_MMCSDINT0, + .end = IRQ_DA8XX_MMCSDINT0, + .flags = IORESOURCE_IRQ, + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(0, 16), + .end = EDMA_CTLR_CHAN(0, 16), + .flags = IORESOURCE_DMA, + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(0, 17), + .end = EDMA_CTLR_CHAN(0, 17), + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da8xx_mmcsd0_device = { + .name = "davinci_mmc", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources), + .resource = da8xx_mmcsd0_resources, +}; + +int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) +{ + da8xx_mmcsd0_device.dev.platform_data = config; + return platform_device_register(&da8xx_mmcsd0_device); +} diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index de16f347566..a55b650db71 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -31,6 +31,8 @@ #define DAVINCI_MMCSD0_BASE 0x01E10000 #define DM355_MMCSD0_BASE 0x01E11000 #define DM355_MMCSD1_BASE 0x01E00000 +#define DM365_MMCSD0_BASE 0x01D11000 +#define DM365_MMCSD1_BASE 0x01D00000 static struct resource i2c_resources[] = { { @@ -82,10 +84,10 @@ static struct resource mmcsd0_resources[] = { }, /* DMA channels: RX, then TX */ { - .start = DAVINCI_DMA_MMCRXEVT, + .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT), .flags = IORESOURCE_DMA, }, { - .start = DAVINCI_DMA_MMCTXEVT, + .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT), .flags = IORESOURCE_DMA, }, }; @@ -119,10 +121,10 @@ static struct resource mmcsd1_resources[] = { }, /* DMA channels: RX, then TX */ { - .start = 30, /* rx */ + .start = EDMA_CTLR_CHAN(0, 30), /* rx */ .flags = IORESOURCE_DMA, }, { - .start = 31, /* tx */ + .start = EDMA_CTLR_CHAN(0, 31), /* tx */ .flags = IORESOURCE_DMA, }, }; @@ -154,19 +156,31 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) */ switch (module) { case 1: - if (!cpu_is_davinci_dm355()) + if (cpu_is_davinci_dm355()) { + /* REVISIT we may not need all these pins if e.g. this + * is a hard-wired SDIO device... + */ + davinci_cfg_reg(DM355_SD1_CMD); + davinci_cfg_reg(DM355_SD1_CLK); + davinci_cfg_reg(DM355_SD1_DATA0); + davinci_cfg_reg(DM355_SD1_DATA1); + davinci_cfg_reg(DM355_SD1_DATA2); + davinci_cfg_reg(DM355_SD1_DATA3); + } else if (cpu_is_davinci_dm365()) { + void __iomem *pupdctl1 = + IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); + + /* Configure pull down control */ + __raw_writel((__raw_readl(pupdctl1) & ~0x400), + pupdctl1); + + mmcsd1_resources[0].start = DM365_MMCSD1_BASE; + mmcsd1_resources[0].end = DM365_MMCSD1_BASE + + SZ_4K - 1; + mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1; + } else break; - /* REVISIT we may not need all these pins if e.g. this - * is a hard-wired SDIO device... - */ - davinci_cfg_reg(DM355_SD1_CMD); - davinci_cfg_reg(DM355_SD1_CLK); - davinci_cfg_reg(DM355_SD1_DATA0); - davinci_cfg_reg(DM355_SD1_DATA1); - davinci_cfg_reg(DM355_SD1_DATA2); - davinci_cfg_reg(DM355_SD1_DATA3); - pdev = &davinci_mmcsd1_device; break; case 0: @@ -180,9 +194,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) /* enable RX EDMA */ davinci_cfg_reg(DM355_EVT26_MMC0_RX); - } - - else if (cpu_is_davinci_dm644x()) { + } else if (cpu_is_davinci_dm365()) { + mmcsd0_resources[0].start = DM365_MMCSD0_BASE; + mmcsd0_resources[0].end = DM365_MMCSD0_BASE + + SZ_4K - 1; + mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; + } else if (cpu_is_davinci_dm644x()) { /* REVISIT: should this be in board-init code? */ void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); @@ -216,6 +233,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) static struct resource wdt_resources[] = { { + .start = DAVINCI_WDOG_BASE, + .end = DAVINCI_WDOG_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, }; @@ -229,11 +248,6 @@ struct platform_device davinci_wdt_device = { static void davinci_init_wdt(void) { - struct davinci_soc_info *soc_info = &davinci_soc_info; - - wdt_resources[0].start = (resource_size_t)soc_info->wdt_base; - wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1; - platform_device_register(&davinci_wdt_device); } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index baaaf328de2..059670018af 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -30,6 +30,7 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -360,8 +361,8 @@ static struct davinci_clk dm355_clks[] = { CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), - CLK("soc-audio.0", NULL, &asp0_clk), - CLK("soc-audio.1", NULL, &asp1_clk), + CLK("davinci-asp.0", NULL, &asp0_clk), + CLK("davinci-asp.1", NULL, &asp1_clk), CLK("davinci_mmc.0", NULL, &mmcsd0_clk), CLK("davinci_mmc.1", NULL, &mmcsd1_clk), CLK(NULL, "spi0", &spi0_clk), @@ -481,6 +482,20 @@ INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) + +MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) +MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) +MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) +MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) +MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) + +MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) +MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) +MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) +MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) +MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) +MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false) +MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false) #endif }; @@ -558,17 +573,38 @@ static const s8 dma_chan_dm355_no_event[] = { -1 }; -static struct edma_soc_info dm355_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm355_no_event, +static const s8 +queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1}, +}; + +static const s8 +queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1}, +}; + +static struct edma_soc_info dm355_edma_info[] = { + { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = dma_chan_dm355_no_event, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, + }, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -586,10 +622,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -598,12 +636,98 @@ static struct resource edma_resources[] = { static struct platform_device dm355_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm355_edma_info, + .id = 0, + .dev.platform_data = dm355_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +static struct resource dm355_asp1_resources[] = { + { + .start = DAVINCI_ASP1_BASE, + .end = DAVINCI_ASP1_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DAVINCI_DMA_ASP1_TX, + .end = DAVINCI_DMA_ASP1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DMA_ASP1_RX, + .end = DAVINCI_DMA_ASP1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm355_asp1_device = { + .name = "davinci-asp", + .id = 1, + .num_resources = ARRAY_SIZE(dm355_asp1_resources), + .resource = dm355_asp1_resources, +}; + +static struct resource dm355_vpss_resources[] = { + { + /* VPSS BL Base address */ + .name = "vpss", + .start = 0x01c70800, + .end = 0x01c70800 + 0xff, + .flags = IORESOURCE_MEM, + }, + { + /* VPSS CLK Base address */ + .name = "vpss", + .start = 0x01c70000, + .end = 0x01c70000 + 0xf, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm355_vpss_device = { + .name = "vpss", + .id = -1, + .dev.platform_data = "dm355_vpss", + .num_resources = ARRAY_SIZE(dm355_vpss_resources), + .resource = dm355_vpss_resources, +}; + +static struct resource vpfe_resources[] = { + { + .start = IRQ_VDINT0, + .end = IRQ_VDINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_VDINT1, + .end = IRQ_VDINT1, + .flags = IORESOURCE_IRQ, + }, + /* CCDC Base address */ + { + .flags = IORESOURCE_MEM, + .start = 0x01c70600, + .end = 0x01c70600 + 0x1ff, + }, +}; + +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct platform_device vpfe_capture_dev = { + .name = CAPTURE_DRV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(vpfe_resources), + .resource = vpfe_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void dm355_set_vpfe_config(struct vpfe_config *cfg) +{ + vpfe_capture_dev.dev.platform_data = cfg; +} + /*----------------------------------------------------------------------*/ static struct map_desc dm355_io_desc[] = { @@ -704,7 +828,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .intc_irq_prios = dm355_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm355_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), .gpio_num = 104, .gpio_irq = IRQ_DM355_GPIOBNK0, @@ -713,6 +836,19 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { .sram_len = SZ_32K, }; +void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) +{ + /* we don't use ASP1 IRQs, or we'd need to mux them ... */ + if (evt_enable & ASP1_TX_EVT_EN) + davinci_cfg_reg(DM355_EVT8_ASP1_TX); + + if (evt_enable & ASP1_RX_EVT_EN) + davinci_cfg_reg(DM355_EVT9_ASP1_RX); + + dm355_asp1_device.dev.platform_data = pdata; + platform_device_register(&dm355_asp1_device); +} + void __init dm355_init(void) { davinci_common_init(&davinci_soc_info_dm355); @@ -725,6 +861,20 @@ static int __init dm355_init_devices(void) davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); + platform_device_register(&dm355_vpss_device); + /* + * setup Mux configuration for vpfe input and register + * vpfe capture platform device + */ + davinci_cfg_reg(DM355_VIN_PCLK); + davinci_cfg_reg(DM355_VIN_CAM_WEN); + davinci_cfg_reg(DM355_VIN_CAM_VD); + davinci_cfg_reg(DM355_VIN_CAM_HD); + davinci_cfg_reg(DM355_VIN_YIN_EN); + davinci_cfg_reg(DM355_VIN_CINL_EN); + davinci_cfg_reg(DM355_VIN_CINH_EN); + platform_device_register(&vpfe_capture_dev); + return 0; } postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c new file mode 100644 index 00000000000..e8151743470 --- /dev/null +++ b/arch/arm/mach-davinci/dm365.c @@ -0,0 +1,926 @@ +/* + * TI DaVinci DM365 chip specific setup + * + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/gpio.h> + +#include <asm/mach/map.h> + +#include <mach/dm365.h> +#include <mach/clock.h> +#include <mach/cputype.h> +#include <mach/edma.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/time.h> +#include <mach/serial.h> +#include <mach/common.h> + +#include "clock.h" +#include "mux.h" + +#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ + +static struct pll_data pll1_data = { + .num = 1, + .phys_base = DAVINCI_PLL1_BASE, + .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, +}; + +static struct pll_data pll2_data = { + .num = 2, + .phys_base = DAVINCI_PLL2_BASE, + .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DM365_REF_FREQ, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll1_data, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk clkout0_clk = { + .name = "clkout0", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_sysclk6 = { + .name = "pll1_sysclk6", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll1_sysclk7 = { + .name = "pll1_sysclk7", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk pll1_sysclk8 = { + .name = "pll1_sysclk8", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV8, +}; + +static struct clk pll1_sysclk9 = { + .name = "pll1_sysclk9", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV9, +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll2_data, +}; + +static struct clk pll2_aux_clk = { + .name = "pll2_aux_clk", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk clkout1_clk = { + .name = "clkout1", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclk2 = { + .name = "pll2_sysclk2", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll2_sysclk3 = { + .name = "pll2_sysclk3", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll2_sysclk4 = { + .name = "pll2_sysclk4", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll2_sysclk5 = { + .name = "pll2_sysclk5", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll2_sysclk6 = { + .name = "pll2_sysclk6", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll2_sysclk7 = { + .name = "pll2_sysclk7", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk pll2_sysclk8 = { + .name = "pll2_sysclk8", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV8, +}; + +static struct clk pll2_sysclk9 = { + .name = "pll2_sysclk9", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV9, +}; + +static struct clk vpss_dac_clk = { + .name = "vpss_dac", + .parent = &pll1_sysclk3, + .lpsc = DM365_LPSC_DAC_CLK, +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk5, + .lpsc = DM365_LPSC_VPSSMSTR, + .flags = CLK_PSC, +}; + +static struct clk arm_clk = { + .name = "arm_clk", + .parent = &pll2_sysclk2, + .lpsc = DAVINCI_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_UART1, +}; + +static struct clk i2c_clk = { + .name = "i2c", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_I2C, +}; + +static struct clk mmcsd0_clk = { + .name = "mmcsd0", + .parent = &pll1_sysclk8, + .lpsc = DAVINCI_LPSC_MMC_SD, +}; + +static struct clk mmcsd1_clk = { + .name = "mmcsd1", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_MMC_SD1, +}; + +static struct clk spi0_clk = { + .name = "spi0", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_SPI, +}; + +static struct clk spi1_clk = { + .name = "spi1", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_SPI1, +}; + +static struct clk spi2_clk = { + .name = "spi2", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_SPI2, +}; + +static struct clk spi3_clk = { + .name = "spi3", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_SPI3, +}; + +static struct clk spi4_clk = { + .name = "spi4", + .parent = &pll1_aux_clk, + .lpsc = DM365_LPSC_SPI4, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_GPIO, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_AEMIF, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM2, +}; + +static struct clk pwm3_clk = { + .name = "pwm3", + .parent = &ref_clk, + .lpsc = DM365_LPSC_PWM3, +}; + +static struct clk timer0_clk = { + .name = "timer0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER0, +}; + +static struct clk timer1_clk = { + .name = "timer1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER1, +}; + +static struct clk timer2_clk = { + .name = "timer2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER2, + .usecount = 1, +}; + +static struct clk timer3_clk = { + .name = "timer3", + .parent = &pll1_aux_clk, + .lpsc = DM365_LPSC_TIMER3, +}; + +static struct clk usb_clk = { + .name = "usb", + .parent = &pll2_sysclk1, + .lpsc = DAVINCI_LPSC_USB, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_EMAC, +}; + +static struct clk voicecodec_clk = { + .name = "voice_codec", + .parent = &pll2_sysclk4, + .lpsc = DM365_LPSC_VOICE_CODEC, +}; + +static struct clk asp0_clk = { + .name = "asp0", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_McBSP1, +}; + +static struct clk rto_clk = { + .name = "rto", + .parent = &pll1_sysclk4, + .lpsc = DM365_LPSC_RTO, +}; + +static struct clk mjcp_clk = { + .name = "mjcp", + .parent = &pll1_sysclk3, + .lpsc = DM365_LPSC_MJCP, +}; + +static struct davinci_clk dm365_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), + CLK(NULL, "clkout0", &clkout0_clk), + CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), + CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), + CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), + CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), + CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_aux", &pll2_aux_clk), + CLK(NULL, "clkout1", &clkout1_clk), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), + CLK(NULL, "pll2_sysclk3", &pll2_sysclk3), + CLK(NULL, "pll2_sysclk4", &pll2_sysclk4), + CLK(NULL, "pll2_sysclk5", &pll2_sysclk5), + CLK(NULL, "pll2_sysclk6", &pll2_sysclk6), + CLK(NULL, "pll2_sysclk7", &pll2_sysclk7), + CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), + CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), + CLK(NULL, "vpss_dac", &vpss_dac_clk), + CLK(NULL, "vpss_master", &vpss_master_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK("i2c_davinci.1", NULL, &i2c_clk), + CLK("davinci_mmc.0", NULL, &mmcsd0_clk), + CLK("davinci_mmc.1", NULL, &mmcsd1_clk), + CLK("spi_davinci.0", NULL, &spi0_clk), + CLK("spi_davinci.1", NULL, &spi1_clk), + CLK("spi_davinci.2", NULL, &spi2_clk), + CLK("spi_davinci.3", NULL, &spi3_clk), + CLK("spi_davinci.4", NULL, &spi4_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK(NULL, "pwm3", &pwm3_clk), + CLK(NULL, "timer0", &timer0_clk), + CLK(NULL, "timer1", &timer1_clk), + CLK("watchdog", NULL, &timer2_clk), + CLK(NULL, "timer3", &timer3_clk), + CLK(NULL, "usb", &usb_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK("voice_codec", NULL, &voicecodec_clk), + CLK("soc-audio.0", NULL, &asp0_clk), + CLK(NULL, "rto", &rto_clk), + CLK(NULL, "mjcp", &mjcp_clk), + CLK(NULL, NULL, NULL), +}; + +/*----------------------------------------------------------------------*/ + +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + + +static const struct mux_config dm365_pins[] = { +#ifdef CONFIG_DAVINCI_MUX +MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) + +MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) +MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) +MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) +MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) +MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) +MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) + +MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) +MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) + +MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false) +MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) +MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) +MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) +MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) + +MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) +MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) +MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) +MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) +MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) +MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) + +MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) +MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) +MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) +MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) +MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) + +MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) +MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) +MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) +MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) +MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) +MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) + +MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) +MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) +MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) +MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) +MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) +MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) +MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) +MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) +MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) +MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) +MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) + +MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false) + +MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) +MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) +MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) +MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) +MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) +MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) +MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) +MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) +MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) +MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) +MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) +MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) + +MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) +MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) +MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) +MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) +MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) + +MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) +MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) +MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) +MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) +MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) + +MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) +MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) +MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) +MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) +MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) + +MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) +MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) +MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) +MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) +MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) + +MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) +MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) +MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) + +MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) +MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) +MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) +MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) +MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) +MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) +MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) +MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) +MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) +MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) + +INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) +INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) +INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) +INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) +INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) +INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) +INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) +INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) +INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) +INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) +INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) +INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) +INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) +INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) +INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) +#endif +}; + +static struct emac_platform_data dm365_emac_pdata = { + .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, + .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, + .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, + .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET, + .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, + .version = EMAC_VERSION_2, +}; + +static struct resource dm365_emac_resources[] = { + { + .start = DM365_EMAC_BASE, + .end = DM365_EMAC_BASE + 0x47ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DM365_EMAC_RXTHRESH, + .end = IRQ_DM365_EMAC_RXTHRESH, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM365_EMAC_RXPULSE, + .end = IRQ_DM365_EMAC_RXPULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM365_EMAC_TXPULSE, + .end = IRQ_DM365_EMAC_TXPULSE, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM365_EMAC_MISCPULSE, + .end = IRQ_DM365_EMAC_MISCPULSE, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dm365_emac_device = { + .name = "davinci_emac", + .id = 1, + .dev = { + .platform_data = &dm365_emac_pdata, + }, + .num_resources = ARRAY_SIZE(dm365_emac_resources), + .resource = dm365_emac_resources, +}; + +static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_VDINT0] = 2, + [IRQ_VDINT1] = 6, + [IRQ_VDINT2] = 6, + [IRQ_HISTINT] = 6, + [IRQ_H3AINT] = 6, + [IRQ_PRVUINT] = 6, + [IRQ_RSZINT] = 6, + [IRQ_DM365_INSFINT] = 7, + [IRQ_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_DM365_IMCOPINT] = 4, + [IRQ_USBINT] = 4, + [IRQ_DM365_RTOINT] = 7, + [IRQ_DM365_TINT5] = 7, + [IRQ_DM365_TINT6] = 5, + [IRQ_CCINT0] = 5, + [IRQ_CCERRINT] = 5, + [IRQ_TCERRINT0] = 5, + [IRQ_TCERRINT] = 7, + [IRQ_PSCIN] = 4, + [IRQ_DM365_SPINT2_1] = 7, + [IRQ_DM365_TINT7] = 7, + [IRQ_DM365_SDIOINT0] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_DM365_MMCINT1] = 7, + [IRQ_DM365_PWMINT3] = 7, + [IRQ_DDRINT] = 4, + [IRQ_AEMIFINT] = 2, + [IRQ_DM365_SDIOINT1] = 2, + [IRQ_TINT0_TINT12] = 7, + [IRQ_TINT0_TINT34] = 7, + [IRQ_TINT1_TINT12] = 7, + [IRQ_TINT1_TINT34] = 7, + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 3, + [IRQ_PWMINT2] = 3, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM365_SPIINT0_0] = 3, + [IRQ_DM365_SPIINT3_0] = 3, + [IRQ_DM365_GPIO0] = 3, + [IRQ_DM365_GPIO1] = 7, + [IRQ_DM365_GPIO2] = 4, + [IRQ_DM365_GPIO3] = 4, + [IRQ_DM365_GPIO4] = 7, + [IRQ_DM365_GPIO5] = 7, + [IRQ_DM365_GPIO6] = 7, + [IRQ_DM365_GPIO7] = 7, + [IRQ_DM365_EMAC_RXTHRESH] = 7, + [IRQ_DM365_EMAC_RXPULSE] = 7, + [IRQ_DM365_EMAC_TXPULSE] = 7, + [IRQ_DM365_EMAC_MISCPULSE] = 7, + [IRQ_DM365_GPIO12] = 7, + [IRQ_DM365_GPIO13] = 7, + [IRQ_DM365_GPIO14] = 7, + [IRQ_DM365_GPIO15] = 7, + [IRQ_DM365_KEYINT] = 7, + [IRQ_DM365_TCERRINT2] = 7, + [IRQ_DM365_TCERRINT3] = 7, + [IRQ_DM365_EMUINT] = 7, +}; + +/* Four Transfer Controllers on DM365 */ +static const s8 +dm365_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, +}; + +static const s8 +dm365_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 7}, + {1, 7}, + {2, 7}, + {3, 0}, + {-1, -1}, +}; + +static struct edma_soc_info dm365_edma_info[] = { + { + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm365_queue_tc_mapping, + .queue_priority_mapping = dm365_queue_priority_mapping, + .default_queue = EVENTQ_2, + }, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc0", + .start = 0x01c00000, + .end = 0x01c00000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = 0x01c10000, + .end = 0x01c10000 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = 0x01c10400, + .end = 0x01c10400 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc2", + .start = 0x01c10800, + .end = 0x01c10800 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc3", + .start = 0x01c10c00, + .end = 0x01c10c00 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_CCERRINT, + .flags = IORESOURCE_IRQ, + }, + /* not using TC*_ERR */ +}; + +static struct platform_device dm365_edma_device = { + .name = "edma", + .id = 0, + .dev.platform_data = dm365_edma_info, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, +}; + +static struct map_desc dm365_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = SRAM_VIRT, + .pfn = __phys_to_pfn(0x00010000), + .length = SZ_32K, + /* MT_MEMORY_NONCACHED requires supersection alignment */ + .type = MT_DEVICE, + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id dm365_ids[] = { + { + .variant = 0x0, + .part_no = 0xb83e, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM365, + .name = "dm365_rev1.1", + }, + { + .variant = 0x8, + .part_no = 0xb83e, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM365, + .name = "dm365_rev1.2", + }, +}; + +static void __iomem *dm365_psc_bases[] = { + IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), +}; + +struct davinci_timer_info dm365_timer_info = { + .timers = davinci_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct plat_serial8250_port dm365_serial_platform_data[] = { + { + .mapbase = DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0 + }, +}; + +static struct platform_device dm365_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm365_serial_platform_data, + }, +}; + +static struct davinci_soc_info davinci_soc_info_dm365 = { + .io_desc = dm365_io_desc, + .io_desc_num = ARRAY_SIZE(dm365_io_desc), + .jtag_id_base = IO_ADDRESS(0x01c40028), + .ids = dm365_ids, + .ids_num = ARRAY_SIZE(dm365_ids), + .cpu_clks = dm365_clks, + .psc_bases = dm365_psc_bases, + .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), + .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_pins = dm365_pins, + .pinmux_pins_num = ARRAY_SIZE(dm365_pins), + .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_type = DAVINCI_INTC_TYPE_AINTC, + .intc_irq_prios = dm365_default_priorities, + .intc_irq_num = DAVINCI_N_AINTC_IRQ, + .timer_info = &dm365_timer_info, + .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_num = 104, + .gpio_irq = IRQ_DM365_GPIO0, + .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ + .serial_dev = &dm365_serial_device, + .emac_pdata = &dm365_emac_pdata, + .sram_dma = 0x00010000, + .sram_len = SZ_32K, +}; + +void __init dm365_init(void) +{ + davinci_common_init(&davinci_soc_info_dm365); +} + +static int __init dm365_init_devices(void) +{ + if (!cpu_is_davinci_dm365()) + return 0; + + davinci_cfg_reg(DM365_INT_EDMA_CC); + platform_device_register(&dm365_edma_device); + platform_device_register(&dm365_emac_device); + + return 0; +} +postcore_initcall(dm365_init_devices); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index fb5449b3c97..d6e0fa5a8d8 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -27,6 +27,7 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" @@ -303,7 +304,7 @@ struct davinci_clk dm644x_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK("palm_bk3710", NULL, &ide_clk), - CLK("soc-audio.0", NULL, &asp_clk), + CLK("davinci-asp", NULL, &asp_clk), CLK("davinci_mmc.0", NULL, &mmcsd_clk), CLK(NULL, "spi", &spi_clk), CLK(NULL, "gpio", &gpio_clk), @@ -484,17 +485,38 @@ static const s8 dma_chan_dm644x_no_event[] = { -1 }; -static struct edma_soc_info dm644x_edma_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .noevent = dma_chan_dm644x_no_event, +static const s8 +queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {-1, -1}, +}; + +static const s8 +queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 3}, + {1, 7}, + {-1, -1}, +}; + +static struct edma_soc_info dm644x_edma_info[] = { + { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .noevent = dma_chan_dm644x_no_event, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, + }, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -512,10 +534,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -524,12 +548,91 @@ static struct resource edma_resources[] = { static struct platform_device dm644x_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm644x_edma_info, + .id = 0, + .dev.platform_data = dm644x_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ +static struct resource dm644x_asp_resources[] = { + { + .start = DAVINCI_ASP0_BASE, + .end = DAVINCI_ASP0_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DAVINCI_DMA_ASP0_TX, + .end = DAVINCI_DMA_ASP0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DMA_ASP0_RX, + .end = DAVINCI_DMA_ASP0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm644x_asp_device = { + .name = "davinci-asp", + .id = -1, + .num_resources = ARRAY_SIZE(dm644x_asp_resources), + .resource = dm644x_asp_resources, +}; + +static struct resource dm644x_vpss_resources[] = { + { + /* VPSS Base address */ + .name = "vpss", + .start = 0x01c73400, + .end = 0x01c73400 + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_vpss_device = { + .name = "vpss", + .id = -1, + .dev.platform_data = "dm644x_vpss", + .num_resources = ARRAY_SIZE(dm644x_vpss_resources), + .resource = dm644x_vpss_resources, +}; + +static struct resource vpfe_resources[] = { + { + .start = IRQ_VDINT0, + .end = IRQ_VDINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_VDINT1, + .end = IRQ_VDINT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = 0x01c70400, + .end = 0x01c70400 + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); +static struct platform_device vpfe_capture_dev = { + .name = CAPTURE_DRV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(vpfe_resources), + .resource = vpfe_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void dm644x_set_vpfe_config(struct vpfe_config *cfg) +{ + vpfe_capture_dev.dev.platform_data = cfg; +} + /*----------------------------------------------------------------------*/ static struct map_desc dm644x_io_desc[] = { @@ -557,6 +660,13 @@ static struct davinci_id dm644x_ids[] = { .cpu_id = DAVINCI_CPU_ID_DM6446, .name = "dm6446", }, + { + .variant = 0x1, + .part_no = 0xb700, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM6446, + .name = "dm6446a", + }, }; static void __iomem *dm644x_psc_bases[] = { @@ -630,7 +740,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .intc_irq_prios = dm644x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm644x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), .gpio_num = 71, .gpio_irq = IRQ_GPIOBNK0, @@ -640,6 +749,13 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { .sram_len = SZ_16K, }; +void __init dm644x_init_asp(struct snd_platform_data *pdata) +{ + davinci_cfg_reg(DM644X_MCBSP); + dm644x_asp_device.dev.platform_data = pdata; + platform_device_register(&dm644x_asp_device); +} + void __init dm644x_init(void) { davinci_common_init(&davinci_soc_info_dm644x); @@ -652,6 +768,9 @@ static int __init dm644x_init_devices(void) platform_device_register(&dm644x_edma_device); platform_device_register(&dm644x_emac_device); + platform_device_register(&dm644x_vpss_device); + platform_device_register(&vpfe_capture_dev); + return 0; } postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 334f0711e0f..0976049c7b3 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -27,10 +27,20 @@ #include <mach/time.h> #include <mach/serial.h> #include <mach/common.h> +#include <mach/asp.h> #include "clock.h" #include "mux.h" +#define DAVINCI_VPIF_BASE (0x01C12000) +#define VDD3P3V_PWDN_OFFSET (0x48) +#define VSCLKDIS_OFFSET (0x6C) + +#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ + BIT_MASK(0)) +#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ + BIT_MASK(8)) + /* * Device specific clocks */ @@ -162,6 +172,41 @@ static struct clk arm_clk = { .flags = ALWAYS_ENABLED, }; +static struct clk edma_cc_clk = { + .name = "edma_cc", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPCC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc0_clk = { + .name = "edma_tc0", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc1_clk = { + .name = "edma_tc1", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc2_clk = { + .name = "edma_tc2", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC2, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc3_clk = { + .name = "edma_tc3", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC3, + .flags = ALWAYS_ENABLED, +}; + static struct clk uart0_clk = { .name = "uart0", .parent = &aux_clkin, @@ -192,6 +237,18 @@ static struct clk gpio_clk = { .lpsc = DM646X_LPSC_GPIO, }; +static struct clk mcasp0_clk = { + .name = "mcasp0", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_McASP0, +}; + +static struct clk mcasp1_clk = { + .name = "mcasp1", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_McASP1, +}; + static struct clk aemif_clk = { .name = "aemif", .parent = &pll1_sysclk3, @@ -237,6 +294,13 @@ static struct clk timer2_clk = { .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ }; + +static struct clk ide_clk = { + .name = "ide", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_ATA, +}; + static struct clk vpif0_clk = { .name = "vpif0", .parent = &ref_clk, @@ -269,11 +333,18 @@ struct davinci_clk dm646x_clks[] = { CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), CLK(NULL, "dsp", &dsp_clk), CLK(NULL, "arm", &arm_clk), + CLK(NULL, "edma_cc", &edma_cc_clk), + CLK(NULL, "edma_tc0", &edma_tc0_clk), + CLK(NULL, "edma_tc1", &edma_tc1_clk), + CLK(NULL, "edma_tc2", &edma_tc2_clk), + CLK(NULL, "edma_tc3", &edma_tc3_clk), CLK(NULL, "uart0", &uart0_clk), CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), CLK("i2c_davinci.1", NULL, &i2c_clk), CLK(NULL, "gpio", &gpio_clk), + CLK("davinci-mcasp.0", NULL, &mcasp0_clk), + CLK("davinci-mcasp.1", NULL, &mcasp1_clk), CLK(NULL, "aemif", &aemif_clk), CLK("davinci_emac.1", NULL, &emac_clk), CLK(NULL, "pwm0", &pwm0_clk), @@ -281,6 +352,7 @@ struct davinci_clk dm646x_clks[] = { CLK(NULL, "timer0", &timer0_clk), CLK(NULL, "timer1", &timer1_clk), CLK("watchdog", NULL, &timer2_clk), + CLK("palm_bk3710", NULL, &ide_clk), CLK(NULL, "vpif0", &vpif0_clk), CLK(NULL, "vpif1", &vpif1_clk), CLK(NULL, NULL, NULL), @@ -344,7 +416,7 @@ static struct platform_device dm646x_emac_device = { */ static const struct mux_config dm646x_pins[] = { #ifdef CONFIG_DAVINCI_MUX -MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) +MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) @@ -451,17 +523,43 @@ static const s8 dma_chan_dm646x_no_event[] = { -1 }; -static struct edma_soc_info dm646x_edma_info = { - .n_channel = 64, - .n_region = 6, /* 0-1, 4-7 */ - .n_slot = 512, - .n_tc = 4, - .noevent = dma_chan_dm646x_no_event, +/* Four Transfer Controllers on DM646x */ +static const s8 +dm646x_queue_tc_mapping[][2] = { + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, +}; + +static const s8 +dm646x_queue_priority_mapping[][2] = { + /* {event queue no, Priority} */ + {0, 4}, + {1, 0}, + {2, 5}, + {3, 1}, + {-1, -1}, +}; + +static struct edma_soc_info dm646x_edma_info[] = { + { + .n_channel = 64, + .n_region = 6, /* 0-1, 4-7 */ + .n_slot = 512, + .n_tc = 4, + .n_cc = 1, + .noevent = dma_chan_dm646x_no_event, + .queue_tc_mapping = dm646x_queue_tc_mapping, + .queue_priority_mapping = dm646x_queue_priority_mapping, + }, }; static struct resource edma_resources[] = { { - .name = "edma_cc", + .name = "edma_cc0", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, @@ -491,10 +589,12 @@ static struct resource edma_resources[] = { .flags = IORESOURCE_MEM, }, { + .name = "edma0", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { + .name = "edma0_err", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -503,12 +603,167 @@ static struct resource edma_resources[] = { static struct platform_device dm646x_edma_device = { .name = "edma", - .id = -1, - .dev.platform_data = &dm646x_edma_info, + .id = 0, + .dev.platform_data = dm646x_edma_info, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; +static struct resource ide_resources[] = { + { + .start = DM646X_ATA_REG_BASE, + .end = DM646X_ATA_REG_BASE + 0x7ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DM646X_IDE, + .end = IRQ_DM646X_IDE, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ide_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device ide_dev = { + .name = "palm_bk3710", + .id = -1, + .resource = ide_resources, + .num_resources = ARRAY_SIZE(ide_resources), + .dev = { + .dma_mask = &ide_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm646x_mcasp0_resources[] = { + { + .name = "mcasp0", + .start = DAVINCI_DM646X_MCASP0_REG_BASE, + .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, + .flags = IORESOURCE_MEM, + }, + /* first TX, then RX */ + { + .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, + .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, + .flags = IORESOURCE_DMA, + }, + { + .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, + .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource dm646x_mcasp1_resources[] = { + { + .name = "mcasp1", + .start = DAVINCI_DM646X_MCASP1_REG_BASE, + .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, + .flags = IORESOURCE_MEM, + }, + /* DIT mode, only TX event */ + { + .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, + .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, + .flags = IORESOURCE_DMA, + }, + /* DIT mode, dummy entry */ + { + .start = -1, + .end = -1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device dm646x_mcasp0_device = { + .name = "davinci-mcasp", + .id = 0, + .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), + .resource = dm646x_mcasp0_resources, +}; + +static struct platform_device dm646x_mcasp1_device = { + .name = "davinci-mcasp", + .id = 1, + .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), + .resource = dm646x_mcasp1_resources, +}; + +static struct platform_device dm646x_dit_device = { + .name = "spdif-dit", + .id = -1, +}; + +static u64 vpif_dma_mask = DMA_BIT_MASK(32); + +static struct resource vpif_resource[] = { + { + .start = DAVINCI_VPIF_BASE, + .end = DAVINCI_VPIF_BASE + 0x03ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device vpif_dev = { + .name = "vpif", + .id = -1, + .dev = { + .dma_mask = &vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = vpif_resource, + .num_resources = ARRAY_SIZE(vpif_resource), +}; + +static struct resource vpif_display_resource[] = { + { + .start = IRQ_DM646X_VP_VERTINT2, + .end = IRQ_DM646X_VP_VERTINT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_VP_VERTINT3, + .end = IRQ_DM646X_VP_VERTINT3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vpif_display_dev = { + .name = "vpif_display", + .id = -1, + .dev = { + .dma_mask = &vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = vpif_display_resource, + .num_resources = ARRAY_SIZE(vpif_display_resource), +}; + +static struct resource vpif_capture_resource[] = { + { + .start = IRQ_DM646X_VP_VERTINT0, + .end = IRQ_DM646X_VP_VERTINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_VP_VERTINT1, + .end = IRQ_DM646X_VP_VERTINT1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device vpif_capture_dev = { + .name = "vpif_capture", + .id = -1, + .dev = { + .dma_mask = &vpif_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = vpif_capture_resource, + .num_resources = ARRAY_SIZE(vpif_capture_resource), +}; + /*----------------------------------------------------------------------*/ static struct map_desc dm646x_io_desc[] = { @@ -609,7 +864,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { .intc_irq_prios = dm646x_default_priorities, .intc_irq_num = DAVINCI_N_AINTC_IRQ, .timer_info = &dm646x_timer_info, - .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), .gpio_num = 43, /* Only 33 usable */ .gpio_irq = IRQ_DM646X_GPIOBNK0, @@ -619,6 +873,51 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { .sram_len = SZ_32K, }; +void __init dm646x_init_ide() +{ + davinci_cfg_reg(DM646X_ATAEN); + platform_device_register(&ide_dev); +} + +void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) +{ + dm646x_mcasp0_device.dev.platform_data = pdata; + platform_device_register(&dm646x_mcasp0_device); +} + +void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) +{ + dm646x_mcasp1_device.dev.platform_data = pdata; + platform_device_register(&dm646x_mcasp1_device); + platform_device_register(&dm646x_dit_device); +} + +void dm646x_setup_vpif(struct vpif_display_config *display_config, + struct vpif_capture_config *capture_config) +{ + unsigned int value; + void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); + + value = __raw_readl(base + VSCLKDIS_OFFSET); + value &= ~VSCLKDIS_MASK; + __raw_writel(value, base + VSCLKDIS_OFFSET); + + value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); + value &= ~VDD3P3V_VID_MASK; + __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); + + davinci_cfg_reg(DM646X_STSOMUX_DISABLE); + davinci_cfg_reg(DM646X_STSIMUX_DISABLE); + davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); + davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); + + vpif_display_dev.dev.platform_data = display_config; + vpif_capture_dev.dev.platform_data = capture_config; + platform_device_register(&vpif_dev); + platform_device_register(&vpif_display_dev); + platform_device_register(&vpif_capture_dev); +} + void __init dm646x_init(void) { davinci_common_init(&davinci_soc_info_dm646x); diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 15e9eb158bb..f2e57d27295 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -100,132 +100,158 @@ #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ #define EDMA_PARM 0x4000 /* 128 param entries */ -#define DAVINCI_DMA_3PCC_BASE 0x01C00000 - #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) +#define EDMA_DCHMAP 0x0100 /* 64 registers */ +#define CHMAP_EXIST BIT(24) + #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_MAX_EVQUE 2 /* FIXME too small */ +#define EDMA_MAX_CC 2 /*****************************************************************************/ -static void __iomem *edmacc_regs_base; +static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; -static inline unsigned int edma_read(int offset) +static inline unsigned int edma_read(unsigned ctlr, int offset) { - return (unsigned int)__raw_readl(edmacc_regs_base + offset); + return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); } -static inline void edma_write(int offset, int val) +static inline void edma_write(unsigned ctlr, int offset, int val) { - __raw_writel(val, edmacc_regs_base + offset); + __raw_writel(val, edmacc_regs_base[ctlr] + offset); } -static inline void edma_modify(int offset, unsigned and, unsigned or) +static inline void edma_modify(unsigned ctlr, int offset, unsigned and, + unsigned or) { - unsigned val = edma_read(offset); + unsigned val = edma_read(ctlr, offset); val &= and; val |= or; - edma_write(offset, val); + edma_write(ctlr, offset, val); } -static inline void edma_and(int offset, unsigned and) +static inline void edma_and(unsigned ctlr, int offset, unsigned and) { - unsigned val = edma_read(offset); + unsigned val = edma_read(ctlr, offset); val &= and; - edma_write(offset, val); + edma_write(ctlr, offset, val); } -static inline void edma_or(int offset, unsigned or) +static inline void edma_or(unsigned ctlr, int offset, unsigned or) { - unsigned val = edma_read(offset); + unsigned val = edma_read(ctlr, offset); val |= or; - edma_write(offset, val); + edma_write(ctlr, offset, val); } -static inline unsigned int edma_read_array(int offset, int i) +static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) { - return edma_read(offset + (i << 2)); + return edma_read(ctlr, offset + (i << 2)); } -static inline void edma_write_array(int offset, int i, unsigned val) +static inline void edma_write_array(unsigned ctlr, int offset, int i, + unsigned val) { - edma_write(offset + (i << 2), val); + edma_write(ctlr, offset + (i << 2), val); } -static inline void edma_modify_array(int offset, int i, +static inline void edma_modify_array(unsigned ctlr, int offset, int i, unsigned and, unsigned or) { - edma_modify(offset + (i << 2), and, or); + edma_modify(ctlr, offset + (i << 2), and, or); } -static inline void edma_or_array(int offset, int i, unsigned or) +static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) { - edma_or(offset + (i << 2), or); + edma_or(ctlr, offset + (i << 2), or); } -static inline void edma_or_array2(int offset, int i, int j, unsigned or) +static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, + unsigned or) { - edma_or(offset + ((i*2 + j) << 2), or); + edma_or(ctlr, offset + ((i*2 + j) << 2), or); } -static inline void edma_write_array2(int offset, int i, int j, unsigned val) +static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, + unsigned val) { - edma_write(offset + ((i*2 + j) << 2), val); + edma_write(ctlr, offset + ((i*2 + j) << 2), val); } -static inline unsigned int edma_shadow0_read(int offset) +static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) { - return edma_read(EDMA_SHADOW0 + offset); + return edma_read(ctlr, EDMA_SHADOW0 + offset); } -static inline unsigned int edma_shadow0_read_array(int offset, int i) +static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, + int i) { - return edma_read(EDMA_SHADOW0 + offset + (i << 2)); + return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); } -static inline void edma_shadow0_write(int offset, unsigned val) +static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) { - edma_write(EDMA_SHADOW0 + offset, val); + edma_write(ctlr, EDMA_SHADOW0 + offset, val); } -static inline void edma_shadow0_write_array(int offset, int i, unsigned val) +static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, + unsigned val) { - edma_write(EDMA_SHADOW0 + offset + (i << 2), val); + edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); } -static inline unsigned int edma_parm_read(int offset, int param_no) +static inline unsigned int edma_parm_read(unsigned ctlr, int offset, + int param_no) { - return edma_read(EDMA_PARM + offset + (param_no << 5)); + return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); } -static inline void edma_parm_write(int offset, int param_no, unsigned val) +static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, + unsigned val) { - edma_write(EDMA_PARM + offset + (param_no << 5), val); + edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); } -static inline void edma_parm_modify(int offset, int param_no, +static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, unsigned and, unsigned or) { - edma_modify(EDMA_PARM + offset + (param_no << 5), and, or); + edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); } -static inline void edma_parm_and(int offset, int param_no, unsigned and) +static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, + unsigned and) { - edma_and(EDMA_PARM + offset + (param_no << 5), and); + edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); } -static inline void edma_parm_or(int offset, int param_no, unsigned or) +static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, + unsigned or) { - edma_or(EDMA_PARM + offset + (param_no << 5), or); + edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); } /*****************************************************************************/ /* actual number of DMA channels and slots on this silicon */ -static unsigned num_channels; -static unsigned num_slots; +struct edma { + /* how many dma resources of each type */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + unsigned num_cc; + enum dma_event_q default_queue; + + /* list of channels with no even trigger; terminated by "-1" */ + const s8 *noevent; + + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); -static struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; -} intr_data[EDMA_MAX_DMACH]; + /* The edma_noevent bit for each channel is clear unless + * it doesn't trigger DMA events on this platform. It uses a + * bit of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); -/* The edma_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. - */ -static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + unsigned irq_res_start; + unsigned irq_res_end; -/* The edma_noevent bit for each channel is clear unless - * it doesn't trigger DMA events on this platform. It uses a - * bit of SOC-specific initialization code. - */ -static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_MAX_DMACH]; +}; + +static struct edma *edma_info[EDMA_MAX_CC]; /* dummy param set used to (re)initialize parameter RAM slots */ static const struct edmacc_param dummy_paramset = { @@ -233,47 +259,52 @@ static const struct edmacc_param dummy_paramset = { .ccnt = 1, }; -static const int __initconst -queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = { -/* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {-1, -1} -}; - -static const int __initconst -queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = { - /* {event queue no, Priority} */ - {0, 3}, - {1, 7}, - {-1, -1} -}; - /*****************************************************************************/ -static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no) +static void map_dmach_queue(unsigned ctlr, unsigned ch_no, + enum dma_event_q queue_no) { int bit = (ch_no & 0x7) * 4; /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) - queue_no = EVENTQ_1; + queue_no = edma_info[ctlr]->default_queue; queue_no &= 7; - edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3), + edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit), queue_no << bit); } -static void __init map_queue_tc(int queue_no, int tc_no) +static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) { int bit = queue_no * 4; - edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); + edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); } -static void __init assign_priority_to_queue(int queue_no, int priority) +static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, + int priority) { int bit = queue_no * 4; - edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); + edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), + ((priority & 0x7) << bit)); +} + +/** + * map_dmach_param - Maps channel number to param entry number + * + * This maps the dma channel number to param entry numberter. In + * other words using the DMA channel mapping registers a param entry + * can be mapped to any channel + * + * Callers are responsible for ensuring the channel mapping logic is + * included in that particular EDMA variant (Eg : dm646x) + * + */ +static void __init map_dmach_param(unsigned ctlr) +{ + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); } static inline void @@ -281,22 +312,39 @@ setup_dma_interrupt(unsigned lch, void (*callback)(unsigned channel, u16 ch_status, void *data), void *data) { + unsigned ctlr; + + ctlr = EDMA_CTLR(lch); + lch = EDMA_CHAN_SLOT(lch); + if (!callback) { - edma_shadow0_write_array(SH_IECR, lch >> 5, + edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, (1 << (lch & 0x1f))); } - intr_data[lch].callback = callback; - intr_data[lch].data = data; + edma_info[ctlr]->intr_data[lch].callback = callback; + edma_info[ctlr]->intr_data[lch].data = data; if (callback) { - edma_shadow0_write_array(SH_ICR, lch >> 5, + edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, (1 << (lch & 0x1f))); - edma_shadow0_write_array(SH_IESR, lch >> 5, + edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, (1 << (lch & 0x1f))); } } +static int irq2ctlr(int irq) +{ + if (irq >= edma_info[0]->irq_res_start && + irq <= edma_info[0]->irq_res_end) + return 0; + else if (irq >= edma_info[1]->irq_res_start && + irq <= edma_info[1]->irq_res_end) + return 1; + + return -1; +} + /****************************************************************************** * * DMA interrupt handler @@ -305,32 +353,39 @@ setup_dma_interrupt(unsigned lch, static irqreturn_t dma_irq_handler(int irq, void *data) { int i; + unsigned ctlr; unsigned int cnt = 0; + ctlr = irq2ctlr(irq); + dev_dbg(data, "dma_irq_handler\n"); - if ((edma_shadow0_read_array(SH_IPR, 0) == 0) - && (edma_shadow0_read_array(SH_IPR, 1) == 0)) + if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) + && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) return IRQ_NONE; while (1) { int j; - if (edma_shadow0_read_array(SH_IPR, 0)) + if (edma_shadow0_read_array(ctlr, SH_IPR, 0)) j = 0; - else if (edma_shadow0_read_array(SH_IPR, 1)) + else if (edma_shadow0_read_array(ctlr, SH_IPR, 1)) j = 1; else break; dev_dbg(data, "IPR%d %08x\n", j, - edma_shadow0_read_array(SH_IPR, j)); + edma_shadow0_read_array(ctlr, SH_IPR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; - if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) { + if (edma_shadow0_read_array(ctlr, SH_IPR, j) & + (1 << i)) { /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(SH_ICR, j, (1 << i)); - if (intr_data[k].callback) { - intr_data[k].callback(k, DMA_COMPLETE, - intr_data[k].data); + edma_shadow0_write_array(ctlr, SH_ICR, j, + (1 << i)); + if (edma_info[ctlr]->intr_data[k].callback) { + edma_info[ctlr]->intr_data[k].callback( + k, DMA_COMPLETE, + edma_info[ctlr]->intr_data[k]. + data); } } } @@ -338,7 +393,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) if (cnt > 10) break; } - edma_shadow0_write(SH_IEVAL, 1); + edma_shadow0_write(ctlr, SH_IEVAL, 1); return IRQ_HANDLED; } @@ -350,78 +405,87 @@ static irqreturn_t dma_irq_handler(int irq, void *data) static irqreturn_t dma_ccerr_handler(int irq, void *data) { int i; + unsigned ctlr; unsigned int cnt = 0; + ctlr = irq2ctlr(irq); + dev_dbg(data, "dma_ccerr_handler\n"); - if ((edma_read_array(EDMA_EMR, 0) == 0) && - (edma_read_array(EDMA_EMR, 1) == 0) && - (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0)) + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) return IRQ_NONE; while (1) { int j = -1; - if (edma_read_array(EDMA_EMR, 0)) + if (edma_read_array(ctlr, EDMA_EMR, 0)) j = 0; - else if (edma_read_array(EDMA_EMR, 1)) + else if (edma_read_array(ctlr, EDMA_EMR, 1)) j = 1; if (j >= 0) { dev_dbg(data, "EMR%d %08x\n", j, - edma_read_array(EDMA_EMR, j)); + edma_read_array(ctlr, EDMA_EMR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; - if (edma_read_array(EDMA_EMR, j) & (1 << i)) { + if (edma_read_array(ctlr, EDMA_EMR, j) & + (1 << i)) { /* Clear the corresponding EMR bits */ - edma_write_array(EDMA_EMCR, j, 1 << i); + edma_write_array(ctlr, EDMA_EMCR, j, + 1 << i); /* Clear any SER */ - edma_shadow0_write_array(SH_SECR, j, - (1 << i)); - if (intr_data[k].callback) { - intr_data[k].callback(k, - DMA_CC_ERROR, - intr_data - [k].data); + edma_shadow0_write_array(ctlr, SH_SECR, + j, (1 << i)); + if (edma_info[ctlr]->intr_data[k]. + callback) { + edma_info[ctlr]->intr_data[k]. + callback(k, + DMA_CC_ERROR, + edma_info[ctlr]->intr_data + [k].data); } } } - } else if (edma_read(EDMA_QEMR)) { + } else if (edma_read(ctlr, EDMA_QEMR)) { dev_dbg(data, "QEMR %02x\n", - edma_read(EDMA_QEMR)); + edma_read(ctlr, EDMA_QEMR)); for (i = 0; i < 8; i++) { - if (edma_read(EDMA_QEMR) & (1 << i)) { + if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) { /* Clear the corresponding IPR bits */ - edma_write(EDMA_QEMCR, 1 << i); - edma_shadow0_write(SH_QSECR, (1 << i)); + edma_write(ctlr, EDMA_QEMCR, 1 << i); + edma_shadow0_write(ctlr, SH_QSECR, + (1 << i)); /* NOTE: not reported!! */ } } - } else if (edma_read(EDMA_CCERR)) { + } else if (edma_read(ctlr, EDMA_CCERR)) { dev_dbg(data, "CCERR %08x\n", - edma_read(EDMA_CCERR)); + edma_read(ctlr, EDMA_CCERR)); /* FIXME: CCERR.BIT(16) ignored! much better * to just write CCERRCLR with CCERR value... */ for (i = 0; i < 8; i++) { - if (edma_read(EDMA_CCERR) & (1 << i)) { + if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) { /* Clear the corresponding IPR bits */ - edma_write(EDMA_CCERRCLR, 1 << i); + edma_write(ctlr, EDMA_CCERRCLR, 1 << i); /* NOTE: not reported!! */ } } } - if ((edma_read_array(EDMA_EMR, 0) == 0) - && (edma_read_array(EDMA_EMR, 1) == 0) - && (edma_read(EDMA_QEMR) == 0) - && (edma_read(EDMA_CCERR) == 0)) { + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) + && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) + && (edma_read(ctlr, EDMA_QEMR) == 0) + && (edma_read(ctlr, EDMA_CCERR) == 0)) { break; } cnt++; if (cnt > 10) break; } - edma_write(EDMA_EEVAL, 1); + edma_write(ctlr, EDMA_EEVAL, 1); return IRQ_HANDLED; } @@ -445,6 +509,45 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data) return IRQ_HANDLED; } +static int reserve_contiguous_params(int ctlr, unsigned int id, + unsigned int num_params, + unsigned int start_param) +{ + int i, j; + unsigned int count = num_params; + + for (i = start_param; i < edma_info[ctlr]->num_slots; ++i) { + j = EDMA_CHAN_SLOT(i); + if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) + count--; + if (count == 0) + break; + else if (id == EDMA_CONT_PARAMS_FIXED_EXACT) + break; + else + count = num_params; + } + + /* + * We have to clear any bits that we set + * if we run out parameter RAMs, i.e we do find a set + * of contiguous parameter RAMs but do not find the exact number + * requested as we may reach the total number of parameter RAMs + */ + if (count) { + for (j = i - num_params + count + 1; j <= i ; ++j) + clear_bit(j, edma_info[ctlr]->edma_inuse); + + return -EBUSY; + } + + for (j = i - num_params + 1; j <= i; ++j) + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), + &dummy_paramset, PARM_SIZE); + + return EDMA_CTLR_CHAN(ctlr, i - num_params + 1); +} + /*-----------------------------------------------------------------------*/ /* Resource alloc/free: dma channels, parameter RAM slots */ @@ -484,35 +587,53 @@ int edma_alloc_channel(int channel, void *data, enum dma_event_q eventq_no) { + unsigned i, done, ctlr = 0; + + if (channel >= 0) { + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + } + if (channel < 0) { - channel = 0; - for (;;) { - channel = find_next_bit(edma_noevent, - num_channels, channel); - if (channel == num_channels) - return -ENOMEM; - if (!test_and_set_bit(channel, edma_inuse)) + for (i = 0; i < EDMA_MAX_CC; i++) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_info[i]-> + edma_noevent, + edma_info[i]->num_channels, + channel); + if (channel == edma_info[i]->num_channels) + return -ENOMEM; + if (!test_and_set_bit(channel, + edma_info[i]->edma_inuse)) { + done = 1; + ctlr = i; + break; + } + channel++; + } + if (done) break; - channel++; } - } else if (channel >= num_channels) { + } else if (channel >= edma_info[ctlr]->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, edma_inuse)) { + } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { return -EBUSY; } /* ensure access through shadow region 0 */ - edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); + edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); /* ensure no events are pending */ - edma_stop(channel); - memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); if (callback) - setup_dma_interrupt(channel, callback, data); + setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), + callback, data); - map_dmach_queue(channel, eventq_no); + map_dmach_queue(ctlr, channel, eventq_no); return channel; } @@ -532,15 +653,20 @@ EXPORT_SYMBOL(edma_alloc_channel); */ void edma_free_channel(unsigned channel) { - if (channel >= num_channels) + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= edma_info[ctlr]->num_channels) return; setup_dma_interrupt(channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel), + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_inuse); + clear_bit(channel, edma_info[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_channel); @@ -558,28 +684,33 @@ EXPORT_SYMBOL(edma_free_channel); * * Returns the number of the slot, else negative errno. */ -int edma_alloc_slot(int slot) +int edma_alloc_slot(unsigned ctlr, int slot) { + if (slot >= 0) + slot = EDMA_CHAN_SLOT(slot); + if (slot < 0) { - slot = num_channels; + slot = edma_info[ctlr]->num_channels; for (;;) { - slot = find_next_zero_bit(edma_inuse, - num_slots, slot); - if (slot == num_slots) + slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, + edma_info[ctlr]->num_slots, slot); + if (slot == edma_info[ctlr]->num_slots) return -ENOMEM; - if (!test_and_set_bit(slot, edma_inuse)) + if (!test_and_set_bit(slot, + edma_info[ctlr]->edma_inuse)) break; } - } else if (slot < num_channels || slot >= num_slots) { + } else if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots) { return -EINVAL; - } else if (test_and_set_bit(slot, edma_inuse)) { + } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { return -EBUSY; } - memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - return slot; + return EDMA_CTLR_CHAN(ctlr, slot); } EXPORT_SYMBOL(edma_alloc_slot); @@ -593,15 +724,119 @@ EXPORT_SYMBOL(edma_alloc_slot); */ void edma_free_slot(unsigned slot) { - if (slot < num_channels || slot >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots) return; - memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - clear_bit(slot, edma_inuse); + clear_bit(slot, edma_info[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_slot); + +/** + * edma_alloc_cont_slots- alloc contiguous parameter RAM slots + * The API will return the starting point of a set of + * contiguous PARAM's that have been requested + * + * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT + * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT + * @count: number of contiguous Paramter RAM's + * @param - the start value of Parameter RAM that should be passed if id + * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT + * + * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of + * contiguous Parameter RAMs from parameter RAM 64 in the case of DaVinci SOCs + * and 32 in the case of Primus + * + * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a + * set of contiguous parameter RAMs from the "param" that is passed as an + * argument to the API. + * + * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries + * starts looking for a set of contiguous parameter RAMs from the "param" + * that is passed as an argument to the API. On failure the API will try to + * find a set of contiguous Parameter RAMs in the remaining Parameter RAMs + */ +int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) +{ + /* + * The start slot requested should be greater than + * the number of channels and lesser than the total number + * of slots + */ + if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots) + return -EINVAL; + + /* + * The number of parameter RAMs requested cannot be less than 1 + * and cannot be more than the number of slots minus the number of + * channels + */ + if (count < 1 || count > + (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) + return -EINVAL; + + switch (id) { + case EDMA_CONT_PARAMS_ANY: + return reserve_contiguous_params(ctlr, id, count, + edma_info[ctlr]->num_channels); + case EDMA_CONT_PARAMS_FIXED_EXACT: + case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: + return reserve_contiguous_params(ctlr, id, count, slot); + default: + return -EINVAL; + } + +} +EXPORT_SYMBOL(edma_alloc_cont_slots); + +/** + * edma_free_cont_slots - deallocate DMA parameter RAMs + * @slot: first parameter RAM of a set of parameter RAMs to be freed + * @count: the number of contiguous parameter RAMs to be freed + * + * This deallocates the parameter RAM slots allocated by + * edma_alloc_cont_slots. + * Callers/applications need to keep track of sets of contiguous + * parameter RAMs that have been allocated using the edma_alloc_cont_slots + * API. + * Callers are responsible for ensuring the slots are inactive, and will + * not be activated. + */ +int edma_free_cont_slots(unsigned slot, int count) +{ + unsigned ctlr; + int i; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_channels || + slot >= edma_info[ctlr]->num_slots || + count < 1) + return -EINVAL; + + for (i = slot; i < slot + count; ++i) { + ctlr = EDMA_CTLR(i); + slot = EDMA_CHAN_SLOT(i); + + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_info[ctlr]->edma_inuse); + } + + return 0; +} +EXPORT_SYMBOL(edma_free_cont_slots); + /*-----------------------------------------------------------------------*/ /* Parameter RAM operations (i) -- read/write partial slots */ @@ -620,8 +855,13 @@ EXPORT_SYMBOL(edma_free_slot); void edma_set_src(unsigned slot, dma_addr_t src_port, enum address_mode mode, enum fifo_width width) { - if (slot < num_slots) { - unsigned int i = edma_parm_read(PARM_OPT, slot); + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); if (mode) { /* set SAM and program FWID */ @@ -630,11 +870,11 @@ void edma_set_src(unsigned slot, dma_addr_t src_port, /* clear SAM */ i &= ~SAM; } - edma_parm_write(PARM_OPT, slot, i); + edma_parm_write(ctlr, PARM_OPT, slot, i); /* set the source port address in source register of param structure */ - edma_parm_write(PARM_SRC, slot, src_port); + edma_parm_write(ctlr, PARM_SRC, slot, src_port); } } EXPORT_SYMBOL(edma_set_src); @@ -653,8 +893,13 @@ EXPORT_SYMBOL(edma_set_src); void edma_set_dest(unsigned slot, dma_addr_t dest_port, enum address_mode mode, enum fifo_width width) { - if (slot < num_slots) { - unsigned int i = edma_parm_read(PARM_OPT, slot); + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); if (mode) { /* set DAM and program FWID */ @@ -663,10 +908,10 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port, /* clear DAM */ i &= ~DAM; } - edma_parm_write(PARM_OPT, slot, i); + edma_parm_write(ctlr, PARM_OPT, slot, i); /* set the destination port address in dest register of param structure */ - edma_parm_write(PARM_DST, slot, dest_port); + edma_parm_write(ctlr, PARM_DST, slot, dest_port); } } EXPORT_SYMBOL(edma_set_dest); @@ -683,8 +928,12 @@ EXPORT_SYMBOL(edma_set_dest); void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) { struct edmacc_param temp; + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - edma_read_slot(slot, &temp); + edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); if (src != NULL) *src = temp.src; if (dst != NULL) @@ -704,10 +953,15 @@ EXPORT_SYMBOL(edma_get_position); */ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) { - if (slot < num_slots) { - edma_parm_modify(PARM_SRC_DST_BIDX, slot, + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 0xffff0000, src_bidx); - edma_parm_modify(PARM_SRC_DST_CIDX, slot, + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 0xffff0000, src_cidx); } } @@ -725,10 +979,15 @@ EXPORT_SYMBOL(edma_set_src_index); */ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) { - if (slot < num_slots) { - edma_parm_modify(PARM_SRC_DST_BIDX, slot, + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 0x0000ffff, dest_bidx << 16); - edma_parm_modify(PARM_SRC_DST_CIDX, slot, + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 0x0000ffff, dest_cidx << 16); } } @@ -767,16 +1026,21 @@ void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, u16 bcnt_rld, enum sync_dimension sync_mode) { - if (slot < num_slots) { - edma_parm_modify(PARM_LINK_BCNTRLD, slot, + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot < edma_info[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, 0x0000ffff, bcnt_rld << 16); if (sync_mode == ASYNC) - edma_parm_and(PARM_OPT, slot, ~SYNCDIM); + edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); else - edma_parm_or(PARM_OPT, slot, SYNCDIM); + edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); /* Set the acount, bcount, ccount registers */ - edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt); - edma_parm_write(PARM_CCNT, slot, ccnt); + edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); } } EXPORT_SYMBOL(edma_set_transfer_params); @@ -790,11 +1054,19 @@ EXPORT_SYMBOL(edma_set_transfer_params); */ void edma_link(unsigned from, unsigned to) { - if (from >= num_slots) + unsigned ctlr_from, ctlr_to; + + ctlr_from = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + ctlr_to = EDMA_CTLR(to); + to = EDMA_CHAN_SLOT(to); + + if (from >= edma_info[ctlr_from]->num_slots) return; - if (to >= num_slots) + if (to >= edma_info[ctlr_to]->num_slots) return; - edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); + edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } EXPORT_SYMBOL(edma_link); @@ -807,9 +1079,14 @@ EXPORT_SYMBOL(edma_link); */ void edma_unlink(unsigned from) { - if (from >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + + if (from >= edma_info[ctlr]->num_slots) return; - edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff); + edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); } EXPORT_SYMBOL(edma_unlink); @@ -829,9 +1106,15 @@ EXPORT_SYMBOL(edma_unlink); */ void edma_write_slot(unsigned slot, const struct edmacc_param *param) { - if (slot >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot >= edma_info[ctlr]->num_slots) return; - memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE); + memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, + PARM_SIZE); } EXPORT_SYMBOL(edma_write_slot); @@ -845,9 +1128,15 @@ EXPORT_SYMBOL(edma_write_slot); */ void edma_read_slot(unsigned slot, struct edmacc_param *param) { - if (slot >= num_slots) + unsigned ctlr; + + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); + + if (slot >= edma_info[ctlr]->num_slots) return; - memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE); + memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), + PARM_SIZE); } EXPORT_SYMBOL(edma_read_slot); @@ -864,10 +1153,15 @@ EXPORT_SYMBOL(edma_read_slot); */ void edma_pause(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { unsigned int mask = (1 << (channel & 0x1f)); - edma_shadow0_write_array(SH_EECR, channel >> 5, mask); + edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); } } EXPORT_SYMBOL(edma_pause); @@ -880,10 +1174,15 @@ EXPORT_SYMBOL(edma_pause); */ void edma_resume(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { unsigned int mask = (1 << (channel & 0x1f)); - edma_shadow0_write_array(SH_EESR, channel >> 5, mask); + edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); } } EXPORT_SYMBOL(edma_resume); @@ -901,28 +1200,33 @@ EXPORT_SYMBOL(edma_resume); */ int edma_start(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { int j = channel >> 5; unsigned int mask = (1 << (channel & 0x1f)); /* EDMA channels without event association */ - if (test_bit(channel, edma_noevent)) { + if (test_bit(channel, edma_info[ctlr]->edma_noevent)) { pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(SH_ESR, j)); - edma_shadow0_write_array(SH_ESR, j, mask); + edma_shadow0_read_array(ctlr, SH_ESR, j)); + edma_shadow0_write_array(ctlr, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(SH_ER, j)); + edma_shadow0_read_array(ctlr, SH_ER, j)); /* Clear any pending error */ - edma_write_array(EDMA_EMCR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); /* Clear any SER */ - edma_shadow0_write_array(SH_SECR, j, mask); - edma_shadow0_write_array(SH_EESR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_shadow0_write_array(ctlr, SH_EESR, j, mask); pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(SH_EER, j)); + edma_shadow0_read_array(ctlr, SH_EER, j)); return 0; } @@ -941,17 +1245,22 @@ EXPORT_SYMBOL(edma_start); */ void edma_stop(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { int j = channel >> 5; unsigned int mask = (1 << (channel & 0x1f)); - edma_shadow0_write_array(SH_EECR, j, mask); - edma_shadow0_write_array(SH_ECR, j, mask); - edma_shadow0_write_array(SH_SECR, j, mask); - edma_write_array(EDMA_EMCR, j, mask); + edma_shadow0_write_array(ctlr, SH_EECR, j, mask); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(SH_EER, j)); + edma_shadow0_read_array(ctlr, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -975,18 +1284,23 @@ EXPORT_SYMBOL(edma_stop); void edma_clean_channel(unsigned channel) { - if (channel < num_channels) { + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel < edma_info[ctlr]->num_channels) { int j = (channel >> 5); unsigned int mask = 1 << (channel & 0x1f); pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(EDMA_EMR, j)); - edma_shadow0_write_array(SH_ECR, j, mask); + edma_read_array(ctlr, EDMA_EMR, j)); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ - edma_write_array(EDMA_EMCR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); /* Clear any SER */ - edma_shadow0_write_array(SH_SECR, j, mask); - edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3); } } EXPORT_SYMBOL(edma_clean_channel); @@ -998,12 +1312,17 @@ EXPORT_SYMBOL(edma_clean_channel); */ void edma_clear_event(unsigned channel) { - if (channel >= num_channels) + unsigned ctlr; + + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= edma_info[ctlr]->num_channels) return; if (channel < 32) - edma_write(EDMA_ECR, 1 << channel); + edma_write(ctlr, EDMA_ECR, 1 << channel); else - edma_write(EDMA_ECRH, 1 << (channel - 32)); + edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32)); } EXPORT_SYMBOL(edma_clear_event); @@ -1012,62 +1331,133 @@ EXPORT_SYMBOL(edma_clear_event); static int __init edma_probe(struct platform_device *pdev) { struct edma_soc_info *info = pdev->dev.platform_data; - int i; - int status; + const s8 (*queue_priority_mapping)[2]; + const s8 (*queue_tc_mapping)[2]; + int i, j, found = 0; + int status = -1; const s8 *noevent; - int irq = 0, err_irq = 0; - struct resource *r; - resource_size_t len; + int irq[EDMA_MAX_CC] = {0, 0}; + int err_irq[EDMA_MAX_CC] = {0, 0}; + struct resource *r[EDMA_MAX_CC] = {NULL}; + resource_size_t len[EDMA_MAX_CC]; + char res_name[10]; + char irq_name[10]; if (!info) return -ENODEV; - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc"); - if (!r) - return -ENODEV; + for (j = 0; j < EDMA_MAX_CC; j++) { + sprintf(res_name, "edma_cc%d", j); + r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, + res_name); + if (!r[j]) { + if (found) + break; + else + return -ENODEV; + } else + found = 1; + + len[j] = resource_size(r[j]); + + r[j] = request_mem_region(r[j]->start, len[j], + dev_name(&pdev->dev)); + if (!r[j]) { + status = -EBUSY; + goto fail1; + } - len = r->end - r->start + 1; + edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); + if (!edmacc_regs_base[j]) { + status = -EBUSY; + goto fail1; + } - r = request_mem_region(r->start, len, r->name); - if (!r) - return -EBUSY; + edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); + if (!edma_info[j]) { + status = -ENOMEM; + goto fail1; + } + memset(edma_info[j], 0, sizeof(struct edma)); + + edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, + EDMA_MAX_DMACH); + edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, + EDMA_MAX_PARAMENTRY); + edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, + EDMA_MAX_CC); + + edma_info[j]->default_queue = info[j].default_queue; + if (!edma_info[j]->default_queue) + edma_info[j]->default_queue = EVENTQ_1; + + dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", + edmacc_regs_base[j]); + + for (i = 0; i < edma_info[j]->num_slots; i++) + memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), + &dummy_paramset, PARM_SIZE); + + noevent = info[j].noevent; + if (noevent) { + while (*noevent != -1) + set_bit(*noevent++, edma_info[j]->edma_noevent); + } - edmacc_regs_base = ioremap(r->start, len); - if (!edmacc_regs_base) { - status = -EBUSY; - goto fail1; - } + sprintf(irq_name, "edma%d", j); + irq[j] = platform_get_irq_byname(pdev, irq_name); + edma_info[j]->irq_res_start = irq[j]; + status = request_irq(irq[j], dma_irq_handler, 0, "edma", + &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + irq[j], status); + goto fail; + } - num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH); - num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY); + sprintf(irq_name, "edma%d_err", j); + err_irq[j] = platform_get_irq_byname(pdev, irq_name); + edma_info[j]->irq_res_end = err_irq[j]; + status = request_irq(err_irq[j], dma_ccerr_handler, 0, + "edma_error", &pdev->dev); + if (status < 0) { + dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + err_irq[j], status); + goto fail; + } - dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base); + /* Everything lives on transfer controller 1 until otherwise + * specified. This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < edma_info[j]->num_channels; i++) + map_dmach_queue(j, i, EVENTQ_1); - for (i = 0; i < num_slots; i++) - memcpy_toio(edmacc_regs_base + PARM_OFFSET(i), - &dummy_paramset, PARM_SIZE); + queue_tc_mapping = info[j].queue_tc_mapping; + queue_priority_mapping = info[j].queue_priority_mapping; - noevent = info->noevent; - if (noevent) { - while (*noevent != -1) - set_bit(*noevent++, edma_noevent); - } + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(j, queue_tc_mapping[i][0], + queue_tc_mapping[i][1]); - irq = platform_get_irq(pdev, 0); - status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", - irq, status); - goto fail; - } + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(j, + queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic + * exist + */ + if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(j); - err_irq = platform_get_irq(pdev, 1); - status = request_irq(err_irq, dma_ccerr_handler, 0, - "edma_error", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", - err_irq, status); - goto fail; + for (i = 0; i < info[j].n_region; i++) { + edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); + edma_write_array(j, EDMA_QRAE, i, 0x0); + } } if (tc_errs_handled) { @@ -1087,38 +1477,23 @@ static int __init edma_probe(struct platform_device *pdev) } } - /* Everything lives on transfer controller 1 until otherwise specified. - * This way, long transfers on the low priority queue - * started by the codec engine will not cause audio defects. - */ - for (i = 0; i < num_channels; i++) - map_dmach_queue(i, EVENTQ_1); - - /* Event queue to TC mapping */ - for (i = 0; queue_tc_mapping[i][0] != -1; i++) - map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]); - - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); - - for (i = 0; i < info->n_region; i++) { - edma_write_array2(EDMA_DRAE, i, 0, 0x0); - edma_write_array2(EDMA_DRAE, i, 1, 0x0); - edma_write_array(EDMA_QRAE, i, 0x0); - } - return 0; fail: - if (err_irq) - free_irq(err_irq, NULL); - if (irq) - free_irq(irq, NULL); - iounmap(edmacc_regs_base); + for (i = 0; i < EDMA_MAX_CC; i++) { + if (err_irq[i]) + free_irq(err_irq[i], &pdev->dev); + if (irq[i]) + free_irq(irq[i], &pdev->dev); + } fail1: - release_mem_region(r->start, len); + for (i = 0; i < EDMA_MAX_CC; i++) { + if (r[i]) + release_mem_region(r[i]->start, len[i]); + if (edmacc_regs_base[i]) + iounmap(edmacc_regs_base[i]); + kfree(edma_info[i]); + } return status; } diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 1b6532159c5..f6ea9db11f4 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -34,6 +34,7 @@ static DEFINE_SPINLOCK(gpio_lock); struct davinci_gpio { struct gpio_chip chip; struct gpio_controller *__iomem regs; + int irq_base; }; static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; @@ -161,8 +162,7 @@ pure_initcall(davinci_gpio_setup); * used as output pins ... which is convenient for testing. * * NOTE: The first few GPIOs also have direct INTC hookups in addition - * to their GPIOBNK0 irq, with a bit less overhead but less flexibility - * on triggering (e.g. no edge options). We don't try to use those. + * to their GPIOBNK0 irq, with a bit less overhead. * * All those INTC hookups (direct, plus several IRQ banks) can also * serve as EDMA event triggers. @@ -171,7 +171,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(unsigned irq) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); + u32 mask = (u32) get_irq_data(irq); __raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_rising); @@ -180,7 +180,7 @@ static void gpio_irq_disable(unsigned irq) static void gpio_irq_enable(unsigned irq) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); + u32 mask = (u32) get_irq_data(irq); unsigned status = irq_desc[irq].status; status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; @@ -196,7 +196,7 @@ static void gpio_irq_enable(unsigned irq) static int gpio_irq_type(unsigned irq, unsigned trigger) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); + u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; @@ -260,6 +260,45 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) /* now it may re-trigger */ } +static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + + if (d->irq_base >= 0) + return d->irq_base + offset; + else + return -ENODEV; +} + +static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + /* NOTE: we assume for now that only irqs in the first gpio_chip + * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). + */ + if (offset < soc_info->gpio_unbanked) + return soc_info->gpio_irq + offset; + else + return -ENODEV; +} + +static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) +{ + struct gpio_controller *__iomem g = get_irq_chip_data(irq); + u32 mask = (u32) get_irq_data(irq); + + if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + return -EINVAL; + + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + ? &g->set_falling : &g->clr_falling); + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + ? &g->set_rising : &g->clr_rising); + + return 0; +} + /* * NOTE: for suspend/resume, probably best to make a platform_device with * suspend_late/resume_resume calls hooking into results of the set_wake() @@ -275,6 +314,7 @@ static int __init davinci_gpio_irq_setup(void) u32 binten = 0; unsigned ngpio, bank_irq; struct davinci_soc_info *soc_info = &davinci_soc_info; + struct gpio_controller *__iomem g; ngpio = soc_info->gpio_num; @@ -292,12 +332,63 @@ static int __init davinci_gpio_irq_setup(void) } clk_enable(clk); + /* Arrange gpio_to_irq() support, handling either direct IRQs or + * banked IRQs. Having GPIOs in the first GPIO bank use direct + * IRQs, while the others use banked IRQs, would need some setup + * tweaks to recognize hardware which can do that. + */ + for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { + chips[bank].chip.to_irq = gpio_to_irq_banked; + chips[bank].irq_base = soc_info->gpio_unbanked + ? -EINVAL + : (soc_info->intc_irq_num + gpio); + } + + /* + * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO + * controller only handling trigger modes. We currently assume no + * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. + */ + if (soc_info->gpio_unbanked) { + static struct irq_chip gpio_irqchip_unbanked; + + /* pass "bank 0" GPIO IRQs to AINTC */ + chips[0].chip.to_irq = gpio_to_irq_unbanked; + binten = BIT(0); + + /* AINTC handles mask/unmask; GPIO handles triggering */ + irq = bank_irq; + gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); + gpio_irqchip_unbanked.name = "GPIO-AINTC"; + gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; + + /* default trigger: both edges */ + g = gpio2controller(0); + __raw_writel(~0, &g->set_falling); + __raw_writel(~0, &g->set_rising); + + /* set the direct IRQs up to use that irqchip */ + for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { + set_irq_chip(irq, &gpio_irqchip_unbanked); + set_irq_data(irq, (void *) __gpio_mask(gpio)); + set_irq_chip_data(irq, g); + irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; + } + + goto done; + } + + /* + * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we + * then chain through our own handler. + */ for (gpio = 0, irq = gpio_to_irq(0), bank = 0; gpio < ngpio; bank++, bank_irq++) { - struct gpio_controller *__iomem g = gpio2controller(gpio); unsigned i; + /* disabled by default, enabled only as needed */ + g = gpio2controller(gpio); __raw_writel(~0, &g->clr_falling); __raw_writel(~0, &g->clr_rising); @@ -309,6 +400,7 @@ static int __init davinci_gpio_irq_setup(void) for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { set_irq_chip(irq, &gpio_irqchip); set_irq_chip_data(irq, g); + set_irq_data(irq, (void *) __gpio_mask(gpio)); set_irq_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } @@ -316,6 +408,7 @@ static int __init davinci_gpio_irq_setup(void) binten |= BIT(bank); } +done: /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index e0abc437d79..18e4ce34ece 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -5,21 +5,73 @@ #define __ASM_ARCH_DAVINCI_ASP_H #include <mach/irqs.h> +#include <mach/edma.h> -/* Bases of register banks */ +/* Bases of dm644x and dm355 register banks */ #define DAVINCI_ASP0_BASE 0x01E02000 #define DAVINCI_ASP1_BASE 0x01E04000 -/* EDMA channels */ +/* Bases of dm646x register banks */ +#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 +#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 + +/* Bases of da850/da830 McASP0 register banks */ +#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 + +/* Bases of da830 McASP1 register banks */ +#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 + +/* EDMA channels of dm644x and dm355 */ #define DAVINCI_DMA_ASP0_TX 2 #define DAVINCI_DMA_ASP0_RX 3 #define DAVINCI_DMA_ASP1_TX 8 #define DAVINCI_DMA_ASP1_RX 9 +/* EDMA channels of dm646x */ +#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 +#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 +#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 + +/* EDMA channels of da850/da830 McASP0 */ +#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 +#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 + +/* EDMA channels of da830 McASP1 */ +#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 +#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 + /* Interrupts */ #define DAVINCI_ASP0_RX_INT IRQ_MBRINT #define DAVINCI_ASP0_TX_INT IRQ_MBXINT #define DAVINCI_ASP1_RX_INT IRQ_MBRINT #define DAVINCI_ASP1_TX_INT IRQ_MBXINT +struct snd_platform_data { + u32 tx_dma_offset; + u32 rx_dma_offset; + enum dma_event_q eventq_no; /* event queue number */ + unsigned int codec_fmt; + + /* McASP specific fields */ + int tdm_slots; + u8 op_mode; + u8 num_serializer; + u8 *serial_dir; + u8 version; + u8 txnumevt; + u8 rxnumevt; +}; + +enum { + MCASP_VERSION_1 = 0, /* DM646x */ + MCASP_VERSION_2, /* DA8xx/OMAPL1x */ +}; + +#define INACTIVE_MODE 0 +#define TX_MODE 1 +#define RX_MODE 2 + +#define DAVINCI_MCASP_IIS_MODE 0 +#define DAVINCI_MCASP_DIT_MODE 1 + #endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index a1f03b606d8..1fd3917cae4 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -60,10 +60,10 @@ struct davinci_soc_info { u8 *intc_irq_prios; unsigned long intc_irq_num; struct davinci_timer_info *timer_info; - void __iomem *wdt_base; void __iomem *gpio_base; unsigned gpio_num; unsigned gpio_irq; + unsigned gpio_unbanked; struct platform_device *serial_dev; struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index d12a5ed2959..189b1ff1364 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -30,6 +30,9 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM6446 0x64460000 #define DAVINCI_CPU_ID_DM6467 0x64670000 #define DAVINCI_CPU_ID_DM355 0x03550000 +#define DAVINCI_CPU_ID_DM365 0x03650000 +#define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -40,6 +43,9 @@ static inline int is_davinci_ ##type(void) \ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) +IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) +IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) +IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -59,4 +65,22 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) #define cpu_is_davinci_dm355() 0 #endif +#ifdef CONFIG_ARCH_DAVINCI_DM365 +#define cpu_is_davinci_dm365() is_davinci_dm365() +#else +#define cpu_is_davinci_dm365() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DA830 +#define cpu_is_davinci_da830() is_davinci_da830() +#else +#define cpu_is_davinci_da830() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DA850 +#define cpu_is_davinci_da850() is_davinci_da850() +#else +#define cpu_is_davinci_da850() 0 +#endif + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 00000000000..d4095d0572c --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -0,0 +1,121 @@ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include <mach/serial.h> +#include <mach/edma.h> +#include <mach/i2c.h> +#include <mach/emac.h> +#include <mach/asp.h> +#include <mach/mmc.h> + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) + +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_JTAG_ID_REG 0x01c14018 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 +#define DA8XX_LCD_CNTRL_BASE 0x01e13000 +#define DA8XX_MMCSD0_BASE 0x01c40000 +#define DA8XX_AEMIF_CS2_BASE 0x60000000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 + +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define PINMUX5 0x14 +#define PINMUX6 0x18 +#define PINMUX7 0x1c +#define PINMUX8 0x20 +#define PINMUX9 0x24 +#define PINMUX10 0x28 +#define PINMUX11 0x2c +#define PINMUX12 0x30 +#define PINMUX13 0x34 +#define PINMUX14 0x38 +#define PINMUX15 0x3c +#define PINMUX16 0x40 +#define PINMUX17 0x44 +#define PINMUX18 0x48 +#define PINMUX19 0x4c + +void __init da830_init(void); +void __init da850_init(void); + +int da8xx_register_edma(void); +int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); +int da8xx_register_watchdog(void); +int da8xx_register_emac(void); +int da8xx_register_lcdc(void); +int da8xx_register_mmcsd0(struct davinci_mmc_config *config); +void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); + +extern struct platform_device da8xx_serial_device; +extern struct emac_platform_data da8xx_emac_pdata; + +extern const short da830_emif25_pins[]; +extern const short da830_spi0_pins[]; +extern const short da830_spi1_pins[]; +extern const short da830_mmc_sd_pins[]; +extern const short da830_uart0_pins[]; +extern const short da830_uart1_pins[]; +extern const short da830_uart2_pins[]; +extern const short da830_usb20_pins[]; +extern const short da830_usb11_pins[]; +extern const short da830_uhpi_pins[]; +extern const short da830_cpgmac_pins[]; +extern const short da830_emif3c_pins[]; +extern const short da830_mcasp0_pins[]; +extern const short da830_mcasp1_pins[]; +extern const short da830_mcasp2_pins[]; +extern const short da830_i2c0_pins[]; +extern const short da830_i2c1_pins[]; +extern const short da830_lcdcntl_pins[]; +extern const short da830_pwm_pins[]; +extern const short da830_ecap0_pins[]; +extern const short da830_ecap1_pins[]; +extern const short da830_ecap2_pins[]; +extern const short da830_eqep0_pins[]; +extern const short da830_eqep1_pins[]; + +extern const short da850_uart0_pins[]; +extern const short da850_uart1_pins[]; +extern const short da850_uart2_pins[]; +extern const short da850_i2c0_pins[]; +extern const short da850_i2c1_pins[]; +extern const short da850_cpgmac_pins[]; +extern const short da850_mcasp_pins[]; +extern const short da850_lcdcntl_pins[]; +extern const short da850_mmcsd0_pins[]; +extern const short da850_nand_pins[]; +extern const short da850_nor_pins[]; + +int da8xx_pinmux_setup(const short pins[]); + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index de3fc2182b4..17ab5236da6 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -24,7 +24,15 @@ tst \rx, #1 @ MMU enabled? moveq \rx, #0x01000000 @ physical base address movne \rx, #0xfe000000 @ virtual base +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + orr \rx, \rx, #0x00d00000 @ physical base address + orr \rx, \rx, #0x0000d000 @ of UART 2 +#else orr \rx, \rx, #0x00c20000 @ UART 0 +#endif .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h index 54903b72438..85536d8e833 100644 --- a/arch/arm/mach-davinci/include/mach/dm355.h +++ b/arch/arm/mach-davinci/include/mach/dm355.h @@ -12,11 +12,18 @@ #define __ASM_ARCH_DM355_H #include <mach/hardware.h> +#include <mach/asp.h> +#include <media/davinci/vpfe_capture.h> + +#define ASP1_TX_EVT_EN 1 +#define ASP1_RX_EVT_EN 2 struct spi_board_info; void __init dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len); +void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); +void dm355_set_vpfe_config(struct vpfe_config *cfg); #endif /* __ASM_ARCH_DM355_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h new file mode 100644 index 00000000000..09db4343bb4 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_DM365_H +#define __ASM_ARCH_DM665_H + +#include <linux/platform_device.h> +#include <mach/hardware.h> +#include <mach/emac.h> + +#define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_CNTRL_OFFSET (0x0000) +#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) +#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) +#define DM365_EMAC_MDIO_OFFSET (0x4000) +#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) + +void __init dm365_init(void); + +#endif /* __ASM_ARCH_DM365_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 15d42b92a8c..0efb73852c2 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -25,6 +25,8 @@ #include <linux/platform_device.h> #include <mach/hardware.h> #include <mach/emac.h> +#include <mach/asp.h> +#include <media/davinci/vpfe_capture.h> #define DM644X_EMAC_BASE (0x01C80000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) @@ -34,5 +36,7 @@ #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) void __init dm644x_init(void); +void __init dm644x_init_asp(struct snd_platform_data *pdata); +void dm644x_set_vpfe_config(struct vpfe_config *cfg); #endif /* __ASM_ARCH_DM644X_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 1fc764c8646..8cec746ae9d 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -13,6 +13,9 @@ #include <mach/hardware.h> #include <mach/emac.h> +#include <mach/asp.h> +#include <linux/i2c.h> +#include <linux/videodev2.h> #define DM646X_EMAC_BASE (0x01C80000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000) @@ -21,6 +24,68 @@ #define DM646X_EMAC_MDIO_OFFSET (0x4000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM646X_ATA_REG_BASE (0x01C66000) + void __init dm646x_init(void); +void __init dm646x_init_ide(void); +void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); +void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); + +void dm646x_video_init(void); + +enum vpif_if_type { + VPIF_IF_BT656, + VPIF_IF_BT1120, + VPIF_IF_RAW_BAYER +}; + +struct vpif_interface { + enum vpif_if_type if_type; + unsigned hd_pol:1; + unsigned vd_pol:1; + unsigned fid_pol:1; +}; + +struct vpif_subdev_info { + const char *name; + struct i2c_board_info board_info; + u32 input; + u32 output; + unsigned can_route:1; + struct vpif_interface vpif_if; +}; + +struct vpif_display_config { + int (*set_clock)(int, int); + struct vpif_subdev_info *subdevinfo; + int subdev_count; + const char **output; + int output_count; + const char *card_name; +}; + +struct vpif_input { + struct v4l2_input input; + const char *subdev_name; +}; + +#define VPIF_CAPTURE_MAX_CHANNELS 2 + +struct vpif_capture_chan_config { + const struct vpif_input *inputs; + int input_count; +}; + +struct vpif_capture_config { + int (*setup_input_channel_mode)(int); + int (*setup_input_path)(int, const char *); + struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS]; + struct vpif_subdev_info *subdev_info; + int subdev_count; + const char *card_name; +}; + +void dm646x_setup_vpif(struct vpif_display_config *, + struct vpif_capture_config *); #endif /* __ASM_ARCH_DM646X_H */ diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index 24a379239d7..eb8bfd7925e 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -139,6 +139,54 @@ struct edmacc_param { #define DAVINCI_DMA_PWM1 53 #define DAVINCI_DMA_PWM2 54 +/* DA830 specific EDMA3 information */ +#define EDMA_DA830_NUM_DMACH 32 +#define EDMA_DA830_NUM_TCC 32 +#define EDMA_DA830_NUM_PARAMENTRY 128 +#define EDMA_DA830_NUM_EVQUE 2 +#define EDMA_DA830_NUM_TC 2 +#define EDMA_DA830_CHMAP_EXIST 0 +#define EDMA_DA830_NUM_REGIONS 4 +#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu +#define DA830_DMACH2EVENT_MAP1 0x00000000u +#define DA830_EDMA_ARM_OWN 0x30FFCCFFu + +/* DA830 specific EDMA3 Events Information */ +enum DA830_edma_ch { + DA830_DMACH_MCASP0_RX, + DA830_DMACH_MCASP0_TX, + DA830_DMACH_MCASP1_RX, + DA830_DMACH_MCASP1_TX, + DA830_DMACH_MCASP2_RX, + DA830_DMACH_MCASP2_TX, + DA830_DMACH_GPIO_BNK0INT, + DA830_DMACH_GPIO_BNK1INT, + DA830_DMACH_UART0_RX, + DA830_DMACH_UART0_TX, + DA830_DMACH_TMR64P0_EVTOUT12, + DA830_DMACH_TMR64P0_EVTOUT34, + DA830_DMACH_UART1_RX, + DA830_DMACH_UART1_TX, + DA830_DMACH_SPI0_RX, + DA830_DMACH_SPI0_TX, + DA830_DMACH_MMCSD_RX, + DA830_DMACH_MMCSD_TX, + DA830_DMACH_SPI1_RX, + DA830_DMACH_SPI1_TX, + DA830_DMACH_DMAX_EVTOUT6, + DA830_DMACH_DMAX_EVTOUT7, + DA830_DMACH_GPIO_BNK2INT, + DA830_DMACH_GPIO_BNK3INT, + DA830_DMACH_I2C0_RX, + DA830_DMACH_I2C0_TX, + DA830_DMACH_I2C1_RX, + DA830_DMACH_I2C1_TX, + DA830_DMACH_GPIO_BNK4INT, + DA830_DMACH_GPIO_BNK5INT, + DA830_DMACH_UART2_RX, + DA830_DMACH_UART2_TX +}; + /*ch_status paramater of callback function possible values*/ #define DMA_COMPLETE 1 #define DMA_CC_ERROR 2 @@ -162,6 +210,8 @@ enum fifo_width { enum dma_event_q { EVENTQ_0 = 0, EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, EVENTQ_DEFAULT = -1 }; @@ -170,8 +220,15 @@ enum sync_dimension { ABSYNC = 1 }; +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) +#define EDMA_CTLR(i) ((i) >> 16) +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) + #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, @@ -180,9 +237,13 @@ int edma_alloc_channel(int channel, void edma_free_channel(unsigned channel); /* alloc/free parameter RAM slots */ -int edma_alloc_slot(int slot); +int edma_alloc_slot(unsigned ctlr, int slot); void edma_free_slot(unsigned slot); +/* alloc/free a set of contiguous parameter RAM slots */ +int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); +int edma_free_cont_slots(unsigned slot, int count); + /* calls that operate on part of a parameter RAM slot */ void edma_set_src(unsigned slot, dma_addr_t src_port, enum address_mode mode, enum fifo_width); @@ -216,9 +277,13 @@ struct edma_soc_info { unsigned n_region; unsigned n_slot; unsigned n_tc; + unsigned n_cc; + enum dma_event_q default_queue; /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; + const s8 (*queue_tc_mapping)[2]; + const s8 (*queue_priority_mapping)[2]; }; #endif diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index ae074556831..f3b8ef87815 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -42,6 +42,9 @@ */ #define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */ +/* Convert GPIO signal to GPIO pin number */ +#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) + struct gpio_controller { u32 dir; u32 out_data; @@ -78,6 +81,8 @@ __gpio_to_controller(unsigned gpio) ptr = base + 0x60; else if (gpio < 32 * 4) ptr = base + 0x88; + else if (gpio < 32 * 5) + ptr = base + 0xb0; else ptr = NULL; return ptr; @@ -142,15 +147,13 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { - if (gpio >= DAVINCI_N_GPIO) - return -EINVAL; - return davinci_soc_info.intc_irq_num + gpio; + return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned irq) { - /* caller guarantees gpio_to_irq() succeeded */ - return irq - davinci_soc_info.intc_irq_num; + /* don't support the reverse mapping */ + return -ENOSYS; } #endif /* __DAVINCI_GPIO_H */ diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index 48c77934d51..41c89386e39 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -24,4 +24,21 @@ /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 +/* + * I/O mapping + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define __IO_ADDRESS(x) ((x) + IO_OFFSET) +#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) + +#ifdef __ASSEMBLER__ +#define IOMEM(x) x +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index 2479785405a..62b0a90309a 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h @@ -14,18 +14,6 @@ #define IO_SPACE_LIMIT 0xffffffff /* - * ---------------------------------------------------------------------------- - * I/O mapping - * ---------------------------------------------------------------------------- - */ -#define IO_PHYS 0x01c00000 -#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ -#define IO_SIZE 0x00400000 -#define IO_VIRT (IO_PHYS + IO_OFFSET) -#define io_v2p(va) ((va) - IO_OFFSET) -#define __IO_ADDRESS(x) ((x) + IO_OFFSET) - -/* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ @@ -33,19 +21,12 @@ #define __mem_pci(a) (a) #define __mem_isa(a) (a) -#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) - -#ifdef __ASSEMBLER__ -#define IOMEM(x) x -#else -#define IOMEM(x) ((void __force __iomem *)(x)) - +#ifndef __ASSEMBLER__ #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) #define __arch_iounmap(v) davinci_iounmap(v) void __iomem *davinci_ioremap(unsigned long phys, size_t size, unsigned int type); void davinci_iounmap(volatile void __iomem *addr); - -#endif /* __ASSEMBLER__ */ +#endif #endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index bc5d6aaa69a..3c918a77261 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -99,9 +99,6 @@ #define IRQ_EMUINT 63 #define DAVINCI_N_AINTC_IRQ 64 -#define DAVINCI_N_GPIO 104 - -#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 @@ -206,4 +203,206 @@ #define IRQ_DM355_GPIOBNK5 59 #define IRQ_DM355_GPIOBNK6 60 +/* DaVinci DM365-specific Interrupts */ +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 +#define IRQ_DM365_IMCOPINT 11 +#define IRQ_DM365_RTOINT 13 +#define IRQ_DM365_TINT5 14 +#define IRQ_DM365_TINT6 15 +#define IRQ_DM365_SPINT2_1 21 +#define IRQ_DM365_TINT7 22 +#define IRQ_DM365_SDIOINT0 23 +#define IRQ_DM365_MMCINT1 27 +#define IRQ_DM365_PWMINT3 28 +#define IRQ_DM365_SDIOINT1 31 +#define IRQ_DM365_SPIINT0_0 42 +#define IRQ_DM365_SPIINT3_0 43 +#define IRQ_DM365_GPIO0 44 +#define IRQ_DM365_GPIO1 45 +#define IRQ_DM365_GPIO2 46 +#define IRQ_DM365_GPIO3 47 +#define IRQ_DM365_GPIO4 48 +#define IRQ_DM365_GPIO5 49 +#define IRQ_DM365_GPIO6 50 +#define IRQ_DM365_GPIO7 51 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_EMAC_MISCPULSE 55 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_EMUINT 63 + +/* DA8XX interrupts */ +#define IRQ_DA8XX_COMMTX 0 +#define IRQ_DA8XX_COMMRX 1 +#define IRQ_DA8XX_NINT 2 +#define IRQ_DA8XX_EVTOUT0 3 +#define IRQ_DA8XX_EVTOUT1 4 +#define IRQ_DA8XX_EVTOUT2 5 +#define IRQ_DA8XX_EVTOUT3 6 +#define IRQ_DA8XX_EVTOUT4 7 +#define IRQ_DA8XX_EVTOUT5 8 +#define IRQ_DA8XX_EVTOUT6 9 +#define IRQ_DA8XX_EVTOUT7 10 +#define IRQ_DA8XX_CCINT0 11 +#define IRQ_DA8XX_CCERRINT 12 +#define IRQ_DA8XX_TCERRINT0 13 +#define IRQ_DA8XX_AEMIFINT 14 +#define IRQ_DA8XX_I2CINT0 15 +#define IRQ_DA8XX_MMCSDINT0 16 +#define IRQ_DA8XX_MMCSDINT1 17 +#define IRQ_DA8XX_ALLINT0 18 +#define IRQ_DA8XX_RTC 19 +#define IRQ_DA8XX_SPINT0 20 +#define IRQ_DA8XX_TINT12_0 21 +#define IRQ_DA8XX_TINT34_0 22 +#define IRQ_DA8XX_TINT12_1 23 +#define IRQ_DA8XX_TINT34_1 24 +#define IRQ_DA8XX_UARTINT0 25 +#define IRQ_DA8XX_KEYMGRINT 26 +#define IRQ_DA8XX_SECINT 26 +#define IRQ_DA8XX_SECKEYERR 26 +#define IRQ_DA8XX_CHIPINT0 28 +#define IRQ_DA8XX_CHIPINT1 29 +#define IRQ_DA8XX_CHIPINT2 30 +#define IRQ_DA8XX_CHIPINT3 31 +#define IRQ_DA8XX_TCERRINT1 32 +#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 +#define IRQ_DA8XX_C0_RX_PULSE 34 +#define IRQ_DA8XX_C0_TX_PULSE 35 +#define IRQ_DA8XX_C0_MISC_PULSE 36 +#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 +#define IRQ_DA8XX_C1_RX_PULSE 38 +#define IRQ_DA8XX_C1_TX_PULSE 39 +#define IRQ_DA8XX_C1_MISC_PULSE 40 +#define IRQ_DA8XX_MEMERR 41 +#define IRQ_DA8XX_GPIO0 42 +#define IRQ_DA8XX_GPIO1 43 +#define IRQ_DA8XX_GPIO2 44 +#define IRQ_DA8XX_GPIO3 45 +#define IRQ_DA8XX_GPIO4 46 +#define IRQ_DA8XX_GPIO5 47 +#define IRQ_DA8XX_GPIO6 48 +#define IRQ_DA8XX_GPIO7 49 +#define IRQ_DA8XX_GPIO8 50 +#define IRQ_DA8XX_I2CINT1 51 +#define IRQ_DA8XX_LCDINT 52 +#define IRQ_DA8XX_UARTINT1 53 +#define IRQ_DA8XX_MCASPINT 54 +#define IRQ_DA8XX_ALLINT1 55 +#define IRQ_DA8XX_SPINT1 56 +#define IRQ_DA8XX_UHPI_INT1 57 +#define IRQ_DA8XX_USB_INT 58 +#define IRQ_DA8XX_IRQN 59 +#define IRQ_DA8XX_RWAKEUP 60 +#define IRQ_DA8XX_UARTINT2 61 +#define IRQ_DA8XX_DFTSSINT 62 +#define IRQ_DA8XX_EHRPWM0 63 +#define IRQ_DA8XX_EHRPWM0TZ 64 +#define IRQ_DA8XX_EHRPWM1 65 +#define IRQ_DA8XX_EHRPWM1TZ 66 +#define IRQ_DA8XX_ECAP0 69 +#define IRQ_DA8XX_ECAP1 70 +#define IRQ_DA8XX_ECAP2 71 +#define IRQ_DA8XX_ARMCLKSTOPREQ 90 + +/* DA830 specific interrupts */ +#define IRQ_DA830_MPUERR 27 +#define IRQ_DA830_IOPUERR 27 +#define IRQ_DA830_BOOTCFGERR 27 +#define IRQ_DA830_EHRPWM2 67 +#define IRQ_DA830_EHRPWM2TZ 68 +#define IRQ_DA830_EQEP0 72 +#define IRQ_DA830_EQEP1 73 +#define IRQ_DA830_T12CMPINT0_0 74 +#define IRQ_DA830_T12CMPINT1_0 75 +#define IRQ_DA830_T12CMPINT2_0 76 +#define IRQ_DA830_T12CMPINT3_0 77 +#define IRQ_DA830_T12CMPINT4_0 78 +#define IRQ_DA830_T12CMPINT5_0 79 +#define IRQ_DA830_T12CMPINT6_0 80 +#define IRQ_DA830_T12CMPINT7_0 81 +#define IRQ_DA830_T12CMPINT0_1 82 +#define IRQ_DA830_T12CMPINT1_1 83 +#define IRQ_DA830_T12CMPINT2_1 84 +#define IRQ_DA830_T12CMPINT3_1 85 +#define IRQ_DA830_T12CMPINT4_1 86 +#define IRQ_DA830_T12CMPINT5_1 87 +#define IRQ_DA830_T12CMPINT6_1 88 +#define IRQ_DA830_T12CMPINT7_1 89 + +#define DA830_N_CP_INTC_IRQ 96 + +/* DA850 speicific interrupts */ +#define IRQ_DA850_MPUADDRERR0 27 +#define IRQ_DA850_MPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR0 27 +#define IRQ_DA850_IOPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR1 27 +#define IRQ_DA850_IOPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR2 27 +#define IRQ_DA850_IOPUPROTERR2 27 +#define IRQ_DA850_BOOTCFG_ADDR_ERR 27 +#define IRQ_DA850_BOOTCFG_PROT_ERR 27 +#define IRQ_DA850_MPUADDRERR1 27 +#define IRQ_DA850_MPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR3 27 +#define IRQ_DA850_IOPUPROTERR3 27 +#define IRQ_DA850_IOPUADDRERR4 27 +#define IRQ_DA850_IOPUPROTERR4 27 +#define IRQ_DA850_IOPUADDRERR5 27 +#define IRQ_DA850_IOPUPROTERR5 27 +#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 +#define IRQ_DA850_SATAINT 67 +#define IRQ_DA850_TINT12_2 68 +#define IRQ_DA850_TINT34_2 68 +#define IRQ_DA850_TINTALL_2 68 +#define IRQ_DA850_MMCSDINT0_1 72 +#define IRQ_DA850_MMCSDINT1_1 73 +#define IRQ_DA850_T12CMPINT0_2 74 +#define IRQ_DA850_T12CMPINT1_2 75 +#define IRQ_DA850_T12CMPINT2_2 76 +#define IRQ_DA850_T12CMPINT3_2 77 +#define IRQ_DA850_T12CMPINT4_2 78 +#define IRQ_DA850_T12CMPINT5_2 79 +#define IRQ_DA850_T12CMPINT6_2 80 +#define IRQ_DA850_T12CMPINT7_2 81 +#define IRQ_DA850_T12CMPINT0_3 82 +#define IRQ_DA850_T12CMPINT1_3 83 +#define IRQ_DA850_T12CMPINT2_3 84 +#define IRQ_DA850_T12CMPINT3_3 85 +#define IRQ_DA850_T12CMPINT4_3 86 +#define IRQ_DA850_T12CMPINT5_3 87 +#define IRQ_DA850_T12CMPINT6_3 88 +#define IRQ_DA850_T12CMPINT7_3 89 +#define IRQ_DA850_RPIINT 91 +#define IRQ_DA850_VPIFINT 92 +#define IRQ_DA850_CCINT1 93 +#define IRQ_DA850_CCERRINT1 94 +#define IRQ_DA850_TCERRINT2 95 +#define IRQ_DA850_TINT12_3 96 +#define IRQ_DA850_TINT34_3 96 +#define IRQ_DA850_TINTALL_3 96 +#define IRQ_DA850_MCBSP0RINT 97 +#define IRQ_DA850_MCBSP0XINT 98 +#define IRQ_DA850_MCBSP1RINT 99 +#define IRQ_DA850_MCBSP1XINT 100 + +#define DA850_N_CP_INTC_IRQ 101 + +/* da850 currently has the most gpio pins (144) */ +#define DAVINCI_N_GPIO 144 +/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ +#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) + #endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index c712c7cdf38..80309aed534 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -20,9 +20,16 @@ /************************************************************************** * Definitions **************************************************************************/ -#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_DDR_BASE 0x80000000 +#define DA8XX_DDR_BASE 0xc0000000 +#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) +#error Cannot enable DaVinci and DA8XX platforms concurrently +#elif defined(CONFIG_ARCH_DAVINCI_DA8XX) +#define PHYS_OFFSET DA8XX_DDR_BASE +#else #define PHYS_OFFSET DAVINCI_DDR_BASE +#endif /* * Increase size of DMA-consistent memory region diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 27378458542..bb84893a4e8 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -154,6 +154,737 @@ enum davinci_dm355_index { DM355_EVT8_ASP1_TX, DM355_EVT9_ASP1_RX, DM355_EVT26_MMC0_RX, + + /* Video Out */ + DM355_VOUT_FIELD, + DM355_VOUT_FIELD_G70, + DM355_VOUT_HVSYNC, + DM355_VOUT_COUTL_EN, + DM355_VOUT_COUTH_EN, + + /* Video In Pin Mux */ + DM355_VIN_PCLK, + DM355_VIN_CAM_WEN, + DM355_VIN_CAM_VD, + DM355_VIN_CAM_HD, + DM355_VIN_YIN_EN, + DM355_VIN_CINL_EN, + DM355_VIN_CINH_EN, +}; + +enum davinci_dm365_index { + /* MMC/SD 0 */ + DM365_MMCSD0, + + /* MMC/SD 1 */ + DM365_SD1_CLK, + DM365_SD1_CMD, + DM365_SD1_DATA3, + DM365_SD1_DATA2, + DM365_SD1_DATA1, + DM365_SD1_DATA0, + + /* I2C */ + DM365_I2C_SDA, + DM365_I2C_SCL, + + /* AEMIF */ + DM365_AEMIF_AR, + DM365_AEMIF_A3, + DM365_AEMIF_A7, + DM365_AEMIF_D15_8, + DM365_AEMIF_CE0, + + /* ASP0 function */ + DM365_MCBSP0_BDX, + DM365_MCBSP0_X, + DM365_MCBSP0_BFSX, + DM365_MCBSP0_BDR, + DM365_MCBSP0_R, + DM365_MCBSP0_BFSR, + + /* SPI0 */ + DM365_SPI0_SCLK, + DM365_SPI0_SDI, + DM365_SPI0_SDO, + DM365_SPI0_SDENA0, + DM365_SPI0_SDENA1, + + /* UART */ + DM365_UART0_RXD, + DM365_UART0_TXD, + DM365_UART1_RXD, + DM365_UART1_TXD, + DM365_UART1_RTS, + DM365_UART1_CTS, + + /* EMAC */ + DM365_EMAC_TX_EN, + DM365_EMAC_TX_CLK, + DM365_EMAC_COL, + DM365_EMAC_TXD3, + DM365_EMAC_TXD2, + DM365_EMAC_TXD1, + DM365_EMAC_TXD0, + DM365_EMAC_RXD3, + DM365_EMAC_RXD2, + DM365_EMAC_RXD1, + DM365_EMAC_RXD0, + DM365_EMAC_RX_CLK, + DM365_EMAC_RX_DV, + DM365_EMAC_RX_ER, + DM365_EMAC_CRS, + DM365_EMAC_MDIO, + DM365_EMAC_MDCLK, + + /* Keypad */ + DM365_KEYPAD, + + /* PWM */ + DM365_PWM0, + DM365_PWM0_G23, + DM365_PWM1, + DM365_PWM1_G25, + DM365_PWM2_G87, + DM365_PWM2_G88, + DM365_PWM2_G89, + DM365_PWM2_G90, + DM365_PWM3_G80, + DM365_PWM3_G81, + DM365_PWM3_G85, + DM365_PWM3_G86, + + /* SPI1 */ + DM365_SPI1_SCLK, + DM365_SPI1_SDO, + DM365_SPI1_SDI, + DM365_SPI1_SDENA0, + DM365_SPI1_SDENA1, + + /* SPI2 */ + DM365_SPI2_SCLK, + DM365_SPI2_SDO, + DM365_SPI2_SDI, + DM365_SPI2_SDENA0, + DM365_SPI2_SDENA1, + + /* SPI3 */ + DM365_SPI3_SCLK, + DM365_SPI3_SDO, + DM365_SPI3_SDI, + DM365_SPI3_SDENA0, + DM365_SPI3_SDENA1, + + /* SPI4 */ + DM365_SPI4_SCLK, + DM365_SPI4_SDO, + DM365_SPI4_SDI, + DM365_SPI4_SDENA0, + DM365_SPI4_SDENA1, + + /* GPIO */ + DM365_GPIO20, + DM365_GPIO33, + DM365_GPIO40, + + /* Video */ + DM365_VOUT_FIELD, + DM365_VOUT_FIELD_G81, + DM365_VOUT_HVSYNC, + DM365_VOUT_COUTL_EN, + DM365_VOUT_COUTH_EN, + DM365_VIN_CAM_WEN, + DM365_VIN_CAM_VD, + DM365_VIN_CAM_HD, + DM365_VIN_YIN4_7_EN, + DM365_VIN_YIN0_3_EN, + + /* IRQ muxing */ + DM365_INT_EDMA_CC, + DM365_INT_EDMA_TC0_ERR, + DM365_INT_EDMA_TC1_ERR, + DM365_INT_EDMA_TC2_ERR, + DM365_INT_EDMA_TC3_ERR, + DM365_INT_PRTCSS, + DM365_INT_EMAC_RXTHRESH, + DM365_INT_EMAC_RXPULSE, + DM365_INT_EMAC_TXPULSE, + DM365_INT_EMAC_MISCPULSE, + DM365_INT_IMX0_ENABLE, + DM365_INT_IMX0_DISABLE, + DM365_INT_HDVICP_ENABLE, + DM365_INT_HDVICP_DISABLE, + DM365_INT_IMX1_ENABLE, + DM365_INT_IMX1_DISABLE, + DM365_INT_NSF_ENABLE, + DM365_INT_NSF_DISABLE, + + /* EDMA event muxing */ + DM365_EVT2_ASP_TX, + DM365_EVT3_ASP_RX, + DM365_EVT26_MMC0_RX, +}; + +enum da830_index { + DA830_GPIO7_14, + DA830_RTCK, + DA830_GPIO7_15, + DA830_EMU_0, + DA830_EMB_SDCKE, + DA830_EMB_CLK_GLUE, + DA830_EMB_CLK, + DA830_NEMB_CS_0, + DA830_NEMB_CAS, + DA830_NEMB_RAS, + DA830_NEMB_WE, + DA830_EMB_BA_1, + DA830_EMB_BA_0, + DA830_EMB_A_0, + DA830_EMB_A_1, + DA830_EMB_A_2, + DA830_EMB_A_3, + DA830_EMB_A_4, + DA830_EMB_A_5, + DA830_GPIO7_0, + DA830_GPIO7_1, + DA830_GPIO7_2, + DA830_GPIO7_3, + DA830_GPIO7_4, + DA830_GPIO7_5, + DA830_GPIO7_6, + DA830_GPIO7_7, + DA830_EMB_A_6, + DA830_EMB_A_7, + DA830_EMB_A_8, + DA830_EMB_A_9, + DA830_EMB_A_10, + DA830_EMB_A_11, + DA830_EMB_A_12, + DA830_EMB_D_31, + DA830_GPIO7_8, + DA830_GPIO7_9, + DA830_GPIO7_10, + DA830_GPIO7_11, + DA830_GPIO7_12, + DA830_GPIO7_13, + DA830_GPIO3_13, + DA830_EMB_D_30, + DA830_EMB_D_29, + DA830_EMB_D_28, + DA830_EMB_D_27, + DA830_EMB_D_26, + DA830_EMB_D_25, + DA830_EMB_D_24, + DA830_EMB_D_23, + DA830_EMB_D_22, + DA830_EMB_D_21, + DA830_EMB_D_20, + DA830_EMB_D_19, + DA830_EMB_D_18, + DA830_EMB_D_17, + DA830_EMB_D_16, + DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, + DA830_EMB_D_0, + DA830_EMB_D_1, + DA830_EMB_D_2, + DA830_EMB_D_3, + DA830_EMB_D_4, + DA830_EMB_D_5, + DA830_EMB_D_6, + DA830_GPIO6_0, + DA830_GPIO6_1, + DA830_GPIO6_2, + DA830_GPIO6_3, + DA830_GPIO6_4, + DA830_GPIO6_5, + DA830_GPIO6_6, + DA830_EMB_D_7, + DA830_EMB_D_8, + DA830_EMB_D_9, + DA830_EMB_D_10, + DA830_EMB_D_11, + DA830_EMB_D_12, + DA830_EMB_D_13, + DA830_EMB_D_14, + DA830_GPIO6_7, + DA830_GPIO6_8, + DA830_GPIO6_9, + DA830_GPIO6_10, + DA830_GPIO6_11, + DA830_GPIO6_12, + DA830_GPIO6_13, + DA830_GPIO6_14, + DA830_EMB_D_15, + DA830_NEMB_WE_DQM_1, + DA830_NEMB_WE_DQM_0, + DA830_SPI0_SOMI_0, + DA830_SPI0_SIMO_0, + DA830_SPI0_CLK, + DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + DA830_EQEP0I, + DA830_EQEP0S, + DA830_EQEP1I, + DA830_NUART0_CTS, + DA830_NUART0_RTS, + DA830_EQEP0A, + DA830_EQEP0B, + DA830_GPIO6_15, + DA830_GPIO5_14, + DA830_GPIO5_15, + DA830_GPIO5_0, + DA830_GPIO5_1, + DA830_GPIO5_2, + DA830_GPIO5_3, + DA830_GPIO5_4, + DA830_SPI1_SOMI_0, + DA830_SPI1_SIMO_0, + DA830_SPI1_CLK, + DA830_UART0_RXD, + DA830_UART0_TXD, + DA830_AXR1_10, + DA830_AXR1_11, + DA830_NSPI1_ENA, + DA830_I2C1_SCL, + DA830_I2C1_SDA, + DA830_EQEP1S, + DA830_I2C0_SDA, + DA830_I2C0_SCL, + DA830_UART2_RXD, + DA830_TM64P0_IN12, + DA830_TM64P0_OUT12, + DA830_GPIO5_5, + DA830_GPIO5_6, + DA830_GPIO5_7, + DA830_GPIO5_8, + DA830_GPIO5_9, + DA830_GPIO5_10, + DA830_GPIO5_11, + DA830_GPIO5_12, + DA830_NSPI1_SCS_0, + DA830_USB0_DRVVBUS, + DA830_AHCLKX0, + DA830_ACLKX0, + DA830_AFSX0, + DA830_AHCLKR0, + DA830_ACLKR0, + DA830_AFSR0, + DA830_UART2_TXD, + DA830_AHCLKX2, + DA830_ECAP0_APWM0, + DA830_RMII_MHZ_50_CLK, + DA830_ECAP1_APWM1, + DA830_USB_REFCLKIN, + DA830_GPIO5_13, + DA830_GPIO4_15, + DA830_GPIO2_11, + DA830_GPIO2_12, + DA830_GPIO2_13, + DA830_GPIO2_14, + DA830_GPIO2_15, + DA830_GPIO3_12, + DA830_AMUTE0, + DA830_AXR0_0, + DA830_AXR0_1, + DA830_AXR0_2, + DA830_AXR0_3, + DA830_AXR0_4, + DA830_AXR0_5, + DA830_AXR0_6, + DA830_RMII_TXD_0, + DA830_RMII_TXD_1, + DA830_RMII_TXEN, + DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, + DA830_RMII_RXD_1, + DA830_RMII_RXER, + DA830_AFSR2, + DA830_ACLKX2, + DA830_AXR2_3, + DA830_AXR2_2, + DA830_AXR2_1, + DA830_AFSX2, + DA830_ACLKR2, + DA830_NRESETOUT, + DA830_GPIO3_0, + DA830_GPIO3_1, + DA830_GPIO3_2, + DA830_GPIO3_3, + DA830_GPIO3_4, + DA830_GPIO3_5, + DA830_GPIO3_6, + DA830_AXR0_7, + DA830_AXR0_8, + DA830_UART1_RXD, + DA830_UART1_TXD, + DA830_AXR0_11, + DA830_AHCLKX1, + DA830_ACLKX1, + DA830_AFSX1, + DA830_MDIO_CLK, + DA830_MDIO_D, + DA830_AXR0_9, + DA830_AXR0_10, + DA830_EPWM0B, + DA830_EPWM0A, + DA830_EPWMSYNCI, + DA830_AXR2_0, + DA830_EPWMSYNC0, + DA830_GPIO3_7, + DA830_GPIO3_8, + DA830_GPIO3_9, + DA830_GPIO3_10, + DA830_GPIO3_11, + DA830_GPIO3_14, + DA830_GPIO3_15, + DA830_GPIO4_10, + DA830_AHCLKR1, + DA830_ACLKR1, + DA830_AFSR1, + DA830_AMUTE1, + DA830_AXR1_0, + DA830_AXR1_1, + DA830_AXR1_2, + DA830_AXR1_3, + DA830_ECAP2_APWM2, + DA830_EHRPWMGLUETZ, + DA830_EQEP1A, + DA830_GPIO4_11, + DA830_GPIO4_12, + DA830_GPIO4_13, + DA830_GPIO4_14, + DA830_GPIO4_0, + DA830_GPIO4_1, + DA830_GPIO4_2, + DA830_GPIO4_3, + DA830_AXR1_4, + DA830_AXR1_5, + DA830_AXR1_6, + DA830_AXR1_7, + DA830_AXR1_8, + DA830_AXR1_9, + DA830_EMA_D_0, + DA830_EMA_D_1, + DA830_EQEP1B, + DA830_EPWM2B, + DA830_EPWM2A, + DA830_EPWM1B, + DA830_EPWM1A, + DA830_MMCSD_DAT_0, + DA830_MMCSD_DAT_1, + DA830_UHPI_HD_0, + DA830_UHPI_HD_1, + DA830_GPIO4_4, + DA830_GPIO4_5, + DA830_GPIO4_6, + DA830_GPIO4_7, + DA830_GPIO4_8, + DA830_GPIO4_9, + DA830_GPIO0_0, + DA830_GPIO0_1, + DA830_EMA_D_2, + DA830_EMA_D_3, + DA830_EMA_D_4, + DA830_EMA_D_5, + DA830_EMA_D_6, + DA830_EMA_D_7, + DA830_EMA_D_8, + DA830_EMA_D_9, + DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, + DA830_MMCSD_DAT_4, + DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, + DA830_MMCSD_DAT_7, + DA830_UHPI_HD_8, + DA830_UHPI_HD_9, + DA830_UHPI_HD_2, + DA830_UHPI_HD_3, + DA830_UHPI_HD_4, + DA830_UHPI_HD_5, + DA830_UHPI_HD_6, + DA830_UHPI_HD_7, + DA830_LCD_D_8, + DA830_LCD_D_9, + DA830_GPIO0_2, + DA830_GPIO0_3, + DA830_GPIO0_4, + DA830_GPIO0_5, + DA830_GPIO0_6, + DA830_GPIO0_7, + DA830_GPIO0_8, + DA830_GPIO0_9, + DA830_EMA_D_10, + DA830_EMA_D_11, + DA830_EMA_D_12, + DA830_EMA_D_13, + DA830_EMA_D_14, + DA830_EMA_D_15, + DA830_EMA_A_0, + DA830_EMA_A_1, + DA830_UHPI_HD_10, + DA830_UHPI_HD_11, + DA830_UHPI_HD_12, + DA830_UHPI_HD_13, + DA830_UHPI_HD_14, + DA830_UHPI_HD_15, + DA830_LCD_D_7, + DA830_MMCSD_CLK, + DA830_LCD_D_10, + DA830_LCD_D_11, + DA830_LCD_D_12, + DA830_LCD_D_13, + DA830_LCD_D_14, + DA830_LCD_D_15, + DA830_UHPI_HCNTL0, + DA830_GPIO0_10, + DA830_GPIO0_11, + DA830_GPIO0_12, + DA830_GPIO0_13, + DA830_GPIO0_14, + DA830_GPIO0_15, + DA830_GPIO1_0, + DA830_GPIO1_1, + DA830_EMA_A_2, + DA830_EMA_A_3, + DA830_EMA_A_4, + DA830_EMA_A_5, + DA830_EMA_A_6, + DA830_EMA_A_7, + DA830_EMA_A_8, + DA830_EMA_A_9, + DA830_MMCSD_CMD, + DA830_LCD_D_6, + DA830_LCD_D_3, + DA830_LCD_D_2, + DA830_LCD_D_1, + DA830_LCD_D_0, + DA830_LCD_PCLK, + DA830_LCD_HSYNC, + DA830_UHPI_HCNTL1, + DA830_GPIO1_2, + DA830_GPIO1_3, + DA830_GPIO1_4, + DA830_GPIO1_5, + DA830_GPIO1_6, + DA830_GPIO1_7, + DA830_GPIO1_8, + DA830_GPIO1_9, + DA830_EMA_A_10, + DA830_EMA_A_11, + DA830_EMA_A_12, + DA830_EMA_BA_1, + DA830_EMA_BA_0, + DA830_EMA_CLK, + DA830_EMA_SDCKE, + DA830_NEMA_CAS, + DA830_LCD_VSYNC, + DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + DA830_LCD_D_5, + DA830_LCD_D_4, + DA830_OBSCLK, + DA830_NEMA_CS_4, + DA830_UHPI_HHWIL, + DA830_AHCLKR2, + DA830_GPIO1_10, + DA830_GPIO1_11, + DA830_GPIO1_12, + DA830_GPIO1_13, + DA830_GPIO1_14, + DA830_GPIO1_15, + DA830_GPIO2_0, + DA830_GPIO2_1, + DA830_NEMA_RAS, + DA830_NEMA_WE, + DA830_NEMA_CS_0, + DA830_NEMA_CS_2, + DA830_NEMA_CS_3, + DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, + DA830_NEMA_WE_DQM_0, + DA830_NEMA_CS_5, + DA830_UHPI_HRNW, + DA830_NUHPI_HAS, + DA830_NUHPI_HCS, + DA830_NUHPI_HDS1, + DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, + DA830_AXR0_12, + DA830_AMUTE2, + DA830_AXR0_13, + DA830_AXR0_14, + DA830_AXR0_15, + DA830_GPIO2_2, + DA830_GPIO2_3, + DA830_GPIO2_4, + DA830_GPIO2_5, + DA830_GPIO2_6, + DA830_GPIO2_7, + DA830_GPIO2_8, + DA830_GPIO2_9, + DA830_EMA_WAIT_0, + DA830_NUHPI_HRDY, + DA830_GPIO2_10, +}; + +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, + + /* EMAC function */ + DA850_MII_TXEN, + DA850_MII_TXCLK, + DA850_MII_COL, + DA850_MII_TXD_3, + DA850_MII_TXD_2, + DA850_MII_TXD_1, + DA850_MII_TXD_0, + DA850_MII_RXER, + DA850_MII_CRS, + DA850_MII_RXCLK, + DA850_MII_RXDV, + DA850_MII_RXD_3, + DA850_MII_RXD_2, + DA850_MII_RXD_1, + DA850_MII_RXD_0, + DA850_MDIO_CLK, + DA850_MDIO_D, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, + + /* LCD function */ + DA850_LCD_D_7, + DA850_LCD_D_6, + DA850_LCD_D_5, + DA850_LCD_D_4, + DA850_LCD_D_3, + DA850_LCD_D_2, + DA850_LCD_D_1, + DA850_LCD_D_0, + DA850_LCD_D_15, + DA850_LCD_D_14, + DA850_LCD_D_13, + DA850_LCD_D_12, + DA850_LCD_D_11, + DA850_LCD_D_10, + DA850_LCD_D_9, + DA850_LCD_D_8, + DA850_LCD_PCLK, + DA850_LCD_HSYNC, + DA850_LCD_VSYNC, + DA850_NLCD_AC_ENB_CS, + + /* MMC/SD0 function */ + DA850_MMCSD0_DAT_0, + DA850_MMCSD0_DAT_1, + DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, + DA850_MMCSD0_CLK, + DA850_MMCSD0_CMD, + + /* EMIF2.5/EMIFA function */ + DA850_EMA_D_7, + DA850_EMA_D_6, + DA850_EMA_D_5, + DA850_EMA_D_4, + DA850_EMA_D_3, + DA850_EMA_D_2, + DA850_EMA_D_1, + DA850_EMA_D_0, + DA850_EMA_A_1, + DA850_EMA_A_2, + DA850_NEMA_CS_3, + DA850_NEMA_CS_4, + DA850_NEMA_WE, + DA850_NEMA_OE, + DA850_EMA_D_15, + DA850_EMA_D_14, + DA850_EMA_D_13, + DA850_EMA_D_12, + DA850_EMA_D_11, + DA850_EMA_D_10, + DA850_EMA_D_9, + DA850_EMA_D_8, + DA850_EMA_A_0, + DA850_EMA_A_3, + DA850_EMA_A_4, + DA850_EMA_A_5, + DA850_EMA_A_6, + DA850_EMA_A_7, + DA850_EMA_A_8, + DA850_EMA_A_9, + DA850_EMA_A_10, + DA850_EMA_A_11, + DA850_EMA_A_12, + DA850_EMA_A_13, + DA850_EMA_A_14, + DA850_EMA_A_15, + DA850_EMA_A_16, + DA850_EMA_A_17, + DA850_EMA_A_18, + DA850_EMA_A_19, + DA850_EMA_A_20, + DA850_EMA_A_21, + DA850_EMA_A_22, + DA850_EMA_A_23, + DA850_EMA_BA_1, + DA850_EMA_CLK, + DA850_EMA_WAIT_1, + DA850_NEMA_CS_2, + + /* GPIO function */ + DA850_GPIO2_15, + DA850_GPIO8_10, + DA850_GPIO4_0, + DA850_GPIO4_1, }; #ifdef CONFIG_DAVINCI_MUX diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index ab8a2586d1c..171173c1dba 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -81,6 +81,24 @@ #define DM355_LPSC_RTO 12 #define DM355_LPSC_VPSS_DAC 41 +/* DM365 */ +#define DM365_LPSC_TIMER3 5 +#define DM365_LPSC_SPI1 6 +#define DM365_LPSC_MMC_SD1 7 +#define DM365_LPSC_McBSP1 8 +#define DM365_LPSC_PWM3 10 +#define DM365_LPSC_SPI2 11 +#define DM365_LPSC_RTO 12 +#define DM365_LPSC_TIMER4 17 +#define DM365_LPSC_SPI0 22 +#define DM365_LPSC_SPI3 38 +#define DM365_LPSC_SPI4 39 +#define DM365_LPSC_EMAC 40 +#define DM365_LPSC_VOICE_CODEC 44 +#define DM365_LPSC_DAC_CLK 46 +#define DM365_LPSC_VPSSMSTR 47 +#define DM365_LPSC_MJCP 50 + /* * LPSC Assignments */ @@ -118,6 +136,50 @@ #define DM646X_LPSC_TIMER1 35 #define DM646X_LPSC_ARM_INTC 45 +/* PSC0 defines */ +#define DA8XX_LPSC0_TPCC 0 +#define DA8XX_LPSC0_TPTC0 1 +#define DA8XX_LPSC0_TPTC1 2 +#define DA8XX_LPSC0_EMIF25 3 +#define DA8XX_LPSC0_SPI0 4 +#define DA8XX_LPSC0_MMC_SD 5 +#define DA8XX_LPSC0_AINTC 6 +#define DA8XX_LPSC0_ARM_RAM_ROM 7 +#define DA8XX_LPSC0_SECU_MGR 8 +#define DA8XX_LPSC0_UART0 9 +#define DA8XX_LPSC0_SCR0_SS 10 +#define DA8XX_LPSC0_SCR1_SS 11 +#define DA8XX_LPSC0_SCR2_SS 12 +#define DA8XX_LPSC0_DMAX 13 +#define DA8XX_LPSC0_ARM 14 +#define DA8XX_LPSC0_GEM 15 + +/* PSC1 defines */ +#define DA850_LPSC1_TPCC1 0 +#define DA8XX_LPSC1_USB20 1 +#define DA8XX_LPSC1_USB11 2 +#define DA8XX_LPSC1_GPIO 3 +#define DA8XX_LPSC1_UHPI 4 +#define DA8XX_LPSC1_CPGMAC 5 +#define DA8XX_LPSC1_EMIF3C 6 +#define DA8XX_LPSC1_McASP0 7 +#define DA830_LPSC1_McASP1 8 +#define DA850_LPSC1_SATA 8 +#define DA830_LPSC1_McASP2 9 +#define DA8XX_LPSC1_SPI1 10 +#define DA8XX_LPSC1_I2C 11 +#define DA8XX_LPSC1_UART1 12 +#define DA8XX_LPSC1_UART2 13 +#define DA8XX_LPSC1_LCDC 16 +#define DA8XX_LPSC1_PWM 17 +#define DA8XX_LPSC1_ECAP 20 +#define DA830_LPSC1_EQEP 21 +#define DA850_LPSC1_TPTC2 21 +#define DA8XX_LPSC1_SCR_P0_SS 24 +#define DA8XX_LPSC1_SCR_P1_SS 25 +#define DA8XX_LPSC1_CR_P3_SS 26 +#define DA8XX_LPSC1_L3_CBA_RAM 31 + extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, char enable); diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 794fa5cf93c..a584697a9e7 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -11,13 +11,17 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H -#include <mach/io.h> +#include <mach/hardware.h> #define DAVINCI_MAX_NR_UARTS 3 #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) +#define DA8XX_UART0_BASE (IO_PHYS + 0x042000) +#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) +#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) + /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index b7e7036674f..8e4f10fe126 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h @@ -16,12 +16,12 @@ extern void davinci_watchdog_reset(void); -static void arch_idle(void) +static inline void arch_idle(void) { cpu_do_idle(); } -static void arch_reset(char mode, const char *cmd) +static inline void arch_reset(char mode, const char *cmd) { davinci_watchdog_reset(); } diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 1e27475f9a2..33796b4db17 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -21,8 +21,11 @@ static u32 *uart; static u32 *get_uart_base(void) { - /* Add logic here for new platforms, using __macine_arch_type */ - return (u32 *)DAVINCI_UART0_BASE; + if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM || + __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) + return (u32 *)DA8XX_UART2_BASE; + else + return (u32 *)DAVINCI_UART0_BASE; } /* PORT_16C550A, in polled non-fifo mode */ diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h index ad51625b660..d49646a8e20 100644 --- a/arch/arm/mach-davinci/include/mach/vmalloc.h +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h @@ -8,7 +8,7 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include <mach/io.h> +#include <mach/hardware.h> /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ #define VMALLOC_END (IO_VIRT - (2<<20)) diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index d310f579aa8..898905e4894 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -91,3 +91,17 @@ int __init_or_module davinci_cfg_reg(const unsigned long index) return 0; } EXPORT_SYMBOL(davinci_cfg_reg); + +int da8xx_pinmux_setup(const short pins[]) +{ + int i, error = -EINVAL; + + if (pins) + for (i = 0; pins[i] >= 0; i++) { + error = davinci_cfg_reg(pins[i]); + if (error) + break; + } + + return error; +} diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c index db54b2a66b4..4f1fc9b318b 100644 --- a/arch/arm/mach-davinci/sram.c +++ b/arch/arm/mach-davinci/sram.c @@ -60,7 +60,7 @@ static int __init sram_init(void) int status = 0; if (len) { - len = min(len, SRAM_SIZE); + len = min_t(unsigned, len, SRAM_SIZE); sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); if (!sram_pool) status = -ENOMEM; diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 0884ca57bfb..0d1b6d407b4 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -406,11 +406,11 @@ struct sys_timer davinci_timer = { void davinci_watchdog_reset(void) { u32 tgcr, wdtcr; - struct davinci_soc_info *soc_info = &davinci_soc_info; - void __iomem *base = soc_info->wdt_base; + struct platform_device *pdev = &davinci_wdt_device; + void __iomem *base = IO_ADDRESS(pdev->resource[0].start); struct clk *wd_clk; - wd_clk = clk_get(&davinci_wdt_device.dev, NULL); + wd_clk = clk_get(&pdev->dev, NULL); if (WARN_ON(IS_ERR(wd_clk))) return; clk_enable(wd_clk); @@ -420,11 +420,11 @@ void davinci_watchdog_reset(void) /* reset timer, set mode to 64-bit watchdog, and unreset */ tgcr = 0; - __raw_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TGCR); tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - __raw_writel(tgcr, base + TCR); + __raw_writel(tgcr, base + TGCR); /* clear counter and period regs */ __raw_writel(0, base + TIM12); @@ -432,12 +432,8 @@ void davinci_watchdog_reset(void) __raw_writel(0, base + PRD12); __raw_writel(0, base + PRD34); - /* enable */ - wdtcr = __raw_readl(base + WDTCR); - wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT; - __raw_writel(wdtcr, base + WDTCR); - /* put watchdog in pre-active state */ + wdtcr = __raw_readl(base + WDTCR); wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); __raw_writel(wdtcr, base + WDTCR); diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index abedb633718..06f55931620 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -13,6 +13,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/cputype.h> #define DAVINCI_USB_OTG_BASE 0x01C64000 @@ -64,6 +65,10 @@ static struct resource usb_resources[] = { .start = IRQ_USBINT, .flags = IORESOURCE_IRQ, }, + { + /* placeholder for the dedicated CPPI IRQ */ + .flags = IORESOURCE_IRQ, + }, }; static u64 usb_dmamask = DMA_BIT_MASK(32); @@ -84,6 +89,14 @@ void __init setup_usb(unsigned mA, unsigned potpgt_msec) { usb_data.power = mA / 2; usb_data.potpgt = potpgt_msec / 2; + + if (cpu_is_davinci_dm646x()) { + /* Override the defaults as DM6467 uses different IRQs. */ + usb_dev.resource[1].start = IRQ_DM646X_USBINT; + usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT; + } else /* other devices don't have dedicated CPPI IRQ */ + usb_dev.num_resources = 2; + platform_device_register(&usb_dev); } |