diff options
Diffstat (limited to 'arch/arm/mach-imx/src.c')
| -rw-r--r-- | arch/arm/mach-imx/src.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 36cacbd0dcc..4bde04f99e3 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -14,19 +14,26 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/smp.h> #include <asm/unified.h> #define SRC_SCR 0x000 #define SRC_GPR1 0x020 +#define BP_SRC_SCR_WARM_RESET_ENABLE 0 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 static void __iomem *src_base; +#ifndef CONFIG_SMP +#define cpu_logical_map(cpu) 0 +#endif + void imx_enable_cpu(int cpu, bool enable) { u32 mask, val; + cpu = cpu_logical_map(cpu); mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); val = readl_relaxed(src_base + SRC_SCR); val = enable ? val | mask : val & ~mask; @@ -35,15 +42,38 @@ void imx_enable_cpu(int cpu, bool enable) void imx_set_cpu_jump(int cpu, void *jump_addr) { + cpu = cpu_logical_map(cpu); writel_relaxed(BSYM(virt_to_phys(jump_addr)), src_base + SRC_GPR1 + cpu * 8); } +void imx_src_prepare_restart(void) +{ + u32 val; + + /* clear enable bits of secondary cores */ + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); + + /* clear persistent entry register of primary core */ + writel_relaxed(0, src_base + SRC_GPR1); +} + void __init imx_src_init(void) { struct device_node *np; + u32 val; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); src_base = of_iomap(np, 0); WARN_ON(!src_base); + + /* + * force warm reset sources to generate cold reset + * for a more reliable restart + */ + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); } |