diff options
Diffstat (limited to 'arch/arm/mach-lpc32xx')
| -rw-r--r-- | arch/arm/mach-lpc32xx/clock.c | 62 | ||||
| -rw-r--r-- | arch/arm/mach-lpc32xx/common.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-lpc32xx/include/mach/platform.h | 51 | ||||
| -rw-r--r-- | arch/arm/mach-lpc32xx/phy3250.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-lpc32xx/pm.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-lpc32xx/timer.c | 48 |
6 files changed, 75 insertions, 91 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 473015ac07b..ab8c2164742 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -82,6 +82,7 @@ * will also impact the individual peripheral rates. */ +#include <linux/export.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/errno.h> @@ -97,9 +98,10 @@ #include "clock.h" #include "common.h" +static DEFINE_SPINLOCK(global_clkregs_lock); + static struct clk clk_armpll; static struct clk clk_usbpll; -static DEFINE_MUTEX(clkm_lock); /* * Post divider values for PLLs based on selected register value @@ -127,7 +129,7 @@ static struct clk osc_32KHz = { static int local_pll397_enable(struct clk *clk, int enable) { u32 reg; - unsigned long timeout = 1 + msecs_to_jiffies(10); + unsigned long timeout = jiffies + msecs_to_jiffies(10); reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL); @@ -142,7 +144,7 @@ static int local_pll397_enable(struct clk *clk, int enable) /* Wait for PLL397 lock */ while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) && - (timeout > jiffies)) + time_before(jiffies, timeout)) cpu_relax(); if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & @@ -156,7 +158,7 @@ static int local_pll397_enable(struct clk *clk, int enable) static int local_oscmain_enable(struct clk *clk, int enable) { u32 reg; - unsigned long timeout = 1 + msecs_to_jiffies(10); + unsigned long timeout = jiffies + msecs_to_jiffies(10); reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL); @@ -171,7 +173,7 @@ static int local_oscmain_enable(struct clk *clk, int enable) /* Wait for main oscillator to start */ while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & LPC32XX_CLKPWR_MOSC_DISABLE) != 0) && - (timeout > jiffies)) + time_before(jiffies, timeout)) cpu_relax(); if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & @@ -383,7 +385,7 @@ static int local_usbpll_enable(struct clk *clk, int enable) { u32 reg; int ret = -ENODEV; - unsigned long timeout = 1 + msecs_to_jiffies(10); + unsigned long timeout = jiffies + msecs_to_jiffies(10); reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); @@ -396,7 +398,7 @@ static int local_usbpll_enable(struct clk *clk, int enable) __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); /* Wait for PLL lock */ - while ((timeout > jiffies) & (ret == -ENODEV)) { + while (time_before(jiffies, timeout) && (ret == -ENODEV)) { reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS) ret = 0; @@ -926,20 +928,8 @@ static struct clk clk_lcd = { .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN, }; -static inline void clk_lock(void) -{ - mutex_lock(&clkm_lock); -} - -static inline void clk_unlock(void) -{ - mutex_unlock(&clkm_lock); -} - static void local_clk_disable(struct clk *clk) { - WARN_ON(clk->usecount == 0); - /* Don't attempt to disable clock if it has no users */ if (clk->usecount > 0) { clk->usecount--; @@ -982,10 +972,11 @@ static int local_clk_enable(struct clk *clk) int clk_enable(struct clk *clk) { int ret; + unsigned long flags; - clk_lock(); + spin_lock_irqsave(&global_clkregs_lock, flags); ret = local_clk_enable(clk); - clk_unlock(); + spin_unlock_irqrestore(&global_clkregs_lock, flags); return ret; } @@ -996,9 +987,11 @@ EXPORT_SYMBOL(clk_enable); */ void clk_disable(struct clk *clk) { - clk_lock(); + unsigned long flags; + + spin_lock_irqsave(&global_clkregs_lock, flags); local_clk_disable(clk); - clk_unlock(); + spin_unlock_irqrestore(&global_clkregs_lock, flags); } EXPORT_SYMBOL(clk_disable); @@ -1007,13 +1000,7 @@ EXPORT_SYMBOL(clk_disable); */ unsigned long clk_get_rate(struct clk *clk) { - unsigned long rate; - - clk_lock(); - rate = clk->get_rate(clk); - clk_unlock(); - - return rate; + return clk->get_rate(clk); } EXPORT_SYMBOL(clk_get_rate); @@ -1029,11 +1016,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate) * the actual rate set as part of the peripheral dividers * instead of high level clock control */ - if (clk->set_rate) { - clk_lock(); + if (clk->set_rate) ret = clk->set_rate(clk, rate); - clk_unlock(); - } return ret; } @@ -1044,15 +1028,11 @@ EXPORT_SYMBOL(clk_set_rate); */ long clk_round_rate(struct clk *clk, unsigned long rate) { - clk_lock(); - if (clk->round_rate) rate = clk->round_rate(clk, rate); else rate = clk->get_rate(clk); - clk_unlock(); - return rate; } EXPORT_SYMBOL(clk_round_rate); @@ -1110,11 +1090,11 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1) _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan) _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand) + _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0) + _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1) _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc) - _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0) - _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1) _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc) - _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc) + _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc) _REGISTER_CLOCK("lpc-net.0", NULL, clk_net) _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd) _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd) diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 04b72739eb9..68f2e46d98a 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -66,7 +66,6 @@ extern u32 clk_get_pclk_div(void); */ extern void lpc32xx_get_uid(u32 devid[4]); -extern void lpc32xx_watchdog_reset(void); extern u32 lpc32xx_return_iram_size(void); /* diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index 14ea8d1aadb..c584f5bb164 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -591,42 +591,42 @@ /* * Timer/counter register offsets */ -#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00) -#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04) -#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08) -#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C) -#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10) -#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14) -#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18) -#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) -#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20) -#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24) -#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28) -#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) -#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30) -#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34) -#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38) -#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) -#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) +#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) +#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) +#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) +#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) +#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) +#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) +#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) +#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) +#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) +#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) +#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) +#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) +#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) +#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) +#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) +#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) +#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) /* * ir register definitions */ -#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) -#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) +#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) +#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) /* * tcr register definitions */ -#define LCP32XX_TIMER_CNTR_TCR_EN 0x1 -#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2 +#define LPC32XX_TIMER_CNTR_TCR_EN 0x1 +#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 /* * mcr register definitions */ -#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) -#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) -#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) +#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) +#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) +#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) /* * Standard UART register offsets @@ -690,5 +690,8 @@ #define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) #define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) #define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) +#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) +#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) +#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) #endif diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index a2f0d4e3f77..4590a8b52e7 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -271,6 +271,8 @@ static struct platform_device lpc32xx_gpio_led_device = { }; static struct platform_device *phy3250_devs[] __initdata = { + &lpc32xx_rtc_device, + &lpc32xx_tsc_device, &lpc32xx_i2c0_device, &lpc32xx_i2c1_device, &lpc32xx_i2c2_device, diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index b9c80597b7b..207e81275ff 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -13,7 +13,7 @@ /* * LPC32XX CPU and system power management * - * The LCP32XX has three CPU modes for controlling system power: run, + * The LPC32XX has three CPU modes for controlling system power: run, * direct-run, and halt modes. When switching between halt and run modes, * the CPU transistions through direct-run mode. For Linux, direct-run * mode is not used in normal operation. Halt mode is used when the diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index b42c909bbee..c40667c3316 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -34,11 +34,11 @@ static int lpc32xx_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) { - __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET, - LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, - LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, + LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); + __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, + LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); return 0; } @@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode, * disable the timer to wait for the first call to * set_next_event(). */ - __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); break; case CLOCK_EVT_MODE_UNUSED: @@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &lpc32xx_clkevt; /* Clear match */ - __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0), - LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); + __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), + LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); evt->event_handler(evt); @@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void) clkrate = clkrate / clk_get_pclk_div(); /* Initial timer setup */ - __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0), - LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); - __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) | - LCP32XX_TIMER_CNTR_MCR_STOP(0) | - LCP32XX_TIMER_CNTR_MCR_RESET(0), - LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE)); + __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); + __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), + LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE)); + __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); + __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) | + LPC32XX_TIMER_CNTR_MCR_STOP(0) | + LPC32XX_TIMER_CNTR_MCR_RESET(0), + LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE)); /* Setup tick interrupt */ setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); @@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void) clockevents_register_device(&lpc32xx_clkevt); /* Use timer1 as clock source. */ - __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET, - LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); - __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE)); - __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); - __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, - LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); - - clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE), + __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, + LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); + __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE)); + __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); + __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, + LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); + + clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE), "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up); } |