diff options
Diffstat (limited to 'arch/arm/mach-mmp')
31 files changed, 1512 insertions, 39 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index c6a564fc4a7..6ab843eaa35 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -1,6 +1,6 @@ if ARCH_MMP -menu "Marvell PXA168/910 Implmentations" +menu "Marvell PXA168/910/MMP2 Implmentations" config MACH_ASPENITE bool "Marvell's PXA168 Aspenite Development Board" @@ -16,6 +16,13 @@ config MACH_ZYLONITE2 Say 'Y' here if you want to support the Marvell PXA168-based Zylonite2 Development Board. +config MACH_AVENGERS_LITE + bool "Marvell's PXA168 Avengers Lite Development Board" + select CPU_PXA168 + help + Say 'Y' here if you want to support the Marvell PXA168-based + Avengers Lite Development Board. + config MACH_TAVOREVB bool "Marvell's PXA910 TavorEVB Development Board" select CPU_PXA910 @@ -30,6 +37,26 @@ config MACH_TTC_DKB Say 'Y' here if you want to support the Marvell PXA910-based TTC_DKB Development Board. +config MACH_FLINT + bool "Marvell's Flint Development Platform" + select CPU_MMP2 + help + Say 'Y' here if you want to support the Marvell MMP2-based + Flint Development Platform. + MMP2-based board can't be co-existed with PXA168-based & + PXA910-based development board. Since MMP2 is compatible to + ARMv6 architecture. + +config MACH_MARVELL_JASPER + bool "Marvell's Jasper Development Platform" + select CPU_MMP2 + help + Say 'Y' here if you want to support the Marvell MMP2-base + Jasper Development Platform. + MMP2-based board can't be co-existed with PXA168-based & + PXA910-based development board. Since MMP2 is compatible to + ARMv6 architecture. + endmenu config CPU_PXA168 @@ -44,4 +71,10 @@ config CPU_PXA910 help Select code specific to PXA910 +config CPU_MMP2 + bool + select CPU_V6 + select CPU_32v6K + help + Select code specific to MMP2. MMP2 is ARMv6 compatible. endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 6883e658488..8b66d06739c 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -2,14 +2,18 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o irq.o time.o +obj-y += common.o clock.o devices.o time.o # SoC support -obj-$(CONFIG_CPU_PXA168) += pxa168.o -obj-$(CONFIG_CPU_PXA910) += pxa910.o +obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o +obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o +obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o +obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o +obj-$(CONFIG_MACH_FLINT) += flint.o +obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index a2d307ec042..244655d323e 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -59,6 +59,13 @@ static unsigned long common_pin_config[] __initdata = { /* UART1 */ GPIO107_UART1_RXD, GPIO108_UART1_TXD, + + /* SSP1 */ + GPIO113_I2S_MCLK, + GPIO114_I2S_FRM, + GPIO115_I2S_BCLK, + GPIO116_I2S_RXD, + GPIO117_I2S_TXD, }; static struct smc91x_platdata smc91x_info = { @@ -123,12 +130,18 @@ static struct pxa3xx_nand_platform_data aspenite_nand_info = { .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), }; +static struct i2c_board_info aspenite_i2c_info[] __initdata = { + { I2C_BOARD_INFO("wm8753", 0x1b), }, +}; + static void __init common_init(void) { mfp_config(ARRAY_AND_SIZE(common_pin_config)); /* on-chip devices */ pxa168_add_uart(1); + pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info)); + pxa168_add_ssp(1); pxa168_add_nand(&aspenite_nand_info); /* off-chip devices */ diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c new file mode 100644 index 00000000000..8c3fa5d14f4 --- /dev/null +++ b/arch/arm/mach-mmp/avengers_lite.c @@ -0,0 +1,51 @@ +/* + * linux/arch/arm/mach-mmp/avengers_lite.c + * + * Support for the Marvell PXA168-based Avengers lite Development Platform. + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-pxa168.h> +#include <mach/pxa168.h> +#include <mach/irqs.h> + + +#include "common.h" +#include <linux/delay.h> + +/* Avengers lite MFP configurations */ +static unsigned long avengers_lite_pin_config_V16F[] __initdata = { + /* DEBUG_UART */ + GPIO88_UART2_TXD, + GPIO89_UART2_RXD, +}; + +static void __init avengers_lite_init(void) +{ + mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F)); + + /* on-chip devices */ + pxa168_add_uart(2); +} + +MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa168_init_irq, + .timer = &pxa168_timer, + .init_machine = avengers_lite_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c index 2a46ed5cc2a..886e05648f0 100644 --- a/arch/arm/mach-mmp/clock.c +++ b/arch/arm/mach-mmp/clock.c @@ -88,11 +88,3 @@ unsigned long clk_get_rate(struct clk *clk) return rate; } EXPORT_SYMBOL(clk_get_rate); - -void clks_register(struct clk_lookup *clks, size_t num) -{ - int i; - - for (i = 0; i < num; i++) - clkdev_add(&clks[i]); -} diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index eefffbe683b..016ae94691c 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h @@ -68,5 +68,3 @@ struct clk clk_##_name = { \ extern struct clk clk_pxa168_gpio; extern struct clk clk_pxa168_timers; - -extern void clks_register(struct clk_lookup *, size_t); diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index c33fbbc4941..b4a0ba05a0f 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -3,11 +3,15 @@ struct sys_timer; extern void timer_init(int irq); +extern void mmp2_clear_pmic_int(void); extern struct sys_timer pxa168_timer; extern struct sys_timer pxa910_timer; +extern struct sys_timer mmp2_timer; extern void __init pxa168_init_irq(void); extern void __init pxa910_init_irq(void); +extern void __init mmp2_init_icu(void); +extern void __init mmp2_init_irq(void); extern void __init icu_init_irq(void); extern void __init pxa_map_io(void); diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c new file mode 100644 index 00000000000..4ec7709a346 --- /dev/null +++ b/arch/arm/mach-mmp/flint.c @@ -0,0 +1,123 @@ +/* + * linux/arch/arm/mach-mmp/flint.c + * + * Support for the Marvell Flint Development Platform. + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/smc91x.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-mmp2.h> +#include <mach/mmp2.h> + +#include "common.h" + +static unsigned long flint_pin_config[] __initdata = { + /* UART1 */ + GPIO45_UART1_RXD, + GPIO46_UART1_TXD, + + /* UART2 */ + GPIO47_UART2_RXD, + GPIO48_UART2_TXD, + + /* SMC */ + GPIO151_SMC_SCLK, + GPIO145_SMC_nCS0, + GPIO146_SMC_nCS1, + GPIO152_SMC_BE0, + GPIO153_SMC_BE1, + GPIO154_SMC_IRQ, + GPIO113_SMC_RDY, + + /*Ethernet*/ + GPIO155_GPIO155, + + /* DFI */ + GPIO168_DFI_D0, + GPIO167_DFI_D1, + GPIO166_DFI_D2, + GPIO165_DFI_D3, + GPIO107_DFI_D4, + GPIO106_DFI_D5, + GPIO105_DFI_D6, + GPIO104_DFI_D7, + GPIO111_DFI_D8, + GPIO164_DFI_D9, + GPIO163_DFI_D10, + GPIO162_DFI_D11, + GPIO161_DFI_D12, + GPIO110_DFI_D13, + GPIO109_DFI_D14, + GPIO108_DFI_D15, + GPIO143_ND_nCS0, + GPIO144_ND_nCS1, + GPIO147_ND_nWE, + GPIO148_ND_nRE, + GPIO150_ND_ALE, + GPIO149_ND_CLE, + GPIO112_ND_RDY0, + GPIO160_ND_RDY1, +}; + +static struct smc91x_platdata flint_smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_resources[] = { + [0] = { + .start = SMC_CS1_PHYS_BASE + 0x300, + .end = SMC_CS1_PHYS_BASE + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gpio_to_irq(155), + .end = gpio_to_irq(155), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + } +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .dev = { + .platform_data = &flint_smc91x_info, + }, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static void __init flint_init(void) +{ + mfp_config(ARRAY_AND_SIZE(flint_pin_config)); + + /* on-chip devices */ + mmp2_add_uart(1); + mmp2_add_uart(2); + + /* off-chip devices */ + platform_device_register(&smc91x_device); +} + +MACHINE_START(FLINT, "Flint Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = mmp2_init_irq, + .timer = &mmp2_timer, + .init_machine = flint_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h index 25e797b0908..83b18721d93 100644 --- a/arch/arm/mach-mmp/include/mach/cputype.h +++ b/arch/arm/mach-mmp/include/mach/cputype.h @@ -8,6 +8,7 @@ * * PXA168 A0 0x41159263 0x56158400 0x00A0A333 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 + * MMP2 Z0 0x560f5811 */ #ifdef CONFIG_CPU_PXA168 @@ -24,7 +25,15 @@ # define __cpu_is_pxa910(id) (0) #endif +#ifdef CONFIG_CPU_MMP2 +# define __cpu_is_mmp2(id) \ + ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; }) +#else +# define __cpu_is_mmp2(id) (0) +#endif + #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) #define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) +#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); }) #endif /* __ASM_MACH_CPUTYPE_H */ diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S index a850f87de51..76deff238e1 100644 --- a/arch/arm/mach-mmp/include/mach/debug-macro.S +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S @@ -11,7 +11,7 @@ #include <mach/addr-map.h> - .macro addruart,rx + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? ldreq \rx, =APB_PHYS_BASE @ physical diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index 24585397217..1fa0a492454 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -34,4 +34,16 @@ struct pxa_device_desc pxa910_device_##_name __initdata = { \ .size = _size, \ .dma = { _dma }, \ }; + +#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ +struct pxa_device_desc mmp2_device_##_name __initdata = { \ + .dev_name = "mmp2-" #_name, \ + .drv_name = _drv, \ + .id = _id, \ + .irq = IRQ_MMP2_##_irq, \ + .start = _start, \ + .size = _size, \ + .dma = { _dma }, \ +} + extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S index 6d3cd35478b..c42d9d4e892 100644 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S @@ -15,7 +15,12 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =ICU_AP_IRQ_SEL_INT_NUM + mrc p15, 0, \tmp, c0, c0, 0 @ CPUID + and \tmp, \tmp, #0xff00 + cmp \tmp, #0x5800 + ldr \base, =ICU_VIRT_BASE + addne \base, \base, #0x10c @ PJ1 AP INT SEL register + addeq \base, \base, #0x104 @ PJ4 IRQ SEL register .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h index ab26d13295c..ee8b02ed801 100644 --- a/arch/arm/mach-mmp/include/mach/gpio.h +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -10,7 +10,7 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) -#define NR_BUILTIN_GPIO (128) +#define NR_BUILTIN_GPIO (192) #define gpio_to_bank(gpio) ((gpio) >> 5) #define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index d68871b0f28..b379cdec4d3 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -5,10 +5,10 @@ * Interrupt numbers for PXA168 */ #define IRQ_PXA168_NONE (-1) -#define IRQ_PXA168_SSP3 0 -#define IRQ_PXA168_SSP2 1 -#define IRQ_PXA168_SSP1 2 -#define IRQ_PXA168_SSP0 3 +#define IRQ_PXA168_SSP4 0 +#define IRQ_PXA168_SSP3 1 +#define IRQ_PXA168_SSP2 2 +#define IRQ_PXA168_SSP1 3 #define IRQ_PXA168_PMIC_INT 4 #define IRQ_PXA168_RTC_INT 5 #define IRQ_PXA168_RTC_ALARM 6 @@ -20,7 +20,7 @@ #define IRQ_PXA168_TIMER2 14 #define IRQ_PXA168_TIMER3 15 #define IRQ_PXA168_CMU 16 -#define IRQ_PXA168_SSP4 17 +#define IRQ_PXA168_SSP5 17 #define IRQ_PXA168_MSP_WAKEUP 19 #define IRQ_PXA168_CF_WAKEUP 20 #define IRQ_PXA168_XD_WAKEUP 21 @@ -113,10 +113,119 @@ #define IRQ_PXA910_AP_PMU 60 #define IRQ_PXA910_SM_INT 63 /* from PinMux */ -#define IRQ_GPIO_START 64 -#define IRQ_GPIO_NUM 128 +/* + * Interrupt numbers for MMP2 + */ +#define IRQ_MMP2_NONE (-1) +#define IRQ_MMP2_SSP1 0 +#define IRQ_MMP2_SSP2 1 +#define IRQ_MMP2_SSPA1 2 +#define IRQ_MMP2_SSPA2 3 +#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ +#define IRQ_MMP2_RTC_MUX 5 +#define IRQ_MMP2_TWSI1 7 +#define IRQ_MMP2_GPU 8 +#define IRQ_MMP2_KEYPAD 9 +#define IRQ_MMP2_ROTARY 10 +#define IRQ_MMP2_TRACKBALL 11 +#define IRQ_MMP2_ONEWIRE 12 +#define IRQ_MMP2_TIMER1 13 +#define IRQ_MMP2_TIMER2 14 +#define IRQ_MMP2_TIMER3 15 +#define IRQ_MMP2_RIPC 16 +#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ +#define IRQ_MMP2_HDMI 19 +#define IRQ_MMP2_SSP3 20 +#define IRQ_MMP2_SSP4 21 +#define IRQ_MMP2_USB_HS1 22 +#define IRQ_MMP2_USB_HS2 23 +#define IRQ_MMP2_UART3 24 +#define IRQ_MMP2_UART1 27 +#define IRQ_MMP2_UART2 28 +#define IRQ_MMP2_MIPI_DSI 29 +#define IRQ_MMP2_CI2 30 +#define IRQ_MMP2_PMU_TIMER1 31 +#define IRQ_MMP2_PMU_TIMER2 32 +#define IRQ_MMP2_PMU_TIMER3 33 +#define IRQ_MMP2_USB_FS 34 +#define IRQ_MMP2_MISC_MUX 35 +#define IRQ_MMP2_WDT1 36 +#define IRQ_MMP2_NAND_DMA 37 +#define IRQ_MMP2_USIM 38 +#define IRQ_MMP2_MMC 39 +#define IRQ_MMP2_WTM 40 +#define IRQ_MMP2_LCD 41 +#define IRQ_MMP2_CI 42 +#define IRQ_MMP2_IRE 43 +#define IRQ_MMP2_USB_OTG 44 +#define IRQ_MMP2_NAND 45 +#define IRQ_MMP2_UART4 46 +#define IRQ_MMP2_DMA_FIQ 47 +#define IRQ_MMP2_DMA_RIQ 48 +#define IRQ_MMP2_GPIO 49 +#define IRQ_MMP2_SSP_MUX 51 +#define IRQ_MMP2_MMC2 52 +#define IRQ_MMP2_MMC3 53 +#define IRQ_MMP2_MMC4 54 +#define IRQ_MMP2_MIPI_HSI 55 +#define IRQ_MMP2_MSP 58 +#define IRQ_MMP2_MIPI_SLIM_DMA 59 +#define IRQ_MMP2_PJ4_FREQ_CHG 60 +#define IRQ_MMP2_MIPI_SLIM 62 +#define IRQ_MMP2_SM 63 + +#define IRQ_MMP2_MUX_BASE 64 + +/* secondary interrupt of INT #4 */ +#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) +#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) +#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) + +/* secondary interrupt of INT #5 */ +#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) +#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) +#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) + +/* secondary interrupt of INT #17 */ +#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) +#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) +#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) +#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) +#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) + +/* secondary interrupt of INT #35 */ +#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) +#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) +#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) +#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) +#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) +#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) +#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) +#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) +#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) +#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) +#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) +#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) +#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) +#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) +#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) + +/* secondary interrupt of INT #51 */ +#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15) +#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0) +#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1) + +#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) + +#define IRQ_GPIO_START 128 +#define IRQ_GPIO_NUM 192 #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) -#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) +/* Board IRQ - 64 by default, increase if not enough */ +#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM) +#define IRQ_BOARD_END (IRQ_BOARD_START + 64) + +#define NR_IRQS (IRQ_BOARD_END) #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h new file mode 100644 index 00000000000..761c2dacc07 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h @@ -0,0 +1,395 @@ +#ifndef __ASM_MACH_MFP_MMP2_H +#define __ASM_MACH_MFP_MMP2_H + +#include <mach/mfp.h> + +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + +/* GPIO */ +#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) +#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) +#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0) +#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0) +#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) +#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) +#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) +#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0) +#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1) +#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1) +#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1) +#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1) +#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1) +#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1) +#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1) +#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1) +#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1) +#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1) +#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1) +#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1) +#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0) +#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0) +#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0) +#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0) +#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0) +#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0) +#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0) +#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0) +#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0) +#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0) +#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0) +#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0) +#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0) +#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0) +#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0) +#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1) +#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1) +#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1) +#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1) +#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1) +#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1) +#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1) +#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1) +#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1) +#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1) +#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1) +#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1) +#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1) +#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) +#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1) +#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1) +#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1) +#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1) +#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1) +#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1) +#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1) +#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1) +#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1) +#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1) +#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1) +#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1) +#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1) + +/* DFI */ +#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) +#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0) +#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0) +#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0) +#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0) +#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0) +#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0) +#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0) +#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0) +#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0) +#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0) +#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0) +#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0) +#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0) +#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0) +#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0) +#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0) +#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0) +#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0) +#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0) +#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0) +#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0) +#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0) +#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0) + +/* Static Memory Controller */ +#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0) +#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0) +#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0) +#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0) +#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0) +#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0) +#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0) + +/* Ethernet */ +#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2) + +/* UART1 */ +#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1) +#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1) +#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1) +#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1) +#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1) +#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1) + +/* UART2 */ +#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1) +#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1) +#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1) +#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1) + +/* UART3 */ +#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1) +#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1) +#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1) +#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1) + +/* MMC1 */ +#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST) +#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST) +#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST) +#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST) +#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST) +#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST) +#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST) +#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST) +#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST) +#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST) +#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST) +#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST) + +/*MMC2*/ +#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST) +#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST) +#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST) +#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST) +#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST) +#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST) + +/*MMC3*/ +#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST) +#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST) +#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST) +#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST) +#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST) +#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST) +#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST) +#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST) +#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST) +#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST) + +/* LCD */ +#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST) +#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST) +#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST) +#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST) +#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST) +#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST) +#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST) +#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST) +#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST) +#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST) +#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST) +#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST) +#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST) +#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST) +#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST) +#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST) +#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST) +#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST) +#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST) +#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST) +#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST) +#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST) +#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST) +#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST) +#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST) +#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST) +#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST) +#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST) +#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST) +#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST) +#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST) +#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST) +#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST) + +#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST) + +/*LCD TV path*/ +#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST) +#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST) +#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST) +#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST) +#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST) +#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST) +#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST) +#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST) +#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST) +#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST) +#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST) +#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST) + +/* I2C */ +#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW) +#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW) +#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW) +#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW) +#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW) +#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW) +#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW) +#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW) +#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW) +#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW) + +/* SSPA1 */ +#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1) +#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1) +#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1) +#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1) + +/* SSPA2 */ +#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1) +#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1) +#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1) +#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1) + +/* Keypad */ +#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) +#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) +#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) +#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) +#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) +#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) +#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) +#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) +#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) +#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) +#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) +#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) +#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) +#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) +#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) +#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) +#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) +#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) +#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) +#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) +#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1) +#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1) +#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1) +#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1) + +/* CAMERA */ +#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST) +#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST) +#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST) +#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST) +#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST) +#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST) +#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST) +#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST) +#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST) +#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST) +#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST) +#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST) + +/* PMIC */ +#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0) + +#endif /* __ASM_MACH_MFP_MMP2_H */ + diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index 3b216bf41e7..ded43c455ec 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -193,7 +193,9 @@ #define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3) #define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3) -/* UART1 */ +/* UART */ +#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2) +#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2) #define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST) #define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST) #define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST) diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h new file mode 100644 index 00000000000..fec220bd504 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -0,0 +1,60 @@ +#ifndef __ASM_MACH_MMP2_H +#define __ASM_MACH_MMP2_H + +#include <linux/i2c.h> +#include <mach/devices.h> +#include <plat/i2c.h> + +extern struct pxa_device_desc mmp2_device_uart1; +extern struct pxa_device_desc mmp2_device_uart2; +extern struct pxa_device_desc mmp2_device_uart3; +extern struct pxa_device_desc mmp2_device_uart4; +extern struct pxa_device_desc mmp2_device_twsi1; +extern struct pxa_device_desc mmp2_device_twsi2; +extern struct pxa_device_desc mmp2_device_twsi3; +extern struct pxa_device_desc mmp2_device_twsi4; +extern struct pxa_device_desc mmp2_device_twsi5; +extern struct pxa_device_desc mmp2_device_twsi6; + +static inline int mmp2_add_uart(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &mmp2_device_uart1; break; + case 2: d = &mmp2_device_uart2; break; + case 3: d = &mmp2_device_uart3; break; + case 4: d = &mmp2_device_uart4; break; + default: + return -EINVAL; + } + + return pxa_register_device(d, NULL, 0); +} + +static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, + struct i2c_board_info *info, unsigned size) +{ + struct pxa_device_desc *d = NULL; + int ret; + + switch (id) { + case 1: d = &mmp2_device_twsi1; break; + case 2: d = &mmp2_device_twsi2; break; + case 3: d = &mmp2_device_twsi3; break; + case 4: d = &mmp2_device_twsi4; break; + case 5: d = &mmp2_device_twsi5; break; + case 6: d = &mmp2_device_twsi6; break; + default: + return -EINVAL; + } + + ret = i2c_register_board_info(id - 1, info, size); + if (ret) + return ret; + + return pxa_register_device(d, data, sizeof(*data)); +} + +#endif /* __ASM_MACH_MMP2_H */ + diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 3ad612cbdf0..3b2bd5d5eb0 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -14,6 +14,11 @@ extern struct pxa_device_desc pxa168_device_pwm1; extern struct pxa_device_desc pxa168_device_pwm2; extern struct pxa_device_desc pxa168_device_pwm3; extern struct pxa_device_desc pxa168_device_pwm4; +extern struct pxa_device_desc pxa168_device_ssp1; +extern struct pxa_device_desc pxa168_device_ssp2; +extern struct pxa_device_desc pxa168_device_ssp3; +extern struct pxa_device_desc pxa168_device_ssp4; +extern struct pxa_device_desc pxa168_device_ssp5; extern struct pxa_device_desc pxa168_device_nand; static inline int pxa168_add_uart(int id) @@ -67,6 +72,22 @@ static inline int pxa168_add_pwm(int id) return pxa_register_device(d, NULL, 0); } +static inline int pxa168_add_ssp(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &pxa168_device_ssp1; break; + case 2: d = &pxa168_device_ssp2; break; + case 3: d = &pxa168_device_ssp3; break; + case 4: d = &pxa168_device_ssp4; break; + case 5: d = &pxa168_device_ssp5; break; + default: + return -EINVAL; + } + return pxa_register_device(d, NULL, 0); +} + static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info) { return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 98ccbee4bd0..1a96585336b 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -26,8 +26,6 @@ #define APBC_PXA168_PWM2 APBC_REG(0x010) #define APBC_PXA168_PWM3 APBC_REG(0x014) #define APBC_PXA168_PWM4 APBC_REG(0x018) -#define APBC_PXA168_SSP1 APBC_REG(0x01c) -#define APBC_PXA168_SSP2 APBC_REG(0x020) #define APBC_PXA168_RTC APBC_REG(0x028) #define APBC_PXA168_TWSI0 APBC_REG(0x02c) #define APBC_PXA168_KPC APBC_REG(0x030) @@ -35,14 +33,16 @@ #define APBC_PXA168_AIB APBC_REG(0x03c) #define APBC_PXA168_SW_JTAG APBC_REG(0x040) #define APBC_PXA168_ONEWIRE APBC_REG(0x048) -#define APBC_PXA168_SSP3 APBC_REG(0x04c) #define APBC_PXA168_ASFAR APBC_REG(0x050) #define APBC_PXA168_ASSAR APBC_REG(0x054) -#define APBC_PXA168_SSP4 APBC_REG(0x058) -#define APBC_PXA168_SSP5 APBC_REG(0x05c) #define APBC_PXA168_TWSI1 APBC_REG(0x06c) #define APBC_PXA168_UART3 APBC_REG(0x070) #define APBC_PXA168_AC97 APBC_REG(0x084) +#define APBC_PXA168_SSP1 APBC_REG(0x81c) +#define APBC_PXA168_SSP2 APBC_REG(0x820) +#define APBC_PXA168_SSP3 APBC_REG(0x84c) +#define APBC_PXA168_SSP4 APBC_REG(0x858) +#define APBC_PXA168_SSP5 APBC_REG(0x85c) /* * APB Clock register offsets for PXA910 @@ -69,6 +69,47 @@ #define APBC_PXA910_ASFAR APBC_REG(0x050) #define APBC_PXA910_ASSAR APBC_REG(0x054) +/* + * APB Clock register offsets for MMP2 + */ +#define APBC_MMP2_RTC APBC_REG(0x000) +#define APBC_MMP2_TWSI1 APBC_REG(0x004) +#define APBC_MMP2_TWSI2 APBC_REG(0x008) +#define APBC_MMP2_TWSI3 APBC_REG(0x00c) +#define APBC_MMP2_TWSI4 APBC_REG(0x010) +#define APBC_MMP2_ONEWIRE APBC_REG(0x014) +#define APBC_MMP2_KPC APBC_REG(0x018) +#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) +#define APBC_MMP2_SW_JTAG APBC_REG(0x020) +#define APBC_MMP2_TIMERS APBC_REG(0x024) +#define APBC_MMP2_UART1 APBC_REG(0x02c) +#define APBC_MMP2_UART2 APBC_REG(0x030) +#define APBC_MMP2_UART3 APBC_REG(0x034) +#define APBC_MMP2_GPIO APBC_REG(0x038) +#define APBC_MMP2_PWM0 APBC_REG(0x03c) +#define APBC_MMP2_PWM1 APBC_REG(0x040) +#define APBC_MMP2_PWM2 APBC_REG(0x044) +#define APBC_MMP2_PWM3 APBC_REG(0x048) +#define APBC_MMP2_SSP0 APBC_REG(0x04c) +#define APBC_MMP2_SSP1 APBC_REG(0x050) +#define APBC_MMP2_SSP2 APBC_REG(0x054) +#define APBC_MMP2_SSP3 APBC_REG(0x058) +#define APBC_MMP2_SSP4 APBC_REG(0x05c) +#define APBC_MMP2_SSP5 APBC_REG(0x060) +#define APBC_MMP2_AIB APBC_REG(0x064) +#define APBC_MMP2_ASFAR APBC_REG(0x068) +#define APBC_MMP2_ASSAR APBC_REG(0x06c) +#define APBC_MMP2_USIM APBC_REG(0x070) +#define APBC_MMP2_MPMU APBC_REG(0x074) +#define APBC_MMP2_IPC APBC_REG(0x078) +#define APBC_MMP2_TWSI5 APBC_REG(0x07c) +#define APBC_MMP2_TWSI6 APBC_REG(0x080) +#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) +#define APBC_MMP2_UART4 APBC_REG(0x088) +#define APBC_MMP2_RIPC APBC_REG(0x08c) +#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ +#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) + /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h index e5f08723e0c..f882d91894b 100644 --- a/arch/arm/mach-mmp/include/mach/regs-icu.h +++ b/arch/arm/mach-mmp/include/mach/regs-icu.h @@ -17,10 +17,12 @@ #define ICU_REG(x) (ICU_VIRT_BASE + (x)) #define ICU_INT_CONF(n) ICU_REG((n) << 2) +#define ICU_INT_CONF_MASK (0xf) + +/************ PXA168/PXA910 (MMP) *********************/ #define ICU_INT_CONF_AP_INT (1 << 6) #define ICU_INT_CONF_CP_INT (1 << 5) #define ICU_INT_CONF_IRQ (1 << 4) -#define ICU_INT_CONF_MASK (0xf) #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ @@ -28,4 +30,42 @@ #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ +/************************** MMP2 ***********************/ + +/* + * IRQ0/FIQ0 is routed to SP IRQ/FIQ. + * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ. + */ +#define ICU_INT_ROUTE_SP_IRQ (1 << 4) +#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5) +#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6) + +#define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138) +#define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c) +#define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140) +#define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144) + +#define MMP2_ICU_INT4_STATUS ICU_REG(0x150) +#define MMP2_ICU_INT5_STATUS ICU_REG(0x154) +#define MMP2_ICU_INT17_STATUS ICU_REG(0x158) +#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c) +#define MMP2_ICU_INT51_STATUS ICU_REG(0x160) + +#define MMP2_ICU_INT4_MASK ICU_REG(0x168) +#define MMP2_ICU_INT5_MASK ICU_REG(0x16C) +#define MMP2_ICU_INT17_MASK ICU_REG(0x170) +#define MMP2_ICU_INT35_MASK ICU_REG(0x174) +#define MMP2_ICU_INT51_MASK ICU_REG(0x178) + +#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100) +#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104) +#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108) + +#define MMP2_ICU_INVERT ICU_REG(0x164) + +#define MMP2_ICU_INV_PMIC (1 << 0) +#define MMP2_ICU_INV_PERF (1 << 1) +#define MMP2_ICU_INV_COMMTX (1 << 2) +#define MMP2_ICU_INV_COMMRX (1 << 3) + #endif /* __ASM_MACH_ICU_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-smc.h b/arch/arm/mach-mmp/include/mach/regs-smc.h new file mode 100644 index 00000000000..e484d40d71b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-smc.h @@ -0,0 +1,37 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/regs-smc.h + * + * Static Memory Controller Registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_REGS_SMC_H +#define __ASM_MACH_REGS_SMC_H + +#include <mach/addr-map.h> + +#define SMC_VIRT_BASE (AXI_VIRT_BASE + 0x83800) +#define SMC_REG(x) (SMC_VIRT_BASE + (x)) + +#define SMC_MSC0 SMC_REG(0x0020) +#define SMC_MSC1 SMC_REG(0x0024) +#define SMC_SXCNFG0 SMC_REG(0x0030) +#define SMC_SXCNFG1 SMC_REG(0x0034) +#define SMC_MEMCLKCFG SMC_REG(0x0068) +#define SMC_CSDFICFG0 SMC_REG(0x0090) +#define SMC_CSDFICFG1 SMC_REG(0x0094) +#define SMC_CLK_RET_DEL SMC_REG(0x00b0) +#define SMC_ADV_RET_DEL SMC_REG(0x00b4) +#define SMC_CSADRMAP0 SMC_REG(0x00c0) +#define SMC_CSADRMAP1 SMC_REG(0x00c4) +#define SMC_WE_AP0 SMC_REG(0x00e0) +#define SMC_WE_AP1 SMC_REG(0x00e4) +#define SMC_OE_AP0 SMC_REG(0x00f0) +#define SMC_OE_AP1 SMC_REG(0x00f4) +#define SMC_ADV_AP0 SMC_REG(0x0100) +#define SMC_ADV_AP1 SMC_REG(0x0104) + +#endif /* __ASM_MACH_REGS_SMC_H */ diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h index 6cebbd0ca8f..70c9f1d88c0 100644 --- a/arch/arm/mach-mmp/include/mach/timex.h +++ b/arch/arm/mach-mmp/include/mach/timex.h @@ -6,4 +6,8 @@ * published by the Free Software Foundation. */ +#ifdef CONFIG_CPU_MMP2 +#define CLOCK_TICK_RATE 6500000 +#else #define CLOCK_TICK_RATE 3250000 +#endif diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h index c93d5fa5865..85bd8a2d84b 100644 --- a/arch/arm/mach-mmp/include/mach/uncompress.h +++ b/arch/arm/mach-mmp/include/mach/uncompress.h @@ -8,15 +8,16 @@ #include <linux/serial_reg.h> #include <mach/addr-map.h> +#include <asm/mach-types.h> #define UART1_BASE (APB_PHYS_BASE + 0x36000) #define UART2_BASE (APB_PHYS_BASE + 0x17000) #define UART3_BASE (APB_PHYS_BASE + 0x18000) +static volatile unsigned long *UART; + static inline void putc(char c) { - volatile unsigned long *UART = (unsigned long *)UART2_BASE; - /* UART enabled? */ if (!(UART[UART_IER] & UART_IER_UUE)) return; @@ -34,8 +35,17 @@ static inline void flush(void) { } +static inline void arch_decomp_setup(void) +{ + /* default to UART2 */ + UART = (unsigned long *)UART2_BASE; + + if (machine_is_avengers_lite()) + UART = (unsigned long *)UART3_BASE; +} + /* * nothing to do */ -#define arch_decomp_setup() + #define arch_decomp_wdog() diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h index b60ccaf9fee..1d0bac003ad 100644 --- a/arch/arm/mach-mmp/include/mach/vmalloc.h +++ b/arch/arm/mach-mmp/include/mach/vmalloc.h @@ -2,4 +2,4 @@ * linux/arch/arm/mach-mmp/include/mach/vmalloc.h */ -#define VMALLOC_END 0xfe000000 +#define VMALLOC_END 0xfe000000UL diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c new file mode 100644 index 00000000000..cb18221c0af --- /dev/null +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -0,0 +1,154 @@ +/* + * linux/arch/arm/mach-mmp/irq-mmp2.c + * + * Generic IRQ handling, GPIO IRQ demultiplexing, etc. + * + * Author: Haojian Zhuang <haojian.zhuang@marvell.com> + * Copyright: Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/regs-icu.h> + +#include "common.h" + +static void icu_mask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r &= ~ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static void icu_unmask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r |= ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static struct irq_chip icu_irq_chip = { + .name = "icu_irq", + .mask = icu_mask_irq, + .mask_ack = icu_mask_irq, + .unmask = icu_unmask_irq, +}; + +static void pmic_irq_ack(unsigned int irq) +{ + if (irq == IRQ_MMP2_PMIC) + mmp2_clear_pmic_int(); +} + +#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +static void _name_##_mask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +static void _name_##_unmask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \ +{ \ + unsigned long status, mask, n; \ + mask = __raw_readl(prefix##_MASK); \ + while (1) { \ + status = __raw_readl(prefix##_STATUS) & ~mask; \ + if (status == 0) \ + break; \ + n = find_first_bit(&status, BITS_PER_LONG); \ + while (n < BITS_PER_LONG) { \ + generic_handle_irq(irq_base + n); \ + n = find_next_bit(&status, BITS_PER_LONG, n+1); \ + } \ + } \ +} + +#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \ +SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static struct irq_chip _name_##_irq_chip = { \ + .name = #_name_, \ + .mask = _name_##_mask_irq, \ + .unmask = _name_##_unmask_irq, \ +} + +SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); +SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5); +SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17); +SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35); +SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51); + +static void init_mux_irq(struct irq_chip *chip, int start, int num) +{ + int irq; + + for (irq = start; num > 0; irq++, num--) { + /* mask and clear the IRQ */ + chip->mask(irq); + if (chip->ack) + chip->ack(irq); + + set_irq_chip(irq, chip); + set_irq_flags(irq, IRQF_VALID); + set_irq_handler(irq, handle_level_irq); + } +} + +void __init mmp2_init_icu(void) +{ + int irq; + + for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { + icu_mask_irq(irq); + set_irq_chip(irq, &icu_irq_chip); + set_irq_flags(irq, IRQF_VALID); + + switch (irq) { + case IRQ_MMP2_PMIC_MUX: + case IRQ_MMP2_RTC_MUX: + case IRQ_MMP2_TWSI_MUX: + case IRQ_MMP2_MISC_MUX: + case IRQ_MMP2_SSP_MUX: + break; + default: + set_irq_handler(irq, handle_level_irq); + break; + } + } + + /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register + * to be written to clear the interrupt + */ + pmic_irq_chip.ack = pmic_irq_ack; + + init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); + init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); + init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); + init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); + init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); + + set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); +} diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq-pxa168.c index 52ff2f065eb..52ff2f065eb 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/arch/arm/mach-mmp/irq-pxa168.c diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c new file mode 100644 index 00000000000..d77dd41d60e --- /dev/null +++ b/arch/arm/mach-mmp/jasper.c @@ -0,0 +1,144 @@ +/* + * linux/arch/arm/mach-mmp/jasper.c + * + * Support for the Marvell Jasper Development Platform. + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/max8649.h> +#include <linux/mfd/max8925.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-mmp2.h> +#include <mach/mmp2.h> +#include <mach/irqs.h> + +#include "common.h" + +static unsigned long jasper_pin_config[] __initdata = { + /* UART1 */ + GPIO29_UART1_RXD, + GPIO30_UART1_TXD, + + /* UART3 */ + GPIO51_UART3_RXD, + GPIO52_UART3_TXD, + + /* DFI */ + GPIO168_DFI_D0, + GPIO167_DFI_D1, + GPIO166_DFI_D2, + GPIO165_DFI_D3, + GPIO107_DFI_D4, + GPIO106_DFI_D5, + GPIO105_DFI_D6, + GPIO104_DFI_D7, + GPIO111_DFI_D8, + GPIO164_DFI_D9, + GPIO163_DFI_D10, + GPIO162_DFI_D11, + GPIO161_DFI_D12, + GPIO110_DFI_D13, + GPIO109_DFI_D14, + GPIO108_DFI_D15, + GPIO143_ND_nCS0, + GPIO144_ND_nCS1, + GPIO147_ND_nWE, + GPIO148_ND_nRE, + GPIO150_ND_ALE, + GPIO149_ND_CLE, + GPIO112_ND_RDY0, + GPIO160_ND_RDY1, + + /* PMIC */ + PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, +}; + +static struct regulator_consumer_supply max8649_supply[] = { + REGULATOR_SUPPLY("vcc_core", NULL), +}; + +static struct regulator_init_data max8649_init_data = { + .constraints = { + .name = "vcc_core range", + .min_uV = 1150000, + .max_uV = 1280000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8649_supply[0], +}; + +static struct max8649_platform_data jasper_max8649_info = { + .mode = 2, /* VID1 = 1, VID0 = 0 */ + .extclk = 0, + .ramp_timing = MAX8649_RAMP_32MV, + .regulator = &max8649_init_data, +}; + +static struct max8925_backlight_pdata jasper_backlight_data = { + .dual_string = 0, +}; + +static struct max8925_power_pdata jasper_power_data = { + .batt_detect = 0, /* can't detect battery by ID pin */ + .topoff_threshold = MAX8925_TOPOFF_THR_10PER, + .fast_charge = MAX8925_FCHG_1000MA, +}; + +static struct max8925_platform_data jasper_max8925_info = { + .backlight = &jasper_backlight_data, + .power = &jasper_power_data, + .irq_base = IRQ_BOARD_START, +}; + +static struct i2c_board_info jasper_twsi1_info[] = { + [0] = { + .type = "max8649", + .addr = 0x60, + .platform_data = &jasper_max8649_info, + }, + [1] = { + .type = "max8925", + .addr = 0x3c, + .irq = IRQ_MMP2_PMIC, + .platform_data = &jasper_max8925_info, + }, +}; + +static void __init jasper_init(void) +{ + mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); + + /* on-chip devices */ + mmp2_add_uart(1); + mmp2_add_uart(3); + mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); + + regulator_has_full_constraints(); +} + +MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = mmp2_init_irq, + .timer = &mmp2_timer, + .init_machine = jasper_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c new file mode 100644 index 00000000000..7f5eb059bb0 --- /dev/null +++ b/arch/arm/mach-mmp/mmp2.c @@ -0,0 +1,173 @@ +/* + * linux/arch/arm/mach-mmp/mmp2.c + * + * code name MMP2 + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/hardware/cache-tauros2.h> + +#include <mach/addr-map.h> +#include <mach/regs-apbc.h> +#include <mach/regs-apmu.h> +#include <mach/cputype.h> +#include <mach/irqs.h> +#include <mach/dma.h> +#include <mach/mfp.h> +#include <mach/gpio.h> +#include <mach/devices.h> + +#include "common.h" +#include "clock.h" + +#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) + +#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) + +static struct mfp_addr_map mmp2_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO58, 0x54), + MFP_ADDR_X(GPIO59, GPIO73, 0x280), + MFP_ADDR_X(GPIO74, GPIO101, 0x170), + + MFP_ADDR(GPIO102, 0x0), + MFP_ADDR(GPIO103, 0x4), + MFP_ADDR(GPIO104, 0x1fc), + MFP_ADDR(GPIO105, 0x1f8), + MFP_ADDR(GPIO106, 0x1f4), + MFP_ADDR(GPIO107, 0x1f0), + MFP_ADDR(GPIO108, 0x21c), + MFP_ADDR(GPIO109, 0x218), + MFP_ADDR(GPIO110, 0x214), + MFP_ADDR(GPIO111, 0x200), + MFP_ADDR(GPIO112, 0x244), + MFP_ADDR(GPIO113, 0x25c), + MFP_ADDR(GPIO114, 0x164), + MFP_ADDR_X(GPIO115, GPIO122, 0x260), + + MFP_ADDR(GPIO123, 0x148), + MFP_ADDR_X(GPIO124, GPIO141, 0xc), + + MFP_ADDR(GPIO142, 0x8), + MFP_ADDR_X(GPIO143, GPIO151, 0x220), + MFP_ADDR_X(GPIO152, GPIO153, 0x248), + MFP_ADDR_X(GPIO154, GPIO155, 0x254), + MFP_ADDR_X(GPIO156, GPIO159, 0x14c), + + MFP_ADDR(GPIO160, 0x250), + MFP_ADDR(GPIO161, 0x210), + MFP_ADDR(GPIO162, 0x20c), + MFP_ADDR(GPIO163, 0x208), + MFP_ADDR(GPIO164, 0x204), + MFP_ADDR(GPIO165, 0x1ec), + MFP_ADDR(GPIO166, 0x1e8), + MFP_ADDR(GPIO167, 0x1e4), + MFP_ADDR(GPIO168, 0x1e0), + + MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140), + MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc), + + MFP_ADDR(PMIC_INT, 0x2c4), + MFP_ADDR(CLK_REQ, 0x160), + + MFP_ADDR_END, +}; + +void mmp2_clear_pmic_int(void) +{ + unsigned long mfpr_pmic, data; + + mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; + data = __raw_readl(mfpr_pmic); + __raw_writel(data | (1 << 6), mfpr_pmic); + __raw_writel(data, mfpr_pmic); +} + +static void __init mmp2_init_gpio(void) +{ + int i; + + /* enable GPIO clock */ + __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); + + /* unmask GPIO edge detection for all 6 banks -- APMASKx */ + for (i = 0; i < 6; i++) + __raw_writel(0xffffffff, APMASK(i)); + + pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); +} + +void __init mmp2_init_irq(void) +{ + mmp2_init_icu(); + mmp2_init_gpio(); +} + +/* APB peripheral clocks */ +static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); +static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); +static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); +static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); +static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); +static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); +static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); +static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); +static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); +static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); +static APBC_CLK(rtc, MMP2_RTC, 0, 32768); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), +}; + +static int __init mmp2_init(void) +{ + if (cpu_is_mmp2()) { +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(); +#endif + mfp_init_base(MFPR_VIRT_BASE); + mfp_init_addr(mmp2_addr_map); + pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); + clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); + } + + return 0; +} +postcore_initcall(mmp2_init); + +/* on-chip devices */ +MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); +MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); +MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); +MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); +MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); +MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); +MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); +MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); +MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); +MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); +MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); + diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 37dbdde17fa..652ae660634 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -72,6 +72,11 @@ static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); +static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); +static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); +static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); +static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); +static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); static APMU_CLK(nand, NAND, 0x01db, 208000000); @@ -85,6 +90,11 @@ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), + INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), + INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), + INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), + INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), + INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), }; @@ -94,7 +104,7 @@ static int __init pxa168_init(void) mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); - clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); + clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); } return 0; @@ -132,3 +142,8 @@ PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); +PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53); +PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55); +PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); +PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); +PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index d4049508a4d..46f2d69bef3 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -131,7 +131,7 @@ static int __init pxa910_init(void) mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); - clks_register(ARRAY_AND_SIZE(pxa910_clkregs)); + clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); } return 0; diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index a8400bb891e..cf75694e968 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -30,7 +30,10 @@ #include <mach/addr-map.h> #include <mach/regs-timers.h> +#include <mach/regs-apbc.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include <asm/mach/time.h> #include "clock.h" @@ -158,7 +161,7 @@ static void __init timer_config(void) __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ - ccr &= TMR_CCR_CS_0(0x3); + ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3); __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); /* free-running mode */ @@ -197,3 +200,24 @@ void __init timer_init(int irq) clocksource_register(&cksrc); clockevents_register_device(&ckevt); } + +static void __init mmp2_timer_init(void) +{ + unsigned long clk_rst; + + __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + + /* + * enable bus/functional clock, enable 6.5MHz (divider 4), + * release reset + */ + clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); + __raw_writel(clk_rst, APBC_MMP2_TIMERS); + + timer_init(IRQ_MMP2_TIMER1); +} + +struct sys_timer mmp2_timer = { + .init = mmp2_timer_init, +}; + |