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-rw-r--r--arch/arm/mach-mvebu/Kconfig30
-rw-r--r--arch/arm/mach-mvebu/Makefile5
-rw-r--r--arch/arm/mach-mvebu/Makefile.boot3
-rw-r--r--arch/arm/mach-mvebu/addr-map.c134
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c4
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.h (renamed from arch/arm/mach-mvebu/include/mach/armada-370-xp.h)2
-rw-r--r--arch/arm/mach-mvebu/include/mach/debug-macro.S24
-rw-r--r--arch/arm/mach-mvebu/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-mvebu/include/mach/timex.h13
-rw-r--r--arch/arm/mach-mvebu/include/mach/uncompress.h43
10 files changed, 169 insertions, 90 deletions
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index caa2c5e734f..416d46ef7eb 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,15 +1,39 @@
+config ARCH_MVEBU
+ bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+ select CLKSRC_MMIO
+ select COMMON_CLK
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+ select MULTI_IRQ_HANDLER
+ select PINCTRL
+ select PLAT_ORION
+ select SPARSE_IRQ
+
if ARCH_MVEBU
menu "Marvell SOC with device tree"
config MACH_ARMADA_370_XP
- bool "Marvell Armada 370 and Aramada XP boards"
+ bool
select ARMADA_370_XP_TIMER
select CPU_V7
+
+config MACH_ARMADA_370
+ bool "Marvell Armada 370 boards"
+ select MACH_ARMADA_370_XP
+ select PINCTRL_ARMADA_370
help
+ Say 'Y' here if you want your kernel to support boards based
+ on the Marvell Armada 370 SoC with device tree.
- Say 'Y' here if you want your kernel to support boards based on
- Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+ bool "Marvell Armada XP boards"
+ select MACH_ARMADA_370_XP
+ select PINCTRL_ARMADA_XP
+ help
+ Say 'Y' here if you want your kernel to support boards based
+ on the Marvell Armada XP SoC with device tree.
endmenu
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index e61d2b8fdf5..57f996b6aa0 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,2 +1,5 @@
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ -I$(srctree)/arch/arm/plat-orion/include
+
obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
deleted file mode 100644
index 2579a2fc233..00000000000
--- a/arch/arm/mach-mvebu/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y := 0x00008000
-dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-db.dtb
-dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-xp-db.dtb
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 00000000000..fe454a4430b
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS 1
+#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
+#define ARMADA_XP_TARGET_ETH1 3
+#define ARMADA_XP_TARGET_PCIE_0_2 4
+#define ARMADA_XP_TARGET_ETH0 7
+#define ARMADA_XP_TARGET_PCIE_1_3 8
+
+#define ARMADA_370_TARGET_DEV_BUS 1
+#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
+#define ARMADA_370_TARGET_PCIE_0 4
+#define ARMADA_370_TARGET_PCIE_1 8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+ /*
+ * Window for the BootROM, needed for SMP on Armada XP
+ */
+ { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+ ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+ /* End marker */
+ { -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+ /* End marker */
+ { -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+ { .compatible = "marvell,armada-addr-decoding-controller" },
+ { /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+ unsigned int offset;
+
+ /* The register layout is a bit annoying and the below code
+ * tries to cope with it.
+ * - At offset 0x0, there are the registers for the first 8
+ * windows, with 4 registers of 32 bits per window (ctrl,
+ * base, remap low, remap high)
+ * - Then at offset 0x80, there is a hole of 0x10 bytes for
+ * the internal registers base address and internal units
+ * sync barrier register.
+ * - Then at offset 0x90, there the registers for 12
+ * windows, with only 2 registers of 32 bits per window
+ * (ctrl, base).
+ */
+ if (win < 8)
+ offset = (win << 4);
+ else
+ offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+ return cfg->bridge_virt_base + offset;
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+ .num_wins = 20,
+ .remappable_wins = 8,
+ .win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+ struct device_node *np;
+ void __iomem *mbus_unit_addr_decoding_base;
+ void __iomem *sdram_addr_decoding_base;
+
+ np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+ if (!np)
+ return -ENODEV;
+
+ mbus_unit_addr_decoding_base = of_iomap(np, 0);
+ BUG_ON(!mbus_unit_addr_decoding_base);
+
+ sdram_addr_decoding_base =
+ mbus_unit_addr_decoding_base +
+ ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+ addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+
+ /*
+ * Disable, clear and configure windows.
+ */
+ if (of_machine_is_compatible("marvell,armadaxp"))
+ orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+ else if (of_machine_is_compatible("marvell,armada370"))
+ orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+ else {
+ pr_err("Unsupported SoC\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Setup MBUS dram target info.
+ */
+ orion_setup_cpu_mbus_target(&addr_map_cfg,
+ sdram_addr_decoding_base);
+ return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 4ef923b032e..49d791548ad 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -20,12 +20,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <mach/armada-370-xp.h>
+#include "armada-370-xp.h"
#include "common.h"
static struct map_desc armada_370_xp_io_desc[] __initdata = {
{
- .virtual = ARMADA_370_XP_REGS_VIRT_BASE,
+ .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
.length = ARMADA_370_XP_REGS_SIZE,
.type = MT_DEVICE,
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 25f0ca8d782..aac9bebc6b0 100644
--- a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
#define __MACH_ARMADA_370_XP_H
#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
#define ARMADA_370_XP_REGS_SIZE SZ_1M
#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/mach-mvebu/include/mach/debug-macro.S
deleted file mode 100644
index 22825760c7e..00000000000
--- a/arch/arm/mach-mvebu/include/mach/debug-macro.S
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Early serial output macro for Marvell SoC
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- * Gregory Clement <gregory.clement@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <mach/armada-370-xp.h>
-
- .macro addruart, rp, rv, tmp
- ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE
- ldr \rv, =ARMADA_370_XP_REGS_VIRT_BASE
- orr \rp, \rp, #0x00012000
- orr \rv, \rv, #0x00012000
- .endm
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 00000000000..40a8c178f10
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
deleted file mode 100644
index ab324a3748f..00000000000
--- a/arch/arm/mach-mvebu/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Marvell Armada SoC time definitions
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
deleted file mode 100644
index d6a100ccf30..00000000000
--- a/arch/arm/mach-mvebu/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Marvell Armada SoC kernel uncompression UART routines
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/armada-370-xp.h>
-
-#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
- + 0x12000))
-#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
- + 0x12014))
-
-#define LSR_THRE 0x20
-
-static void putc(const char c)
-{
- int i;
-
- for (i = 0; i < 0x1000; i++) {
- /* Transmit fifo not full? */
- if (*UART_LSR & LSR_THRE)
- break;
- }
-
- *UART_THR = c;
-}
-
-static void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()