diff options
Diffstat (limited to 'arch/arm/mach-mxs/regs-clkctrl-mx28.h')
| -rw-r--r-- | arch/arm/mach-mxs/regs-clkctrl-mx28.h | 177 |
1 files changed, 0 insertions, 177 deletions
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h index 661df18755f..7d1b061d794 100644 --- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h @@ -31,10 +31,6 @@ #define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) #define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) -#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 -#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ - (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ @@ -43,10 +39,6 @@ #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 -#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ - (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) #define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ @@ -55,10 +47,6 @@ #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 -#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ - (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ @@ -67,22 +55,13 @@ #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 #define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 -#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF -#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) #define HW_CLKCTRL_PLL0CTRL1 (0x00000010) #define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 -#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 -#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 -#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ - (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ @@ -94,7 +73,6 @@ #define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ @@ -103,10 +81,6 @@ #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 -#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ - (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) #define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 #define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ @@ -115,10 +89,6 @@ #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 -#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 -#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ - (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ @@ -127,22 +97,13 @@ #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 #define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 -#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF -#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) #define HW_CLKCTRL_PLL1CTRL1 (0x00000030) #define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 -#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 -#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 -#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ - (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ @@ -154,51 +115,31 @@ #define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) #define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 -#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) -#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 #define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 #define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) #define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 -#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 -#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF -#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) #define HW_CLKCTRL_CPU (0x00000050) #define HW_CLKCTRL_CPU_SET (0x00000054) #define HW_CLKCTRL_CPU_CLR (0x00000058) #define HW_CLKCTRL_CPU_TOG (0x0000005c) -#define BP_CLKCTRL_CPU_RSRVD5 30 -#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 -#define BF_CLKCTRL_CPU_RSRVD5(v) \ - (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 -#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 #define BP_CLKCTRL_CPU_DIV_XTAL 16 #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) -#define BP_CLKCTRL_CPU_RSRVD3 13 -#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 -#define BF_CLKCTRL_CPU_RSRVD3(v) \ - (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 -#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 -#define BP_CLKCTRL_CPU_RSRVD1 6 -#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 -#define BF_CLKCTRL_CPU_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) #define BP_CLKCTRL_CPU_DIV_CPU 0 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F #define BF_CLKCTRL_CPU_DIV_CPU(v) \ @@ -212,7 +153,6 @@ #define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 -#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 @@ -232,10 +172,6 @@ #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 -#define BP_CLKCTRL_HBUS_RSRVD1 6 -#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 -#define BF_CLKCTRL_HBUS_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 #define BP_CLKCTRL_HBUS_DIV 0 #define BM_CLKCTRL_HBUS_DIV 0x0000001F @@ -245,10 +181,6 @@ #define HW_CLKCTRL_XBUS (0x00000070) #define BM_CLKCTRL_XBUS_BUSY 0x80000000 -#define BP_CLKCTRL_XBUS_RSRVD1 12 -#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 -#define BF_CLKCTRL_XBUS_RSRVD1(v) \ - (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 #define BP_CLKCTRL_XBUS_DIV 0 @@ -263,19 +195,10 @@ #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 -#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 -#define BP_CLKCTRL_XTAL_RSRVD2 27 -#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 -#define BF_CLKCTRL_XTAL_RSRVD2(v) \ - (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 -#define BP_CLKCTRL_XTAL_RSRVD1 2 -#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC -#define BF_CLKCTRL_XTAL_RSRVD1(v) \ - (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) #define BP_CLKCTRL_XTAL_DIV_UART 0 #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 #define BF_CLKCTRL_XTAL_DIV_UART(v) \ @@ -285,12 +208,7 @@ #define BP_CLKCTRL_SSP0_CLKGATE 31 #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP0_BUSY 0x20000000 -#define BP_CLKCTRL_SSP0_RSRVD1 10 -#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP0_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) #define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP0_DIV 0 #define BM_CLKCTRL_SSP0_DIV 0x000001FF @@ -301,12 +219,7 @@ #define BP_CLKCTRL_SSP1_CLKGATE 31 #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP1_BUSY 0x20000000 -#define BP_CLKCTRL_SSP1_RSRVD1 10 -#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP1_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) #define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP1_DIV 0 #define BM_CLKCTRL_SSP1_DIV 0x000001FF @@ -317,12 +230,7 @@ #define BP_CLKCTRL_SSP2_CLKGATE 31 #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP2_BUSY 0x20000000 -#define BP_CLKCTRL_SSP2_RSRVD1 10 -#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP2_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) #define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP2_DIV 0 #define BM_CLKCTRL_SSP2_DIV 0x000001FF @@ -333,12 +241,7 @@ #define BP_CLKCTRL_SSP3_CLKGATE 31 #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 -#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 #define BM_CLKCTRL_SSP3_BUSY 0x20000000 -#define BP_CLKCTRL_SSP3_RSRVD1 10 -#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 -#define BF_CLKCTRL_SSP3_RSRVD1(v) \ - (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) #define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 #define BP_CLKCTRL_SSP3_DIV 0 #define BM_CLKCTRL_SSP3_DIV 0x000001FF @@ -349,12 +252,7 @@ #define BP_CLKCTRL_GPMI_CLKGATE 31 #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 -#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 #define BM_CLKCTRL_GPMI_BUSY 0x20000000 -#define BP_CLKCTRL_GPMI_RSRVD1 11 -#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 -#define BF_CLKCTRL_GPMI_RSRVD1(v) \ - (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 #define BP_CLKCTRL_GPMI_DIV 0 #define BM_CLKCTRL_GPMI_DIV 0x000003FF @@ -365,10 +263,6 @@ #define BP_CLKCTRL_SPDIF_CLKGATE 31 #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 -#define BP_CLKCTRL_SPDIF_RSRVD 0 -#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF -#define BF_CLKCTRL_SPDIF_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) #define HW_CLKCTRL_EMI (0x000000f0) @@ -379,24 +273,12 @@ #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 -#define BP_CLKCTRL_EMI_RSRVD3 18 -#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 -#define BF_CLKCTRL_EMI_RSRVD3(v) \ - (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BP_CLKCTRL_EMI_RSRVD2 12 -#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 -#define BF_CLKCTRL_EMI_RSRVD2(v) \ - (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) #define BP_CLKCTRL_EMI_DIV_XTAL 8 #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) -#define BP_CLKCTRL_EMI_RSRVD1 6 -#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 -#define BF_CLKCTRL_EMI_RSRVD1(v) \ - (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) #define BP_CLKCTRL_EMI_DIV_EMI 0 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F #define BF_CLKCTRL_EMI_DIV_EMI(v) \ @@ -406,12 +288,7 @@ #define BP_CLKCTRL_SAIF0_CLKGATE 31 #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 -#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 #define BM_CLKCTRL_SAIF0_BUSY 0x20000000 -#define BP_CLKCTRL_SAIF0_RSRVD1 17 -#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 -#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ - (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 #define BP_CLKCTRL_SAIF0_DIV 0 #define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF @@ -422,12 +299,7 @@ #define BP_CLKCTRL_SAIF1_CLKGATE 31 #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 -#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 #define BM_CLKCTRL_SAIF1_BUSY 0x20000000 -#define BP_CLKCTRL_SAIF1_RSRVD1 17 -#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 -#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ - (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 #define BP_CLKCTRL_SAIF1_DIV 0 #define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF @@ -438,12 +310,7 @@ #define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 #define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 -#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 #define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 -#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 -#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 -#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ - (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 #define BP_CLKCTRL_DIS_LCDIF_DIV 0 #define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF @@ -453,12 +320,7 @@ #define HW_CLKCTRL_ETM (0x00000130) #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 -#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 #define BM_CLKCTRL_ETM_BUSY 0x20000000 -#define BP_CLKCTRL_ETM_RSRVD1 8 -#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 -#define BF_CLKCTRL_ETM_RSRVD1(v) \ - (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 #define BP_CLKCTRL_ETM_DIV 0 #define BM_CLKCTRL_ETM_DIV 0x0000007F @@ -471,7 +333,6 @@ #define BP_CLKCTRL_ENET_DISABLE 30 #define BM_CLKCTRL_ENET_DISABLE 0x40000000 #define BM_CLKCTRL_ENET_STATUS 0x20000000 -#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 #define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 #define BP_CLKCTRL_ENET_DIV_TIME 21 #define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 @@ -493,37 +354,23 @@ #define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 #define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 -#define BP_CLKCTRL_ENET_RSRVD0 0 -#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF -#define BF_CLKCTRL_ENET_RSRVD0(v) \ - (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) #define HW_CLKCTRL_HSADC (0x00000150) -#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 #define BM_CLKCTRL_HSADC_RESETB 0x40000000 #define BP_CLKCTRL_HSADC_FREQDIV 28 #define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 #define BF_CLKCTRL_HSADC_FREQDIV(v) \ (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) -#define BP_CLKCTRL_HSADC_RSRVD1 0 -#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF -#define BF_CLKCTRL_HSADC_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) #define HW_CLKCTRL_FLEXCAN (0x00000160) -#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 #define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 #define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 #define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 #define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 -#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 -#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF -#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ - (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) #define HW_CLKCTRL_FRAC0 (0x000001b0) #define HW_CLKCTRL_FRAC0_SET (0x000001b4) @@ -564,10 +411,6 @@ #define HW_CLKCTRL_FRAC1_CLR (0x000001c8) #define HW_CLKCTRL_FRAC1_TOG (0x000001cc) -#define BP_CLKCTRL_FRAC1_RSRVD2 24 -#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 -#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ - (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) #define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 #define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 #define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 @@ -595,22 +438,10 @@ #define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) #define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) -#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 -#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 -#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ - (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 -#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 -#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 -#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ - (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 -#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 -#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 -#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ - (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 @@ -623,10 +454,6 @@ #define HW_CLKCTRL_RESET (0x000001e0) -#define BP_CLKCTRL_RESET_RSRVD 6 -#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 -#define BF_CLKCTRL_RESET_RSRVD(v) \ - (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 @@ -640,10 +467,6 @@ #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) -#define BP_CLKCTRL_STATUS_RSRVD 0 -#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF -#define BF_CLKCTRL_STATUS_RSRVD(v) \ - (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) #define HW_CLKCTRL_VERSION (0x00000200) |