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Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c83
1 files changed, 68 insertions, 15 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2af0e3f00ce..08e86d793a1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -270,8 +270,8 @@ static struct clk dpll_abe_ck = {
.dpll_data = &dpll_abe_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
- .recalc = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
+ .recalc = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
};
@@ -1195,11 +1195,33 @@ static struct clk l4_wkup_clk_mux_ck = {
.recalc = &omap2_clksel_recalc,
};
+static const struct clksel_rate div2_2to1_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+ { .div = 0 },
+};
+
+static const struct clksel ocp_abe_iclk_div[] = {
+ { .parent = &aess_fclk, .rates = div2_2to1_rates },
+ { .parent = NULL },
+};
+
+static struct clk mpu_periphclk = {
+ .name = "mpu_periphclk",
+ .parent = &dpll_mpu_ck,
+ .ops = &clkops_null,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
+ .clksel = ocp_abe_iclk_div,
+ .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+ .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .recalc = &omap2_clksel_recalc,
};
static struct clk per_abe_24m_fclk = {
@@ -1398,9 +1420,9 @@ static struct clk dss_dss_clk = {
};
static const struct clksel_rate div3_8to32_rates[] = {
- { .div = 8, .val = 0, .flags = RATE_IN_44XX },
- { .div = 16, .val = 1, .flags = RATE_IN_44XX },
- { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+ { .div = 8, .val = 0, .flags = RATE_IN_4460 },
+ { .div = 16, .val = 1, .flags = RATE_IN_4460 },
+ { .div = 32, .val = 2, .flags = RATE_IN_4460 },
{ .div = 0 },
};
@@ -3175,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
+ CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
@@ -3281,7 +3304,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
- CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
+ CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
@@ -3292,7 +3315,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
- CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
+ CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
@@ -3300,7 +3323,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
- CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
+ CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
@@ -3360,9 +3383,31 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
- CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
- CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
+ CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
+ CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
+ CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X),
+ CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
+ CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
+ CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
+ CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
+ CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)
@@ -3370,16 +3415,24 @@ int __init omap4xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg;
- if (cpu_is_omap44xx()) {
+ if (cpu_is_omap443x()) {
cpu_mask = RATE_IN_4430;
cpu_clkflg = CK_443X;
} else if (cpu_is_omap446x()) {
- cpu_mask = RATE_IN_4460;
- cpu_clkflg = CK_446X;
+ cpu_mask = RATE_IN_4460 | RATE_IN_4430;
+ cpu_clkflg = CK_446X | CK_443X;
+ } else {
+ return 0;
}
clk_init(&omap2_clk_functions);
- omap2_clk_disable_clkdm_control();
+
+ /*
+ * Must stay commented until all OMAP SoC drivers are
+ * converted to runtime PM, or drivers may start crashing
+ *
+ * omap2_clk_disable_clkdm_control();
+ */
for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
c++)
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-02-18 10:53:25 +0000