diff options
Diffstat (limited to 'arch/arm/mach-omap2/omap-smp.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap-smp.c | 65 |
1 files changed, 57 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 9a35adf9123..cd42d921940 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -24,14 +24,15 @@ #include <asm/hardware/gic.h> #include <asm/smp_scu.h> -#include <mach/hardware.h> -#include <mach/omap-secure.h> -#include <mach/omap-wakeupgen.h> +#include "omap-secure.h" +#include "omap-wakeupgen.h" #include <asm/cputype.h> +#include "soc.h" #include "iomap.h" #include "common.h" #include "clockdomain.h" +#include "pm.h" #define CPU_MASK 0xff0ffff0 #define CPU_CORTEX_A9 0x410FC090 @@ -39,6 +40,8 @@ #define OMAP5_CORE_COUNT 0x2 +u16 pm44xx_errata; + /* SCU base address */ static void __iomem *scu_base; @@ -49,7 +52,7 @@ void __iomem *omap4_get_scu_base(void) return scu_base; } -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit omap4_secondary_init(unsigned int cpu) { /* * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. @@ -77,7 +80,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) { static struct clockdomain *cpu1_clkdm; static bool booted; @@ -118,8 +121,37 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * 4.3.4.2 Power States of CPU0 and CPU1 */ if (booted) { + /* + * GIC distributor control register has changed between + * CortexA9 r1pX and r2pX. The Control Register secure + * banked version is now composed of 2 bits: + * bit 0 == Secure Enable + * bit 1 == Non-Secure Enable + * The Non-Secure banked register has not changed + * Because the ROM Code is based on the r1pX GIC, the CPU1 + * GIC restoration will cause a problem to CPU0 Non-Secure SW. + * The workaround must be: + * 1) Before doing the CPU1 wakeup, CPU0 must disable + * the GIC distributor + * 2) CPU1 must re-enable the GIC distributor on + * it's wakeup path. + */ + if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { + local_irq_disable(); + gic_dist_disable(); + } + clkdm_wakeup(cpu1_clkdm); clkdm_allow_idle(cpu1_clkdm); + + if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { + while (gic_dist_disabled()) { + udelay(1); + cpu_relax(); + } + gic_timer_retrigger(); + local_irq_enable(); + } } else { dsb_sev(); booted = true; @@ -138,7 +170,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init wakeup_secondary(void) { + void *startup_addr = omap_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); + + if (cpu_is_omap446x()) { + startup_addr = omap_secondary_startup_4460; + pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; + } + /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing @@ -146,7 +185,7 @@ static void __init wakeup_secondary(void) * A barrier is added to ensure that write buffer is drained */ if (omap_secure_apis_support()) - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); + omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else __raw_writel(virt_to_phys(omap5_secondary_startup), base + OMAP_AUX_CORE_BOOT_1); @@ -165,7 +204,7 @@ static void __init wakeup_secondary(void) * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ -void __init smp_init_cpus(void) +static void __init omap4_smp_init_cpus(void) { unsigned int i = 0, ncores = 1, cpu_id; @@ -196,7 +235,7 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { /* @@ -207,3 +246,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); wakeup_secondary(); } + +struct smp_operations omap4_smp_ops __initdata = { + .smp_init_cpus = omap4_smp_init_cpus, + .smp_prepare_cpus = omap4_smp_prepare_cpus, + .smp_secondary_init = omap4_secondary_init, + .smp_boot_secondary = omap4_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = omap4_cpu_die, +#endif +}; |