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-rw-r--r--arch/arm/mach-omap2/Kconfig64
-rw-r--r--arch/arm/mach-omap2/Makefile90
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c23
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c153
-rw-r--r--[-rwxr-xr-x]arch/arm/mach-omap2/board-3630sdp.c7
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c48
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c239
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c257
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c676
-rw-r--r--arch/arm/mach-omap2/board-generic.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c9
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c311
-rw-r--r--arch/arm/mach-omap2/board-ldp.c16
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c545
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c18
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c301
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c208
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c28
-rw-r--r--arch/arm/mach-omap2/board-overo.c18
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c63
-rw-r--r--arch/arm/mach-omap2/board-rx51.c54
-rw-r--r--arch/arm/mach-omap2/board-sdp-flash.c272
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c2
-rw-r--r--[-rwxr-xr-x]arch/arm/mach-omap2/board-zoom-peripherals.c32
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom3.c18
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c122
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c173
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c62
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_sys.c50
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c255
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c121
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c409
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c386
-rw-r--r--arch/arm/mach-omap2/clock.c1029
-rw-r--r--arch/arm/mach-omap2/clock.h50
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c1911
-rw-r--r--arch/arm/mach-omap2/clock2430.c59
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c (renamed from arch/arm/mach-omap2/clock2xxx_data.c)643
-rw-r--r--arch/arm/mach-omap2/clock2xxx.c560
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h31
-rw-r--r--arch/arm/mach-omap2/clock34xx.c262
-rw-r--r--arch/arm/mach-omap2/clock34xx.h19
-rw-r--r--arch/arm/mach-omap2/clock3517.c124
-rw-r--r--arch/arm/mach-omap2/clock3517.h14
-rw-r--r--arch/arm/mach-omap2/clock36xx.c72
-rw-r--r--arch/arm/mach-omap2/clock36xx.h13
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c104
-rw-r--r--arch/arm/mach-omap2/clock3xxx.h21
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c (renamed from arch/arm/mach-omap2/clock34xx_data.c)900
-rw-r--r--arch/arm/mach-omap2/clock44xx.c33
-rw-r--r--arch/arm/mach-omap2/clock44xx.h13
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c796
-rw-r--r--arch/arm/mach-omap2/clockdomain.c784
-rw-r--r--arch/arm/mach-omap2/clockdomains.h672
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx.h250
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h28
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h536
-rw-r--r--arch/arm/mach-omap2/cm.h8
-rw-r--r--arch/arm/mach-omap2/control.c6
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c228
-rw-r--r--arch/arm/mach-omap2/devices.c45
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c (renamed from arch/arm/mach-omap2/dpll.c)191
-rw-r--r--arch/arm/mach-omap2/emu.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c142
-rw-r--r--arch/arm/mach-omap2/gpmc.c13
-rw-r--r--arch/arm/mach-omap2/hsmmc.c266
-rw-r--r--arch/arm/mach-omap2/hsmmc.h (renamed from arch/arm/mach-omap2/mmc-twl4030.h)14
-rw-r--r--arch/arm/mach-omap2/i2c.c6
-rw-r--r--arch/arm/mach-omap2/id.c47
-rw-r--r--arch/arm/mach-omap2/include/mach/am35xx.h26
-rw-r--r--arch/arm/mach-omap2/include/mach/board-sdp.h21
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S132
-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S128
-rw-r--r--arch/arm/mach-omap2/io.c135
-rw-r--r--arch/arm/mach-omap2/iommu2.c1
-rw-r--r--arch/arm/mach-omap2/irq.c22
-rw-r--r--arch/arm/mach-omap2/mailbox.c59
-rw-r--r--arch/arm/mach-omap2/mcbsp.c25
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c537
-rw-r--r--arch/arm/mach-omap2/mux.c78
-rw-r--r--arch/arm/mach-omap2/mux.h26
-rw-r--r--arch/arm/mach-omap2/mux34xx.c47
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S6
-rw-r--r--arch/arm/mach-omap2/omap44xx-smc.S32
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c319
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c (renamed from arch/arm/mach-omap2/omap_hwmod_2420.h)38
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c (renamed from arch/arm/mach-omap2/omap_hwmod_2430.h)38
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_34xx.h168
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c181
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c68
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h24
-rw-r--r--arch/arm/mach-omap2/opp2420_data.c38
-rw-r--r--arch/arm/mach-omap2/opp2430_data.c30
-rw-r--r--arch/arm/mach-omap2/opp2xxx.h5
-rw-r--r--arch/arm/mach-omap2/pm-debug.c38
-rw-r--r--arch/arm/mach-omap2/pm.h28
-rw-r--r--arch/arm/mach-omap2/pm24xx.c54
-rw-r--r--arch/arm/mach-omap2/pm34xx.c95
-rw-r--r--arch/arm/mach-omap2/powerdomain.c776
-rw-r--r--arch/arm/mach-omap2/powerdomains.h134
-rw-r--r--arch/arm/mach-omap2/powerdomains24xx.h91
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h159
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx.h310
-rw-r--r--arch/arm/mach-omap2/prcm-common.h9
-rw-r--r--arch/arm/mach-omap2/prcm.c129
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h1010
-rw-r--r--arch/arm/mach-omap2/prm.h19
-rw-r--r--arch/arm/mach-omap2/prm44xx.h32
-rw-r--r--arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h51
-rw-r--r--arch/arm/mach-omap2/sdrc.c11
-rw-r--r--arch/arm/mach-omap2/serial.c125
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S70
-rw-r--r--arch/arm/mach-omap2/timer-gp.c5
-rw-r--r--arch/arm/mach-omap2/timer-mpu.c2
-rw-r--r--arch/arm/mach-omap2/usb-ehci.c6
-rw-r--r--arch/arm/mach-omap2/usb-musb.c82
118 files changed, 14035 insertions, 6314 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 10eafa70a90..2455dcc744a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,28 +1,19 @@
comment "OMAP Core Type"
depends on ARCH_OMAP2
-config ARCH_OMAP24XX
- bool "OMAP24xx Based System"
- depends on ARCH_OMAP2
-
config ARCH_OMAP2420
bool "OMAP2420 support"
- depends on ARCH_OMAP24XX
+ depends on ARCH_OMAP2
select OMAP_DM_TIMER
select ARCH_OMAP_OTG
config ARCH_OMAP2430
bool "OMAP2430 support"
- depends on ARCH_OMAP24XX
-
-config ARCH_OMAP34XX
- bool "OMAP34xx Based System"
- depends on ARCH_OMAP3
- select USB_ARCH_HAS_EHCI
+ depends on ARCH_OMAP2
config ARCH_OMAP3430
bool "OMAP3430 support"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select ARCH_OMAP_OTG
config OMAP_PACKAGE_CBC
@@ -38,11 +29,11 @@ config OMAP_PACKAGE_CBP
bool
comment "OMAP Board Type"
- depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
+ depends on ARCH_OMAP2PLUS
config MACH_OMAP_GENERIC
bool "Generic OMAP board"
- depends on ARCH_OMAP2 && ARCH_OMAP24XX
+ depends on ARCH_OMAP2
config MACH_OMAP2_TUSB6010
bool
@@ -51,54 +42,61 @@ config MACH_OMAP2_TUSB6010
config MACH_OMAP_H4
bool "OMAP 2420 H4 board"
- depends on ARCH_OMAP2 && ARCH_OMAP24XX
+ depends on ARCH_OMAP2
select OMAP_DEBUG_DEVICES
config MACH_OMAP_APOLLON
bool "OMAP 2420 Apollon board"
- depends on ARCH_OMAP2 && ARCH_OMAP24XX
+ depends on ARCH_OMAP2
config MACH_OMAP_2430SDP
bool "OMAP 2430 SDP board"
- depends on ARCH_OMAP2 && ARCH_OMAP24XX
+ depends on ARCH_OMAP2
config MACH_OMAP3_BEAGLE
bool "OMAP3 BEAGLE board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
+config MACH_DEVKIT8000
+ bool "DEVKIT8000 board"
+ depends on ARCH_OMAP3
+ select OMAP_PACKAGE_CUS
+ select OMAP_MUX
+
config MACH_OMAP_LDP
bool "OMAP3 LDP board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OVERO
bool "Gumstix Overo board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OMAP3EVM
bool "OMAP 3530 EVM board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
+ select OMAP_PACKAGE_CBB
config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OMAP3_TOUCHBOOK
bool "OMAP3 Touch Book"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select BACKLIGHT_CLASS_DEVICE
config MACH_OMAP_3430SDP
bool "OMAP 3430 SDP board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_NOKIA_N800
@@ -119,33 +117,33 @@ config MACH_NOKIA_N8X0
config MACH_NOKIA_RX51
bool "Nokia RX-51 board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OMAP_ZOOM2
bool "OMAP3 Zoom2 board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OMAP_ZOOM3
bool "OMAP3630 Zoom3 board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBP
config MACH_CM_T35
bool "CompuLab CM-T35 module"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CUS
select OMAP_MUX
config MACH_IGEP0020
- bool "IGEP0020"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ bool "IGEP v2 board"
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBB
config MACH_OMAP_3630SDP
bool "OMAP3630 SDP board"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
select OMAP_PACKAGE_CBP
config MACH_OMAP_4430SDP
@@ -161,7 +159,7 @@ config OMAP3_EMU
config OMAP3_SDRC_AC_TIMING
bool "Enable SDRC AC timing register changes"
- depends on ARCH_OMAP3 && ARCH_OMAP34XX
+ depends on ARCH_OMAP3
default n
help
If you know that none of your system initiators will attempt to
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b32678b848b..4b9fc57770d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,27 +5,36 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
-omap-2-3-common = irq.o sdrc.o omap_hwmod.o
-omap-3-4-common = dpll.o
+omap-2-3-common = irq.o sdrc.o
+hwmod-common = omap_hwmod.o \
+ omap_hwmod_common_data.o
prcm-common = prcm.o powerdomain.o
-clock-common = clock.o clock_common_data.o clockdomain.o
+clock-common = clock.o clock_common_data.o \
+ clockdomain.o clkt_dpll.o \
+ clkt_clksel.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
- $(omap-3-4-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common)
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
# SMP support ONLY available for OMAP4
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
+obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o
+
+AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
# Functions loaded to SRAM
obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
+AFLAGS_sram242x.o :=-Wa,-march=armv6
+AFLAGS_sram243x.o :=-Wa,-march=armv6
+AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
+
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
@@ -36,9 +45,13 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# Power Management
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+
+AFLAGS_sleep24xx.o :=-Wa,-march=armv6
+AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
+
endif
# PRCM
@@ -47,14 +60,31 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
# Clock framework
-obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
+ clkt2xxx_sys.o \
+ clkt2xxx_dpllcore.o \
+ clkt2xxx_virt_prcm_set.o \
+ clkt2xxx_apll.o clkt2xxx_osc.o
+obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o
+obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o
+obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
+ clock34xx.o clkt34xx_dpll3m2.o \
+ clock3517.o clock36xx.o \
+ dpll3xxx.o clock3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
+ dpll3xxx.o
+
+# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
-obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
-obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o
+
+# hwmod data
+obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
+obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
+obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
# EMU peripherals
-obj-$(CONFIG_OMAP3_EMU) += emu.o
+obj-$(CONFIG_OMAP3_EMU) += emu.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
@@ -71,45 +101,48 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \
- mmc-twl4030.o
+ hsmmc.o
+obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OVERO) += board-overo.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \
- mmc-twl4030.o
+ hsmmc.o \
+ board-sdp-flash.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
board-rx51-sdram.o \
board-rx51-peripherals.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \
board-zoom-peripherals.o \
- mmc-twl4030.o \
+ hsmmc.o \
board-zoom-debugboard.o
obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \
board-zoom-peripherals.o \
- mmc-twl4030.o \
+ hsmmc.o \
board-zoom-debugboard.o
obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \
board-zoom-peripherals.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
- mmc-twl4030.o
+ hsmmc.o
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
-obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
+obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
# Platform specific device init code
obj-y += usb-musb.o
@@ -119,5 +152,8 @@ obj-y += usb-ehci.o
onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
obj-y += $(onenand-m) $(onenand-y)
+nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
+obj-y += $(nand-m) $(nand-y)
+
smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o
obj-y += $(smc91x-m) $(smc91x-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index e508904fb67..01d113ff9fc 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/i2c/twl.h>
#include <linux/err.h>
@@ -28,7 +29,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
#include <mach/gpio.h>
#include <plat/mux.h>
@@ -38,7 +38,7 @@
#include <plat/usb.h>
#include <plat/gpmc-smc91x.h>
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define SDP2430_CS0_BASE 0x04000000
#define SECONDARY_LCD_GPIO 147
@@ -74,8 +74,7 @@ static struct mtd_partition sdp2430_partitions[] = {
}
};
-static struct flash_platform_data sdp2430_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data sdp2430_flash_data = {
.width = 2,
.parts = sdp2430_partitions,
.nr_parts = ARRAY_SIZE(sdp2430_partitions),
@@ -88,7 +87,7 @@ static struct resource sdp2430_flash_resource = {
};
static struct platform_device sdp2430_flash_device = {
- .name = "omapflash",
+ .name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &sdp2430_flash_data,
@@ -183,7 +182,7 @@ static int __init omap2430_i2c_init(void)
return 0;
}
-static struct twl4030_hsmmc_info mmc[] __initdata = {
+static struct omap2_hsmmc_info mmc[] __initdata = {
{
.mmc = 1,
.wires = 4,
@@ -194,6 +193,12 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
{} /* Terminator */
};
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init omap_2430sdp_init(void)
{
int ret;
@@ -202,8 +207,8 @@ static void __init omap_2430sdp_init(void)
platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
omap_serial_init();
- twl4030_mmc_init(mmc);
- usb_musb_init();
+ omap2_hsmmc_init(mmc);
+ usb_musb_init(&musb_board_data);
board_smc91x_init();
/* Turn off secondary LCD backlight */
@@ -215,7 +220,7 @@ static void __init omap_2430sdp_init(void)
static void __init omap_2430sdp_map_io(void)
{
omap2_set_globals_243x();
- omap2_map_common_io();
+ omap243x_map_common_io();
}
MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index c90b0d0b192..5822bcf7b15 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -41,9 +41,12 @@
#include <plat/control.h>
#include <plat/gpmc-smc91x.h>
+#include <mach/board-sdp.h>
+
#include "mux.h"
#include "sdram-qimonda-hyb18m512160af-6.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
+#include "pm.h"
#define CONFIG_DISABLE_HFCLK 1
@@ -55,6 +58,24 @@
#define TWL4030_MSECURE_GPIO 22
+/* FIXME: These values need to be updated based on more profiling on 3430sdp*/
+static struct cpuidle_params omap3_cpuidle_params_table[] = {
+ /* C1 */
+ {1, 2, 2, 5},
+ /* C2 */
+ {1, 10, 10, 30},
+ /* C3 */
+ {1, 50, 50, 300},
+ /* C4 */
+ {1, 1500, 1800, 4000},
+ /* C5 */
+ {1, 2500, 7500, 12000},
+ /* C6 */
+ {1, 3000, 8500, 15000},
+ /* C7 */
+ {1, 10000, 30000, 300000},
+};
+
static int board_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
@@ -305,6 +326,7 @@ static void __init omap_3430sdp_init_irq(void)
{
omap_board_config = sdp3430_config;
omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+ omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
@@ -326,7 +348,7 @@ static struct twl4030_bci_platform_data sdp3430_bci_data = {
.tblsize = ARRAY_SIZE(sdp3430_batt_table),
};
-static struct twl4030_hsmmc_info mmc[] = {
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
/* 8 bits (default) requires S6.3 == ON,
@@ -363,7 +385,7 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
*/
mmc[0].gpio_cd = gpio + 0;
mmc[1].gpio_cd = gpio + 1;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
* regulators will be set up only *after* we return.
@@ -520,10 +542,6 @@ static struct regulator_init_data sdp3430_vdac = {
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
{
- .supply = "vdvi",
- .dev = &sdp3430_lcd_device.dev,
- },
- {
.supply = "vdds_dsi",
.dev = &sdp3430_dss_device.dev,
}
@@ -630,7 +648,7 @@ static void enable_board_wakeup_source(void)
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
}
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
@@ -650,6 +668,120 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static struct mtd_partition sdp_nor_partitions[] = {
+ /* bootloader (U-Boot, etc) in first sector */
+ {
+ .name = "Bootloader-NOR",
+ .offset = 0,
+ .size = SZ_256K,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ /* bootloader params in the next sector */
+ {
+ .name = "Params-NOR",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_256K,
+ .mask_flags = 0,
+ },
+ /* kernel */
+ {
+ .name = "Kernel-NOR",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_2M,
+ .mask_flags = 0
+ },
+ /* file system */
+ {
+ .name = "Filesystem-NOR",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ .mask_flags = 0
+ }
+};
+
+static struct mtd_partition sdp_onenand_partitions[] = {
+ {
+ .name = "X-Loader-OneNAND",
+ .offset = 0,
+ .size = 4 * (64 * 2048),
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "U-Boot-OneNAND",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 2 * (64 * 2048),
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },
+ {
+ .name = "U-Boot Environment-OneNAND",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 1 * (64 * 2048),
+ },
+ {
+ .name = "Kernel-OneNAND",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 16 * (64 * 2048),
+ },
+ {
+ .name = "File System-OneNAND",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct mtd_partition sdp_nand_partitions[] = {
+ /* All the partition sizes are listed in terms of NAND block size */
+ {
+ .name = "X-Loader-NAND",
+ .offset = 0,
+ .size = 4 * (64 * 2048),
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ {
+ .name = "U-Boot-NAND",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
+ .size = 10 * (64 * 2048),
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ {
+ .name = "Boot Env-NAND",
+
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
+ .size = 6 * (64 * 2048),
+ },
+ {
+ .name = "Kernel-NAND",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
+ .size = 40 * (64 * 2048),
+ },
+ {
+ .name = "File System - NAND",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
+ },
+};
+
+static struct flash_partitions sdp_flash_partitions[] = {
+ {
+ .parts = sdp_nor_partitions,
+ .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
+ },
+ {
+ .parts = sdp_onenand_partitions,
+ .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
+ },
+ {
+ .parts = sdp_nand_partitions,
+ .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
+ },
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init omap_3430sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -664,8 +796,9 @@ static void __init omap_3430sdp_init(void)
ARRAY_SIZE(sdp3430_spi_board_info));
ads7846_dev_init();
omap_serial_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
board_smc91x_init();
+ sdp_flash_init(sdp_flash_partitions);
sdp3430_display_init();
enable_board_wakeup_source();
usb_ehci_init(&ehci_pdata);
@@ -674,7 +807,7 @@ static void __init omap_3430sdp_init(void)
static void __init omap_3430sdp_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 73905963281..504d2bd222f 100755..100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -54,7 +54,7 @@ static void enable_board_wakeup_source(void)
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
}
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
@@ -68,8 +68,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
static void __init omap_sdp_map_io(void)
{
- omap2_set_globals_343x();
- omap2_map_common_io();
+ omap2_set_globals_36xx();
+ omap34xx_map_common_io();
}
static struct omap_board_config_kernel sdp_config[] __initdata = {
@@ -96,6 +96,7 @@ static struct omap_board_mux board_mux[] __initdata = {
static void __init omap_sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+ omap_serial_init();
zoom_peripherals_init();
board_smc91x_init();
enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 0c6be6b4a7e..b88f28c5814 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -17,6 +17,7 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
+#include <linux/usb/otg.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@@ -27,7 +28,9 @@
#include <plat/common.h>
#include <plat/control.h>
#include <plat/timer-gp.h>
+#include <plat/usb.h>
#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
static struct platform_device sdp4430_lcd_device = {
.name = "sdp4430_lcd",
@@ -38,10 +41,6 @@ static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_lcd_device,
};
-static struct omap_uart_config sdp4430_uart_config __initdata = {
- .enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
-};
-
static struct omap_lcd_config sdp4430_lcd_config __initdata = {
.ctrl_name = "internal",
};
@@ -50,6 +49,35 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
{ OMAP_TAG_LCD, &sdp4430_lcd_config },
};
+#ifdef CONFIG_CACHE_L2X0
+static int __init omap_l2_cache_init(void)
+{
+ extern void omap_smc1(u32 fn, u32 arg);
+ void __iomem *l2cache_base;
+
+ /* To avoid code running on other OMAPs in
+ * multi-omap builds
+ */
+ if (!cpu_is_omap44xx())
+ return -ENODEV;
+
+ /* Static mapping, never released */
+ l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
+ BUG_ON(!l2cache_base);
+
+ /* Enable PL310 L2 Cache controller */
+ omap_smc1(0x102, 0x1);
+
+ /* 32KB way size, 16-way associativity,
+ * parity disabled
+ */
+ l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+
+ return 0;
+}
+early_initcall(omap_l2_cache_init);
+#endif
+
static void __init gic_init_irq(void)
{
void __iomem *base;
@@ -77,17 +105,27 @@ static void __init omap_4430sdp_init_irq(void)
omap_gpio_init();
}
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_UTMI,
+ .mode = MUSB_PERIPHERAL,
+ .power = 100,
+};
static void __init omap_4430sdp_init(void)
{
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
omap_serial_init();
+ /* OMAP4 SDP uses internal transceiver so register nop transceiver */
+ usb_nop_xceiv_register();
+ /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
+ if (!cpu_is_omap44xx())
+ usb_musb_init(&musb_board_data);
}
static void __init omap_4430sdp_map_io(void)
{
omap2_set_globals_443x();
- omap2_map_common_io();
+ omap44xx_map_common_io();
}
MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index b4e6eca0e8a..c1c4389fbd8 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -20,8 +20,10 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
+#include <linux/i2c/pca953x.h>
#include <mach/hardware.h>
+#include <mach/am35xx.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -29,9 +31,228 @@
#include <plat/board.h>
#include <plat/common.h>
#include <plat/usb.h>
+#include <plat/display.h>
#include "mux.h"
+#define LCD_PANEL_PWR 176
+#define LCD_PANEL_BKLIGHT_PWR 182
+#define LCD_PANEL_PWM 181
+
+static struct i2c_board_info __initdata am3517evm_i2c_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("s35390a", 0x30),
+ .type = "s35390a",
+ },
+};
+
+/*
+ * RTC - S35390A
+ */
+#define GPIO_RTCS35390A_IRQ 55
+
+static void __init am3517_evm_rtc_init(void)
+{
+ int r;
+
+ omap_mux_init_gpio(GPIO_RTCS35390A_IRQ, OMAP_PIN_INPUT_PULLUP);
+ r = gpio_request(GPIO_RTCS35390A_IRQ, "rtcs35390a-irq");
+ if (r < 0) {
+ printk(KERN_WARNING "failed to request GPIO#%d\n",
+ GPIO_RTCS35390A_IRQ);
+ return;
+ }
+ r = gpio_direction_input(GPIO_RTCS35390A_IRQ);
+ if (r < 0) {
+ printk(KERN_WARNING "GPIO#%d cannot be configured as input\n",
+ GPIO_RTCS35390A_IRQ);
+ gpio_free(GPIO_RTCS35390A_IRQ);
+ return;
+ }
+ am3517evm_i2c_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ);
+}
+
+/*
+ * I2C GPIO Expander - TCA6416
+ */
+
+/* Mounted on Base-Board */
+static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+};
+static struct i2c_board_info __initdata am3517evm_tca6416_info_0[] = {
+ {
+ I2C_BOARD_INFO("tca6416", 0x21),
+ .platform_data = &am3517evm_gpio_expander_info_0,
+ },
+};
+
+/* Mounted on UI Card */
+static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_1 = {
+ .gpio_base = OMAP_MAX_GPIO_LINES + 16,
+};
+static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_2 = {
+ .gpio_base = OMAP_MAX_GPIO_LINES + 32,
+};
+static struct i2c_board_info __initdata am3517evm_ui_tca6416_info[] = {
+ {
+ I2C_BOARD_INFO("tca6416", 0x20),
+ .platform_data = &am3517evm_ui_gpio_expander_info_1,
+ },
+ {
+ I2C_BOARD_INFO("tca6416", 0x21),
+ .platform_data = &am3517evm_ui_gpio_expander_info_2,
+ },
+};
+
+static int __init am3517_evm_i2c_init(void)
+{
+ omap_register_i2c_bus(1, 400, NULL, 0);
+ omap_register_i2c_bus(2, 400, am3517evm_tca6416_info_0,
+ ARRAY_SIZE(am3517evm_tca6416_info_0));
+ omap_register_i2c_bus(3, 400, am3517evm_ui_tca6416_info,
+ ARRAY_SIZE(am3517evm_ui_tca6416_info));
+
+ return 0;
+}
+
+static int lcd_enabled;
+static int dvi_enabled;
+
+static void __init am3517_evm_display_init(void)
+{
+ int r;
+
+ omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN);
+ omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN);
+ /*
+ * Enable GPIO 182 = LCD Backlight Power
+ */
+ r = gpio_request(LCD_PANEL_BKLIGHT_PWR, "lcd_backlight_pwr");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_backlight_pwr\n");
+ return;
+ }
+ gpio_direction_output(LCD_PANEL_BKLIGHT_PWR, 1);
+ /*
+ * Enable GPIO 181 = LCD Panel PWM
+ */
+ r = gpio_request(LCD_PANEL_PWM, "lcd_pwm");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_pwm\n");
+ goto err_1;
+ }
+ gpio_direction_output(LCD_PANEL_PWM, 1);
+ /*
+ * Enable GPIO 176 = LCD Panel Power enable pin
+ */
+ r = gpio_request(LCD_PANEL_PWR, "lcd_panel_pwr");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_pwr\n");
+ goto err_2;
+ }
+ gpio_direction_output(LCD_PANEL_PWR, 1);
+
+ printk(KERN_INFO "Display initialized successfully\n");
+ return;
+
+err_2:
+ gpio_free(LCD_PANEL_PWM);
+err_1:
+ gpio_free(LCD_PANEL_BKLIGHT_PWR);
+}
+
+static int am3517_evm_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+ if (dvi_enabled) {
+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
+ return -EINVAL;
+ }
+ gpio_set_value(LCD_PANEL_PWR, 1);
+ lcd_enabled = 1;
+
+ return 0;
+}
+
+static void am3517_evm_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+ gpio_set_value(LCD_PANEL_PWR, 0);
+ lcd_enabled = 0;
+}
+
+static struct omap_dss_device am3517_evm_lcd_device = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = "lcd",
+ .driver_name = "sharp_lq_panel",
+ .phy.dpi.data_lines = 16,
+ .platform_enable = am3517_evm_panel_enable_lcd,
+ .platform_disable = am3517_evm_panel_disable_lcd,
+};
+
+static int am3517_evm_panel_enable_tv(struct omap_dss_device *dssdev)
+{
+ return 0;
+}
+
+static void am3517_evm_panel_disable_tv(struct omap_dss_device *dssdev)
+{
+}
+
+static struct omap_dss_device am3517_evm_tv_device = {
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .name = "tv",
+ .driver_name = "venc",
+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+ .platform_enable = am3517_evm_panel_enable_tv,
+ .platform_disable = am3517_evm_panel_disable_tv,
+};
+
+static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev)
+{
+ if (lcd_enabled) {
+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
+ return -EINVAL;
+ }
+ dvi_enabled = 1;
+
+ return 0;
+}
+
+static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
+{
+ dvi_enabled = 0;
+}
+
+static struct omap_dss_device am3517_evm_dvi_device = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = "dvi",
+ .driver_name = "generic_panel",
+ .phy.dpi.data_lines = 24,
+ .platform_enable = am3517_evm_panel_enable_dvi,
+ .platform_disable = am3517_evm_panel_disable_dvi,
+};
+
+static struct omap_dss_device *am3517_evm_dss_devices[] = {
+ &am3517_evm_lcd_device,
+ &am3517_evm_tv_device,
+ &am3517_evm_dvi_device,
+};
+
+static struct omap_dss_board_info am3517_evm_dss_data = {
+ .num_devices = ARRAY_SIZE(am3517_evm_dss_devices),
+ .devices = am3517_evm_dss_devices,
+ .default_device = &am3517_evm_lcd_device,
+};
+
+struct platform_device am3517_evm_dss_device = {
+ .name = "omapdss",
+ .id = -1,
+ .dev = {
+ .platform_data = &am3517_evm_dss_data,
+ },
+};
+
/*
* Board initialization
*/
@@ -39,6 +260,7 @@ static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
};
static struct platform_device *am3517_evm_devices[] __initdata = {
+ &am3517_evm_dss_device,
};
static void __init am3517_evm_init_irq(void)
@@ -51,7 +273,7 @@ static void __init am3517_evm_init_irq(void)
omap_gpio_init();
}
-static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -73,17 +295,30 @@ static struct omap_board_mux board_mux[] __initdata = {
static void __init am3517_evm_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+ am3517_evm_i2c_init();
platform_add_devices(am3517_evm_devices,
ARRAY_SIZE(am3517_evm_devices));
omap_serial_init();
+
+ /* Configure GPIO for EHCI port */
+ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
usb_ehci_init(&ehci_pdata);
+ /* DSS */
+ am3517_evm_display_init();
+
+ /* RTC - S35390A */
+ am3517_evm_rtc_init();
+
+ i2c_register_board_info(1, am3517evm_i2c_boardinfo,
+ ARRAY_SIZE(am3517evm_i2c_boardinfo));
}
static void __init am3517_evm_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index fbbd68d69cc..aa69fb99974 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -337,7 +337,7 @@ static void __init omap_apollon_init(void)
static void __init omap_apollon_map_io(void)
{
omap2_set_globals_242x();
- omap2_map_common_io();
+ omap242x_map_common_io();
}
MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 2626a9f8a73..2de4f79f03a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -32,6 +32,9 @@
#include <linux/i2c/twl.h>
#include <linux/regulator/machine.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/tdo24m.h>
+
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -41,12 +44,13 @@
#include <plat/nand.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
+#include <plat/display.h>
#include <mach/hardware.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define CM_T35_GPIO_PENDOWN 57
@@ -248,7 +252,6 @@ static inline void cm_t35_init_nand(void) {}
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <plat/mcspi.h>
@@ -304,6 +307,193 @@ static void __init cm_t35_init_ads7846(void)
static inline void cm_t35_init_ads7846(void) {}
#endif
+#define CM_T35_LCD_EN_GPIO 157
+#define CM_T35_LCD_BL_GPIO 58
+#define CM_T35_DVI_EN_GPIO 54
+
+static int lcd_bl_gpio;
+static int lcd_en_gpio;
+static int dvi_en_gpio;
+
+static int lcd_enabled;
+static int dvi_enabled;
+
+static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+ if (dvi_enabled) {
+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
+ return -EINVAL;
+ }
+
+ gpio_set_value(lcd_en_gpio, 1);
+ gpio_set_value(lcd_bl_gpio, 1);
+
+ lcd_enabled = 1;
+
+ return 0;
+}
+
+static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+ lcd_enabled = 0;
+
+ gpio_set_value(lcd_bl_gpio, 0);
+ gpio_set_value(lcd_en_gpio, 0);
+}
+
+static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
+{
+ if (lcd_enabled) {
+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
+ return -EINVAL;
+ }
+
+ gpio_set_value(dvi_en_gpio, 0);
+ dvi_enabled = 1;
+
+ return 0;
+}
+
+static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
+{
+ gpio_set_value(dvi_en_gpio, 1);
+ dvi_enabled = 0;
+}
+
+static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
+{
+ return 0;
+}
+
+static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
+{
+}
+
+static struct omap_dss_device cm_t35_lcd_device = {
+ .name = "lcd",
+ .driver_name = "toppoly_tdo35s_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 18,
+ .platform_enable = cm_t35_panel_enable_lcd,
+ .platform_disable = cm_t35_panel_disable_lcd,
+};
+
+static struct omap_dss_device cm_t35_dvi_device = {
+ .name = "dvi",
+ .driver_name = "generic_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 24,
+ .platform_enable = cm_t35_panel_enable_dvi,
+ .platform_disable = cm_t35_panel_disable_dvi,
+};
+
+static struct omap_dss_device cm_t35_tv_device = {
+ .name = "tv",
+ .driver_name = "venc",
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+ .platform_enable = cm_t35_panel_enable_tv,
+ .platform_disable = cm_t35_panel_disable_tv,
+};
+
+static struct omap_dss_device *cm_t35_dss_devices[] = {
+ &cm_t35_lcd_device,
+ &cm_t35_dvi_device,
+ &cm_t35_tv_device,
+};
+
+static struct omap_dss_board_info cm_t35_dss_data = {
+ .num_devices = ARRAY_SIZE(cm_t35_dss_devices),
+ .devices = cm_t35_dss_devices,
+ .default_device = &cm_t35_dvi_device,
+};
+
+static struct platform_device cm_t35_dss_device = {
+ .name = "omapdss",
+ .id = -1,
+ .dev = {
+ .platform_data = &cm_t35_dss_data,
+ },
+};
+
+static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
+ .turbo_mode = 0,
+ .single_channel = 1, /* 0: slave, 1: master */
+};
+
+static struct tdo24m_platform_data tdo24m_config = {
+ .model = TDO35S,
+};
+
+static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
+ {
+ .modalias = "tdo24m",
+ .bus_num = 4,
+ .chip_select = 0,
+ .max_speed_hz = 1000000,
+ .controller_data = &tdo24m_mcspi_config,
+ .platform_data = &tdo24m_config,
+ },
+};
+
+static void __init cm_t35_init_display(void)
+{
+ int err;
+
+ lcd_en_gpio = CM_T35_LCD_EN_GPIO;
+ lcd_bl_gpio = CM_T35_LCD_BL_GPIO;
+ dvi_en_gpio = CM_T35_DVI_EN_GPIO;
+
+ spi_register_board_info(cm_t35_lcd_spi_board_info,
+ ARRAY_SIZE(cm_t35_lcd_spi_board_info));
+
+ err = gpio_request(lcd_en_gpio, "LCD RST");
+ if (err) {
+ pr_err("CM-T35: failed to get LCD reset GPIO\n");
+ goto out;
+ }
+
+ err = gpio_request(lcd_bl_gpio, "LCD BL");
+ if (err) {
+ pr_err("CM-T35: failed to get LCD backlight control GPIO\n");
+ goto err_lcd_bl;
+ }
+
+ err = gpio_request(dvi_en_gpio, "DVI EN");
+ if (err) {
+ pr_err("CM-T35: failed to get DVI reset GPIO\n");
+ goto err_dvi_en;
+ }
+
+ gpio_export(lcd_en_gpio, 0);
+ gpio_export(lcd_bl_gpio, 0);
+ gpio_export(dvi_en_gpio, 0);
+ gpio_direction_output(lcd_en_gpio, 0);
+ gpio_direction_output(lcd_bl_gpio, 0);
+ gpio_direction_output(dvi_en_gpio, 1);
+
+ msleep(50);
+ gpio_set_value(lcd_en_gpio, 1);
+
+ err = platform_device_register(&cm_t35_dss_device);
+ if (err) {
+ pr_err("CM-T35: failed to register DSS device\n");
+ goto err_dev_reg;
+ }
+
+ return;
+
+err_dev_reg:
+ gpio_free(dvi_en_gpio);
+err_dvi_en:
+ gpio_free(lcd_bl_gpio);
+err_lcd_bl:
+ gpio_free(lcd_en_gpio);
+out:
+
+ return;
+}
+
static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
.supply = "vmmc",
};
@@ -312,6 +502,16 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
.supply = "vmmc_aux",
};
+static struct regulator_consumer_supply cm_t35_vdac_supply = {
+ .supply = "vdda_dac",
+ .dev = &cm_t35_dss_device.dev,
+};
+
+static struct regulator_consumer_supply cm_t35_vdvi_supply = {
+ .supply = "vdvi",
+ .dev = &cm_t35_dss_device.dev,
+};
+
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {
.constraints = {
@@ -342,6 +542,35 @@ static struct regulator_init_data cm_t35_vsim = {
.consumer_supplies = &cm_t35_vsim_supply,
};
+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+static struct regulator_init_data cm_t35_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &cm_t35_vdac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data cm_t35_vpll2 = {
+ .constraints = {
+ .name = "VDVI",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &cm_t35_vdvi_supply,
+};
+
static struct twl4030_usb_data cm_t35_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
@@ -364,7 +593,7 @@ static struct twl4030_keypad_data cm_t35_kp_data = {
.rep = 1,
};
-static struct twl4030_hsmmc_info mmc[] = {
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 4,
@@ -383,7 +612,7 @@ static struct twl4030_hsmmc_info mmc[] = {
{} /* Terminator */
};
-static struct ehci_hcd_omap_platform_data ehci_pdata = {
+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -413,7 +642,7 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
cm_t35_vmmc1_supply.dev = mmc[0].dev;
@@ -445,6 +674,8 @@ static struct twl4030_platform_data cm_t35_twldata = {
.gpio = &cm_t35_gpio_data,
.vmmc1 = &cm_t35_vmmc1,
.vsim = &cm_t35_vsim,
+ .vdac = &cm_t35_vdac,
+ .vpll2 = &cm_t35_vpll2,
};
static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = {
@@ -479,7 +710,7 @@ static void __init cm_t35_init_irq(void)
static void __init cm_t35_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
static struct omap_board_mux board_mux[] __initdata = {
@@ -568,6 +799,11 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+ /* display controls */
+ OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+ OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+ OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
/* TPS IRQ */
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
OMAP_PIN_INPUT_PULLUP),
@@ -575,6 +811,12 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init cm_t35_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
@@ -584,8 +826,9 @@ static void __init cm_t35_init(void)
cm_t35_init_ads7846();
cm_t35_init_ethernet();
cm_t35_init_led();
+ cm_t35_init_display();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
}
MACHINE_START(CM_T35, "Compulab CM-T35")
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
new file mode 100644
index 00000000000..47e3af2166d
--- /dev/null
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -0,0 +1,676 @@
+/*
+ * board-devkit8000.c - TimLL Devkit8000
+ *
+ * Copyright (C) 2009 Kim Botherway
+ * Copyright (C) 2010 Thomas Weber
+ *
+ * Modified from mach-omap2/board-omap3beagle.c
+ *
+ * Initial code: Syed Mohammed Khasim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc.h>
+#include <plat/nand.h>
+#include <plat/usb.h>
+#include <plat/timer-gp.h>
+#include <plat/display.h>
+
+#include <plat/mcspi.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <linux/dm9000.h>
+#include <linux/interrupt.h>
+
+#include "sdram-micron-mt46h32m32lf-6.h"
+
+#include "mux.h"
+#include "hsmmc.h"
+
+#define GPMC_CS0_BASE 0x60
+#define GPMC_CS_SIZE 0x30
+
+#define NAND_BLOCK_SIZE SZ_128K
+
+#define OMAP_DM9000_GPIO_IRQ 25
+#define OMAP3_DEVKIT_TS_GPIO 27
+
+static struct mtd_partition devkit8000_nand_partitions[] = {
+ /* All the partition sizes are listed in terms of NAND block size */
+ {
+ .name = "X-Loader",
+ .offset = 0,
+ .size = 4 * NAND_BLOCK_SIZE,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
+ .size = 15 * NAND_BLOCK_SIZE,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
+ .size = 1 * NAND_BLOCK_SIZE,
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
+ .size = 32 * NAND_BLOCK_SIZE,
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct omap_nand_platform_data devkit8000_nand_data = {
+ .options = NAND_BUSWIDTH_16,
+ .parts = devkit8000_nand_partitions,
+ .nr_parts = ARRAY_SIZE(devkit8000_nand_partitions),
+ .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+};
+
+static struct resource devkit8000_nand_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device devkit8000_nand_device = {
+ .name = "omap2-nand",
+ .id = -1,
+ .dev = {
+ .platform_data = &devkit8000_nand_data,
+ },
+ .num_resources = 1,
+ .resource = &devkit8000_nand_resource,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
+ {
+ .mmc = 1,
+ .wires = 8,
+ .gpio_wp = 29,
+ },
+ {} /* Terminator */
+};
+static struct omap_board_config_kernel devkit8000_config[] __initdata = {
+};
+
+static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
+{
+ twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1);
+ twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
+
+ return 0;
+}
+
+static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
+{
+}
+static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
+{
+ return 0;
+}
+
+static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
+{
+}
+
+static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev)
+{
+
+ return 0;
+}
+
+static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev)
+{
+}
+
+
+static struct regulator_consumer_supply devkit8000_vmmc1_supply = {
+ .supply = "vmmc",
+};
+
+static struct regulator_consumer_supply devkit8000_vsim_supply = {
+ .supply = "vmmc_aux",
+};
+
+
+static struct omap_dss_device devkit8000_lcd_device = {
+ .name = "lcd",
+ .driver_name = "innolux_at_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 24,
+ .platform_enable = devkit8000_panel_enable_lcd,
+ .platform_disable = devkit8000_panel_disable_lcd,
+};
+static struct omap_dss_device devkit8000_dvi_device = {
+ .name = "dvi",
+ .driver_name = "generic_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 24,
+ .platform_enable = devkit8000_panel_enable_dvi,
+ .platform_disable = devkit8000_panel_disable_dvi,
+};
+
+static struct omap_dss_device devkit8000_tv_device = {
+ .name = "tv",
+ .driver_name = "venc",
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+ .platform_enable = devkit8000_panel_enable_tv,
+ .platform_disable = devkit8000_panel_disable_tv,
+};
+
+
+static struct omap_dss_device *devkit8000_dss_devices[] = {
+ &devkit8000_lcd_device,
+ &devkit8000_dvi_device,
+ &devkit8000_tv_device,
+};
+
+static struct omap_dss_board_info devkit8000_dss_data = {
+ .num_devices = ARRAY_SIZE(devkit8000_dss_devices),
+ .devices = devkit8000_dss_devices,
+ .default_device = &devkit8000_lcd_device,
+};
+
+static struct platform_device devkit8000_dss_device = {
+ .name = "omapdss",
+ .id = -1,
+ .dev = {
+ .platform_data = &devkit8000_dss_data,
+ },
+};
+
+static struct regulator_consumer_supply devkit8000_vdda_dac_supply = {
+ .supply = "vdda_dac",
+ .dev = &devkit8000_dss_device.dev,
+};
+
+static int board_keymap[] = {
+ KEY(0, 0, KEY_1),
+ KEY(1, 0, KEY_2),
+ KEY(2, 0, KEY_3),
+ KEY(0, 1, KEY_4),
+ KEY(1, 1, KEY_5),
+ KEY(2, 1, KEY_6),
+ KEY(3, 1, KEY_F5),
+ KEY(0, 2, KEY_7),
+ KEY(1, 2, KEY_8),
+ KEY(2, 2, KEY_9),
+ KEY(3, 2, KEY_F6),
+ KEY(0, 3, KEY_F7),
+ KEY(1, 3, KEY_0),
+ KEY(2, 3, KEY_F8),
+ PERSISTENT_KEY(4, 5),
+ KEY(4, 4, KEY_VOLUMEUP),
+ KEY(5, 5, KEY_VOLUMEDOWN),
+ 0
+};
+
+static struct matrix_keymap_data board_map_data = {
+ .keymap = board_keymap,
+ .keymap_size = ARRAY_SIZE(board_keymap),
+};
+
+static struct twl4030_keypad_data devkit8000_kp_data = {
+ .keymap_data = &board_map_data,
+ .rows = 6,
+ .cols = 6,
+ .rep = 1,
+};
+
+static struct gpio_led gpio_leds[];
+
+static int devkit8000_twl_gpio_setup(struct device *dev,
+ unsigned gpio, unsigned ngpio)
+{
+ omap_mux_init_gpio(29, OMAP_PIN_INPUT);
+ /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+ mmc[0].gpio_cd = gpio + 0;
+ omap2_hsmmc_init(mmc);
+
+ /* link regulators to MMC adapters */
+ devkit8000_vmmc1_supply.dev = mmc[0].dev;
+ devkit8000_vsim_supply.dev = mmc[0].dev;
+
+ return 0;
+}
+
+static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+ .irq_base = TWL4030_GPIO_IRQ_BASE,
+ .irq_end = TWL4030_GPIO_IRQ_END,
+ .use_leds = true,
+ .pullups = BIT(1),
+ .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
+ | BIT(15) | BIT(16) | BIT(17),
+ .setup = devkit8000_twl_gpio_setup,
+};
+
+static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = {
+ {
+ .supply = "vdvi",
+ .dev = &devkit8000_lcd_device.dev,
+ },
+ {
+ .supply = "vdds_dsi",
+ .dev = &devkit8000_dss_device.dev,
+ }
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data devkit8000_vmmc1 = {
+ .constraints = {
+ .min_uV = 1850000,
+ .max_uV = 3150000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &devkit8000_vmmc1_supply,
+};
+
+/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+static struct regulator_init_data devkit8000_vsim = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 3000000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &devkit8000_vsim_supply,
+};
+
+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+static struct regulator_init_data devkit8000_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &devkit8000_vdda_dac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data devkit8000_vpll2 = {
+ .constraints = {
+ .name = "VDVI",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll2_supplies),
+ .consumer_supplies = devkit8000_vpll2_supplies,
+};
+
+static struct twl4030_usb_data devkit8000_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_codec_audio_data devkit8000_audio_data = {
+ .audio_mclk = 26000000,
+};
+
+static struct twl4030_codec_data devkit8000_codec_data = {
+ .audio_mclk = 26000000,
+ .audio = &devkit8000_audio_data,
+};
+
+static struct twl4030_platform_data devkit8000_twldata = {
+ .irq_base = TWL4030_IRQ_BASE,
+ .irq_end = TWL4030_IRQ_END,
+
+ /* platform_data for children goes here */
+ .usb = &devkit8000_usb_data,
+ .gpio = &devkit8000_gpio_data,
+ .codec = &devkit8000_codec_data,
+ .vmmc1 = &devkit8000_vmmc1,
+ .vsim = &devkit8000_vsim,
+ .vdac = &devkit8000_vdac,
+ .vpll2 = &devkit8000_vpll2,
+ .keypad = &devkit8000_kp_data,
+};
+
+static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("twl4030", 0x48),
+ .flags = I2C_CLIENT_WAKE,
+ .irq = INT_34XX_SYS_NIRQ,
+ .platform_data = &devkit8000_twldata,
+ },
+};
+
+static int __init devkit8000_i2c_init(void)
+{
+ omap_register_i2c_bus(1, 2600, devkit8000_i2c_boardinfo,
+ ARRAY_SIZE(devkit8000_i2c_boardinfo));
+ /* Bus 3 is attached to the DVI port where devices like the pico DLP
+ * projector don't work reliably with 400kHz */
+ omap_register_i2c_bus(3, 400, NULL, 0);
+ return 0;
+}
+
+static struct gpio_led gpio_leds[] = {
+ {
+ .name = "led1",
+ .default_trigger = "heartbeat",
+ .gpio = 186,
+ .active_low = true,
+ },
+ {
+ .name = "led2",
+ .default_trigger = "mmc0",
+ .gpio = 163,
+ .active_low = true,
+ },
+ {
+ .name = "ledB",
+ .default_trigger = "none",
+ .gpio = 153,
+ .active_low = true,
+ },
+ {
+ .name = "led3",
+ .default_trigger = "none",
+ .gpio = 164,
+ .active_low = true,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
+static struct gpio_keys_button gpio_buttons[] = {
+ {
+ .code = BTN_EXTRA,
+ .gpio = 26,
+ .desc = "user",
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data gpio_key_info = {
+ .buttons = gpio_buttons,
+ .nbuttons = ARRAY_SIZE(gpio_buttons),
+};
+
+static struct platform_device keys_gpio = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_key_info,
+ },
+};
+
+
+static void __init devkit8000_init_irq(void)
+{
+ omap_board_config = devkit8000_config;
+ omap_board_config_size = ARRAY_SIZE(devkit8000_config);
+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+ omap_init_irq();
+#ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+#endif
+ omap_gpio_init();
+}
+
+static void __init devkit8000_ads7846_init(void)
+{
+ int gpio = OMAP3_DEVKIT_TS_GPIO;
+ int ret;
+
+ ret = gpio_request(gpio, "ads7846_pen_down");
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to request GPIO %d for "
+ "ads7846 pen down IRQ\n", gpio);
+ return;
+ }
+
+ gpio_direction_input(gpio);
+}
+
+static int ads7846_get_pendown_state(void)
+{
+ return !gpio_get_value(OMAP3_DEVKIT_TS_GPIO);
+}
+
+static struct ads7846_platform_data ads7846_config = {
+ .x_max = 0x0fff,
+ .y_max = 0x0fff,
+ .x_plate_ohms = 180,
+ .pressure_max = 255,
+ .debounce_max = 10,
+ .debounce_tol = 5,
+ .debounce_rep = 1,
+ .get_pendown_state = ads7846_get_pendown_state,
+ .keep_vref_on = 1,
+ .settle_delay_usecs = 150,
+};
+
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+ .turbo_mode = 0,
+ .single_channel = 1, /* 0: slave, 1: master */
+};
+
+static struct spi_board_info devkit8000_spi_board_info[] __initdata = {
+ {
+ .modalias = "ads7846",
+ .bus_num = 2,
+ .chip_select = 0,
+ .max_speed_hz = 1500000,
+ .controller_data = &ads7846_mcspi_config,
+ .irq = OMAP_GPIO_IRQ(OMAP3_DEVKIT_TS_GPIO),
+ .platform_data = &ads7846_config,
+ }
+};
+
+#define OMAP_DM9000_BASE 0x2c000000
+
+static struct resource omap_dm9000_resources[] = {
+ [0] = {
+ .start = OMAP_DM9000_BASE,
+ .end = (OMAP_DM9000_BASE + 0x4 - 1),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = (OMAP_DM9000_BASE + 0x400),
+ .end = (OMAP_DM9000_BASE + 0x400 + 0x4 - 1),
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = OMAP_GPIO_IRQ(OMAP_DM9000_GPIO_IRQ),
+ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+ },
+};
+
+static struct dm9000_plat_data omap_dm9000_platdata = {
+ .flags = DM9000_PLATF_16BITONLY,
+};
+
+static struct platform_device omap_dm9000_dev = {
+ .name = "dm9000",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(omap_dm9000_resources),
+ .resource = omap_dm9000_resources,
+ .dev = {
+ .platform_data = &omap_dm9000_platdata,
+ },
+};
+
+static void __init omap_dm9000_init(void)
+{
+ if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) {
+ printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n",
+ OMAP_DM9000_GPIO_IRQ);
+ return;
+ }
+
+ gpio_direction_input(OMAP_DM9000_GPIO_IRQ);
+}
+
+static struct platform_device *devkit8000_devices[] __initdata = {
+ &devkit8000_dss_device,
+ &leds_gpio,
+ &keys_gpio,
+ &omap_dm9000_dev,
+};
+
+static void __init devkit8000_flash_init(void)
+{
+ u8 cs = 0;
+ u8 nandcs = GPMC_CS_NUM + 1;
+
+ u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
+
+ /* find out the chip-select on which NAND exists */
+ while (cs < GPMC_CS_NUM) {
+ u32 ret = 0;
+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+ if ((ret & 0xC00) == 0x800) {
+ printk(KERN_INFO "Found NAND on CS%d\n", cs);
+ if (nandcs > GPMC_CS_NUM)
+ nandcs = cs;
+ }
+ cs++;
+ }
+
+ if (nandcs > GPMC_CS_NUM) {
+ printk(KERN_INFO "NAND: Unable to find configuration "
+ "in GPMC\n ");
+ return;
+ }
+
+ if (nandcs < GPMC_CS_NUM) {
+ devkit8000_nand_data.cs = nandcs;
+ devkit8000_nand_data.gpmc_cs_baseaddr = (void *)
+ (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
+ devkit8000_nand_data.gpmc_baseaddr = (void *)
+ (gpmc_base_add);
+
+ printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+ if (platform_device_register(&devkit8000_nand_device) < 0)
+ printk(KERN_ERR "Unable to register NAND device\n");
+ }
+}
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+
+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+ .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+ .phy_reset = true,
+ .reset_gpio_port[0] = -EINVAL,
+ .reset_gpio_port[1] = -EINVAL,
+ .reset_gpio_port[2] = -EINVAL
+};
+
+static void __init devkit8000_init(void)
+{
+ omap_serial_init();
+
+ omap_dm9000_init();
+
+ devkit8000_i2c_init();
+ platform_add_devices(devkit8000_devices,
+ ARRAY_SIZE(devkit8000_devices));
+ omap_board_config = devkit8000_config;
+ omap_board_config_size = ARRAY_SIZE(devkit8000_config);
+
+ spi_register_board_info(devkit8000_spi_board_info,
+ ARRAY_SIZE(devkit8000_spi_board_info));
+
+ devkit8000_ads7846_init();
+
+ usb_musb_init(&musb_board_data);
+ usb_ehci_init(&ehci_pdata);
+ devkit8000_flash_init();
+
+ /* Ensure SDRC pins are mux'd for self-refresh */
+ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+static void __init devkit8000_map_io(void)
+{
+ omap2_set_globals_343x();
+ omap34xx_map_common_io();
+}
+
+MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
+ .phys_io = 0x48000000,
+ .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
+ .boot_params = 0x80000100,
+ .map_io = devkit8000_map_io,
+ .init_irq = devkit8000_init_irq,
+ .init_machine = devkit8000_init,
+ .timer = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 7e6e6ca88be..16cc0686067 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -50,7 +50,7 @@ static void __init omap_generic_init(void)
static void __init omap_generic_map_io(void)
{
omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
- omap2_map_common_io();
+ omap242x_map_common_io();
}
MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index cfb7f1257d2..0665f2c8dc8 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/i2c.h>
@@ -29,7 +30,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
#include <plat/control.h>
#include <mach/gpio.h>
@@ -115,8 +115,7 @@ static struct mtd_partition h4_partitions[] = {
}
};
-static struct flash_platform_data h4_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data h4_flash_data = {
.width = 2,
.parts = h4_partitions,
.nr_parts = ARRAY_SIZE(h4_partitions),
@@ -127,7 +126,7 @@ static struct resource h4_flash_resource = {
};
static struct platform_device h4_flash_device = {
- .name = "omapflash",
+ .name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &h4_flash_data,
@@ -370,7 +369,7 @@ static void __init omap_h4_init(void)
static void __init omap_h4_map_io(void)
{
omap2_set_globals_242x();
- omap2_map_common_io();
+ omap242x_map_common_io();
}
MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 117b8fd7e3a..d55c57b761a 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -28,16 +28,121 @@
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
+#include <plat/display.h>
+#include <plat/onenand.h>
#include "mux.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
+#include "sdram-numonyx-m65kxxxxam.h"
#define IGEP2_SMSC911X_CS 5
#define IGEP2_SMSC911X_GPIO 176
#define IGEP2_GPIO_USBH_NRESET 24
-#define IGEP2_GPIO_LED0_RED 26
-#define IGEP2_GPIO_LED0_GREEN 27
+#define IGEP2_GPIO_LED0_GREEN 26
+#define IGEP2_GPIO_LED0_RED 27
#define IGEP2_GPIO_LED1_RED 28
+#define IGEP2_GPIO_DVI_PUP 170
+#define IGEP2_GPIO_WIFI_NPD 94
+#define IGEP2_GPIO_WIFI_NRESET 95
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+
+#define ONENAND_MAP 0x20000000
+
+/* NAND04GR4E1A ( x2 Flash built-in COMBO POP MEMORY )
+ * Since the device is equipped with two DataRAMs, and two-plane NAND
+ * Flash memory array, these two component enables simultaneous program
+ * of 4KiB. Plane1 has only even blocks such as block0, block2, block4
+ * while Plane2 has only odd blocks such as block1, block3, block5.
+ * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
+ */
+
+static struct mtd_partition igep2_onenand_partitions[] = {
+ {
+ .name = "X-Loader",
+ .offset = 0,
+ .size = 2 * (64*(2*2048))
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 6 * (64*(2*2048)),
+ },
+ {
+ .name = "Environment",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 2 * (64*(2*2048)),
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 12 * (64*(2*2048)),
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static int igep2_onenand_setup(void __iomem *onenand_base, int freq)
+{
+ /* nothing is required to be setup for onenand as of now */
+ return 0;
+}
+
+static struct omap_onenand_platform_data igep2_onenand_data = {
+ .parts = igep2_onenand_partitions,
+ .nr_parts = ARRAY_SIZE(igep2_onenand_partitions),
+ .onenand_setup = igep2_onenand_setup,
+ .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
+};
+
+static struct platform_device igep2_onenand_device = {
+ .name = "omap2-onenand",
+ .id = -1,
+ .dev = {
+ .platform_data = &igep2_onenand_data,
+ },
+};
+
+void __init igep2_flash_init(void)
+{
+ u8 cs = 0;
+ u8 onenandcs = GPMC_CS_NUM + 1;
+
+ while (cs < GPMC_CS_NUM) {
+ u32 ret = 0;
+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+ /* Check if NAND/oneNAND is configured */
+ if ((ret & 0xC00) == 0x800)
+ /* NAND found */
+ pr_err("IGEP v2: Unsupported NAND found\n");
+ else {
+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+ if ((ret & 0x3F) == (ONENAND_MAP >> 24))
+ /* ONENAND found */
+ onenandcs = cs;
+ }
+ cs++;
+ }
+ if (onenandcs > GPMC_CS_NUM) {
+ pr_err("IGEP v2: Unable to find configuration in GPMC\n");
+ return;
+ }
+
+ if (onenandcs < GPMC_CS_NUM) {
+ igep2_onenand_data.cs = onenandcs;
+ if (platform_device_register(&igep2_onenand_device) < 0)
+ pr_err("IGEP v2: Unable to register OneNAND device\n");
+ }
+}
+
+#else
+void __init igep2_flash_init(void) {}
+#endif
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -106,6 +211,10 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = {
.supply = "vmmc",
};
+static struct regulator_consumer_supply igep2_vmmc2_supply = {
+ .supply = "vmmc",
+};
+
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data igep2_vmmc1 = {
.constraints = {
@@ -121,7 +230,22 @@ static struct regulator_init_data igep2_vmmc1 = {
.consumer_supplies = &igep2_vmmc1_supply,
};
-static struct twl4030_hsmmc_info mmc[] = {
+/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */
+static struct regulator_init_data igep2_vmmc2 = {
+ .constraints = {
+ .min_uV = 1850000,
+ .max_uV = 3150000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &igep2_vmmc2_supply,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 4,
@@ -142,12 +266,13 @@ static int igep2_twl_gpio_setup(struct device *dev,
{
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
* regulators will be set up only *after* we return.
*/
igep2_vmmc1_supply.dev = mmc[0].dev;
+ igep2_vmmc2_supply.dev = mmc[1].dev;
return 0;
};
@@ -164,23 +289,146 @@ static struct twl4030_usb_data igep2_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
+static int igep2_enable_dvi(struct omap_dss_device *dssdev)
+{
+ gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
+
+ return 0;
+}
+
+static void igep2_disable_dvi(struct omap_dss_device *dssdev)
+{
+ gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0);
+}
+
+static struct omap_dss_device igep2_dvi_device = {
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .name = "dvi",
+ .driver_name = "generic_panel",
+ .phy.dpi.data_lines = 24,
+ .platform_enable = igep2_enable_dvi,
+ .platform_disable = igep2_disable_dvi,
+};
+
+static struct omap_dss_device *igep2_dss_devices[] = {
+ &igep2_dvi_device
+};
+
+static struct omap_dss_board_info igep2_dss_data = {
+ .num_devices = ARRAY_SIZE(igep2_dss_devices),
+ .devices = igep2_dss_devices,
+ .default_device = &igep2_dvi_device,
+};
+
+static struct platform_device igep2_dss_device = {
+ .name = "omapdss",
+ .id = -1,
+ .dev = {
+ .platform_data = &igep2_dss_data,
+ },
+};
+
+static struct regulator_consumer_supply igep2_vpll2_supply = {
+ .supply = "vdds_dsi",
+ .dev = &igep2_dss_device.dev,
+};
+
+static struct regulator_init_data igep2_vpll2 = {
+ .constraints = {
+ .name = "VDVI",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &igep2_vpll2_supply,
+};
+
+static void __init igep2_display_init(void)
+{
+ if (gpio_request(IGEP2_GPIO_DVI_PUP, "GPIO_DVI_PUP") &&
+ gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1))
+ pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
+}
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led igep2_gpio_leds[] = {
+ {
+ .name = "led0:red",
+ .gpio = IGEP2_GPIO_LED0_RED,
+ },
+ {
+ .name = "led0:green",
+ .default_trigger = "heartbeat",
+ .gpio = IGEP2_GPIO_LED0_GREEN,
+ },
+ {
+ .name = "led1:red",
+ .gpio = IGEP2_GPIO_LED1_RED,
+ },
+};
+
+static struct gpio_led_platform_data igep2_led_pdata = {
+ .leds = igep2_gpio_leds,
+ .num_leds = ARRAY_SIZE(igep2_gpio_leds),
+};
+
+static struct platform_device igep2_led_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &igep2_led_pdata,
+ },
+};
+
+static void __init igep2_init_led(void)
+{
+ platform_device_register(&igep2_led_device);
+}
+
+#else
+static inline void igep2_init_led(void) {}
+#endif
+
+static struct platform_device *igep2_devices[] __initdata = {
+ &igep2_dss_device,
+};
+
static void __init igep2_init_irq(void)
{
omap_board_config = igep2_config;
omap_board_config_size = ARRAY_SIZE(igep2_config);
- omap2_init_common_hw(NULL, NULL);
+ omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
+static struct twl4030_codec_audio_data igep2_audio_data = {
+ .audio_mclk = 26000000,
+};
+
+static struct twl4030_codec_data igep2_codec_data = {
+ .audio_mclk = 26000000,
+ .audio = &igep2_audio_data,
+};
+
static struct twl4030_platform_data igep2_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &igep2_usb_data,
+ .codec = &igep2_codec_data,
.gpio = &igep2_gpio_data,
.vmmc1 = &igep2_vmmc1,
+ .vmmc2 = &igep2_vmmc2,
+ .vpll2 = &igep2_vpll2,
};
@@ -203,6 +451,23 @@ static int __init igep2_i2c_init(void)
return 0;
}
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+ .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+ .phy_reset = true,
+ .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
+ .reset_gpio_port[1] = -EINVAL,
+ .reset_gpio_port[2] = -EINVAL,
+};
+
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
@@ -215,38 +480,62 @@ static void __init igep2_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
igep2_i2c_init();
+ platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
omap_serial_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
+ usb_ehci_init(&ehci_pdata);
+ igep2_flash_init();
+ igep2_init_led();
+ igep2_display_init();
igep2_init_smsc911x();
/* GPIO userspace leds */
- if ((gpio_request(IGEP2_GPIO_LED0_RED, "GPIO_LED0_RED") == 0) &&
+#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
+ if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) &&
(gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
gpio_export(IGEP2_GPIO_LED0_RED, 0);
gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
} else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
- if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "GPIO_LED0_GREEN") == 0) &&
+ if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) &&
(gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
} else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
- if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_LED1_RED") == 0) &&
+ if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) &&
(gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
gpio_export(IGEP2_GPIO_LED1_RED, 0);
gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
} else
pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
+#endif
+
+ /* GPIO W-LAN + Bluetooth combo module */
+ if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
+ (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) {
+ gpio_export(IGEP2_GPIO_WIFI_NPD, 0);
+/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */
+ } else
+ pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n");
+
+ if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
+ (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) {
+ gpio_export(IGEP2_GPIO_WIFI_NRESET, 0);
+ gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0);
+ udelay(10);
+ gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1);
+ } else
+ pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n");
}
static void __init igep2_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(IGEP0020, "IGEP v2 board")
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 995d4a2b2df..5fcb52e7129 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -44,7 +44,7 @@
#include <plat/usb.h>
#include "mux.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define LDP_SMSC911X_CS 1
#define LDP_SMSC911X_GPIO 152
@@ -359,7 +359,7 @@ static int __init omap_i2c_init(void)
return 0;
}
-static struct twl4030_hsmmc_info mmc[] __initdata = {
+static struct omap2_hsmmc_info mmc[] __initdata = {
{
.mmc = 1,
.wires = 4,
@@ -383,6 +383,12 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init omap_ldp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -394,9 +400,9 @@ static void __init omap_ldp_init(void)
ARRAY_SIZE(ldp_spi_board_info));
ads7846_dev_init();
omap_serial_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
ldp_vmmc1_supply.dev = mmc[0].dev;
}
@@ -404,7 +410,7 @@ static void __init omap_ldp_init(void)
static void __init omap_ldp_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP_LDP, "OMAP LDP board")
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 764ab1ed576..3ccc34ebdcc 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -17,6 +17,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/stddef.h>
+#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/usb/musb.h>
@@ -25,11 +26,114 @@
#include <plat/board.h>
#include <plat/common.h>
+#include <plat/menelaus.h>
#include <mach/irqs.h>
#include <plat/mcspi.h>
#include <plat/onenand.h>
+#include <plat/mmc.h>
#include <plat/serial.h>
+static int slot1_cover_open;
+static int slot2_cover_open;
+static struct device *mmc_device;
+
+#define TUSB6010_ASYNC_CS 1
+#define TUSB6010_SYNC_CS 4
+#define TUSB6010_GPIO_INT 58
+#define TUSB6010_GPIO_ENABLE 0
+#define TUSB6010_DMACHAN 0x3f
+
+#if defined(CONFIG_USB_TUSB6010) || \
+ defined(CONFIG_USB_TUSB6010_MODULE)
+/*
+ * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
+ * 1.5 V voltage regulators of PM companion chip. Companion chip will then
+ * provide then PGOOD signal to TUSB6010 which will release it from reset.
+ */
+static int tusb_set_power(int state)
+{
+ int i, retval = 0;
+
+ if (state) {
+ gpio_set_value(TUSB6010_GPIO_ENABLE, 1);
+ msleep(1);
+
+ /* Wait until TUSB6010 pulls INT pin down */
+ i = 100;
+ while (i && gpio_get_value(TUSB6010_GPIO_INT)) {
+ msleep(1);
+ i--;
+ }
+
+ if (!i) {
+ printk(KERN_ERR "tusb: powerup failed\n");
+ retval = -ENODEV;
+ }
+ } else {
+ gpio_set_value(TUSB6010_GPIO_ENABLE, 0);
+ msleep(10);
+ }
+
+ return retval;
+}
+
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct musb_hdrc_platform_data tusb_data = {
+#if defined(CONFIG_USB_MUSB_OTG)
+ .mode = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
+ .mode = MUSB_PERIPHERAL,
+#else /* defined(CONFIG_USB_MUSB_HOST) */
+ .mode = MUSB_HOST,
+#endif
+ .set_power = tusb_set_power,
+ .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */
+ .power = 100, /* Max 100 mA VBUS for host mode */
+ .config = &musb_config,
+};
+
+static void __init n8x0_usb_init(void)
+{
+ int ret = 0;
+ static char announce[] __initdata = KERN_INFO "TUSB 6010\n";
+
+ /* PM companion chip power control pin */
+ ret = gpio_request(TUSB6010_GPIO_ENABLE, "TUSB6010 enable");
+ if (ret != 0) {
+ printk(KERN_ERR "Could not get TUSB power GPIO%i\n",
+ TUSB6010_GPIO_ENABLE);
+ return;
+ }
+ gpio_direction_output(TUSB6010_GPIO_ENABLE, 0);
+
+ tusb_set_power(0);
+
+ ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
+ TUSB6010_ASYNC_CS, TUSB6010_SYNC_CS,
+ TUSB6010_GPIO_INT, TUSB6010_DMACHAN);
+ if (ret != 0)
+ goto err;
+
+ printk(announce);
+
+ return;
+
+err:
+ gpio_free(TUSB6010_GPIO_ENABLE);
+}
+#else
+
+static void __init n8x0_usb_init(void) {}
+
+#endif /*CONFIG_USB_TUSB6010 */
+
+
static struct omap2_mcspi_device_config p54spi_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1,
@@ -96,10 +200,446 @@ static void __init n8x0_onenand_init(void) {}
#endif
+#if defined(CONFIG_MENELAUS) && \
+ (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
+
+/*
+ * On both N800 and N810, only the first of the two MMC controllers is in use.
+ * The two MMC slots are multiplexed via Menelaus companion chip over I2C.
+ * On N800, both slots are powered via Menelaus. On N810, only one of the
+ * slots is powered via Menelaus. The N810 EMMC is powered via GPIO.
+ *
+ * VMMC slot 1 on both N800 and N810
+ * VDCDC3_APE and VMCS2_APE slot 2 on N800
+ * GPIO23 and GPIO9 slot 2 EMMC on N810
+ *
+ */
+#define N8X0_SLOT_SWITCH_GPIO 96
+#define N810_EMMC_VSD_GPIO 23
+#define N810_EMMC_VIO_GPIO 9
+
+static int n8x0_mmc_switch_slot(struct device *dev, int slot)
+{
+#ifdef CONFIG_MMC_DEBUG
+ dev_dbg(dev, "Choose slot %d\n", slot + 1);
+#endif
+ gpio_set_value(N8X0_SLOT_SWITCH_GPIO, slot);
+ return 0;
+}
+
+static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot,
+ int power_on, int vdd)
+{
+ int mV;
+
+#ifdef CONFIG_MMC_DEBUG
+ dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
+ power_on ? "on" : "off", vdd);
+#endif
+ if (slot == 0) {
+ if (!power_on)
+ return menelaus_set_vmmc(0);
+ switch (1 << vdd) {
+ case MMC_VDD_33_34:
+ case MMC_VDD_32_33:
+ case MMC_VDD_31_32:
+ mV = 3100;
+ break;
+ case MMC_VDD_30_31:
+ mV = 3000;
+ break;
+ case MMC_VDD_28_29:
+ mV = 2800;
+ break;
+ case MMC_VDD_165_195:
+ mV = 1850;
+ break;
+ default:
+ BUG();
+ }
+ return menelaus_set_vmmc(mV);
+ } else {
+ if (!power_on)
+ return menelaus_set_vdcdc(3, 0);
+ switch (1 << vdd) {
+ case MMC_VDD_33_34:
+ case MMC_VDD_32_33:
+ mV = 3300;
+ break;
+ case MMC_VDD_30_31:
+ case MMC_VDD_29_30:
+ mV = 3000;
+ break;
+ case MMC_VDD_28_29:
+ case MMC_VDD_27_28:
+ mV = 2800;
+ break;
+ case MMC_VDD_24_25:
+ case MMC_VDD_23_24:
+ mV = 2400;
+ break;
+ case MMC_VDD_22_23:
+ case MMC_VDD_21_22:
+ mV = 2200;
+ break;
+ case MMC_VDD_20_21:
+ mV = 2000;
+ break;
+ case MMC_VDD_165_195:
+ mV = 1800;
+ break;
+ default:
+ BUG();
+ }
+ return menelaus_set_vdcdc(3, mV);
+ }
+ return 0;
+}
+
+static void n810_set_power_emmc(struct device *dev,
+ int power_on)
+{
+ dev_dbg(dev, "Set EMMC power %s\n", power_on ? "on" : "off");
+
+ if (power_on) {
+ gpio_set_value(N810_EMMC_VSD_GPIO, 1);
+ msleep(1);
+ gpio_set_value(N810_EMMC_VIO_GPIO, 1);
+ msleep(1);
+ } else {
+ gpio_set_value(N810_EMMC_VIO_GPIO, 0);
+ msleep(50);
+ gpio_set_value(N810_EMMC_VSD_GPIO, 0);
+ msleep(50);
+ }
+}
+
+static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
+ int vdd)
+{
+ if (machine_is_nokia_n800() || slot == 0)
+ return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
+
+ n810_set_power_emmc(dev, power_on);
+
+ return 0;
+}
+
+static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
+{
+ int r;
+
+ dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1,
+ bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
+ BUG_ON(slot != 0 && slot != 1);
+ slot++;
+ switch (bus_mode) {
+ case MMC_BUSMODE_OPENDRAIN:
+ r = menelaus_set_mmc_opendrain(slot, 1);
+ break;
+ case MMC_BUSMODE_PUSHPULL:
+ r = menelaus_set_mmc_opendrain(slot, 0);
+ break;
+ default:
+ BUG();
+ }
+ if (r != 0 && printk_ratelimit())
+ dev_err(dev, "MMC: unable to set bus mode for slot %d\n",
+ slot);
+ return r;
+}
+
+static int n8x0_mmc_get_cover_state(struct device *dev, int slot)
+{
+ slot++;
+ BUG_ON(slot != 1 && slot != 2);
+ if (slot == 1)
+ return slot1_cover_open;
+ else
+ return slot2_cover_open;
+}
+
+static void n8x0_mmc_callback(void *data, u8 card_mask)
+{
+ int bit, *openp, index;
+
+ if (machine_is_nokia_n800()) {
+ bit = 1 << 1;
+ openp = &slot2_cover_open;
+ index = 1;
+ } else {
+ bit = 1;
+ openp = &slot1_cover_open;
+ index = 0;
+ }
+
+ if (card_mask & bit)
+ *openp = 1;
+ else
+ *openp = 0;
+
+ omap_mmc_notify_cover_event(mmc_device, index, *openp);
+}
+
+void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state)
+{
+ if (mmc_device == NULL)
+ return;
+
+ slot1_cover_open = !closed_state;
+ omap_mmc_notify_cover_event(mmc_device, 0, closed_state);
+}
+
+static int n8x0_mmc_late_init(struct device *dev)
+{
+ int r, bit, *openp;
+ int vs2sel;
+
+ mmc_device = dev;
+
+ r = menelaus_set_slot_sel(1);
+ if (r < 0)
+ return r;
+
+ if (machine_is_nokia_n800())
+ vs2sel = 0;
+ else
+ vs2sel = 2;
+
+ r = menelaus_set_mmc_slot(2, 0, vs2sel, 1);
+ if (r < 0)
+ return r;
+
+ n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */
+ n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16);
+
+ r = menelaus_set_mmc_slot(1, 1, 0, 1);
+ if (r < 0)
+ return r;
+ r = menelaus_set_mmc_slot(2, 1, vs2sel, 1);
+ if (r < 0)
+ return r;
+
+ r = menelaus_get_slot_pin_states();
+ if (r < 0)
+ return r;
+
+ if (machine_is_nokia_n800()) {
+ bit = 1 << 1;
+ openp = &slot2_cover_open;
+ } else {
+ bit = 1;
+ openp = &slot1_cover_open;
+ slot2_cover_open = 0;
+ }
+
+ /* All slot pin bits seem to be inversed until first switch change */
+ if (r == 0xf || r == (0xf & ~bit))
+ r = ~r;
+
+ if (r & bit)
+ *openp = 1;
+ else
+ *openp = 0;
+
+ r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL);
+
+ return r;
+}
+
+static void n8x0_mmc_shutdown(struct device *dev)
+{
+ int vs2sel;
+
+ if (machine_is_nokia_n800())
+ vs2sel = 0;
+ else
+ vs2sel = 2;
+
+ menelaus_set_mmc_slot(1, 0, 0, 0);
+ menelaus_set_mmc_slot(2, 0, vs2sel, 0);
+}
+
+static void n8x0_mmc_cleanup(struct device *dev)
+{
+ menelaus_unregister_mmc_callback();
+
+ gpio_free(N8X0_SLOT_SWITCH_GPIO);
+
+ if (machine_is_nokia_n810()) {
+ gpio_free(N810_EMMC_VSD_GPIO);
+ gpio_free(N810_EMMC_VIO_GPIO);
+ }
+}
+
+/*
+ * MMC controller1 has two slots that are multiplexed via I2C.
+ * MMC controller2 is not in use.
+ */
+static struct omap_mmc_platform_data mmc1_data = {
+ .nr_slots = 2,
+ .switch_slot = n8x0_mmc_switch_slot,
+ .init = n8x0_mmc_late_init,
+ .cleanup = n8x0_mmc_cleanup,
+ .shutdown = n8x0_mmc_shutdown,
+ .max_freq = 24000000,
+ .dma_mask = 0xffffffff,
+ .slots[0] = {
+ .wires = 4,
+ .set_power = n8x0_mmc_set_power,
+ .set_bus_mode = n8x0_mmc_set_bus_mode,
+ .get_cover_state = n8x0_mmc_get_cover_state,
+ .ocr_mask = MMC_VDD_165_195 | MMC_VDD_30_31 |
+ MMC_VDD_32_33 | MMC_VDD_33_34,
+ .name = "internal",
+ },
+ .slots[1] = {
+ .set_power = n8x0_mmc_set_power,
+ .set_bus_mode = n8x0_mmc_set_bus_mode,
+ .get_cover_state = n8x0_mmc_get_cover_state,
+ .ocr_mask = MMC_VDD_165_195 | MMC_VDD_20_21 |
+ MMC_VDD_21_22 | MMC_VDD_22_23 |
+ MMC_VDD_23_24 | MMC_VDD_24_25 |
+ MMC_VDD_27_28 | MMC_VDD_28_29 |
+ MMC_VDD_29_30 | MMC_VDD_30_31 |
+ MMC_VDD_32_33 | MMC_VDD_33_34,
+ .name = "external",
+ },
+};
+
+static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
+
+void __init n8x0_mmc_init(void)
+
+{
+ int err;
+
+ if (machine_is_nokia_n810()) {
+ mmc1_data.slots[0].name = "external";
+
+ /*
+ * Some Samsung Movinand chips do not like open-ended
+ * multi-block reads and fall to braind-dead state
+ * while doing so. Reducing the number of blocks in
+ * the transfer or delays in clock disable do not help
+ */
+ mmc1_data.slots[1].name = "internal";
+ mmc1_data.slots[1].ban_openended = 1;
+ }
+
+ err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch");
+ if (err)
+ return;
+
+ gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0);
+
+ if (machine_is_nokia_n810()) {
+ err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf");
+ if (err) {
+ gpio_free(N8X0_SLOT_SWITCH_GPIO);
+ return;
+ }
+ gpio_direction_output(N810_EMMC_VSD_GPIO, 0);
+
+ err = gpio_request(N810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
+ if (err) {
+ gpio_free(N8X0_SLOT_SWITCH_GPIO);
+ gpio_free(N810_EMMC_VSD_GPIO);
+ return;
+ }
+ gpio_direction_output(N810_EMMC_VIO_GPIO, 0);
+ }
+
+ mmc_data[0] = &mmc1_data;
+ omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC);
+}
+#else
+
+void __init n8x0_mmc_init(void)
+{
+}
+
+void n8x0_mmc_slot1_cover_handler(void *arg, int state)
+{
+}
+
+#endif /* CONFIG_MMC_OMAP */
+
+#ifdef CONFIG_MENELAUS
+
+static int n8x0_auto_sleep_regulators(void)
+{
+ u32 val;
+ int ret;
+
+ val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \
+ | EN_VAUX_SLEEP | EN_VIO_SLEEP \
+ | EN_VMEM_SLEEP | EN_DC3_SLEEP \
+ | EN_VC_SLEEP | EN_DC2_SLEEP;
+
+ ret = menelaus_set_regulator_sleep(1, val);
+ if (ret < 0) {
+ printk(KERN_ERR "Could not set regulators to sleep on "
+ "menelaus: %u\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int n8x0_auto_voltage_scale(void)
+{
+ int ret;
+
+ ret = menelaus_set_vcore_hw(1400, 1050);
+ if (ret < 0) {
+ printk(KERN_ERR "Could not set VCORE voltage on "
+ "menelaus: %u\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int n8x0_menelaus_late_init(struct device *dev)
+{
+ int ret;
+
+ ret = n8x0_auto_voltage_scale();
+ if (ret < 0)
+ return ret;
+ ret = n8x0_auto_sleep_regulators();
+ if (ret < 0)
+ return ret;
+ return 0;
+}
+
+static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = {
+ {
+ I2C_BOARD_INFO("menelaus", 0x72),
+ .irq = INT_24XX_SYS_NIRQ,
+ },
+};
+
+static struct menelaus_platform_data n8x0_menelaus_platform_data = {
+ .late_init = n8x0_menelaus_late_init,
+};
+
+static void __init n8x0_menelaus_init(void)
+{
+ n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data;
+ omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
+ ARRAY_SIZE(n8x0_i2c_board_info_1));
+}
+
+#else
+static inline void __init n8x0_menelaus_init(void)
+{
+}
+#endif
+
static void __init n8x0_map_io(void)
{
omap2_set_globals_242x();
- omap2_map_common_io();
+ omap242x_map_common_io();
}
static void __init n8x0_init_irq(void)
@@ -116,7 +656,10 @@ static void __init n8x0_init_machine(void)
ARRAY_SIZE(n800_spi_board_info));
omap_serial_init();
+ n8x0_menelaus_init();
n8x0_onenand_init();
+ n8x0_mmc_init();
+ n8x0_usb_init();
}
MACHINE_START(NOKIA_N800, "Nokia N800")
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 231cb4ec184..962d377970e 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -45,7 +45,7 @@
#include <plat/timer-gp.h>
#include "mux.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define GPMC_CS0_BASE 0x60
#define GPMC_CS_SIZE 0x30
@@ -108,7 +108,7 @@ static struct platform_device omap3beagle_nand_device = {
#include "sdram-micron-mt46h32m32lf-6.h"
-static struct twl4030_hsmmc_info mmc[] = {
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 8,
@@ -147,7 +147,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
beagle_vmmc1_supply.dev = mmc[0].dev;
@@ -410,7 +410,7 @@ static void __init omap3beagle_flash_init(void)
}
}
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
@@ -430,6 +430,12 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -443,7 +449,7 @@ static void __init omap3_beagle_init(void)
/* REVISIT leave DVI powered down until it's needed ... */
gpio_direction_output(170, true);
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);
omap3beagle_flash_init();
@@ -455,7 +461,7 @@ static void __init omap3_beagle_init(void)
static void __init omap3_beagle_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 34de1785157..017bb2f4f7d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -41,10 +41,11 @@
#include <plat/usb.h>
#include <plat/common.h>
#include <plat/mcspi.h>
+#include <plat/display.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define OMAP3_EVM_TS_GPIO 175
#define OMAP3_EVM_EHCI_VBUS 22
@@ -147,6 +148,187 @@ static inline void __init omap3evm_init_smsc911x(void)
static inline void __init omap3evm_init_smsc911x(void) { return; }
#endif
+/*
+ * OMAP3EVM LCD Panel control signals
+ */
+#define OMAP3EVM_LCD_PANEL_LR 2
+#define OMAP3EVM_LCD_PANEL_UD 3
+#define OMAP3EVM_LCD_PANEL_INI 152
+#define OMAP3EVM_LCD_PANEL_ENVDD 153
+#define OMAP3EVM_LCD_PANEL_QVGA 154
+#define OMAP3EVM_LCD_PANEL_RESB 155
+#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
+#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
+
+static int lcd_enabled;
+static int dvi_enabled;
+
+static void __init omap3_evm_display_init(void)
+{
+ int r;
+
+ r = gpio_request(OMAP3EVM_LCD_PANEL_RESB, "lcd_panel_resb");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_resb\n");
+ return;
+ }
+ gpio_direction_output(OMAP3EVM_LCD_PANEL_RESB, 1);
+
+ r = gpio_request(OMAP3EVM_LCD_PANEL_INI, "lcd_panel_ini");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_ini\n");
+ goto err_1;
+ }
+ gpio_direction_output(OMAP3EVM_LCD_PANEL_INI, 1);
+
+ r = gpio_request(OMAP3EVM_LCD_PANEL_QVGA, "lcd_panel_qvga");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_qvga\n");
+ goto err_2;
+ }
+ gpio_direction_output(OMAP3EVM_LCD_PANEL_QVGA, 0);
+
+ r = gpio_request(OMAP3EVM_LCD_PANEL_LR, "lcd_panel_lr");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_lr\n");
+ goto err_3;
+ }
+ gpio_direction_output(OMAP3EVM_LCD_PANEL_LR, 1);
+
+ r = gpio_request(OMAP3EVM_LCD_PANEL_UD, "lcd_panel_ud");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_ud\n");
+ goto err_4;
+ }
+ gpio_direction_output(OMAP3EVM_LCD_PANEL_UD, 1);
+
+ r = gpio_request(OMAP3EVM_LCD_PANEL_ENVDD, "lcd_panel_envdd");
+ if (r) {
+ printk(KERN_ERR "failed to get lcd_panel_envdd\n");
+ goto err_5;
+ }
+ gpio_direction_output(OMAP3EVM_LCD_PANEL_ENVDD, 0);
+
+ return;
+
+err_5:
+ gpio_free(OMAP3EVM_LCD_PANEL_UD);
+err_4:
+ gpio_free(OMAP3EVM_LCD_PANEL_LR);
+err_3:
+ gpio_free(OMAP3EVM_LCD_PANEL_QVGA);
+err_2:
+ gpio_free(OMAP3EVM_LCD_PANEL_INI);
+err_1:
+ gpio_free(OMAP3EVM_LCD_PANEL_RESB);
+
+}
+
+static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
+{
+ if (dvi_enabled) {
+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
+ return -EINVAL;
+ }
+ gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
+
+ if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+ gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+ else
+ gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+
+ lcd_enabled = 1;
+ return 0;
+}
+
+static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
+{
+ gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
+
+ if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+ gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+ else
+ gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+
+ lcd_enabled = 0;
+}
+
+static struct omap_dss_device omap3_evm_lcd_device = {
+ .name = "lcd",
+ .driver_name = "sharp_ls_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 18,
+ .platform_enable = omap3_evm_enable_lcd,
+ .platform_disable = omap3_evm_disable_lcd,
+};
+
+static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
+{
+ return 0;
+}
+
+static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
+{
+}
+
+static struct omap_dss_device omap3_evm_tv_device = {
+ .name = "tv",
+ .driver_name = "venc",
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+ .platform_enable = omap3_evm_enable_tv,
+ .platform_disable = omap3_evm_disable_tv,
+};
+
+static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
+{
+ if (lcd_enabled) {
+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
+ return -EINVAL;
+ }
+
+ gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
+
+ dvi_enabled = 1;
+ return 0;
+}
+
+static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
+{
+ gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
+
+ dvi_enabled = 0;
+}
+
+static struct omap_dss_device omap3_evm_dvi_device = {
+ .name = "dvi",
+ .driver_name = "generic_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 24,
+ .platform_enable = omap3_evm_enable_dvi,
+ .platform_disable = omap3_evm_disable_dvi,
+};
+
+static struct omap_dss_device *omap3_evm_dss_devices[] = {
+ &omap3_evm_lcd_device,
+ &omap3_evm_tv_device,
+ &omap3_evm_dvi_device,
+};
+
+static struct omap_dss_board_info omap3_evm_dss_data = {
+ .num_devices = ARRAY_SIZE(omap3_evm_dss_devices),
+ .devices = omap3_evm_dss_devices,
+ .default_device = &omap3_evm_lcd_device,
+};
+
+static struct platform_device omap3_evm_dss_device = {
+ .name = "omapdss",
+ .id = -1,
+ .dev = {
+ .platform_data = &omap3_evm_dss_data,
+ },
+};
+
static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
.supply = "vmmc",
};
@@ -185,7 +367,7 @@ static struct regulator_init_data omap3evm_vsim = {
.consumer_supplies = &omap3evm_vsim_supply,
};
-static struct twl4030_hsmmc_info mmc[] = {
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 4,
@@ -225,7 +407,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
mmc[0].gpio_cd = gpio + 0;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
omap3evm_vmmc1_supply.dev = mmc[0].dev;
@@ -236,6 +418,14 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
* the P2 connector; notably LEDA for the LCD backlight.
*/
+ /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
+ gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+
+ /* gpio + 7 == DVI Enable */
+ gpio_request(gpio + 7, "EN_DVI");
+ gpio_direction_output(gpio + 7, 0);
+
/* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -258,20 +448,23 @@ static struct twl4030_usb_data omap3evm_usb_data = {
static int board_keymap[] = {
KEY(0, 0, KEY_LEFT),
- KEY(0, 1, KEY_RIGHT),
- KEY(0, 2, KEY_A),
- KEY(0, 3, KEY_B),
- KEY(1, 0, KEY_DOWN),
+ KEY(0, 1, KEY_DOWN),
+ KEY(0, 2, KEY_ENTER),
+ KEY(0, 3, KEY_M),
+
+ KEY(1, 0, KEY_RIGHT),
KEY(1, 1, KEY_UP),
- KEY(1, 2, KEY_E),
- KEY(1, 3, KEY_F),
- KEY(2, 0, KEY_ENTER),
- KEY(2, 1, KEY_I),
+ KEY(1, 2, KEY_I),
+ KEY(1, 3, KEY_N),
+
+ KEY(2, 0, KEY_A),
+ KEY(2, 1, KEY_E),
KEY(2, 2, KEY_J),
- KEY(2, 3, KEY_K),
- KEY(3, 0, KEY_M),
- KEY(3, 1, KEY_N),
- KEY(3, 2, KEY_O),
+ KEY(2, 3, KEY_O),
+
+ KEY(3, 0, KEY_B),
+ KEY(3, 1, KEY_F),
+ KEY(3, 2, KEY_K),
KEY(3, 3, KEY_P)
};
@@ -300,6 +493,47 @@ static struct twl4030_codec_data omap3evm_codec_data = {
.audio = &omap3evm_audio_data,
};
+static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
+ .supply = "vdda_dac",
+ .dev = &omap3_evm_dss_device.dev,
+};
+
+/* VDAC for DSS driving S-Video */
+static struct regulator_init_data omap3_evm_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &omap3_evm_vdda_dac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_consumer_supply omap3_evm_vpll2_supply = {
+ .supply = "vdvi",
+ .dev = &omap3_evm_lcd_device.dev,
+};
+
+static struct regulator_init_data omap3_evm_vpll2 = {
+ .constraints = {
+ .name = "VDVI",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &omap3_evm_vpll2_supply,
+};
+
static struct twl4030_platform_data omap3evm_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
@@ -310,6 +544,8 @@ static struct twl4030_platform_data omap3evm_twldata = {
.usb = &omap3evm_usb_data,
.gpio = &omap3evm_gpio_data,
.codec = &omap3evm_codec_data,
+ .vdac = &omap3_evm_vdac,
+ .vpll2 = &omap3_evm_vpll2,
};
static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
@@ -337,15 +573,6 @@ static int __init omap3_evm_i2c_init(void)
return 0;
}
-static struct platform_device omap3_evm_lcd_device = {
- .name = "omap3evm_lcd",
- .id = -1,
-};
-
-static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
- .ctrl_name = "internal",
-};
-
static void ads7846_dev_init(void)
{
if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0)
@@ -393,7 +620,6 @@ struct spi_board_info omap3evm_spi_board_info[] = {
};
static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
- { OMAP_TAG_LCD, &omap3_evm_lcd_config },
};
static void __init omap3_evm_init_irq(void)
@@ -406,10 +632,10 @@ static void __init omap3_evm_init_irq(void)
}
static struct platform_device *omap3_evm_devices[] __initdata = {
- &omap3_evm_lcd_device,
+ &omap3_evm_dss_device,
};
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
@@ -424,12 +650,24 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
+ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
+ OMAP_PIN_OFF_INPUT_PULLUP |
+ OMAP_PIN_OFF_WAKEUPENABLE),
+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+ OMAP_PIN_OFF_INPUT_PULLUP |
+ OMAP_PIN_OFF_WAKEUPENABLE),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
@@ -443,10 +681,10 @@ static void __init omap3_evm_init(void)
ARRAY_SIZE(omap3evm_spi_board_info));
omap_serial_init();
-#ifdef CONFIG_NOP_USB_XCEIV
+
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
usb_nop_xceiv_register();
-#endif
+
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
@@ -469,16 +707,17 @@ static void __init omap3_evm_init(void)
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
ehci_pdata.reset_gpio_port[1] = 135;
}
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);
ads7846_dev_init();
omap3evm_init_smsc911x();
+ omap3_evm_display_init();
}
static void __init omap3_evm_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index ef17cf1ab6d..395d049bf01 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,10 +40,11 @@
#include <mach/hardware.h>
#include <plat/mcspi.h>
#include <plat/usb.h>
+#include <plat/display.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define OMAP3_PANDORA_TS_GPIO 94
@@ -192,7 +193,41 @@ static struct twl4030_keypad_data pandora_kp_data = {
.rep = 1,
};
-static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
+static struct omap_dss_device pandora_lcd_device = {
+ .name = "lcd",
+ .driver_name = "tpo_td043mtea1_panel",
+ .type = OMAP_DISPLAY_TYPE_DPI,
+ .phy.dpi.data_lines = 24,
+ .reset_gpio = 157,
+};
+
+static struct omap_dss_device pandora_tv_device = {
+ .name = "tv",
+ .driver_name = "venc",
+ .type = OMAP_DISPLAY_TYPE_VENC,
+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
+};
+
+static struct omap_dss_device *pandora_dss_devices[] = {
+ &pandora_lcd_device,
+ &pandora_tv_device,
+};
+
+static struct omap_dss_board_info pandora_dss_data = {
+ .num_devices = ARRAY_SIZE(pandora_dss_devices),
+ .devices = pandora_dss_devices,
+ .default_device = &pandora_lcd_device,
+};
+
+static struct platform_device pandora_dss_device = {
+ .name = "omapdss",
+ .id = -1,
+ .dev = {
+ .platform_data = &pandora_dss_data,
+ },
+};
+
+static struct omap2_hsmmc_info omap3pandora_mmc[] = {
{
.mmc = 1,
.wires = 4,
@@ -217,25 +252,13 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
{} /* Terminator */
};
-static struct regulator_consumer_supply pandora_vmmc1_supply = {
- .supply = "vmmc",
-};
-
-static struct regulator_consumer_supply pandora_vmmc2_supply = {
- .supply = "vmmc",
-};
-
static int omap3pandora_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
omap3pandora_mmc[0].gpio_cd = gpio + 0;
omap3pandora_mmc[1].gpio_cd = gpio + 1;
- twl4030_mmc_init(omap3pandora_mmc);
-
- /* link regulators to MMC adapters */
- pandora_vmmc1_supply.dev = omap3pandora_mmc[0].dev;
- pandora_vmmc2_supply.dev = omap3pandora_mmc[1].dev;
+ omap2_hsmmc_init(omap3pandora_mmc);
return 0;
}
@@ -247,6 +270,36 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
.setup = omap3pandora_twl_gpio_setup,
};
+static struct regulator_consumer_supply pandora_vmmc1_supply =
+ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+
+static struct regulator_consumer_supply pandora_vmmc2_supply =
+ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+
+static struct regulator_consumer_supply pandora_vdda_dac_supply =
+ REGULATOR_SUPPLY("vdda_dac", "omapdss");
+
+static struct regulator_consumer_supply pandora_vdds_supplies[] = {
+ REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+};
+
+static struct regulator_consumer_supply pandora_vcc_lcd_supply =
+ REGULATOR_SUPPLY("vcc", "display0");
+
+static struct regulator_consumer_supply pandora_usb_phy_supply =
+ REGULATOR_SUPPLY("hsusb0", "ehci-omap.0");
+
+/* ads7846 on SPI and 2 nub controllers on I2C */
+static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+ REGULATOR_SUPPLY("vcc", "3-0066"),
+ REGULATOR_SUPPLY("vcc", "3-0067"),
+};
+
+static struct regulator_consumer_supply pandora_adac_supply =
+ REGULATOR_SUPPLY("vcc", "soc-audio");
+
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data pandora_vmmc1 = {
.constraints = {
@@ -277,6 +330,96 @@ static struct regulator_init_data pandora_vmmc2 = {
.consumer_supplies = &pandora_vmmc2_supply,
};
+/* VDAC for DSS driving S-Video */
+static struct regulator_init_data pandora_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &pandora_vdda_dac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data pandora_vpll2 = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies),
+ .consumer_supplies = pandora_vdds_supplies,
+};
+
+/* VAUX1 for LCD */
+static struct regulator_init_data pandora_vaux1 = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &pandora_vcc_lcd_supply,
+};
+
+/* VAUX2 for USB host PHY */
+static struct regulator_init_data pandora_vaux2 = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &pandora_usb_phy_supply,
+};
+
+/* VAUX4 for ads7846 and nubs */
+static struct regulator_init_data pandora_vaux4 = {
+ .constraints = {
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(pandora_vaux4_supplies),
+ .consumer_supplies = pandora_vaux4_supplies,
+};
+
+/* VSIM for audio DAC */
+static struct regulator_init_data pandora_vsim = {
+ .constraints = {
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &pandora_adac_supply,
+};
+
static struct twl4030_usb_data omap3pandora_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
@@ -298,6 +441,12 @@ static struct twl4030_platform_data omap3pandora_twldata = {
.codec = &omap3pandora_codec_data,
.vmmc1 = &pandora_vmmc1,
.vmmc2 = &pandora_vmmc2,
+ .vdac = &pandora_vdac,
+ .vpll2 = &pandora_vpll2,
+ .vaux1 = &pandora_vaux1,
+ .vaux2 = &pandora_vaux2,
+ .vaux4 = &pandora_vaux4,
+ .vsim = &pandora_vsim,
.keypad = &pandora_kp_data,
};
@@ -310,12 +459,20 @@ static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
},
};
+static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("bq27500", 0x55),
+ .flags = I2C_CLIENT_WAKE,
+ },
+};
+
static int __init omap3pandora_i2c_init(void)
{
omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
ARRAY_SIZE(omap3pandora_i2c_boardinfo));
/* i2c2 pins are not connected */
- omap_register_i2c_bus(3, 100, NULL, 0);
+ omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
+ ARRAY_SIZE(omap3pandora_i2c3_boardinfo));
return 0;
}
@@ -365,6 +522,12 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
.controller_data = &ads7846_mcspi_config,
.irq = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO),
.platform_data = &ads7846_config,
+ }, {
+ .modalias = "tpo_td043mtea1_panel_spi",
+ .bus_num = 1,
+ .chip_select = 1,
+ .max_speed_hz = 375000,
+ .platform_data = &pandora_lcd_device,
}
};
@@ -379,9 +542,10 @@ static void __init omap3pandora_init_irq(void)
static struct platform_device *omap3pandora_devices[] __initdata = {
&pandora_leds_gpio,
&pandora_keys_gpio,
+ &pandora_dss_device,
};
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -401,6 +565,12 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init omap3pandora_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -413,7 +583,7 @@ static void __init omap3pandora_init(void)
omap3pandora_ads7846_init();
usb_ehci_init(&ehci_pdata);
pandora_keys_gpio_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
@@ -423,7 +593,7 @@ static void __init omap3pandora_init(void)
static void __init omap3pandora_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index fe3d22cb245..2504d41f923 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -50,7 +50,7 @@
#include <plat/timer-gp.h>
#include "mux.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#include <asm/setup.h>
@@ -122,7 +122,7 @@ static struct platform_device omap3touchbook_nand_device = {
#include "sdram-micron-mt46h32m32lf-6.h"
-static struct twl4030_hsmmc_info mmc[] = {
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 8,
@@ -161,7 +161,7 @@ static int touchbook_twl_gpio_setup(struct device *dev,
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
touchbook_vmmc1_supply.dev = mmc[0].dev;
@@ -493,7 +493,7 @@ static void __init omap3touchbook_flash_init(void)
}
}
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
@@ -518,14 +518,20 @@ static void omap3_touchbook_poweroff(void)
gpio_direction_output(TB_KILL_POWER_GPIO, 0);
}
-static void __init early_touchbook_revision(char **p)
+static int __init early_touchbook_revision(char *p)
{
- if (!*p)
- return;
+ if (!p)
+ return 0;
- strict_strtoul(*p, 10, &touchbook_revision);
+ return strict_strtoul(p, 10, &touchbook_revision);
}
-__early_param("tbr=", early_touchbook_revision);
+early_param("tbr", early_touchbook_revision);
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
static void __init omap3_touchbook_init(void)
{
@@ -545,7 +551,7 @@ static void __init omap3_touchbook_init(void)
spi_register_board_info(omap3_ads7846_spi_board_info,
ARRAY_SIZE(omap3_ads7846_spi_board_info));
omap3_ads7846_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);
omap3touchbook_flash_init();
@@ -557,7 +563,7 @@ static void __init omap3_touchbook_init(void)
static void __init omap3_touchbook_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index d192dd98a59..8848c7c5ce4 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -48,7 +48,7 @@
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define OVERO_GPIO_BT_XGATE 15
#define OVERO_GPIO_W2W_NRESET 16
@@ -272,7 +272,7 @@ static void __init overo_flash_init(void)
}
}
-static struct twl4030_hsmmc_info mmc[] = {
+static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 4,
@@ -297,7 +297,7 @@ static struct regulator_consumer_supply overo_vmmc1_supply = {
static int overo_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
overo_vmmc1_supply.dev = mmc[0].dev;
@@ -394,7 +394,7 @@ static struct platform_device *overo_devices[] __initdata = {
&overo_lcd_device,
};
-static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -413,6 +413,12 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
static void __init overo_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -420,7 +426,7 @@ static void __init overo_init(void)
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
omap_serial_init();
overo_flash_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);
overo_ads7846_init();
overo_init_smsc911x();
@@ -469,7 +475,7 @@ static void __init overo_init(void)
static void __init overo_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OVERO, "Gumstix Overo")
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acafdbc8aa1..4377a4cf36e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -34,7 +34,7 @@
#include <plat/gpmc-smc91x.h>
#include "mux.h"
-#include "mmc-twl4030.h"
+#include "hsmmc.h"
#define SYSTEM_REV_B_USES_VAUX3 0x1699
#define SYSTEM_REV_S_USES_VAUX3 0x8
@@ -209,7 +209,47 @@ static struct twl4030_madc_platform_data rx51_madc_data = {
.irq_line = 1,
};
-static struct twl4030_hsmmc_info mmc[] = {
+/* Enable input logic and pull all lines up when eMMC is on. */
+static struct omap_board_mux rx51_mmc2_on_mux[] = {
+ OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/* Disable input logic and pull all lines down when eMMC is off. */
+static struct omap_board_mux rx51_mmc2_off_mux[] = {
+ OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Current flows to eMMC when eMMC is off and the data lines are pulled up,
+ * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
+ */
+static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
+{
+ if (power_on)
+ omap_mux_write_array(rx51_mmc2_on_mux);
+ else
+ omap_mux_write_array(rx51_mmc2_off_mux);
+}
+
+static struct omap2_hsmmc_info mmc[] __initdata = {
{
.name = "external",
.mmc = 1,
@@ -222,25 +262,29 @@ static struct twl4030_hsmmc_info mmc[] = {
{
.name = "internal",
.mmc = 2,
- .wires = 8,
+ .wires = 8, /* See also rx51_mmc2_remux */
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.nonremovable = true,
.power_saving = true,
+ .remux = rx51_mmc2_remux,
},
{} /* Terminator */
};
static struct regulator_consumer_supply rx51_vmmc1_supply = {
- .supply = "vmmc",
+ .supply = "vmmc",
+ .dev_name = "mmci-omap-hs.0",
};
static struct regulator_consumer_supply rx51_vmmc2_supply = {
- .supply = "vmmc",
+ .supply = "vmmc",
+ .dev_name = "mmci-omap-hs.1",
};
static struct regulator_consumer_supply rx51_vsim_supply = {
- .supply = "vmmc_aux",
+ .supply = "vmmc_aux",
+ .dev_name = "mmci-omap-hs.1",
};
static struct regulator_init_data rx51_vaux1 = {
@@ -375,12 +419,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
gpio_request(gpio + 7, "speaker_en");
gpio_direction_output(gpio + 7, 1);
- /* set up MMC adapters, linking their regulators to them */
- twl4030_mmc_init(mmc);
- rx51_vmmc1_supply.dev = mmc[0].dev;
- rx51_vmmc2_supply.dev = mmc[1].dev;
- rx51_vsim_supply.dev = mmc[1].dev;
-
return 0;
}
@@ -751,5 +789,6 @@ void __init rx51_peripherals_init(void)
rx51_init_wl1251();
spi_register_board_info(rx51_peripherals_spi_board_info,
ARRAY_SIZE(rx51_peripherals_spi_board_info));
+ omap2_hsmmc_init(mmc);
}
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 67bb3476b70..b155c366c65 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -16,6 +16,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
+#include <linux/leds.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@@ -30,9 +31,49 @@
#include <plat/usb.h>
#include "mux.h"
+#include "pm.h"
+
+#define RX51_GPIO_SLEEP_IND 162
struct omap_sdrc_params *rx51_get_sdram_timings(void);
+static struct gpio_led gpio_leds[] = {
+ {
+ .name = "sleep_ind",
+ .gpio = RX51_GPIO_SLEEP_IND,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
+static struct cpuidle_params rx51_cpuidle_params[] = {
+ /* C1 */
+ {1, 110, 162, 5},
+ /* C2 */
+ {1, 106, 180, 309},
+ /* C3 */
+ {0, 107, 410, 46057},
+ /* C4 */
+ {0, 121, 3374, 46057},
+ /* C5 */
+ {1, 855, 1146, 46057},
+ /* C6 */
+ {0, 7580, 4134, 484329},
+ /* C7 */
+ {1, 7505, 15274, 484329},
+};
+
static struct omap_lcd_config rx51_lcd_config = {
.ctrl_name = "internal",
};
@@ -62,6 +103,7 @@ static void __init rx51_init_irq(void)
omap_board_config = rx51_config;
omap_board_config_size = ARRAY_SIZE(rx51_config);
+ omap3_pm_init_cpuidle(rx51_cpuidle_params);
sdrc_params = rx51_get_sdram_timings();
omap2_init_common_hw(sdrc_params, sdrc_params);
omap_init_irq();
@@ -78,22 +120,30 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_PERIPHERAL,
+ .power = 0,
+};
+
static void __init rx51_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
rx51_peripherals_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+
+ platform_device_register(&leds_gpio);
}
static void __init rx51_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-sdp-flash.c
new file mode 100644
index 00000000000..2d026328e38
--- /dev/null
+++ b/arch/arm/mach-omap2/board-sdp-flash.c
@@ -0,0 +1,272 @@
+/*
+ * board-sdp-flash.c
+ * Modified from mach-omap2/board-3430sdp-flash.c
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Vimal Singh <vimalsingh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/io.h>
+
+#include <plat/gpmc.h>
+#include <plat/nand.h>
+#include <plat/onenand.h>
+#include <plat/tc.h>
+#include <mach/board-sdp.h>
+
+#define REG_FPGA_REV 0x10
+#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
+#define MAX_SUPPORTED_GPMC_CONFIG 3
+
+#define DEBUG_BASE 0x08000000 /* debug board */
+
+#define PDC_NOR 1
+#define PDC_NAND 2
+#define PDC_ONENAND 3
+#define DBG_MPDB 4
+
+/* various memory sizes */
+#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
+#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
+
+/*
+ * SDP3430 V2 Board CS organization
+ * Different from SDP3430 V1. Now 4 switches used to specify CS
+ *
+ * See also the Switch S8 settings in the comments.
+ *
+ * REVISIT: Add support for 2430 SDP
+ */
+static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = {
+ {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
+ {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
+ {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
+};
+
+static struct physmap_flash_data sdp_nor_data = {
+ .width = 2,
+};
+
+static struct resource sdp_nor_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device sdp_nor_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &sdp_nor_data,
+ },
+ .num_resources = 1,
+ .resource = &sdp_nor_resource,
+};
+
+static void
+__init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs)
+{
+ int err;
+
+ sdp_nor_data.parts = sdp_nor_parts.parts;
+ sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts;
+
+ /* Configure start address and size of NOR device */
+ if (omap_rev() >= OMAP3430_REV_ES1_0) {
+ err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
+ (unsigned long *)&sdp_nor_resource.start);
+ sdp_nor_resource.end = sdp_nor_resource.start
+ + FLASH_SIZE_SDPV2 - 1;
+ } else {
+ err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
+ (unsigned long *)&sdp_nor_resource.start);
+ sdp_nor_resource.end = sdp_nor_resource.start
+ + FLASH_SIZE_SDPV1 - 1;
+ }
+ if (err < 0) {
+ printk(KERN_ERR "NOR: Can't request GPMC CS\n");
+ return;
+ }
+ if (platform_device_register(&sdp_nor_device) < 0)
+ printk(KERN_ERR "Unable to register NOR device\n");
+}
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+static struct omap_onenand_platform_data board_onenand_data = {
+ .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
+};
+
+static void
+__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
+{
+ board_onenand_data.cs = cs;
+ board_onenand_data.parts = sdp_onenand_parts.parts;
+ board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts;
+
+ gpmc_onenand_init(&board_onenand_data);
+}
+#else
+static void
+__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
+{
+}
+#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+ defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+
+/* Note that all values in this struct are in nanoseconds */
+static struct gpmc_timings nand_timings = {
+
+ .sync_clk = 0,
+
+ .cs_on = 0,
+ .cs_rd_off = 36,
+ .cs_wr_off = 36,
+
+ .adv_on = 6,
+ .adv_rd_off = 24,
+ .adv_wr_off = 36,
+
+ .we_off = 30,
+ .oe_off = 48,
+
+ .access = 54,
+ .rd_cycle = 72,
+ .wr_cycle = 72,
+
+ .wr_access = 30,
+ .wr_data_mux_bus = 0,
+};
+
+static struct omap_nand_platform_data sdp_nand_data = {
+ .nand_setup = NULL,
+ .gpmc_t = &nand_timings,
+ .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+ .dev_ready = NULL,
+ .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
+};
+
+static void
+__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
+{
+ sdp_nand_data.cs = cs;
+ sdp_nand_data.parts = sdp_nand_parts.parts;
+ sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts;
+
+ sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT +
+ GPMC_CS0_BASE +
+ cs * GPMC_CS_SIZE);
+ sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT);
+
+ gpmc_nand_init(&sdp_nand_data);
+}
+#else
+static void
+__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
+{
+}
+#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
+
+/**
+ * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
+ * the various cs values.
+ */
+static u8 get_gpmc0_type(void)
+{
+ u8 cs = 0;
+ void __iomem *fpga_map_addr;
+
+ fpga_map_addr = ioremap(DEBUG_BASE, 4096);
+ if (!fpga_map_addr)
+ return -ENOMEM;
+
+ if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
+ /* we dont have an DEBUG FPGA??? */
+ /* Depend on #defines!! default to strata boot return param */
+ goto unmap;
+
+ /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
+ cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
+
+ /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
+ if (omap_rev() >= OMAP3430_REV_ES1_0)
+ /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
+ cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
+ ((cs & 2) << 1) | ((cs & 1) << 3);
+ else
+ /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
+ cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
+unmap:
+ iounmap(fpga_map_addr);
+ return cs;
+}
+
+/**
+ * sdp3430_flash_init - Identify devices connected to GPMC and register.
+ *
+ * @return - void.
+ */
+void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
+{
+ u8 cs = 0;
+ u8 norcs = GPMC_CS_NUM + 1;
+ u8 nandcs = GPMC_CS_NUM + 1;
+ u8 onenandcs = GPMC_CS_NUM + 1;
+ u8 idx;
+ unsigned char *config_sel = NULL;
+
+ /* REVISIT: Is this return correct idx for 2430 SDP?
+ * for which cs configuration matches for 2430 SDP?
+ */
+ idx = get_gpmc0_type();
+ if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
+ printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
+ return;
+ }
+ config_sel = (unsigned char *)(chip_sel_sdp[idx]);
+
+ while (cs < GPMC_CS_NUM) {
+ switch (config_sel[cs]) {
+ case PDC_NOR:
+ if (norcs > GPMC_CS_NUM)
+ norcs = cs;
+ break;
+ case PDC_NAND:
+ if (nandcs > GPMC_CS_NUM)
+ nandcs = cs;
+ break;
+ case PDC_ONENAND:
+ if (onenandcs > GPMC_CS_NUM)
+ onenandcs = cs;
+ break;
+ };
+ cs++;
+ }
+
+ if (norcs > GPMC_CS_NUM)
+ printk(KERN_INFO "NOR: Unable to find configuration "
+ "in GPMC\n");
+ else
+ board_nor_init(sdp_partition_info[0], norcs);
+
+ if (onenandcs > GPMC_CS_NUM)
+ printk(KERN_INFO "OneNAND: Unable to find configuration "
+ "in GPMC\n");
+ else
+ board_onenand_init(sdp_partition_info[1], onenandcs);
+
+ if (nandcs > GPMC_CS_NUM)
+ printk(KERN_INFO "NAND: Unable to find configuration "
+ "in GPMC\n");
+ else
+ board_nand_init(sdp_partition_info[2], nandcs);
+}
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index bb4018b6064..e15d2e87cfc 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -96,7 +96,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
static struct platform_device zoom_debugboard_serial_device = {
.name = "serial8250",
- .id = 3,
+ .id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 8dd277c3666..6b3984964cc 100755..100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -24,7 +24,8 @@
#include <plat/common.h>
#include <plat/usb.h>
-#include "mmc-twl4030.h"
+#include "mux.h"
+#include "hsmmc.h"
/* Zoom2 has Qwerty keyboard*/
static int board_keymap[] = {
@@ -63,21 +64,21 @@ static int board_keymap[] = {
KEY(5, 1, KEY_H),
KEY(5, 2, KEY_J),
KEY(5, 3, KEY_F3),
+ KEY(5, 4, KEY_UNKNOWN),
KEY(5, 5, KEY_VOLUMEDOWN),
KEY(5, 6, KEY_M),
- KEY(5, 7, KEY_ENTER),
+ KEY(5, 7, KEY_RIGHT),
KEY(6, 0, KEY_Q),
KEY(6, 1, KEY_A),
KEY(6, 2, KEY_N),
KEY(6, 3, KEY_BACKSPACE),
KEY(6, 6, KEY_P),
- KEY(6, 7, KEY_SELECT),
+ KEY(6, 7, KEY_UP),
KEY(7, 0, KEY_PROG1), /*MACRO 1 <User defined> */
KEY(7, 1, KEY_PROG2), /*MACRO 2 <User defined> */
KEY(7, 2, KEY_PROG3), /*MACRO 3 <User defined> */
KEY(7, 3, KEY_PROG4), /*MACRO 4 <User defined> */
- KEY(7, 5, KEY_RIGHT),
- KEY(7, 6, KEY_UP),
+ KEY(7, 6, KEY_SELECT),
KEY(7, 7, KEY_DOWN)
};
@@ -150,7 +151,7 @@ static struct regulator_init_data zoom_vsim = {
.consumer_supplies = &zoom_vsim_supply,
};
-static struct twl4030_hsmmc_info mmc[] __initdata = {
+static struct omap2_hsmmc_info mmc[] __initdata = {
{
.name = "external",
.mmc = 1,
@@ -175,7 +176,7 @@ static int zoom_twl_gpio_setup(struct device *dev,
{
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
- twl4030_mmc_init(mmc);
+ omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
* regulators will be set up only *after* we return.
@@ -263,9 +264,22 @@ static int __init omap_i2c_init(void)
return 0;
}
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 100,
+};
+
+static void enable_board_wakeup_source(void)
+{
+ /* T2 interrupt line (keypad) */
+ omap_mux_init_signal("sys_nirq",
+ OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
+}
+
void __init zoom_peripherals_init(void)
{
omap_i2c_init();
- omap_serial_init();
- usb_musb_init();
+ usb_musb_init(&musb_board_data);
+ enable_board_wakeup_source();
}
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index bb87cf7878f..9a26f84b114 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -87,7 +87,7 @@ static void __init omap_zoom2_init(void)
static void __init omap_zoom2_map_io(void)
{
omap2_set_globals_343x();
- omap2_map_common_io();
+ omap34xx_map_common_io();
}
MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index a9fe9181b01..cd3e40cf3ac 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -20,14 +20,15 @@
#include <plat/common.h>
#include <plat/board.h>
+#include <plat/usb.h>
#include "mux.h"
#include "sdram-hynix-h8mbx00u0mer-0em.h"
static void __init omap_zoom_map_io(void)
{
- omap2_set_globals_343x();
- omap2_map_common_io();
+ omap2_set_globals_36xx();
+ omap34xx_map_common_io();
}
static struct omap_board_config_kernel zoom_config[] __initdata = {
@@ -51,11 +52,24 @@ static struct omap_board_mux board_mux[] __initdata = {
#define board_mux NULL
#endif
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+ .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+ .phy_reset = true,
+ .reset_gpio_port[0] = -EINVAL,
+ .reset_gpio_port[1] = 64,
+ .reset_gpio_port[2] = -EINVAL,
+};
+
static void __init omap_zoom_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
zoom_peripherals_init();
zoom_debugboard_init();
+
+ omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
+ usb_ehci_init(&ehci_pdata);
}
MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
new file mode 100644
index 00000000000..43d7246ce33
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -0,0 +1,122 @@
+/*
+ * OMAP2xxx APLL clock control functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/prcm.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED 0
+#define EN_APLL_LOCKED 3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ 0
+#define APLLS_CLKIN_13MHZ 2
+#define APLLS_CLKIN_12MHZ 3
+
+void __iomem *cm_idlest_pll;
+
+/* Private functions */
+
+/* Enable an APLL if off */
+static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
+{
+ u32 cval, apll_mask;
+
+ apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+ cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+ if ((cval & apll_mask) == apll_mask)
+ return 0; /* apll already enabled */
+
+ cval &= ~apll_mask;
+ cval |= apll_mask;
+ cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+ omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
+ OMAP24XX_CM_IDLEST_VAL, clk->name);
+
+ /*
+ * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+ * fails?
+ */
+ return 0;
+}
+
+static int omap2_clk_apll96_enable(struct clk *clk)
+{
+ return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
+}
+
+static int omap2_clk_apll54_enable(struct clk *clk)
+{
+ return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
+}
+
+/* Stop APLL */
+static void omap2_clk_apll_disable(struct clk *clk)
+{
+ u32 cval;
+
+ cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+ cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+ cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+/* Public data */
+
+const struct clkops clkops_apll96 = {
+ .enable = omap2_clk_apll96_enable,
+ .disable = omap2_clk_apll_disable,
+};
+
+const struct clkops clkops_apll54 = {
+ .enable = omap2_clk_apll54_enable,
+ .disable = omap2_clk_apll_disable,
+};
+
+/* Public functions */
+
+u32 omap2xxx_get_apll_clkin(void)
+{
+ u32 aplls, srate = 0;
+
+ aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+ aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+ aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+ if (aplls == APLLS_CLKIN_19_2MHZ)
+ srate = 19200000;
+ else if (aplls == APLLS_CLKIN_13MHZ)
+ srate = 13000000;
+ else if (aplls == APLLS_CLKIN_12MHZ)
+ srate = 12000000;
+
+ return srate;
+}
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
new file mode 100644
index 00000000000..019048434f1
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -0,0 +1,173 @@
+/*
+ * DPLL + CORE_CLK composite clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX The DPLL and CORE clocks should be split into two separate clock
+ * types.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
+
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual). This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
+{
+ long long core_clk;
+ u32 v;
+
+ core_clk = omap2_get_dpll_rate(clk);
+
+ v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+ if (v == CORE_CLK_SRC_32K)
+ core_clk = 32768;
+ else
+ core_clk *= v;
+
+ return core_clk;
+}
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+static long omap2_dpllcore_round_rate(unsigned long target_rate)
+{
+ u32 high, low, core_clk_src;
+
+ core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+ if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
+ high = curr_prcm_set->dpll_speed * 2;
+ low = curr_prcm_set->dpll_speed;
+ } else { /* DPLL clockout x 2 */
+ high = curr_prcm_set->dpll_speed;
+ low = curr_prcm_set->dpll_speed / 2;
+ }
+
+#ifdef DOWN_VARIABLE_DPLL
+ if (target_rate > high)
+ return high;
+ else
+ return target_rate;
+#else
+ if (target_rate > low)
+ return high;
+ else
+ return low;
+#endif
+
+}
+
+unsigned long omap2_dpllcore_recalc(struct clk *clk)
+{
+ return omap2xxx_clk_get_core_rate(clk);
+}
+
+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
+{
+ u32 cur_rate, low, mult, div, valid_rate, done_rate;
+ u32 bypass = 0;
+ struct prcm_config tmpset;
+ const struct dpll_data *dd;
+
+ cur_rate = omap2xxx_clk_get_core_rate(dclk);
+ mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+ if ((rate == (cur_rate / 2)) && (mult == 2)) {
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+ } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+ } else if (rate != cur_rate) {
+ valid_rate = omap2_dpllcore_round_rate(rate);
+ if (valid_rate != rate)
+ return -EINVAL;
+
+ if (mult == 1)
+ low = curr_prcm_set->dpll_speed;
+ else
+ low = curr_prcm_set->dpll_speed / 2;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ return -EINVAL;
+
+ tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+ tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+ dd->div1_mask);
+ div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+ tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+ if (rate > low) {
+ tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+ mult = ((rate / 2) / 1000000);
+ done_rate = CORE_CLK_SRC_DPLL_X2;
+ } else {
+ tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+ mult = (rate / 1000000);
+ done_rate = CORE_CLK_SRC_DPLL;
+ }
+ tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+ tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+ /* Worst case */
+ tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+ if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
+ bypass = 1;
+
+ /* For omap2xxx_sdrc_init_params() */
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+ /* Force dll lock mode */
+ omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+ bypass);
+
+ /* Errata: ret dll entry state */
+ omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+ omap2xxx_sdrc_reprogram(done_rate, 0);
+ }
+
+ return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
new file mode 100644
index 00000000000..2167be84a5b
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -0,0 +1,62 @@
+/*
+ * OMAP2xxx osc_clk-specific clock code
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+ u32 pcc;
+
+ pcc = __raw_readl(prcm_clksrc_ctrl);
+
+ __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+
+ return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+ u32 pcc;
+
+ pcc = __raw_readl(prcm_clksrc_ctrl);
+
+ __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+}
+
+const struct clkops clkops_oscck = {
+ .enable = omap2_enable_osc_ck,
+ .disable = omap2_disable_osc_ck,
+};
+
+unsigned long omap2_osc_clk_recalc(struct clk *clk)
+{
+ return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
+}
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
new file mode 100644
index 00000000000..822b5a79f45
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -0,0 +1,50 @@
+/*
+ * OMAP2xxx sys_clk-specific clock code
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+
+void __iomem *prcm_clksrc_ctrl;
+
+u32 omap2xxx_get_sysclkdiv(void)
+{
+ u32 div;
+
+ div = __raw_readl(prcm_clksrc_ctrl);
+ div &= OMAP_SYSCLKDIV_MASK;
+ div >>= OMAP_SYSCLKDIV_SHIFT;
+
+ return div;
+}
+
+unsigned long omap2xxx_sys_clk_recalc(struct clk *clk)
+{
+ return clk->parent->rate / omap2xxx_get_sysclkdiv();
+}
+
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
new file mode 100644
index 00000000000..e60ca4e47bb
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -0,0 +1,255 @@
+/*
+ * OMAP2xxx DVFS virtual clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of this code should be replaceable by the upcoming OPP layer
+ * code. However, some notion of "rate set" is probably still necessary
+ * for OMAP2xxx at least. Rate sets should be generalized so they can be
+ * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
+ * has in the past expressed a preference to use rate sets for OPP changes,
+ * rather than dynamically recalculating the clock tree, so if someone wants
+ * this badly enough to write the code to handle it, we should support it
+ * as an option.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+#include <linux/slab.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+const struct prcm_config *curr_prcm_set;
+const struct prcm_config *rate_table;
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+unsigned long omap2_table_mpu_recalc(struct clk *clk)
+{
+ return curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+ const struct prcm_config *ptr;
+ long highest_rate;
+ long sys_ck_rate;
+
+ sys_ck_rate = clk_get_rate(sclk);
+
+ highest_rate = -EINVAL;
+
+ for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+ if (!(ptr->flags & cpu_mask))
+ continue;
+ if (ptr->xtal_speed != sys_ck_rate)
+ continue;
+
+ highest_rate = ptr->mpu_speed;
+
+ /* Can check only after xtal frequency check */
+ if (ptr->mpu_speed <= rate)
+ break;
+ }
+ return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+ u32 cur_rate, done_rate, bypass = 0, tmp;
+ const struct prcm_config *prcm;
+ unsigned long found_speed = 0;
+ unsigned long flags;
+ long sys_ck_rate;
+
+ sys_ck_rate = clk_get_rate(sclk);
+
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+
+ if (prcm->xtal_speed != sys_ck_rate)
+ continue;
+
+ if (prcm->mpu_speed <= rate) {
+ found_speed = prcm->mpu_speed;
+ break;
+ }
+ }
+
+ if (!found_speed) {
+ printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+ rate / 1000000);
+ return -EINVAL;
+ }
+
+ curr_prcm_set = prcm;
+ cur_rate = omap2xxx_clk_get_core_rate(dclk);
+
+ if (prcm->dpll_speed == cur_rate / 2) {
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+ } else if (prcm->dpll_speed == cur_rate * 2) {
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+ } else if (prcm->dpll_speed != cur_rate) {
+ local_irq_save(flags);
+
+ if (prcm->dpll_speed == prcm->xtal_speed)
+ bypass = 1;
+
+ if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+ CORE_CLK_SRC_DPLL_X2)
+ done_rate = CORE_CLK_SRC_DPLL_X2;
+ else
+ done_rate = CORE_CLK_SRC_DPLL;
+
+ /* MPU divider */
+ cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+ /* dsp + iva1 div(2420), iva2.1(2430) */
+ cm_write_mod_reg(prcm->cm_clksel_dsp,
+ OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+ cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+ /* Major subsystem dividers */
+ tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+ cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+ CM_CLKSEL1);
+
+ if (cpu_is_omap2430())
+ cm_write_mod_reg(prcm->cm_clksel_mdm,
+ OMAP2430_MDM_MOD, CM_CLKSEL);
+
+ /* x2 to enter omap2xxx_sdrc_init_params() */
+ omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+ omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+ bypass);
+
+ omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+ omap2xxx_sdrc_reprogram(done_rate, 0);
+
+ local_irq_restore(flags);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ * XXX This should be replaced by an OPP layer in the near future
+ */
+static struct cpufreq_frequency_table *freq_table;
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+ const struct prcm_config *prcm;
+ long sys_ck_rate;
+ int i = 0;
+ int tbl_sz = 0;
+
+ if (!cpu_is_omap24xx())
+ return;
+
+ sys_ck_rate = clk_get_rate(sclk);
+
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck_rate)
+ continue;
+
+ /* don't put bypass rates in table */
+ if (prcm->dpll_speed == prcm->xtal_speed)
+ continue;
+
+ tbl_sz++;
+ }
+
+ /*
+ * XXX Ensure that we're doing what CPUFreq expects for this error
+ * case and the following one
+ */
+ if (tbl_sz == 0) {
+ pr_warning("%s: no matching entries in rate_table\n",
+ __func__);
+ return;
+ }
+
+ /* Include the CPUFREQ_TABLE_END terminator entry */
+ tbl_sz++;
+
+ freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
+ GFP_ATOMIC);
+ if (!freq_table) {
+ pr_err("%s: could not kzalloc frequency table\n", __func__);
+ return;
+ }
+
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck_rate)
+ continue;
+
+ /* don't put bypass rates in table */
+ if (prcm->dpll_speed == prcm->xtal_speed)
+ continue;
+
+ freq_table[i].index = i;
+ freq_table[i].frequency = prcm->mpu_speed / 1000;
+ i++;
+ }
+
+ freq_table[i].index = i;
+ freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+ *table = &freq_table[0];
+}
+
+void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+ if (!cpu_is_omap24xx())
+ return;
+
+ kfree(freq_table);
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
new file mode 100644
index 00000000000..b2b1e37bb6b
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -0,0 +1,121 @@
+/*
+ * OMAP34xx M2 divider clock code
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Jouni Högander
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock3xxx.h"
+#include "clock34xx.h"
+#include "sdrc.h"
+
+#define CYCLES_PER_MHZ 1000000
+
+/*
+ * CORE DPLL (DPLL3) M2 divider rate programming functions
+ *
+ * These call into SRAM code to do the actual CM writes, since the SDRAM
+ * is clocked from DPLL3.
+ */
+
+/**
+ * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Program the DPLL M2 divider with the rounded target rate. Returns
+ * -EINVAL upon error, or 0 upon success.
+ */
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 new_div = 0;
+ u32 unlock_dll = 0;
+ u32 c;
+ unsigned long validrate, sdrcrate, _mpurate;
+ struct omap_sdrc_params *sdrc_cs0;
+ struct omap_sdrc_params *sdrc_cs1;
+ int ret;
+
+ if (!clk || !rate)
+ return -EINVAL;
+
+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ if (validrate != rate)
+ return -EINVAL;
+
+ sdrcrate = sdrc_ick_p->rate;
+ if (rate > clk->rate)
+ sdrcrate <<= ((rate / clk->rate) >> 1);
+ else
+ sdrcrate >>= ((clk->rate / rate) >> 1);
+
+ ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+ if (ret)
+ return -EINVAL;
+
+ if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
+ pr_debug("clock: will unlock SDRC DLL\n");
+ unlock_dll = 1;
+ }
+
+ /*
+ * XXX This only needs to be done when the CPU frequency changes
+ */
+ _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+ c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+ c += 1; /* for safety */
+ c *= SDRC_MPURATE_LOOPS;
+ c >>= SDRC_MPURATE_SCALE;
+ if (c == 0)
+ c = 1;
+
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ validrate);
+ pr_debug("clock: SDRC CS0 timing params used:"
+ " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+ sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+ if (sdrc_cs1)
+ pr_debug("clock: SDRC CS1 timing params used: "
+ " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+ sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+ if (sdrc_cs1)
+ omap3_configure_core_dpll(
+ new_div, unlock_dll, c, rate > clk->rate,
+ sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+ sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+ sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+ sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+ else
+ omap3_configure_core_dpll(
+ new_div, unlock_dll, c, rate > clk->rate,
+ sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+ sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+ 0, 0, 0, 0);
+
+ return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
new file mode 100644
index 00000000000..e50812dd03f
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -0,0 +1,409 @@
+/*
+ * clkt_clksel.c - OMAP2/3/4 clksel clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX At some point these clksel clocks should be split into
+ * "divider" clocks and "mux" clocks to better match the hardware.
+ *
+ * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
+ * many of the OMAP1 clocks should be convertible to use this
+ * mechanism.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+/* Private functions */
+
+/**
+ * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * @clk: OMAP struct clk ptr to inspect
+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ *
+ * Scan the struct clksel array associated with the clock to find
+ * the element associated with the supplied parent clock address.
+ * Returns a pointer to the struct clksel on success or NULL on error.
+ */
+static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
+ struct clk *src_clk)
+{
+ const struct clksel *clks;
+
+ if (!clk->clksel)
+ return NULL;
+
+ for (clks = clk->clksel; clks->parent; clks++) {
+ if (clks->parent == src_clk)
+ break; /* Found the requested parent */
+ }
+
+ if (!clks->parent) {
+ printk(KERN_ERR "clock: Could not find parent clock %s in "
+ "clksel array of clock %s\n", src_clk->name,
+ clk->name);
+ return NULL;
+ }
+
+ return clks;
+}
+
+/*
+ * Converts encoded control register address into a full address
+ * On error, the return value (parent_div) will be 0.
+ */
+static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
+ u32 *field_val)
+{
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+
+ clks = _omap2_get_clksel_by_parent(clk, src_clk);
+ if (!clks)
+ return 0;
+
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
+ break; /* Found the default rate for this platform */
+ }
+
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find default rate for "
+ "clock %s parent %s\n", clk->name,
+ src_clk->parent->name);
+ return 0;
+ }
+
+ /* Should never happen. Add a clksel mask to the struct clk. */
+ WARN_ON(clk->clksel_mask == 0);
+
+ *field_val = clkr->val;
+
+ return clkr->div;
+}
+
+
+/* Public functions */
+
+/**
+ * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Given a pointer to a source-selectable struct clk, read the hardware
+ * register and determine what its parent is currently set to. Update the
+ * clk->parent field with the appropriate clk ptr.
+ */
+void omap2_init_clksel_parent(struct clk *clk)
+{
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+ u32 r, found = 0;
+
+ if (!clk->clksel)
+ return;
+
+ r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ r >>= __ffs(clk->clksel_mask);
+
+ for (clks = clk->clksel; clks->parent && !found; clks++) {
+ for (clkr = clks->rates; clkr->div && !found; clkr++) {
+ if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
+ if (clk->parent != clks->parent) {
+ pr_debug("clock: inited %s parent "
+ "to %s (was %s)\n",
+ clk->name, clks->parent->name,
+ ((clk->parent) ?
+ clk->parent->name : "NULL"));
+ clk_reparent(clk, clks->parent);
+ };
+ found = 1;
+ }
+ }
+ }
+
+ if (!found)
+ printk(KERN_ERR "clock: init parent: could not find "
+ "regval %0x for clock %s\n", r, clk->name);
+
+ return;
+}
+
+/*
+ * Used for clocks that are part of CLKSEL_xyz governed clocks.
+ * REVISIT: Maybe change to use clk->enable() functions like on omap1?
+ */
+unsigned long omap2_clksel_recalc(struct clk *clk)
+{
+ unsigned long rate;
+ u32 div = 0;
+
+ pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
+
+ div = omap2_clksel_get_divisor(clk);
+ if (div == 0)
+ return clk->rate;
+
+ rate = clk->parent->rate / div;
+
+ pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
+
+ return rate;
+}
+
+/**
+ * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ * @new_div: ptr to where we should store the divisor
+ *
+ * Finds 'best' divider value in an array based on the source and target
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+ u32 *new_div)
+{
+ unsigned long test_rate;
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+ u32 last_div = 0;
+
+ pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
+ clk->name, target_rate);
+
+ *new_div = 1;
+
+ clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+ if (!clks)
+ return ~0;
+
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if (!(clkr->flags & cpu_mask))
+ continue;
+
+ /* Sanity check */
+ if (clkr->div <= last_div)
+ pr_err("clock: clksel_rate table not sorted "
+ "for clock %s", clk->name);
+
+ last_div = clkr->div;
+
+ test_rate = clk->parent->rate / clkr->div;
+
+ if (test_rate <= target_rate)
+ break; /* found it */
+ }
+
+ if (!clkr->div) {
+ pr_err("clock: Could not find divisor for target "
+ "rate %ld for clock %s parent %s\n", target_rate,
+ clk->name, clk->parent->name);
+ return ~0;
+ }
+
+ *new_div = clkr->div;
+
+ pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
+ (clk->parent->rate / clkr->div));
+
+ return clk->parent->rate / clkr->div;
+}
+
+/**
+ * omap2_clksel_round_rate - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * Compatibility wrapper for OMAP clock framework
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
+{
+ u32 new_div;
+
+ return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+}
+
+
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ if (clk->round_rate)
+ return clk->round_rate(clk, rate);
+
+ return clk->rate;
+}
+
+/**
+ * omap2_clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor. The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling. Returns 0 on error
+ */
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
+{
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+
+ clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+ if (!clks)
+ return 0;
+
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
+ break;
+ }
+
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find fieldval %d for "
+ "clock %s parent %s\n", field_val, clk->name,
+ clk->parent->name);
+ return 0;
+ }
+
+ return clkr->div;
+}
+
+/**
+ * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
+ * find the corresponding register field value. The return register value is
+ * the value before left-shifting. Returns ~0 on error
+ */
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
+{
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+
+ /* should never happen */
+ WARN_ON(div == 0);
+
+ clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+ if (!clks)
+ return ~0;
+
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if ((clkr->flags & cpu_mask) && (clkr->div == div))
+ break;
+ }
+
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find divisor %d for "
+ "clock %s parent %s\n", div, clk->name,
+ clk->parent->name);
+ return ~0;
+ }
+
+ return clkr->val;
+}
+
+/**
+ * omap2_clksel_get_divisor - get current divider applied to parent clock.
+ * @clk: OMAP struct clk to use.
+ *
+ * Returns the integer divisor upon success or 0 on error.
+ */
+u32 omap2_clksel_get_divisor(struct clk *clk)
+{
+ u32 v;
+
+ if (!clk->clksel_mask)
+ return 0;
+
+ v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ v >>= __ffs(clk->clksel_mask);
+
+ return omap2_clksel_to_divisor(clk, v);
+}
+
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 v, field_val, validrate, new_div = 0;
+
+ if (!clk->clksel_mask)
+ return -EINVAL;
+
+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ if (validrate != rate)
+ return -EINVAL;
+
+ field_val = omap2_divisor_to_clksel(clk, new_div);
+ if (field_val == ~0)
+ return -EINVAL;
+
+ v = __raw_readl(clk->clksel_reg);
+ v &= ~clk->clksel_mask;
+ v |= field_val << __ffs(clk->clksel_mask);
+ __raw_writel(v, clk->clksel_reg);
+ v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+
+ clk->rate = clk->parent->rate / new_div;
+
+ return 0;
+}
+
+int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
+{
+ u32 field_val, v, parent_div;
+
+ if (!clk->clksel)
+ return -EINVAL;
+
+ parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
+ if (!parent_div)
+ return -EINVAL;
+
+ /* Set new source value (previous dividers if any in effect) */
+ v = __raw_readl(clk->clksel_reg);
+ v &= ~clk->clksel_mask;
+ v |= field_val << __ffs(clk->clksel_mask);
+ __raw_writel(v, clk->clksel_reg);
+ v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+
+ clk_reparent(clk, new_parent);
+
+ /* CLKSEL clocks follow their parents' rates, divided by a divisor */
+ clk->rate = new_parent->rate;
+
+ if (parent_div > 0)
+ clk->rate /= parent_div;
+
+ pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+ clk->name, clk->parent->name, clk->rate);
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
new file mode 100644
index 00000000000..6ce512e902c
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -0,0 +1,386 @@
+/*
+ * OMAP2/3/4 DPLL clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/div64.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+/* DPLL rate rounding: minimum DPLL multiplier, divider values */
+#define DPLL_MIN_MULTIPLIER 2
+#define DPLL_MIN_DIVIDER 1
+
+/* Possible error results from _dpll_test_mult */
+#define DPLL_MULT_UNDERFLOW -1
+
+/*
+ * Scale factor to mitigate roundoff errors in DPLL rate rounding.
+ * The higher the scale factor, the greater the risk of arithmetic overflow,
+ * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
+ * must be a power of DPLL_SCALE_BASE.
+ */
+#define DPLL_SCALE_FACTOR 64
+#define DPLL_SCALE_BASE 2
+#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
+ (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
+
+/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+#define DPLL_FINT_BAND1_MIN 750000
+#define DPLL_FINT_BAND1_MAX 2100000
+#define DPLL_FINT_BAND2_MIN 7500000
+#define DPLL_FINT_BAND2_MAX 21000000
+
+/* _dpll_test_fint() return codes */
+#define DPLL_FINT_UNDERFLOW -1
+#define DPLL_FINT_INVALID -2
+
+/* Private functions */
+
+/*
+ * _dpll_test_fint - test whether an Fint value is valid for the DPLL
+ * @clk: DPLL struct clk to test
+ * @n: divider value (N) to test
+ *
+ * Tests whether a particular divider @n will result in a valid DPLL
+ * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
+ * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
+ * (assuming that it is counting N upwards), or -2 if the enclosing loop
+ * should skip to the next iteration (again assuming N is increasing).
+ */
+static int _dpll_test_fint(struct clk *clk, u8 n)
+{
+ struct dpll_data *dd;
+ long fint;
+ int ret = 0;
+
+ dd = clk->dpll_data;
+
+ /* DPLL divider must result in a valid jitter correction val */
+ fint = clk->parent->rate / (n + 1);
+ if (fint < DPLL_FINT_BAND1_MIN) {
+
+ pr_debug("rejecting n=%d due to Fint failure, "
+ "lowering max_divider\n", n);
+ dd->max_divider = n;
+ ret = DPLL_FINT_UNDERFLOW;
+
+ } else if (fint > DPLL_FINT_BAND1_MAX &&
+ fint < DPLL_FINT_BAND2_MIN) {
+
+ pr_debug("rejecting n=%d due to Fint failure\n", n);
+ ret = DPLL_FINT_INVALID;
+
+ } else if (fint > DPLL_FINT_BAND2_MAX) {
+
+ pr_debug("rejecting n=%d due to Fint failure, "
+ "boosting min_divider\n", n);
+ dd->min_divider = n;
+ ret = DPLL_FINT_INVALID;
+
+ }
+
+ return ret;
+}
+
+static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
+ unsigned int m, unsigned int n)
+{
+ unsigned long long num;
+
+ num = (unsigned long long)parent_rate * m;
+ do_div(num, n);
+ return num;
+}
+
+/*
+ * _dpll_test_mult - test a DPLL multiplier value
+ * @m: pointer to the DPLL m (multiplier) value under test
+ * @n: current DPLL n (divider) value under test
+ * @new_rate: pointer to storage for the resulting rounded rate
+ * @target_rate: the desired DPLL rate
+ * @parent_rate: the DPLL's parent clock rate
+ *
+ * This code tests a DPLL multiplier value, ensuring that the
+ * resulting rate will not be higher than the target_rate, and that
+ * the multiplier value itself is valid for the DPLL. Initially, the
+ * integer pointed to by the m argument should be prescaled by
+ * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
+ * a non-scaled m upon return. This non-scaled m will result in a
+ * new_rate as close as possible to target_rate (but not greater than
+ * target_rate) given the current (parent_rate, n, prescaled m)
+ * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
+ * non-scaled m attempted to underflow, which can allow the calling
+ * function to bail out early; or 0 upon success.
+ */
+static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
+ unsigned long target_rate,
+ unsigned long parent_rate)
+{
+ int r = 0, carry = 0;
+
+ /* Unscale m and round if necessary */
+ if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
+ carry = 1;
+ *m = (*m / DPLL_SCALE_FACTOR) + carry;
+
+ /*
+ * The new rate must be <= the target rate to avoid programming
+ * a rate that is impossible for the hardware to handle
+ */
+ *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+ if (*new_rate > target_rate) {
+ (*m)--;
+ *new_rate = 0;
+ }
+
+ /* Guard against m underflow */
+ if (*m < DPLL_MIN_MULTIPLIER) {
+ *m = DPLL_MIN_MULTIPLIER;
+ *new_rate = 0;
+ r = DPLL_MULT_UNDERFLOW;
+ }
+
+ if (*new_rate == 0)
+ *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+
+ return r;
+}
+
+/* Public functions */
+
+void omap2_init_dpll_parent(struct clk *clk)
+{
+ u32 v;
+ struct dpll_data *dd;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ return;
+
+ /* Return bypass rate if DPLL is bypassed */
+ v = __raw_readl(dd->control_reg);
+ v &= dd->enable_mask;
+ v >>= __ffs(dd->enable_mask);
+
+ /* Reparent in case the dpll is in bypass */
+ if (cpu_is_omap24xx()) {
+ if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP2XXX_EN_DPLL_FRBYPASS)
+ clk_reparent(clk, dd->clk_bypass);
+ } else if (cpu_is_omap34xx()) {
+ if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP3XXX_EN_DPLL_FRBYPASS)
+ clk_reparent(clk, dd->clk_bypass);
+ } else if (cpu_is_omap44xx()) {
+ if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+ v == OMAP4XXX_EN_DPLL_MNBYPASS)
+ clk_reparent(clk, dd->clk_bypass);
+ }
+ return;
+}
+
+/**
+ * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
+ * @clk: struct clk * of a DPLL
+ *
+ * DPLLs can be locked or bypassed - basically, enabled or disabled.
+ * When locked, the DPLL output depends on the M and N values. When
+ * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
+ * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
+ * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
+ * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
+ * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
+ * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
+ * if the clock @clk is not a DPLL.
+ */
+u32 omap2_get_dpll_rate(struct clk *clk)
+{
+ long long dpll_clk;
+ u32 dpll_mult, dpll_div, v;
+ struct dpll_data *dd;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ return 0;
+
+ /* Return bypass rate if DPLL is bypassed */
+ v = __raw_readl(dd->control_reg);
+ v &= dd->enable_mask;
+ v >>= __ffs(dd->enable_mask);
+
+ if (cpu_is_omap24xx()) {
+ if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP2XXX_EN_DPLL_FRBYPASS)
+ return dd->clk_bypass->rate;
+ } else if (cpu_is_omap34xx()) {
+ if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP3XXX_EN_DPLL_FRBYPASS)
+ return dd->clk_bypass->rate;
+ } else if (cpu_is_omap44xx()) {
+ if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+ v == OMAP4XXX_EN_DPLL_MNBYPASS)
+ return dd->clk_bypass->rate;
+ }
+
+ v = __raw_readl(dd->mult_div1_reg);
+ dpll_mult = v & dd->mult_mask;
+ dpll_mult >>= __ffs(dd->mult_mask);
+ dpll_div = v & dd->div1_mask;
+ dpll_div >>= __ffs(dd->div1_mask);
+
+ dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+ do_div(dpll_clk, dpll_div + 1);
+
+ return dpll_clk;
+}
+
+/* DPLL rate rounding code */
+
+/**
+ * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
+ * @clk: struct clk * of the DPLL
+ * @tolerance: maximum rate error tolerance
+ *
+ * Set the maximum DPLL rate error tolerance for the rate rounding
+ * algorithm. The rate tolerance is an attempt to balance DPLL power
+ * saving (the least divider value "n") vs. rate fidelity (the least
+ * difference between the desired DPLL target rate and the rounded
+ * rate out of the algorithm). So, increasing the tolerance is likely
+ * to decrease DPLL power consumption and increase DPLL rate error.
+ * Returns -EINVAL if provided a null clock ptr or a clk that is not a
+ * DPLL; or 0 upon success.
+ */
+int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
+{
+ if (!clk || !clk->dpll_data)
+ return -EINVAL;
+
+ clk->dpll_data->rate_tolerance = tolerance;
+
+ return 0;
+}
+
+/**
+ * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
+ * @clk: struct clk * for a DPLL
+ * @target_rate: desired DPLL clock rate
+ *
+ * Given a DPLL, a desired target rate, and a rate tolerance, round
+ * the target rate to a possible, programmable rate for this DPLL.
+ * Rate tolerance is assumed to be set by the caller before this
+ * function is called. Attempts to select the minimum possible n
+ * within the tolerance to reduce power consumption. Stores the
+ * computed (m, n) in the DPLL's dpll_data structure so set_rate()
+ * will not need to call this (expensive) function again. Returns ~0
+ * if the target rate cannot be rounded, either because the rate is
+ * too low or because the rate tolerance is set too tightly; or the
+ * rounded rate upon success.
+ */
+long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+{
+ int m, n, r, e, scaled_max_m;
+ unsigned long scaled_rt_rp, new_rate;
+ int min_e = -1, min_e_m = -1, min_e_n = -1;
+ struct dpll_data *dd;
+
+ if (!clk || !clk->dpll_data)
+ return ~0;
+
+ dd = clk->dpll_data;
+
+ pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
+ "%ld\n", clk->name, target_rate);
+
+ scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+ scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
+
+ dd->last_rounded_rate = 0;
+
+ for (n = dd->min_divider; n <= dd->max_divider; n++) {
+
+ /* Is the (input clk, divider) pair valid for the DPLL? */
+ r = _dpll_test_fint(clk, n);
+ if (r == DPLL_FINT_UNDERFLOW)
+ break;
+ else if (r == DPLL_FINT_INVALID)
+ continue;
+
+ /* Compute the scaled DPLL multiplier, based on the divider */
+ m = scaled_rt_rp * n;
+
+ /*
+ * Since we're counting n up, a m overflow means we
+ * can bail out completely (since as n increases in
+ * the next iteration, there's no way that m can
+ * increase beyond the current m)
+ */
+ if (m > scaled_max_m)
+ break;
+
+ r = _dpll_test_mult(&m, n, &new_rate, target_rate,
+ dd->clk_ref->rate);
+
+ /* m can't be set low enough for this n - try with a larger n */
+ if (r == DPLL_MULT_UNDERFLOW)
+ continue;
+
+ e = target_rate - new_rate;
+ pr_debug("clock: n = %d: m = %d: rate error is %d "
+ "(new_rate = %ld)\n", n, m, e, new_rate);
+
+ if (min_e == -1 ||
+ min_e >= (int)(abs(e) - dd->rate_tolerance)) {
+ min_e = e;
+ min_e_m = m;
+ min_e_n = n;
+
+ pr_debug("clock: found new least error %d\n", min_e);
+
+ /* We found good settings -- bail out now */
+ if (min_e <= dd->rate_tolerance)
+ break;
+ }
+ }
+
+ if (min_e < 0) {
+ pr_debug("clock: error: target rate or tolerance too low\n");
+ return ~0;
+ }
+
+ dd->last_rounded_m = min_e_m;
+ dd->last_rounded_n = min_e_n;
+ dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
+ min_e_m, min_e_n);
+
+ pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
+ min_e, min_e_m, min_e_n);
+ pr_debug("clock: final rate: %ld (target rate: %ld)\n",
+ dd->last_rounded_rate, target_rate);
+
+ return dd->last_rounded_rate;
+}
+
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 759c72a48f7..a6d0b34b799 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -2,7 +2,7 @@
* linux/arch/arm/mach-omap2/clock.c
*
* Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2008 Nokia Corporation
+ * Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@@ -14,11 +14,10 @@
*/
#undef DEBUG
-#include <linux/module.h>
#include <linux/kernel.h>
-#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
+#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
@@ -28,10 +27,7 @@
#include <plat/clockdomain.h>
#include <plat/cpu.h>
#include <plat/prcm.h>
-#include <asm/div64.h>
-#include <plat/sdrc.h>
-#include "sdrc.h"
#include "clock.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
@@ -39,140 +35,44 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
-/* DPLL rate rounding: minimum DPLL multiplier, divider values */
-#define DPLL_MIN_MULTIPLIER 1
-#define DPLL_MIN_DIVIDER 1
-
-/* Possible error results from _dpll_test_mult */
-#define DPLL_MULT_UNDERFLOW -1
+u8 cpu_mask;
/*
- * Scale factor to mitigate roundoff errors in DPLL rate rounding.
- * The higher the scale factor, the greater the risk of arithmetic overflow,
- * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
- * must be a power of DPLL_SCALE_BASE.
+ * OMAP2+ specific clock functions
*/
-#define DPLL_SCALE_FACTOR 64
-#define DPLL_SCALE_BASE 2
-#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
- (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
-
-/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
-#define DPLL_FINT_BAND1_MIN 750000
-#define DPLL_FINT_BAND1_MAX 2100000
-#define DPLL_FINT_BAND2_MIN 7500000
-#define DPLL_FINT_BAND2_MAX 21000000
-
-/* _dpll_test_fint() return codes */
-#define DPLL_FINT_UNDERFLOW -1
-#define DPLL_FINT_INVALID -2
-
-u8 cpu_mask;
-
-/*-------------------------------------------------------------------------
- * OMAP2/3/4 specific clock functions
- *-------------------------------------------------------------------------*/
-
-void omap2_init_dpll_parent(struct clk *clk)
-{
- u32 v;
- struct dpll_data *dd;
-
- dd = clk->dpll_data;
- if (!dd)
- return;
- /* Return bypass rate if DPLL is bypassed */
- v = __raw_readl(dd->control_reg);
- v &= dd->enable_mask;
- v >>= __ffs(dd->enable_mask);
-
- /* Reparent in case the dpll is in bypass */
- if (cpu_is_omap24xx()) {
- if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
- v == OMAP2XXX_EN_DPLL_FRBYPASS)
- clk_reparent(clk, dd->clk_bypass);
- } else if (cpu_is_omap34xx()) {
- if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
- v == OMAP3XXX_EN_DPLL_FRBYPASS)
- clk_reparent(clk, dd->clk_bypass);
- } else if (cpu_is_omap44xx()) {
- if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
- v == OMAP4XXX_EN_DPLL_FRBYPASS ||
- v == OMAP4XXX_EN_DPLL_MNBYPASS)
- clk_reparent(clk, dd->clk_bypass);
- }
- return;
-}
+/* Private functions */
/**
- * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
- * @clk: struct clk *
- *
- * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
- * don't take effect until the VALID_CONFIG bit is written, write the
- * VALID_CONFIG bit and wait for the write to complete. No return value.
- */
-static void _omap2xxx_clk_commit(struct clk *clk)
-{
- if (!cpu_is_omap24xx())
- return;
-
- if (!(clk->flags & DELAYED_APP))
- return;
-
- prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
- OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
- /* OCP barrier */
- prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
-}
-
-/*
- * _dpll_test_fint - test whether an Fint value is valid for the DPLL
- * @clk: DPLL struct clk to test
- * @n: divider value (N) to test
+ * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ * @clk: struct clk * belonging to the module
*
- * Tests whether a particular divider @n will result in a valid DPLL
- * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
- * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
- * (assuming that it is counting N upwards), or -2 if the enclosing loop
- * should skip to the next iteration (again assuming N is increasing).
+ * If the necessary clocks for the OMAP hardware IP block that
+ * corresponds to clock @clk are enabled, then wait for the module to
+ * indicate readiness (i.e., to leave IDLE). This code does not
+ * belong in the clock code and will be moved in the medium term to
+ * module-dependent code. No return value.
*/
-static int _dpll_test_fint(struct clk *clk, u8 n)
+static void _omap2_module_wait_ready(struct clk *clk)
{
- struct dpll_data *dd;
- long fint;
- int ret = 0;
-
- dd = clk->dpll_data;
-
- /* DPLL divider must result in a valid jitter correction val */
- fint = clk->parent->rate / (n + 1);
- if (fint < DPLL_FINT_BAND1_MIN) {
-
- pr_debug("rejecting n=%d due to Fint failure, "
- "lowering max_divider\n", n);
- dd->max_divider = n;
- ret = DPLL_FINT_UNDERFLOW;
-
- } else if (fint > DPLL_FINT_BAND1_MAX &&
- fint < DPLL_FINT_BAND2_MIN) {
-
- pr_debug("rejecting n=%d due to Fint failure\n", n);
- ret = DPLL_FINT_INVALID;
-
- } else if (fint > DPLL_FINT_BAND2_MAX) {
-
- pr_debug("rejecting n=%d due to Fint failure, "
- "boosting min_divider\n", n);
- dd->min_divider = n;
- ret = DPLL_FINT_INVALID;
+ void __iomem *companion_reg, *idlest_reg;
+ u8 other_bit, idlest_bit, idlest_val;
+ /* Not all modules have multiple clocks that their IDLEST depends on */
+ if (clk->ops->find_companion) {
+ clk->ops->find_companion(clk, &companion_reg, &other_bit);
+ if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+ return;
}
- return ret;
+ clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
+
+ omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
+ clk->name);
}
+/* Public functions */
+
/**
* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
* @clk: OMAP clock struct ptr to use
@@ -181,7 +81,6 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
* clockdomain pointer, and save it into the struct clk. Intended to be
* called during clk_register(). No return value.
*/
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
@@ -199,117 +98,6 @@ void omap2_init_clk_clkdm(struct clk *clk)
"clkdm %s\n", clk->name, clk->clkdm_name);
}
}
-#endif
-
-/**
- * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
- * @clk: OMAP clock struct ptr to use
- *
- * Given a pointer to a source-selectable struct clk, read the hardware
- * register and determine what its parent is currently set to. Update the
- * clk->parent field with the appropriate clk ptr.
- */
-void omap2_init_clksel_parent(struct clk *clk)
-{
- const struct clksel *clks;
- const struct clksel_rate *clkr;
- u32 r, found = 0;
-
- if (!clk->clksel)
- return;
-
- r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
- r >>= __ffs(clk->clksel_mask);
-
- for (clks = clk->clksel; clks->parent && !found; clks++) {
- for (clkr = clks->rates; clkr->div && !found; clkr++) {
- if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
- if (clk->parent != clks->parent) {
- pr_debug("clock: inited %s parent "
- "to %s (was %s)\n",
- clk->name, clks->parent->name,
- ((clk->parent) ?
- clk->parent->name : "NULL"));
- clk_reparent(clk, clks->parent);
- };
- found = 1;
- }
- }
- }
-
- if (!found)
- printk(KERN_ERR "clock: init parent: could not find "
- "regval %0x for clock %s\n", r, clk->name);
-
- return;
-}
-
-/**
- * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
- * @clk: struct clk * of a DPLL
- *
- * DPLLs can be locked or bypassed - basically, enabled or disabled.
- * When locked, the DPLL output depends on the M and N values. When
- * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
- * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
- * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
- * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
- * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
- * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
- * if the clock @clk is not a DPLL.
- */
-u32 omap2_get_dpll_rate(struct clk *clk)
-{
- long long dpll_clk;
- u32 dpll_mult, dpll_div, v;
- struct dpll_data *dd;
-
- dd = clk->dpll_data;
- if (!dd)
- return 0;
-
- /* Return bypass rate if DPLL is bypassed */
- v = __raw_readl(dd->control_reg);
- v &= dd->enable_mask;
- v >>= __ffs(dd->enable_mask);
-
- if (cpu_is_omap24xx()) {
- if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
- v == OMAP2XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
- } else if (cpu_is_omap34xx()) {
- if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
- v == OMAP3XXX_EN_DPLL_FRBYPASS)
- return dd->clk_bypass->rate;
- } else if (cpu_is_omap44xx()) {
- if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
- v == OMAP4XXX_EN_DPLL_FRBYPASS ||
- v == OMAP4XXX_EN_DPLL_MNBYPASS)
- return dd->clk_bypass->rate;
- }
-
- v = __raw_readl(dd->mult_div1_reg);
- dpll_mult = v & dd->mult_mask;
- dpll_mult >>= __ffs(dd->mult_mask);
- dpll_div = v & dd->div1_mask;
- dpll_div >>= __ffs(dd->div1_mask);
-
- dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
- do_div(dpll_clk, dpll_div + 1);
-
- return dpll_clk;
-}
-
-/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
-{
- WARN_ON(!clk->fixed_div);
-
- return clk->parent->rate / clk->fixed_div;
-}
/**
* omap2_clk_dflt_find_companion - find companion clock to @clk
@@ -351,7 +139,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
* @clk: struct clk * to find IDLEST info for
* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
- * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
+ * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
+ * @idlest_val: u8 * to return the idle status indicator
*
* Return the CM_IDLEST register address and bit shift corresponding
* to the module that "owns" this clock. This default code assumes
@@ -361,40 +150,26 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
* CM_IDLEST2). This is not true for all modules. No return value.
*/
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
- u8 *idlest_bit)
+ u8 *idlest_bit, u8 *idlest_val)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = clk->enable_bit;
-}
-/**
- * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
- * @clk: struct clk * belonging to the module
- *
- * If the necessary clocks for the OMAP hardware IP block that
- * corresponds to clock @clk are enabled, then wait for the module to
- * indicate readiness (i.e., to leave IDLE). This code does not
- * belong in the clock code and will be moved in the medium term to
- * module-dependent code. No return value.
- */
-static void omap2_module_wait_ready(struct clk *clk)
-{
- void __iomem *companion_reg, *idlest_reg;
- u8 other_bit, idlest_bit;
-
- /* Not all modules have multiple clocks that their IDLEST depends on */
- if (clk->ops->find_companion) {
- clk->ops->find_companion(clk, &companion_reg, &other_bit);
- if (!(__raw_readl(companion_reg) & (1 << other_bit)))
- return;
- }
-
- clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
+ /*
+ * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+ * 34xx reverses this, just to keep us on our toes
+ * AM35xx uses both, depending on the module.
+ */
+ if (cpu_is_omap24xx())
+ *idlest_val = OMAP24XX_CM_IDLEST_VAL;
+ else if (cpu_is_omap34xx())
+ *idlest_val = OMAP34XX_CM_IDLEST_VAL;
+ else
+ BUG();
- omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
}
int omap2_dflt_clk_enable(struct clk *clk)
@@ -416,7 +191,7 @@ int omap2_dflt_clk_enable(struct clk *clk)
v = __raw_readl(clk->enable_reg); /* OCP barrier */
if (clk->ops->find_idlest)
- omap2_module_wait_ready(clk);
+ _omap2_module_wait_ready(clk);
return 0;
}
@@ -456,337 +231,109 @@ const struct clkops clkops_omap2_dflt = {
.disable = omap2_dflt_clk_disable,
};
-/* Enables clock without considering parent dependencies or use count
- * REVISIT: Maybe change this to use clk->enable like on omap1?
+/**
+ * omap2_clk_disable - disable a clock, if the system is not using it
+ * @clk: struct clk * to disable
+ *
+ * Decrements the usecount on struct clk @clk. If there are no users
+ * left, call the clkops-specific clock disable function to disable it
+ * in hardware. If the clock is part of a clockdomain (which they all
+ * should be), request that the clockdomain be disabled. (It too has
+ * a usecount, and so will not be disabled in the hardware until it no
+ * longer has any users.) If the clock has a parent clock (most of
+ * them do), then call ourselves, recursing on the parent clock. This
+ * can cause an entire branch of the clock tree to be powered off by
+ * simply disabling one clock. Intended to be called with the clockfw_lock
+ * spinlock held. No return value.
*/
-static int _omap2_clk_enable(struct clk *clk)
-{
- return clk->ops->enable(clk);
-}
-
-/* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
-{
- clk->ops->disable(clk);
-}
-
void omap2_clk_disable(struct clk *clk)
{
- if (clk->usecount > 0 && !(--clk->usecount)) {
- _omap2_clk_disable(clk);
- if (clk->parent)
- omap2_clk_disable(clk->parent);
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
- if (clk->clkdm)
- omap2_clkdm_clk_disable(clk->clkdm, clk);
-#endif
-
+ if (clk->usecount == 0) {
+ WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
+ "already 0?", clk->name);
+ return;
}
-}
-int omap2_clk_enable(struct clk *clk)
-{
- int ret = 0;
+ pr_debug("clock: %s: decrementing usecount\n", clk->name);
- if (clk->usecount++ == 0) {
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
- if (clk->clkdm)
- omap2_clkdm_clk_enable(clk->clkdm, clk);
-#endif
+ clk->usecount--;
- if (clk->parent) {
- ret = omap2_clk_enable(clk->parent);
- if (ret)
- goto err;
- }
+ if (clk->usecount > 0)
+ return;
- ret = _omap2_clk_enable(clk);
- if (ret) {
- if (clk->parent)
- omap2_clk_disable(clk->parent);
+ pr_debug("clock: %s: disabling in hardware\n", clk->name);
- goto err;
- }
- }
- return ret;
+ clk->ops->disable(clk);
-err:
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
-#endif
- clk->usecount--;
- return ret;
-}
-
-/*
- * Used for clocks that are part of CLKSEL_xyz governed clocks.
- * REVISIT: Maybe change to use clk->enable() functions like on omap1?
- */
-unsigned long omap2_clksel_recalc(struct clk *clk)
-{
- unsigned long rate;
- u32 div = 0;
-
- pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
-
- div = omap2_clksel_get_divisor(clk);
- if (div == 0)
- return clk->rate;
-
- rate = clk->parent->rate / div;
-
- pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
-
- return rate;
-}
-
-/**
- * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
- * @clk: OMAP struct clk ptr to inspect
- * @src_clk: OMAP struct clk ptr of the parent clk to search for
- *
- * Scan the struct clksel array associated with the clock to find
- * the element associated with the supplied parent clock address.
- * Returns a pointer to the struct clksel on success or NULL on error.
- */
-static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
- struct clk *src_clk)
-{
- const struct clksel *clks;
-
- if (!clk->clksel)
- return NULL;
-
- for (clks = clk->clksel; clks->parent; clks++) {
- if (clks->parent == src_clk)
- break; /* Found the requested parent */
- }
-
- if (!clks->parent) {
- printk(KERN_ERR "clock: Could not find parent clock %s in "
- "clksel array of clock %s\n", src_clk->name,
- clk->name);
- return NULL;
- }
- return clks;
+ if (clk->parent)
+ omap2_clk_disable(clk->parent);
}
/**
- * omap2_clksel_round_rate_div - find divisor for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- * @new_div: ptr to where we should store the divisor
+ * omap2_clk_enable - request that the system enable a clock
+ * @clk: struct clk * to enable
*
- * Finds 'best' divider value in an array based on the source and target
- * rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
- *
- * Returns the rounded clock rate or returns 0xffffffff on error.
+ * Increments the usecount on struct clk @clk. If there were no users
+ * previously, then recurse up the clock tree, enabling all of the
+ * clock's parents and all of the parent clockdomains, and finally,
+ * enabling @clk's clockdomain, and @clk itself. Intended to be
+ * called with the clockfw_lock spinlock held. Returns 0 upon success
+ * or a negative error code upon failure.
*/
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
- u32 *new_div)
-{
- unsigned long test_rate;
- const struct clksel *clks;
- const struct clksel_rate *clkr;
- u32 last_div = 0;
-
- pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
- clk->name, target_rate);
-
- *new_div = 1;
-
- clks = omap2_get_clksel_by_parent(clk, clk->parent);
- if (!clks)
- return ~0;
-
- for (clkr = clks->rates; clkr->div; clkr++) {
- if (!(clkr->flags & cpu_mask))
- continue;
-
- /* Sanity check */
- if (clkr->div <= last_div)
- pr_err("clock: clksel_rate table not sorted "
- "for clock %s", clk->name);
-
- last_div = clkr->div;
-
- test_rate = clk->parent->rate / clkr->div;
-
- if (test_rate <= target_rate)
- break; /* found it */
- }
-
- if (!clkr->div) {
- pr_err("clock: Could not find divisor for target "
- "rate %ld for clock %s parent %s\n", target_rate,
- clk->name, clk->parent->name);
- return ~0;
- }
-
- *new_div = clkr->div;
-
- pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
- (clk->parent->rate / clkr->div));
-
- return (clk->parent->rate / clkr->div);
-}
-
-/**
- * omap2_clksel_round_rate - find rounded rate for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- *
- * Compatibility wrapper for OMAP clock framework
- * Finds best target rate based on the source clock and possible dividers.
- * rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
- *
- * Returns the rounded clock rate or returns 0xffffffff on error.
- */
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
-{
- u32 new_div;
-
- return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
-}
-
-
-/* Given a clock and a rate apply a clock specific rounding function */
-long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+int omap2_clk_enable(struct clk *clk)
{
- if (clk->round_rate)
- return clk->round_rate(clk, rate);
+ int ret;
- if (clk->flags & RATE_FIXED)
- printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
- "on fixed-rate clock %s\n", clk->name);
+ pr_debug("clock: %s: incrementing usecount\n", clk->name);
- return clk->rate;
-}
-
-/**
- * omap2_clksel_to_divisor() - turn clksel field value into integer divider
- * @clk: OMAP struct clk to use
- * @field_val: register field value to find
- *
- * Given a struct clk of a rate-selectable clksel clock, and a register field
- * value to search for, find the corresponding clock divisor. The register
- * field value should be pre-masked and shifted down so the LSB is at bit 0
- * before calling. Returns 0 on error
- */
-u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
-{
- const struct clksel *clks;
- const struct clksel_rate *clkr;
+ clk->usecount++;
- clks = omap2_get_clksel_by_parent(clk, clk->parent);
- if (!clks)
+ if (clk->usecount > 1)
return 0;
- for (clkr = clks->rates; clkr->div; clkr++) {
- if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
- break;
- }
+ pr_debug("clock: %s: enabling in hardware\n", clk->name);
- if (!clkr->div) {
- printk(KERN_ERR "clock: Could not find fieldval %d for "
- "clock %s parent %s\n", field_val, clk->name,
- clk->parent->name);
- return 0;
+ if (clk->parent) {
+ ret = omap2_clk_enable(clk->parent);
+ if (ret) {
+ WARN(1, "clock: %s: could not enable parent %s: %d\n",
+ clk->name, clk->parent->name, ret);
+ goto oce_err1;
+ }
}
- return clkr->div;
-}
-
-/**
- * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
- * @clk: OMAP struct clk to use
- * @div: integer divisor to search for
- *
- * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
- * find the corresponding register field value. The return register value is
- * the value before left-shifting. Returns ~0 on error
- */
-u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
-{
- const struct clksel *clks;
- const struct clksel_rate *clkr;
-
- /* should never happen */
- WARN_ON(div == 0);
-
- clks = omap2_get_clksel_by_parent(clk, clk->parent);
- if (!clks)
- return ~0;
-
- for (clkr = clks->rates; clkr->div; clkr++) {
- if ((clkr->flags & cpu_mask) && (clkr->div == div))
- break;
+ if (clk->clkdm) {
+ ret = omap2_clkdm_clk_enable(clk->clkdm, clk);
+ if (ret) {
+ WARN(1, "clock: %s: could not enable clockdomain %s: "
+ "%d\n", clk->name, clk->clkdm->name, ret);
+ goto oce_err2;
+ }
}
- if (!clkr->div) {
- printk(KERN_ERR "clock: Could not find divisor %d for "
- "clock %s parent %s\n", div, clk->name,
- clk->parent->name);
- return ~0;
+ ret = clk->ops->enable(clk);
+ if (ret) {
+ WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
+ goto oce_err3;
}
- return clkr->val;
-}
-
-/**
- * omap2_clksel_get_divisor - get current divider applied to parent clock.
- * @clk: OMAP struct clk to use.
- *
- * Returns the integer divisor upon success or 0 on error.
- */
-u32 omap2_clksel_get_divisor(struct clk *clk)
-{
- u32 v;
-
- if (!clk->clksel_mask)
- return 0;
-
- v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
- v >>= __ffs(clk->clksel_mask);
-
- return omap2_clksel_to_divisor(clk, v);
-}
-
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 v, field_val, validrate, new_div = 0;
-
- if (!clk->clksel_mask)
- return -EINVAL;
-
- validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
- if (validrate != rate)
- return -EINVAL;
-
- field_val = omap2_divisor_to_clksel(clk, new_div);
- if (field_val == ~0)
- return -EINVAL;
-
- v = __raw_readl(clk->clksel_reg);
- v &= ~clk->clksel_mask;
- v |= field_val << __ffs(clk->clksel_mask);
- __raw_writel(v, clk->clksel_reg);
- v = __raw_readl(clk->clksel_reg); /* OCP barrier */
-
- clk->rate = clk->parent->rate / new_div;
+ return 0;
- _omap2xxx_clk_commit(clk);
+oce_err3:
+ if (clk->clkdm)
+ omap2_clkdm_clk_disable(clk->clkdm, clk);
+oce_err2:
+ if (clk->parent)
+ omap2_clk_disable(clk->parent);
+oce_err1:
+ clk->usecount--;
- return 0;
+ return ret;
}
-
/* Set the clock rate for a clock source */
int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
{
@@ -794,11 +341,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
- /* CONFIG_PARTICIPANT clocks are changed only in sets via the
- rate table mechanism, driven by mpu_speed */
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk->set_rate)
ret = clk->set_rate(clk, rate);
@@ -806,289 +348,152 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
return ret;
}
-/*
- * Converts encoded control register address into a full address
- * On error, the return value (parent_div) will be 0.
- */
-static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
- u32 *field_val)
-{
- const struct clksel *clks;
- const struct clksel_rate *clkr;
-
- clks = omap2_get_clksel_by_parent(clk, src_clk);
- if (!clks)
- return 0;
-
- for (clkr = clks->rates; clkr->div; clkr++) {
- if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
- break; /* Found the default rate for this platform */
- }
-
- if (!clkr->div) {
- printk(KERN_ERR "clock: Could not find default rate for "
- "clock %s parent %s\n", clk->name,
- src_clk->parent->name);
- return 0;
- }
-
- /* Should never happen. Add a clksel mask to the struct clk. */
- WARN_ON(clk->clksel_mask == 0);
-
- *field_val = clkr->val;
-
- return clkr->div;
-}
-
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
{
- u32 field_val, v, parent_div;
-
- if (clk->flags & CONFIG_PARTICIPANT)
- return -EINVAL;
-
if (!clk->clksel)
return -EINVAL;
- parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
- if (!parent_div)
- return -EINVAL;
-
- /* Set new source value (previous dividers if any in effect) */
- v = __raw_readl(clk->clksel_reg);
- v &= ~clk->clksel_mask;
- v |= field_val << __ffs(clk->clksel_mask);
- __raw_writel(v, clk->clksel_reg);
- v = __raw_readl(clk->clksel_reg); /* OCP barrier */
-
- _omap2xxx_clk_commit(clk);
-
- clk_reparent(clk, new_parent);
-
- /* CLKSEL clocks follow their parents' rates, divided by a divisor */
- clk->rate = new_parent->rate;
-
- if (parent_div > 0)
- clk->rate /= parent_div;
-
- pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
- clk->name, clk->parent->name, clk->rate);
+ if (clk->parent == new_parent)
+ return 0;
- return 0;
+ return omap2_clksel_set_parent(clk, new_parent);
}
-/* DPLL rate rounding code */
+/* OMAP3/4 non-CORE DPLL clkops */
-/**
- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
- * @clk: struct clk * of the DPLL
- * @tolerance: maximum rate error tolerance
- *
- * Set the maximum DPLL rate error tolerance for the rate rounding
- * algorithm. The rate tolerance is an attempt to balance DPLL power
- * saving (the least divider value "n") vs. rate fidelity (the least
- * difference between the desired DPLL target rate and the rounded
- * rate out of the algorithm). So, increasing the tolerance is likely
- * to decrease DPLL power consumption and increase DPLL rate error.
- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
- * DPLL; or 0 upon success.
- */
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
-{
- if (!clk || !clk->dpll_data)
- return -EINVAL;
-
- clk->dpll_data->rate_tolerance = tolerance;
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
- return 0;
-}
+const struct clkops clkops_omap3_noncore_dpll_ops = {
+ .enable = omap3_noncore_dpll_enable,
+ .disable = omap3_noncore_dpll_disable,
+};
-static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
- unsigned int m, unsigned int n)
-{
- unsigned long long num;
+#endif
- num = (unsigned long long)parent_rate * m;
- do_div(num, n);
- return num;
-}
/*
- * _dpll_test_mult - test a DPLL multiplier value
- * @m: pointer to the DPLL m (multiplier) value under test
- * @n: current DPLL n (divider) value under test
- * @new_rate: pointer to storage for the resulting rounded rate
- * @target_rate: the desired DPLL rate
- * @parent_rate: the DPLL's parent clock rate
- *
- * This code tests a DPLL multiplier value, ensuring that the
- * resulting rate will not be higher than the target_rate, and that
- * the multiplier value itself is valid for the DPLL. Initially, the
- * integer pointed to by the m argument should be prescaled by
- * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
- * a non-scaled m upon return. This non-scaled m will result in a
- * new_rate as close as possible to target_rate (but not greater than
- * target_rate) given the current (parent_rate, n, prescaled m)
- * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
- * non-scaled m attempted to underflow, which can allow the calling
- * function to bail out early; or 0 upon success.
+ * OMAP2+ clock reset and init functions
*/
-static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
- unsigned long target_rate,
- unsigned long parent_rate)
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+void omap2_clk_disable_unused(struct clk *clk)
{
- int r = 0, carry = 0;
+ u32 regval32, v;
- /* Unscale m and round if necessary */
- if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
- carry = 1;
- *m = (*m / DPLL_SCALE_FACTOR) + carry;
+ v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
- /*
- * The new rate must be <= the target rate to avoid programming
- * a rate that is impossible for the hardware to handle
- */
- *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
- if (*new_rate > target_rate) {
- (*m)--;
- *new_rate = 0;
- }
+ regval32 = __raw_readl(clk->enable_reg);
+ if ((regval32 & (1 << clk->enable_bit)) == v)
+ return;
- /* Guard against m underflow */
- if (*m < DPLL_MIN_MULTIPLIER) {
- *m = DPLL_MIN_MULTIPLIER;
- *new_rate = 0;
- r = DPLL_MULT_UNDERFLOW;
+ printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
+ if (cpu_is_omap34xx()) {
+ omap2_clk_enable(clk);
+ omap2_clk_disable(clk);
+ } else {
+ clk->ops->disable(clk);
}
-
- if (*new_rate == 0)
- *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
-
- return r;
+ if (clk->clkdm != NULL)
+ pwrdm_clkdm_state_switch(clk->clkdm);
}
+#endif
/**
- * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
- * @clk: struct clk * for a DPLL
- * @target_rate: desired DPLL clock rate
+ * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
+ * @mpurate_ck_name: clk name of the clock to change rate
*
- * Given a DPLL, a desired target rate, and a rate tolerance, round
- * the target rate to a possible, programmable rate for this DPLL.
- * Rate tolerance is assumed to be set by the caller before this
- * function is called. Attempts to select the minimum possible n
- * within the tolerance to reduce power consumption. Stores the
- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
- * will not need to call this (expensive) function again. Returns ~0
- * if the target rate cannot be rounded, either because the rate is
- * too low or because the rate tolerance is set too tightly; or the
- * rounded rate upon success.
+ * Change the ARM MPU clock rate to the rate specified on the command
+ * line, if one was specified. @mpurate_ck_name should be
+ * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
+ * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
+ * handled by the virt_prcm_set clock, but this should be handled by
+ * the OPP layer. XXX This is intended to be handled by the OPP layer
+ * code in the near future and should be removed from the clock code.
+ * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
+ * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
+ * cannot be found, or 0 upon success.
*/
-long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
{
- int m, n, r, e, scaled_max_m;
- unsigned long scaled_rt_rp, new_rate;
- int min_e = -1, min_e_m = -1, min_e_n = -1;
- struct dpll_data *dd;
+ struct clk *mpurate_ck;
+ int r;
- if (!clk || !clk->dpll_data)
- return ~0;
-
- dd = clk->dpll_data;
-
- pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
- "%ld\n", clk->name, target_rate);
-
- scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
- scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
-
- dd->last_rounded_rate = 0;
-
- for (n = dd->min_divider; n <= dd->max_divider; n++) {
-
- /* Is the (input clk, divider) pair valid for the DPLL? */
- r = _dpll_test_fint(clk, n);
- if (r == DPLL_FINT_UNDERFLOW)
- break;
- else if (r == DPLL_FINT_INVALID)
- continue;
-
- /* Compute the scaled DPLL multiplier, based on the divider */
- m = scaled_rt_rp * n;
-
- /*
- * Since we're counting n up, a m overflow means we
- * can bail out completely (since as n increases in
- * the next iteration, there's no way that m can
- * increase beyond the current m)
- */
- if (m > scaled_max_m)
- break;
-
- r = _dpll_test_mult(&m, n, &new_rate, target_rate,
- dd->clk_ref->rate);
-
- /* m can't be set low enough for this n - try with a larger n */
- if (r == DPLL_MULT_UNDERFLOW)
- continue;
-
- e = target_rate - new_rate;
- pr_debug("clock: n = %d: m = %d: rate error is %d "
- "(new_rate = %ld)\n", n, m, e, new_rate);
-
- if (min_e == -1 ||
- min_e >= (int)(abs(e) - dd->rate_tolerance)) {
- min_e = e;
- min_e_m = m;
- min_e_n = n;
-
- pr_debug("clock: found new least error %d\n", min_e);
+ if (!mpurate)
+ return -EINVAL;
- /* We found good settings -- bail out now */
- if (min_e <= dd->rate_tolerance)
- break;
- }
- }
+ mpurate_ck = clk_get(NULL, mpurate_ck_name);
+ if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
+ return -ENOENT;
- if (min_e < 0) {
- pr_debug("clock: error: target rate or tolerance too low\n");
- return ~0;
+ r = clk_set_rate(mpurate_ck, mpurate);
+ if (IS_ERR_VALUE(r)) {
+ WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
+ mpurate_ck->name, mpurate, r);
+ return -EINVAL;
}
- dd->last_rounded_m = min_e_m;
- dd->last_rounded_n = min_e_n;
- dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
- min_e_m, min_e_n);
+ calibrate_delay();
+ recalculate_root_clocks();
- pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
- min_e, min_e_m, min_e_n);
- pr_debug("clock: final rate: %ld (target rate: %ld)\n",
- dd->last_rounded_rate, target_rate);
+ clk_put(mpurate_ck);
- return dd->last_rounded_rate;
+ return 0;
}
-/*-------------------------------------------------------------------------
- * Omap2 clock reset and init functions
- *-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-void omap2_clk_disable_unused(struct clk *clk)
+/**
+ * omap2_clk_print_new_rates - print summary of current clock tree rates
+ * @hfclkin_ck_name: clk name for the off-chip HF oscillator
+ * @core_ck_name: clk name for the on-chip CORE_CLK
+ * @mpu_ck_name: clk name for the ARM MPU clock
+ *
+ * Prints a short message to the console with the HFCLKIN oscillator
+ * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
+ * Called by the boot-time MPU rate switching code. XXX This is intended
+ * to be handled by the OPP layer code in the near future and should be
+ * removed from the clock code. No return value.
+ */
+void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
+ const char *core_ck_name,
+ const char *mpu_ck_name)
{
- u32 regval32, v;
+ struct clk *hfclkin_ck, *core_ck, *mpu_ck;
+ unsigned long hfclkin_rate;
- v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
+ mpu_ck = clk_get(NULL, mpu_ck_name);
+ if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
+ return;
- regval32 = __raw_readl(clk->enable_reg);
- if ((regval32 & (1 << clk->enable_bit)) == v)
+ core_ck = clk_get(NULL, core_ck_name);
+ if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
return;
- printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
- if (cpu_is_omap34xx()) {
- omap2_clk_enable(clk);
- omap2_clk_disable(clk);
- } else
- _omap2_clk_disable(clk);
- if (clk->clkdm != NULL)
- pwrdm_clkdm_state_switch(clk->clkdm);
-}
+ hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
+ if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
+ return;
+
+ hfclkin_rate = clk_get_rate(hfclkin_ck);
+
+ pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
+ "%ld.%01ld/%ld/%ld MHz\n",
+ (hfclkin_rate / 1000000),
+ ((hfclkin_rate / 100000) % 10),
+ (clk_get_rate(core_ck) / 1000000),
+ (clk_get_rate(mpu_ck) / 1000000));
+}
+
+/* Common data */
+
+struct clk_functions omap2_clk_functions = {
+ .clk_enable = omap2_clk_enable,
+ .clk_disable = omap2_clk_disable,
+ .clk_round_rate = omap2_clk_round_rate,
+ .clk_set_rate = omap2_clk_set_rate,
+ .clk_set_parent = omap2_clk_set_parent,
+ .clk_disable_unused = omap2_clk_disable_unused,
+#ifdef CONFIG_CPU_FREQ
+ /* These will be removed when the OPP code is integrated */
+ .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+ .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
#endif
+};
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 93c48df3b5b..ad8a1f7c1af 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -47,7 +47,10 @@
#define DPLL_LOW_POWER_BYPASS 0x5
#define DPLL_LOCKED 0x7
-int omap2_clk_init(void);
+/* DPLL Type and DCO Selection Flags */
+#define DPLL_J_TYPE 0x1
+#define DPLL_NO_DCO_SEL 0x2
+
int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
@@ -78,23 +81,53 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
u32 *new_div);
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
-void omap2_clk_prepare_for_reboot(void);
+
+
+#ifdef CONFIG_ARCH_OMAP2
+void omap2xxx_clk_prepare_for_reboot(void);
+#else
+static inline void omap2xxx_clk_prepare_for_reboot(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+void omap3_clk_prepare_for_reboot(void);
+#else
+static inline void omap3_clk_prepare_for_reboot(void)
+{
+}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+void omap4_clk_prepare_for_reboot(void);
+#else
+static inline void omap4_clk_prepare_for_reboot(void)
+{
+}
+#endif
+
int omap2_dflt_clk_enable(struct clk *clk);
void omap2_dflt_clk_disable(struct clk *clk);
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
- u8 *idlest_bit);
+ u8 *idlest_bit, u8 *idlest_val);
+int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
+void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
+ const char *core_ck_name,
+ const char *mpu_ck_name);
extern u8 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
+extern const struct clkops clkops_dummy;
extern const struct clkops clkops_omap2_dflt;
extern struct clk_functions omap2_clk_functions;
@@ -104,5 +137,14 @@ extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
+extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
+#else
+#define omap2_clk_init_cpufreq_table 0
+#define omap2_clk_exit_cpufreq_table 0
+#endif
+
+extern const struct clkops clkops_omap3_noncore_dpll_ops;
#endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
new file mode 100644
index 00000000000..d932b142d0b
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -0,0 +1,1911 @@
+/*
+ * linux/arch/arm/mach-omap2/clock2420_data.c
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+
+#include <plat/clkdev_omap.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "prm.h"
+#include "cm.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+
+#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
+
+/*
+ * 2420 clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In many
+ * cases the parent is selectable. The get/set parent calls will also
+ * switch sources.
+ *
+ * Many some clocks say always_enabled, but they can be auto idled for
+ * power savings. They will always be available upon clock request.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+ * noteworthy that most periferals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+ */
+
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+ .name = "func_32k_ck",
+ .ops = &clkops_null,
+ .rate = 32000,
+ .clkdm_name = "wkup_clkdm",
+};
+
+static struct clk secure_32k_ck = {
+ .name = "secure_32k_ck",
+ .ops = &clkops_null,
+ .rate = 32768,
+ .clkdm_name = "wkup_clkdm",
+};
+
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
+ .name = "osc_ck",
+ .ops = &clkops_oscck,
+ .clkdm_name = "wkup_clkdm",
+ .recalc = &omap2_osc_clk_recalc,
+};
+
+/* Without modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
+ .name = "sys_ck", /* ~ ref_clk also */
+ .ops = &clkops_null,
+ .parent = &osc_ck,
+ .clkdm_name = "wkup_clkdm",
+ .recalc = &omap2xxx_sys_clk_recalc,
+};
+
+static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
+ .name = "alt_ck",
+ .ops = &clkops_null,
+ .rate = 54000000,
+ .clkdm_name = "wkup_clkdm",
+};
+
+/*
+ * Analog domain root source clocks
+ */
+
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
+ * deal with this
+ */
+
+static struct dpll_data dpll_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .mult_mask = OMAP24XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP24XX_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_mask = OMAP24XX_EN_DPLL_MASK,
+ .max_multiplier = 1023,
+ .min_divider = 1,
+ .max_divider = 16,
+ .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+/*
+ * XXX Cannot add round_rate here yet, as this is still a composite clock,
+ * not just a DPLL
+ */
+static struct clk dpll_ck = {
+ .name = "dpll_ck",
+ .ops = &clkops_null,
+ .parent = &sys_ck, /* Can be func_32k also */
+ .dpll_data = &dpll_dd,
+ .clkdm_name = "wkup_clkdm",
+ .recalc = &omap2_dpllcore_recalc,
+ .set_rate = &omap2_reprogram_dpllcore,
+};
+
+static struct clk apll96_ck = {
+ .name = "apll96_ck",
+ .ops = &clkops_apll96,
+ .parent = &sys_ck,
+ .rate = 96000000,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
+};
+
+static struct clk apll54_ck = {
+ .name = "apll54_ck",
+ .ops = &clkops_apll54,
+ .parent = &sys_ck,
+ .rate = 54000000,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
+};
+
+/*
+ * PRCM digital base sources
+ */
+
+/* func_54m_ck */
+
+static const struct clksel_rate func_54m_apll54_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate func_54m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel func_54m_clksel[] = {
+ { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+ { .parent = &alt_ck, .rates = func_54m_alt_rates, },
+ { .parent = NULL },
+};
+
+static struct clk func_54m_ck = {
+ .name = "func_54m_ck",
+ .ops = &clkops_null,
+ .parent = &apll54_ck, /* can also be alt_clk */
+ .clkdm_name = "wkup_clkdm",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_54M_SOURCE,
+ .clksel = func_54m_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+ .name = "core_ck",
+ .ops = &clkops_null,
+ .parent = &dpll_ck, /* can also be 32k */
+ .clkdm_name = "wkup_clkdm",
+ .recalc = &followparent_recalc,
+};
+
+static struct clk func_96m_ck = {
+ .name = "func_96m_ck",
+ .ops = &clkops_null,
+ .parent = &apll96_ck,
+ .clkdm_name = "wkup_clkdm",
+ .recalc = &followparent_recalc,
+};
+
+/* func_48m_ck */
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+ { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel func_48m_clksel[] = {
+ { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+ { .parent = &alt_ck, .rates = func_48m_alt_rates },
+ { .parent = NULL }
+};
+
+static struct clk func_48m_ck = {
+ .name = "func_48m_ck",
+ .ops = &clkops_null,
+ .parent = &apll96_ck, /* 96M or Alt */
+ .clkdm_name = "wkup_clkdm",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_48M_SOURCE,
+ .clksel = func_48m_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk func_12m_ck = {
+ .name = "func_12m_ck",
+ .ops = &clkops_null,
+ .parent = &func_48m_ck,
+ .fixed_div = 4,
+ .clkdm_name = "wkup_clkdm",
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+ .name = "ck_wdt1_osc",
+ .ops = &clkops_null, /* RMK: missing? */
+ .parent = &osc_ck,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+ { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+ { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+ { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+ { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+ { .parent = NULL }
+};
+
+static struct clk sys_clkout_src = {
+ .name = "sys_clkout_src",
+ .ops = &clkops_omap2_dflt,
+ .parent = &func_54m_ck,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
+ .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
+ .clksel = common_clkout_src_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate common_clkout_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 },
+};
+
+static const struct clksel sys_clkout_clksel[] = {
+ { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+ { .parent = NULL }
+};
+
+static struct clk sys_clkout = {
+ .name = "sys_clkout",
+ .ops = &clkops_null,
+ .parent = &sys_clkout_src,
+ .clkdm_name = "wkup_clkdm",
+ .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
+ .clksel = sys_clkout_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2_src = {
+ .name = "sys_clkout2_src",
+ .ops = &clkops_omap2_dflt,
+ .parent = &func_54m_ck,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
+ .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
+ .clksel = common_clkout_src_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+ { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
+ { .parent = NULL }
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2 = {
+ .name = "sys_clkout2",
+ .ops = &clkops_null,
+ .parent = &sys_clkout2_src,
+ .clkdm_name = "wkup_clkdm",
+ .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
+ .clksel = sys_clkout2_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk emul_ck = {
+ .name = "emul_ck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &func_54m_ck,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
+ .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
+ .recalc = &followparent_recalc,
+
+};
+
+/*
+ * MPU clock domain
+ * Clocks:
+ * MPU_FCLK, MPU_ICLK
+ * INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_242X },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 0 },
+};
+
+static const struct clksel mpu_clksel[] = {
+ { .parent = &core_ck, .rates = mpu_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk mpu_ck = { /* Control cpu */
+ .name = "mpu_ck",
+ .ops = &clkops_null,
+ .parent = &core_ck,
+ .clkdm_name = "mpu_clkdm",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
+ .clksel = mpu_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * DSP (2420-UMA+IVA1) clock domain
+ * Clocks:
+ * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 0 },
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+ { .parent = &core_ck, .rates = dsp_fck_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk dsp_fck = {
+ .name = "dsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_ck,
+ .clkdm_name = "dsp_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
+ .clksel = dsp_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* DSP interface clock */
+static const struct clksel_rate dsp_irate_ick_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 },
+};
+
+static const struct clksel dsp_irate_ick_clksel[] = {
+ { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+ { .parent = NULL }
+};
+
+/* This clock does not exist as such in the TRM. */
+static struct clk dsp_irate_ick = {
+ .name = "dsp_irate_ick",
+ .ops = &clkops_null,
+ .parent = &dsp_fck,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
+ .clksel = dsp_irate_ick_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* 2420 only */
+static struct clk dsp_ick = {
+ .name = "dsp_ick", /* apparently ipi and isp */
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &dsp_irate_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
+};
+
+/*
+ * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
+ * the C54x, but which is contained in the DSP powerdomain. Does not
+ * exist on later OMAPs.
+ */
+static struct clk iva1_ifck = {
+ .name = "iva1_ifck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_ck,
+ .clkdm_name = "iva1_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
+ .clksel = dsp_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* IVA1 mpu/int/i/f clocks are /2 of parent */
+static struct clk iva1_mpu_int_ifck = {
+ .name = "iva1_mpu_int_ifck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &iva1_ifck,
+ .clkdm_name = "iva1_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ * CAM, HS-USB.
+ * F-CLOCK
+ * SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_242X },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 16, .val = 16, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel core_l3_clksel[] = {
+ { .parent = &core_ck, .rates = core_l3_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
+ .name = "core_l3_ck",
+ .ops = &clkops_null,
+ .parent = &core_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
+ .clksel = core_l3_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+ { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+ { .parent = NULL },
+};
+
+/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
+static struct clk usb_l4_ick = { /* FS-USB interface clock */
+ .name = "usb_l4_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
+ .clksel = usb_l4_ick_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks. Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel l4_clksel[] = {
+ { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+ { .parent = NULL }
+};
+
+static struct clk l4_ck = { /* used both as an ick and fck */
+ .name = "l4_ck",
+ .ops = &clkops_null,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
+ .clksel = l4_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+ { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk ssi_ssr_sst_fck = {
+ .name = "ssi_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
+ .clksel = ssi_ssr_sst_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+ .name = "ssi_l4_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+
+/*
+ * GFX clock domain
+ * Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+ { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+ { .parent = NULL },
+};
+
+static struct clk gfx_3d_fck = {
+ .name = "gfx_3d_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "gfx_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_3D_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP_CLKSEL_GFX_MASK,
+ .clksel = gfx_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_2d_fck = {
+ .name = "gfx_2d_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "gfx_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_2D_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP_CLKSEL_GFX_MASK,
+ .clksel = gfx_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_ick = {
+ .name = "gfx_ick", /* From l3 */
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "gfx_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP_EN_GFX_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+ { .parent = &core_ck, .rates = dss1_fck_core_rates },
+ { .parent = NULL },
+};
+
+static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
+ .name = "dss_ick",
+ .ops = &clkops_omap2_dflt,
+ .parent = &l4_ck, /* really both l3 and l4 */
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss1_fck = {
+ .name = "dss1_fck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &core_ck, /* Core or sys */
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
+ .clksel = dss1_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel dss2_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+ { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+ { .parent = NULL }
+};
+
+static struct clk dss2_fck = { /* Alt clk used in power management */
+ .name = "dss2_fck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
+ .clksel = dss2_fck_clksel,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss_54m_fck = { /* Alt clk used in power management */
+ .name = "dss_54m_fck", /* 54m tv clk */
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_54m_ck,
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_TV_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+ { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+ { .parent = &sys_ck, .rates = gpt_sys_rates },
+ { .parent = &alt_ck, .rates = gpt_alt_rates },
+ { .parent = NULL },
+};
+
+static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt1_fck = {
+ .name = "gpt1_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+ .name = "gpt2_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt3_fck = {
+ .name = "gpt3_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt4_fck = {
+ .name = "gpt4_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt5_fck = {
+ .name = "gpt5_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt6_fck = {
+ .name = "gpt6_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt7_fck = {
+ .name = "gpt7_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt8_fck = {
+ .name = "gpt8_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt9_fck = {
+ .name = "gpt9_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt10_fck = {
+ .name = "gpt10_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt11_fck = {
+ .name = "gpt11_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt12_fck = {
+ .name = "gpt12_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &secure_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+ .name = "mcbsp1_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp2_fck = {
+ .name = "mcbsp2_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+ .name = "mcspi1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+ .name = "mcspi1_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_48m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+ .name = "mcspi2_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+ .name = "mcspi2_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_48m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+ .name = "uart1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+ .name = "uart1_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_48m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+ .name = "uart2_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+ .name = "uart2_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_48m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+ .name = "uart3_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+ .name = "uart3_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_48m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpios_ick = {
+ .name = "gpios_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpios_fck = {
+ .name = "gpios_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_ick = {
+ .name = "mpu_wdt_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_fck = {
+ .name = "mpu_wdt_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sync_32k_ick = {
+ .name = "sync_32k_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+ .name = "cam_ick",
+ .ops = &clkops_omap2_dflt,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
+ * split into two separate clocks, since the parent clocks are different
+ * and the clockdomains are also different.
+ */
+static struct clk cam_fck = {
+ .name = "cam_fck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt4_ick = {
+ .name = "wdt4_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt4_fck = {
+ .name = "wdt4_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+ .name = "wdt3_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+ .name = "wdt3_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_32k_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+ .name = "mspro_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+ .name = "mspro_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc_ick = {
+ .name = "mmc_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc_fck = {
+ .name = "mmc_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+ .name = "fac_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk fac_fck = {
+ .name = "fac_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_12m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk eac_ick = {
+ .name = "eac_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk eac_fck = {
+ .name = "eac_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+ .name = "hdq_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+ .name = "hdq_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_12m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+ .name = "i2c2_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+ .name = "i2c2_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_12m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+ .name = "i2c1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+ .name = "i2c1_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_12m_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+ .ops = &clkops_null, /* RMK: missing? */
+ .parent = &core_l3_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sdma_fck = {
+ .name = "sdma_fck",
+ .ops = &clkops_null, /* RMK: missing? */
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sdma_ick = {
+ .name = "sdma_ick",
+ .ops = &clkops_null, /* RMK: missing? */
+ .parent = &l4_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .recalc = &followparent_recalc,
+};
+
+static struct clk vlynq_ick = {
+ .name = "vlynq_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_242X },
+ { .div = 2, .val = 2, .flags = RATE_IN_242X },
+ { .div = 3, .val = 3, .flags = RATE_IN_242X },
+ { .div = 4, .val = 4, .flags = RATE_IN_242X },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 9, .val = 9, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
+ { .div = 18, .val = 18, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+ { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+ { .parent = &core_ck, .rates = vlynq_fck_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk vlynq_fck = {
+ .name = "vlynq_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
+ .clksel = vlynq_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk des_ick = {
+ .name = "des_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_DES_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sha_ick = {
+ .name = "sha_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_SHA_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+ .name = "rng_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_RNG_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk aes_ick = {
+ .name = "aes_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_AES_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+ .name = "pka_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_PKA_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usb_fck = {
+ .name = "usb_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_48m_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+ .name = "virt_prcm_set",
+ .ops = &clkops_null,
+ .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
+ .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
+ .set_rate = &omap2_select_table_rate,
+ .round_rate = &omap2_round_to_table_rate,
+};
+
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap2420_clks[] = {
+ /* external root sources */
+ CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
+ CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
+ CLK(NULL, "osc_ck", &osc_ck, CK_242X),
+ CLK(NULL, "sys_ck", &sys_ck, CK_242X),
+ CLK(NULL, "alt_ck", &alt_ck, CK_242X),
+ /* internal analog sources */
+ CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
+ CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
+ CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
+ /* internal prcm root sources */
+ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
+ CLK(NULL, "core_ck", &core_ck, CK_242X),
+ CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
+ CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
+ CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
+ CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
+ CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
+ CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
+ CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+ CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
+ CLK(NULL, "emul_ck", &emul_ck, CK_242X),
+ /* mpu domain clocks */
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
+ /* dsp domain clocks */
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
+ CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X),
+ CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
+ CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
+ CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+ /* GFX domain clocks */
+ CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
+ CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
+ CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
+ /* DSS domain clocks */
+ CLK("omapdss", "ick", &dss_ick, CK_242X),
+ CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X),
+ CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X),
+ CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X),
+ /* L3 domain clocks */
+ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
+ CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
+ CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
+ /* L4 domain clocks */
+ CLK(NULL, "l4_ck", &l4_ck, CK_242X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
+ /* virtual meta-group clock */
+ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
+ /* general l4 interface ck, multi-parent functional clk */
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
+ CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
+ CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
+ CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
+ CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
+ CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
+ CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
+ CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
+ CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X),
+ CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
+ CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
+ CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
+ CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
+ CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
+ CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
+ CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
+ CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
+ CLK(NULL, "fac_ick", &fac_ick, CK_242X),
+ CLK(NULL, "fac_fck", &fac_fck, CK_242X),
+ CLK(NULL, "eac_ick", &eac_ick, CK_242X),
+ CLK(NULL, "eac_fck", &eac_fck, CK_242X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
+ CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
+ CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X),
+ CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
+ CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X),
+ CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
+ CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
+ CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
+ CLK(NULL, "des_ick", &des_ick, CK_242X),
+ CLK(NULL, "sha_ick", &sha_ick, CK_242X),
+ CLK("omap_rng", "ick", &rng_ick, CK_242X),
+ CLK(NULL, "aes_ick", &aes_ick, CK_242X),
+ CLK(NULL, "pka_ick", &pka_ick, CK_242X),
+ CLK(NULL, "usb_fck", &usb_fck, CK_242X),
+ CLK("musb_hdrc", "fck", &osc_ck, CK_242X),
+};
+
+/*
+ * init code
+ */
+
+int __init omap2420_clk_init(void)
+{
+ const struct prcm_config *prcm;
+ struct omap_clk *c;
+ u32 clkrate;
+
+ prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+ cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+ cpu_mask = RATE_IN_242X;
+ rate_table = omap2420_rate_table;
+
+ clk_init(&omap2_clk_functions);
+
+ for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+ c++)
+ clk_preinit(c->lk.clk);
+
+ osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
+ propagate_rate(&osc_ck);
+ sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
+ propagate_rate(&sys_ck);
+
+ for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
+ c++) {
+ clkdev_add(&c->lk);
+ clk_register(c->lk.clk);
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
+
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck.rate)
+ continue;
+ if (prcm->dpll_speed <= clkrate)
+ break;
+ }
+ curr_prcm_set = prcm;
+
+ recalculate_root_clocks();
+
+ pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+ (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+ /*
+ * Only enable those clocks we will need, let the drivers
+ * enable other clocks as necessary
+ */
+ clk_enable_init_clocks();
+
+ /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+ vclk = clk_get(NULL, "virt_prcm_set");
+ sclk = clk_get(NULL, "sys_ck");
+ dclk = clk_get(NULL, "dpll_ck");
+
+ return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
new file mode 100644
index 00000000000..44d0cccc51a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -0,0 +1,59 @@
+/*
+ * clock2430.c - OMAP2430-specific clock integration code
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules. No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit,
+ u8 *idlest_val)
+{
+ *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST);
+ *idlest_bit = clk->enable_bit;
+ *idlest_val = OMAP24XX_CM_IDLEST_VAL;
+}
+
+/* 2430 I2CHS has non-standard IDLEST register */
+const struct clkops clkops_omap2430_i2chs_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = omap2430_clk_i2chs_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 97dc7cf7751..0438b6e4f51 100644
--- a/arch/arm/mach-omap2/clock2xxx_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1,8 +1,8 @@
/*
- * linux/arch/arm/mach-omap2/clock2xxx_data.c
+ * linux/arch/arm/mach-omap2/clock2430_data.c
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
+ * Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@@ -13,9 +13,9 @@
* published by the Free Software Foundation.
*/
-#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/clk.h>
+#include <linux/list.h>
#include <plat/clkdev_omap.h>
@@ -28,8 +28,10 @@
#include "cm-regbits-24xx.h"
#include "sdrc.h"
-/*-------------------------------------------------------------------------
- * 24xx clock tree.
+#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
+
+/*
+ * 2430 clock tree.
*
* NOTE:In many cases here we are assigning a 'default' parent. In many
* cases the parent is selectable. The get/set parent calls will also
@@ -46,14 +48,13 @@
* domains. Many get their interface clocks from the L4 domain, but get
* functional clocks from fixed sources or other core domain derived
* clocks.
- *-------------------------------------------------------------------------*/
+ */
/* Base external input clocks */
static struct clk func_32k_ck = {
.name = "func_32k_ck",
.ops = &clkops_null,
.rate = 32000,
- .flags = RATE_FIXED,
.clkdm_name = "wkup_clkdm",
};
@@ -61,7 +62,6 @@ static struct clk secure_32k_ck = {
.name = "secure_32k_ck",
.ops = &clkops_null,
.rate = 32768,
- .flags = RATE_FIXED,
.clkdm_name = "wkup_clkdm",
};
@@ -79,14 +79,13 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.ops = &clkops_null,
.parent = &osc_ck,
.clkdm_name = "wkup_clkdm",
- .recalc = &omap2_sys_clk_recalc,
+ .recalc = &omap2xxx_sys_clk_recalc,
};
static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.name = "alt_ck",
.ops = &clkops_null,
.rate = 54000000,
- .flags = RATE_FIXED,
.clkdm_name = "wkup_clkdm",
};
@@ -107,7 +106,7 @@ static struct dpll_data dpll_dd = {
.clk_ref = &sys_ck,
.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_mask = OMAP24XX_EN_DPLL_MASK,
- .max_multiplier = 1024,
+ .max_multiplier = 1023,
.min_divider = 1,
.max_divider = 16,
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
@@ -132,7 +131,7 @@ static struct clk apll96_ck = {
.ops = &clkops_apll96,
.parent = &sys_ck,
.rate = 96000000,
- .flags = RATE_FIXED | ENABLE_ON_INIT,
+ .flags = ENABLE_ON_INIT,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
@@ -143,7 +142,7 @@ static struct clk apll54_ck = {
.ops = &clkops_apll54,
.parent = &sys_ck,
.rate = 54000000,
- .flags = RATE_FIXED | ENABLE_ON_INIT,
+ .flags = ENABLE_ON_INIT,
.clkdm_name = "wkup_clkdm",
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
@@ -208,7 +207,6 @@ static const struct clksel func_96m_clksel[] = {
{ .parent = NULL }
};
-/* The parent of this clock is not selectable on 2420. */
static struct clk func_96m_ck = {
.name = "func_96m_ck",
.ops = &clkops_null,
@@ -219,8 +217,6 @@ static struct clk func_96m_ck = {
.clksel_mask = OMAP2430_96M_SOURCE,
.clksel = func_96m_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/* func_48m_ck */
@@ -261,7 +257,7 @@ static struct clk func_12m_ck = {
.parent = &func_48m_ck,
.fixed_div = 4,
.clkdm_name = "wkup_clkdm",
- .recalc = &omap2_fixed_divisor_recalc,
+ .recalc = &omap_fixed_divisor_recalc,
};
/* Secure timer, only available in secure mode */
@@ -313,10 +309,10 @@ static struct clk sys_clkout_src = {
.ops = &clkops_omap2_dflt,
.parent = &func_54m_ck,
.clkdm_name = "wkup_clkdm",
- .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
.clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
.clksel = common_clkout_src_clksel,
.recalc = &omap2_clksel_recalc,
@@ -343,7 +339,7 @@ static struct clk sys_clkout = {
.ops = &clkops_null,
.parent = &sys_clkout_src,
.clkdm_name = "wkup_clkdm",
- .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
.clksel = sys_clkout_clksel,
.recalc = &omap2_clksel_recalc,
@@ -351,48 +347,12 @@ static struct clk sys_clkout = {
.set_rate = &omap2_clksel_set_rate
};
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2_src = {
- .name = "sys_clkout2_src",
- .ops = &clkops_omap2_dflt,
- .parent = &func_54m_ck,
- .clkdm_name = "wkup_clkdm",
- .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
- .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
- .init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
- .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
- .clksel = common_clkout_src_clksel,
- .recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
-};
-
-static const struct clksel sys_clkout2_clksel[] = {
- { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
- { .parent = NULL }
-};
-
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2 = {
- .name = "sys_clkout2",
- .ops = &clkops_null,
- .parent = &sys_clkout2_src,
- .clkdm_name = "wkup_clkdm",
- .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
- .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
- .clksel = sys_clkout2_clksel,
- .recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
-};
-
static struct clk emul_ck = {
.name = "emul_ck",
.ops = &clkops_omap2_dflt,
.parent = &func_54m_ck,
.clkdm_name = "wkup_clkdm",
- .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
+ .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &followparent_recalc,
@@ -411,9 +371,6 @@ static struct clk emul_ck = {
static const struct clksel_rate mpu_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
- { .div = 4, .val = 4, .flags = RATE_IN_242X },
- { .div = 6, .val = 6, .flags = RATE_IN_242X },
- { .div = 8, .val = 8, .flags = RATE_IN_242X },
{ .div = 0 },
};
@@ -426,22 +383,18 @@ static struct clk mpu_ck = { /* Control cpu */
.name = "mpu_ck",
.ops = &clkops_null,
.parent = &core_ck,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "mpu_clkdm",
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
.clksel = mpu_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/*
- * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
+ * DSP (2430-IVA2.1) clock domain
* Clocks:
* 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
- * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
*
* Won't be too specific here. The core clock comes into this block
* it is divided then tee'ed. One branch goes directly to xyz enable
@@ -453,9 +406,6 @@ static const struct clksel_rate dsp_fck_core_rates[] = {
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
- { .div = 6, .val = 6, .flags = RATE_IN_242X },
- { .div = 8, .val = 8, .flags = RATE_IN_242X },
- { .div = 12, .val = 12, .flags = RATE_IN_242X },
{ .div = 0 },
};
@@ -468,7 +418,6 @@ static struct clk dsp_fck = {
.name = "dsp_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "dsp_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -476,8 +425,6 @@ static struct clk dsp_fck = {
.clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
.clksel = dsp_fck_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/* DSP interface clock */
@@ -498,23 +445,10 @@ static struct clk dsp_irate_ick = {
.name = "dsp_irate_ick",
.ops = &clkops_null,
.parent = &dsp_fck,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
.clksel = dsp_irate_ick_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
-};
-
-/* 2420 only */
-static struct clk dsp_ick = {
- .name = "dsp_ick", /* apparently ipi and isp */
- .ops = &clkops_omap2_dflt_wait,
- .parent = &dsp_irate_ick,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
- .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
- .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
};
/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
@@ -522,45 +456,11 @@ static struct clk iva2_1_ick = {
.name = "iva2_1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &dsp_irate_ick,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
};
/*
- * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
- * the C54x, but which is contained in the DSP powerdomain. Does not
- * exist on later OMAPs.
- */
-static struct clk iva1_ifck = {
- .name = "iva1_ifck",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &core_ck,
- .flags = CONFIG_PARTICIPANT | DELAYED_APP,
- .clkdm_name = "iva1_clkdm",
- .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
- .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
- .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
- .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
- .clksel = dsp_fck_clksel,
- .recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
-};
-
-/* IVA1 mpu/int/i/f clocks are /2 of parent */
-static struct clk iva1_mpu_int_ifck = {
- .name = "iva1_mpu_int_ifck",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &iva1_ifck,
- .clkdm_name = "iva1_clkdm",
- .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
- .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
- .fixed_div = 2,
- .recalc = &omap2_fixed_divisor_recalc,
-};
-
-/*
* L3 clock domain
* L3 clocks are used for both interface and functional clocks to
* multiple entities. Some of these clocks are completely managed
@@ -581,12 +481,8 @@ static struct clk iva1_mpu_int_ifck = {
*/
static const struct clksel_rate core_l3_core_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
- { .div = 2, .val = 2, .flags = RATE_IN_242X },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
- { .div = 8, .val = 8, .flags = RATE_IN_242X },
- { .div = 12, .val = 12, .flags = RATE_IN_242X },
- { .div = 16, .val = 16, .flags = RATE_IN_242X },
{ .div = 0 }
};
@@ -599,14 +495,11 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.name = "core_l3_ck",
.ops = &clkops_null,
.parent = &core_ck,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "core_l3_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
.clksel = core_l3_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/* usb_l4_ick */
@@ -627,7 +520,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ck,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -635,8 +527,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
.clksel = usb_l4_ick_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/*
@@ -661,14 +551,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
.ops = &clkops_null,
.parent = &core_l3_ck,
- .flags = DELAYED_APP,
.clkdm_name = "core_l4_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
.clksel = l4_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/*
@@ -685,8 +572,6 @@ static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
{ .div = 5, .val = 5, .flags = RATE_IN_243X },
- { .div = 6, .val = 6, .flags = RATE_IN_242X },
- { .div = 8, .val = 8, .flags = RATE_IN_242X },
{ .div = 0 }
};
@@ -699,7 +584,6 @@ static struct clk ssi_ssr_sst_fck = {
.name = "ssi_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
- .flags = DELAYED_APP,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -707,8 +591,6 @@ static struct clk ssi_ssr_sst_fck = {
.clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_sst_fck_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
/*
@@ -737,7 +619,6 @@ static struct clk ssi_l4_ick = {
* divided value of fclk.
*
*/
-/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
static const struct clksel gfx_fck_clksel[] = {
@@ -771,8 +652,6 @@ static struct clk gfx_2d_fck = {
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_fck_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
static struct clk gfx_ick = {
@@ -809,7 +688,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_ck,
- .flags = DELAYED_APP | CONFIG_PARTICIPANT,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
.enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -817,8 +695,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
.clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
.clksel = mdm_ick_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
static struct clk mdm_osc_ck = {
@@ -880,7 +756,6 @@ static struct clk dss1_fck = {
.name = "dss1_fck",
.ops = &clkops_omap2_dflt,
.parent = &core_ck, /* Core or sys */
- .flags = DELAYED_APP,
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -889,8 +764,6 @@ static struct clk dss1_fck = {
.clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
.clksel = dss1_fck_clksel,
.recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
};
static const struct clksel_rate dss2_fck_sys_rates[] = {
@@ -913,7 +786,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.name = "dss2_fck",
.ops = &clkops_omap2_dflt,
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
- .flags = DELAYED_APP,
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_DSS2_SHIFT,
@@ -1242,9 +1114,8 @@ static struct clk gpt12_fck = {
};
static struct clk mcbsp1_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp1_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1253,9 +1124,8 @@ static struct clk mcbsp1_ick = {
};
static struct clk mcbsp1_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp1_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1264,9 +1134,8 @@ static struct clk mcbsp1_fck = {
};
static struct clk mcbsp2_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1275,9 +1144,8 @@ static struct clk mcbsp2_ick = {
};
static struct clk mcbsp2_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1286,9 +1154,8 @@ static struct clk mcbsp2_fck = {
};
static struct clk mcbsp3_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp3_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1297,9 +1164,8 @@ static struct clk mcbsp3_ick = {
};
static struct clk mcbsp3_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp3_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1308,9 +1174,8 @@ static struct clk mcbsp3_fck = {
};
static struct clk mcbsp4_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp4_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 4,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1319,9 +1184,8 @@ static struct clk mcbsp4_ick = {
};
static struct clk mcbsp4_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp4_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 4,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1330,9 +1194,8 @@ static struct clk mcbsp4_fck = {
};
static struct clk mcbsp5_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp5_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 5,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1341,9 +1204,8 @@ static struct clk mcbsp5_ick = {
};
static struct clk mcbsp5_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp5_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 5,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1352,9 +1214,8 @@ static struct clk mcbsp5_fck = {
};
static struct clk mcspi1_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi1_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1363,9 +1224,8 @@ static struct clk mcspi1_ick = {
};
static struct clk mcspi1_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi1_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &func_48m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1374,9 +1234,8 @@ static struct clk mcspi1_fck = {
};
static struct clk mcspi2_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1385,9 +1244,8 @@ static struct clk mcspi2_ick = {
};
static struct clk mcspi2_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &func_48m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1396,9 +1254,8 @@ static struct clk mcspi2_fck = {
};
static struct clk mcspi3_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi3_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1407,9 +1264,8 @@ static struct clk mcspi3_ick = {
};
static struct clk mcspi3_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi3_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &func_48m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1614,26 +1470,6 @@ static struct clk wdt4_fck = {
.recalc = &followparent_recalc,
};
-static struct clk wdt3_ick = {
- .name = "wdt3_ick",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &l4_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP2420_EN_WDT3_SHIFT,
- .recalc = &followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
- .name = "wdt3_fck",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &func_32k_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP2420_EN_WDT3_SHIFT,
- .recalc = &followparent_recalc,
-};
-
static struct clk mspro_ick = {
.name = "mspro_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1654,26 +1490,6 @@ static struct clk mspro_fck = {
.recalc = &followparent_recalc,
};
-static struct clk mmc_ick = {
- .name = "mmc_ick",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &l4_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP2420_EN_MMC_SHIFT,
- .recalc = &followparent_recalc,
-};
-
-static struct clk mmc_fck = {
- .name = "mmc_fck",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &func_96m_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP2420_EN_MMC_SHIFT,
- .recalc = &followparent_recalc,
-};
-
static struct clk fac_ick = {
.name = "fac_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1694,26 +1510,6 @@ static struct clk fac_fck = {
.recalc = &followparent_recalc,
};
-static struct clk eac_ick = {
- .name = "eac_ick",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &l4_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP2420_EN_EAC_SHIFT,
- .recalc = &followparent_recalc,
-};
-
-static struct clk eac_fck = {
- .name = "eac_fck",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &func_96m_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP2420_EN_EAC_SHIFT,
- .recalc = &followparent_recalc,
-};
-
static struct clk hdq_ick = {
.name = "hdq_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1734,10 +1530,13 @@ static struct clk hdq_fck = {
.recalc = &followparent_recalc,
};
+/*
+ * XXX This is marked as a 2420-only define, but it claims to be present
+ * on 2430 also. Double-check.
+ */
static struct clk i2c2_ick = {
- .name = "i2c_ick",
+ .name = "i2c2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1745,21 +1544,9 @@ static struct clk i2c2_ick = {
.recalc = &followparent_recalc,
};
-static struct clk i2c2_fck = {
- .name = "i2c_fck",
- .ops = &clkops_omap2_dflt_wait,
- .id = 2,
- .parent = &func_12m_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP2420_EN_I2C2_SHIFT,
- .recalc = &followparent_recalc,
-};
-
static struct clk i2chs2_fck = {
- .name = "i2c_fck",
+ .name = "i2chs2_fck",
.ops = &clkops_omap2430_i2chs_wait,
- .id = 2,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1767,10 +1554,13 @@ static struct clk i2chs2_fck = {
.recalc = &followparent_recalc,
};
+/*
+ * XXX This is marked as a 2420-only define, but it claims to be present
+ * on 2430 also. Double-check.
+ */
static struct clk i2c1_ick = {
- .name = "i2c_ick",
+ .name = "i2c1_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1778,21 +1568,9 @@ static struct clk i2c1_ick = {
.recalc = &followparent_recalc,
};
-static struct clk i2c1_fck = {
- .name = "i2c_fck",
- .ops = &clkops_omap2_dflt_wait,
- .id = 1,
- .parent = &func_12m_ck,
- .clkdm_name = "core_l4_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP2420_EN_I2C1_SHIFT,
- .recalc = &followparent_recalc,
-};
-
static struct clk i2chs1_fck = {
- .name = "i2c_fck",
+ .name = "i2chs1_fck",
.ops = &clkops_omap2430_i2chs_wait,
- .id = 1,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1825,58 +1603,6 @@ static struct clk sdma_ick = {
.recalc = &followparent_recalc,
};
-static struct clk vlynq_ick = {
- .name = "vlynq_ick",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &core_l3_ck,
- .clkdm_name = "core_l3_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
- .recalc = &followparent_recalc,
-};
-
-static const struct clksel_rate vlynq_fck_96m_rates[] = {
- { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
- { .div = 0 }
-};
-
-static const struct clksel_rate vlynq_fck_core_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_242X },
- { .div = 2, .val = 2, .flags = RATE_IN_242X },
- { .div = 3, .val = 3, .flags = RATE_IN_242X },
- { .div = 4, .val = 4, .flags = RATE_IN_242X },
- { .div = 6, .val = 6, .flags = RATE_IN_242X },
- { .div = 8, .val = 8, .flags = RATE_IN_242X },
- { .div = 9, .val = 9, .flags = RATE_IN_242X },
- { .div = 12, .val = 12, .flags = RATE_IN_242X },
- { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
- { .div = 18, .val = 18, .flags = RATE_IN_242X },
- { .div = 0 }
-};
-
-static const struct clksel vlynq_fck_clksel[] = {
- { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
- { .parent = &core_ck, .rates = vlynq_fck_core_rates },
- { .parent = NULL }
-};
-
-static struct clk vlynq_fck = {
- .name = "vlynq_fck",
- .ops = &clkops_omap2_dflt_wait,
- .parent = &func_96m_ck,
- .flags = DELAYED_APP,
- .clkdm_name = "core_l3_clkdm",
- .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
- .init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
- .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
- .clksel = vlynq_fck_clksel,
- .recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate
-};
-
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1959,7 +1685,7 @@ static struct clk usbhs_ick = {
};
static struct clk mmchs1_ick = {
- .name = "mmchs_ick",
+ .name = "mmchs1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
@@ -1969,7 +1695,7 @@ static struct clk mmchs1_ick = {
};
static struct clk mmchs1_fck = {
- .name = "mmchs_fck",
+ .name = "mmchs1_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &func_96m_ck,
.clkdm_name = "core_l3_clkdm",
@@ -1979,9 +1705,8 @@ static struct clk mmchs1_fck = {
};
static struct clk mmchs2_ick = {
- .name = "mmchs_ick",
+ .name = "mmchs2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1990,9 +1715,8 @@ static struct clk mmchs2_ick = {
};
static struct clk mmchs2_fck = {
- .name = "mmchs_fck",
+ .name = "mmchs2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &func_96m_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2030,7 +1754,7 @@ static struct clk mdm_intc_ick = {
};
static struct clk mmchsdb1_fck = {
- .name = "mmchsdb_fck",
+ .name = "mmchsdb1_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &func_32k_ck,
.clkdm_name = "core_l4_clkdm",
@@ -2040,9 +1764,8 @@ static struct clk mmchsdb1_fck = {
};
static struct clk mmchsdb2_fck = {
- .name = "mmchsdb_fck",
+ .name = "mmchsdb2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &func_32k_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2067,7 +1790,6 @@ static struct clk mmchsdb2_fck = {
static struct clk virt_prcm_set = {
.name = "virt_prcm_set",
.ops = &clkops_null,
- .flags = DELAYED_APP,
.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
.recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
.set_rate = &omap2_select_table_rate,
@@ -2079,149 +1801,134 @@ static struct clk virt_prcm_set = {
* clkdev integration
*/
-static struct omap_clk omap24xx_clks[] = {
+static struct omap_clk omap2430_clks[] = {
/* external root sources */
- CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
- CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
- CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
- CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
- CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
+ CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
+ CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
+ CLK(NULL, "osc_ck", &osc_ck, CK_243X),
+ CLK(NULL, "sys_ck", &sys_ck, CK_243X),
+ CLK(NULL, "alt_ck", &alt_ck, CK_243X),
/* internal analog sources */
- CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
- CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
- CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
+ CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
+ CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
+ CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
/* internal prcm root sources */
- CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
- CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
- CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
- CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
- CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
- CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
- CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
- CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
- CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
- CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
- CLK(NULL, "emul_ck", &emul_ck, CK_242X),
+ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
+ CLK(NULL, "core_ck", &core_ck, CK_243X),
+ CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
+ CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
+ CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
+ CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
+ CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
+ CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
+ CLK(NULL, "emul_ck", &emul_ck, CK_243X),
/* mpu domain clocks */
- CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
/* dsp domain clocks */
- CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
- CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
- CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
+ CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
- CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
- CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
/* GFX domain clocks */
- CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
- CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
- CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
+ CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
+ CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
+ CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
/* Modem domain clocks */
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
- CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
- CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
- CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
- CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
+ CLK("omapdss", "ick", &dss_ick, CK_243X),
+ CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X),
+ CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X),
+ CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X),
/* L3 domain clocks */
- CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
- CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
- CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
+ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
+ CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
+ CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
/* L4 domain clocks */
- CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
- CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
+ CLK(NULL, "l4_ck", &l4_ck, CK_243X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
/* virtual meta-group clock */
- CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
+ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
/* general l4 interface ck, multi-parent functional clk */
- CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
- CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
- CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
- CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
- CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
+ CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
+ CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
- CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
- CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
+ CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
+ CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
- CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
- CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
- CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
- CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
- CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
- CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
- CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
- CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
- CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
- CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
- CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
- CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
- CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
+ CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
+ CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
+ CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
+ CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
+ CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
- CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
- CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
- CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
- CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
- CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
- CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
- CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
- CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
- CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
- CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
- CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
- CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
- CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
- CLK(NULL, "eac_ick", &eac_ick, CK_242X),
- CLK(NULL, "eac_fck", &eac_fck, CK_242X),
- CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
- CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
- CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
- CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
+ CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
+ CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
+ CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
+ CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
+ CLK(NULL, "fac_ick", &fac_ick, CK_243X),
+ CLK(NULL, "fac_fck", &fac_fck, CK_243X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
+ CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
+ CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X),
CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
- CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
- CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
+ CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X),
CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
- CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
- CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
- CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
- CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
- CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
- CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
- CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
- CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
- CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
- CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
- CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
+ CLK(NULL, "des_ick", &des_ick, CK_243X),
+ CLK(NULL, "sha_ick", &sha_ick, CK_243X),
+ CLK("omap_rng", "ick", &rng_ick, CK_243X),
+ CLK(NULL, "aes_ick", &aes_ick, CK_243X),
+ CLK(NULL, "pka_ick", &pka_ick, CK_243X),
+ CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
@@ -2238,41 +1945,34 @@ static struct omap_clk omap24xx_clks[] = {
* init code
*/
-int __init omap2_clk_init(void)
+int __init omap2430_clk_init(void)
{
const struct prcm_config *prcm;
struct omap_clk *c;
u32 clkrate;
- u16 cpu_clkflg;
-
- if (cpu_is_omap242x()) {
- prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
- cpu_mask = RATE_IN_242X;
- cpu_clkflg = CK_242X;
- rate_table = omap2420_rate_table;
- } else if (cpu_is_omap2430()) {
- prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
- cpu_mask = RATE_IN_243X;
- cpu_clkflg = CK_243X;
- rate_table = omap2430_rate_table;
- }
+
+ prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
+ cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
+ cpu_mask = RATE_IN_243X;
+ rate_table = omap2430_rate_table;
clk_init(&omap2_clk_functions);
- for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+ for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
+ c++)
clk_preinit(c->lk.clk);
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
propagate_rate(&osc_ck);
- sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
+ sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
propagate_rate(&sys_ck);
- for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
- if (c->cpu & cpu_clkflg) {
- clkdev_add(&c->lk);
- clk_register(c->lk.clk);
- omap2_init_clk_clkdm(c->lk.clk);
- }
+ for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
+ c++) {
+ clkdev_add(&c->lk);
+ clk_register(c->lk.clk);
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
@@ -2288,10 +1988,9 @@ int __init omap2_clk_init(void)
recalculate_root_clocks();
- printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
- (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+ pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+ (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
/*
* Only enable those clocks we will need, let the drivers
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index d0e3fb7f929..80bb0f0e92e 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -1,15 +1,15 @@
/*
- * linux/arch/arm/mach-omap2/clock.c
+ * clock2xxx.c - OMAP2xxx-specific clock integration code
*
- * Copyright (C) 2005-2008 Texas Instruments, Inc.
- * Copyright (C) 2004-2008 Nokia Corporation
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
*
- * Contacts:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Paul Walmsley
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
*
- * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- * Gordon McNutt and RidgeRun, Inc.
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -17,529 +17,28 @@
*/
#undef DEBUG
-#include <linux/module.h>
#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
#include <linux/errno.h>
-#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
-#include <linux/cpufreq.h>
-#include <linux/bitops.h>
#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/prcm.h>
-#include <plat/clkdev_omap.h>
-#include <asm/div64.h>
-#include <asm/clkdev.h>
-#include <plat/sdrc.h>
#include "clock.h"
#include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
-
-/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
-#define EN_APLL_STOPPED 0
-#define EN_APLL_LOCKED 3
-
-/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
-#define APLLS_CLKIN_19_2MHZ 0
-#define APLLS_CLKIN_13MHZ 2
-#define APLLS_CLKIN_12MHZ 3
-
-/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
-
-const struct prcm_config *curr_prcm_set;
-const struct prcm_config *rate_table;
-
struct clk *vclk, *sclk, *dclk;
-void __iomem *prcm_clksrc_ctrl;
-
-/*-------------------------------------------------------------------------
- * Omap24xx specific clock functions
- *-------------------------------------------------------------------------*/
-
-/**
- * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
- * @clk: struct clk * being enabled
- * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
- * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
- *
- * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
- * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
- * passes back the correct CM_IDLEST register address for I2CHS
- * modules. No return value.
- */
-static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
- void __iomem **idlest_reg,
- u8 *idlest_bit)
-{
- *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
- *idlest_bit = clk->enable_bit;
-}
-
-/* 2430 I2CHS has non-standard IDLEST register */
-const struct clkops clkops_omap2430_i2chs_wait = {
- .enable = omap2_dflt_clk_enable,
- .disable = omap2_dflt_clk_disable,
- .find_idlest = omap2430_clk_i2chs_find_idlest,
- .find_companion = omap2_clk_dflt_find_companion,
-};
-
-/**
- * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
- *
- * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
- * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
- * (the latter is unusual). This currently should be called with
- * struct clk *dpll_ck, which is a composite clock of dpll_ck and
- * core_ck.
- */
-unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
-{
- long long core_clk;
- u32 v;
-
- core_clk = omap2_get_dpll_rate(clk);
-
- v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
- v &= OMAP24XX_CORE_CLK_SRC_MASK;
-
- if (v == CORE_CLK_SRC_32K)
- core_clk = 32768;
- else
- core_clk *= v;
-
- return core_clk;
-}
-
-static int omap2_enable_osc_ck(struct clk *clk)
-{
- u32 pcc;
-
- pcc = __raw_readl(prcm_clksrc_ctrl);
-
- __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-
- return 0;
-}
-
-static void omap2_disable_osc_ck(struct clk *clk)
-{
- u32 pcc;
-
- pcc = __raw_readl(prcm_clksrc_ctrl);
-
- __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-}
-
-const struct clkops clkops_oscck = {
- .enable = omap2_enable_osc_ck,
- .disable = omap2_disable_osc_ck,
-};
-
-#ifdef OLD_CK
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk *clk)
-{
- u32 div = PRCM_CLKSRC_CTRL;
- div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
- div >>= clk->rate_offset;
- clk->rate = (clk->parent->rate / div);
- propagate_rate(clk);
-}
-#endif /* OLD_CK */
-
-/* Enable an APLL if off */
-static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
-{
- u32 cval, apll_mask;
-
- apll_mask = EN_APLL_LOCKED << clk->enable_bit;
-
- cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-
- if ((cval & apll_mask) == apll_mask)
- return 0; /* apll already enabled */
-
- cval &= ~apll_mask;
- cval |= apll_mask;
- cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-
- omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
- clk->name);
-
- /*
- * REVISIT: Should we return an error code if omap2_wait_clock_ready()
- * fails?
- */
- return 0;
-}
-
-static int omap2_clk_apll96_enable(struct clk *clk)
-{
- return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
-}
-
-static int omap2_clk_apll54_enable(struct clk *clk)
-{
- return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
-}
-
-/* Stop APLL */
-static void omap2_clk_apll_disable(struct clk *clk)
-{
- u32 cval;
-
- cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
- cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
- cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-}
-
-const struct clkops clkops_apll96 = {
- .enable = omap2_clk_apll96_enable,
- .disable = omap2_clk_apll_disable,
-};
-
-const struct clkops clkops_apll54 = {
- .enable = omap2_clk_apll54_enable,
- .disable = omap2_clk_apll_disable,
-};
-
/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-long omap2_dpllcore_round_rate(unsigned long target_rate)
-{
- u32 high, low, core_clk_src;
-
- core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
- core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
-
- if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
- high = curr_prcm_set->dpll_speed * 2;
- low = curr_prcm_set->dpll_speed;
- } else { /* DPLL clockout x 2 */
- high = curr_prcm_set->dpll_speed;
- low = curr_prcm_set->dpll_speed / 2;
- }
-
-#ifdef DOWN_VARIABLE_DPLL
- if (target_rate > high)
- return high;
- else
- return target_rate;
-#else
- if (target_rate > low)
- return high;
- else
- return low;
-#endif
-
-}
-
-unsigned long omap2_dpllcore_recalc(struct clk *clk)
-{
- return omap2xxx_clk_get_core_rate(clk);
-}
-
-int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
-{
- u32 cur_rate, low, mult, div, valid_rate, done_rate;
- u32 bypass = 0;
- struct prcm_config tmpset;
- const struct dpll_data *dd;
-
- cur_rate = omap2xxx_clk_get_core_rate(dclk);
- mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
- mult &= OMAP24XX_CORE_CLK_SRC_MASK;
-
- if ((rate == (cur_rate / 2)) && (mult == 2)) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
- } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
- } else if (rate != cur_rate) {
- valid_rate = omap2_dpllcore_round_rate(rate);
- if (valid_rate != rate)
- return -EINVAL;
-
- if (mult == 1)
- low = curr_prcm_set->dpll_speed;
- else
- low = curr_prcm_set->dpll_speed / 2;
-
- dd = clk->dpll_data;
- if (!dd)
- return -EINVAL;
-
- tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
- tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
- dd->div1_mask);
- div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
- tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
- tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
- if (rate > low) {
- tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
- mult = ((rate / 2) / 1000000);
- done_rate = CORE_CLK_SRC_DPLL_X2;
- } else {
- tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
- mult = (rate / 1000000);
- done_rate = CORE_CLK_SRC_DPLL;
- }
- tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
- tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
-
- /* Worst case */
- tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
-
- if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
- bypass = 1;
-
- /* For omap2xxx_sdrc_init_params() */
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
- /* Force dll lock mode */
- omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
- bypass);
-
- /* Errata: ret dll entry state */
- omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
- omap2xxx_sdrc_reprogram(done_rate, 0);
- }
-
- return 0;
-}
-
-/**
- * omap2_table_mpu_recalc - just return the MPU speed
- * @clk: virt_prcm_set struct clk
- *
- * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
- */
-unsigned long omap2_table_mpu_recalc(struct clk *clk)
-{
- return curr_prcm_set->mpu_speed;
-}
-
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
- *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
- */
-long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
-{
- const struct prcm_config *ptr;
- long highest_rate;
- long sys_ck_rate;
-
- sys_ck_rate = clk_get_rate(sclk);
-
- highest_rate = -EINVAL;
-
- for (ptr = rate_table; ptr->mpu_speed; ptr++) {
- if (!(ptr->flags & cpu_mask))
- continue;
- if (ptr->xtal_speed != sys_ck_rate)
- continue;
-
- highest_rate = ptr->mpu_speed;
-
- /* Can check only after xtal frequency check */
- if (ptr->mpu_speed <= rate)
- break;
- }
- return highest_rate;
-}
-
-/* Sets basic clocks based on the specified rate */
-int omap2_select_table_rate(struct clk *clk, unsigned long rate)
-{
- u32 cur_rate, done_rate, bypass = 0, tmp;
- const struct prcm_config *prcm;
- unsigned long found_speed = 0;
- unsigned long flags;
- long sys_ck_rate;
-
- sys_ck_rate = clk_get_rate(sclk);
-
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
-
- if (prcm->xtal_speed != sys_ck_rate)
- continue;
-
- if (prcm->mpu_speed <= rate) {
- found_speed = prcm->mpu_speed;
- break;
- }
- }
-
- if (!found_speed) {
- printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
- rate / 1000000);
- return -EINVAL;
- }
-
- curr_prcm_set = prcm;
- cur_rate = omap2xxx_clk_get_core_rate(dclk);
-
- if (prcm->dpll_speed == cur_rate / 2) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
- } else if (prcm->dpll_speed == cur_rate * 2) {
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
- } else if (prcm->dpll_speed != cur_rate) {
- local_irq_save(flags);
-
- if (prcm->dpll_speed == prcm->xtal_speed)
- bypass = 1;
-
- if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
- CORE_CLK_SRC_DPLL_X2)
- done_rate = CORE_CLK_SRC_DPLL_X2;
- else
- done_rate = CORE_CLK_SRC_DPLL;
-
- /* MPU divider */
- cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
-
- /* dsp + iva1 div(2420), iva2.1(2430) */
- cm_write_mod_reg(prcm->cm_clksel_dsp,
- OMAP24XX_DSP_MOD, CM_CLKSEL);
-
- cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
-
- /* Major subsystem dividers */
- tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
- cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
- CM_CLKSEL1);
-
- if (cpu_is_omap2430())
- cm_write_mod_reg(prcm->cm_clksel_mdm,
- OMAP2430_MDM_MOD, CM_CLKSEL);
-
- /* x2 to enter omap2xxx_sdrc_init_params() */
- omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
- omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
- bypass);
-
- omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
- omap2xxx_sdrc_reprogram(done_rate, 0);
-
- local_irq_restore(flags);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_CPU_FREQ
-/*
- * Walk PRCM rate table and fillout cpufreq freq_table
+ * Omap24xx specific clock functions
*/
-static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
-
-void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
-{
- struct prcm_config *prcm;
- int i = 0;
-
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
- if (prcm->xtal_speed != sys_ck.rate)
- continue;
-
- /* don't put bypass rates in table */
- if (prcm->dpll_speed == prcm->xtal_speed)
- continue;
-
- freq_table[i].index = i;
- freq_table[i].frequency = prcm->mpu_speed / 1000;
- i++;
- }
-
- if (i == 0) {
- printk(KERN_WARNING "%s: failed to initialize frequency "
- "table\n", __func__);
- return;
- }
-
- freq_table[i].index = i;
- freq_table[i].frequency = CPUFREQ_TABLE_END;
-
- *table = &freq_table[0];
-}
-#endif
-
-struct clk_functions omap2_clk_functions = {
- .clk_enable = omap2_clk_enable,
- .clk_disable = omap2_clk_disable,
- .clk_round_rate = omap2_clk_round_rate,
- .clk_set_rate = omap2_clk_set_rate,
- .clk_set_parent = omap2_clk_set_parent,
- .clk_disable_unused = omap2_clk_disable_unused,
-#ifdef CONFIG_CPU_FREQ
- .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
-#endif
-};
-
-static u32 omap2_get_apll_clkin(void)
-{
- u32 aplls, srate = 0;
-
- aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
- aplls &= OMAP24XX_APLLS_CLKIN_MASK;
- aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
-
- if (aplls == APLLS_CLKIN_19_2MHZ)
- srate = 19200000;
- else if (aplls == APLLS_CLKIN_13MHZ)
- srate = 13000000;
- else if (aplls == APLLS_CLKIN_12MHZ)
- srate = 12000000;
-
- return srate;
-}
-
-static u32 omap2_get_sysclkdiv(void)
-{
- u32 div;
-
- div = __raw_readl(prcm_clksrc_ctrl);
- div &= OMAP_SYSCLKDIV_MASK;
- div >>= OMAP_SYSCLKDIV_SHIFT;
-
- return div;
-}
-
-unsigned long omap2_osc_clk_recalc(struct clk *clk)
-{
- return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
-}
-
-unsigned long omap2_sys_clk_recalc(struct clk *clk)
-{
- return clk->parent->rate / omap2_get_sysclkdiv();
-}
/*
* Set clocks for bypass mode for reboot to work.
*/
-void omap2_clk_prepare_for_reboot(void)
+void omap2xxx_clk_prepare_for_reboot(void)
{
u32 rate;
@@ -551,37 +50,24 @@ void omap2_clk_prepare_for_reboot(void)
}
/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
+ * Switch the MPU rate if specified on cmdline. We cannot do this
+ * early until cmdline is parsed. XXX This should be removed from the
+ * clock code and handled by the OPP layer code in the near future.
*/
-static int __init omap2_clk_arch_init(void)
+static int __init omap2xxx_clk_arch_init(void)
{
- struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
- unsigned long sys_ck_rate;
-
- if (!mpurate)
- return -EINVAL;
+ int ret;
- virt_prcm_set = clk_get(NULL, "virt_prcm_set");
- sys_ck = clk_get(NULL, "sys_ck");
- dpll_ck = clk_get(NULL, "dpll_ck");
- mpu_ck = clk_get(NULL, "mpu_ck");
+ if (!cpu_is_omap24xx())
+ return 0;
- if (clk_set_rate(virt_prcm_set, mpurate))
- printk(KERN_ERR "Could not find matching MPU rate\n");
+ ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set");
+ if (!ret)
+ omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck");
- recalculate_root_clocks();
-
- sys_ck_rate = clk_get_rate(sys_ck);
-
- pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
- (clk_get_rate(dpll_ck) / 1000000),
- (clk_get_rate(mpu_ck) / 1000000));
-
- return 0;
+ return ret;
}
-arch_initcall(omap2_clk_arch_init);
+
+arch_initcall(omap2xxx_clk_arch_init);
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index e35efde4bd8..6a658b890c1 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -1,35 +1,38 @@
/*
* OMAP2 clock function prototypes and macros
*
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
+ * Copyright (C) 2005-2010 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
*/
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
unsigned long omap2_table_mpu_recalc(struct clk *clk);
int omap2_select_table_rate(struct clk *clk, unsigned long rate);
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-unsigned long omap2_sys_clk_recalc(struct clk *clk);
+unsigned long omap2xxx_sys_clk_recalc(struct clk *clk);
unsigned long omap2_osc_clk_recalc(struct clk *clk);
-unsigned long omap2_sys_clk_recalc(struct clk *clk);
unsigned long omap2_dpllcore_recalc(struct clk *clk);
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
+u32 omap2xxx_get_apll_clkin(void);
+u32 omap2xxx_get_sysclkdiv(void);
+void omap2xxx_clk_prepare_for_reboot(void);
-/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
#ifdef CONFIG_ARCH_OMAP2420
-#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
-#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
-#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
+int omap2420_clk_init(void);
#else
-#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
-#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
-#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
+#define omap2420_clk_init() 0
#endif
-extern void __iomem *prcm_clksrc_ctrl;
+#ifdef CONFIG_ARCH_OMAP2430
+int omap2430_clk_init(void);
+#else
+#define omap2430_clk_init() 0
+#endif
+
+extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;
extern struct clk *dclk;
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index ded32364f32..6febd5f11e8 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,13 +2,14 @@
* OMAP3-specific clock framework functions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2010 Nokia Corporation
*
- * Written by Paul Walmsley
- * Testing and integration fixes by Jouni Högander
+ * Paul Walmsley
+ * Jouni Högander
*
* Parts of this code are based on code written by
- * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
+ * Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -16,50 +17,23 @@
*/
#undef DEBUG
-#include <linux/module.h>
#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
-#include <linux/limits.h>
-#include <linux/bitops.h>
-#include <plat/cpu.h>
#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-#include <asm/div64.h>
-#include <asm/clkdev.h>
-#include <plat/sdrc.h>
#include "clock.h"
#include "clock34xx.h"
-#include "sdrc.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm-regbits-34xx.h"
-#define CYCLES_PER_MHZ 1000000
-
-/*
- * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
- * that are sourced by DPLL5, and both of these require this clock
- * to be at 120 MHz for proper operation.
- */
-#define DPLL5_FREQ_FOR_USBHOST 120000000
-
-/* needed by omap3_core_dpll_m2_set_rate() */
-struct clk *sdrc_ick_p, *arm_fck_p;
-
/**
* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
* from the CM_{I,F}CLKEN bit. Pass back the correct info via
@@ -67,13 +41,15 @@ struct clk *sdrc_ick_p, *arm_fck_p;
*/
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
- u8 *idlest_bit)
+ u8 *idlest_bit,
+ u8 *idlest_val)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
+ *idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clkops clkops_omap3430es2_ssi_wait = {
@@ -88,6 +64,7 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
* target IDLEST bits. For our purposes, we are concerned with the
@@ -98,7 +75,8 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
*/
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
- u8 *idlest_bit)
+ u8 *idlest_bit,
+ u8 *idlest_val)
{
u32 r;
@@ -106,6 +84,7 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
*idlest_reg = (__force void __iomem *)r;
/* USBHOST_IDLE has same shift */
*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
+ *idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
@@ -120,6 +99,7 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
@@ -127,13 +107,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
*/
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
- u8 *idlest_bit)
+ u8 *idlest_bit,
+ u8 *idlest_val)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
+ *idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clkops clkops_omap3430es2_hsotgusb_wait = {
@@ -142,213 +124,3 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
-
-const struct clkops clkops_noncore_dpll_ops = {
- .enable = omap3_noncore_dpll_enable,
- .disable = omap3_noncore_dpll_disable,
-};
-
-int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
-{
- /*
- * According to the 12-5 CDP code from TI, "Limitation 2.5"
- * on 3430ES1 prevents us from changing DPLL multipliers or dividers
- * on DPLL4.
- */
- if (omap_rev() == OMAP3430_REV_ES1_0) {
- printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
- "silicon 'Limitation 2.5' on 3430ES1.\n");
- return -EINVAL;
- }
- return omap3_noncore_dpll_set_rate(clk, rate);
-}
-
-
-/*
- * CORE DPLL (DPLL3) rate programming functions
- *
- * These call into SRAM code to do the actual CM writes, since the SDRAM
- * is clocked from DPLL3.
- */
-
-/**
- * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
- * @clk: struct clk * of DPLL to set
- * @rate: rounded target rate
- *
- * Program the DPLL M2 divider with the rounded target rate. Returns
- * -EINVAL upon error, or 0 upon success.
- */
-int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 new_div = 0;
- u32 unlock_dll = 0;
- u32 c;
- unsigned long validrate, sdrcrate, _mpurate;
- struct omap_sdrc_params *sdrc_cs0;
- struct omap_sdrc_params *sdrc_cs1;
- int ret;
-
- if (!clk || !rate)
- return -EINVAL;
-
- validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
- if (validrate != rate)
- return -EINVAL;
-
- sdrcrate = sdrc_ick_p->rate;
- if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) >> 1);
- else
- sdrcrate >>= ((clk->rate / rate) >> 1);
-
- ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
- if (ret)
- return -EINVAL;
-
- if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
- pr_debug("clock: will unlock SDRC DLL\n");
- unlock_dll = 1;
- }
-
- /*
- * XXX This only needs to be done when the CPU frequency changes
- */
- _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
- c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
- c += 1; /* for safety */
- c *= SDRC_MPURATE_LOOPS;
- c >>= SDRC_MPURATE_SCALE;
- if (c == 0)
- c = 1;
-
- pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
- pr_debug("clock: SDRC CS0 timing params used:"
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
- sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
- sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
- if (sdrc_cs1)
- pr_debug("clock: SDRC CS1 timing params used: "
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
- sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
- sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
-
- if (sdrc_cs1)
- omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
- sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
- sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
- sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
- sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
- else
- omap3_configure_core_dpll(
- new_div, unlock_dll, c, rate > clk->rate,
- sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
- sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
- 0, 0, 0, 0);
-
- return 0;
-}
-
-/* Common clock code */
-
-/*
- * As it is structured now, this will prevent an OMAP2/3 multiboot
- * kernel from compiling. This will need further attention.
- */
-#if defined(CONFIG_ARCH_OMAP3)
-
-struct clk_functions omap2_clk_functions = {
- .clk_enable = omap2_clk_enable,
- .clk_disable = omap2_clk_disable,
- .clk_round_rate = omap2_clk_round_rate,
- .clk_set_rate = omap2_clk_set_rate,
- .clk_set_parent = omap2_clk_set_parent,
- .clk_disable_unused = omap2_clk_disable_unused,
-};
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
- /* REVISIT: Not ready for 343x */
-#if 0
- u32 rate;
-
- if (vclk == NULL || sclk == NULL)
- return;
-
- rate = clk_get_rate(sclk);
- clk_set_rate(vclk, rate);
-#endif
-}
-
-void omap3_clk_lock_dpll5(void)
-{
- struct clk *dpll5_clk;
- struct clk *dpll5_m2_clk;
-
- dpll5_clk = clk_get(NULL, "dpll5_ck");
- clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
- clk_enable(dpll5_clk);
-
- /* Enable autoidle to allow it to enter low power bypass */
- omap3_dpll_allow_idle(dpll5_clk);
-
- /* Program dpll5_m2_clk divider for no division */
- dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
- clk_enable(dpll5_m2_clk);
- clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
-
- clk_disable(dpll5_m2_clk);
- clk_disable(dpll5_clk);
- return;
-}
-
-/* REVISIT: Move this init stuff out into clock.c */
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
- struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
- unsigned long osc_sys_rate;
-
- if (!mpurate)
- return -EINVAL;
-
- /* XXX test these for success */
- dpll1_ck = clk_get(NULL, "dpll1_ck");
- arm_fck = clk_get(NULL, "arm_fck");
- core_ck = clk_get(NULL, "core_ck");
- osc_sys_ck = clk_get(NULL, "osc_sys_ck");
-
- /* REVISIT: not yet ready for 343x */
- if (clk_set_rate(dpll1_ck, mpurate))
- printk(KERN_ERR "*** Unable to set MPU rate\n");
-
- recalculate_root_clocks();
-
- osc_sys_rate = clk_get_rate(osc_sys_ck);
-
- pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (osc_sys_rate / 1000000),
- ((osc_sys_rate / 100000) % 10),
- (clk_get_rate(core_ck) / 1000000),
- (clk_get_rate(arm_fck) / 1000000));
-
- calibrate_delay();
-
- return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-
-#endif
-
-
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9a2c07eac9a..628e8de5768 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,24 +1,15 @@
/*
- * OMAP3 clock function prototypes and macros
+ * OMAP34xx clock function prototypes and macros
*
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
*/
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
-int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
-int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
-void omap3_clk_lock_dpll5(void);
-
-extern struct clk *sdrc_ick_p;
-extern struct clk *arm_fck_p;
-
-/* OMAP34xx-specific clkops */
extern const struct clkops clkops_omap3430es2_ssi_wait;
extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
-extern const struct clkops clkops_noncore_dpll_ops;
#endif
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
new file mode 100644
index 00000000000..b496a9305e1
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -0,0 +1,124 @@
+/*
+ * OMAP3517/3505-specific clock framework functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Ranjith Lohithakshan
+ * Paul Walmsley
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
+ * Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock3517.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/*
+ * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
+ * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
+ * at an offset of 4 from ICK enable bit.
+ */
+#define AM35XX_IPSS_ICK_MASK 0xF
+#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
+#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
+#define AM35XX_IPSS_CLK_IDLEST_VAL 0
+
+/**
+ * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
+ *
+ * The interface clocks on AM35xx IPSS reflects the clock idle status
+ * in the enable register itsel at a bit offset of 4 from the enable
+ * bit. A value of 1 indicates that clock is enabled.
+ */
+static void am35xx_clk_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit,
+ u8 *idlest_val)
+{
+ *idlest_reg = (__force void __iomem *)(clk->enable_reg);
+ *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
+ *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
+}
+
+/**
+ * am35xx_clk_find_companion - find companion clock to @clk
+ * @clk: struct clk * to find the companion clock of
+ * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
+ * @other_bit: u8 ** to return the companion clock bit shift in
+ *
+ * Some clocks don't have companion clocks. For example, modules with
+ * only an interface clock (such as HECC) don't have a companion
+ * clock. Right now, this code relies on the hardware exporting a bit
+ * in the correct companion register that indicates that the
+ * nonexistent 'companion clock' is active. Future patches will
+ * associate this type of code with per-module data structures to
+ * avoid this issue, and remove the casts. No return value.
+ */
+static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,
+ u8 *other_bit)
+{
+ *other_reg = (__force void __iomem *)(clk->enable_reg);
+ if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
+ *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
+ else
+ *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
+}
+
+const struct clkops clkops_am35xx_ipss_module_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = am35xx_clk_find_idlest,
+ .find_companion = am35xx_clk_find_companion,
+};
+
+/**
+ * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
+ *
+ * The IPSS target CM_IDLEST bit is at a different shift from the
+ * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
+ * and @idlest_bit. No return value.
+ */
+static void am35xx_clk_ipss_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit,
+ u8 *idlest_val)
+{
+ u32 r;
+
+ r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+ *idlest_reg = (__force void __iomem *)r;
+ *idlest_bit = AM35XX_ST_IPSS_SHIFT;
+ *idlest_val = OMAP34XX_CM_IDLEST_VAL;
+}
+
+const struct clkops clkops_am35xx_ipss_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = am35xx_clk_ipss_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
+
+
diff --git a/arch/arm/mach-omap2/clock3517.h b/arch/arm/mach-omap2/clock3517.h
new file mode 100644
index 00000000000..ca5e5a64c2e
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3517.h
@@ -0,0 +1,14 @@
+/*
+ * OMAP3517/3505 clock function prototypes and macros
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3517_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK3517_H
+
+extern const struct clkops clkops_am35xx_ipss_module_wait;
+extern const struct clkops clkops_am35xx_ipss_wait;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
new file mode 100644
index 00000000000..0c5e25ed887
--- /dev/null
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -0,0 +1,72 @@
+/*
+ * OMAP36xx-specific clkops
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Mike Turquette
+ * Vijaykumar GN
+ * Paul Walmsley
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
+ * Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock36xx.h"
+
+
+/**
+ * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
+ * from HSDivider PWRDN problem Implements Errata ID: i556.
+ * @clk: DPLL output struct clk
+ *
+ * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
+ * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
+ * valueafter their respective PWRDN bits are set. Any dummy write
+ * (Any other value different from the Read value) to the
+ * corresponding CM_CLKSEL register will refresh the dividers.
+ */
+static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
+{
+ u32 dummy_v, orig_v, clksel_shift;
+ int ret;
+
+ /* Clear PWRDN bit of HSDIVIDER */
+ ret = omap2_dflt_clk_enable(clk);
+
+ /* Restore the dividers */
+ if (!ret) {
+ clksel_shift = __ffs(clk->parent->clksel_mask);
+ orig_v = __raw_readl(clk->parent->clksel_reg);
+ dummy_v = orig_v;
+
+ /* Write any other value different from the Read value */
+ dummy_v ^= (1 << clksel_shift);
+ __raw_writel(dummy_v, clk->parent->clksel_reg);
+
+ /* Write the original divider */
+ __raw_writel(orig_v, clk->parent->clksel_reg);
+ }
+
+ return ret;
+}
+
+const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
+ .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
+ .disable = omap2_dflt_clk_disable,
+ .find_companion = omap2_clk_dflt_find_companion,
+ .find_idlest = omap2_clk_dflt_find_idlest,
+};
diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h
new file mode 100644
index 00000000000..a7dee5bc636
--- /dev/null
+++ b/arch/arm/mach-omap2/clock36xx.h
@@ -0,0 +1,13 @@
+/*
+ * OMAP36xx clock function prototypes and macros
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H
+
+extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
new file mode 100644
index 00000000000..a447c4d2c28
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -0,0 +1,104 @@
+/*
+ * OMAP3-specific clock framework functions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Jouni Högander
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock3xxx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/*
+ * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
+ * that are sourced by DPLL5, and both of these require this clock
+ * to be at 120 MHz for proper operation.
+ */
+#define DPLL5_FREQ_FOR_USBHOST 120000000
+
+/* needed by omap3_core_dpll_m2_set_rate() */
+struct clk *sdrc_ick_p, *arm_fck_p;
+
+int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
+{
+ /*
+ * According to the 12-5 CDP code from TI, "Limitation 2.5"
+ * on 3430ES1 prevents us from changing DPLL multipliers or dividers
+ * on DPLL4.
+ */
+ if (omap_rev() == OMAP3430_REV_ES1_0) {
+ pr_err("clock: DPLL4 cannot change rate due to "
+ "silicon 'Limitation 2.5' on 3430ES1.\n");
+ return -EINVAL;
+ }
+
+ return omap3_noncore_dpll_set_rate(clk, rate);
+}
+
+void __init omap3_clk_lock_dpll5(void)
+{
+ struct clk *dpll5_clk;
+ struct clk *dpll5_m2_clk;
+
+ dpll5_clk = clk_get(NULL, "dpll5_ck");
+ clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
+ clk_enable(dpll5_clk);
+
+ /* Enable autoidle to allow it to enter low power bypass */
+ omap3_dpll_allow_idle(dpll5_clk);
+
+ /* Program dpll5_m2_clk divider for no division */
+ dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
+ clk_enable(dpll5_m2_clk);
+ clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
+
+ clk_disable(dpll5_m2_clk);
+ clk_disable(dpll5_clk);
+ return;
+}
+
+/* Common clock code */
+
+/*
+ * Switch the MPU rate if specified on cmdline. We cannot do this
+ * early until cmdline is parsed. XXX This should be removed from the
+ * clock code and handled by the OPP layer code in the near future.
+ */
+static int __init omap3xxx_clk_arch_init(void)
+{
+ int ret;
+
+ if (!cpu_is_omap34xx())
+ return 0;
+
+ ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
+ if (!ret)
+ omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck");
+
+ return ret;
+}
+
+arch_initcall(omap3xxx_clk_arch_init);
+
+
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
new file mode 100644
index 00000000000..8bbeeaf399e
--- /dev/null
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -0,0 +1,21 @@
+/*
+ * OMAP3-common clock function prototypes and macros
+ *
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
+
+int omap3xxx_clk_init(void);
+int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
+void omap3_clk_lock_dpll5(void);
+
+extern struct clk *sdrc_ick_p;
+extern struct clk *arm_fck_p;
+
+extern const struct clkops clkops_noncore_dpll_ops;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 8bdcc9cc7f9..9cba5560519 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1,8 +1,8 @@
/*
* OMAP3 clock data
*
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
*
* Written by Paul Walmsley
* With many device clock fixes by Kevin Hilman and Jouni Högander
@@ -16,15 +16,19 @@
* to be requested from drivers directly.
*/
-#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/clk.h>
+#include <linux/list.h>
#include <plat/control.h>
#include <plat/clkdev_omap.h>
#include "clock.h"
+#include "clock3xxx.h"
#include "clock34xx.h"
+#include "clock36xx.h"
+#include "clock3517.h"
+
#include "cm.h"
#include "cm-regbits-34xx.h"
#include "prm.h"
@@ -37,7 +41,8 @@
#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
/* Maximum DPLL multiplier, divider values for OMAP3 */
-#define OMAP3_MAX_DPLL_MULT 2048
+#define OMAP3_MAX_DPLL_MULT 2047
+#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
#define OMAP3_MAX_DPLL_DIV 128
/*
@@ -59,14 +64,12 @@ static struct clk omap_32k_fck = {
.name = "omap_32k_fck",
.ops = &clkops_null,
.rate = 32768,
- .flags = RATE_FIXED,
};
static struct clk secure_32k_fck = {
.name = "secure_32k_fck",
.ops = &clkops_null,
.rate = 32768,
- .flags = RATE_FIXED,
};
/* Virtual source clocks for osc_sys_ck */
@@ -74,42 +77,36 @@ static struct clk virt_12m_ck = {
.name = "virt_12m_ck",
.ops = &clkops_null,
.rate = 12000000,
- .flags = RATE_FIXED,
};
static struct clk virt_13m_ck = {
.name = "virt_13m_ck",
.ops = &clkops_null,
.rate = 13000000,
- .flags = RATE_FIXED,
};
static struct clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
.ops = &clkops_null,
.rate = 16800000,
- .flags = RATE_FIXED,
};
static struct clk virt_19_2m_ck = {
.name = "virt_19_2m_ck",
.ops = &clkops_null,
.rate = 19200000,
- .flags = RATE_FIXED,
};
static struct clk virt_26m_ck = {
.name = "virt_26m_ck",
.ops = &clkops_null,
.rate = 26000000,
- .flags = RATE_FIXED,
};
static struct clk virt_38_4m_ck = {
.name = "virt_38_4m_ck",
.ops = &clkops_null,
.rate = 38400000,
- .flags = RATE_FIXED,
};
static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -162,7 +159,6 @@ static struct clk osc_sys_ck = {
.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
.clksel = osc_sys_clksel,
/* REVISIT: deal with autoextclkmode? */
- .flags = RATE_FIXED,
.recalc = &omap2_clksel_recalc,
};
@@ -236,6 +232,42 @@ static const struct clksel_rate div16_dpll_rates[] = {
{ .div = 0 }
};
+static const struct clksel_rate div32_dpll4_rates_3630[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_36XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_36XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_36XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_36XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_36XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_36XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_36XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_36XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_36XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_36XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_36XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_36XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_36XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_36XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_36XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_36XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_36XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_36XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_36XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_36XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_36XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_36XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_36XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_36XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_36XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_36XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_36XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_36XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_36XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_36XX },
+ { .div = 32, .val = 32, .flags = RATE_IN_36XX },
+ { .div = 0 }
+};
+
/* DPLL1 */
/* MPU clock source */
/* Type: DPLL */
@@ -337,7 +369,7 @@ static struct dpll_data dpll2_dd = {
static struct clk dpll2_ck = {
.name = "dpll2_ck",
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll2_dd,
.round_rate = &omap2_dpll_round_rate,
@@ -529,7 +561,8 @@ static struct clk emu_core_alwon_ck = {
/* DPLL4 */
/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
/* Type: DPLL */
-static struct dpll_data dpll4_dd = {
+static struct dpll_data dpll4_dd;
+static struct dpll_data dpll4_dd_34xx __initdata = {
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
.mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
.div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
@@ -552,9 +585,32 @@ static struct dpll_data dpll4_dd = {
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
};
+static struct dpll_data dpll4_dd_3630 __initdata = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+ .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
+ .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+ .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+ .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+ .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+ .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
+ .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+ .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
+ .flags = DPLL_J_TYPE
+};
+
static struct clk dpll4_ck = {
.name = "dpll4_ck",
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll4_dd,
.round_rate = &omap2_dpll_round_rate,
@@ -581,8 +637,15 @@ static const struct clksel div16_dpll4_clksel[] = {
{ .parent = NULL }
};
+static const struct clksel div32_dpll4_clksel[] = {
+ { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
+ { .parent = NULL }
+};
+
/* This virtual clock is the source for dpll4_m2x2_ck */
-static struct clk dpll4_m2_ck = {
+static struct clk dpll4_m2_ck;
+
+static struct clk dpll4_m2_ck_34xx __initdata = {
.name = "dpll4_m2_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
@@ -594,6 +657,18 @@ static struct clk dpll4_m2_ck = {
.recalc = &omap2_clksel_recalc,
};
+static struct clk dpll4_m2_ck_3630 __initdata = {
+ .name = "dpll4_m2_ck",
+ .ops = &clkops_null,
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+ .clksel_mask = OMAP3630_DIV_96M_MASK,
+ .clksel = div32_dpll4_clksel,
+ .clkdm_name = "dpll4_clkdm",
+ .recalc = &omap2_clksel_recalc,
+};
+
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m2x2_ck = {
.name = "dpll4_m2x2_ck",
@@ -612,18 +687,24 @@ static struct clk dpll4_m2x2_ck = {
* 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
* CM_96K_(F)CLK.
*/
-static struct clk omap_96m_alwon_fck = {
- .name = "omap_96m_alwon_fck",
+
+/* Adding 192MHz Clock node needed by SGX */
+static struct clk omap_192m_alwon_fck = {
+ .name = "omap_192m_alwon_fck",
.ops = &clkops_null,
.parent = &dpll4_m2x2_ck,
.recalc = &followparent_recalc,
};
-static struct clk cm_96m_fck = {
- .name = "cm_96m_fck",
- .ops = &clkops_null,
- .parent = &omap_96m_alwon_fck,
- .recalc = &followparent_recalc,
+static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_36XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+ { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
+ { .parent = NULL }
};
static const struct clksel_rate omap_96m_dpll_rates[] = {
@@ -636,6 +717,31 @@ static const struct clksel_rate omap_96m_sys_rates[] = {
{ .div = 0 }
};
+static struct clk omap_96m_alwon_fck = {
+ .name = "omap_96m_alwon_fck",
+ .ops = &clkops_null,
+ .parent = &dpll4_m2x2_ck,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk omap_96m_alwon_fck_3630 = {
+ .name = "omap_96m_alwon_fck",
+ .parent = &omap_192m_alwon_fck,
+ .init = &omap2_init_clksel_parent,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
+ .clksel = omap_96m_alwon_fck_clksel
+};
+
+static struct clk cm_96m_fck = {
+ .name = "cm_96m_fck",
+ .ops = &clkops_null,
+ .parent = &omap_96m_alwon_fck,
+ .recalc = &followparent_recalc,
+};
+
static const struct clksel omap_96m_fck_clksel[] = {
{ .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
{ .parent = &sys_ck, .rates = omap_96m_sys_rates },
@@ -654,7 +760,9 @@ static struct clk omap_96m_fck = {
};
/* This virtual clock is the source for dpll4_m3x2_ck */
-static struct clk dpll4_m3_ck = {
+static struct clk dpll4_m3_ck;
+
+static struct clk dpll4_m3_ck_34xx __initdata = {
.name = "dpll4_m3_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
@@ -666,12 +774,23 @@ static struct clk dpll4_m3_ck = {
.recalc = &omap2_clksel_recalc,
};
+static struct clk dpll4_m3_ck_3630 __initdata = {
+ .name = "dpll4_m3_ck",
+ .ops = &clkops_null,
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
+ .clksel = div32_dpll4_clksel,
+ .clkdm_name = "dpll4_clkdm",
+ .recalc = &omap2_clksel_recalc,
+};
+
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m3_ck,
- .init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = INVERT_ENABLE,
@@ -736,11 +855,13 @@ static struct clk omap_12m_fck = {
.ops = &clkops_null,
.parent = &omap_48m_fck,
.fixed_div = 4,
- .recalc = &omap2_fixed_divisor_recalc,
+ .recalc = &omap_fixed_divisor_recalc,
};
/* This virstual clock is the source for dpll4_m4x2_ck */
-static struct clk dpll4_m4_ck = {
+static struct clk dpll4_m4_ck;
+
+static struct clk dpll4_m4_ck_34xx __initdata = {
.name = "dpll4_m4_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
@@ -754,20 +875,36 @@ static struct clk dpll4_m4_ck = {
.round_rate = &omap2_clksel_round_rate,
};
+static struct clk dpll4_m4_ck_3630 __initdata = {
+ .name = "dpll4_m4_ck",
+ .ops = &clkops_null,
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
+ .clksel = div32_dpll4_clksel,
+ .clkdm_name = "dpll4_clkdm",
+ .recalc = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m4x2_ck = {
.name = "dpll4_m4x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m4_ck,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
- .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
.flags = INVERT_ENABLE,
.clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
/* This virtual clock is the source for dpll4_m5x2_ck */
-static struct clk dpll4_m5_ck = {
+static struct clk dpll4_m5_ck;
+
+static struct clk dpll4_m5_ck_34xx __initdata = {
.name = "dpll4_m5_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
@@ -776,6 +913,22 @@ static struct clk dpll4_m5_ck = {
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
.clksel = div16_dpll4_clksel,
.clkdm_name = "dpll4_clkdm",
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk dpll4_m5_ck_3630 __initdata = {
+ .name = "dpll4_m5_ck",
+ .ops = &clkops_null,
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
+ .clksel = div32_dpll4_clksel,
+ .clkdm_name = "dpll4_clkdm",
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate,
.recalc = &omap2_clksel_recalc,
};
@@ -792,7 +945,9 @@ static struct clk dpll4_m5x2_ck = {
};
/* This virtual clock is the source for dpll4_m6x2_ck */
-static struct clk dpll4_m6_ck = {
+static struct clk dpll4_m6_ck;
+
+static struct clk dpll4_m6_ck_34xx __initdata = {
.name = "dpll4_m6_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
@@ -804,12 +959,23 @@ static struct clk dpll4_m6_ck = {
.recalc = &omap2_clksel_recalc,
};
+static struct clk dpll4_m6_ck_3630 __initdata = {
+ .name = "dpll4_m6_ck",
+ .ops = &clkops_null,
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
+ .clksel = div32_dpll4_clksel,
+ .clkdm_name = "dpll4_clkdm",
+ .recalc = &omap2_clksel_recalc,
+};
+
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m6_ck,
- .init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = INVERT_ENABLE,
@@ -854,7 +1020,7 @@ static struct dpll_data dpll5_dd = {
static struct clk dpll5_ck = {
.name = "dpll5_ck",
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll5_dd,
.round_rate = &omap2_dpll_round_rate,
@@ -1045,7 +1211,6 @@ static struct clk iva2_ck = {
.name = "iva2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll2_m2_ck,
- .init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.clkdm_name = "iva2_clkdm",
@@ -1119,7 +1284,6 @@ static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &l3_ick,
- .init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &followparent_recalc,
@@ -1168,12 +1332,24 @@ static struct clk gfx_cg2_ck = {
/* SGX power domain - 3430ES2 only */
static const struct clksel_rate sgx_core_rates[] = {
+ { .div = 2, .val = 5, .flags = RATE_IN_36XX },
{ .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
{ .div = 4, .val = 1, .flags = RATE_IN_343X },
{ .div = 6, .val = 2, .flags = RATE_IN_343X },
{ .div = 0 },
};
+static const struct clksel_rate sgx_192m_rates[] = {
+ { .div = 1, .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate sgx_corex2_rates[] = {
+ { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
+ { .div = 5, .val = 7, .flags = RATE_IN_36XX },
+ { .div = 0 },
+};
+
static const struct clksel_rate sgx_96m_rates[] = {
{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 },
@@ -1182,7 +1358,9 @@ static const struct clksel_rate sgx_96m_rates[] = {
static const struct clksel sgx_clksel[] = {
{ .parent = &core_ck, .rates = sgx_core_rates },
{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
- { .parent = NULL },
+ { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
+ { .parent = &corex2_fck, .rates = sgx_corex2_rates },
+ { .parent = NULL }
};
static struct clk sgx_fck = {
@@ -1196,6 +1374,8 @@ static struct clk sgx_fck = {
.clksel = sgx_clksel,
.clkdm_name = "sgx_clkdm",
.recalc = &omap2_clksel_recalc,
+ .set_rate = &omap2_clksel_set_rate,
+ .round_rate = &omap2_clksel_round_rate
};
static struct clk sgx_ick = {
@@ -1322,9 +1502,8 @@ static struct clk core_96m_fck = {
};
static struct clk mmchs3_fck = {
- .name = "mmchs_fck",
+ .name = "mmchs3_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1333,9 +1512,8 @@ static struct clk mmchs3_fck = {
};
static struct clk mmchs2_fck = {
- .name = "mmchs_fck",
+ .name = "mmchs2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1354,7 +1532,7 @@ static struct clk mspro_fck = {
};
static struct clk mmchs1_fck = {
- .name = "mmchs_fck",
+ .name = "mmchs1_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1364,9 +1542,8 @@ static struct clk mmchs1_fck = {
};
static struct clk i2c3_fck = {
- .name = "i2c_fck",
+ .name = "i2c3_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1375,9 +1552,8 @@ static struct clk i2c3_fck = {
};
static struct clk i2c2_fck = {
- .name = "i2c_fck",
+ .name = "i2c2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1386,9 +1562,8 @@ static struct clk i2c2_fck = {
};
static struct clk i2c1_fck = {
- .name = "i2c_fck",
+ .name = "i2c1_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1417,9 +1592,8 @@ static const struct clksel mcbsp_15_clksel[] = {
};
static struct clk mcbsp5_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp5_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 5,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1431,9 +1605,8 @@ static struct clk mcbsp5_fck = {
};
static struct clk mcbsp1_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp1_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1455,9 +1628,8 @@ static struct clk core_48m_fck = {
};
static struct clk mcspi4_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi4_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 4,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1465,9 +1637,8 @@ static struct clk mcspi4_fck = {
};
static struct clk mcspi3_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi3_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1475,9 +1646,8 @@ static struct clk mcspi3_fck = {
};
static struct clk mcspi2_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1485,9 +1655,8 @@ static struct clk mcspi2_fck = {
};
static struct clk mcspi1_fck = {
- .name = "mcspi_fck",
+ .name = "mcspi1_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1500,6 +1669,7 @@ static struct clk uart2_fck = {
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
@@ -1509,6 +1679,7 @@ static struct clk uart1_fck = {
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
@@ -1588,7 +1759,7 @@ static struct clk ssi_sst_fck_3430es1 = {
.ops = &clkops_null,
.parent = &ssi_ssr_fck_3430es1,
.fixed_div = 2,
- .recalc = &omap2_fixed_divisor_recalc,
+ .recalc = &omap_fixed_divisor_recalc,
};
static struct clk ssi_sst_fck_3430es2 = {
@@ -1596,7 +1767,7 @@ static struct clk ssi_sst_fck_3430es2 = {
.ops = &clkops_null,
.parent = &ssi_ssr_fck_3430es2,
.fixed_div = 2,
- .recalc = &omap2_fixed_divisor_recalc,
+ .recalc = &omap_fixed_divisor_recalc,
};
@@ -1694,9 +1865,8 @@ static struct clk usbtll_ick = {
};
static struct clk mmchs3_ick = {
- .name = "mmchs_ick",
+ .name = "mmchs3_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1746,9 +1916,8 @@ static struct clk des2_ick = {
};
static struct clk mmchs2_ick = {
- .name = "mmchs_ick",
+ .name = "mmchs2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1757,7 +1926,7 @@ static struct clk mmchs2_ick = {
};
static struct clk mmchs1_ick = {
- .name = "mmchs_ick",
+ .name = "mmchs1_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1787,9 +1956,8 @@ static struct clk hdq_ick = {
};
static struct clk mcspi4_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi4_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 4,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1798,9 +1966,8 @@ static struct clk mcspi4_ick = {
};
static struct clk mcspi3_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi3_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1809,9 +1976,8 @@ static struct clk mcspi3_ick = {
};
static struct clk mcspi2_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1820,9 +1986,8 @@ static struct clk mcspi2_ick = {
};
static struct clk mcspi1_ick = {
- .name = "mcspi_ick",
+ .name = "mcspi1_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1831,9 +1996,8 @@ static struct clk mcspi1_ick = {
};
static struct clk i2c3_ick = {
- .name = "i2c_ick",
+ .name = "i2c3_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1842,9 +2006,8 @@ static struct clk i2c3_ick = {
};
static struct clk i2c2_ick = {
- .name = "i2c_ick",
+ .name = "i2c2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1853,9 +2016,8 @@ static struct clk i2c2_ick = {
};
static struct clk i2c1_ick = {
- .name = "i2c_ick",
+ .name = "i2c1_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1904,9 +2066,8 @@ static struct clk gpt10_ick = {
};
static struct clk mcbsp5_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp5_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 5,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1915,9 +2076,8 @@ static struct clk mcbsp5_ick = {
};
static struct clk mcbsp1_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp1_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 1,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2712,9 +2872,8 @@ static struct clk gpt2_ick = {
};
static struct clk mcbsp2_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp2_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2723,9 +2882,8 @@ static struct clk mcbsp2_ick = {
};
static struct clk mcbsp3_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp3_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2734,9 +2892,8 @@ static struct clk mcbsp3_ick = {
};
static struct clk mcbsp4_ick = {
- .name = "mcbsp_ick",
+ .name = "mcbsp4_ick",
.ops = &clkops_omap2_dflt_wait,
- .id = 4,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -2745,15 +2902,14 @@ static struct clk mcbsp4_ick = {
};
static const struct clksel mcbsp_234_clksel[] = {
- { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+ { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
{ .parent = NULL }
};
static struct clk mcbsp2_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp2_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 2,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2765,9 +2921,8 @@ static struct clk mcbsp2_fck = {
};
static struct clk mcbsp3_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp3_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 3,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2779,9 +2934,8 @@ static struct clk mcbsp3_fck = {
};
static struct clk mcbsp4_fck = {
- .name = "mcbsp_fck",
+ .name = "mcbsp4_fck",
.ops = &clkops_omap2_dflt_wait,
- .id = 4,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -2983,144 +3137,251 @@ static struct clk wdt1_fck = {
.recalc = &followparent_recalc,
};
+/* Clocks for AM35XX */
+static struct clk ipss_ick = {
+ .name = "ipss_ick",
+ .ops = &clkops_am35xx_ipss_wait,
+ .parent = &core_l3_ick,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = AM35XX_EN_IPSS_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk emac_ick = {
+ .name = "emac_ick",
+ .ops = &clkops_am35xx_ipss_module_wait,
+ .parent = &ipss_ick,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk rmii_ck = {
+ .name = "rmii_ck",
+ .ops = &clkops_null,
+ .rate = 50000000,
+};
+
+static struct clk emac_fck = {
+ .name = "emac_fck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &rmii_ck,
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_am35xx = {
+ .name = "hsotgusb_ick",
+ .ops = &clkops_am35xx_ipss_module_wait,
+ .parent = &ipss_ick,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hsotgusb_fck_am35xx = {
+ .name = "hsotgusb_fck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &sys_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hecc_ck = {
+ .name = "hecc_ck",
+ .ops = &clkops_am35xx_ipss_module_wait,
+ .parent = &sys_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk vpfe_ick = {
+ .name = "vpfe_ick",
+ .ops = &clkops_am35xx_ipss_module_wait,
+ .parent = &ipss_ick,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pclk_ck = {
+ .name = "pclk_ck",
+ .ops = &clkops_null,
+ .rate = 27000000,
+};
+
+static struct clk vpfe_fck = {
+ .name = "vpfe_fck",
+ .ops = &clkops_omap2_dflt,
+ .parent = &pclk_ck,
+ .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
+ .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * The UART1/2 functional clock acts as the functional
+ * clock for UART4. No separate fclk control available.
+ */
+static struct clk uart4_ick_am35xx = {
+ .name = "uart4_ick",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = AM35XX_EN_UART4_SHIFT,
+ .clkdm_name = "core_l4_clkdm",
+ .recalc = &followparent_recalc,
+};
+
/*
* clkdev
*/
-static struct omap_clk omap34xx_clks[] = {
- CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
- CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
- CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
- CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
- CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
- CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
- CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
- CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
- CLK(NULL, "sys_ck", &sys_ck, CK_343X),
- CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
- CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
- CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
- CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
- CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
- CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+/* XXX At some point we should rename this file to clock3xxx_data.c */
+static struct omap_clk omap3xxx_clks[] = {
+ CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
+ CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
+ CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
+ CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
+ CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
+ CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
+ CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
+ CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
+ CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
+ CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
+ CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
- CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
- CLK(NULL, "core_ck", &core_ck, CK_343X),
- CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
- CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
- CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
- CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
- CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
- CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
- CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
- CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
- CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
- CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
- CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
- CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
- CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
- CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
- CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
- CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
- CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
- CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
- CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
- CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
- CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
- CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
- CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
- CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
- CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
- CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
- CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
- CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
- CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
- CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
- CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
- CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
- CLK(NULL, "arm_fck", &arm_fck, CK_343X),
- CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+ CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
+ CLK(NULL, "core_ck", &core_ck, CK_3XXX),
+ CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
+ CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
+ CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
+ CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
+ CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+ CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
+ CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
+ CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
+ CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
+ CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+ CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
+ CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
+ CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
+ CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
+ CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
+ CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
+ CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+ CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
+ CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
+ CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
+ CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
+ CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
+ CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
+ CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
- CLK(NULL, "l3_ick", &l3_ick, CK_343X),
- CLK(NULL, "l4_ick", &l4_ick, CK_343X),
- CLK(NULL, "rm_ick", &rm_ick, CK_343X),
+ CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
+ CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
+ CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
- CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
- CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
+ CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
+ CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
CLK(NULL, "modem_fck", &modem_fck, CK_343X),
CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
- CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
- CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
- CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
- CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
- CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
- CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
- CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
+ CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
+ CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
+ CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
- CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
- CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
- CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
- CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
- CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
- CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
- CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
- CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
+ CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
+ CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
+ CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
+ CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
+ CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
+ CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
+ CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
+ CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
+ CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
+ CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
+ CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
- CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
- CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
+ CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
+ CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
- CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
+ CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
- CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
- CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
CLK(NULL, "pka_ick", &pka_ick, CK_343X),
- CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
- CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
- CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
+ CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
+ CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
+ CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "icr_ick", &icr_ick, CK_343X),
CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
CLK(NULL, "des2_ick", &des2_ick, CK_343X),
- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
+ CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
+ CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
- CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
- CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
- CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
- CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
- CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
- CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
- CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
- CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
- CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
- CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
- CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
- CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
- CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
- CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
+ CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
+ CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
+ CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
+ CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
+ CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
+ CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
+ CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
+ CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
+ CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
- CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
@@ -3131,96 +3392,111 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
- CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
- CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X),
- CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X),
- CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X),
+ CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
+ CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
+ CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
+ CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
- CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2),
+ CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
- CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
- CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
- CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
+ CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
+ CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
- CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
- CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
- CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
- CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
+ CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
+ CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
+ CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
- CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
- CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
- CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
- CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
- CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
- CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
- CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
- CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
- CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
- CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
- CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
- CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
- CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
- CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
- CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
- CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
- CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
- CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
- CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
- CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
- CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
- CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
- CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
- CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
- CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
- CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
- CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
- CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
- CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
- CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
- CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
- CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
- CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
- CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
- CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
- CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
- CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
- CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
- CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
- CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
- CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
- CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
- CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
- CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X),
- CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
- CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
- CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
- CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
- CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
+ CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
+ CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
+ CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
+ CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
+ CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
+ CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
+ CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
+ CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
+ CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
+ CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
+ CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
+ CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
+ CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
+ CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
+ CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
+ CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
+ CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
+ CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
+ CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
+ CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
+ CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
+ CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
+ CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
+ CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
+ CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
+ CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
+ CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
+ CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
+ CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
- CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
- CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
- CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
-};
-
-
-int __init omap2_clk_init(void)
+ CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
+ CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
+ CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
+ CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
+ CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
+ CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX),
+ CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX),
+ CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
+ CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
+ CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
+ CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
+ CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
+ CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
+};
+
+
+int __init omap3xxx_clk_init(void)
{
- /* struct prcm_config *prcm; */
struct omap_clk *c;
- /* u32 clkrate; */
- u32 cpu_clkflg;
-
- if (cpu_is_omap34xx()) {
+ u32 cpu_clkflg = CK_3XXX;
+
+ if (cpu_is_omap3517()) {
+ cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
+ cpu_clkflg |= CK_3517;
+ } else if (cpu_is_omap3505()) {
+ cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
+ cpu_clkflg |= CK_3505;
+ } else if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_343X;
- cpu_clkflg = CK_343X;
+ cpu_clkflg |= CK_343X;
/*
* Update this if there are further clock changes between ES2
@@ -3234,34 +3510,70 @@ int __init omap2_clk_init(void)
cpu_clkflg |= CK_3430ES2;
}
}
+ if (omap3_has_192mhz_clk())
+ omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
+
+ if (cpu_is_omap3630()) {
+ cpu_mask |= RATE_IN_36XX;
+ cpu_clkflg |= CK_36XX;
+
+ /*
+ * XXX This type of dynamic rewriting of the clock tree is
+ * deprecated and should be revised soon.
+ */
+ dpll4_m2_ck = dpll4_m2_ck_3630;
+ dpll4_m3_ck = dpll4_m3_ck_3630;
+ dpll4_m4_ck = dpll4_m4_ck_3630;
+ dpll4_m5_ck = dpll4_m5_ck_3630;
+ dpll4_m6_ck = dpll4_m6_ck_3630;
+
+ /*
+ * For 3630: override clkops_omap2_dflt_wait for the
+ * clocks affected from PWRDN reset Limitation
+ */
+ dpll3_m3x2_ck.ops =
+ &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+ dpll4_m2x2_ck.ops =
+ &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+ dpll4_m3x2_ck.ops =
+ &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+ dpll4_m4x2_ck.ops =
+ &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+ dpll4_m5x2_ck.ops =
+ &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+ dpll4_m6x2_ck.ops =
+ &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
+ } else {
+ /*
+ * XXX This type of dynamic rewriting of the clock tree is
+ * deprecated and should be revised soon.
+ */
+ dpll4_m2_ck = dpll4_m2_ck_34xx;
+ dpll4_m3_ck = dpll4_m3_ck_34xx;
+ dpll4_m4_ck = dpll4_m4_ck_34xx;
+ dpll4_m5_ck = dpll4_m5_ck_34xx;
+ dpll4_m6_ck = dpll4_m6_ck_34xx;
+ }
+
+ if (cpu_is_omap3630())
+ dpll4_dd = dpll4_dd_3630;
+ else
+ dpll4_dd = dpll4_dd_34xx;
clk_init(&omap2_clk_functions);
- for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+ for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
+ c++)
clk_preinit(c->lk.clk);
- for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+ for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
+ c++)
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
clk_register(c->lk.clk);
omap2_init_clk_clkdm(c->lk.clk);
}
- /* REVISIT: Not yet ready for OMAP3 */
-#if 0
- /* Check the MPU rate set by bootloader */
- clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
- if (prcm->xtal_speed != sys_ck.rate)
- continue;
- if (prcm->dpll_speed <= clkrate)
- break;
- }
- curr_prcm_set = prcm;
-#endif
-
recalculate_root_clocks();
printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c
deleted file mode 100644
index e370868a79a..00000000000
--- a/arch/arm/mach-omap2/clock44xx.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * OMAP4-specific clock framework functions
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- *
- * Rajendra Nayak (rnayak@ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/errno.h>
-#include "clock.h"
-
-struct clk_functions omap2_clk_functions = {
- .clk_enable = omap2_clk_enable,
- .clk_disable = omap2_clk_disable,
- .clk_round_rate = omap2_clk_round_rate,
- .clk_set_rate = omap2_clk_set_rate,
- .clk_set_parent = omap2_clk_set_parent,
- .clk_disable_unused = omap2_clk_disable_unused,
-};
-
-const struct clkops clkops_noncore_dpll_ops = {
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
-};
-
-void omap2_clk_prepare_for_reboot(void)
-{
- return;
-}
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 59b9ced4daa..6be1095936d 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -2,14 +2,19 @@
* OMAP4 clock function prototypes and macros
*
* Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
*/
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
-#define OMAP4430_MAX_DPLL_MULT 2048
+/*
+ * XXX Missing values for the OMAP4 DPLL_USB
+ * XXX Missing min_multiplier values for all OMAP4 DPLLs
+ */
+#define OMAP4430_MAX_DPLL_MULT 2047
#define OMAP4430_MAX_DPLL_DIV 128
-extern const struct clkops clkops_noncore_dpll_ops;
+int omap4xxx_clk_init(void);
#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2210e227d78..a5c0c9c8e49 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1,8 +1,8 @@
/*
* OMAP4 Clock data
*
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
@@ -20,7 +20,7 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
+#include <linux/list.h>
#include <linux/clk.h>
#include <plat/control.h>
@@ -39,42 +39,36 @@ static struct clk extalt_clkin_ck = {
.name = "extalt_clkin_ck",
.rate = 59000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk pad_clks_ck = {
.name = "pad_clks_ck",
.rate = 12000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk pad_slimbus_core_clks_ck = {
.name = "pad_slimbus_core_clks_ck",
.rate = 12000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk secure_32k_clk_src_ck = {
.name = "secure_32k_clk_src_ck",
.rate = 32768,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk slimbus_clk = {
.name = "slimbus_clk",
.rate = 12000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk sys_32k_ck = {
.name = "sys_32k_ck",
.rate = 32768,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk virt_12000000_ck = {
@@ -179,35 +173,30 @@ static struct clk sys_clkin_ck = {
.clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk utmi_phy_clkout_ck = {
.name = "utmi_phy_clkout_ck",
.rate = 12000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk xclk60mhsp1_ck = {
.name = "xclk60mhsp1_ck",
.rate = 12000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk xclk60mhsp2_ck = {
.name = "xclk60mhsp2_ck",
.rate = 12000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
static struct clk xclk60motg_ck = {
.name = "xclk60motg_ck",
.rate = 60000000,
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
};
/* Module clocks and DPLL outputs */
@@ -233,7 +222,6 @@ static struct clk dpll_sys_ref_clk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel abe_dpll_refclk_mux_sel[] = {
@@ -251,7 +239,6 @@ static struct clk abe_dpll_refclk_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_ABE */
@@ -279,11 +266,10 @@ static struct clk dpll_abe_ck = {
.parent = &abe_dpll_refclk_mux_ck,
.dpll_data = &dpll_abe_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_abe_m2x2_ck = {
@@ -291,7 +277,6 @@ static struct clk dpll_abe_m2x2_ck = {
.parent = &dpll_abe_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk abe_24m_fclk = {
@@ -299,7 +284,6 @@ static struct clk abe_24m_fclk = {
.parent = &dpll_abe_m2x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div3_1to4_rates[] = {
@@ -324,7 +308,6 @@ static struct clk abe_clk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel aess_fclk_div[] = {
@@ -342,41 +325,40 @@ static struct clk aess_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div31_1to31_rates[] = {
- { .div = 1, .val = 0, .flags = RATE_IN_4430 },
- { .div = 2, .val = 1, .flags = RATE_IN_4430 },
- { .div = 3, .val = 2, .flags = RATE_IN_4430 },
- { .div = 4, .val = 3, .flags = RATE_IN_4430 },
- { .div = 5, .val = 4, .flags = RATE_IN_4430 },
- { .div = 6, .val = 5, .flags = RATE_IN_4430 },
- { .div = 7, .val = 6, .flags = RATE_IN_4430 },
- { .div = 8, .val = 7, .flags = RATE_IN_4430 },
- { .div = 9, .val = 8, .flags = RATE_IN_4430 },
- { .div = 10, .val = 9, .flags = RATE_IN_4430 },
- { .div = 11, .val = 10, .flags = RATE_IN_4430 },
- { .div = 12, .val = 11, .flags = RATE_IN_4430 },
- { .div = 13, .val = 12, .flags = RATE_IN_4430 },
- { .div = 14, .val = 13, .flags = RATE_IN_4430 },
- { .div = 15, .val = 14, .flags = RATE_IN_4430 },
- { .div = 16, .val = 15, .flags = RATE_IN_4430 },
- { .div = 17, .val = 16, .flags = RATE_IN_4430 },
- { .div = 18, .val = 17, .flags = RATE_IN_4430 },
- { .div = 19, .val = 18, .flags = RATE_IN_4430 },
- { .div = 20, .val = 19, .flags = RATE_IN_4430 },
- { .div = 21, .val = 20, .flags = RATE_IN_4430 },
- { .div = 22, .val = 21, .flags = RATE_IN_4430 },
- { .div = 23, .val = 22, .flags = RATE_IN_4430 },
- { .div = 24, .val = 23, .flags = RATE_IN_4430 },
- { .div = 25, .val = 24, .flags = RATE_IN_4430 },
- { .div = 26, .val = 25, .flags = RATE_IN_4430 },
- { .div = 27, .val = 26, .flags = RATE_IN_4430 },
- { .div = 28, .val = 27, .flags = RATE_IN_4430 },
- { .div = 29, .val = 28, .flags = RATE_IN_4430 },
- { .div = 30, .val = 29, .flags = RATE_IN_4430 },
- { .div = 31, .val = 30, .flags = RATE_IN_4430 },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+ { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+ { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+ { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+ { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+ { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+ { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+ { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+ { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+ { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+ { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+ { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+ { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+ { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+ { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+ { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+ { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+ { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+ { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+ { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+ { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+ { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+ { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+ { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+ { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+ { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+ { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+ { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+ { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+ { .div = 31, .val = 31, .flags = RATE_IN_4430 },
{ .div = 0 },
};
@@ -395,7 +377,6 @@ static struct clk dpll_abe_m3_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel core_hsd_byp_clk_mux_sel[] = {
@@ -413,7 +394,6 @@ static struct clk core_hsd_byp_clk_mux_ck = {
.clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_CORE */
@@ -443,7 +423,6 @@ static struct clk dpll_core_ck = {
.init = &omap2_init_dpll_parent,
.ops = &clkops_null,
.recalc = &omap3_dpll_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dpll_core_m6_div[] = {
@@ -461,7 +440,6 @@ static struct clk dpll_core_m6_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dbgclk_mux_sel[] = {
@@ -475,7 +453,6 @@ static struct clk dbgclk_mux_ck = {
.parent = &sys_clkin_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_core_m2_ck = {
@@ -488,7 +465,6 @@ static struct clk dpll_core_m2_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk ddrphy_ck = {
@@ -496,7 +472,6 @@ static struct clk ddrphy_ck = {
.parent = &dpll_core_m2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_core_m5_ck = {
@@ -509,7 +484,6 @@ static struct clk dpll_core_m5_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel div_core_div[] = {
@@ -527,7 +501,6 @@ static struct clk div_core_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div4_1to8_rates[] = {
@@ -553,7 +526,6 @@ static struct clk div_iva_hs_clk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk div_mpu_hs_clk = {
@@ -566,7 +538,6 @@ static struct clk div_mpu_hs_clk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_core_m4_ck = {
@@ -579,7 +550,6 @@ static struct clk dpll_core_m4_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dll_clk_div_ck = {
@@ -587,7 +557,6 @@ static struct clk dll_clk_div_ck = {
.parent = &dpll_core_m4_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_abe_m2_ck = {
@@ -600,7 +569,6 @@ static struct clk dpll_abe_m2_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_core_m3_ck = {
@@ -613,7 +581,6 @@ static struct clk dpll_core_m3_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_core_m7_ck = {
@@ -626,7 +593,6 @@ static struct clk dpll_core_m7_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
@@ -640,7 +606,6 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
.parent = &dpll_sys_ref_clk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_IVA */
@@ -668,11 +633,10 @@ static struct clk dpll_iva_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_iva_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dpll_iva_m4_div[] = {
@@ -690,7 +654,6 @@ static struct clk dpll_iva_m4_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_iva_m5_ck = {
@@ -703,7 +666,6 @@ static struct clk dpll_iva_m5_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_MPU */
@@ -731,11 +693,10 @@ static struct clk dpll_mpu_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_mpu_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dpll_mpu_m2_div[] = {
@@ -753,7 +714,6 @@ static struct clk dpll_mpu_m2_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk per_hs_clk_div_ck = {
@@ -761,7 +721,6 @@ static struct clk per_hs_clk_div_ck = {
.parent = &dpll_abe_m3_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel per_hsd_byp_clk_mux_sel[] = {
@@ -779,7 +738,6 @@ static struct clk per_hsd_byp_clk_mux_ck = {
.clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_PER */
@@ -807,11 +765,10 @@ static struct clk dpll_per_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_per_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dpll_per_m2_div[] = {
@@ -829,7 +786,6 @@ static struct clk dpll_per_m2_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_per_m2x2_ck = {
@@ -837,7 +793,6 @@ static struct clk dpll_per_m2x2_ck = {
.parent = &dpll_per_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_per_m3_ck = {
@@ -850,7 +805,6 @@ static struct clk dpll_per_m3_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_per_m4_ck = {
@@ -863,7 +817,6 @@ static struct clk dpll_per_m4_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_per_m5_ck = {
@@ -876,7 +829,6 @@ static struct clk dpll_per_m5_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_per_m6_ck = {
@@ -889,7 +841,6 @@ static struct clk dpll_per_m6_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_per_m7_ck = {
@@ -902,7 +853,6 @@ static struct clk dpll_per_m7_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_UNIPRO */
@@ -930,11 +880,10 @@ static struct clk dpll_unipro_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_unipro_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dpll_unipro_m2x2_div[] = {
@@ -952,7 +901,6 @@ static struct clk dpll_unipro_m2x2_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk usb_hs_clk_div_ck = {
@@ -960,7 +908,6 @@ static struct clk usb_hs_clk_div_ck = {
.parent = &dpll_abe_m3_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
/* DPLL_USB */
@@ -980,6 +927,7 @@ static struct dpll_data dpll_usb_dd = {
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.min_divider = 1,
+ .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
};
@@ -988,11 +936,10 @@ static struct clk dpll_usb_ck = {
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_usb_dd,
.init = &omap2_init_dpll_parent,
- .ops = &clkops_noncore_dpll_ops,
+ .ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk dpll_usb_clkdcoldo_ck = {
@@ -1000,7 +947,6 @@ static struct clk dpll_usb_clkdcoldo_ck = {
.parent = &dpll_usb_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel dpll_usb_m2_div[] = {
@@ -1018,7 +964,6 @@ static struct clk dpll_usb_m2_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel ducati_clk_mux_sel[] = {
@@ -1036,7 +981,6 @@ static struct clk ducati_clk_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk func_12m_fclk = {
@@ -1044,7 +988,6 @@ static struct clk func_12m_fclk = {
.parent = &dpll_per_m2x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk func_24m_clk = {
@@ -1052,7 +995,6 @@ static struct clk func_24m_clk = {
.parent = &dpll_per_m2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk func_24mc_fclk = {
@@ -1060,7 +1002,6 @@ static struct clk func_24mc_fclk = {
.parent = &dpll_per_m2x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div2_4to8_rates[] = {
@@ -1084,7 +1025,6 @@ static struct clk func_48m_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk func_48mc_fclk = {
@@ -1092,7 +1032,6 @@ static struct clk func_48mc_fclk = {
.parent = &dpll_per_m2x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div2_2to4_rates[] = {
@@ -1116,7 +1055,6 @@ static struct clk func_64m_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel func_96m_fclk_div[] = {
@@ -1134,7 +1072,6 @@ static struct clk func_96m_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel hsmmc6_fclk_sel[] = {
@@ -1148,7 +1085,6 @@ static struct clk hsmmc6_fclk = {
.parent = &func_64m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div2_1to8_rates[] = {
@@ -1172,7 +1108,6 @@ static struct clk init_60m_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel l3_div_div[] = {
@@ -1190,7 +1125,6 @@ static struct clk l3_div_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel l4_div_div[] = {
@@ -1208,7 +1142,6 @@ static struct clk l4_div_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk lp_clk_div_ck = {
@@ -1216,7 +1149,6 @@ static struct clk lp_clk_div_ck = {
.parent = &dpll_abe_m2x2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1234,7 +1166,6 @@ static struct clk l4_wkup_clk_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel per_abe_nc_fclk_div[] = {
@@ -1252,7 +1183,6 @@ static struct clk per_abe_nc_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel mcasp2_fclk_sel[] = {
@@ -1266,7 +1196,6 @@ static struct clk mcasp2_fclk = {
.parent = &func_96m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk mcasp3_fclk = {
@@ -1274,7 +1203,6 @@ static struct clk mcasp3_fclk = {
.parent = &func_96m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk ocp_abe_iclk = {
@@ -1282,7 +1210,6 @@ static struct clk ocp_abe_iclk = {
.parent = &aess_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk per_abe_24m_fclk = {
@@ -1290,7 +1217,6 @@ static struct clk per_abe_24m_fclk = {
.parent = &dpll_abe_m2_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel pmd_stm_clock_mux_sel[] = {
@@ -1305,7 +1231,6 @@ static struct clk pmd_stm_clock_mux_ck = {
.parent = &sys_clkin_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk pmd_trace_clk_mux_ck = {
@@ -1313,7 +1238,6 @@ static struct clk pmd_trace_clk_mux_ck = {
.parent = &sys_clkin_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static struct clk syc_clk_div_ck = {
@@ -1326,13 +1250,12 @@ static struct clk syc_clk_div_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
/* Leaf clocks controlled by modules */
-static struct clk aes1_ck = {
- .name = "aes1_ck",
+static struct clk aes1_fck = {
+ .name = "aes1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1341,8 +1264,8 @@ static struct clk aes1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk aes2_ck = {
- .name = "aes2_ck",
+static struct clk aes2_fck = {
+ .name = "aes2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1351,8 +1274,8 @@ static struct clk aes2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk aess_ck = {
- .name = "aess_ck",
+static struct clk aess_fck = {
+ .name = "aess_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1361,8 +1284,8 @@ static struct clk aess_ck = {
.recalc = &followparent_recalc,
};
-static struct clk cust_efuse_ck = {
- .name = "cust_efuse_ck",
+static struct clk cust_efuse_fck = {
+ .name = "cust_efuse_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1371,8 +1294,8 @@ static struct clk cust_efuse_ck = {
.recalc = &followparent_recalc,
};
-static struct clk des3des_ck = {
- .name = "des3des_ck",
+static struct clk des3des_fck = {
+ .name = "des3des_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1397,7 +1320,6 @@ static struct clk dmic_sync_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel func_dmic_abe_gfclk_sel[] = {
@@ -1407,9 +1329,9 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = {
{ .parent = NULL },
};
-/* Merged func_dmic_abe_gfclk into dmic_ck */
-static struct clk dmic_ck = {
- .name = "dmic_ck",
+/* Merged func_dmic_abe_gfclk into dmic */
+static struct clk dmic_fck = {
+ .name = "dmic_fck",
.parent = &dmic_sync_mux_ck,
.clksel = func_dmic_abe_gfclk_sel,
.init = &omap2_init_clksel_parent,
@@ -1417,14 +1339,13 @@ static struct clk dmic_ck = {
.clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
-static struct clk dss_ck = {
- .name = "dss_ck",
+static struct clk dss_fck = {
+ .name = "dss_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1433,8 +1354,8 @@ static struct clk dss_ck = {
.recalc = &followparent_recalc,
};
-static struct clk ducati_ck = {
- .name = "ducati_ck",
+static struct clk ducati_ick = {
+ .name = "ducati_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1443,8 +1364,8 @@ static struct clk ducati_ck = {
.recalc = &followparent_recalc,
};
-static struct clk emif1_ck = {
- .name = "emif1_ck",
+static struct clk emif1_ick = {
+ .name = "emif1_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1453,8 +1374,8 @@ static struct clk emif1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk emif2_ck = {
- .name = "emif2_ck",
+static struct clk emif2_ick = {
+ .name = "emif2_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1468,9 +1389,9 @@ static const struct clksel fdif_fclk_div[] = {
{ .parent = NULL },
};
-/* Merged fdif_fclk into fdif_ck */
-static struct clk fdif_ck = {
- .name = "fdif_ck",
+/* Merged fdif_fclk into fdif */
+static struct clk fdif_fck = {
+ .name = "fdif_fck",
.parent = &dpll_per_m4_ck,
.clksel = fdif_fclk_div,
.clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
@@ -1479,7 +1400,6 @@ static struct clk fdif_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "iss_clkdm",
@@ -1500,7 +1420,6 @@ static struct clk per_sgx_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel sgx_clk_mux_sel[] = {
@@ -1509,9 +1428,9 @@ static const struct clksel sgx_clk_mux_sel[] = {
{ .parent = NULL },
};
-/* Merged sgx_clk_mux into gfx_ck */
-static struct clk gfx_ck = {
- .name = "gfx_ck",
+/* Merged sgx_clk_mux into gfx */
+static struct clk gfx_fck = {
+ .name = "gfx_fck",
.parent = &dpll_core_m7_ck,
.clksel = sgx_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1519,14 +1438,13 @@ static struct clk gfx_ck = {
.clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_gfx_clkdm",
};
-static struct clk gpio1_ck = {
- .name = "gpio1_ck",
+static struct clk gpio1_ick = {
+ .name = "gpio1_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1535,8 +1453,8 @@ static struct clk gpio1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk gpio2_ck = {
- .name = "gpio2_ck",
+static struct clk gpio2_ick = {
+ .name = "gpio2_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1545,8 +1463,8 @@ static struct clk gpio2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk gpio3_ck = {
- .name = "gpio3_ck",
+static struct clk gpio3_ick = {
+ .name = "gpio3_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1555,8 +1473,8 @@ static struct clk gpio3_ck = {
.recalc = &followparent_recalc,
};
-static struct clk gpio4_ck = {
- .name = "gpio4_ck",
+static struct clk gpio4_ick = {
+ .name = "gpio4_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1565,8 +1483,8 @@ static struct clk gpio4_ck = {
.recalc = &followparent_recalc,
};
-static struct clk gpio5_ck = {
- .name = "gpio5_ck",
+static struct clk gpio5_ick = {
+ .name = "gpio5_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1575,8 +1493,8 @@ static struct clk gpio5_ck = {
.recalc = &followparent_recalc,
};
-static struct clk gpio6_ck = {
- .name = "gpio6_ck",
+static struct clk gpio6_ick = {
+ .name = "gpio6_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1585,8 +1503,8 @@ static struct clk gpio6_ck = {
.recalc = &followparent_recalc,
};
-static struct clk gpmc_ck = {
- .name = "gpmc_ck",
+static struct clk gpmc_ick = {
+ .name = "gpmc_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1601,9 +1519,12 @@ static const struct clksel dmt1_clk_mux_sel[] = {
{ .parent = NULL },
};
-/* Merged dmt1_clk_mux into gptimer1_ck */
-static struct clk gptimer1_ck = {
- .name = "gptimer1_ck",
+/*
+ * Merged dmt1_clk_mux into gptimer1
+ * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
+ */
+static struct clk gpt1_fck = {
+ .name = "gpt1_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1611,15 +1532,17 @@ static struct clk gptimer1_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_wkup_clkdm",
};
-/* Merged cm2_dm10_mux into gptimer10_ck */
-static struct clk gptimer10_ck = {
- .name = "gptimer10_ck",
+/*
+ * Merged cm2_dm10_mux into gptimer10
+ * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
+ */
+static struct clk gpt10_fck = {
+ .name = "gpt10_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1627,15 +1550,17 @@ static struct clk gptimer10_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
-/* Merged cm2_dm11_mux into gptimer11_ck */
-static struct clk gptimer11_ck = {
- .name = "gptimer11_ck",
+/*
+ * Merged cm2_dm11_mux into gptimer11
+ * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
+ */
+static struct clk gpt11_fck = {
+ .name = "gpt11_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1643,15 +1568,17 @@ static struct clk gptimer11_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
-/* Merged cm2_dm2_mux into gptimer2_ck */
-static struct clk gptimer2_ck = {
- .name = "gptimer2_ck",
+/*
+ * Merged cm2_dm2_mux into gptimer2
+ * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
+ */
+static struct clk gpt2_fck = {
+ .name = "gpt2_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1659,15 +1586,17 @@ static struct clk gptimer2_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
-/* Merged cm2_dm3_mux into gptimer3_ck */
-static struct clk gptimer3_ck = {
- .name = "gptimer3_ck",
+/*
+ * Merged cm2_dm3_mux into gptimer3
+ * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
+ */
+static struct clk gpt3_fck = {
+ .name = "gpt3_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1675,15 +1604,17 @@ static struct clk gptimer3_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
-/* Merged cm2_dm4_mux into gptimer4_ck */
-static struct clk gptimer4_ck = {
- .name = "gptimer4_ck",
+/*
+ * Merged cm2_dm4_mux into gptimer4
+ * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
+ */
+static struct clk gpt4_fck = {
+ .name = "gpt4_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1691,7 +1622,6 @@ static struct clk gptimer4_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
@@ -1703,9 +1633,12 @@ static const struct clksel timer5_sync_mux_sel[] = {
{ .parent = NULL },
};
-/* Merged timer5_sync_mux into gptimer5_ck */
-static struct clk gptimer5_ck = {
- .name = "gptimer5_ck",
+/*
+ * Merged timer5_sync_mux into gptimer5
+ * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
+ */
+static struct clk gpt5_fck = {
+ .name = "gpt5_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1713,15 +1646,17 @@ static struct clk gptimer5_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
-/* Merged timer6_sync_mux into gptimer6_ck */
-static struct clk gptimer6_ck = {
- .name = "gptimer6_ck",
+/*
+ * Merged timer6_sync_mux into gptimer6
+ * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
+ */
+static struct clk gpt6_fck = {
+ .name = "gpt6_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1729,15 +1664,17 @@ static struct clk gptimer6_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
-/* Merged timer7_sync_mux into gptimer7_ck */
-static struct clk gptimer7_ck = {
- .name = "gptimer7_ck",
+/*
+ * Merged timer7_sync_mux into gptimer7
+ * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
+ */
+static struct clk gpt7_fck = {
+ .name = "gpt7_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1745,15 +1682,17 @@ static struct clk gptimer7_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
-/* Merged timer8_sync_mux into gptimer8_ck */
-static struct clk gptimer8_ck = {
- .name = "gptimer8_ck",
+/*
+ * Merged timer8_sync_mux into gptimer8
+ * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
+ */
+static struct clk gpt8_fck = {
+ .name = "gpt8_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1761,15 +1700,17 @@ static struct clk gptimer8_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
-/* Merged cm2_dm9_mux into gptimer9_ck */
-static struct clk gptimer9_ck = {
- .name = "gptimer9_ck",
+/*
+ * Merged cm2_dm9_mux into gptimer9
+ * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
+ */
+static struct clk gpt9_fck = {
+ .name = "gpt9_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
@@ -1777,14 +1718,13 @@ static struct clk gptimer9_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
-static struct clk hdq1w_ck = {
- .name = "hdq1w_ck",
+static struct clk hdq1w_fck = {
+ .name = "hdq1w_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1793,9 +1733,9 @@ static struct clk hdq1w_ck = {
.recalc = &followparent_recalc,
};
-/* Merged hsi_fclk into hsi_ck */
-static struct clk hsi_ck = {
- .name = "hsi_ck",
+/* Merged hsi_fclk into hsi */
+static struct clk hsi_ick = {
+ .name = "hsi_ick",
.parent = &dpll_per_m2x2_ck,
.clksel = per_sgx_fclk_div,
.clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
@@ -1804,14 +1744,13 @@ static struct clk hsi_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_init_clkdm",
};
-static struct clk i2c1_ck = {
- .name = "i2c1_ck",
+static struct clk i2c1_fck = {
+ .name = "i2c1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1820,8 +1759,8 @@ static struct clk i2c1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk i2c2_ck = {
- .name = "i2c2_ck",
+static struct clk i2c2_fck = {
+ .name = "i2c2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1830,8 +1769,8 @@ static struct clk i2c2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk i2c3_ck = {
- .name = "i2c3_ck",
+static struct clk i2c3_fck = {
+ .name = "i2c3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1840,8 +1779,8 @@ static struct clk i2c3_ck = {
.recalc = &followparent_recalc,
};
-static struct clk i2c4_ck = {
- .name = "i2c4_ck",
+static struct clk i2c4_fck = {
+ .name = "i2c4_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1850,8 +1789,8 @@ static struct clk i2c4_ck = {
.recalc = &followparent_recalc,
};
-static struct clk iss_ck = {
- .name = "iss_ck",
+static struct clk iss_fck = {
+ .name = "iss_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1860,8 +1799,8 @@ static struct clk iss_ck = {
.recalc = &followparent_recalc,
};
-static struct clk ivahd_ck = {
- .name = "ivahd_ck",
+static struct clk ivahd_ick = {
+ .name = "ivahd_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1870,8 +1809,8 @@ static struct clk ivahd_ck = {
.recalc = &followparent_recalc,
};
-static struct clk keyboard_ck = {
- .name = "keyboard_ck",
+static struct clk keyboard_fck = {
+ .name = "keyboard_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1880,8 +1819,8 @@ static struct clk keyboard_ck = {
.recalc = &followparent_recalc,
};
-static struct clk l3_instr_interconnect_ck = {
- .name = "l3_instr_interconnect_ck",
+static struct clk l3_instr_interconnect_ick = {
+ .name = "l3_instr_interconnect_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1890,8 +1829,8 @@ static struct clk l3_instr_interconnect_ck = {
.recalc = &followparent_recalc,
};
-static struct clk l3_interconnect_3_ck = {
- .name = "l3_interconnect_3_ck",
+static struct clk l3_interconnect_3_ick = {
+ .name = "l3_interconnect_3_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1909,7 +1848,6 @@ static struct clk mcasp_sync_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel func_mcasp_abe_gfclk_sel[] = {
@@ -1919,9 +1857,9 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
{ .parent = NULL },
};
-/* Merged func_mcasp_abe_gfclk into mcasp_ck */
-static struct clk mcasp_ck = {
- .name = "mcasp_ck",
+/* Merged func_mcasp_abe_gfclk into mcasp */
+static struct clk mcasp_fck = {
+ .name = "mcasp_fck",
.parent = &mcasp_sync_mux_ck,
.clksel = func_mcasp_abe_gfclk_sel,
.init = &omap2_init_clksel_parent,
@@ -1929,7 +1867,6 @@ static struct clk mcasp_ck = {
.clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
@@ -1944,7 +1881,6 @@ static struct clk mcbsp1_sync_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel func_mcbsp1_gfclk_sel[] = {
@@ -1954,9 +1890,9 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
{ .parent = NULL },
};
-/* Merged func_mcbsp1_gfclk into mcbsp1_ck */
-static struct clk mcbsp1_ck = {
- .name = "mcbsp1_ck",
+/* Merged func_mcbsp1_gfclk into mcbsp1 */
+static struct clk mcbsp1_fck = {
+ .name = "mcbsp1_fck",
.parent = &mcbsp1_sync_mux_ck,
.clksel = func_mcbsp1_gfclk_sel,
.init = &omap2_init_clksel_parent,
@@ -1964,7 +1900,6 @@ static struct clk mcbsp1_ck = {
.clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
@@ -1979,7 +1914,6 @@ static struct clk mcbsp2_sync_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel func_mcbsp2_gfclk_sel[] = {
@@ -1989,9 +1923,9 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
{ .parent = NULL },
};
-/* Merged func_mcbsp2_gfclk into mcbsp2_ck */
-static struct clk mcbsp2_ck = {
- .name = "mcbsp2_ck",
+/* Merged func_mcbsp2_gfclk into mcbsp2 */
+static struct clk mcbsp2_fck = {
+ .name = "mcbsp2_fck",
.parent = &mcbsp2_sync_mux_ck,
.clksel = func_mcbsp2_gfclk_sel,
.init = &omap2_init_clksel_parent,
@@ -1999,7 +1933,6 @@ static struct clk mcbsp2_ck = {
.clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
@@ -2014,7 +1947,6 @@ static struct clk mcbsp3_sync_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel func_mcbsp3_gfclk_sel[] = {
@@ -2024,9 +1956,9 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
{ .parent = NULL },
};
-/* Merged func_mcbsp3_gfclk into mcbsp3_ck */
-static struct clk mcbsp3_ck = {
- .name = "mcbsp3_ck",
+/* Merged func_mcbsp3_gfclk into mcbsp3 */
+static struct clk mcbsp3_fck = {
+ .name = "mcbsp3_fck",
.parent = &mcbsp3_sync_mux_ck,
.clksel = func_mcbsp3_gfclk_sel,
.init = &omap2_init_clksel_parent,
@@ -2034,7 +1966,6 @@ static struct clk mcbsp3_ck = {
.clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
@@ -2049,7 +1980,6 @@ static struct clk mcbsp4_sync_mux_ck = {
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel per_mcbsp4_gfclk_sel[] = {
@@ -2058,9 +1988,9 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = {
{ .parent = NULL },
};
-/* Merged per_mcbsp4_gfclk into mcbsp4_ck */
-static struct clk mcbsp4_ck = {
- .name = "mcbsp4_ck",
+/* Merged per_mcbsp4_gfclk into mcbsp4 */
+static struct clk mcbsp4_fck = {
+ .name = "mcbsp4_fck",
.parent = &mcbsp4_sync_mux_ck,
.clksel = per_mcbsp4_gfclk_sel,
.init = &omap2_init_clksel_parent,
@@ -2068,14 +1998,13 @@ static struct clk mcbsp4_ck = {
.clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
-static struct clk mcspi1_ck = {
- .name = "mcspi1_ck",
+static struct clk mcspi1_fck = {
+ .name = "mcspi1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2084,8 +2013,8 @@ static struct clk mcspi1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk mcspi2_ck = {
- .name = "mcspi2_ck",
+static struct clk mcspi2_fck = {
+ .name = "mcspi2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2094,8 +2023,8 @@ static struct clk mcspi2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk mcspi3_ck = {
- .name = "mcspi3_ck",
+static struct clk mcspi3_fck = {
+ .name = "mcspi3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2104,8 +2033,8 @@ static struct clk mcspi3_ck = {
.recalc = &followparent_recalc,
};
-static struct clk mcspi4_ck = {
- .name = "mcspi4_ck",
+static struct clk mcspi4_fck = {
+ .name = "mcspi4_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2114,9 +2043,9 @@ static struct clk mcspi4_ck = {
.recalc = &followparent_recalc,
};
-/* Merged hsmmc1_fclk into mmc1_ck */
-static struct clk mmc1_ck = {
- .name = "mmc1_ck",
+/* Merged hsmmc1_fclk into mmc1 */
+static struct clk mmc1_fck = {
+ .name = "mmc1_fck",
.parent = &func_64m_fclk,
.clksel = hsmmc6_fclk_sel,
.init = &omap2_init_clksel_parent,
@@ -2124,15 +2053,14 @@ static struct clk mmc1_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_init_clkdm",
};
-/* Merged hsmmc2_fclk into mmc2_ck */
-static struct clk mmc2_ck = {
- .name = "mmc2_ck",
+/* Merged hsmmc2_fclk into mmc2 */
+static struct clk mmc2_fck = {
+ .name = "mmc2_fck",
.parent = &func_64m_fclk,
.clksel = hsmmc6_fclk_sel,
.init = &omap2_init_clksel_parent,
@@ -2140,14 +2068,13 @@ static struct clk mmc2_ck = {
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
.enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_init_clkdm",
};
-static struct clk mmc3_ck = {
- .name = "mmc3_ck",
+static struct clk mmc3_fck = {
+ .name = "mmc3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2156,8 +2083,8 @@ static struct clk mmc3_ck = {
.recalc = &followparent_recalc,
};
-static struct clk mmc4_ck = {
- .name = "mmc4_ck",
+static struct clk mmc4_fck = {
+ .name = "mmc4_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2166,8 +2093,8 @@ static struct clk mmc4_ck = {
.recalc = &followparent_recalc,
};
-static struct clk mmc5_ck = {
- .name = "mmc5_ck",
+static struct clk mmc5_fck = {
+ .name = "mmc5_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2176,8 +2103,8 @@ static struct clk mmc5_ck = {
.recalc = &followparent_recalc,
};
-static struct clk ocp_wp1_ck = {
- .name = "ocp_wp1_ck",
+static struct clk ocp_wp1_ick = {
+ .name = "ocp_wp1_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2186,8 +2113,8 @@ static struct clk ocp_wp1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk pdm_ck = {
- .name = "pdm_ck",
+static struct clk pdm_fck = {
+ .name = "pdm_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2196,8 +2123,8 @@ static struct clk pdm_ck = {
.recalc = &followparent_recalc,
};
-static struct clk pkaeip29_ck = {
- .name = "pkaeip29_ck",
+static struct clk pkaeip29_fck = {
+ .name = "pkaeip29_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2206,8 +2133,8 @@ static struct clk pkaeip29_ck = {
.recalc = &followparent_recalc,
};
-static struct clk rng_ck = {
- .name = "rng_ck",
+static struct clk rng_ick = {
+ .name = "rng_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2216,8 +2143,8 @@ static struct clk rng_ck = {
.recalc = &followparent_recalc,
};
-static struct clk sha2md51_ck = {
- .name = "sha2md51_ck",
+static struct clk sha2md51_fck = {
+ .name = "sha2md51_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2226,8 +2153,8 @@ static struct clk sha2md51_ck = {
.recalc = &followparent_recalc,
};
-static struct clk sl2_ck = {
- .name = "sl2_ck",
+static struct clk sl2_ick = {
+ .name = "sl2_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2236,8 +2163,8 @@ static struct clk sl2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk slimbus1_ck = {
- .name = "slimbus1_ck",
+static struct clk slimbus1_fck = {
+ .name = "slimbus1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2246,8 +2173,8 @@ static struct clk slimbus1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk slimbus2_ck = {
- .name = "slimbus2_ck",
+static struct clk slimbus2_fck = {
+ .name = "slimbus2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2256,8 +2183,8 @@ static struct clk slimbus2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk sr_core_ck = {
- .name = "sr_core_ck",
+static struct clk sr_core_fck = {
+ .name = "sr_core_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2266,8 +2193,8 @@ static struct clk sr_core_ck = {
.recalc = &followparent_recalc,
};
-static struct clk sr_iva_ck = {
- .name = "sr_iva_ck",
+static struct clk sr_iva_fck = {
+ .name = "sr_iva_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2276,8 +2203,8 @@ static struct clk sr_iva_ck = {
.recalc = &followparent_recalc,
};
-static struct clk sr_mpu_ck = {
- .name = "sr_mpu_ck",
+static struct clk sr_mpu_fck = {
+ .name = "sr_mpu_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2286,8 +2213,8 @@ static struct clk sr_mpu_ck = {
.recalc = &followparent_recalc,
};
-static struct clk tesla_ck = {
- .name = "tesla_ck",
+static struct clk tesla_ick = {
+ .name = "tesla_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2296,8 +2223,8 @@ static struct clk tesla_ck = {
.recalc = &followparent_recalc,
};
-static struct clk uart1_ck = {
- .name = "uart1_ck",
+static struct clk uart1_fck = {
+ .name = "uart1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2306,8 +2233,8 @@ static struct clk uart1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk uart2_ck = {
- .name = "uart2_ck",
+static struct clk uart2_fck = {
+ .name = "uart2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2316,8 +2243,8 @@ static struct clk uart2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk uart3_ck = {
- .name = "uart3_ck",
+static struct clk uart3_fck = {
+ .name = "uart3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2326,8 +2253,8 @@ static struct clk uart3_ck = {
.recalc = &followparent_recalc,
};
-static struct clk uart4_ck = {
- .name = "uart4_ck",
+static struct clk uart4_fck = {
+ .name = "uart4_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2336,8 +2263,8 @@ static struct clk uart4_ck = {
.recalc = &followparent_recalc,
};
-static struct clk unipro1_ck = {
- .name = "unipro1_ck",
+static struct clk unipro1_fck = {
+ .name = "unipro1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2346,8 +2273,8 @@ static struct clk unipro1_ck = {
.recalc = &followparent_recalc,
};
-static struct clk usb_host_ck = {
- .name = "usb_host_ck",
+static struct clk usb_host_fck = {
+ .name = "usb_host_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2356,8 +2283,8 @@ static struct clk usb_host_ck = {
.recalc = &followparent_recalc,
};
-static struct clk usb_host_fs_ck = {
- .name = "usb_host_fs_ck",
+static struct clk usb_host_fs_fck = {
+ .name = "usb_host_fs_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2366,8 +2293,8 @@ static struct clk usb_host_fs_ck = {
.recalc = &followparent_recalc,
};
-static struct clk usb_otg_ck = {
- .name = "usb_otg_ck",
+static struct clk usb_otg_ick = {
+ .name = "usb_otg_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2376,8 +2303,8 @@ static struct clk usb_otg_ck = {
.recalc = &followparent_recalc,
};
-static struct clk usb_tll_ck = {
- .name = "usb_tll_ck",
+static struct clk usb_tll_ick = {
+ .name = "usb_tll_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2386,8 +2313,8 @@ static struct clk usb_tll_ck = {
.recalc = &followparent_recalc,
};
-static struct clk usbphyocp2scp_ck = {
- .name = "usbphyocp2scp_ck",
+static struct clk usbphyocp2scp_ick = {
+ .name = "usbphyocp2scp_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2396,8 +2323,8 @@ static struct clk usbphyocp2scp_ck = {
.recalc = &followparent_recalc,
};
-static struct clk usim_ck = {
- .name = "usim_ck",
+static struct clk usim_fck = {
+ .name = "usim_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2406,8 +2333,8 @@ static struct clk usim_ck = {
.recalc = &followparent_recalc,
};
-static struct clk wdt2_ck = {
- .name = "wdt2_ck",
+static struct clk wdt2_fck = {
+ .name = "wdt2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2416,8 +2343,8 @@ static struct clk wdt2_ck = {
.recalc = &followparent_recalc,
};
-static struct clk wdt3_ck = {
- .name = "wdt3_ck",
+static struct clk wdt3_fck = {
+ .name = "wdt3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2442,7 +2369,6 @@ static struct clk otg_60m_gfclk_ck = {
.clksel_mask = OMAP4430_CLKSEL_60M_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel stm_clk_div_div[] = {
@@ -2460,7 +2386,6 @@ static struct clk stm_clk_div_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel trace_clk_div_div[] = {
@@ -2478,7 +2403,6 @@ static struct clk trace_clk_div_ck = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel_rate div2_14to18_rates[] = {
@@ -2502,7 +2426,6 @@ static struct clk usim_fclk = {
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel utmi_p1_gfclk_sel[] = {
@@ -2520,7 +2443,6 @@ static struct clk utmi_p1_gfclk_ck = {
.clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
static const struct clksel utmi_p2_gfclk_sel[] = {
@@ -2538,7 +2460,6 @@ static struct clk utmi_p2_gfclk_ck = {
.clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
- .flags = CLOCK_IN_OMAP4430,
};
/*
@@ -2631,106 +2552,139 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
- CLK(NULL, "aes1_ck", &aes1_ck, CK_443X),
- CLK(NULL, "aes2_ck", &aes2_ck, CK_443X),
- CLK(NULL, "aess_ck", &aess_ck, CK_443X),
- CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X),
- CLK(NULL, "des3des_ck", &des3des_ck, CK_443X),
+ CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
+ CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
+ CLK(NULL, "aess_fck", &aess_fck, CK_443X),
+ CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X),
+ CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
- CLK(NULL, "dmic_ck", &dmic_ck, CK_443X),
- CLK(NULL, "dss_ck", &dss_ck, CK_443X),
- CLK(NULL, "ducati_ck", &ducati_ck, CK_443X),
- CLK(NULL, "emif1_ck", &emif1_ck, CK_443X),
- CLK(NULL, "emif2_ck", &emif2_ck, CK_443X),
- CLK(NULL, "fdif_ck", &fdif_ck, CK_443X),
+ CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
+ CLK(NULL, "dss_fck", &dss_fck, CK_443X),
+ CLK(NULL, "ducati_ick", &ducati_ick, CK_443X),
+ CLK(NULL, "emif1_ick", &emif1_ick, CK_443X),
+ CLK(NULL, "emif2_ick", &emif2_ick, CK_443X),
+ CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
- CLK(NULL, "gfx_ck", &gfx_ck, CK_443X),
- CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X),
- CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X),
- CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X),
- CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X),
- CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X),
- CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X),
- CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X),
- CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X),
- CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X),
- CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X),
- CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X),
- CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X),
- CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X),
- CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X),
- CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X),
- CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X),
- CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X),
- CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X),
- CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X),
- CLK(NULL, "hsi_ck", &hsi_ck, CK_443X),
- CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X),
- CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X),
- CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X),
- CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X),
- CLK(NULL, "iss_ck", &iss_ck, CK_443X),
- CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X),
- CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X),
- CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X),
- CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X),
+ CLK(NULL, "gfx_fck", &gfx_fck, CK_443X),
+ CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
+ CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
+ CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
+ CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
+ CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
+ CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
+ CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
+ CLK(NULL, "hsi_ick", &hsi_ick, CK_443X),
+ CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
+ CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
+ CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
+ CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
+ CLK(NULL, "iss_fck", &iss_fck, CK_443X),
+ CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X),
+ CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X),
+ CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X),
+ CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X),
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
- CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X),
+ CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X),
+ CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X),
+ CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X),
+ CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X),
- CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X),
- CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X),
- CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X),
- CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X),
- CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X),
- CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X),
- CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X),
- CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X),
- CLK(NULL, "pdm_ck", &pdm_ck, CK_443X),
- CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X),
- CLK("omap_rng", "ick", &rng_ck, CK_443X),
- CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X),
- CLK(NULL, "sl2_ck", &sl2_ck, CK_443X),
- CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X),
- CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X),
- CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X),
- CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X),
- CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X),
- CLK(NULL, "tesla_ck", &tesla_ck, CK_443X),
- CLK(NULL, "uart1_ck", &uart1_ck, CK_443X),
- CLK(NULL, "uart2_ck", &uart2_ck, CK_443X),
- CLK(NULL, "uart3_ck", &uart3_ck, CK_443X),
- CLK(NULL, "uart4_ck", &uart4_ck, CK_443X),
- CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X),
- CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X),
- CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X),
- CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X),
- CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X),
- CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X),
- CLK(NULL, "usim_ck", &usim_ck, CK_443X),
- CLK("omap_wdt", "fck", &wdt2_ck, CK_443X),
- CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X),
+ CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
+ CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
+ CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
+ CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
+ CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
+ CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
+ CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
+ CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
+ CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
+ CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
+ CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X),
+ CLK(NULL, "pdm_fck", &pdm_fck, CK_443X),
+ CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X),
+ CLK("omap_rng", "ick", &rng_ick, CK_443X),
+ CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X),
+ CLK(NULL, "sl2_ick", &sl2_ick, CK_443X),
+ CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
+ CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
+ CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X),
+ CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X),
+ CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X),
+ CLK(NULL, "tesla_ick", &tesla_ick, CK_443X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
+ CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
+ CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
+ CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
+ CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
+ CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X),
+ CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X),
+ CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X),
+ CLK(NULL, "usim_fck", &usim_fck, CK_443X),
+ CLK("omap_wdt", "fck", &wdt2_fck, CK_443X),
+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
-};
-
-int __init omap2_clk_init(void)
+ CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
+ CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
+ CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
+ CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
+ CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
+ CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
+ CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
+ CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
+ CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
+ CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
+ CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
+};
+
+int __init omap4xxx_clk_init(void)
{
- /* struct prcm_config *prcm; */
struct omap_clk *c;
- /* u32 clkrate; */
u32 cpu_clkflg;
if (cpu_is_omap44xx()) {
@@ -2749,9 +2703,7 @@ int __init omap2_clk_init(void)
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
clk_register(c->lk.clk);
- /* TODO
omap2_init_clk_clkdm(c->lk.clk);
- */
}
recalculate_root_clocks();
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 1a45ed1e8ba..6e568ec995e 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1,10 +1,11 @@
/*
- * OMAP2/3 clockdomain framework functions
+ * OMAP2/3/4 clockdomain framework functions
*
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
*
* Written by Paul Walmsley and Jouni Högander
+ * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -26,43 +27,124 @@
#include <linux/bitops.h>
-#include <plat/clock.h>
-
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
+#include <plat/clock.h>
#include <plat/powerdomain.h>
#include <plat/clockdomain.h>
+#include <plat/prcm.h>
/* clkdm_list contains all registered struct clockdomains */
static LIST_HEAD(clkdm_list);
-/* clkdm_mutex protects clkdm_list add and del ops */
-static DEFINE_MUTEX(clkdm_mutex);
-
-/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */
-static struct clkdm_pwrdm_autodep *autodeps;
+/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
+static struct clkdm_autodep *autodeps;
/* Private functions */
+static struct clockdomain *_clkdm_lookup(const char *name)
+{
+ struct clockdomain *clkdm, *temp_clkdm;
+
+ if (!name)
+ return NULL;
+
+ clkdm = NULL;
+
+ list_for_each_entry(temp_clkdm, &clkdm_list, node) {
+ if (!strcmp(name, temp_clkdm->name)) {
+ clkdm = temp_clkdm;
+ break;
+ }
+ }
+
+ return clkdm;
+}
+
+/**
+ * _clkdm_register - register a clockdomain
+ * @clkdm: struct clockdomain * to register
+ *
+ * Adds a clockdomain to the internal clockdomain list.
+ * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
+ * already registered by the provided name, or 0 upon success.
+ */
+static int _clkdm_register(struct clockdomain *clkdm)
+{
+ struct powerdomain *pwrdm;
+
+ if (!clkdm || !clkdm->name)
+ return -EINVAL;
+
+ if (!omap_chip_is(clkdm->omap_chip))
+ return -EINVAL;
+
+ pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
+ if (!pwrdm) {
+ pr_err("clockdomain: %s: powerdomain %s does not exist\n",
+ clkdm->name, clkdm->pwrdm.name);
+ return -EINVAL;
+ }
+ clkdm->pwrdm.ptr = pwrdm;
+
+ /* Verify that the clockdomain is not already registered */
+ if (_clkdm_lookup(clkdm->name))
+ return -EEXIST;
+
+ list_add(&clkdm->node, &clkdm_list);
+
+ pwrdm_add_clkdm(pwrdm, clkdm);
+
+ pr_debug("clockdomain: registered %s\n", clkdm->name);
+
+ return 0;
+}
+
+/* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */
+static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
+ struct clkdm_dep *deps)
+{
+ struct clkdm_dep *cd;
+
+ if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
+ return ERR_PTR(-EINVAL);
+
+ for (cd = deps; cd->clkdm_name; cd++) {
+ if (!omap_chip_is(cd->omap_chip))
+ continue;
+
+ if (!cd->clkdm && cd->clkdm_name)
+ cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
+ if (cd->clkdm == clkdm)
+ break;
+ }
+
+ if (!cd->clkdm_name)
+ return ERR_PTR(-ENOENT);
+
+ return cd;
+}
+
/*
- * _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store
- * @autodep: struct clkdm_pwrdm_autodep * to resolve
+ * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
+ * @autodep: struct clkdm_autodep * to resolve
*
- * Resolve autodep powerdomain names to powerdomain pointers via
- * pwrdm_lookup() and store the pointers in the autodep structure. An
- * "autodep" is a powerdomain sleep/wakeup dependency that is
+ * Resolve autodep clockdomain names to clockdomain pointers via
+ * clkdm_lookup() and store the pointers in the autodep structure. An
+ * "autodep" is a clockdomain sleep/wakeup dependency that is
* automatically added and removed whenever clocks in the associated
* clockdomain are enabled or disabled (respectively) when the
* clockdomain is in hardware-supervised mode. Meant to be called
* once at clockdomain layer initialization, since these should remain
* fixed for a particular architecture. No return value.
*/
-static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
+static void _autodep_lookup(struct clkdm_autodep *autodep)
{
- struct powerdomain *pwrdm;
+ struct clockdomain *clkdm;
if (!autodep)
return;
@@ -70,13 +152,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
if (!omap_chip_is(autodep->omap_chip))
return;
- pwrdm = pwrdm_lookup(autodep->pwrdm.name);
- if (!pwrdm) {
- pr_err("clockdomain: autodeps: powerdomain %s does not exist\n",
- autodep->pwrdm.name);
- pwrdm = ERR_PTR(-ENOENT);
+ clkdm = clkdm_lookup(autodep->clkdm.name);
+ if (!clkdm) {
+ pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
+ autodep->clkdm.name);
+ clkdm = ERR_PTR(-ENOENT);
}
- autodep->pwrdm.ptr = pwrdm;
+ autodep->clkdm.ptr = clkdm;
}
/*
@@ -89,21 +171,24 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
*/
static void _clkdm_add_autodeps(struct clockdomain *clkdm)
{
- struct clkdm_pwrdm_autodep *autodep;
+ struct clkdm_autodep *autodep;
- for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
- if (IS_ERR(autodep->pwrdm.ptr))
+ if (!autodeps)
+ return;
+
+ for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+ if (IS_ERR(autodep->clkdm.ptr))
continue;
if (!omap_chip_is(autodep->omap_chip))
continue;
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
- "pwrdm %s\n", autodep->pwrdm.ptr->name,
- clkdm->pwrdm.ptr->name);
+ "clkdm %s\n", autodep->clkdm.ptr->name,
+ clkdm->name);
- pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
- pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+ clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
+ clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
}
}
@@ -117,21 +202,24 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
*/
static void _clkdm_del_autodeps(struct clockdomain *clkdm)
{
- struct clkdm_pwrdm_autodep *autodep;
+ struct clkdm_autodep *autodep;
+
+ if (!autodeps)
+ return;
- for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
- if (IS_ERR(autodep->pwrdm.ptr))
+ for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+ if (IS_ERR(autodep->clkdm.ptr))
continue;
if (!omap_chip_is(autodep->omap_chip))
continue;
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
- "pwrdm %s\n", autodep->pwrdm.ptr->name,
- clkdm->pwrdm.ptr->name);
+ "clkdm %s\n", autodep->clkdm.ptr->name,
+ clkdm->name);
- pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
- pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+ clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
+ clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
}
}
@@ -145,152 +233,167 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
*/
static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
{
- u32 v;
+ u32 bits, v;
if (cpu_is_omap24xx()) {
if (enable)
- v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
+ bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
else
- v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
- } else if (cpu_is_omap34xx()) {
+ bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
if (enable)
- v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
+ bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
else
- v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
+ bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
} else {
BUG();
}
- cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
- v << __ffs(clkdm->clktrctrl_mask),
- clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
-}
-
-static struct clockdomain *_clkdm_lookup(const char *name)
-{
- struct clockdomain *clkdm, *temp_clkdm;
-
- if (!name)
- return NULL;
-
- clkdm = NULL;
+ bits = bits << __ffs(clkdm->clktrctrl_mask);
- list_for_each_entry(temp_clkdm, &clkdm_list, node) {
- if (!strcmp(name, temp_clkdm->name)) {
- clkdm = temp_clkdm;
- break;
- }
- }
+ v = __raw_readl(clkdm->clkstctrl_reg);
+ v &= ~(clkdm->clktrctrl_mask);
+ v |= bits;
+ __raw_writel(v, clkdm->clkstctrl_reg);
- return clkdm;
}
-
-/* Public functions */
-
/**
- * clkdm_init - set up the clockdomain layer
- * @clkdms: optional pointer to an array of clockdomains to register
- * @init_autodeps: optional pointer to an array of autodeps to register
+ * _init_wkdep_usecount - initialize wkdep usecounts to match hardware
+ * @clkdm: clockdomain to initialize wkdep usecounts
*
- * Set up internal state. If a pointer to an array of clockdomains
- * was supplied, loop through the list of clockdomains, register all
- * that are available on the current platform. Similarly, if a
- * pointer to an array of clockdomain-powerdomain autodependencies was
- * provided, register those. No return value.
+ * Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
+ * If a wakeup dependency is present in the hardware, the usecount will be
+ * set to 1; otherwise, it will be set to 0. Software should clear all
+ * software wakeup dependencies prior to calling this function if it wishes
+ * to ensure that all usecounts start at 0. No return value.
*/
-void clkdm_init(struct clockdomain **clkdms,
- struct clkdm_pwrdm_autodep *init_autodeps)
+static void _init_wkdep_usecount(struct clockdomain *clkdm)
{
- struct clockdomain **c = NULL;
- struct clkdm_pwrdm_autodep *autodep = NULL;
+ u32 v;
+ struct clkdm_dep *cd;
- if (clkdms)
- for (c = clkdms; *c; c++)
- clkdm_register(*c);
+ if (!clkdm->wkdep_srcs)
+ return;
- autodeps = init_autodeps;
- if (autodeps)
- for (autodep = autodeps; autodep->pwrdm.ptr; autodep++)
- _autodep_lookup(autodep);
+ for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
+ if (!omap_chip_is(cd->omap_chip))
+ continue;
+
+ if (!cd->clkdm && cd->clkdm_name)
+ cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
+ if (!cd->clkdm) {
+ WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
+ "found\n", clkdm->name, cd->clkdm_name);
+ continue;
+ }
+
+ v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
+ PM_WKDEP,
+ (1 << cd->clkdm->dep_bit));
+
+ if (v)
+ pr_debug("clockdomain: %s: wakeup dependency already "
+ "set to wake up when %s wakes\n",
+ clkdm->name, cd->clkdm->name);
+
+ atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
+ }
}
/**
- * clkdm_register - register a clockdomain
- * @clkdm: struct clockdomain * to register
+ * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
+ * @clkdm: clockdomain to initialize sleepdep usecounts
*
- * Adds a clockdomain to the internal clockdomain list.
- * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
- * already registered by the provided name, or 0 upon success.
+ * Initialize the sleep dependency usecount variables for clockdomain @clkdm.
+ * If a sleep dependency is present in the hardware, the usecount will be
+ * set to 1; otherwise, it will be set to 0. Software should clear all
+ * software sleep dependencies prior to calling this function if it wishes
+ * to ensure that all usecounts start at 0. No return value.
*/
-int clkdm_register(struct clockdomain *clkdm)
+static void _init_sleepdep_usecount(struct clockdomain *clkdm)
{
- int ret = -EINVAL;
- struct powerdomain *pwrdm;
+ u32 v;
+ struct clkdm_dep *cd;
- if (!clkdm || !clkdm->name)
- return -EINVAL;
+ if (!cpu_is_omap34xx())
+ return;
- if (!omap_chip_is(clkdm->omap_chip))
- return -EINVAL;
+ if (!clkdm->sleepdep_srcs)
+ return;
- pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
- if (!pwrdm) {
- pr_err("clockdomain: %s: powerdomain %s does not exist\n",
- clkdm->name, clkdm->pwrdm.name);
- return -EINVAL;
- }
- clkdm->pwrdm.ptr = pwrdm;
+ for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
+ if (!omap_chip_is(cd->omap_chip))
+ continue;
- mutex_lock(&clkdm_mutex);
- /* Verify that the clockdomain is not already registered */
- if (_clkdm_lookup(clkdm->name)) {
- ret = -EEXIST;
- goto cr_unlock;
- }
+ if (!cd->clkdm && cd->clkdm_name)
+ cd->clkdm = _clkdm_lookup(cd->clkdm_name);
- list_add(&clkdm->node, &clkdm_list);
+ if (!cd->clkdm) {
+ WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
+ "not found\n", clkdm->name, cd->clkdm_name);
+ continue;
+ }
- pwrdm_add_clkdm(pwrdm, clkdm);
+ v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
+ OMAP3430_CM_SLEEPDEP,
+ (1 << cd->clkdm->dep_bit));
- pr_debug("clockdomain: registered %s\n", clkdm->name);
- ret = 0;
+ if (v)
+ pr_debug("clockdomain: %s: sleep dependency already "
+ "set to prevent from idling until %s "
+ "idles\n", clkdm->name, cd->clkdm->name);
-cr_unlock:
- mutex_unlock(&clkdm_mutex);
+ atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
+ }
+};
- return ret;
-}
+/* Public functions */
/**
- * clkdm_unregister - unregister a clockdomain
- * @clkdm: struct clockdomain * to unregister
+ * clkdm_init - set up the clockdomain layer
+ * @clkdms: optional pointer to an array of clockdomains to register
+ * @init_autodeps: optional pointer to an array of autodeps to register
*
- * Removes a clockdomain from the internal clockdomain list. Returns
- * -EINVAL if clkdm argument is NULL.
+ * Set up internal state. If a pointer to an array of clockdomains
+ * @clkdms was supplied, loop through the list of clockdomains,
+ * register all that are available on the current platform. Similarly,
+ * if a pointer to an array of clockdomain autodependencies
+ * @init_autodeps was provided, register those. No return value.
*/
-int clkdm_unregister(struct clockdomain *clkdm)
+void clkdm_init(struct clockdomain **clkdms,
+ struct clkdm_autodep *init_autodeps)
{
- if (!clkdm)
- return -EINVAL;
-
- pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm);
+ struct clockdomain **c = NULL;
+ struct clockdomain *clkdm;
+ struct clkdm_autodep *autodep = NULL;
- mutex_lock(&clkdm_mutex);
- list_del(&clkdm->node);
- mutex_unlock(&clkdm_mutex);
+ if (clkdms)
+ for (c = clkdms; *c; c++)
+ _clkdm_register(*c);
- pr_debug("clockdomain: unregistered %s\n", clkdm->name);
+ autodeps = init_autodeps;
+ if (autodeps)
+ for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
+ _autodep_lookup(autodep);
- return 0;
+ /*
+ * Ensure that the *dep_usecount registers reflect the current
+ * state of the PRCM.
+ */
+ list_for_each_entry(clkdm, &clkdm_list, node) {
+ _init_wkdep_usecount(clkdm);
+ _init_sleepdep_usecount(clkdm);
+ }
}
/**
* clkdm_lookup - look up a clockdomain by name, return a pointer
* @name: name of clockdomain
*
- * Find a registered clockdomain by its name. Returns a pointer to the
- * struct clockdomain if found, or NULL otherwise.
+ * Find a registered clockdomain by its name @name. Returns a pointer
+ * to the struct clockdomain if found, or NULL otherwise.
*/
struct clockdomain *clkdm_lookup(const char *name)
{
@@ -301,14 +404,12 @@ struct clockdomain *clkdm_lookup(const char *name)
clkdm = NULL;
- mutex_lock(&clkdm_mutex);
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
if (!strcmp(name, temp_clkdm->name)) {
clkdm = temp_clkdm;
break;
}
}
- mutex_unlock(&clkdm_mutex);
return clkdm;
}
@@ -317,8 +418,8 @@ struct clockdomain *clkdm_lookup(const char *name)
* clkdm_for_each - call function on each registered clockdomain
* @fn: callback function *
*
- * Call the supplied function for each registered clockdomain.
- * The callback function can return anything but 0 to bail
+ * Call the supplied function @fn for each registered clockdomain.
+ * The callback function @fn can return anything but 0 to bail
* out early from the iterator. The callback function is called with
* the clkdm_mutex held, so no clockdomain structure manipulation
* functions should be called from the callback, although hardware
@@ -336,13 +437,11 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
if (!fn)
return -EINVAL;
- mutex_lock(&clkdm_mutex);
list_for_each_entry(clkdm, &clkdm_list, node) {
ret = (*fn)(clkdm, user);
if (ret)
break;
}
- mutex_unlock(&clkdm_mutex);
return ret;
}
@@ -353,7 +452,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
* @clkdm: struct clockdomain *
*
* Return a pointer to the struct powerdomain that the specified clockdomain
- * 'clkdm' exists in, or returns NULL if clkdm argument is NULL.
+ * @clkdm exists in, or returns NULL if @clkdm is NULL.
*/
struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
{
@@ -367,11 +466,309 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
/* Hardware clockdomain control */
/**
+ * clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
+ *
+ * When the clockdomain represented by @clkdm2 wakes up, wake up
+ * @clkdm1. Implemented in hardware on the OMAP, this feature is
+ * designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
+ * Returns -EINVAL if presented with invalid clockdomain pointers,
+ * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
+ * success.
+ */
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+ struct clkdm_dep *cd;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ if (IS_ERR(cd)) {
+ pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ return PTR_ERR(cd);
+ }
+
+ if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
+ pr_debug("clockdomain: hardware will wake up %s when %s wakes "
+ "up\n", clkdm1->name, clkdm2->name);
+
+ prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+ clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+ }
+
+ return 0;
+}
+
+/**
+ * clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
+ *
+ * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
+ * wakes up. Returns -EINVAL if presented with invalid clockdomain
+ * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
+ * 0 upon success.
+ */
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+ struct clkdm_dep *cd;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ if (IS_ERR(cd)) {
+ pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ return PTR_ERR(cd);
+ }
+
+ if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
+ pr_debug("clockdomain: hardware will no longer wake up %s "
+ "after %s wakes up\n", clkdm1->name, clkdm2->name);
+
+ prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+ clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+ }
+
+ return 0;
+}
+
+/**
+ * clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
+ *
+ * Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be
+ * awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL
+ * if either clockdomain pointer is invalid; or -ENOENT if the hardware
+ * is incapable.
+ *
+ * REVISIT: Currently this function only represents software-controllable
+ * wakeup dependencies. Wakeup dependencies fixed in hardware are not
+ * yet handled here.
+ */
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+ struct clkdm_dep *cd;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ if (IS_ERR(cd)) {
+ pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ return PTR_ERR(cd);
+ }
+
+ /* XXX It's faster to return the atomic wkdep_usecount */
+ return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
+ (1 << clkdm2->dep_bit));
+}
+
+/**
+ * clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm
+ * @clkdm: struct clockdomain * to remove all wakeup dependencies from
+ *
+ * Remove all inter-clockdomain wakeup dependencies that could cause
+ * @clkdm to wake. Intended to be used during boot to initialize the
+ * PRCM to a known state, after all clockdomains are put into swsup idle
+ * and woken up. Returns -EINVAL if @clkdm pointer is invalid, or
+ * 0 upon success.
+ */
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+{
+ struct clkdm_dep *cd;
+ u32 mask = 0;
+
+ if (!clkdm)
+ return -EINVAL;
+
+ for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+ if (!omap_chip_is(cd->omap_chip))
+ continue;
+
+ /* PRM accesses are slow, so minimize them */
+ mask |= 1 << cd->clkdm->dep_bit;
+ atomic_set(&cd->wkdep_usecount, 0);
+ }
+
+ prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
+
+ return 0;
+}
+
+/**
+ * clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
+ *
+ * Prevent @clkdm1 from automatically going inactive (and then to
+ * retention or off) if @clkdm2 is active. Returns -EINVAL if
+ * presented with invalid clockdomain pointers or called on a machine
+ * that does not support software-configurable hardware sleep
+ * dependencies, -ENOENT if the specified dependency cannot be set in
+ * hardware, or 0 upon success.
+ */
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+ struct clkdm_dep *cd;
+
+ if (!cpu_is_omap34xx())
+ return -EINVAL;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+ if (IS_ERR(cd)) {
+ pr_debug("clockdomain: hardware cannot set/clear sleep "
+ "dependency affecting %s from %s\n", clkdm1->name,
+ clkdm2->name);
+ return PTR_ERR(cd);
+ }
+
+ if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
+ pr_debug("clockdomain: will prevent %s from sleeping if %s "
+ "is active\n", clkdm1->name, clkdm2->name);
+
+ cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+ clkdm1->pwrdm.ptr->prcm_offs,
+ OMAP3430_CM_SLEEPDEP);
+ }
+
+ return 0;
+}
+
+/**
+ * clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
+ *
+ * Allow @clkdm1 to automatically go inactive (and then to retention or
+ * off), independent of the activity state of @clkdm2. Returns -EINVAL
+ * if presented with invalid clockdomain pointers or called on a machine
+ * that does not support software-configurable hardware sleep dependencies,
+ * -ENOENT if the specified dependency cannot be cleared in hardware, or
+ * 0 upon success.
+ */
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+ struct clkdm_dep *cd;
+
+ if (!cpu_is_omap34xx())
+ return -EINVAL;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+ if (IS_ERR(cd)) {
+ pr_debug("clockdomain: hardware cannot set/clear sleep "
+ "dependency affecting %s from %s\n", clkdm1->name,
+ clkdm2->name);
+ return PTR_ERR(cd);
+ }
+
+ if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
+ pr_debug("clockdomain: will no longer prevent %s from "
+ "sleeping if %s is active\n", clkdm1->name,
+ clkdm2->name);
+
+ cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+ clkdm1->pwrdm.ptr->prcm_offs,
+ OMAP3430_CM_SLEEPDEP);
+ }
+
+ return 0;
+}
+
+/**
+ * clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
+ *
+ * Return 1 if a hardware sleep dependency exists wherein @clkdm1 will
+ * not be allowed to automatically go inactive if @clkdm2 is active;
+ * 0 if @clkdm1's automatic power state inactivity transition is independent
+ * of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called
+ * on a machine that does not support software-configurable hardware sleep
+ * dependencies; or -ENOENT if the hardware is incapable.
+ *
+ * REVISIT: Currently this function only represents software-controllable
+ * sleep dependencies. Sleep dependencies fixed in hardware are not
+ * yet handled here.
+ */
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+ struct clkdm_dep *cd;
+
+ if (!cpu_is_omap34xx())
+ return -EINVAL;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+ if (IS_ERR(cd)) {
+ pr_debug("clockdomain: hardware cannot set/clear sleep "
+ "dependency affecting %s from %s\n", clkdm1->name,
+ clkdm2->name);
+ return PTR_ERR(cd);
+ }
+
+ /* XXX It's faster to return the atomic sleepdep_usecount */
+ return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+ OMAP3430_CM_SLEEPDEP,
+ (1 << clkdm2->dep_bit));
+}
+
+/**
+ * clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm
+ * @clkdm: struct clockdomain * to remove all sleep dependencies from
+ *
+ * Remove all inter-clockdomain sleep dependencies that could prevent
+ * @clkdm from idling. Intended to be used during boot to initialize the
+ * PRCM to a known state, after all clockdomains are put into swsup idle
+ * and woken up. Returns -EINVAL if @clkdm pointer is invalid, or
+ * 0 upon success.
+ */
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+{
+ struct clkdm_dep *cd;
+ u32 mask = 0;
+
+ if (!cpu_is_omap34xx())
+ return -EINVAL;
+
+ if (!clkdm)
+ return -EINVAL;
+
+ for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+ if (!omap_chip_is(cd->omap_chip))
+ continue;
+
+ /* PRM accesses are slow, so minimize them */
+ mask |= 1 << cd->clkdm->dep_bit;
+ atomic_set(&cd->sleepdep_usecount, 0);
+ }
+
+ prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+ OMAP3430_CM_SLEEPDEP);
+
+ return 0;
+}
+
+/**
* omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
- * @clk: struct clk * of a clockdomain
+ * @clkdm: struct clkdm * of a clockdomain
*
- * Return the clockdomain's current state transition mode from the
- * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk
+ * Return the clockdomain @clkdm current state transition mode from the
+ * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if @clkdm
* is NULL or the current mode upon success.
*/
static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
@@ -381,7 +778,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
if (!clkdm)
return -EINVAL;
- v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+ v = __raw_readl(clkdm->clkstctrl_reg);
v &= clkdm->clktrctrl_mask;
v >>= __ffs(clkdm->clktrctrl_mask);
@@ -393,7 +790,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a sleep transition on the specified
- * clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if
+ * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if
* clockdomain does not support software-initiated sleep; 0 upon
* success.
*/
@@ -413,15 +810,17 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
if (cpu_is_omap24xx()) {
cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
- clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
+ u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
__ffs(clkdm->clktrctrl_mask));
- cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
- clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+ u32 v = __raw_readl(clkdm->clkstctrl_reg);
+ v &= ~(clkdm->clktrctrl_mask);
+ v |= bits;
+ __raw_writel(v, clkdm->clkstctrl_reg);
} else {
BUG();
@@ -435,7 +834,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
* @clkdm: struct clockdomain *
*
* Instruct the CM to force a wakeup transition on the specified
- * clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the
+ * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the
* clockdomain does not support software-controlled wakeup; 0 upon
* success.
*/
@@ -455,15 +854,17 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
if (cpu_is_omap24xx()) {
cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
- clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
- u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
+ u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
__ffs(clkdm->clktrctrl_mask));
- cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
- clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+ u32 v = __raw_readl(clkdm->clkstctrl_reg);
+ v &= ~(clkdm->clktrctrl_mask);
+ v |= bits;
+ __raw_writel(v, clkdm->clkstctrl_reg);
} else {
BUG();
@@ -476,7 +877,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
* omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
* @clkdm: struct clockdomain *
*
- * Allow the hardware to automatically switch the clockdomain into
+ * Allow the hardware to automatically switch the clockdomain @clkdm into
* active or idle states, as needed by downstream clocks. If the
* clockdomain has any downstream clocks enabled in the clock
* framework, wkdep/sleepdep autodependencies are added; this is so
@@ -496,8 +897,17 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
clkdm->name);
- if (atomic_read(&clkdm->usecount) > 0)
- _clkdm_add_autodeps(clkdm);
+ /*
+ * XXX This should be removed once TI adds wakeup/sleep
+ * dependency code and data for OMAP4.
+ */
+ if (cpu_is_omap44xx()) {
+ WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency "
+ "support is not yet implemented\n");
+ } else {
+ if (atomic_read(&clkdm->usecount) > 0)
+ _clkdm_add_autodeps(clkdm);
+ }
_omap2_clkdm_set_hwsup(clkdm, 1);
@@ -509,8 +919,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
* @clkdm: struct clockdomain *
*
* Prevent the hardware from automatically switching the clockdomain
- * into inactive or idle states. If the clockdomain has downstream
- * clocks enabled in the clock framework, wkdep/sleepdep
+ * @clkdm into inactive or idle states. If the clockdomain has
+ * downstream clocks enabled in the clock framework, wkdep/sleepdep
* autodependencies are removed. No return value.
*/
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
@@ -529,8 +939,17 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
_omap2_clkdm_set_hwsup(clkdm, 0);
- if (atomic_read(&clkdm->usecount) > 0)
- _clkdm_del_autodeps(clkdm);
+ /*
+ * XXX This should be removed once TI adds wakeup/sleep
+ * dependency code and data for OMAP4.
+ */
+ if (cpu_is_omap44xx()) {
+ WARN_ONCE(1, "clockdomain: OMAP4 wakeup/sleep dependency "
+ "support is not yet implemented\n");
+ } else {
+ if (atomic_read(&clkdm->usecount) > 0)
+ _clkdm_del_autodeps(clkdm);
+ }
}
@@ -541,14 +960,14 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
* @clkdm: struct clockdomain *
* @clk: struct clk * of the enabled downstream clock
*
- * Increment the usecount of this clockdomain 'clkdm' and ensure that
- * it is awake. Intended to be called by clk_enable() code. If the
- * clockdomain is in software-supervised idle mode, force the
- * clockdomain to wake. If the clockdomain is in hardware-supervised
- * idle mode, add clkdm-pwrdm autodependencies, to ensure that devices
- * in the clockdomain can be read from/written to by on-chip processors.
- * Returns -EINVAL if passed null pointers; returns 0 upon success or
- * if the clockdomain is in hwsup idle mode.
+ * Increment the usecount of the clockdomain @clkdm and ensure that it
+ * is awake before @clk is enabled. Intended to be called by
+ * clk_enable() code. If the clockdomain is in software-supervised
+ * idle mode, force the clockdomain to wake. If the clockdomain is in
+ * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
+ * ensure that devices in the clockdomain can be read from/written to
+ * by on-chip processors. Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
{
@@ -570,6 +989,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
clk->name);
+ if (!clkdm->clkstctrl_reg)
+ return 0;
+
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
@@ -593,13 +1015,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
* @clkdm: struct clockdomain *
* @clk: struct clk * of the disabled downstream clock
*
- * Decrement the usecount of this clockdomain 'clkdm'. Intended to be
- * called by clk_disable() code. If the usecount goes to 0, put the
- * clockdomain to sleep (software-supervised mode) or remove the
- * clkdm-pwrdm autodependencies (hardware-supervised mode). Returns
- * -EINVAL if passed null pointers; -ERANGE if the clkdm usecount
- * underflows and debugging is enabled; or returns 0 upon success or
- * if the clockdomain is in hwsup idle mode.
+ * Decrement the usecount of this clockdomain @clkdm when @clk is
+ * disabled. Intended to be called by clk_disable() code. If the
+ * clockdomain usecount goes to 0, put the clockdomain to sleep
+ * (software-supervised mode) or remove the clkdm autodependencies
+ * (hardware-supervised mode). Returns -EINVAL if passed null
+ * pointers; -ERANGE if the @clkdm usecount underflows and debugging
+ * is enabled; or returns 0 upon success or if the clockdomain is in
+ * hwsup idle mode.
*/
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
@@ -628,6 +1051,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
clk->name);
+ if (!clkdm->clkstctrl_reg)
+ return 0;
+
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index c4ee0761d90..8fc19ff2cd8 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -1,16 +1,420 @@
/*
* OMAP2/3 clockdomains
*
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
*
- * Written by Paul Walmsley
+ * Written by Paul Walmsley and Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup/sleep
+ * dependencies for the OMAP2/3 chips. Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs or sleepdep_srcs array must have a
+ * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
+ * software-controllable dependencies. Non-software-controllable
+ * dependencies do exist, but they are not encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ * from the Power domain framework
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
#include <plat/clockdomain.h>
+#include "cm.h"
+#include "prm.h"
+
+/*
+ * Clockdomain dependencies for wkdeps/sleepdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+
+/* OMAP2/3-common wakeup dependencies */
+
+/*
+ * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
+ * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
+ * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
+ CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
+ CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+
+/* 24XX-specific possible dependencies */
+
+#ifdef CONFIG_ARCH_OMAP2
+
+/* Wakeup dependency source arrays */
+
+/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
+static struct clkdm_dep dsp_24xx_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ { NULL },
+};
+
+/*
+ * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
+ * 2430 adds MDM
+ */
+static struct clkdm_dep mpu_24xx_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "dsp_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "mdm_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ },
+ { NULL },
+};
+
+/*
+ * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
+ * 2430 adds MDM
+ */
+static struct clkdm_dep core_24xx_wkdeps[] = {
+ {
+ .clkdm_name = "dsp_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "gfx_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "mdm_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ },
+ { NULL },
+};
+
+#endif
+
+
+/* 2430-specific possible wakeup dependencies */
+
+#ifdef CONFIG_ARCH_OMAP2430
+
+/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+static struct clkdm_dep mdm_2430_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+ },
+ { NULL },
+};
+
+#endif /* CONFIG_ARCH_OMAP2430 */
+
+
+/* OMAP3-specific possible dependencies */
+
+#ifdef CONFIG_ARCH_OMAP3
+
+/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep per_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep usbhost_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "dss_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "per_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
+static struct clkdm_dep iva2_wkdeps[] = {
+ {
+ .clkdm_name = "core_l3_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "core_l4_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "dss_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "per_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+
+/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
+static struct clkdm_dep cam_wkdeps[] = {
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
+static struct clkdm_dep dss_wkdeps[] = {
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "wkup_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430: PM_WKDEP_NEON: MPU */
+static struct clkdm_dep neon_wkdeps[] = {
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+
+/* Sleep dependency source arrays for OMAP3-specific clkdms */
+
+/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
+static struct clkdm_dep dss_sleepdeps[] = {
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
+static struct clkdm_dep per_sleepdeps[] = {
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
+static struct clkdm_dep usbhost_sleepdeps[] = {
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ {
+ .clkdm_name = "iva2_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/* 3430: CM_SLEEPDEP_CAM: MPU */
+static struct clkdm_dep cam_sleepdeps[] = {
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+/*
+ * 3430ES1: CM_SLEEPDEP_GFX: MPU
+ * 3430ES2: CM_SLEEPDEP_SGX: MPU
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_sleepdeps[] = {
+ {
+ .clkdm_name = "mpu_clkdm",
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ },
+ { NULL },
+};
+
+#endif /* CONFIG_ARCH_OMAP3 */
+
/*
* OMAP2/3-common clockdomains
@@ -21,10 +425,13 @@
* sys_clkout/sys_clkout2.
*/
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
.name = "wkup_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
+ .dep_bit = OMAP_EN_WKUP_SHIFT,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
@@ -40,6 +447,8 @@ static struct clockdomain cm_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};
+#endif
+
/*
* 2420-only clockdomains
*/
@@ -50,6 +459,8 @@ static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = mpu_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
@@ -58,11 +469,64 @@ static struct clockdomain iva1_2420_clkdm = {
.name = "iva1_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+ .wkdep_srcs = dsp_24xx_wkdeps,
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
-#endif /* CONFIG_ARCH_OMAP2420 */
+static struct clockdomain dsp_2420_clkdm = {
+ .name = "dsp_clkdm",
+ .pwrdm = { .name = "dsp_pwrdm" },
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain gfx_2420_clkdm = {
+ .name = "gfx_clkdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = gfx_sgx_wkdeps,
+ .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain core_l3_2420_clkdm = {
+ .name = "core_l3_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = core_24xx_wkdeps,
+ .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain core_l4_2420_clkdm = {
+ .name = "core_l4_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = core_24xx_wkdeps,
+ .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain dss_2420_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+#endif /* CONFIG_ARCH_OMAP2420 */
/*
@@ -75,80 +539,105 @@ static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = mpu_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
+/* Another case of bit name collisions between several registers: EN_MDM */
static struct clockdomain mdm_clkdm = {
.name = "mdm_clkdm",
.pwrdm = { .name = "mdm_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
+ .wkdep_srcs = mdm_2430_wkdeps,
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-#endif /* CONFIG_ARCH_OMAP2430 */
-
-
-/*
- * 24XX-only clockdomains
- */
-
-#if defined(CONFIG_ARCH_OMAP24XX)
-
-static struct clockdomain dsp_clkdm = {
+static struct clockdomain dsp_2430_clkdm = {
.name = "dsp_clkdm",
.pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+ .wkdep_srcs = dsp_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-static struct clockdomain gfx_24xx_clkdm = {
+static struct clockdomain gfx_2430_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = gfx_sgx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-static struct clockdomain core_l3_24xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_2430_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP24XX_EN_CORE_SHIFT,
+ .wkdep_srcs = core_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-static struct clockdomain core_l4_24xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_2430_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP24XX_EN_CORE_SHIFT,
+ .wkdep_srcs = core_24xx_wkdeps,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-static struct clockdomain dss_24xx_clkdm = {
+static struct clockdomain dss_2430_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-#endif /* CONFIG_ARCH_OMAP24XX */
+#endif /* CONFIG_ARCH_OMAP2430 */
/*
- * 34xx clockdomains
+ * OMAP3 clockdomains
*/
-#if defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP3)
-static struct clockdomain mpu_34xx_clkdm = {
+static struct clockdomain mpu_3xxx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP3430_EN_MPU_SHIFT,
+ .wkdep_srcs = mpu_3xxx_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -157,6 +646,9 @@ static struct clockdomain neon_clkdm = {
.name = "neon_clkdm",
.pwrdm = { .name = "neon_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = neon_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -165,6 +657,10 @@ static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
.pwrdm = { .name = "iva2_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
+ .wkdep_srcs = iva2_wkdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -173,6 +669,9 @@ static struct clockdomain gfx_3430es1_clkdm = {
.name = "gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = gfx_sgx_wkdeps,
+ .sleepdep_srcs = gfx_sgx_sleepdeps,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
};
@@ -181,6 +680,10 @@ static struct clockdomain sgx_clkdm = {
.name = "sgx_clkdm",
.pwrdm = { .name = "sgx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = gfx_sgx_wkdeps,
+ .sleepdep_srcs = gfx_sgx_sleepdeps,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
@@ -196,30 +699,51 @@ static struct clockdomain d2d_clkdm = {
.name = "d2d_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
-static struct clockdomain core_l3_34xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_3xxx_clkdm = {
.name = "core_l3_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP3430_EN_CORE_SHIFT,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
-static struct clockdomain core_l4_34xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_3xxx_clkdm = {
.name = "core_l4_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP3430_EN_CORE_SHIFT,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
-static struct clockdomain dss_34xx_clkdm = {
+/* Another case of bit name collisions between several registers: EN_DSS */
+static struct clockdomain dss_3xxx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "dss_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+ .wkdep_srcs = dss_wkdeps,
+ .sleepdep_srcs = dss_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -228,6 +752,10 @@ static struct clockdomain cam_clkdm = {
.name = "cam_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = cam_wkdeps,
+ .sleepdep_srcs = cam_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -236,6 +764,10 @@ static struct clockdomain usbhost_clkdm = {
.name = "usbhost_clkdm",
.pwrdm = { .name = "usbhost_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .wkdep_srcs = usbhost_wkdeps,
+ .sleepdep_srcs = usbhost_sleepdeps,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
@@ -244,6 +776,11 @@ static struct clockdomain per_clkdm = {
.name = "per_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
+ OMAP2_CM_CLKSTCTRL),
+ .dep_bit = OMAP3430_EN_PER_SHIFT,
+ .wkdep_srcs = per_wkdeps,
+ .sleepdep_srcs = per_sleepdeps,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -256,6 +793,8 @@ static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
+ .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
+ OMAP2_CM_CLKSTCTRL),
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -290,64 +829,70 @@ static struct clockdomain dpll5_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};
-#endif /* CONFIG_ARCH_OMAP34XX */
+#endif /* CONFIG_ARCH_OMAP3 */
+
+#include "clockdomains44xx.h"
/*
- * Clockdomain-powerdomain hwsup dependencies (34XX only)
+ * Clockdomain hwsup dependencies (OMAP3 only)
*/
-static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
+static struct clkdm_autodep clkdm_autodeps[] = {
{
- .pwrdm = { .name = "mpu_pwrdm" },
+ .clkdm = { .name = "mpu_clkdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
- .pwrdm = { .name = "iva2_pwrdm" },
+ .clkdm = { .name = "iva2_clkdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
- .pwrdm = { .name = NULL },
+ .clkdm = { .name = NULL },
}
};
/*
- *
+ * List of clockdomain pointers per platform
*/
static struct clockdomain *clockdomains_omap[] = {
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
&wkup_clkdm,
&cm_clkdm,
&prm_clkdm,
+#endif
#ifdef CONFIG_ARCH_OMAP2420
&mpu_2420_clkdm,
&iva1_2420_clkdm,
+ &dsp_2420_clkdm,
+ &gfx_2420_clkdm,
+ &core_l3_2420_clkdm,
+ &core_l4_2420_clkdm,
+ &dss_2420_clkdm,
#endif
#ifdef CONFIG_ARCH_OMAP2430
&mpu_2430_clkdm,
&mdm_clkdm,
+ &dsp_2430_clkdm,
+ &gfx_2430_clkdm,
+ &core_l3_2430_clkdm,
+ &core_l4_2430_clkdm,
+ &dss_2430_clkdm,
#endif
-#ifdef CONFIG_ARCH_OMAP24XX
- &dsp_clkdm,
- &gfx_24xx_clkdm,
- &core_l3_24xx_clkdm,
- &core_l4_24xx_clkdm,
- &dss_24xx_clkdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP34XX
- &mpu_34xx_clkdm,
+#ifdef CONFIG_ARCH_OMAP3
+ &mpu_3xxx_clkdm,
&neon_clkdm,
&iva2_clkdm,
&gfx_3430es1_clkdm,
&sgx_clkdm,
&d2d_clkdm,
- &core_l3_34xx_clkdm,
- &core_l4_34xx_clkdm,
- &dss_34xx_clkdm,
+ &core_l3_3xxx_clkdm,
+ &core_l4_3xxx_clkdm,
+ &dss_3xxx_clkdm,
&cam_clkdm,
&usbhost_clkdm,
&per_clkdm,
@@ -359,6 +904,33 @@ static struct clockdomain *clockdomains_omap[] = {
&dpll5_clkdm,
#endif
+#ifdef CONFIG_ARCH_OMAP4
+ &l4_cefuse_44xx_clkdm,
+ &l4_cfg_44xx_clkdm,
+ &tesla_44xx_clkdm,
+ &l3_gfx_44xx_clkdm,
+ &ivahd_44xx_clkdm,
+ &l4_secure_44xx_clkdm,
+ &l4_per_44xx_clkdm,
+ &abe_44xx_clkdm,
+ &l3_instr_44xx_clkdm,
+ &l3_init_44xx_clkdm,
+ &mpuss_44xx_clkdm,
+ &mpu0_44xx_clkdm,
+ &mpu1_44xx_clkdm,
+ &l3_emif_44xx_clkdm,
+ &l4_ao_44xx_clkdm,
+ &ducati_44xx_clkdm,
+ &l3_2_44xx_clkdm,
+ &l3_1_44xx_clkdm,
+ &l3_d2d_44xx_clkdm,
+ &iss_44xx_clkdm,
+ &l3_dss_44xx_clkdm,
+ &l4_wkup_44xx_clkdm,
+ &emu_sys_44xx_clkdm,
+ &l3_dma_44xx_clkdm,
+#endif
+
NULL,
};
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h
new file mode 100644
index 00000000000..438aaee2e39
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains44xx.h
@@ -0,0 +1,250 @@
+/*
+ * OMAP4 Clock domains framework
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * To-Do List
+ * -> Populate the Sleep/Wakeup dependencies for the domains
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
+
+#include <plat/clockdomain.h>
+
+#if defined(CONFIG_ARCH_OMAP4)
+
+static struct clockdomain l4_cefuse_44xx_clkdm = {
+ .name = "l4_cefuse_clkdm",
+ .pwrdm = { .name = "cefuse_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_cfg_44xx_clkdm = {
+ .name = "l4_cfg_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain tesla_44xx_clkdm = {
+ .name = "tesla_clkdm",
+ .pwrdm = { .name = "tesla_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_gfx_44xx_clkdm = {
+ .name = "l3_gfx_clkdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain ivahd_44xx_clkdm = {
+ .name = "ivahd_clkdm",
+ .pwrdm = { .name = "ivahd_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_secure_44xx_clkdm = {
+ .name = "l4_secure_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_per_44xx_clkdm = {
+ .name = "l4_per_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain abe_44xx_clkdm = {
+ .name = "abe_clkdm",
+ .pwrdm = { .name = "abe_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_instr_44xx_clkdm = {
+ .name = "l3_instr_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_init_44xx_clkdm = {
+ .name = "l3_init_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpuss_44xx_clkdm = {
+ .name = "mpuss_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpu0_44xx_clkdm = {
+ .name = "mpu0_clkdm",
+ .pwrdm = { .name = "cpu0_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpu1_44xx_clkdm = {
+ .name = "mpu1_clkdm",
+ .pwrdm = { .name = "cpu1_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_emif_44xx_clkdm = {
+ .name = "l3_emif_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_ao_44xx_clkdm = {
+ .name = "l4_ao_clkdm",
+ .pwrdm = { .name = "always_on_core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain ducati_44xx_clkdm = {
+ .name = "ducati_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_2_44xx_clkdm = {
+ .name = "l3_2_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_1_44xx_clkdm = {
+ .name = "l3_1_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_d2d_44xx_clkdm = {
+ .name = "l3_d2d_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain iss_44xx_clkdm = {
+ .name = "iss_clkdm",
+ .pwrdm = { .name = "cam_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_dss_44xx_clkdm = {
+ .name = "l3_dss_clkdm",
+ .pwrdm = { .name = "dss_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_wkup_44xx_clkdm = {
+ .name = "l4_wkup_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain emu_sys_44xx_clkdm = {
+ .name = "emu_sys_clkdm",
+ .pwrdm = { .name = "emu_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_dma_44xx_clkdm = {
+ .name = "l3_dma_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
+ .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6923deb98a2..a3a3ca07e38 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -55,7 +55,7 @@
/* Bits specific to each register */
/* CM_FCLKEN_IVA2 */
-#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
/* CM_CLKEN_PLL_IVA2 */
@@ -168,6 +168,12 @@
#define OMAP3430_EN_SDRC (1 << 1)
#define OMAP3430_EN_SDRC_SHIFT 1
+/* AM35XX specific CM_ICLKEN1_CORE bits */
+#define AM35XX_EN_IPSS_MASK (1 << 4)
+#define AM35XX_EN_IPSS_SHIFT 4
+#define AM35XX_EN_UART4_MASK (1 << 23)
+#define AM35XX_EN_UART4_SHIFT 23
+
/* CM_ICLKEN2_CORE */
#define OMAP3430_EN_PKA (1 << 4)
#define OMAP3430_EN_PKA_SHIFT 4
@@ -220,6 +226,10 @@
#define OMAP3430_ST_SSI_STDBY_SHIFT 0
#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
+/* AM35xx specific CM_IDLEST1_CORE bits */
+#define AM35XX_ST_IPSS_SHIFT 5
+#define AM35XX_ST_IPSS_MASK (1 << 5)
+
/* CM_IDLEST2_CORE */
#define OMAP3430_ST_PKA_SHIFT 4
#define OMAP3430_ST_PKA_MASK (1 << 4)
@@ -336,6 +346,8 @@
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKSEL_L3_SHIFT 0
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
+#define OMAP3630_CLKSEL_96M_SHIFT 12
+#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
/* CM_CLKSTCTRL_CORE */
#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
@@ -379,6 +391,10 @@
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
+/* CM_IDLEST_SGX */
+#define OMAP3430ES2_ST_SGX_SHIFT 1
+#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
+
/* CM_ICLKEN_SGX */
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
@@ -517,12 +533,18 @@
/* CM_CLKSEL2_PLL */
#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
+#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
+#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
/* CM_CLKSEL3_PLL */
#define OMAP3430_DIV_96M_SHIFT 0
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
+#define OMAP3630_DIV_96M_MASK (0x3f << 0)
/* CM_CLKSEL4_PLL */
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
@@ -569,8 +591,10 @@
/* CM_CLKSEL_DSS */
#define OMAP3430_CLKSEL_TV_SHIFT 8
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
+#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
+#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
/* CM_SLEEPDEP_DSS specific bits */
@@ -598,6 +622,7 @@
/* CM_CLKSEL_CAM */
#define OMAP3430_CLKSEL_CAM_SHIFT 0
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
+#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
/* CM_SLEEPDEP_CAM specific bits */
@@ -693,6 +718,7 @@
/* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
+#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
#define OMAP3430_DIV_DPLL3_SHIFT 16
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 0e67f75aa35..ac8458e4325 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -26,7 +26,7 @@
/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
-#define OMAP4430_ABE_DYNDEP_SHIFT (1 << 3)
+#define OMAP4430_ABE_DYNDEP_SHIFT 3
#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3)
/*
@@ -34,15 +34,15 @@
* CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
* CM_TESLA_STATICDEP
*/
-#define OMAP4430_ABE_STATDEP_SHIFT (1 << 3)
+#define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3)
/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_ALWONCORE_DYNDEP_SHIFT (1 << 16)
+#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
-#define OMAP4430_ALWONCORE_STATDEP_SHIFT (1 << 16)
+#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16)
/*
@@ -50,371 +50,371 @@
* CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
* CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
*/
-#define OMAP4430_AUTO_DPLL_MODE_SHIFT (1 << 0)
+#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2)
/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_CEFUSE_DYNDEP_SHIFT (1 << 17)
+#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
-#define OMAP4430_CEFUSE_STATDEP_SHIFT (1 << 17)
+#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17)
/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT (1 << 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13)
/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT (1 << 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12)
/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9)
/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11)
/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT (1 << 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT (1 << 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13)
/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9)
/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9)
/* Used by CM_CEFUSE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT (1 << 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT (1 << 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT (1 << 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14)
/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10)
/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9)
/* Used by CM_DUCATI_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10)
/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8)
/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT (1 << 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15)
/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10)
/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT (1 << 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT (1 << 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT (1 << 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT (1 << 27)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27)
/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT (1 << 31)
+#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31
#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT (1 << 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT (1 << 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT (1 << 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT (1 << 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT (1 << 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT (1 << 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT (1 << 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT (1 << 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19)
/* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8)
/* Used by CM_IVAHD_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT (1 << 14)
+#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14)
/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_SDMA_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_GFX_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INSTR_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8)
/* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9)
/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT (1 << 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12)
/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8)
/* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT (1 << 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT (1 << 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT (1 << 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT (1 << 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT (1 << 25)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25)
/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT (1 << 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT (1 << 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT (1 << 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT (1 << 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10)
/* Used by CM_GFX_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9)
/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11)
/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10)
/* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT (1 << 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9)
/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8)
/* Used by CM_TESLA_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT (1 << 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT (1 << 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT (1 << 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT (1 << 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT (1 << 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15)
/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT (1 << 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT (1 << 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT (1 << 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25)
/* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT (1 << 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11)
/*
@@ -426,7 +426,7 @@
* CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
* CM1_ABE_TIMER8_CLKCTRL
*/
-#define OMAP4430_CLKSEL_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_SHIFT 24
#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24)
/*
@@ -434,43 +434,43 @@
* CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
* CM_CLKSEL_USB_60MHZ
*/
-#define OMAP4430_CLKSEL_0_0_SHIFT (1 << 0)
+#define OMAP4430_CLKSEL_0_0_SHIFT 0
#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0)
/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
-#define OMAP4430_CLKSEL_0_1_SHIFT (1 << 0)
+#define OMAP4430_CLKSEL_0_1_SHIFT 0
#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1)
/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
-#define OMAP4430_CLKSEL_24_25_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_24_25_SHIFT 24
#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25)
/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
-#define OMAP4430_CLKSEL_60M_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_60M_SHIFT 24
#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24)
/* Used by CM1_ABE_AESS_CLKCTRL */
-#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24)
/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
-#define OMAP4430_CLKSEL_CORE_SHIFT (1 << 0)
+#define OMAP4430_CLKSEL_CORE_SHIFT 0
#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0)
/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_CLKSEL_CORE_1_1_SHIFT (1 << 1)
+#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1)
/* Used by CM_WKUP_USIM_CLKCTRL */
-#define OMAP4430_CLKSEL_DIV_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_DIV_SHIFT 24
#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24)
/* Used by CM_CAM_FDIF_CLKCTRL */
-#define OMAP4430_CLKSEL_FCLK_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25)
/* Used by CM_L4PER_MCBSP4_CLKCTRL */
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT (1 << 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25)
/*
@@ -478,58 +478,58 @@
* CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
* CM1_ABE_MCBSP3_CLKCTRL
*/
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT (1 << 26)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27)
/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
-#define OMAP4430_CLKSEL_L3_SHIFT (1 << 4)
+#define OMAP4430_CLKSEL_L3_SHIFT 4
#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4)
/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT (1 << 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2)
/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
-#define OMAP4430_CLKSEL_L4_SHIFT (1 << 8)
+#define OMAP4430_CLKSEL_L4_SHIFT 8
#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8)
/* Used by CM_CLKSEL_ABE */
-#define OMAP4430_CLKSEL_OPP_SHIFT (1 << 0)
+#define OMAP4430_CLKSEL_OPP_SHIFT 0
#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1)
/* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_PER_192M_SHIFT (1 << 25)
+#define OMAP4430_CLKSEL_PER_192M_SHIFT 25
#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT (1 << 27)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26)
/* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24)
/*
* Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
* CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
*/
-#define OMAP4430_CLKSEL_SOURCE_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25)
/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
-#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_CLKSEL_UTMI_P1_SHIFT (1 << 24)
+#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_CLKSEL_UTMI_P2_SHIFT (1 << 25)
+#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25)
/*
@@ -544,23 +544,23 @@
* CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
* CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
*/
-#define OMAP4430_CLKTRCTRL_SHIFT (1 << 0)
+#define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT (1 << 0)
+#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0
#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT (1 << 8)
+#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8
#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_D2D_DYNDEP_SHIFT (1 << 18)
+#define OMAP4430_D2D_DYNDEP_SHIFT 18
#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18)
/* Used by CM_MPU_STATICDEP */
-#define OMAP4430_D2D_STATDEP_SHIFT (1 << 18)
+#define OMAP4430_D2D_STATDEP_SHIFT 18
#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18)
/*
@@ -570,19 +570,19 @@
* CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
* CM_SSC_DELTAMSTEP_DPLL_MPU
*/
-#define OMAP4430_DELTAMSTEP_SHIFT (1 << 0)
+#define OMAP4430_DELTAMSTEP_SHIFT 0
#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DLL_OVERRIDE_SHIFT (1 << 2)
+#define OMAP4430_DLL_OVERRIDE_SHIFT 2
#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2)
/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
-#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT (1 << 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0
#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DLL_RESET_SHIFT (1 << 3)
+#define OMAP4430_DLL_RESET_SHIFT 3
#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3)
/*
@@ -590,40 +590,40 @@
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
*/
-#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT (1 << 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23)
/* Used by CM_CLKDCOLDO_DPLL_USB */
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8)
/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT (1 << 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
*/
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT (1 << 0)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
*/
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT (1 << 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
*/
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8)
/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT (1 << 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10)
/*
@@ -631,11 +631,11 @@
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
*/
-#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6)
/*
@@ -643,11 +643,11 @@
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
*/
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT (1 << 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT (1 << 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7)
/*
@@ -655,23 +655,23 @@
* CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU
*/
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT (1 << 8)
+#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT (1 << 11)
+#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT (1 << 3)
+#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT (1 << 1)
+#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1
#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1)
/*
@@ -679,11 +679,11 @@
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
*/
-#define OMAP4430_DPLL_DIV_SHIFT (1 << 0)
+#define OMAP4430_DPLL_DIV_SHIFT 0
#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_DIV_0_7_SHIFT (1 << 0)
+#define OMAP4430_DPLL_DIV_0_7_SHIFT 0
#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7)
/*
@@ -691,11 +691,11 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT (1 << 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8)
/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT (1 << 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3)
/*
@@ -703,7 +703,7 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_EN_SHIFT (1 << 0)
+#define OMAP4430_DPLL_EN_SHIFT 0
#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2)
/*
@@ -711,7 +711,7 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_LPMODE_EN_SHIFT (1 << 10)
+#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10)
/*
@@ -719,11 +719,11 @@
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
*/
-#define OMAP4430_DPLL_MULT_SHIFT (1 << 8)
+#define OMAP4430_DPLL_MULT_SHIFT 8
#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_MULT_USB_SHIFT (1 << 8)
+#define OMAP4430_DPLL_MULT_USB_SHIFT 8
#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19)
/*
@@ -731,11 +731,11 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_REGM4XEN_SHIFT (1 << 11)
+#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11)
/* Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_SD_DIV_SHIFT (1 << 24)
+#define OMAP4430_DPLL_SD_DIV_SHIFT 24
#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31)
/*
@@ -743,7 +743,7 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_SSC_ACK_SHIFT (1 << 13)
+#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13)
/*
@@ -751,7 +751,7 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT (1 << 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14)
/*
@@ -759,154 +759,154 @@
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
*/
-#define OMAP4430_DPLL_SSC_EN_SHIFT (1 << 12)
+#define OMAP4430_DPLL_SSC_EN_SHIFT 12
#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_DSS_DYNDEP_SHIFT (1 << 8)
+#define OMAP4430_DSS_DYNDEP_SHIFT 8
#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_MPU_STATICDEP
*/
-#define OMAP4430_DSS_STATDEP_SHIFT (1 << 8)
+#define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8)
/* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_DUCATI_DYNDEP_SHIFT (1 << 0)
+#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0)
/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
-#define OMAP4430_DUCATI_STATDEP_SHIFT (1 << 0)
+#define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_FREQ_UPDATE_SHIFT (1 << 0)
+#define OMAP4430_FREQ_UPDATE_SHIFT 0
#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0)
/* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_GFX_DYNDEP_SHIFT (1 << 10)
+#define OMAP4430_GFX_DYNDEP_SHIFT 10
#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_GFX_STATDEP_SHIFT (1 << 10)
+#define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT (1 << 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
*/
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
*/
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
*/
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
*/
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
*/
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
*/
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
*/
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
*/
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
*/
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12)
/*
@@ -962,22 +962,22 @@
* CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
* CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
*/
-#define OMAP4430_IDLEST_SHIFT (1 << 16)
+#define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_MASK BITFIELD(16, 17)
/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_ISS_DYNDEP_SHIFT (1 << 9)
+#define OMAP4430_ISS_DYNDEP_SHIFT 9
#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_ISS_STATDEP_SHIFT (1 << 9)
+#define OMAP4430_ISS_STATDEP_SHIFT 9
#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9)
/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
-#define OMAP4430_IVAHD_DYNDEP_SHIFT (1 << 2)
+#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2)
/*
@@ -986,25 +986,25 @@
* CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
* CM_TESLA_STATICDEP
*/
-#define OMAP4430_IVAHD_STATDEP_SHIFT (1 << 2)
+#define OMAP4430_IVAHD_STATDEP_SHIFT 2
#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_L3INIT_DYNDEP_SHIFT (1 << 7)
+#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_L3INIT_STATDEP_SHIFT (1 << 7)
+#define OMAP4430_L3INIT_STATDEP_SHIFT 7
#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7)
/*
* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
* CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
-#define OMAP4430_L3_1_DYNDEP_SHIFT (1 << 5)
+#define OMAP4430_L3_1_DYNDEP_SHIFT 5
#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5)
/*
@@ -1013,7 +1013,7 @@
* CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_L3_1_STATDEP_SHIFT (1 << 5)
+#define OMAP4430_L3_1_STATDEP_SHIFT 5
#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5)
/*
@@ -1022,7 +1022,7 @@
* CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
* CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
*/
-#define OMAP4430_L3_2_DYNDEP_SHIFT (1 << 6)
+#define OMAP4430_L3_2_DYNDEP_SHIFT 6
#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6)
/*
@@ -1031,11 +1031,11 @@
* CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_L3_2_STATDEP_SHIFT (1 << 6)
+#define OMAP4430_L3_2_STATDEP_SHIFT 6
#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6)
/* Used by CM_L3_1_DYNAMICDEP */
-#define OMAP4430_L4CFG_DYNDEP_SHIFT (1 << 12)
+#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12)
/*
@@ -1043,11 +1043,11 @@
* CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
* CM_TESLA_STATICDEP
*/
-#define OMAP4430_L4CFG_STATDEP_SHIFT (1 << 12)
+#define OMAP4430_L4CFG_STATDEP_SHIFT 12
#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12)
/* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_L4PER_DYNDEP_SHIFT (1 << 13)
+#define OMAP4430_L4PER_DYNDEP_SHIFT 13
#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13)
/*
@@ -1055,36 +1055,36 @@
* CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_L4PER_STATDEP_SHIFT (1 << 13)
+#define OMAP4430_L4PER_STATDEP_SHIFT 13
#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_L4SEC_DYNDEP_SHIFT (1 << 14)
+#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
*/
-#define OMAP4430_L4SEC_STATDEP_SHIFT (1 << 14)
+#define OMAP4430_L4SEC_STATDEP_SHIFT 14
#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14)
/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_L4WKUP_DYNDEP_SHIFT (1 << 15)
+#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_L4WKUP_STATDEP_SHIFT (1 << 15)
+#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15)
/*
* Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_MPU_DYNAMICDEP
*/
-#define OMAP4430_MEMIF_DYNDEP_SHIFT (1 << 4)
+#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4)
/*
@@ -1093,7 +1093,7 @@
* CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
*/
-#define OMAP4430_MEMIF_STATDEP_SHIFT (1 << 4)
+#define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4)
/*
@@ -1103,7 +1103,7 @@
* CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_MPU
*/
-#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT (1 << 8)
+#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10)
/*
@@ -1113,7 +1113,7 @@
* CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_MPU
*/
-#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT (1 << 0)
+#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6)
/*
@@ -1169,23 +1169,23 @@
* CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
* CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
*/
-#define OMAP4430_MODULEMODE_SHIFT (1 << 0)
+#define OMAP4430_MODULEMODE_SHIFT 0
#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1)
/* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT (1 << 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9)
/* Used by CM_WKUP_BANDGAP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT (1 << 9)
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9
#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9)
/* Used by CM_CAM_ISS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8)
/*
@@ -1195,119 +1195,119 @@
* CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
*/
-#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8)
/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8)
/* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT (1 << 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT (1 << 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT (1 << 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT (1 << 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT (1 << 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT (1 << 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT (1 << 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT (1 << 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9)
/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT (1 << 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10)
/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT (1 << 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11)
/* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT (1 << 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10)
/* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT (1 << 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11)
/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT (1 << 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT (1 << 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT (1 << 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT (1 << 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10)
/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_XCLK_SHIFT (1 << 8)
+#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8)
/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_OVERRIDE_ENABLE_SHIFT (1 << 19)
+#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19
#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19)
/* Used by CM_CLKSEL_ABE */
-#define OMAP4430_PAD_CLKS_GATE_SHIFT (1 << 8)
+#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8)
/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
-#define OMAP4430_PERF_CURRENT_SHIFT (1 << 0)
+#define OMAP4430_PERF_CURRENT_SHIFT 0
#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7)
/*
@@ -1315,66 +1315,66 @@
* CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
* CM_IVA_DVFS_PERF_TESLA
*/
-#define OMAP4430_PERF_REQ_SHIFT (1 << 0)
+#define OMAP4430_PERF_REQ_SHIFT 0
#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7)
/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT (1 << 0)
+#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0
#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6)
/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT (1 << 8)
+#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8
#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18)
/* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE1_COMPLETED_SHIFT (1 << 0)
+#define OMAP4430_PHASE1_COMPLETED_SHIFT 0
#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0)
/* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE2A_COMPLETED_SHIFT (1 << 1)
+#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1
#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1)
/* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE2B_COMPLETED_SHIFT (1 << 2)
+#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2
#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT (1 << 20)
+#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT (1 << 22)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23)
/* Used by CM_DYN_DEP_PRESCAL */
-#define OMAP4430_PRESCAL_SHIFT (1 << 0)
+#define OMAP4430_PRESCAL_SHIFT 0
#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5)
/* Used by REVISION_CM2, REVISION_CM1 */
-#define OMAP4430_REV_SHIFT (1 << 0)
+#define OMAP4430_REV_SHIFT 0
#define OMAP4430_REV_MASK BITFIELD(0, 7)
/*
* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
*/
-#define OMAP4430_SAR_MODE_SHIFT (1 << 4)
+#define OMAP4430_SAR_MODE_SHIFT 4
#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4)
/* Used by CM_SCALE_FCLK */
-#define OMAP4430_SCALE_FCLK_SHIFT (1 << 0)
+#define OMAP4430_SCALE_FCLK_SHIFT 0
#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0)
/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_SDMA_DYNDEP_SHIFT (1 << 11)
+#define OMAP4430_SDMA_DYNDEP_SHIFT 11
#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_SDMA_STATDEP_SHIFT (1 << 11)
+#define OMAP4430_SDMA_STATDEP_SHIFT 11
#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11)
/* Used by CM_CLKSEL_ABE */
-#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT (1 << 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10)
/*
@@ -1390,7 +1390,7 @@
* CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
*/
-#define OMAP4430_STBYST_SHIFT (1 << 18)
+#define OMAP4430_STBYST_SHIFT 18
#define OMAP4430_STBYST_MASK BITFIELD(18, 18)
/*
@@ -1398,11 +1398,11 @@
* CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
* CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
*/
-#define OMAP4430_ST_DPLL_CLK_SHIFT (1 << 0)
+#define OMAP4430_ST_DPLL_CLK_SHIFT 0
#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0)
/* Used by CM_CLKDCOLDO_DPLL_USB */
-#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT (1 << 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9)
/*
@@ -1410,58 +1410,58 @@
* CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU
*/
-#define OMAP4430_ST_DPLL_CLKOUT_SHIFT (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
*/
-#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9)
/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
-#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT (1 << 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
*/
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
*/
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
*/
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
*/
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9)
/* Used by CM_SYS_CLKSEL */
-#define OMAP4430_SYS_CLKSEL_SHIFT (1 << 0)
+#define OMAP4430_SYS_CLKSEL_SHIFT 0
#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2)
/* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_TESLA_DYNDEP_SHIFT (1 << 1)
+#define OMAP4430_TESLA_DYNDEP_SHIFT 1
#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_TESLA_STATDEP_SHIFT (1 << 1)
+#define OMAP4430_TESLA_STATDEP_SHIFT 1
#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1)
/*
@@ -1469,6 +1469,6 @@
* CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
-#define OMAP4430_WINDOWSIZE_SHIFT (1 << 24)
+#define OMAP4430_WINDOWSIZE_SHIFT 24
#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27)
#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 90a4086fbdf..94728b1ee3c 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -67,7 +67,8 @@
#define CM_CLKSEL 0x0040
#define CM_CLKSEL1 CM_CLKSEL
#define CM_CLKSEL2 0x0044
-#define CM_CLKSTCTRL 0x0048
+#define OMAP2_CM_CLKSTCTRL 0x0048
+#define OMAP4_CM_CLKSTCTRL 0x0000
/* Architecture-specific registers */
@@ -88,7 +89,7 @@
#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
#define OMAP3430_CM_CLKSTST 0x004c
#define OMAP3430ES2_CM_CLKSEL4 0x004c
#define OMAP3430ES2_CM_CLKSEL5 0x0050
@@ -138,5 +139,8 @@ static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
/* CM_IDLEST_GFX */
#define OMAP_ST_GFX (1 << 0)
+/* CM_IDLEST indicator */
+#define OMAP24XX_CM_IDLEST_VAL 0
+#define OMAP34XX_CM_IDLEST_VAL 1
#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index cdd1f35636d..43f8a33655d 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -140,7 +140,11 @@ static struct omap3_control_regs control_context;
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
{
- omap2_ctrl_base = omap2_globals->ctrl;
+ /* Static mapping, never released */
+ if (omap2_globals->ctrl) {
+ omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
+ WARN_ON(!omap2_ctrl_base);
+ }
}
void __iomem *omap_ctrl_base_get(void)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a26d6a08ae3..3d3d035db9a 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -45,6 +45,8 @@
#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
+#define OMAP3_STATE_MAX OMAP3_STATE_C7
+
struct omap3_processor_cx {
u8 valid;
u8 type;
@@ -60,6 +62,30 @@ struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
struct omap3_processor_cx current_cx_state;
struct powerdomain *mpu_pd, *core_pd;
+/*
+ * The latencies/thresholds for various C states have
+ * to be configured from the respective board files.
+ * These are some default values (which might not provide
+ * the best power savings) used on boards which do not
+ * pass these details from the board file.
+ */
+static struct cpuidle_params cpuidle_params_table[] = {
+ /* C1 */
+ {1, 2, 2, 5},
+ /* C2 */
+ {1, 10, 10, 30},
+ /* C3 */
+ {1, 50, 50, 300},
+ /* C4 */
+ {1, 1500, 1800, 4000},
+ /* C5 */
+ {1, 2500, 7500, 12000},
+ /* C6 */
+ {1, 3000, 8500, 15000},
+ /* C7 */
+ {1, 10000, 30000, 300000},
+};
+
static int omap3_idle_bm_check(void)
{
if (!omap3_can_sleep())
@@ -104,13 +130,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
local_irq_disable();
local_fiq_disable();
- if (!enable_off_mode) {
- if (mpu_state < PWRDM_POWER_RET)
- mpu_state = PWRDM_POWER_RET;
- if (core_state < PWRDM_POWER_RET)
- core_state = PWRDM_POWER_RET;
- }
-
pwrdm_set_next_pwrst(mpu_pd, mpu_state);
pwrdm_set_next_pwrst(core_pd, core_state);
@@ -137,7 +156,68 @@ return_sleep_time:
local_irq_enable();
local_fiq_enable();
- return (u32)timespec_to_ns(&ts_idle)/1000;
+ return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
+}
+
+/**
+ * next_valid_state - Find next valid c-state
+ * @dev: cpuidle device
+ * @state: Currently selected c-state
+ *
+ * If the current state is valid, it is returned back to the caller.
+ * Else, this function searches for a lower c-state which is still
+ * valid (as defined in omap3_power_states[]).
+ */
+static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
+ struct cpuidle_state *curr)
+{
+ struct cpuidle_state *next = NULL;
+ struct omap3_processor_cx *cx;
+
+ cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
+
+ /* Check if current state is valid */
+ if (cx->valid) {
+ return curr;
+ } else {
+ u8 idx = OMAP3_STATE_MAX;
+
+ /*
+ * Reach the current state starting at highest C-state
+ */
+ for (; idx >= OMAP3_STATE_C1; idx--) {
+ if (&dev->states[idx] == curr) {
+ next = &dev->states[idx];
+ break;
+ }
+ }
+
+ /*
+ * Should never hit this condition.
+ */
+ WARN_ON(next == NULL);
+
+ /*
+ * Drop to next valid state.
+ * Start search from the next (lower) state.
+ */
+ idx--;
+ for (; idx >= OMAP3_STATE_C1; idx--) {
+ struct omap3_processor_cx *cx;
+
+ cx = cpuidle_get_statedata(&dev->states[idx]);
+ if (cx->valid) {
+ next = &dev->states[idx];
+ break;
+ }
+ }
+ /*
+ * C1 and C2 are always valid.
+ * So, no need to check for 'next==NULL' outside this loop.
+ */
+ }
+
+ return next;
}
/**
@@ -152,7 +232,7 @@ return_sleep_time:
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
- struct cpuidle_state *new_state = state;
+ struct cpuidle_state *new_state = next_valid_state(dev, state);
if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
BUG_ON(!dev->safe_state);
@@ -165,6 +245,50 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+/**
+ * omap3_cpuidle_update_states - Update the cpuidle states.
+ *
+ * Currently, this function toggles the validity of idle states based upon
+ * the flag 'enable_off_mode'. When the flag is set all states are valid.
+ * Else, states leading to OFF state set to be invalid.
+ */
+void omap3_cpuidle_update_states(void)
+{
+ int i;
+
+ for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
+ struct omap3_processor_cx *cx = &omap3_power_states[i];
+
+ if (enable_off_mode) {
+ cx->valid = 1;
+ } else {
+ if ((cx->mpu_state == PWRDM_POWER_OFF) ||
+ (cx->core_state == PWRDM_POWER_OFF))
+ cx->valid = 0;
+ }
+ }
+}
+
+void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
+{
+ int i;
+
+ if (!cpuidle_board_params)
+ return;
+
+ for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
+ cpuidle_params_table[i].valid =
+ cpuidle_board_params[i].valid;
+ cpuidle_params_table[i].sleep_latency =
+ cpuidle_board_params[i].sleep_latency;
+ cpuidle_params_table[i].wake_latency =
+ cpuidle_board_params[i].wake_latency;
+ cpuidle_params_table[i].threshold =
+ cpuidle_board_params[i].threshold;
+ }
+ return;
+}
+
/* omap3_init_power_states - Initialises the OMAP3 specific C states.
*
* Below is the desciption of each C state.
@@ -179,75 +303,103 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
void omap_init_power_states(void)
{
/* C1 . MPU WFI + Core active */
- omap3_power_states[OMAP3_STATE_C1].valid = 1;
+ omap3_power_states[OMAP3_STATE_C1].valid =
+ cpuidle_params_table[OMAP3_STATE_C1].valid;
omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
- omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
- omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
- omap3_power_states[OMAP3_STATE_C1].threshold = 5;
+ omap3_power_states[OMAP3_STATE_C1].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
+ omap3_power_states[OMAP3_STATE_C1].threshold =
+ cpuidle_params_table[OMAP3_STATE_C1].threshold;
omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
/* C2 . MPU WFI + Core inactive */
- omap3_power_states[OMAP3_STATE_C2].valid = 1;
+ omap3_power_states[OMAP3_STATE_C2].valid =
+ cpuidle_params_table[OMAP3_STATE_C2].valid;
omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
- omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
- omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
- omap3_power_states[OMAP3_STATE_C2].threshold = 30;
+ omap3_power_states[OMAP3_STATE_C2].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
+ omap3_power_states[OMAP3_STATE_C2].threshold =
+ cpuidle_params_table[OMAP3_STATE_C2].threshold;
omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
/* C3 . MPU CSWR + Core inactive */
- omap3_power_states[OMAP3_STATE_C3].valid = 1;
+ omap3_power_states[OMAP3_STATE_C3].valid =
+ cpuidle_params_table[OMAP3_STATE_C3].valid;
omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
- omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
- omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
- omap3_power_states[OMAP3_STATE_C3].threshold = 300;
+ omap3_power_states[OMAP3_STATE_C3].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
+ omap3_power_states[OMAP3_STATE_C3].threshold =
+ cpuidle_params_table[OMAP3_STATE_C3].threshold;
omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
/* C4 . MPU OFF + Core inactive */
- omap3_power_states[OMAP3_STATE_C4].valid = 1;
+ omap3_power_states[OMAP3_STATE_C4].valid =
+ cpuidle_params_table[OMAP3_STATE_C4].valid;
omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
- omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
- omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
- omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
+ omap3_power_states[OMAP3_STATE_C4].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
+ omap3_power_states[OMAP3_STATE_C4].threshold =
+ cpuidle_params_table[OMAP3_STATE_C4].threshold;
omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
/* C5 . MPU CSWR + Core CSWR*/
- omap3_power_states[OMAP3_STATE_C5].valid = 1;
+ omap3_power_states[OMAP3_STATE_C5].valid =
+ cpuidle_params_table[OMAP3_STATE_C5].valid;
omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
- omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
- omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
- omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
+ omap3_power_states[OMAP3_STATE_C5].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
+ omap3_power_states[OMAP3_STATE_C5].threshold =
+ cpuidle_params_table[OMAP3_STATE_C5].threshold;
omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
/* C6 . MPU OFF + Core CSWR */
- omap3_power_states[OMAP3_STATE_C6].valid = 1;
+ omap3_power_states[OMAP3_STATE_C6].valid =
+ cpuidle_params_table[OMAP3_STATE_C6].valid;
omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
- omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
- omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
- omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
+ omap3_power_states[OMAP3_STATE_C6].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
+ omap3_power_states[OMAP3_STATE_C6].threshold =
+ cpuidle_params_table[OMAP3_STATE_C6].threshold;
omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
/* C7 . MPU OFF + Core OFF */
- omap3_power_states[OMAP3_STATE_C7].valid = 1;
+ omap3_power_states[OMAP3_STATE_C7].valid =
+ cpuidle_params_table[OMAP3_STATE_C7].valid;
omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
- omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
- omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
- omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
+ omap3_power_states[OMAP3_STATE_C7].sleep_latency =
+ cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
+ omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
+ cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
+ omap3_power_states[OMAP3_STATE_C7].threshold =
+ cpuidle_params_table[OMAP3_STATE_C7].threshold;
omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
@@ -302,6 +454,8 @@ int __init omap3_idle_init(void)
return -EINVAL;
dev->state_count = count;
+ omap3_cpuidle_update_states();
+
if (cpuidle_register_device(dev)) {
printk(KERN_ERR "%s: CPUidle register device failed\n",
__func__);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 18ad93160ab..2271b9bd1f5 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -141,7 +141,7 @@ static inline void omap_init_camera(void)
#define MBOX_REG_SIZE 0x120
#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap_mbox_resources[] = {
+static struct resource omap2_mbox_resources[] = {
{
.start = OMAP24XX_MAILBOX_BASE,
.end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
@@ -156,10 +156,14 @@ static struct resource omap_mbox_resources[] = {
.flags = IORESOURCE_IRQ,
},
};
+static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
+#else
+#define omap2_mbox_resources NULL
+#define omap2_mbox_resources_sz 0
#endif
#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap_mbox_resources[] = {
+static struct resource omap3_mbox_resources[] = {
{
.start = OMAP34XX_MAILBOX_BASE,
.end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
@@ -170,12 +174,16 @@ static struct resource omap_mbox_resources[] = {
.flags = IORESOURCE_IRQ,
},
};
+static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
+#else
+#define omap3_mbox_resources NULL
+#define omap3_mbox_resources_sz 0
#endif
#ifdef CONFIG_ARCH_OMAP4
#define OMAP4_MBOX_REG_SIZE 0x130
-static struct resource omap_mbox_resources[] = {
+static struct resource omap4_mbox_resources[] = {
{
.start = OMAP44XX_MAILBOX_BASE,
.end = OMAP44XX_MAILBOX_BASE +
@@ -183,10 +191,14 @@ static struct resource omap_mbox_resources[] = {
.flags = IORESOURCE_MEM,
},
{
- .start = INT_44XX_MAIL_U0_MPU,
+ .start = OMAP44XX_IRQ_MAIL_U0,
.flags = IORESOURCE_IRQ,
},
};
+static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
+#else
+#define omap4_mbox_resources NULL
+#define omap4_mbox_resources_sz 0
#endif
static struct platform_device mbox_device = {
@@ -196,9 +208,15 @@ static struct platform_device mbox_device = {
static inline void omap_init_mbox(void)
{
- if (cpu_is_omap2420() || cpu_is_omap3430() || cpu_is_omap44xx()) {
- mbox_device.num_resources = ARRAY_SIZE(omap_mbox_resources);
- mbox_device.resource = omap_mbox_resources;
+ if (cpu_is_omap24xx()) {
+ mbox_device.resource = omap2_mbox_resources;
+ mbox_device.num_resources = omap2_mbox_resources_sz;
+ } else if (cpu_is_omap34xx()) {
+ mbox_device.resource = omap3_mbox_resources;
+ mbox_device.num_resources = omap3_mbox_resources_sz;
+ } else if (cpu_is_omap44xx()) {
+ mbox_device.resource = omap4_mbox_resources;
+ mbox_device.num_resources = omap4_mbox_resources_sz;
} else {
pr_err("%s: platform not supported\n", __func__);
return;
@@ -492,7 +510,12 @@ static struct platform_device dummy_pdev = {
**/
static void __init omap_hsmmc_reset(void)
{
- u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
+ u32 i, nr_controllers;
+
+ if (cpu_is_omap242x())
+ return;
+
+ nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
for (i = 0; i < nr_controllers; i++) {
@@ -697,13 +720,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
- irq = INT_44XX_MMC4_IRQ;
+ irq = OMAP44XX_IRQ_MMC4;
break;
case 4:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
- irq = INT_44XX_MMC5_IRQ;
+ irq = OMAP44XX_IRQ_MMC5;
break;
default:
continue;
@@ -715,7 +738,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
} else if (cpu_is_omap44xx()) {
if (i < 3) {
base += OMAP4_MMC_REG_OFFSET;
- irq += IRQ_GIC_START;
+ irq += OMAP44XX_IRQ_GIC_START;
}
size = OMAP4_HSMMC_SIZE;
name = "mmci-omap-hs";
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll3xxx.c
index f6055b49329..b32ccd954a1 100644
--- a/arch/arm/mach-omap2/dpll.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -1,11 +1,14 @@
/*
* OMAP3/4 - specific DPLL control functions
*
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
*
* Written by Paul Walmsley
- * Testing and integration fixes by Jouni Högander
+ * Testing and integration fixes by Jouni Högander
+ *
+ * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
+ * Menon
*
* Parts of this code are based on code written by
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
@@ -15,7 +18,6 @@
* published by the Free Software Foundation.
*/
-#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
@@ -23,13 +25,10 @@
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
-#include <linux/limits.h>
#include <linux/bitops.h>
#include <plat/cpu.h>
#include <plat/clock.h>
-#include <plat/sram.h>
-#include <asm/div64.h>
#include <asm/clkdev.h>
#include "clock.h"
@@ -44,17 +43,7 @@
#define MAX_DPLL_WAIT_TRIES 1000000
-
-/**
- * omap3_dpll_recalc - recalculate DPLL rate
- * @clk: DPLL struct clk
- *
- * Recalculate and propagate the DPLL rate.
- */
-unsigned long omap3_dpll_recalc(struct clk *clk)
-{
- return omap2_get_dpll_rate(clk);
-}
+/* Private functions */
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
@@ -136,8 +125,6 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
return f;
}
-/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
-
/*
* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
* @clk: pointer to a DPLL struct clk
@@ -238,6 +225,122 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
}
/**
+ * lookup_dco_sddiv - Set j-type DPLL4 compensation variables
+ * @clk: pointer to a DPLL struct clk
+ * @dco: digital control oscillator selector
+ * @sd_div: target sigma-delta divider
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ *
+ * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
+ *
+ * XXX This code is not needed for 3430/AM35xx; can it be optimized
+ * out in non-multi-OMAP builds for those chips?
+ */
+static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
+ u8 n)
+{
+ unsigned long fint, clkinp, sd; /* watch out for overflow */
+ int mod1, mod2;
+
+ clkinp = clk->parent->rate;
+ fint = (clkinp / n) * m;
+
+ if (fint < 1000000000)
+ *dco = 2;
+ else
+ *dco = 4;
+ /*
+ * target sigma-delta to near 250MHz
+ * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
+ */
+ clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
+ mod1 = (clkinp * m) % (250 * n);
+ sd = (clkinp * m) / (250 * n);
+ mod2 = sd % 10;
+ sd /= 10;
+
+ if (mod1 || mod2)
+ sd++;
+ *sd_div = sd;
+}
+
+/*
+ * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock.. Returns -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+ struct dpll_data *dd = clk->dpll_data;
+ u32 v;
+
+ /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+ _omap3_noncore_dpll_bypass(clk);
+
+ /*
+ * Set jitter correction. No jitter correction for OMAP4 and 3630
+ * since freqsel field is no longer present
+ */
+ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+ v = __raw_readl(dd->control_reg);
+ v &= ~dd->freqsel_mask;
+ v |= freqsel << __ffs(dd->freqsel_mask);
+ __raw_writel(v, dd->control_reg);
+ }
+
+ /* Set DPLL multiplier, divider */
+ v = __raw_readl(dd->mult_div1_reg);
+ v &= ~(dd->mult_mask | dd->div1_mask);
+ v |= m << __ffs(dd->mult_mask);
+ v |= (n - 1) << __ffs(dd->div1_mask);
+
+ /*
+ * XXX This code is not needed for 3430/AM35XX; can it be optimized
+ * out in non-multi-OMAP builds for those chips?
+ */
+ if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) {
+ u8 dco, sd_div;
+ lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
+ /* XXX This probably will need revision for OMAP4 */
+ v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
+ | OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
+ v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK);
+ v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
+ }
+
+ __raw_writel(v, dd->mult_div1_reg);
+
+ /* We let the clock framework set the other output dividers later */
+
+ /* REVISIT: Set ramp-up delay? */
+
+ _omap3_noncore_dpll_lock(clk);
+
+ return 0;
+}
+
+/* Public functions */
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+unsigned long omap3_dpll_recalc(struct clk *clk)
+{
+ return omap2_get_dpll_rate(clk);
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
+/**
* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
* @clk: pointer to a DPLL struct clk
*
@@ -292,48 +395,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
/* Non-CORE DPLL rate set code */
-/*
- * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
- *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock.. Returns -EINVAL upon error, or 0 upon success.
- */
-int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-{
- struct dpll_data *dd = clk->dpll_data;
- u32 v;
-
- /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
- _omap3_noncore_dpll_bypass(clk);
-
- /* Set jitter correction */
- if (!cpu_is_omap44xx()) {
- v = __raw_readl(dd->control_reg);
- v &= ~dd->freqsel_mask;
- v |= freqsel << __ffs(dd->freqsel_mask);
- __raw_writel(v, dd->control_reg);
- }
-
- /* Set DPLL multiplier, divider */
- v = __raw_readl(dd->mult_div1_reg);
- v &= ~(dd->mult_mask | dd->div1_mask);
- v |= m << __ffs(dd->mult_mask);
- v |= (n - 1) << __ffs(dd->div1_mask);
- __raw_writel(v, dd->mult_div1_reg);
-
- /* We let the clock framework set the other output dividers later */
-
- /* REVISIT: Set ramp-up delay? */
-
- _omap3_noncore_dpll_lock(clk);
-
- return 0;
-}
-
/**
* omap3_noncore_dpll_set_rate - set non-core DPLL rate
* @clk: struct clk * of DPLL to set
@@ -384,8 +445,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
if (dd->last_rounded_rate == 0)
return -EINVAL;
- /* No freqsel on OMAP4 */
- if (!cpu_is_omap44xx()) {
+ /* No freqsel on OMAP4 and OMAP3630 */
+ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
if (!freqsel)
@@ -530,7 +591,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
v = __raw_readl(dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
- if (v != OMAP3XXX_EN_DPLL_LOCKED)
+ if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
rate = clk->parent->rate;
else
rate = clk->parent->rate * 2;
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index ec0d984a26f..9c442e290cc 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -56,6 +56,9 @@ static struct amba_device omap3_etm_device = {
static int __init emu_init(void)
{
+ if (!cpu_is_omap34xx())
+ return -ENODEV;
+
amba_device_register(&omap3_etb_device, &iomem_resource);
amba_device_register(&omap3_etm_device, &iomem_resource);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
new file mode 100644
index 00000000000..e57fb29ff85
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -0,0 +1,142 @@
+/*
+ * gpmc-nand.c
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Vimal Singh <vimalsingh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/mach/flash.h>
+
+#include <plat/nand.h>
+#include <plat/board.h>
+#include <plat/gpmc.h>
+
+#define WR_RD_PIN_MONITORING 0x00600000
+
+static struct omap_nand_platform_data *gpmc_nand_data;
+
+static struct resource gpmc_nand_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device gpmc_nand_device = {
+ .name = "omap2-nand",
+ .id = 0,
+ .num_resources = 1,
+ .resource = &gpmc_nand_resource,
+};
+
+static int omap2_nand_gpmc_retime(void)
+{
+ struct gpmc_timings t;
+ int err;
+
+ if (!gpmc_nand_data->gpmc_t)
+ return 0;
+
+ memset(&t, 0, sizeof(t));
+ t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);
+ t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
+ t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
+
+ /* Read */
+ t.adv_rd_off = gpmc_round_ns_to_ticks(
+ gpmc_nand_data->gpmc_t->adv_rd_off);
+ t.oe_on = t.adv_on;
+ t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access);
+ t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off);
+ t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off);
+ t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle);
+
+ /* Write */
+ t.adv_wr_off = gpmc_round_ns_to_ticks(
+ gpmc_nand_data->gpmc_t->adv_wr_off);
+ t.we_on = t.oe_on;
+ if (cpu_is_omap34xx()) {
+ t.wr_data_mux_bus = gpmc_round_ns_to_ticks(
+ gpmc_nand_data->gpmc_t->wr_data_mux_bus);
+ t.wr_access = gpmc_round_ns_to_ticks(
+ gpmc_nand_data->gpmc_t->wr_access);
+ }
+ t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off);
+ t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);
+ t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
+
+ /* Configure GPMC */
+ gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1,
+ GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) |
+ GPMC_CONFIG1_DEVICETYPE_NAND);
+
+ err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int gpmc_nand_setup(void)
+{
+ struct device *dev = &gpmc_nand_device.dev;
+
+ /* Set timings in GPMC */
+ if (omap2_nand_gpmc_retime() < 0) {
+ dev_err(dev, "Unable to set gpmc timings\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
+{
+ unsigned int val;
+ int err = 0;
+ struct device *dev = &gpmc_nand_device.dev;
+
+ gpmc_nand_data = _nand_data;
+ gpmc_nand_data->nand_setup = gpmc_nand_setup;
+ gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+
+ err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
+ &gpmc_nand_data->phys_base);
+ if (err < 0) {
+ dev_err(dev, "Cannot request GPMC CS\n");
+ return err;
+ }
+
+ err = gpmc_nand_setup();
+ if (err < 0) {
+ dev_err(dev, "NAND platform setup failed: %d\n", err);
+ return err;
+ }
+
+ /* Enable RD PIN Monitoring Reg */
+ if (gpmc_nand_data->dev_ready) {
+ val = gpmc_cs_read_reg(gpmc_nand_data->cs,
+ GPMC_CS_CONFIG1);
+ val |= WR_RD_PIN_MONITORING;
+ gpmc_cs_write_reg(gpmc_nand_data->cs,
+ GPMC_CS_CONFIG1, val);
+ }
+
+ err = platform_device_register(&gpmc_nand_device);
+ if (err < 0) {
+ dev_err(dev, "Unable to register NAND device\n");
+ goto out_free_cs;
+ }
+
+ return 0;
+
+out_free_cs:
+ gpmc_cs_free(gpmc_nand_data->cs);
+
+ return err;
+}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index bd8cb597472..5bc3ca03551 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -505,7 +505,7 @@ static void __init gpmc_mem_init(void)
void __init gpmc_init(void)
{
u32 l;
- char *ck;
+ char *ck = NULL;
if (cpu_is_omap24xx()) {
ck = "core_l3_ck";
@@ -521,6 +521,9 @@ void __init gpmc_init(void)
l = OMAP44XX_GPMC_BASE;
}
+ if (WARN_ON(!ck))
+ return;
+
gpmc_l3_clk = clk_get(NULL, ck);
if (IS_ERR(gpmc_l3_clk)) {
printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
@@ -534,6 +537,8 @@ void __init gpmc_init(void)
BUG();
}
+ clk_enable(gpmc_l3_clk);
+
l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
/* Set smart idle mode and automatic L3 clock gating */
@@ -547,9 +552,10 @@ void __init gpmc_init(void)
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_gpmc_regs gpmc_context;
-void omap3_gpmc_save_context()
+void omap3_gpmc_save_context(void)
{
int i;
+
gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
@@ -578,9 +584,10 @@ void omap3_gpmc_save_context()
}
}
-void omap3_gpmc_restore_context()
+void omap3_gpmc_restore_context(void)
{
int i;
+
gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
new file mode 100644
index 00000000000..9ad229594b4
--- /dev/null
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -0,0 +1,266 @@
+/*
+ * linux/arch/arm/mach-omap2/hsmmc.c
+ *
+ * Copyright (C) 2007-2008 Texas Instruments
+ * Copyright (C) 2008 Nokia Corporation
+ * Author: Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <mach/hardware.h>
+#include <plat/control.h>
+#include <plat/mmc.h>
+#include <plat/omap-pm.h>
+
+#include "hsmmc.h"
+
+#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+
+static u16 control_pbias_offset;
+static u16 control_devconf1_offset;
+
+#define HSMMC_NAME_LEN 9
+
+static struct hsmmc_controller {
+ char name[HSMMC_NAME_LEN + 1];
+} hsmmc[OMAP34XX_NR_MMC];
+
+#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+
+static int hsmmc_get_context_loss(struct device *dev)
+{
+ return omap_pm_get_dev_context_loss_count(dev);
+}
+
+#else
+#define hsmmc_get_context_loss NULL
+#endif
+
+static void hsmmc1_before_set_reg(struct device *dev, int slot,
+ int power_on, int vdd)
+{
+ u32 reg, prog_io;
+ struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+ if (mmc->slots[0].remux)
+ mmc->slots[0].remux(dev, slot, power_on);
+
+ /*
+ * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
+ * card with Vcc regulator (from twl4030 or whatever). OMAP has both
+ * 1.8V and 3.0V modes, controlled by the PBIAS register.
+ *
+ * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
+ * is most naturally TWL VSIM; those pins also use PBIAS.
+ *
+ * FIXME handle VMMC1A as needed ...
+ */
+ if (power_on) {
+ if (cpu_is_omap2430()) {
+ reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
+ if ((1 << vdd) >= MMC_VDD_30_31)
+ reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
+ else
+ reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
+ omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
+ }
+
+ if (mmc->slots[0].internal_clock) {
+ reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ reg |= OMAP2_MMCSDIO1ADPCLKISEL;
+ omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
+ }
+
+ reg = omap_ctrl_readl(control_pbias_offset);
+ if (cpu_is_omap3630()) {
+ /* Set MMC I/O to 52Mhz */
+ prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
+ prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
+ omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
+ } else {
+ reg |= OMAP2_PBIASSPEEDCTRL0;
+ }
+ reg &= ~OMAP2_PBIASLITEPWRDNZ0;
+ omap_ctrl_writel(reg, control_pbias_offset);
+ } else {
+ reg = omap_ctrl_readl(control_pbias_offset);
+ reg &= ~OMAP2_PBIASLITEPWRDNZ0;
+ omap_ctrl_writel(reg, control_pbias_offset);
+ }
+}
+
+static void hsmmc1_after_set_reg(struct device *dev, int slot,
+ int power_on, int vdd)
+{
+ u32 reg;
+
+ /* 100ms delay required for PBIAS configuration */
+ msleep(100);
+
+ if (power_on) {
+ reg = omap_ctrl_readl(control_pbias_offset);
+ reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
+ if ((1 << vdd) <= MMC_VDD_165_195)
+ reg &= ~OMAP2_PBIASLITEVMODE0;
+ else
+ reg |= OMAP2_PBIASLITEVMODE0;
+ omap_ctrl_writel(reg, control_pbias_offset);
+ } else {
+ reg = omap_ctrl_readl(control_pbias_offset);
+ reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
+ OMAP2_PBIASLITEVMODE0);
+ omap_ctrl_writel(reg, control_pbias_offset);
+ }
+}
+
+static void hsmmc23_before_set_reg(struct device *dev, int slot,
+ int power_on, int vdd)
+{
+ struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+ if (mmc->slots[0].remux)
+ mmc->slots[0].remux(dev, slot, power_on);
+
+ if (power_on) {
+ /* Only MMC2 supports a CLKIN */
+ if (mmc->slots[0].internal_clock) {
+ u32 reg;
+
+ reg = omap_ctrl_readl(control_devconf1_offset);
+ reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+ omap_ctrl_writel(reg, control_devconf1_offset);
+ }
+ }
+}
+
+static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
+
+void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+ struct omap2_hsmmc_info *c;
+ int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
+ int i;
+
+ if (cpu_is_omap2430()) {
+ control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
+ control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
+ } else {
+ control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+ control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
+ }
+
+ for (c = controllers; c->mmc; c++) {
+ struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
+ struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+
+ if (!c->mmc || c->mmc > nr_hsmmc) {
+ pr_debug("MMC%d: no such controller\n", c->mmc);
+ continue;
+ }
+ if (mmc) {
+ pr_debug("MMC%d: already configured\n", c->mmc);
+ continue;
+ }
+
+ mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
+ GFP_KERNEL);
+ if (!mmc) {
+ pr_err("Cannot allocate memory for mmc device!\n");
+ goto done;
+ }
+
+ if (c->name)
+ strncpy(hc->name, c->name, HSMMC_NAME_LEN);
+ else
+ snprintf(hc->name, ARRAY_SIZE(hc->name),
+ "mmc%islot%i", c->mmc, 1);
+ mmc->slots[0].name = hc->name;
+ mmc->nr_slots = 1;
+ mmc->slots[0].wires = c->wires;
+ mmc->slots[0].internal_clock = !c->ext_clock;
+ mmc->dma_mask = 0xffffffff;
+
+ mmc->get_context_loss_count = hsmmc_get_context_loss;
+
+ mmc->slots[0].switch_pin = c->gpio_cd;
+ mmc->slots[0].gpio_wp = c->gpio_wp;
+
+ mmc->slots[0].remux = c->remux;
+
+ if (c->cover_only)
+ mmc->slots[0].cover = 1;
+
+ if (c->nonremovable)
+ mmc->slots[0].nonremovable = 1;
+
+ if (c->power_saving)
+ mmc->slots[0].power_saving = 1;
+
+ if (c->no_off)
+ mmc->slots[0].no_off = 1;
+
+ if (c->vcc_aux_disable_is_sleep)
+ mmc->slots[0].vcc_aux_disable_is_sleep = 1;
+
+ /* NOTE: MMC slots should have a Vcc regulator set up.
+ * This may be from a TWL4030-family chip, another
+ * controllable regulator, or a fixed supply.
+ *
+ * temporary HACK: ocr_mask instead of fixed supply
+ */
+ mmc->slots[0].ocr_mask = c->ocr_mask;
+
+ switch (c->mmc) {
+ case 1:
+ /* on-chip level shifting via PBIAS0/PBIAS1 */
+ mmc->slots[0].before_set_reg = hsmmc1_before_set_reg;
+ mmc->slots[0].after_set_reg = hsmmc1_after_set_reg;
+
+ /* Omap3630 HSMMC1 supports only 4-bit */
+ if (cpu_is_omap3630() && c->wires > 4) {
+ c->wires = 4;
+ mmc->slots[0].wires = c->wires;
+ }
+ break;
+ case 2:
+ if (c->ext_clock)
+ c->transceiver = 1;
+ if (c->transceiver && c->wires > 4)
+ c->wires = 4;
+ /* FALLTHROUGH */
+ case 3:
+ /* off-chip level shifting, or none */
+ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
+ mmc->slots[0].after_set_reg = NULL;
+ break;
+ default:
+ pr_err("MMC%d configuration not supported!\n", c->mmc);
+ kfree(mmc);
+ continue;
+ }
+ hsmmc_data[c->mmc - 1] = mmc;
+ }
+
+ omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+
+ /* pass the device nodes back to board setup code */
+ for (c = controllers; c->mmc; c++) {
+ struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+
+ if (!c->mmc || c->mmc > nr_hsmmc)
+ continue;
+ c->dev = mmc->dev;
+ }
+
+done:
+ for (i = 0; i < nr_hsmmc; i++)
+ kfree(hsmmc_data[i]);
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/hsmmc.h
index a47e68563fb..36f0ba8d89e 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -6,7 +6,7 @@
* published by the Free Software Foundation.
*/
-struct twl4030_hsmmc_info {
+struct omap2_hsmmc_info {
u8 mmc; /* controller 1/2/3 */
u8 wires; /* 1/4/8 wires */
bool transceiver; /* MMC-2 option */
@@ -14,22 +14,24 @@ struct twl4030_hsmmc_info {
bool cover_only; /* No card detect - just cover switch */
bool nonremovable; /* Nonremovable e.g. eMMC */
bool power_saving; /* Try to sleep or power off when possible */
+ bool no_off; /* power_saving and power is not to go off */
+ bool vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
int gpio_cd; /* or -EINVAL */
int gpio_wp; /* or -EINVAL */
char *name; /* or NULL for default */
struct device *dev; /* returned: pointer to mmc adapter */
int ocr_mask; /* temporary HACK */
+ /* Remux (pad configuation) when powering on/off */
+ void (*remux)(struct device *dev, int slot, int power_on);
};
-#if defined(CONFIG_REGULATOR) && \
- (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
- defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
+#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
-void twl4030_mmc_init(struct twl4030_hsmmc_info *);
+void omap2_hsmmc_init(struct omap2_hsmmc_info *);
#else
-static inline void twl4030_mmc_init(struct twl4030_hsmmc_info *info)
+static inline void omap2_hsmmc_init(struct omap2_hsmmc_info *info)
{
}
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 789ca8c02f0..7951ae1447e 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -25,9 +25,7 @@
#include "mux.h"
-int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
- struct i2c_board_info const *info,
- unsigned len)
+void __init omap2_i2c_mux_pins(int bus_id)
{
if (cpu_is_omap24xx()) {
const int omap24xx_pins[][2] = {
@@ -51,6 +49,4 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
-
- return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a091b53657b..37b8a1a4adf 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -57,6 +57,8 @@ int omap_type(void)
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
} else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
+ } else if (cpu_is_omap44xx()) {
+ val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
} else {
pr_err("Cannot detect omap type!\n");
goto out;
@@ -175,6 +177,8 @@ void __init omap3_check_features(void)
OMAP3_CHECK_FEATURE(status, SGX);
OMAP3_CHECK_FEATURE(status, NEON);
OMAP3_CHECK_FEATURE(status, ISP);
+ if (cpu_is_omap3630())
+ omap3_features |= OMAP3_HAS_192MHZ_CLK;
/*
* TODO: Get additional info (where applicable)
@@ -188,6 +192,8 @@ void __init omap3_check_revision(void)
u16 hawkeye;
u8 rev;
+ omap_chip.oc = CHIP_IS_OMAP3430;
+
/*
* We cannot access revision registers on ES1.0.
* If the processor type is Cortex-A8 and the revision is 0x0
@@ -196,6 +202,7 @@ void __init omap3_check_revision(void)
cpuid = read_cpuid(CPUID_ID);
if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
+ omap_chip.oc |= CHIP_IS_OMAP3430ES1;
return;
}
@@ -216,18 +223,28 @@ void __init omap3_check_revision(void)
case 0: /* Take care of early samples */
case 1:
omap_revision = OMAP3430_REV_ES2_0;
+ omap_chip.oc |= CHIP_IS_OMAP3430ES2;
break;
case 2:
omap_revision = OMAP3430_REV_ES2_1;
+ omap_chip.oc |= CHIP_IS_OMAP3430ES2;
break;
case 3:
omap_revision = OMAP3430_REV_ES3_0;
+ omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
break;
case 4:
+ omap_revision = OMAP3430_REV_ES3_1;
+ omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+ break;
+ case 7:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
- omap_revision = OMAP3430_REV_ES3_1;
+ omap_revision = OMAP3430_REV_ES3_1_2;
+
+ /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
+ omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
}
break;
case 0xb868:
@@ -235,14 +252,18 @@ void __init omap3_check_revision(void)
*
* Set the device to be OMAP3505 here. Actual device
* is identified later based on the features.
+ *
+ * REVISIT: AM3505/AM3517 should have their own CHIP_IS
*/
omap_revision = OMAP3505_REV(rev);
+ omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
break;
case 0xb891:
/* FALLTHROUGH */
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_0;
+ omap_chip.oc |= CHIP_IS_OMAP3630ES1;
}
}
@@ -264,6 +285,7 @@ void __init omap4_check_revision(void)
if ((hawkeye == 0xb852) && (rev == 0x0)) {
omap_revision = OMAP4430_REV_ES1_0;
+ omap_chip.oc |= CHIP_IS_OMAP4430ES1;
pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
return;
}
@@ -341,6 +363,7 @@ void __init omap3_cpuinfo(void)
OMAP3_SHOW_FEATURE(sgx);
OMAP3_SHOW_FEATURE(neon);
OMAP3_SHOW_FEATURE(isp);
+ OMAP3_SHOW_FEATURE(192mhz_clk);
printk(")\n");
}
@@ -360,6 +383,7 @@ void __init omap2_check_revision(void)
omap3_check_revision();
omap3_check_features();
omap3_cpuinfo();
+ return;
} else if (cpu_is_omap44xx()) {
omap4_check_revision();
return;
@@ -374,27 +398,14 @@ void __init omap2_check_revision(void)
if (cpu_is_omap243x()) {
/* Currently only supports 2430ES2.1 and 2430-all */
omap_chip.oc |= CHIP_IS_OMAP2430;
+ return;
} else if (cpu_is_omap242x()) {
/* Currently only supports 2420ES2.1.1 and 2420-all */
omap_chip.oc |= CHIP_IS_OMAP2420;
- } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
- omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
- } else if (cpu_is_omap343x()) {
- omap_chip.oc = CHIP_IS_OMAP3430;
- if (omap_rev() == OMAP3430_REV_ES1_0)
- omap_chip.oc |= CHIP_IS_OMAP3430ES1;
- else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
- omap_rev() <= OMAP3430_REV_ES2_1)
- omap_chip.oc |= CHIP_IS_OMAP3430ES2;
- else if (omap_rev() == OMAP3430_REV_ES3_0)
- omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
- else if (omap_rev() == OMAP3430_REV_ES3_1)
- omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
- else if (omap_rev() == OMAP3630_REV_ES1_0)
- omap_chip.oc |= CHIP_IS_OMAP3630ES1;
- } else {
- pr_err("Uninitialized omap_chip, please fix!\n");
+ return;
}
+
+ pr_err("Uninitialized omap_chip, please fix!\n");
}
/*
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
new file mode 100644
index 00000000000..a705f946fc4
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -0,0 +1,26 @@
+/*:
+ * Address mappings and base address for AM35XX specific interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Sriramakrishnan <srk@ti.com>
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_AM35XX_H
+#define __ASM_ARCH_AM35XX_H
+
+/*
+ * Base addresses
+ * Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules
+ */
+#define AM35XX_IPSS_EMAC_BASE 0x5C000000
+#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
+#define AM35XX_IPSS_HECC_BASE 0x5C050000
+#define AM35XX_IPSS_VPFE_BASE 0x5C060000
+
+#endif /* __ASM_ARCH_AM35XX_H */
diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-sdp.h
new file mode 100644
index 00000000000..465169c0908
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-sdp.h
@@ -0,0 +1,21 @@
+/*
+ * board-sdp.h
+ *
+ * Information structures for SDP-specific board config data
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+struct flash_partitions {
+ struct mtd_partition *parts;
+ int nr_parts;
+};
+
+extern void sdp_flash_init(struct flash_partitions []);
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index e9f255df916..4a63a2ea484 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -11,32 +11,107 @@
*
*/
- .macro addruart,rx
+#include <linux/serial_reg.h>
+
+#include <plat/serial.h>
+
+#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
+
+ .pushsection .data
+omap_uart_phys: .word 0
+omap_uart_virt: .word 0
+omap_uart_lsr: .word 0
+ .popsection
+
+ /*
+ * Note that this code won't work if the bootloader passes
+ * a wrong machine ID number in r1. To debug, just hardcode
+ * the desired UART phys and virt addresses temporarily into
+ * the omap_uart_phys and omap_uart_virt above.
+ */
+ .macro addruart, rx, tmp
+
+ /* Use omap_uart_phys/virt if already configured */
+10: mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldreq \rx, =omap_uart_phys @ physical base address
+ ldrne \rx, =omap_uart_virt @ virtual base address
+ ldr \rx, [\rx, #0]
+ cmp \rx, #0 @ is port configured?
+ bne 99f @ already configured
+
+ /* Check UART1 scratchpad register for uart to use */
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
-#ifdef CONFIG_ARCH_OMAP2
moveq \rx, #0x48000000 @ physical base address
movne \rx, #0xfa000000 @ virtual base
- orr \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
- add \rx, \rx, #0x00002000 @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
- add \rx, \rx, #0x00004000 @ UART 3
-#endif
-
-#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
- moveq \rx, #0x48000000 @ physical base address
- movne \rx, #0xfa000000 @ virtual base
- orr \rx, \rx, #0x0006a000
-#ifdef CONFIG_OMAP_LL_DEBUG_UART2
- add \rx, \rx, #0x00002000 @ UART 2
-#endif
-#ifdef CONFIG_OMAP_LL_DEBUG_UART3
- add \rx, \rx, #0x00fb0000 @ UART 3
- add \rx, \rx, #0x00006000
-#endif
-#endif
+ orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4
+ ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad
+
+ /* Select the UART to use based on the UART1 scratchpad value */
+ cmp \rx, #0 @ no port configured?
+ beq 21f @ if none, try to use UART1
+ cmp \rx, #OMAP2UART1 @ OMAP2/3/4UART1
+ beq 21f @ configure OMAP2/3/4UART1
+ cmp \rx, #OMAP2UART2 @ OMAP2/3/4UART2
+ beq 22f @ configure OMAP2/3/4UART2
+ cmp \rx, #OMAP2UART3 @ only on 24xx
+ beq 23f @ configure OMAP2UART3
+ cmp \rx, #OMAP3UART3 @ only on 34xx
+ beq 33f @ configure OMAP3UART3
+ cmp \rx, #OMAP4UART3 @ only on 44xx
+ beq 43f @ configure OMAP4UART3
+ cmp \rx, #OMAP3UART4 @ only on 36xx
+ beq 34f @ configure OMAP3UART4
+ cmp \rx, #OMAP4UART4 @ only on 44xx
+ beq 44f @ configure OMAP4UART4
+ cmp \rx, #ZOOM_UART @ only on zoom2/3
+ beq 95f @ configure ZOOM_UART
+
+ /* Configure the UART offset from the phys/virt base */
+21: mov \rx, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
+ b 98f
+22: mov \rx, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
+ b 98f
+23: mov \rx, #UART_OFFSET(OMAP2_UART3_BASE)
+ b 98f
+33: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE)
+ add \rx, \rx, #0x00fb0000
+ add \rx, \rx, #0x00006000 @ OMAP3_UART3_BASE
+ b 98f
+34: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE)
+ add \rx, \rx, #0x00fb0000
+ add \rx, \rx, #0x00028000 @ OMAP3_UART4_BASE
+ b 98f
+43: mov \rx, #UART_OFFSET(OMAP4_UART3_BASE)
+ b 98f
+44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE)
+ b 98f
+95: mov \rx, #ZOOM_UART_BASE
+ ldr \tmp, =omap_uart_phys
+ str \rx, [\tmp, #0]
+ mov \rx, #ZOOM_UART_VIRT
+ ldr \tmp, =omap_uart_virt
+ str \rx, [\tmp, #0]
+ mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
+ ldr \tmp, =omap_uart_lsr
+ str \rx, [\tmp, #0]
+ b 10b
+
+ /* Store both phys and virt address for the uart */
+98: add \rx, \rx, #0x48000000 @ phys base
+ ldr \tmp, =omap_uart_phys
+ str \rx, [\tmp, #0]
+ sub \rx, \rx, #0x48000000 @ phys base
+ add \rx, \rx, #0xfa000000 @ virt base
+ ldr \tmp, =omap_uart_virt
+ str \rx, [\tmp, #0]
+ mov \rx, #(UART_LSR << OMAP_PORT_SHIFT)
+ ldr \tmp, =omap_uart_lsr
+ str \rx, [\tmp, #0]
+
+ b 10b
+99:
.endm
.macro senduart,rd,rx
@@ -44,15 +119,12 @@
.endm
.macro busyuart,rd,rx
-1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
- and \rd, \rd, #0x60
- teq \rd, #0x60
- beq 1002f
- ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
- and \rd, \rd, #0x60
- teq \rd, #0x60
+1001: ldr \rd, =omap_uart_lsr
+ ldr \rd, [\rd, #0]
+ ldrb \rd, [\rx, \rd]
+ and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
+ teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
bne 1001b
-1002:
.endm
.macro waituart,rd,rx
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index c7f1720bf28..50fd7491664 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -17,46 +17,134 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
-
-/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
-#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#elif defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
#include <plat/omap44xx.h>
-#endif
-#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
-#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
+
+#include <plat/multi.h>
+
+#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
.macro disable_fiq
.endm
- .macro get_irqnr_preamble, base, tmp
+ .macro arch_ret_to_user, tmp1, tmp2
.endm
- .macro arch_ret_to_user, tmp1, tmp2
+/*
+ * Unoptimized irq functions for multi-omap2, 3 and 4
+ */
+
+#ifdef MULTI_OMAP2
+ .pushsection .data
+omap_irq_base: .word 0
+ .popsection
+
+ /* Configure the interrupt base on the first interrupt */
+ .macro get_irqnr_preamble, base, tmp
+9:
+ ldr \base, =omap_irq_base @ irq base address
+ ldr \base, [\base, #0] @ irq base value
+ cmp \base, #0 @ already configured?
+ bne 9997f @ nothing to do
+
+ mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
+ and \tmp, \tmp, #0x000f0000 @ only check architecture
+ cmp \tmp, #0x00070000 @ is v6?
+ beq 2400f @ found v6 so it's omap24xx
+ mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
+ and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
+ cmp \tmp, #0x00000080 @ cortex A-8?
+ beq 3400f @ found A-8 so it's omap34xx
+ cmp \tmp, #0x00000090 @ cortex A-9?
+ beq 4400f @ found A-9 so it's omap44xx
+2400: ldr \base, =OMAP2_IRQ_BASE
+ ldr \tmp, =omap_irq_base
+ str \base, [\tmp, #0]
+ b 9b
+3400: ldr \base, =OMAP3_IRQ_BASE
+ ldr \tmp, =omap_irq_base
+ str \base, [\tmp, #0]
+ b 9b
+4400: ldr \base, =OMAP4_IRQ_BASE
+ ldr \tmp, =omap_irq_base
+ str \base, [\tmp, #0]
+ b 9b
+9997:
.endm
-#ifndef CONFIG_ARCH_OMAP4
+ /* Check the pending interrupts. Note that base already set */
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =OMAP2_VA_IC_BASE
+ tst \base, #0x100 @ gic address?
+ bne 4401f @ found gic
+
+ /* Handle omap2 and omap3 */
ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
cmp \irqnr, #0x0
- bne 2222f
+ bne 9998f
ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
cmp \irqnr, #0x0
- bne 2222f
+ bne 9998f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
-2222:
+9998:
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+ b 9999f
+ /* Handle omap4 */
+4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
+ ldr \tmp, =1021
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #29
+ cmpcc \irqnr, \irqnr
+ cmpne \irqnr, \tmp
+ cmpcs \irqnr, \irqnr
+9999:
.endm
+
+
+#else /* MULTI_OMAP2 */
+
+
+/*
+ * Optimized irq functions for omap2, 3 and 4
+ */
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ .macro get_irqnr_preamble, base, tmp
+#ifdef CONFIG_ARCH_OMAP2
+ ldr \base, =OMAP2_IRQ_BASE
#else
-#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+ ldr \base, =OMAP3_IRQ_BASE
+#endif
+ .endm
+
+ /* Check the pending interrupts. Note that base already set */
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
+ cmp \irqnr, #0x0
+ bne 9999f
+ ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
+ cmp \irqnr, #0x0
+ bne 9999f
+ ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+ cmp \irqnr, #0x0
+9999:
+ ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+ and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+
+ .endm
+#endif
+
+
+#ifdef CONFIG_ARCH_OMAP4
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =OMAP4_IRQ_BASE
+ .endm
/*
* The interrupt numbering scheme is defined in the
@@ -78,7 +166,6 @@
* valid range for an IRQ (30-1020 inclusive).
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
ldr \irqstat, [\base, #GIC_CPU_INTACK]
ldr \tmp, =1021
@@ -119,6 +206,7 @@
cmp \tmp, #0
.endm
#endif
+#endif /* MULTI_OMAP2 */
.macro irq_prio_table
.endm
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a8749e8017b..87f676acf61 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,10 +33,11 @@
#include <plat/sdrc.h>
#include <plat/gpmc.h>
#include <plat/serial.h>
-#include <plat/mux.h>
#include <plat/vram.h>
-#include "clock.h"
+#include "clock2xxx.h"
+#include "clock3xxx.h"
+#include "clock44xx.h"
#include <plat/omap-pm.h>
#include <plat/powerdomain.h>
@@ -45,16 +46,13 @@
#include <plat/clockdomain.h>
#include "clockdomains.h"
#include <plat/omap_hwmod.h>
-#include "omap_hwmod_2420.h"
-#include "omap_hwmod_2430.h"
-#include "omap_hwmod_34xx.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
static struct map_desc omap24xx_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,
@@ -73,21 +71,21 @@ static struct map_desc omap24xx_io_desc[] __initdata = {
#ifdef CONFIG_ARCH_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
{
- .virtual = DSP_MEM_24XX_VIRT,
- .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
- .length = DSP_MEM_24XX_SIZE,
+ .virtual = DSP_MEM_2420_VIRT,
+ .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
+ .length = DSP_MEM_2420_SIZE,
.type = MT_DEVICE
},
{
- .virtual = DSP_IPI_24XX_VIRT,
- .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
- .length = DSP_IPI_24XX_SIZE,
+ .virtual = DSP_IPI_2420_VIRT,
+ .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
+ .length = DSP_IPI_2420_SIZE,
.type = MT_DEVICE
},
{
- .virtual = DSP_MMU_24XX_VIRT,
- .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
- .length = DSP_MMU_24XX_SIZE,
+ .virtual = DSP_MMU_2420_VIRT,
+ .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
+ .length = DSP_MMU_2420_SIZE,
.type = MT_DEVICE
},
};
@@ -124,7 +122,7 @@ static struct map_desc omap243x_io_desc[] __initdata = {
#endif
#endif
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
{
.virtual = L3_34XX_VIRT,
@@ -139,12 +137,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
.type = MT_DEVICE
},
{
- .virtual = L4_WK_34XX_VIRT,
- .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
- .length = L4_WK_34XX_SIZE,
- .type = MT_DEVICE
- },
- {
.virtual = OMAP34XX_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
.length = OMAP34XX_GPMC_SIZE,
@@ -191,12 +183,6 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
.type = MT_DEVICE,
},
{
- .virtual = L4_WK_44XX_VIRT,
- .pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
- .length = L4_WK_44XX_SIZE,
- .type = MT_DEVICE,
- },
- {
.virtual = OMAP44XX_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
.length = OMAP44XX_GPMC_SIZE,
@@ -235,37 +221,54 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif
-void __init omap2_map_common_io(void)
+static void __init _omap2_map_common_io(void)
+{
+ /* Normally devicemaps_init() would flush caches and tlb after
+ * mdesc->map_io(), but we must also do it here because of the CPU
+ * revision check below.
+ */
+ local_flush_tlb_all();
+ flush_cache_all();
+
+ omap2_check_revision();
+ omap_sram_init();
+ omapfb_reserve_sdram();
+ omap_vram_reserve_sdram();
+}
+
+#ifdef CONFIG_ARCH_OMAP2420
+void __init omap242x_map_common_io(void)
{
-#if defined(CONFIG_ARCH_OMAP2420)
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
+ _omap2_map_common_io();
+}
#endif
-#if defined(CONFIG_ARCH_OMAP2430)
+#ifdef CONFIG_ARCH_OMAP2430
+void __init omap243x_map_common_io(void)
+{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
+ _omap2_map_common_io();
+}
#endif
-#if defined(CONFIG_ARCH_OMAP34XX)
+#ifdef CONFIG_ARCH_OMAP3
+void __init omap34xx_map_common_io(void)
+{
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
+ _omap2_map_common_io();
+}
#endif
-#if defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP4
+void __init omap44xx_map_common_io(void)
+{
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
-#endif
- /* Normally devicemaps_init() would flush caches and tlb after
- * mdesc->map_io(), but we must also do it here because of the CPU
- * revision check below.
- */
- local_flush_tlb_all();
- flush_cache_all();
-
- omap2_check_revision();
- omap_sram_init();
- omapfb_reserve_sdram();
- omap_vram_reserve_sdram();
+ _omap2_map_common_io();
}
+#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
@@ -304,30 +307,36 @@ static int __init _omap2_init_reprogram_sdrc(void)
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
- struct omap_hwmod **hwmods = NULL;
+ pwrdm_init(powerdomains_omap);
+ clkdm_init(clockdomains_omap, clkdm_autodeps);
+ if (cpu_is_omap242x())
+ omap2420_hwmod_init();
+ else if (cpu_is_omap243x())
+ omap2430_hwmod_init();
+ else if (cpu_is_omap34xx())
+ omap3xxx_hwmod_init();
+ omap2_mux_init();
+ /* The OPP tables have to be registered before a clk init */
+ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
if (cpu_is_omap2420())
- hwmods = omap2420_hwmods;
+ omap2420_clk_init();
else if (cpu_is_omap2430())
- hwmods = omap2430_hwmods;
+ omap2430_clk_init();
else if (cpu_is_omap34xx())
- hwmods = omap34xx_hwmods;
+ omap3xxx_clk_init();
+ else if (cpu_is_omap44xx())
+ omap4xxx_clk_init();
+ else
+ pr_err("Could not init clock framework - unknown CPU\n");
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
- /* The OPP tables have to be registered before a clk init */
- omap_hwmod_init(hwmods);
- omap2_mux_init();
- omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
- pwrdm_init(powerdomains_omap);
- clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
-#endif
- omap2_clk_init();
omap_serial_early_init();
-#ifndef CONFIG_ARCH_OMAP4
- omap_hwmod_late_init();
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
+ omap_hwmod_late_init();
omap_pm_if_init();
- omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
- _omap2_init_reprogram_sdrc();
-#endif
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
+ _omap2_init_reprogram_sdrc();
+ }
gpmc_init();
}
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 6f4b7cc8f4d..4f63dc6859a 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -15,6 +15,7 @@
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/module.h>
+#include <linux/slab.h>
#include <linux/stringify.h>
#include <plat/iommu.h>
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e9bc782fa41..26aeef560aa 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -194,7 +194,7 @@ void __init omap_init_irq(void)
int i;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
- unsigned long base;
+ unsigned long base = 0;
struct omap_irq_bank *bank = irq_banks + i;
if (cpu_is_omap24xx())
@@ -202,6 +202,8 @@ void __init omap_init_irq(void)
else if (cpu_is_omap34xx())
base = OMAP34XX_IC_BASE;
+ BUG_ON(!base);
+
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
if (!bank->base_reg) {
@@ -274,4 +276,22 @@ void omap_intc_restore_context(void)
}
/* MIRs are saved and restore with other PRCM registers */
}
+
+void omap3_intc_suspend(void)
+{
+ /* A pending interrupt would prevent OMAP from entering suspend */
+ omap_ack_irq(0);
+}
+
+void omap3_intc_prepare_idle(void)
+{
+ /* Disable autoidle as it can stall interrupt controller */
+ intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
+}
+
+void omap3_intc_resume_idle(void)
+{
+ /* Re-enable autoidle */
+ intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
+}
#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 281ab634244..318f3638653 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -40,6 +40,9 @@
#define AUTOIDLE (1 << 0)
#define SOFTRESET (1 << 1)
#define SMARTIDLE (2 << 3)
+#define OMAP4_SOFTRESET (1 << 0)
+#define OMAP4_NOIDLE (1 << 2)
+#define OMAP4_SMARTIDLE (2 << 2)
/* SYSSTATUS: register bit definition */
#define RESETDONE (1 << 0)
@@ -93,29 +96,47 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
if (IS_ERR(mbox_ick_handle)) {
- printk(KERN_ERR "Could not get mailboxes_ick: %d\n",
+ printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
PTR_ERR(mbox_ick_handle));
return PTR_ERR(mbox_ick_handle);
}
clk_enable(mbox_ick_handle);
- mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
- timeout = jiffies + msecs_to_jiffies(20);
- do {
- l = mbox_read_reg(MAILBOX_SYSSTATUS);
- if (l & RESETDONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (!(l & RESETDONE)) {
- pr_err("Can't take mmu out of reset\n");
- return -ENODEV;
+ if (cpu_is_omap44xx()) {
+ mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
+ timeout = jiffies + msecs_to_jiffies(20);
+ do {
+ l = mbox_read_reg(MAILBOX_SYSCONFIG);
+ if (!(l & OMAP4_SOFTRESET))
+ break;
+ } while (!time_after(jiffies, timeout));
+
+ if (l & OMAP4_SOFTRESET) {
+ pr_err("Can't take mailbox out of reset\n");
+ return -ENODEV;
+ }
+ } else {
+ mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
+ timeout = jiffies + msecs_to_jiffies(20);
+ do {
+ l = mbox_read_reg(MAILBOX_SYSSTATUS);
+ if (l & RESETDONE)
+ break;
+ } while (!time_after(jiffies, timeout));
+
+ if (!(l & RESETDONE)) {
+ pr_err("Can't take mailbox out of reset\n");
+ return -ENODEV;
+ }
}
l = mbox_read_reg(MAILBOX_REVISION);
pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
- l = SMARTIDLE | AUTOIDLE;
+ if (cpu_is_omap44xx())
+ l = OMAP4_SMARTIDLE;
+ else
+ l = SMARTIDLE | AUTOIDLE;
mbox_write_reg(l, MAILBOX_SYSCONFIG);
omap2_mbox_enable_irq(mbox, IRQ_RX);
@@ -409,19 +430,19 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
if (unlikely(!res)) {
dev_err(&pdev->dev, "invalid irq resource\n");
ret = -ENODEV;
- goto err_iva1;
+ omap_mbox_unregister(&mbox_dsp_info);
+ goto err_dsp;
}
mbox_iva_info.irq = res->start;
ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
- if (ret)
- goto err_iva1;
+ if (ret) {
+ omap_mbox_unregister(&mbox_dsp_info);
+ goto err_dsp;
+ }
}
#endif
return 0;
-err_iva1:
- omap_mbox_unregister(&mbox_dsp_info);
-
err_dsp:
iounmap(mbox_base);
return ret;
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index baa45173385..2f3cad6f940 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -16,6 +16,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
#include <mach/irqs.h>
#include <plat/dma.h>
@@ -65,9 +66,11 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
},
};
#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
+#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
#else
#define omap2420_mcbsp_pdata NULL
#define OMAP2420_MCBSP_PDATA_SZ 0
+#define OMAP2420_MCBSP_REG_NUM 0
#endif
#ifdef CONFIG_ARCH_OMAP2430
@@ -114,12 +117,14 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
},
};
#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
+#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
#else
#define omap2430_mcbsp_pdata NULL
#define OMAP2430_MCBSP_PDATA_SZ 0
+#define OMAP2430_MCBSP_REG_NUM 0
#endif
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
{
.phys_base = OMAP34XX_MCBSP1_BASE,
@@ -132,6 +137,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
},
{
.phys_base = OMAP34XX_MCBSP2_BASE,
+ .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
@@ -141,6 +147,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
},
{
.phys_base = OMAP34XX_MCBSP3_BASE,
+ .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
@@ -168,9 +175,11 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
},
};
#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
+#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
#else
#define omap34xx_mcbsp_pdata NULL
#define OMAP34XX_MCBSP_PDATA_SZ 0
+#define OMAP34XX_MCBSP_REG_NUM 0
#endif
static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
@@ -208,17 +217,23 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
},
};
#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
+#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
static int __init omap2_mcbsp_init(void)
{
- if (cpu_is_omap2420())
+ if (cpu_is_omap2420()) {
omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
- if (cpu_is_omap2430())
+ omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
+ } else if (cpu_is_omap2430()) {
omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
- if (cpu_is_omap34xx())
+ omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
+ } else if (cpu_is_omap34xx()) {
omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
- if (cpu_is_omap44xx())
+ omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
+ } else if (cpu_is_omap44xx()) {
omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
+ omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
+ }
mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
GFP_KERNEL);
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
deleted file mode 100644
index 0c3c72d934b..00000000000
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/mmc-twl4030.c
- *
- * Copyright (C) 2007-2008 Texas Instruments
- * Copyright (C) 2008 Nokia Corporation
- * Author: Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/hardware.h>
-#include <plat/control.h>
-#include <plat/mmc.h>
-#include <plat/board.h>
-
-#include "mmc-twl4030.h"
-
-
-#if defined(CONFIG_REGULATOR) && \
- (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
-
-static u16 control_pbias_offset;
-static u16 control_devconf1_offset;
-
-#define HSMMC_NAME_LEN 9
-
-static struct twl_mmc_controller {
- struct omap_mmc_platform_data *mmc;
- /* Vcc == configured supply
- * Vcc_alt == optional
- * - MMC1, supply for DAT4..DAT7
- * - MMC2/MMC2, external level shifter voltage supply, for
- * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
- */
- struct regulator *vcc;
- struct regulator *vcc_aux;
- char name[HSMMC_NAME_LEN + 1];
-} hsmmc[OMAP34XX_NR_MMC];
-
-static int twl_mmc_card_detect(int irq)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
- struct omap_mmc_platform_data *mmc;
-
- mmc = hsmmc[i].mmc;
- if (!mmc)
- continue;
- if (irq != mmc->slots[0].card_detect_irq)
- continue;
-
- /* NOTE: assumes card detect signal is active-low */
- return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
- }
- return -ENOSYS;
-}
-
-static int twl_mmc_get_ro(struct device *dev, int slot)
-{
- struct omap_mmc_platform_data *mmc = dev->platform_data;
-
- /* NOTE: assumes write protect signal is active-high */
- return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
-}
-
-static int twl_mmc_get_cover_state(struct device *dev, int slot)
-{
- struct omap_mmc_platform_data *mmc = dev->platform_data;
-
- /* NOTE: assumes card detect signal is active-low */
- return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
-}
-
-/*
- * MMC Slot Initialization.
- */
-static int twl_mmc_late_init(struct device *dev)
-{
- struct omap_mmc_platform_data *mmc = dev->platform_data;
- int ret = 0;
- int i;
-
- /* MMC/SD/SDIO doesn't require a card detect switch */
- if (gpio_is_valid(mmc->slots[0].switch_pin)) {
- ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
- if (ret)
- goto done;
- ret = gpio_direction_input(mmc->slots[0].switch_pin);
- if (ret)
- goto err;
- }
-
- /* require at least main regulator */
- for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
- if (hsmmc[i].name == mmc->slots[0].name) {
- struct regulator *reg;
-
- hsmmc[i].mmc = mmc;
-
- reg = regulator_get(dev, "vmmc");
- if (IS_ERR(reg)) {
- dev_dbg(dev, "vmmc regulator missing\n");
- /* HACK: until fixed.c regulator is usable,
- * we don't require a main regulator
- * for MMC2 or MMC3
- */
- if (i != 0)
- break;
- ret = PTR_ERR(reg);
- hsmmc[i].vcc = NULL;
- goto err;
- }
- hsmmc[i].vcc = reg;
- mmc->slots[0].ocr_mask = mmc_regulator_get_ocrmask(reg);
-
- /* allow an aux regulator */
- reg = regulator_get(dev, "vmmc_aux");
- hsmmc[i].vcc_aux = IS_ERR(reg) ? NULL : reg;
-
- /* UGLY HACK: workaround regulator framework bugs.
- * When the bootloader leaves a supply active, it's
- * initialized with zero usecount ... and we can't
- * disable it without first enabling it. Until the
- * framework is fixed, we need a workaround like this
- * (which is safe for MMC, but not in general).
- */
- if (regulator_is_enabled(hsmmc[i].vcc) > 0) {
- regulator_enable(hsmmc[i].vcc);
- regulator_disable(hsmmc[i].vcc);
- }
- if (hsmmc[i].vcc_aux) {
- if (regulator_is_enabled(reg) > 0) {
- regulator_enable(reg);
- regulator_disable(reg);
- }
- }
-
- break;
- }
- }
-
- return 0;
-
-err:
- gpio_free(mmc->slots[0].switch_pin);
-done:
- mmc->slots[0].card_detect_irq = 0;
- mmc->slots[0].card_detect = NULL;
-
- dev_err(dev, "err %d configuring card detect\n", ret);
- return ret;
-}
-
-static void twl_mmc_cleanup(struct device *dev)
-{
- struct omap_mmc_platform_data *mmc = dev->platform_data;
- int i;
-
- gpio_free(mmc->slots[0].switch_pin);
- for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
- regulator_put(hsmmc[i].vcc);
- regulator_put(hsmmc[i].vcc_aux);
- }
-}
-
-#ifdef CONFIG_PM
-
-static int twl_mmc_suspend(struct device *dev, int slot)
-{
- struct omap_mmc_platform_data *mmc = dev->platform_data;
-
- disable_irq(mmc->slots[0].card_detect_irq);
- return 0;
-}
-
-static int twl_mmc_resume(struct device *dev, int slot)
-{
- struct omap_mmc_platform_data *mmc = dev->platform_data;
-
- enable_irq(mmc->slots[0].card_detect_irq);
- return 0;
-}
-
-#else
-#define twl_mmc_suspend NULL
-#define twl_mmc_resume NULL
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
-
-static int twl4030_mmc_get_context_loss(struct device *dev)
-{
- /* FIXME: PM DPS not implemented yet */
- return 0;
-}
-
-#else
-#define twl4030_mmc_get_context_loss NULL
-#endif
-
-static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
- int vdd)
-{
- u32 reg, prog_io;
- int ret = 0;
- struct twl_mmc_controller *c = &hsmmc[0];
- struct omap_mmc_platform_data *mmc = dev->platform_data;
-
- /*
- * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
- * card with Vcc regulator (from twl4030 or whatever). OMAP has both
- * 1.8V and 3.0V modes, controlled by the PBIAS register.
- *
- * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
- * is most naturally TWL VSIM; those pins also use PBIAS.
- *
- * FIXME handle VMMC1A as needed ...
- */
- if (power_on) {
- if (cpu_is_omap2430()) {
- reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
- if ((1 << vdd) >= MMC_VDD_30_31)
- reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
- else
- reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
- omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
- }
-
- if (mmc->slots[0].internal_clock) {
- reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
- reg |= OMAP2_MMCSDIO1ADPCLKISEL;
- omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
- }
-
- reg = omap_ctrl_readl(control_pbias_offset);
- if (cpu_is_omap3630()) {
- /* Set MMC I/O to 52Mhz */
- prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
- prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
- omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
- } else {
- reg |= OMAP2_PBIASSPEEDCTRL0;
- }
- reg &= ~OMAP2_PBIASLITEPWRDNZ0;
- omap_ctrl_writel(reg, control_pbias_offset);
-
- ret = mmc_regulator_set_ocr(c->vcc, vdd);
-
- /* 100ms delay required for PBIAS configuration */
- msleep(100);
- reg = omap_ctrl_readl(control_pbias_offset);
- reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
- if ((1 << vdd) <= MMC_VDD_165_195)
- reg &= ~OMAP2_PBIASLITEVMODE0;
- else
- reg |= OMAP2_PBIASLITEVMODE0;
- omap_ctrl_writel(reg, control_pbias_offset);
- } else {
- reg = omap_ctrl_readl(control_pbias_offset);
- reg &= ~OMAP2_PBIASLITEPWRDNZ0;
- omap_ctrl_writel(reg, control_pbias_offset);
-
- ret = mmc_regulator_set_ocr(c->vcc, 0);
-
- /* 100ms delay required for PBIAS configuration */
- msleep(100);
- reg = omap_ctrl_readl(control_pbias_offset);
- reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
- OMAP2_PBIASLITEVMODE0);
- omap_ctrl_writel(reg, control_pbias_offset);
- }
-
- return ret;
-}
-
-static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd)
-{
- int ret = 0;
- struct twl_mmc_controller *c = NULL;
- struct omap_mmc_platform_data *mmc = dev->platform_data;
- int i;
-
- for (i = 1; i < ARRAY_SIZE(hsmmc); i++) {
- if (mmc == hsmmc[i].mmc) {
- c = &hsmmc[i];
- break;
- }
- }
-
- if (c == NULL)
- return -ENODEV;
-
- /* If we don't see a Vcc regulator, assume it's a fixed
- * voltage always-on regulator.
- */
- if (!c->vcc)
- return 0;
-
- /*
- * Assume Vcc regulator is used only to power the card ... OMAP
- * VDDS is used to power the pins, optionally with a transceiver to
- * support cards using voltages other than VDDS (1.8V nominal). When a
- * transceiver is used, DAT3..7 are muxed as transceiver control pins.
- *
- * In some cases this regulator won't support enable/disable;
- * e.g. it's a fixed rail for a WLAN chip.
- *
- * In other cases vcc_aux switches interface power. Example, for
- * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
- * chips/cards need an interface voltage rail too.
- */
- if (power_on) {
- /* only MMC2 supports a CLKIN */
- if (mmc->slots[0].internal_clock) {
- u32 reg;
-
- reg = omap_ctrl_readl(control_devconf1_offset);
- reg |= OMAP2_MMCSDIO2ADPCLKISEL;
- omap_ctrl_writel(reg, control_devconf1_offset);
- }
- ret = mmc_regulator_set_ocr(c->vcc, vdd);
- /* enable interface voltage rail, if needed */
- if (ret == 0 && c->vcc_aux) {
- ret = regulator_enable(c->vcc_aux);
- if (ret < 0)
- ret = mmc_regulator_set_ocr(c->vcc, 0);
- }
- } else {
- if (c->vcc_aux && (ret = regulator_is_enabled(c->vcc_aux)) > 0)
- ret = regulator_disable(c->vcc_aux);
- if (ret == 0)
- ret = mmc_regulator_set_ocr(c->vcc, 0);
- }
-
- return ret;
-}
-
-static int twl_mmc1_set_sleep(struct device *dev, int slot, int sleep, int vdd,
- int cardsleep)
-{
- struct twl_mmc_controller *c = &hsmmc[0];
- int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
-
- return regulator_set_mode(c->vcc, mode);
-}
-
-static int twl_mmc23_set_sleep(struct device *dev, int slot, int sleep, int vdd,
- int cardsleep)
-{
- struct twl_mmc_controller *c = NULL;
- struct omap_mmc_platform_data *mmc = dev->platform_data;
- int i, err, mode;
-
- for (i = 1; i < ARRAY_SIZE(hsmmc); i++) {
- if (mmc == hsmmc[i].mmc) {
- c = &hsmmc[i];
- break;
- }
- }
-
- if (c == NULL)
- return -ENODEV;
-
- /*
- * If we don't see a Vcc regulator, assume it's a fixed
- * voltage always-on regulator.
- */
- if (!c->vcc)
- return 0;
-
- mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
-
- if (!c->vcc_aux)
- return regulator_set_mode(c->vcc, mode);
-
- if (cardsleep) {
- /* VCC can be turned off if card is asleep */
- struct regulator *vcc_aux = c->vcc_aux;
-
- c->vcc_aux = NULL;
- if (sleep)
- err = twl_mmc23_set_power(dev, slot, 0, 0);
- else
- err = twl_mmc23_set_power(dev, slot, 1, vdd);
- c->vcc_aux = vcc_aux;
- } else
- err = regulator_set_mode(c->vcc, mode);
- if (err)
- return err;
- return regulator_set_mode(c->vcc_aux, mode);
-}
-
-static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
-
-void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
-{
- struct twl4030_hsmmc_info *c;
- int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
-
- if (cpu_is_omap2430()) {
- control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
- control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
- nr_hsmmc = 2;
- } else {
- control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
- control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
- }
-
- for (c = controllers; c->mmc; c++) {
- struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
-
- if (!c->mmc || c->mmc > nr_hsmmc) {
- pr_debug("MMC%d: no such controller\n", c->mmc);
- continue;
- }
- if (mmc) {
- pr_debug("MMC%d: already configured\n", c->mmc);
- continue;
- }
-
- mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
- if (!mmc) {
- pr_err("Cannot allocate memory for mmc device!\n");
- return;
- }
-
- if (c->name)
- strncpy(twl->name, c->name, HSMMC_NAME_LEN);
- else
- snprintf(twl->name, ARRAY_SIZE(twl->name),
- "mmc%islot%i", c->mmc, 1);
- mmc->slots[0].name = twl->name;
- mmc->nr_slots = 1;
- mmc->slots[0].wires = c->wires;
- mmc->slots[0].internal_clock = !c->ext_clock;
- mmc->dma_mask = 0xffffffff;
- mmc->init = twl_mmc_late_init;
-
- /* note: twl4030 card detect GPIOs can disable VMMCx ... */
- if (gpio_is_valid(c->gpio_cd)) {
- mmc->cleanup = twl_mmc_cleanup;
- mmc->suspend = twl_mmc_suspend;
- mmc->resume = twl_mmc_resume;
-
- mmc->slots[0].switch_pin = c->gpio_cd;
- mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
- if (c->cover_only)
- mmc->slots[0].get_cover_state = twl_mmc_get_cover_state;
- else
- mmc->slots[0].card_detect = twl_mmc_card_detect;
- } else
- mmc->slots[0].switch_pin = -EINVAL;
-
- mmc->get_context_loss_count =
- twl4030_mmc_get_context_loss;
-
- /* write protect normally uses an OMAP gpio */
- if (gpio_is_valid(c->gpio_wp)) {
- gpio_request(c->gpio_wp, "mmc_wp");
- gpio_direction_input(c->gpio_wp);
-
- mmc->slots[0].gpio_wp = c->gpio_wp;
- mmc->slots[0].get_ro = twl_mmc_get_ro;
- } else
- mmc->slots[0].gpio_wp = -EINVAL;
-
- if (c->nonremovable)
- mmc->slots[0].nonremovable = 1;
-
- if (c->power_saving)
- mmc->slots[0].power_saving = 1;
-
- /* NOTE: MMC slots should have a Vcc regulator set up.
- * This may be from a TWL4030-family chip, another
- * controllable regulator, or a fixed supply.
- *
- * temporary HACK: ocr_mask instead of fixed supply
- */
- mmc->slots[0].ocr_mask = c->ocr_mask;
-
- switch (c->mmc) {
- case 1:
- /* on-chip level shifting via PBIAS0/PBIAS1 */
- mmc->slots[0].set_power = twl_mmc1_set_power;
- mmc->slots[0].set_sleep = twl_mmc1_set_sleep;
-
- /* Omap3630 HSMMC1 supports only 4-bit */
- if (cpu_is_omap3630() && c->wires > 4) {
- c->wires = 4;
- mmc->slots[0].wires = c->wires;
- }
- break;
- case 2:
- if (c->ext_clock)
- c->transceiver = 1;
- if (c->transceiver && c->wires > 4)
- c->wires = 4;
- /* FALLTHROUGH */
- case 3:
- /* off-chip level shifting, or none */
- mmc->slots[0].set_power = twl_mmc23_set_power;
- mmc->slots[0].set_sleep = twl_mmc23_set_sleep;
- break;
- default:
- pr_err("MMC%d configuration not supported!\n", c->mmc);
- kfree(mmc);
- continue;
- }
- hsmmc_data[c->mmc - 1] = mmc;
- }
-
- omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
-
- /* pass the device nodes back to board setup code */
- for (c = controllers; c->mmc; c++) {
- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
-
- if (!c->mmc || c->mmc > nr_hsmmc)
- continue;
- c->dev = mmc->dev;
- }
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index e071b3fd187..8b3d26935a3 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -26,6 +26,7 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/ctype.h>
@@ -51,7 +52,7 @@ struct omap_mux_entry {
static unsigned long mux_phys;
static void __iomem *mux_base;
-static inline u16 omap_mux_read(u16 reg)
+u16 omap_mux_read(u16 reg)
{
if (cpu_is_omap24xx())
return __raw_readb(mux_base + reg);
@@ -59,7 +60,7 @@ static inline u16 omap_mux_read(u16 reg)
return __raw_readw(mux_base + reg);
}
-static inline void omap_mux_write(u16 val, u16 reg)
+void omap_mux_write(u16 val, u16 reg)
{
if (cpu_is_omap24xx())
__raw_writeb(val, mux_base + reg);
@@ -67,7 +68,15 @@ static inline void omap_mux_write(u16 val, u16 reg)
__raw_writew(val, mux_base + reg);
}
-#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
+void omap_mux_write_array(struct omap_board_mux *board_mux)
+{
+ while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
+ omap_mux_write(board_mux->value, board_mux->reg_offset);
+ board_mux++;
+ }
+}
+
+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX)
static struct omap_mux_cfg arch_mux_cfg;
@@ -361,7 +370,7 @@ int __init omap2_mux_init(void)
/*----------------------------------------------------------------------------*/
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
static LIST_HEAD(muxmodes);
static DEFINE_MUTEX(muxmode_mutex);
@@ -478,7 +487,7 @@ int __init omap_mux_init_signal(char *muxname, int val)
static inline void omap_mux_decode(struct seq_file *s, u16 val)
{
char *flags[OMAP_MUX_MAX_NR_FLAGS];
- char mode[14];
+ char mode[sizeof("OMAP_MUX_MODE") + 1];
int i = -1;
sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
@@ -545,6 +554,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
if (!m0_name)
continue;
+ /* REVISIT: Needs to be updated if mode0 names get longer */
for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
if (m0_name[i] == '\0') {
m0_def[i] = m0_name[i];
@@ -833,14 +843,6 @@ static void __init omap_mux_set_cmdline_signals(void)
kfree(options);
}
-static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
-{
- while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
- omap_mux_write(board_mux->value, board_mux->reg_offset);
- board_mux++;
- }
-}
-
static int __init omap_mux_copy_names(struct omap_mux *src,
struct omap_mux *dst)
{
@@ -960,7 +962,12 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *entry;
-#ifndef CONFIG_OMAP_MUX
+#ifdef CONFIG_OMAP_MUX
+ if (!superset->muxnames || !superset->muxnames[0]) {
+ superset++;
+ continue;
+ }
+#else
/* Skip pins that are not muxed as GPIO by bootloader */
if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
superset++;
@@ -977,6 +984,38 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
}
}
+#ifdef CONFIG_OMAP_MUX
+
+static void omap_mux_init_package(struct omap_mux *superset,
+ struct omap_mux *package_subset,
+ struct omap_ball *package_balls)
+{
+ if (package_subset)
+ omap_mux_package_fixup(package_subset, superset);
+ if (package_balls)
+ omap_mux_package_init_balls(package_balls, superset);
+}
+
+static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+{
+ omap_mux_set_cmdline_signals();
+ omap_mux_write_array(board_mux);
+}
+
+#else
+
+static void omap_mux_init_package(struct omap_mux *superset,
+ struct omap_mux *package_subset,
+ struct omap_ball *package_balls)
+{
+}
+
+static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+{
+}
+
+#endif
+
int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
@@ -993,17 +1032,12 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
return -ENODEV;
}
-#ifdef CONFIG_OMAP_MUX
- omap_mux_package_fixup(package_subset, superset);
- omap_mux_package_init_balls(package_balls, superset);
- omap_mux_set_cmdline_signals();
- omap_mux_set_board_signals(board_mux);
-#endif
-
+ omap_mux_init_package(superset, package_subset, package_balls);
omap_mux_init_list(superset);
+ omap_mux_init_signals(board_mux);
return 0;
}
-#endif /* CONFIG_ARCH_OMAP34XX */
+#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index d8b4d5ad227..480abc56e60 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -102,7 +102,7 @@ struct omap_board_mux {
u16 value;
};
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3)
/**
* omap_mux_init_gpio - initialize a signal based on the GPIO number
@@ -147,6 +147,30 @@ u16 omap_mux_get_gpio(int gpio);
void omap_mux_set_gpio(u16 val, int gpio);
/**
+ * omap_mux_read() - read mux register
+ * @mux_offset: Offset of the mux register
+ *
+ */
+u16 omap_mux_read(u16 mux_offset);
+
+/**
+ * omap_mux_write() - write mux register
+ * @val: New mux register value
+ * @mux_offset: Offset of the mux register
+ *
+ * This should be only needed for dynamic remuxing of non-gpio signals.
+ */
+void omap_mux_write(u16 val, u16 mux_offset);
+
+/**
+ * omap_mux_write_array() - write an array of mux registers
+ * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
+ *
+ * This should be only needed for dynamic remuxing of non-gpio signals.
+ */
+void omap_mux_write_array(struct omap_board_mux *board_mux);
+
+/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 68e0a595f9a..07aa7b3c95f 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -649,6 +649,53 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
_OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
"uart3_tx_irtx", NULL, NULL, NULL,
"gpio_166", NULL, NULL, "safe_mode"),
+
+ /* Only on 3630, see omap36xx_cbp_subset for the signals */
+ _OMAP3_MUXENTRY(GPMC_A11, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(GPMC_A11, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
+ _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index aa3f65c2ac9..ef0e7a00dd6 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -33,7 +33,7 @@
ENTRY(omap_secondary_startup)
hold: ldr r12,=0x103
dsb
- smc @ read from AuxCoreBoot0
+ smc #0 @ read from AuxCoreBoot0
mov r0, r0, lsr #9
mrc p15, 0, r4, c0, c0, 5
and r4, r4, #0x0f
@@ -52,7 +52,7 @@ ENTRY(omap_modify_auxcoreboot0)
stmfd sp!, {r1-r12, lr}
ldr r12, =0x104
dsb
- smc
+ smc #0
ldmfd sp!, {r1-r12, pc}
END(omap_modify_auxcoreboot0)
@@ -60,6 +60,6 @@ ENTRY(omap_auxcoreboot_addr)
stmfd sp!, {r2-r12, lr}
ldr r12, =0x105
dsb
- smc
+ smc #0
ldmfd sp!, {r2-r12, pc}
END(omap_auxcoreboot_addr)
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
new file mode 100644
index 00000000000..f61c7771ca4
--- /dev/null
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -0,0 +1,32 @@
+/*
+ * OMAP44xx secure APIs file.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * This is common routine to manage secure monitor API
+ * used to modify the PL310 secure registers.
+ * 'r0' contains the value to be modified and 'r12' contains
+ * the monitor API number. It uses few CPU registers
+ * internally and hence they need be backed up including
+ * link register "lr".
+ * Function signature : void omap_smc1(u32 fn, u32 arg)
+ */
+
+ENTRY(omap_smc1)
+ stmfd sp!, {r2-r12, lr}
+ mov r12, r0
+ mov r0, r1
+ dsb
+ smc #0
+ ldmfd sp!, {r2-r12, pc}
+END(omap_smc1)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d8c8545875b..e436dcb1979 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -84,17 +84,17 @@ static u8 inited;
*/
static int _update_sysc_cache(struct omap_hwmod *oh)
{
- if (!oh->sysconfig) {
- WARN(!oh->sysconfig, "omap_hwmod: %s: cannot read "
- "OCP_SYSCONFIG: not defined on hwmod\n", oh->name);
+ if (!oh->class->sysc) {
+ WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
return -EINVAL;
}
/* XXX ensure module interface clock is up */
- oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
+ oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
- oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
+ if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
+ oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
return 0;
}
@@ -104,14 +104,13 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
* @v: OCP_SYSCONFIG value to write
* @oh: struct omap_hwmod *
*
- * Write @v into the module OCP_SYSCONFIG register, if it has one. No
- * return value.
+ * Write @v into the module class' OCP_SYSCONFIG register, if it has
+ * one. No return value.
*/
static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
{
- if (!oh->sysconfig) {
- WARN(!oh->sysconfig, "omap_hwmod: %s: cannot write "
- "OCP_SYSCONFIG: not defined on hwmod\n", oh->name);
+ if (!oh->class->sysc) {
+ WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
return;
}
@@ -119,7 +118,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
if (oh->_sysc_cache != v) {
oh->_sysc_cache = v;
- omap_hwmod_writel(v, oh, oh->sysconfig->sysc_offs);
+ omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs);
}
}
@@ -136,12 +135,23 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
u32 *v)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE))
+ u32 mstandby_mask;
+ u8 mstandby_shift;
+
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
+ return -EINVAL;
+
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
return -EINVAL;
+ }
+
+ mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
+ mstandby_mask = (0x3 << mstandby_shift);
- *v &= ~SYSC_MIDLEMODE_MASK;
- *v |= __ffs(standbymode) << SYSC_MIDLEMODE_SHIFT;
+ *v &= ~mstandby_mask;
+ *v |= __ffs(standbymode) << mstandby_shift;
return 0;
}
@@ -158,12 +168,23 @@ static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
*/
static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE))
+ u32 sidle_mask;
+ u8 sidle_shift;
+
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
+ return -EINVAL;
+
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
return -EINVAL;
+ }
- *v &= ~SYSC_SIDLEMODE_MASK;
- *v |= __ffs(idlemode) << SYSC_SIDLEMODE_SHIFT;
+ sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
+ sidle_mask = (0x3 << sidle_shift);
+
+ *v &= ~sidle_mask;
+ *v |= __ffs(idlemode) << sidle_shift;
return 0;
}
@@ -181,12 +202,23 @@ static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
*/
static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
+ u32 clkact_mask;
+ u8 clkact_shift;
+
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
return -EINVAL;
- *v &= ~SYSC_CLOCKACTIVITY_MASK;
- *v |= clockact << SYSC_CLOCKACTIVITY_SHIFT;
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ return -EINVAL;
+ }
+
+ clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
+ clkact_mask = (0x3 << clkact_shift);
+
+ *v &= ~clkact_mask;
+ *v |= clockact << clkact_shift;
return 0;
}
@@ -201,11 +233,20 @@ static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
*/
static int _set_softreset(struct omap_hwmod *oh, u32 *v)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET))
+ u32 softrst_mask;
+
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
+ return -EINVAL;
+
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
return -EINVAL;
+ }
+
+ softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
- *v |= SYSC_SOFTRESET_MASK;
+ *v |= softrst_mask;
return 0;
}
@@ -226,12 +267,23 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
u32 *v)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE))
+ u32 autoidle_mask;
+ u8 autoidle_shift;
+
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
return -EINVAL;
- *v &= ~SYSC_AUTOIDLE_MASK;
- *v |= autoidle << SYSC_AUTOIDLE_SHIFT;
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ return -EINVAL;
+ }
+
+ autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
+ autoidle_mask = (0x3 << autoidle_shift);
+
+ *v &= ~autoidle_mask;
+ *v |= autoidle << autoidle_shift;
return 0;
}
@@ -245,14 +297,21 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
*/
static int _enable_wakeup(struct omap_hwmod *oh)
{
- u32 v;
+ u32 v, wakeup_mask;
+
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ return -EINVAL;
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
return -EINVAL;
+ }
+
+ wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
v = oh->_sysc_cache;
- v |= SYSC_ENAWAKEUP_MASK;
+ v |= wakeup_mask;
_write_sysconfig(v, oh);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
@@ -271,14 +330,21 @@ static int _enable_wakeup(struct omap_hwmod *oh)
*/
static int _disable_wakeup(struct omap_hwmod *oh)
{
- u32 v;
+ u32 v, wakeup_mask;
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
return -EINVAL;
+ if (!oh->class->sysc->sysc_fields) {
+ WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+ return -EINVAL;
+ }
+
+ wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
+
v = oh->_sysc_cache;
- v &= ~SYSC_ENAWAKEUP_MASK;
+ v &= ~wakeup_mask;
_write_sysconfig(v, oh);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
@@ -298,15 +364,14 @@ static int _disable_wakeup(struct omap_hwmod *oh)
* be accessed by the IVA, there should be a sleepdep between the IVA
* initiator and the module). Only applies to modules in smart-idle
* mode. Returns -EINVAL upon error or passes along
- * pwrdm_add_sleepdep() value upon success.
+ * clkdm_add_sleepdep() value upon success.
*/
static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
{
if (!oh->_clk)
return -EINVAL;
- return pwrdm_add_sleepdep(oh->_clk->clkdm->pwrdm.ptr,
- init_oh->_clk->clkdm->pwrdm.ptr);
+ return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
}
/**
@@ -319,15 +384,14 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
* be accessed by the IVA, there should be no sleepdep between the IVA
* initiator and the module). Only applies to modules in smart-idle
* mode. Returns -EINVAL upon error or passes along
- * pwrdm_add_sleepdep() value upon success.
+ * clkdm_del_sleepdep() value upon success.
*/
static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
{
if (!oh->_clk)
return -EINVAL;
- return pwrdm_del_sleepdep(oh->_clk->clkdm->pwrdm.ptr,
- init_oh->_clk->clkdm->pwrdm.ptr);
+ return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
}
/**
@@ -343,18 +407,18 @@ static int _init_main_clk(struct omap_hwmod *oh)
struct clk *c;
int ret = 0;
- if (!oh->clkdev_con_id)
+ if (!oh->main_clk)
return 0;
- c = clk_get_sys(oh->clkdev_dev_id, oh->clkdev_con_id);
- WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s.%s\n",
- oh->name, oh->clkdev_dev_id, oh->clkdev_con_id);
+ c = omap_clk_get_by_name(oh->main_clk);
+ WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get main_clk %s\n",
+ oh->name, oh->main_clk);
if (IS_ERR(c))
ret = -EINVAL;
oh->_clk = c;
WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
- oh->clkdev_con_id, c->name);
+ oh->main_clk, c->name);
return ret;
}
@@ -377,13 +441,12 @@ static int _init_interface_clks(struct omap_hwmod *oh)
return 0;
for (i = 0, os = *oh->slaves; i < oh->slaves_cnt; i++, os++) {
- if (!os->clkdev_con_id)
+ if (!os->clk)
continue;
- c = clk_get_sys(os->clkdev_dev_id, os->clkdev_con_id);
+ c = omap_clk_get_by_name(os->clk);
WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get "
- "interface_clk %s.%s\n", oh->name,
- os->clkdev_dev_id, os->clkdev_con_id);
+ "interface_clk %s\n", oh->name, os->clk);
if (IS_ERR(c))
ret = -EINVAL;
os->_clk = c;
@@ -407,10 +470,9 @@ static int _init_opt_clks(struct omap_hwmod *oh)
int ret = 0;
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
- c = clk_get_sys(oc->clkdev_dev_id, oc->clkdev_con_id);
+ c = omap_clk_get_by_name(oc->clk);
WARN(IS_ERR(c), "omap_hwmod: %s: cannot clk_get opt_clk "
- "%s.%s\n", oh->name, oc->clkdev_dev_id,
- oc->clkdev_con_id);
+ "%s\n", oh->name, oc->clk);
if (IS_ERR(c))
ret = -EINVAL;
oc->_clk = c;
@@ -567,27 +629,28 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
*/
static void _sysc_enable(struct omap_hwmod *oh)
{
- u8 idlemode;
+ u8 idlemode, sf;
u32 v;
- if (!oh->sysconfig)
+ if (!oh->class->sysc)
return;
v = oh->_sysc_cache;
+ sf = oh->class->sysc->sysc_flags;
- if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) {
+ if (sf & SYSC_HAS_SIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
_set_slave_idlemode(oh, idlemode, &v);
}
- if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) {
+ if (sf & SYSC_HAS_MIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
_set_master_standbymode(oh, idlemode, &v);
}
- if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) {
+ if (sf & SYSC_HAS_AUTOIDLE) {
idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
0 : 1;
_set_module_autoidle(oh, idlemode, &v);
@@ -600,9 +663,9 @@ static void _sysc_enable(struct omap_hwmod *oh)
* calling into this code. But this must wait until the
* clock structures are tagged with omap_hwmod entries
*/
- if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
- oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
- _set_clockactivity(oh, oh->sysconfig->clockact, &v);
+ if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
+ (sf & SYSC_HAS_CLOCKACTIVITY))
+ _set_clockactivity(oh, oh->class->sysc->clockact, &v);
_write_sysconfig(v, oh);
}
@@ -618,21 +681,22 @@ static void _sysc_enable(struct omap_hwmod *oh)
*/
static void _sysc_idle(struct omap_hwmod *oh)
{
- u8 idlemode;
+ u8 idlemode, sf;
u32 v;
- if (!oh->sysconfig)
+ if (!oh->class->sysc)
return;
v = oh->_sysc_cache;
+ sf = oh->class->sysc->sysc_flags;
- if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE) {
+ if (sf & SYSC_HAS_SIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
_set_slave_idlemode(oh, idlemode, &v);
}
- if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) {
+ if (sf & SYSC_HAS_MIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
_set_master_standbymode(oh, idlemode, &v);
@@ -651,19 +715,21 @@ static void _sysc_idle(struct omap_hwmod *oh)
static void _sysc_shutdown(struct omap_hwmod *oh)
{
u32 v;
+ u8 sf;
- if (!oh->sysconfig)
+ if (!oh->class->sysc)
return;
v = oh->_sysc_cache;
+ sf = oh->class->sysc->sysc_flags;
- if (oh->sysconfig->sysc_flags & SYSC_HAS_SIDLEMODE)
+ if (sf & SYSC_HAS_SIDLEMODE)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
- if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
+ if (sf & SYSC_HAS_MIDLEMODE)
_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
- if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)
+ if (sf & SYSC_HAS_AUTOIDLE)
_set_module_autoidle(oh, 1, &v);
_write_sysconfig(v, oh);
@@ -780,9 +846,9 @@ static int _reset(struct omap_hwmod *oh)
u32 r, v;
int c = 0;
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
- (oh->sysconfig->sysc_flags & SYSS_MISSING))
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) ||
+ (oh->class->sysc->sysc_flags & SYSS_MISSING))
return -EINVAL;
/* clocks must be on for this operation */
@@ -800,7 +866,7 @@ static int _reset(struct omap_hwmod *oh)
return r;
_write_sysconfig(v, oh);
- omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
+ omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) &
SYSS_RESETDONE_MASK),
MAX_MODULE_RESET_WAIT, c);
@@ -846,7 +912,7 @@ static int _enable(struct omap_hwmod *oh)
_add_initiator_dep(oh, mpu_oh);
_enable_clocks(oh);
- if (oh->sysconfig) {
+ if (oh->class->sysc) {
if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
_update_sysc_cache(oh);
_sysc_enable(oh);
@@ -877,7 +943,7 @@ static int _idle(struct omap_hwmod *oh)
pr_debug("omap_hwmod: %s: idling\n", oh->name);
- if (oh->sysconfig)
+ if (oh->class->sysc)
_sysc_idle(oh);
_del_initiator_dep(oh, mpu_oh);
_disable_clocks(oh);
@@ -907,7 +973,7 @@ static int _shutdown(struct omap_hwmod *oh)
pr_debug("omap_hwmod: %s: disabling\n", oh->name);
- if (oh->sysconfig)
+ if (oh->class->sysc)
_sysc_shutdown(oh);
_del_initiator_dep(oh, mpu_oh);
/* XXX what about the other system initiators here? DMA, tesla, d2d */
@@ -967,7 +1033,7 @@ static int _setup(struct omap_hwmod *oh)
* _enable() function should be split to avoid the
* rewrite of the OCP_SYSCONFIG register.
*/
- if (oh->sysconfig) {
+ if (oh->class->sysc) {
_update_sysc_cache(oh);
_sysc_enable(oh);
}
@@ -993,13 +1059,33 @@ void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
__raw_writel(v, oh->_rt_va + reg_offs);
}
+int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
+{
+ u32 v;
+ int retval = 0;
+
+ if (!oh)
+ return -EINVAL;
+
+ v = oh->_sysc_cache;
+
+ retval = _set_slave_idlemode(oh, idlemode, &v);
+ if (!retval)
+ _write_sysconfig(v, oh);
+
+ return retval;
+}
+
/**
* omap_hwmod_register - register a struct omap_hwmod
* @oh: struct omap_hwmod *
*
- * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod already
- * has been registered by the same name; -EINVAL if the omap_hwmod is in the
- * wrong state, or 0 on success.
+ * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod
+ * already has been registered by the same name; -EINVAL if the
+ * omap_hwmod is in the wrong state, if @oh is NULL, if the
+ * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
+ * name, or if the omap_hwmod's class is missing a name; or 0 upon
+ * success.
*
* XXX The data should be copied into bootmem, so the original data
* should be marked __initdata and freed after init. This would allow
@@ -1011,7 +1097,8 @@ int omap_hwmod_register(struct omap_hwmod *oh)
{
int ret, ms_id;
- if (!oh || (oh->_state != _HWMOD_STATE_UNKNOWN))
+ if (!oh || !oh->name || !oh->class || !oh->class->name ||
+ (oh->_state != _HWMOD_STATE_UNKNOWN))
return -EINVAL;
mutex_lock(&omap_hwmod_mutex);
@@ -1284,7 +1371,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
{
BUG_ON(!oh);
- if (!oh->sysconfig || !oh->sysconfig->sysc_flags) {
+ if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
WARN(1, "omap_device: %s: OCP barrier impossible due to "
"device configuration\n", oh->name);
return;
@@ -1294,7 +1381,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
* Forces posted writes to complete on the OCP thread handling
* register writes
*/
- omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);
+ omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
}
/**
@@ -1424,6 +1511,9 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
c = oh->slaves[oh->_mpu_port_index]->_clk;
}
+ if (!c->clkdm)
+ return NULL;
+
return c->clkdm->pwrdm.ptr;
}
@@ -1487,8 +1577,8 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
*/
int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
return -EINVAL;
mutex_lock(&omap_hwmod_mutex);
@@ -1512,8 +1602,8 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
*/
int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
{
- if (!oh->sysconfig ||
- !(oh->sysconfig->sysc_flags & SYSC_HAS_ENAWAKEUP))
+ if (!oh->class->sysc ||
+ !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
return -EINVAL;
mutex_lock(&omap_hwmod_mutex);
@@ -1522,3 +1612,52 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
return 0;
}
+
+/**
+ * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
+ * @classname: struct omap_hwmod_class name to search for
+ * @fn: callback function pointer to call for each hwmod in class @classname
+ * @user: arbitrary context data to pass to the callback function
+ *
+ * For each omap_hwmod of class @classname, call @fn. Takes
+ * omap_hwmod_mutex to prevent the hwmod list from changing during the
+ * iteration. If the callback function returns something other than
+ * zero, the iterator is terminated, and the callback function's return
+ * value is passed back to the caller. Returns 0 upon success, -EINVAL
+ * if @classname or @fn are NULL, or passes back the error code from @fn.
+ */
+int omap_hwmod_for_each_by_class(const char *classname,
+ int (*fn)(struct omap_hwmod *oh,
+ void *user),
+ void *user)
+{
+ struct omap_hwmod *temp_oh;
+ int ret = 0;
+
+ if (!classname || !fn)
+ return -EINVAL;
+
+ pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
+ __func__, classname);
+
+ mutex_lock(&omap_hwmod_mutex);
+
+ list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
+ if (!strcmp(temp_oh->class->name, classname)) {
+ pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
+ __func__, temp_oh->name);
+ ret = (*fn)(temp_oh, user);
+ if (ret)
+ break;
+ }
+ }
+
+ mutex_unlock(&omap_hwmod_mutex);
+
+ if (ret)
+ pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
+ __func__, ret);
+
+ return ret;
+}
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a9ca1b99a30..eb7ee2453b2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420.h
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1,7 +1,7 @@
/*
- * omap_hwmod_2420.h - hardware modules present on the OMAP2420 chips
+ * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
*
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -9,20 +9,26 @@
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
- *
+ * XXX these should be marked initdata for multi-OMAP kernels
*/
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H
-
-#ifdef CONFIG_ARCH_OMAP2420
-
#include <plat/omap_hwmod.h>
#include <mach/irqs.h>
#include <plat/cpu.h>
#include <plat/dma.h>
+#include "omap_hwmod_common_data.h"
+
#include "prm-regbits-24xx.h"
+/*
+ * OMAP2420 hardware module integration data
+ *
+ * ALl of the data in this section should be autogeneratable from the
+ * TI hardware database or other technical documentation. Data that
+ * is driver-specific or driver-kernel integration-specific belongs
+ * elsewhere.
+ */
+
static struct omap_hwmod omap2420_mpu_hwmod;
static struct omap_hwmod omap2420_l3_hwmod;
static struct omap_hwmod omap2420_l4_core_hwmod;
@@ -54,6 +60,7 @@ static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = {
/* L3 */
static struct omap_hwmod omap2420_l3_hwmod = {
.name = "l3_hwmod",
+ .class = &l3_hwmod_class,
.masters = omap2420_l3_masters,
.masters_cnt = ARRAY_SIZE(omap2420_l3_masters),
.slaves = omap2420_l3_slaves,
@@ -83,6 +90,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
/* L4 CORE */
static struct omap_hwmod omap2420_l4_core_hwmod = {
.name = "l4_core_hwmod",
+ .class = &l4_hwmod_class,
.masters = omap2420_l4_core_masters,
.masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
.slaves = omap2420_l4_core_slaves,
@@ -102,6 +110,7 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
/* L4 WKUP */
static struct omap_hwmod omap2420_l4_wkup_hwmod = {
.name = "l4_wkup_hwmod",
+ .class = &l4_hwmod_class,
.masters = omap2420_l4_wkup_masters,
.masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
.slaves = omap2420_l4_wkup_slaves,
@@ -117,8 +126,8 @@ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
/* MPU */
static struct omap_hwmod omap2420_mpu_hwmod = {
.name = "mpu_hwmod",
- .clkdev_dev_id = NULL,
- .clkdev_con_id = "mpu_ck",
+ .class = &mpu_hwmod_class,
+ .main_clk = "mpu_ck",
.masters = omap2420_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -132,10 +141,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
NULL,
};
-#else
-# define omap2420_hwmods 0
-#endif
-
-#endif
+int __init omap2420_hwmod_init(void)
+{
+ return omap_hwmod_init(omap2420_hwmods);
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 59a208bea6c..241bd823072 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430.h
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1,7 +1,7 @@
/*
- * omap_hwmod_2430.h - hardware modules present on the OMAP2430 chips
+ * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
*
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -9,20 +9,26 @@
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
- *
+ * XXX these should be marked initdata for multi-OMAP kernels
*/
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H
-
-#ifdef CONFIG_ARCH_OMAP2430
-
#include <plat/omap_hwmod.h>
#include <mach/irqs.h>
#include <plat/cpu.h>
#include <plat/dma.h>
+#include "omap_hwmod_common_data.h"
+
#include "prm-regbits-24xx.h"
+/*
+ * OMAP2430 hardware module integration data
+ *
+ * ALl of the data in this section should be autogeneratable from the
+ * TI hardware database or other technical documentation. Data that
+ * is driver-specific or driver-kernel integration-specific belongs
+ * elsewhere.
+ */
+
static struct omap_hwmod omap2430_mpu_hwmod;
static struct omap_hwmod omap2430_l3_hwmod;
static struct omap_hwmod omap2430_l4_core_hwmod;
@@ -54,6 +60,7 @@ static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = {
/* L3 */
static struct omap_hwmod omap2430_l3_hwmod = {
.name = "l3_hwmod",
+ .class = &l3_hwmod_class,
.masters = omap2430_l3_masters,
.masters_cnt = ARRAY_SIZE(omap2430_l3_masters),
.slaves = omap2430_l3_slaves,
@@ -85,6 +92,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
/* L4 CORE */
static struct omap_hwmod omap2430_l4_core_hwmod = {
.name = "l4_core_hwmod",
+ .class = &l4_hwmod_class,
.masters = omap2430_l4_core_masters,
.masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
.slaves = omap2430_l4_core_slaves,
@@ -104,6 +112,7 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
/* L4 WKUP */
static struct omap_hwmod omap2430_l4_wkup_hwmod = {
.name = "l4_wkup_hwmod",
+ .class = &l4_hwmod_class,
.masters = omap2430_l4_wkup_masters,
.masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
.slaves = omap2430_l4_wkup_slaves,
@@ -119,8 +128,8 @@ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
/* MPU */
static struct omap_hwmod omap2430_mpu_hwmod = {
.name = "mpu_hwmod",
- .clkdev_dev_id = NULL,
- .clkdev_con_id = "mpu_ck",
+ .class = &mpu_hwmod_class,
+ .main_clk = "mpu_ck",
.masters = omap2430_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -134,10 +143,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
NULL,
};
-#else
-# define omap2430_hwmods 0
-#endif
-
-#endif
+int __init omap2430_hwmod_init(void)
+{
+ return omap_hwmod_init(omap2430_hwmods);
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h
deleted file mode 100644
index b6076b9c364..00000000000
--- a/arch/arm/mach-omap2/omap_hwmod_34xx.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips
- *
- * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
-
-#ifdef CONFIG_ARCH_OMAP34XX
-
-#include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
-#include <plat/dma.h>
-
-#include "prm-regbits-34xx.h"
-
-static struct omap_hwmod omap34xx_mpu_hwmod;
-static struct omap_hwmod omap34xx_l3_hwmod;
-static struct omap_hwmod omap34xx_l4_core_hwmod;
-static struct omap_hwmod omap34xx_l4_per_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = {
- .master = &omap34xx_l3_hwmod,
- .slave = &omap34xx_l4_core_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L3 -> L4_PER interface */
-static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = {
- .master = &omap34xx_l3_hwmod,
- .slave = &omap34xx_l4_per_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = {
- .master = &omap34xx_mpu_hwmod,
- .slave = &omap34xx_l3_hwmod,
- .user = OCP_USER_MPU,
-};
-
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = {
- &omap34xx_mpu__l3,
-};
-
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = {
- &omap34xx_l3__l4_core,
- &omap34xx_l3__l4_per,
-};
-
-/* L3 */
-static struct omap_hwmod omap34xx_l3_hwmod = {
- .name = "l3_hwmod",
- .masters = omap34xx_l3_masters,
- .masters_cnt = ARRAY_SIZE(omap34xx_l3_masters),
- .slaves = omap34xx_l3_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_l3_slaves),
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-};
-
-static struct omap_hwmod omap34xx_l4_wkup_hwmod;
-
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = {
- .master = &omap34xx_l4_core_hwmod,
- .slave = &omap34xx_l4_wkup_hwmod,
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = {
- &omap34xx_l3__l4_core,
-};
-
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = {
- &omap34xx_l4_core__l4_wkup,
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap34xx_l4_core_hwmod = {
- .name = "l4_core_hwmod",
- .masters = omap34xx_l4_core_masters,
- .masters_cnt = ARRAY_SIZE(omap34xx_l4_core_masters),
- .slaves = omap34xx_l4_core_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_l4_core_slaves),
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-};
-
-/* Slave interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = {
- &omap34xx_l3__l4_per,
-};
-
-/* Master interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = {
-};
-
-/* L4 PER */
-static struct omap_hwmod omap34xx_l4_per_hwmod = {
- .name = "l4_per_hwmod",
- .masters = omap34xx_l4_per_masters,
- .masters_cnt = ARRAY_SIZE(omap34xx_l4_per_masters),
- .slaves = omap34xx_l4_per_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_l4_per_slaves),
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-};
-
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = {
- &omap34xx_l4_core__l4_wkup,
-};
-
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = {
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap34xx_l4_wkup_hwmod = {
- .name = "l4_wkup_hwmod",
- .masters = omap34xx_l4_wkup_masters,
- .masters_cnt = ARRAY_SIZE(omap34xx_l4_wkup_masters),
- .slaves = omap34xx_l4_wkup_slaves,
- .slaves_cnt = ARRAY_SIZE(omap34xx_l4_wkup_slaves),
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-};
-
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = {
- &omap34xx_mpu__l3,
-};
-
-/* MPU */
-static struct omap_hwmod omap34xx_mpu_hwmod = {
- .name = "mpu_hwmod",
- .clkdev_dev_id = NULL,
- .clkdev_con_id = "arm_fck",
- .masters = omap34xx_mpu_masters,
- .masters_cnt = ARRAY_SIZE(omap34xx_mpu_masters),
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-};
-
-static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
- &omap34xx_l3_hwmod,
- &omap34xx_l4_core_hwmod,
- &omap34xx_l4_per_hwmod,
- &omap34xx_l4_wkup_hwmod,
- &omap34xx_mpu_hwmod,
- NULL,
-};
-
-#else
-# define omap34xx_hwmods 0
-#endif
-
-#endif
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
new file mode 100644
index 00000000000..ed608400426
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -0,0 +1,181 @@
+/*
+ * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
+ *
+ * Copyright (C) 2009-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The data in this file should be completely autogeneratable from
+ * the TI hardware database or other technical documentation.
+ *
+ * XXX these should be marked initdata for multi-OMAP kernels
+ */
+#include <plat/omap_hwmod.h>
+#include <mach/irqs.h>
+#include <plat/cpu.h>
+#include <plat/dma.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "prm-regbits-34xx.h"
+
+/*
+ * OMAP3xxx hardware module integration data
+ *
+ * ALl of the data in this section should be autogeneratable from the
+ * TI hardware database or other technical documentation. Data that
+ * is driver-specific or driver-kernel integration-specific belongs
+ * elsewhere.
+ */
+
+static struct omap_hwmod omap3xxx_mpu_hwmod;
+static struct omap_hwmod omap3xxx_l3_hwmod;
+static struct omap_hwmod omap3xxx_l4_core_hwmod;
+static struct omap_hwmod omap3xxx_l4_per_hwmod;
+
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = {
+ .master = &omap3xxx_l3_hwmod,
+ .slave = &omap3xxx_l4_core_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L3 -> L4_PER interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = {
+ .master = &omap3xxx_l3_hwmod,
+ .slave = &omap3xxx_l4_per_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = {
+ .master = &omap3xxx_mpu_hwmod,
+ .slave = &omap3xxx_l3_hwmod,
+ .user = OCP_USER_MPU,
+};
+
+/* Slave interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = {
+ &omap3xxx_mpu__l3,
+};
+
+/* Master interfaces on the L3 interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = {
+ &omap3xxx_l3__l4_core,
+ &omap3xxx_l3__l4_per,
+};
+
+/* L3 */
+static struct omap_hwmod omap3xxx_l3_hwmod = {
+ .name = "l3_hwmod",
+ .class = &l3_hwmod_class,
+ .masters = omap3xxx_l3_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters),
+ .slaves = omap3xxx_l3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
+
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_l4_wkup_hwmod,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* Slave interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
+ &omap3xxx_l3__l4_core,
+};
+
+/* Master interfaces on the L4_CORE interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
+ &omap3xxx_l4_core__l4_wkup,
+};
+
+/* L4 CORE */
+static struct omap_hwmod omap3xxx_l4_core_hwmod = {
+ .name = "l4_core_hwmod",
+ .class = &l4_hwmod_class,
+ .masters = omap3xxx_l4_core_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
+ .slaves = omap3xxx_l4_core_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* Slave interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
+ &omap3xxx_l3__l4_per,
+};
+
+/* Master interfaces on the L4_PER interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
+};
+
+/* L4 PER */
+static struct omap_hwmod omap3xxx_l4_per_hwmod = {
+ .name = "l4_per_hwmod",
+ .class = &l4_hwmod_class,
+ .masters = omap3xxx_l4_per_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
+ .slaves = omap3xxx_l4_per_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* Slave interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
+ &omap3xxx_l4_core__l4_wkup,
+};
+
+/* Master interfaces on the L4_WKUP interconnect */
+static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
+};
+
+/* L4 WKUP */
+static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
+ .name = "l4_wkup_hwmod",
+ .class = &l4_hwmod_class,
+ .masters = omap3xxx_l4_wkup_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
+ .slaves = omap3xxx_l4_wkup_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* Master interfaces on the MPU device */
+static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
+ &omap3xxx_mpu__l3,
+};
+
+/* MPU */
+static struct omap_hwmod omap3xxx_mpu_hwmod = {
+ .name = "mpu_hwmod",
+ .class = &mpu_hwmod_class,
+ .main_clk = "arm_fck",
+ .masters = omap3xxx_mpu_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ &omap3xxx_l3_hwmod,
+ &omap3xxx_l4_core_hwmod,
+ &omap3xxx_l4_per_hwmod,
+ &omap3xxx_l4_wkup_hwmod,
+ &omap3xxx_mpu_hwmod,
+ NULL,
+};
+
+int __init omap3xxx_hwmod_init(void)
+{
+ return omap_hwmod_init(omap3xxx_hwmods);
+}
+
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
new file mode 100644
index 00000000000..1e80b914fa1
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -0,0 +1,68 @@
+/*
+ * omap_hwmod common data structures
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ * Benoît Cousson
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This data/structures are to be used while defining OMAP on-chip module
+ * data and their integration with other OMAP modules and Linux.
+ */
+
+#include <plat/omap_hwmod.h>
+
+#include "omap_hwmod_common_data.h"
+
+/**
+ * struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme.
+ *
+ * To be used by hwmod structure to specify the sysconfig offsets
+ * if the device ip is compliant with the original PRCM protocol
+ * defined for OMAP2420.
+ */
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
+ .midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT,
+ .clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
+ .sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT,
+ .enwkup_shift = SYSC_TYPE1_ENAWAKEUP_SHIFT,
+ .srst_shift = SYSC_TYPE1_SOFTRESET_SHIFT,
+ .autoidle_shift = SYSC_TYPE1_AUTOIDLE_SHIFT,
+};
+
+/**
+ * struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme.
+ *
+ * To be used by hwmod structure to specify the sysconfig offsets if the
+ * device ip is compliant with the new PRCM protocol defined for new
+ * OMAP4 IPs.
+ */
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
+ .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT,
+ .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT,
+ .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
+};
+
+
+/*
+ * omap_hwmod class data
+ */
+
+struct omap_hwmod_class l3_hwmod_class = {
+ .name = "l3"
+};
+
+struct omap_hwmod_class l4_hwmod_class = {
+ .name = "l4"
+};
+
+struct omap_hwmod_class mpu_hwmod_class = {
+ .name = "mpu"
+};
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
new file mode 100644
index 00000000000..3645a28c7c2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -0,0 +1,24 @@
+/*
+ * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Benoît Cousson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H
+
+#include <plat/omap_hwmod.h>
+
+/* OMAP hwmod classes - forward declarations */
+extern struct omap_hwmod_class l3_hwmod_class;
+extern struct omap_hwmod_class l4_hwmod_class;
+extern struct omap_hwmod_class mpu_hwmod_class;
+
+#endif
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index 126a9396b3a..e6dda694fd5 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -9,45 +9,47 @@
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
* These configurations are characterized by voltage and speed for clocks.
* The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
+ * these combinations is via the 'ratios' which the clocks operate with
* respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
+ * setting. All configurations can be described by a DPLL setting and a ratio.
*
* XXX Missing voltage data.
+ * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
*
* THe format described in this file is deprecated. Once a reasonable
* OPP API exists, the data in this file should be converted to use it.
*
* This is technically part of the OMAP2xxx clock code.
+ *
+ * Considerable work is still needed to fully support dynamic frequency
+ * changes on OMAP2xxx-series chips. Readers interested in such a
+ * project are encouraged to review the Maemo Diablo RX-34 and RX-44
+ * kernel source at:
+ * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
*/
#include "opp2xxx.h"
#include "sdrc.h"
#include "clock.h"
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+/*
+ * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
*
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
+ * Filling in table based on H4 boards available. There are quite a
+ * few more rate combinations which could be defined.
*
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used. Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set. The exception is the bypass setting which is
- * availble for low power bypass.
+ * When multiple values are defined the start up will try and choose
+ * the fastest one. If a 'fast' value is defined, then automatically,
+ * the /2 one should be included as it can be used. Generally having
+ * more than one fast set does not make sense, as static timings need
+ * to be changed to change the set. The exception is the bypass
+ * setting which is available for low power bypass.
*
* Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
+ **/
const struct prcm_config omap2420_rate_table[] = {
/* PRCM I - FAST */
{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index edb81672c84..1b9596ae201 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -1,5 +1,5 @@
/*
- * opp2420_data.c - old-style "OPP" table for OMAP2420
+ * opp2430_data.c - old-style "OPP" table for OMAP2430
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
@@ -9,16 +9,16 @@
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
* These configurations are characterized by voltage and speed for clocks.
* The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
+ * these combinations is via the 'ratios' which the clocks operate with
* respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ * setting. All configurations can be described by a DPLL setting and a ratio.
*
* 2430 differs from 2420 in that there are no more phase synchronizers used.
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
* 2430 (iva2.1, NOdsp, mdm)
*
* XXX Missing voltage data.
+ * XXX Missing 19.2MHz sys_clk rate sets.
*
* THe format described in this file is deprecated. Once a reasonable
* OPP API exists, the data in this file should be converted to use it.
@@ -30,24 +30,24 @@
#include "sdrc.h"
#include "clock.h"
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+/*
+ * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
*
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
+ * Filling in table based on 2430-SDPs variants available. There are
+ * quite a few more rate combinations which could be defined.
*
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used. Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set. The exception is the bypass setting which is
- * availble for low power bypass.
+ * When multiple values are defined the start up will try and choose
+ * the fastest one. If a 'fast' value is defined, then automatically,
+ * the /2 one should be included as it can be used. Generally having
+ * more than one fast set does not make sense, as static timings need
+ * to be changed to change the set. The exception is the bypass
+ * setting which is available for low power bypass.
*
* Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
+ */
const struct prcm_config omap2430_rate_table[] = {
/* PRCM #4 - ratio2 (ES2.1) - FAST */
{S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index ed6df04e2f2..38b73055050 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -417,7 +417,12 @@ struct prcm_config {
extern const struct prcm_config omap2420_rate_table[];
+
+#ifdef CONFIG_ARCH_OMAP2430
extern const struct prcm_config omap2430_rate_table[];
+#else
+#define omap2430_rate_table NULL
+#endif
extern const struct prcm_config *rate_table;
extern const struct prcm_config *curr_prcm_set;
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 860b755d222..6cac9817c24 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -25,6 +25,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/slab.h>
#include <plat/clock.h>
#include <plat/board.h>
@@ -54,8 +55,6 @@ int omap2_pm_debug;
regs[reg_count++].val = \
__raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
-static int __init pm_dbg_init(void);
-
void omap2_pm_dump(int mode, int resume, unsigned int us)
{
struct reg {
@@ -69,9 +68,9 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
#if 0
/* MPU */
DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
- DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
- DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
- DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
+ DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
+ DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
+ DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
#endif
#if 0
@@ -95,7 +94,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
- DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
+ DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
#endif
#if 0
/* DSP */
@@ -105,11 +104,11 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
+ DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
+ DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
+ DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
+ DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
+ DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
}
#endif
} else {
@@ -167,6 +166,8 @@ struct dentry *pm_dbg_dir;
static int pm_dbg_init_done;
+static int __init pm_dbg_init(void);
+
enum {
DEBUG_FILE_COUNTERS = 0,
DEBUG_FILE_TIMERS,
@@ -385,6 +386,11 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
seq_printf(s, ",%s:%d", pwrdm_state_names[i],
pwrdm->state_counter[i]);
+ seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
+ for (i = 0; i < pwrdm->banks; i++)
+ seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
+ pwrdm->ret_mem_off_counter[i]);
+
seq_printf(s, "\n");
return 0;
@@ -488,9 +494,11 @@ int pm_dbg_regset_init(int reg_set)
static int pwrdm_suspend_get(void *data, u64 *val)
{
- *val = omap3_pm_get_suspend_state((struct powerdomain *)data);
+ int ret;
+ ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
+ *val = ret;
- if (*val >= 0)
+ if (ret >= 0)
return 0;
return *val;
}
@@ -575,7 +583,7 @@ static int __init pm_dbg_init(void)
(void) debugfs_create_file("time", S_IRUGO,
d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
- pwrdm_for_each_nolock(pwrdms_setup, (void *)d);
+ pwrdm_for_each(pwrdms_setup, (void *)d);
pm_dbg_dir = debugfs_create_dir("registers", d);
if (IS_ERR(pm_dbg_dir))
@@ -604,6 +612,4 @@ static int __init pm_dbg_init(void)
}
arch_initcall(pm_dbg_init);
-#else
-void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
#endif
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0bf345db714..bd6466a2b03 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -23,6 +23,22 @@ extern int omap3_can_sleep(void);
extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
extern int omap3_idle_init(void);
+struct cpuidle_params {
+ u8 valid;
+ u32 sleep_latency;
+ u32 wake_latency;
+ u32 threshold;
+};
+
+#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
+extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
+#else
+static
+inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
+{
+}
+#endif
+
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
@@ -32,12 +48,20 @@ extern struct omap_dm_timer *gptimer_wakeup;
#ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern int omap2_pm_debug;
+#else
+#define omap2_pm_dump(mode, resume, us) do {} while (0);
+#define omap2_pm_debug 0
+#endif
+
+#if defined(CONFIG_CPU_IDLE)
+extern void omap3_cpuidle_update_states(void);
+#endif
+
+#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
extern int pm_dbg_regset_save(int reg_set);
extern int pm_dbg_regset_init(int reg_set);
#else
-#define omap2_pm_dump(mode, resume, us) do {} while (0);
-#define omap2_pm_debug 0
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#define pm_dbg_regset_save(reg_set) do {} while (0);
#define pm_dbg_regset_init(reg_set) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index cba05b9f041..374299ea7ad 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -57,11 +57,8 @@ static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
void __iomem *sdrc_power);
-static struct powerdomain *mpu_pwrdm;
-static struct powerdomain *core_pwrdm;
-
-static struct clockdomain *dsp_clkdm;
-static struct clockdomain *gfx_clkdm;
+static struct powerdomain *mpu_pwrdm, *core_pwrdm;
+static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
static struct clk *osc_ck, *emul_ck;
@@ -219,11 +216,12 @@ static void omap2_enter_mpu_retention(void)
/* Try to enter MPU retention */
prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
OMAP_LOGICRETSTATE,
- MPU_MOD, PM_PWSTCTRL);
+ MPU_MOD, OMAP2_PM_PWSTCTRL);
} else {
/* Block MPU retention */
- prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
+ prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,
+ OMAP2_PM_PWSTCTRL);
only_idle = 1;
}
@@ -333,9 +331,17 @@ static struct platform_suspend_ops omap_pm_ops = {
.valid = suspend_valid_only_mem,
};
-static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
+/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
- omap2_clkdm_allow_idle(clkdm);
+ clkdm_clear_all_wkdeps(clkdm);
+ clkdm_clear_all_sleepdeps(clkdm);
+
+ if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+ omap2_clkdm_allow_idle(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+ atomic_read(&clkdm->usecount) == 0)
+ omap2_clkdm_sleep(clkdm);
return 0;
}
@@ -348,14 +354,6 @@ static void __init prcm_setup_regs(void)
prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
OMAP2_PRCM_SYSCONFIG_OFFSET);
- /* Set all domain wakeup dependencies */
- prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
- prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
- prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
- prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
- if (cpu_is_omap2430())
- prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
-
/*
* Set CORE powerdomain memory banks to retain their contents
* during RETENTION
@@ -384,8 +382,12 @@ static void __init prcm_setup_regs(void)
pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
omap2_clkdm_sleep(gfx_clkdm);
- /* Enable clockdomain hardware-supervised control for all clkdms */
- clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
+ /*
+ * Clear clockdomain wakeup dependencies and enable
+ * hardware-supervised idle for all clkdms
+ */
+ clkdm_for_each(clkdms_setup, NULL);
+ clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
/* Enable clock autoidle for all domains */
cm_write_mod_reg(OMAP24XX_AUTO_CAM |
@@ -481,7 +483,7 @@ static int __init omap2_pm_init(void)
l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
- /* Look up important powerdomains, clockdomains */
+ /* Look up important powerdomains */
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
if (!mpu_pwrdm)
@@ -491,9 +493,19 @@ static int __init omap2_pm_init(void)
if (!core_pwrdm)
pr_err("PM: core_pwrdm not found\n");
+ /* Look up important clockdomains */
+
+ mpu_clkdm = clkdm_lookup("mpu_clkdm");
+ if (!mpu_clkdm)
+ pr_err("PM: mpu_clkdm not found\n");
+
+ wkup_clkdm = clkdm_lookup("wkup_clkdm");
+ if (!wkup_clkdm)
+ pr_err("PM: wkup_clkdm not found\n");
+
dsp_clkdm = clkdm_lookup("dsp_clkdm");
if (!dsp_clkdm)
- pr_err("PM: mpu_clkdm not found\n");
+ pr_err("PM: dsp_clkdm not found\n");
gfx_clkdm = clkdm_lookup("gfx_clkdm");
if (!gfx_clkdm)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 81ed252a0f8..ea0000bc535 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -26,6 +26,8 @@
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
#include <plat/sram.h>
#include <plat/clockdomain.h>
@@ -124,9 +126,17 @@ static void omap3_core_save_context(void)
control_padconf_off |= START_PADCONF_SAVE;
omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
/* wait for the save to complete */
- while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
- & PADCONF_SAVE_DONE)
- ;
+ while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
+ & PADCONF_SAVE_DONE))
+ udelay(1);
+
+ /*
+ * Force write last pad into memory, as this can fail in some
+ * cases according to erratas 1.157, 1.185
+ */
+ omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
+ OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
+
/* Save the Interrupt controller context */
omap_intc_save_context();
/* Save the GPMC context */
@@ -392,6 +402,7 @@ void omap_sram_idle(void)
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
omap3_enable_io_chain();
}
+ omap3_intc_prepare_idle();
/*
* On EMU/HS devices ROM code restores a SRDC value
@@ -438,6 +449,7 @@ void omap_sram_idle(void)
OMAP3430_GR_MOD,
OMAP3_PRM_VOLTCTRL_OFFSET);
}
+ omap3_intc_resume_idle();
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
@@ -578,6 +590,8 @@ static int omap3_pm_suspend(void)
}
omap_uart_prepare_suspend();
+ omap3_intc_suspend();
+
omap_sram_idle();
restore:
@@ -672,10 +686,10 @@ static void __init omap3_iva_idle(void)
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
- OMAP3430_IVA2_MOD, RM_RSTCTRL);
+ OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Enable IVA2 clock */
- cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
+ cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
OMAP3430_IVA2_MOD, CM_FCLKEN);
/* Set IVA2 boot mode to 'idle' */
@@ -683,7 +697,7 @@ static void __init omap3_iva_idle(void)
OMAP343X_CONTROL_IVA2_BOOTMOD);
/* Un-reset IVA2 */
- prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
+ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
/* Disable IVA2 clock */
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
@@ -692,7 +706,7 @@ static void __init omap3_iva_idle(void)
prm_write_mod_reg(OMAP3430_RST1_IVA2 |
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
- OMAP3430_IVA2_MOD, RM_RSTCTRL);
+ OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
}
static void __init omap3_d2d_idle(void)
@@ -715,8 +729,8 @@ static void __init omap3_d2d_idle(void)
/* reset modem */
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
- CORE_MOD, RM_RSTCTRL);
- prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
+ CORE_MOD, OMAP2_RM_RSTCTRL);
+ prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
}
static void __init prcm_setup_regs(void)
@@ -835,6 +849,8 @@ static void __init prcm_setup_regs(void)
CM_AUTOIDLE);
}
+ omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
+
/*
* Set all plls to autoidle. This is needed until autoidle is
* enabled by clockfw
@@ -875,15 +891,23 @@ static void __init prcm_setup_regs(void)
prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+ /* Enable PM_WKEN to support DSS LPR */
+ prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
+ OMAP3430_DSS_MOD, PM_WKEN);
+
/* Enable wakeups in PER */
prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
- OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
+ OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
+ OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
+ OMAP3430_EN_MCBSP4,
OMAP3430_PER_MOD, PM_WKEN);
/* and allow them to wake up MPU */
prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
- OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
+ OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
+ OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
+ OMAP3430_EN_MCBSP4,
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
/* Don't attach IVA interrupts */
@@ -893,31 +917,13 @@ static void __init prcm_setup_regs(void)
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
/* Clear any pending 'reset' flags */
- prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
-
- /* Clear any pending PRCM interrupts */
- prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-
- /* Don't attach IVA interrupts */
- prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
- prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
- prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
- prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
-
- /* Clear any pending 'reset' flags */
- prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
- prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+ prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+ prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
@@ -936,6 +942,10 @@ void omap3_pm_off_mode_enable(int enable)
else
state = PWRDM_POWER_RET;
+#ifdef CONFIG_CPU_IDLE
+ omap3_cpuidle_update_states();
+#endif
+
list_for_each_entry(pwrst, &pwrst_list, node) {
pwrst->next_state = state;
set_pwrdm_state(pwrst->pwrdm, state);
@@ -993,6 +1003,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
*/
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
+ clkdm_clear_all_wkdeps(clkdm);
+ clkdm_clear_all_sleepdeps(clkdm);
+
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
omap2_clkdm_allow_idle(clkdm);
else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
@@ -1013,6 +1026,7 @@ void omap_push_sram_idle(void)
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
+ struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
int ret;
if (!cpu_is_omap34xx())
@@ -1052,6 +1066,11 @@ static int __init omap3_pm_init(void)
core_pwrdm = pwrdm_lookup("core_pwrdm");
cam_pwrdm = pwrdm_lookup("cam_pwrdm");
+ neon_clkdm = clkdm_lookup("neon_clkdm");
+ mpu_clkdm = clkdm_lookup("mpu_clkdm");
+ per_clkdm = clkdm_lookup("per_clkdm");
+ core_clkdm = clkdm_lookup("core_clkdm");
+
omap_push_sram_idle();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops);
@@ -1060,14 +1079,14 @@ static int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
omap3_idle_init();
- pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
+ clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
/*
* REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
* IO-pad wakeup. Otherwise it will unnecessarily waste power
* waking up PER with every CORE wakeup - see
* http://marc.info/?l=linux-omap&m=121852150710062&w=2
*/
- pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
+ clkdm_add_wkdep(per_clkdm, core_clkdm);
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 26b3f3ee82a..ebfce7d1a5d 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -2,10 +2,12 @@
* OMAP powerdomain control
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
*
+ * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@@ -26,12 +28,15 @@
#include "cm.h"
#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
#include <plat/cpu.h>
#include <plat/powerdomain.h>
#include <plat/clockdomain.h>
+#include <plat/prcm.h>
#include "pm.h"
@@ -40,28 +45,42 @@ enum {
PWRDM_STATE_PREV,
};
-/* pwrdm_list contains all registered struct powerdomains */
-static LIST_HEAD(pwrdm_list);
+/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */
+static u16 pwrstctrl_reg_offs;
-/*
- * pwrdm_rwlock protects pwrdm_list add and del ops - also reused to
- * protect pwrdm_clkdms[] during clkdm add/del ops
- */
-static DEFINE_RWLOCK(pwrdm_rwlock);
+/* Variable holding value of the CPU dependent PWRSTST Register Offset */
+static u16 pwrstst_reg_offs;
+/* OMAP3 and OMAP4 specific register bit initialisations
+ * Notice that the names here are not according to each power
+ * domain but the bit mapping used applies to all of them
+ */
-/* Private functions */
-
-static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
- u32 v;
+/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
+#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
+#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
+#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
+#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
+#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
+
+/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
+#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE
+#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE
+#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE
+#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE
+#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
+
+/* OMAP3 and OMAP4 Memory Status bits */
+#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
+#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
+#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
+#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
+#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
- v = prm_read_mod_reg(domain, idx);
- v &= mask;
- v >>= __ffs(mask);
+/* pwrdm_list contains all registered struct powerdomains */
+static LIST_HEAD(pwrdm_list);
- return v;
-}
+/* Private functions */
static struct powerdomain *_pwrdm_lookup(const char *name)
{
@@ -79,32 +98,63 @@ static struct powerdomain *_pwrdm_lookup(const char *name)
return pwrdm;
}
-/* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */
-static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
- struct pwrdm_dep *deps)
+/**
+ * _pwrdm_register - register a powerdomain
+ * @pwrdm: struct powerdomain * to register
+ *
+ * Adds a powerdomain to the internal powerdomain list. Returns
+ * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
+ * already registered by the provided name, or 0 upon success.
+ */
+static int _pwrdm_register(struct powerdomain *pwrdm)
{
- struct pwrdm_dep *pd;
+ int i;
+
+ if (!pwrdm)
+ return -EINVAL;
+
+ if (!omap_chip_is(pwrdm->omap_chip))
+ return -EINVAL;
- if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
- return ERR_PTR(-EINVAL);
+ if (_pwrdm_lookup(pwrdm->name))
+ return -EEXIST;
- for (pd = deps; pd->pwrdm_name; pd++) {
+ list_add(&pwrdm->node, &pwrdm_list);
- if (!omap_chip_is(pd->omap_chip))
- continue;
+ /* Initialize the powerdomain's state counter */
+ for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
+ pwrdm->state_counter[i] = 0;
- if (!pd->pwrdm && pd->pwrdm_name)
- pd->pwrdm = pwrdm_lookup(pd->pwrdm_name);
+ pwrdm->ret_logic_off_counter = 0;
+ for (i = 0; i < pwrdm->banks; i++)
+ pwrdm->ret_mem_off_counter[i] = 0;
- if (pd->pwrdm == pwrdm)
- break;
+ pwrdm_wait_transition(pwrdm);
+ pwrdm->state = pwrdm_read_pwrst(pwrdm);
+ pwrdm->state_counter[pwrdm->state] = 1;
- }
+ pr_debug("powerdomain: registered %s\n", pwrdm->name);
- if (!pd->pwrdm_name)
- return ERR_PTR(-ENOENT);
+ return 0;
+}
- return pd->pwrdm;
+static void _update_logic_membank_counters(struct powerdomain *pwrdm)
+{
+ int i;
+ u8 prev_logic_pwrst, prev_mem_pwrst;
+
+ prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm);
+ if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) &&
+ (prev_logic_pwrst == PWRDM_POWER_OFF))
+ pwrdm->ret_logic_off_counter++;
+
+ for (i = 0; i < pwrdm->banks; i++) {
+ prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i);
+
+ if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) &&
+ (prev_mem_pwrst == PWRDM_POWER_OFF))
+ pwrdm->ret_mem_off_counter[i]++;
+ }
}
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
@@ -126,6 +176,8 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
prev = pwrdm_read_prev_pwrst(pwrdm);
if (pwrdm->state != prev)
pwrdm->state_counter[prev]++;
+ if (prev == PWRDM_POWER_RET)
+ _update_logic_membank_counters(pwrdm);
break;
default:
return -EINVAL;
@@ -154,134 +206,71 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
return 0;
}
-static __init void _pwrdm_setup(struct powerdomain *pwrdm)
-{
- int i;
-
- for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
- pwrdm->state_counter[i] = 0;
-
- pwrdm_wait_transition(pwrdm);
- pwrdm->state = pwrdm_read_pwrst(pwrdm);
- pwrdm->state_counter[pwrdm->state] = 1;
-
-}
-
/* Public functions */
/**
* pwrdm_init - set up the powerdomain layer
+ * @pwrdm_list: array of struct powerdomain pointers to register
*
- * Loop through the list of powerdomains, registering all that are
- * available on the current CPU. If pwrdm_list is supplied and not
- * null, all of the referenced powerdomains will be registered. No
- * return value.
+ * Loop through the array of powerdomains @pwrdm_list, registering all
+ * that are available on the current CPU. If pwrdm_list is supplied
+ * and not null, all of the referenced powerdomains will be
+ * registered. No return value. XXX pwrdm_list is not really a
+ * "list"; it is an array. Rename appropriately.
*/
void pwrdm_init(struct powerdomain **pwrdm_list)
{
struct powerdomain **p = NULL;
- if (pwrdm_list) {
- for (p = pwrdm_list; *p; p++) {
- pwrdm_register(*p);
- _pwrdm_setup(*p);
- }
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL;
+ pwrstst_reg_offs = OMAP2_PM_PWSTST;
+ } else if (cpu_is_omap44xx()) {
+ pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL;
+ pwrstst_reg_offs = OMAP4_PM_PWSTST;
+ } else {
+ printk(KERN_ERR "Power Domain struct not supported for " \
+ "this CPU\n");
+ return;
}
-}
-
-/**
- * pwrdm_register - register a powerdomain
- * @pwrdm: struct powerdomain * to register
- *
- * Adds a powerdomain to the internal powerdomain list. Returns
- * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
- * already registered by the provided name, or 0 upon success.
- */
-int pwrdm_register(struct powerdomain *pwrdm)
-{
- unsigned long flags;
- int ret = -EINVAL;
-
- if (!pwrdm)
- return -EINVAL;
- if (!omap_chip_is(pwrdm->omap_chip))
- return -EINVAL;
-
- write_lock_irqsave(&pwrdm_rwlock, flags);
- if (_pwrdm_lookup(pwrdm->name)) {
- ret = -EEXIST;
- goto pr_unlock;
+ if (pwrdm_list) {
+ for (p = pwrdm_list; *p; p++)
+ _pwrdm_register(*p);
}
-
- list_add(&pwrdm->node, &pwrdm_list);
-
- pr_debug("powerdomain: registered %s\n", pwrdm->name);
- ret = 0;
-
-pr_unlock:
- write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
- return ret;
-}
-
-/**
- * pwrdm_unregister - unregister a powerdomain
- * @pwrdm: struct powerdomain * to unregister
- *
- * Removes a powerdomain from the internal powerdomain list. Returns
- * -EINVAL if pwrdm argument is NULL.
- */
-int pwrdm_unregister(struct powerdomain *pwrdm)
-{
- unsigned long flags;
-
- if (!pwrdm)
- return -EINVAL;
-
- write_lock_irqsave(&pwrdm_rwlock, flags);
- list_del(&pwrdm->node);
- write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
- pr_debug("powerdomain: unregistered %s\n", pwrdm->name);
-
- return 0;
}
/**
* pwrdm_lookup - look up a powerdomain by name, return a pointer
* @name: name of powerdomain
*
- * Find a registered powerdomain by its name. Returns a pointer to the
- * struct powerdomain if found, or NULL otherwise.
+ * Find a registered powerdomain by its name @name. Returns a pointer
+ * to the struct powerdomain if found, or NULL otherwise.
*/
struct powerdomain *pwrdm_lookup(const char *name)
{
struct powerdomain *pwrdm;
- unsigned long flags;
if (!name)
return NULL;
- read_lock_irqsave(&pwrdm_rwlock, flags);
pwrdm = _pwrdm_lookup(name);
- read_unlock_irqrestore(&pwrdm_rwlock, flags);
return pwrdm;
}
/**
- * pwrdm_for_each_nolock - call function on each registered clockdomain
+ * pwrdm_for_each - call function on each registered clockdomain
* @fn: callback function *
*
- * Call the supplied function for each registered powerdomain. The
- * callback function can return anything but 0 to bail out early from
- * the iterator. Returns the last return value of the callback function, which
- * should be 0 for success or anything else to indicate failure; or -EINVAL if
- * the function pointer is null.
+ * Call the supplied function @fn for each registered powerdomain.
+ * The callback function @fn can return anything but 0 to bail out
+ * early from the iterator. Returns the last return value of the
+ * callback function, which should be 0 for success or anything else
+ * to indicate failure; or -EINVAL if the function pointer is null.
*/
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user)
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user)
{
struct powerdomain *temp_pwrdm;
int ret = 0;
@@ -299,40 +288,17 @@ int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
}
/**
- * pwrdm_for_each - call function on each registered clockdomain
- * @fn: callback function *
- *
- * This function is the same as 'pwrdm_for_each_nolock()', but keeps the
- * &pwrdm_rwlock locked for reading, so no powerdomain structure manipulation
- * functions should be called from the callback, although hardware powerdomain
- * control functions are fine.
- */
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user)
-{
- unsigned long flags;
- int ret;
-
- read_lock_irqsave(&pwrdm_rwlock, flags);
- ret = pwrdm_for_each_nolock(fn, user);
- read_unlock_irqrestore(&pwrdm_rwlock, flags);
-
- return ret;
-}
-
-/**
* pwrdm_add_clkdm - add a clockdomain to a powerdomain
* @pwrdm: struct powerdomain * to add the clockdomain to
* @clkdm: struct clockdomain * to associate with a powerdomain
*
- * Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'. This
+ * Associate the clockdomain @clkdm with a powerdomain @pwrdm. This
* enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if
* presented with invalid pointers; -ENOMEM if memory could not be allocated;
* or 0 upon success.
*/
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
{
- unsigned long flags;
int i;
int ret = -EINVAL;
@@ -342,8 +308,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
pr_debug("powerdomain: associating clockdomain %s with powerdomain "
"%s\n", clkdm->name, pwrdm->name);
- write_lock_irqsave(&pwrdm_rwlock, flags);
-
for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
if (!pwrdm->pwrdm_clkdms[i])
break;
@@ -368,8 +332,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
ret = 0;
pac_exit:
- write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
return ret;
}
@@ -378,14 +340,13 @@ pac_exit:
* @pwrdm: struct powerdomain * to add the clockdomain to
* @clkdm: struct clockdomain * to associate with a powerdomain
*
- * Dissociate the clockdomain 'clkdm' from the powerdomain
- * 'pwrdm'. Returns -EINVAL if presented with invalid pointers;
- * -ENOENT if the clkdm was not associated with the powerdomain, or 0
- * upon success.
+ * Dissociate the clockdomain @clkdm from the powerdomain
+ * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT
+ * if @clkdm was not associated with the powerdomain, or 0 upon
+ * success.
*/
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
{
- unsigned long flags;
int ret = -EINVAL;
int i;
@@ -395,8 +356,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
"%s\n", clkdm->name, pwrdm->name);
- write_lock_irqsave(&pwrdm_rwlock, flags);
-
for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
if (pwrdm->pwrdm_clkdms[i] == clkdm)
break;
@@ -413,8 +372,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
ret = 0;
pdc_exit:
- write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
return ret;
}
@@ -423,259 +380,34 @@ pdc_exit:
* @pwrdm: struct powerdomain * to iterate over
* @fn: callback function *
*
- * Call the supplied function for each clockdomain in the powerdomain
- * 'pwrdm'. The callback function can return anything but 0 to bail
- * out early from the iterator. The callback function is called with
- * the pwrdm_rwlock held for reading, so no powerdomain structure
- * manipulation functions should be called from the callback, although
- * hardware powerdomain control functions are fine. Returns -EINVAL
- * if presented with invalid pointers; or passes along the last return
- * value of the callback function, which should be 0 for success or
- * anything else to indicate failure.
+ * Call the supplied function @fn for each clockdomain in the powerdomain
+ * @pwrdm. The callback function can return anything but 0 to bail
+ * out early from the iterator. Returns -EINVAL if presented with
+ * invalid pointers; or passes along the last return value of the
+ * callback function, which should be 0 for success or anything else
+ * to indicate failure.
*/
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
int (*fn)(struct powerdomain *pwrdm,
struct clockdomain *clkdm))
{
- unsigned long flags;
int ret = 0;
int i;
if (!fn)
return -EINVAL;
- read_lock_irqsave(&pwrdm_rwlock, flags);
-
for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
- read_unlock_irqrestore(&pwrdm_rwlock, flags);
-
return ret;
}
-
-/**
- * pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1
- * @pwrdm1: wake this struct powerdomain * up (dependent)
- * @pwrdm2: when this struct powerdomain * wakes up (source)
- *
- * When the powerdomain represented by pwrdm2 wakes up (due to an
- * interrupt), wake up pwrdm1. Implemented in hardware on the OMAP,
- * this feature is designed to reduce wakeup latency of the dependent
- * powerdomain. Returns -EINVAL if presented with invalid powerdomain
- * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
- * 0 upon success.
- */
-int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
- struct powerdomain *p;
-
- if (!pwrdm1)
- return -EINVAL;
-
- p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
- if (IS_ERR(p)) {
- pr_debug("powerdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
- return PTR_ERR(p);
- }
-
- pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
- pwrdm1->name, pwrdm2->name);
-
- prm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
- pwrdm1->prcm_offs, PM_WKDEP);
-
- return 0;
-}
-
-/**
- * pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1
- * @pwrdm1: wake this struct powerdomain * up (dependent)
- * @pwrdm2: when this struct powerdomain * wakes up (source)
- *
- * Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2
- * wakes up. Returns -EINVAL if presented with invalid powerdomain
- * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
- * 0 upon success.
- */
-int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
- struct powerdomain *p;
-
- if (!pwrdm1)
- return -EINVAL;
-
- p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
- if (IS_ERR(p)) {
- pr_debug("powerdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
- return PTR_ERR(p);
- }
-
- pr_debug("powerdomain: hardware will no longer wake up %s after %s "
- "wakes up\n", pwrdm1->name, pwrdm2->name);
-
- prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
- pwrdm1->prcm_offs, PM_WKDEP);
-
- return 0;
-}
-
-/**
- * pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1
- * @pwrdm1: wake this struct powerdomain * up (dependent)
- * @pwrdm2: when this struct powerdomain * wakes up (source)
- *
- * Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be
- * awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL
- * if either powerdomain pointer is invalid; or -ENOENT if the hardware
- * is incapable.
- *
- * REVISIT: Currently this function only represents software-controllable
- * wakeup dependencies. Wakeup dependencies fixed in hardware are not
- * yet handled here.
- */
-int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
- struct powerdomain *p;
-
- if (!pwrdm1)
- return -EINVAL;
-
- p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
- if (IS_ERR(p)) {
- pr_debug("powerdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
- return PTR_ERR(p);
- }
-
- return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
- (1 << pwrdm2->dep_bit));
-}
-
-/**
- * pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1
- * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
- * @pwrdm2: when this struct powerdomain * is active (source)
- *
- * Prevent pwrdm1 from automatically going inactive (and then to
- * retention or off) if pwrdm2 is still active. Returns -EINVAL if
- * presented with invalid powerdomain pointers or called on a machine
- * that does not support software-configurable hardware sleep dependencies,
- * -ENOENT if the specified dependency cannot be set in hardware, or
- * 0 upon success.
- */
-int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
- struct powerdomain *p;
-
- if (!cpu_is_omap34xx())
- return -EINVAL;
-
- if (!pwrdm1)
- return -EINVAL;
-
- p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
- if (IS_ERR(p)) {
- pr_debug("powerdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", pwrdm1->name,
- pwrdm2->name);
- return PTR_ERR(p);
- }
-
- pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
- pwrdm1->name, pwrdm2->name);
-
- cm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
- pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
-
- return 0;
-}
-
-/**
- * pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1
- * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
- * @pwrdm2: when this struct powerdomain * is active (source)
- *
- * Allow pwrdm1 to automatically go inactive (and then to retention or
- * off), independent of the activity state of pwrdm2. Returns -EINVAL
- * if presented with invalid powerdomain pointers or called on a machine
- * that does not support software-configurable hardware sleep dependencies,
- * -ENOENT if the specified dependency cannot be cleared in hardware, or
- * 0 upon success.
- */
-int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
- struct powerdomain *p;
-
- if (!cpu_is_omap34xx())
- return -EINVAL;
-
- if (!pwrdm1)
- return -EINVAL;
-
- p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
- if (IS_ERR(p)) {
- pr_debug("powerdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", pwrdm1->name,
- pwrdm2->name);
- return PTR_ERR(p);
- }
-
- pr_debug("powerdomain: will no longer prevent %s from sleeping if "
- "%s is active\n", pwrdm1->name, pwrdm2->name);
-
- cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
- pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
-
- return 0;
-}
-
-/**
- * pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1
- * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
- * @pwrdm2: when this struct powerdomain * is active (source)
- *
- * Return 1 if a hardware sleep dependency exists wherein pwrdm1 will
- * not be allowed to automatically go inactive if pwrdm2 is active;
- * 0 if pwrdm1's automatic power state inactivity transition is independent
- * of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called
- * on a machine that does not support software-configurable hardware sleep
- * dependencies; or -ENOENT if the hardware is incapable.
- *
- * REVISIT: Currently this function only represents software-controllable
- * sleep dependencies. Sleep dependencies fixed in hardware are not
- * yet handled here.
- */
-int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
- struct powerdomain *p;
-
- if (!cpu_is_omap34xx())
- return -EINVAL;
-
- if (!pwrdm1)
- return -EINVAL;
-
- p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
- if (IS_ERR(p)) {
- pr_debug("powerdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", pwrdm1->name,
- pwrdm2->name);
- return PTR_ERR(p);
- }
-
- return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
- (1 << pwrdm2->dep_bit));
-}
-
/**
* pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
* @pwrdm: struct powerdomain *
*
- * Return the number of controllable memory banks in powerdomain pwrdm,
+ * Return the number of controllable memory banks in powerdomain @pwrdm,
* starting with 1. Returns -EINVAL if the powerdomain pointer is null.
*/
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
@@ -691,7 +423,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
* @pwrdm: struct powerdomain * to set
* @pwrst: one of the PWRDM_POWER_* macros
*
- * Set the powerdomain pwrdm's next power state to pwrst. The powerdomain
+ * Set the powerdomain @pwrdm's next power state to @pwrst. The powerdomain
* may not enter this state immediately if the preconditions for this state
* have not been satisfied. Returns -EINVAL if the powerdomain pointer is
* null or if the power state is invalid for the powerdomin, or returns 0
@@ -710,7 +442,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT),
- pwrdm->prcm_offs, PM_PWSTCTRL);
+ pwrdm->prcm_offs, pwrstctrl_reg_offs);
return 0;
}
@@ -719,7 +451,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
* pwrdm_read_next_pwrst - get next powerdomain power state
* @pwrdm: struct powerdomain * to get power state
*
- * Return the powerdomain pwrdm's next power state. Returns -EINVAL
+ * Return the powerdomain @pwrdm's next power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the next power state
* upon success.
*/
@@ -728,15 +460,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
if (!pwrdm)
return -EINVAL;
- return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
- OMAP_POWERSTATE_MASK);
+ return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK);
}
/**
* pwrdm_read_pwrst - get current powerdomain power state
* @pwrdm: struct powerdomain * to get power state
*
- * Return the powerdomain pwrdm's current power state. Returns -EINVAL
+ * Return the powerdomain @pwrdm's current power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the current power state
* upon success.
*/
@@ -745,15 +477,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
if (!pwrdm)
return -EINVAL;
- return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
- OMAP_POWERSTATEST_MASK);
+ return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ pwrstst_reg_offs, OMAP_POWERSTATEST_MASK);
}
/**
* pwrdm_read_prev_pwrst - get previous powerdomain power state
* @pwrdm: struct powerdomain * to get previous power state
*
- * Return the powerdomain pwrdm's previous power state. Returns -EINVAL
+ * Return the powerdomain @pwrdm's previous power state. Returns -EINVAL
* if the powerdomain pointer is null or returns the previous power state
* upon success.
*/
@@ -771,11 +503,11 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
* @pwrdm: struct powerdomain * to set
* @pwrst: one of the PWRDM_POWER_* macros
*
- * Set the next power state that the logic portion of the powerdomain
- * pwrdm will enter when the powerdomain enters retention. This will
- * be either RETENTION or OFF, if supported. Returns -EINVAL if the
- * powerdomain pointer is null or the target power state is not not
- * supported, or returns 0 upon success.
+ * Set the next power state @pwrst that the logic portion of the
+ * powerdomain @pwrdm will enter when the powerdomain enters retention.
+ * This will be either RETENTION or OFF, if supported. Returns
+ * -EINVAL if the powerdomain pointer is null or the target power
+ * state is not not supported, or returns 0 upon success.
*/
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
{
@@ -796,7 +528,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
*/
prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
(pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
- pwrdm->prcm_offs, PM_PWSTCTRL);
+ pwrdm->prcm_offs, pwrstctrl_reg_offs);
return 0;
}
@@ -807,13 +539,14 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
* @bank: memory bank number to set (0-3)
* @pwrst: one of the PWRDM_POWER_* macros
*
- * Set the next power state that memory bank x of the powerdomain
- * pwrdm will enter when the powerdomain enters the ON state. Bank
- * will be a number from 0 to 3, and represents different types of
- * memory, depending on the powerdomain. Returns -EINVAL if the
- * powerdomain pointer is null or the target power state is not not
- * supported for this memory bank, -EEXIST if the target memory bank
- * does not exist or is not controllable, or returns 0 upon success.
+ * Set the next power state @pwrst that memory bank @bank of the
+ * powerdomain @pwrdm will enter when the powerdomain enters the ON
+ * state. @bank will be a number from 0 to 3, and represents different
+ * types of memory, depending on the powerdomain. Returns -EINVAL if
+ * the powerdomain pointer is null or the target power state is not
+ * not supported for this memory bank, -EEXIST if the target memory
+ * bank does not exist or is not controllable, or returns 0 upon
+ * success.
*/
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
{
@@ -839,16 +572,19 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
*/
switch (bank) {
case 0:
- m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK;
+ m = OMAP_MEM0_ONSTATE_MASK;
break;
case 1:
- m = OMAP3430_L1FLATMEMONSTATE_MASK;
+ m = OMAP_MEM1_ONSTATE_MASK;
break;
case 2:
- m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK;
+ m = OMAP_MEM2_ONSTATE_MASK;
break;
case 3:
- m = OMAP3430_L2FLATMEMONSTATE_MASK;
+ m = OMAP_MEM3_ONSTATE_MASK;
+ break;
+ case 4:
+ m = OMAP_MEM4_ONSTATE_MASK;
break;
default:
WARN_ON(1); /* should never happen */
@@ -856,7 +592,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
}
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
- pwrdm->prcm_offs, PM_PWSTCTRL);
+ pwrdm->prcm_offs, pwrstctrl_reg_offs);
return 0;
}
@@ -867,14 +603,15 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
* @bank: memory bank number to set (0-3)
* @pwrst: one of the PWRDM_POWER_* macros
*
- * Set the next power state that memory bank x of the powerdomain
- * pwrdm will enter when the powerdomain enters the RETENTION state.
- * Bank will be a number from 0 to 3, and represents different types
- * of memory, depending on the powerdomain. pwrst will be either
- * RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain
- * pointer is null or the target power state is not not supported for
- * this memory bank, -EEXIST if the target memory bank does not exist
- * or is not controllable, or returns 0 upon success.
+ * Set the next power state @pwrst that memory bank @bank of the
+ * powerdomain @pwrdm will enter when the powerdomain enters the
+ * RETENTION state. Bank will be a number from 0 to 3, and represents
+ * different types of memory, depending on the powerdomain. @pwrst
+ * will be either RETENTION or OFF, if supported. Returns -EINVAL if
+ * the powerdomain pointer is null or the target power state is not
+ * not supported for this memory bank, -EEXIST if the target memory
+ * bank does not exist or is not controllable, or returns 0 upon
+ * success.
*/
int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
{
@@ -900,16 +637,19 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
*/
switch (bank) {
case 0:
- m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
+ m = OMAP_MEM0_RETSTATE_MASK;
break;
case 1:
- m = OMAP3430_L1FLATMEMRETSTATE;
+ m = OMAP_MEM1_RETSTATE_MASK;
break;
case 2:
- m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
+ m = OMAP_MEM2_RETSTATE_MASK;
break;
case 3:
- m = OMAP3430_L2FLATMEMRETSTATE;
+ m = OMAP_MEM3_RETSTATE_MASK;
+ break;
+ case 4:
+ m = OMAP_MEM4_RETSTATE_MASK;
break;
default:
WARN_ON(1); /* should never happen */
@@ -917,7 +657,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
}
prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
- PM_PWSTCTRL);
+ pwrstctrl_reg_offs);
return 0;
}
@@ -926,27 +666,27 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
* pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
* @pwrdm: struct powerdomain * to get current logic retention power state
*
- * Return the current power state that the logic portion of
- * powerdomain pwrdm will enter
- * Returns -EINVAL if the powerdomain pointer is null or returns the
- * current logic retention power state upon success.
+ * Return the power state that the logic portion of powerdomain @pwrdm
+ * will enter when the powerdomain enters retention. Returns -EINVAL
+ * if the powerdomain pointer is null or returns the logic retention
+ * power state upon success.
*/
int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
if (!pwrdm)
return -EINVAL;
- return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
- OMAP3430_LOGICSTATEST);
+ return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ pwrstst_reg_offs, OMAP3430_LOGICSTATEST);
}
/**
* pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
* @pwrdm: struct powerdomain * to get previous logic power state
*
- * Return the powerdomain pwrdm's logic power state. Returns -EINVAL
- * if the powerdomain pointer is null or returns the previous logic
- * power state upon success.
+ * Return the powerdomain @pwrdm's previous logic power state. Returns
+ * -EINVAL if the powerdomain pointer is null or returns the previous
+ * logic power state upon success.
*/
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
{
@@ -964,12 +704,35 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
}
/**
+ * pwrdm_read_logic_retst - get next powerdomain logic power state
+ * @pwrdm: struct powerdomain * to get next logic power state
+ *
+ * Return the powerdomain pwrdm's logic power state. Returns -EINVAL
+ * if the powerdomain pointer is null or returns the next logic
+ * power state upon success.
+ */
+int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+ if (!pwrdm)
+ return -EINVAL;
+
+ /*
+ * The register bit names below may not correspond to the
+ * actual names of the bits in each powerdomain's register,
+ * but the type of value returned is the same for each
+ * powerdomain.
+ */
+ return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs,
+ OMAP3430_LOGICSTATEST);
+}
+
+/**
* pwrdm_read_mem_pwrst - get current memory bank power state
* @pwrdm: struct powerdomain * to get current memory bank power state
* @bank: memory bank number (0-3)
*
- * Return the powerdomain pwrdm's current memory power state for bank
- * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
+ * Return the powerdomain @pwrdm's current memory power state for bank
+ * @bank. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
* the target memory bank does not exist or is not controllable, or
* returns the current memory power state upon success.
*/
@@ -994,23 +757,27 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
*/
switch (bank) {
case 0:
- m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK;
+ m = OMAP_MEM0_STATEST_MASK;
break;
case 1:
- m = OMAP3430_L1FLATMEMSTATEST_MASK;
+ m = OMAP_MEM1_STATEST_MASK;
break;
case 2:
- m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK;
+ m = OMAP_MEM2_STATEST_MASK;
break;
case 3:
- m = OMAP3430_L2FLATMEMSTATEST_MASK;
+ m = OMAP_MEM3_STATEST_MASK;
+ break;
+ case 4:
+ m = OMAP_MEM4_STATEST_MASK;
break;
default:
WARN_ON(1); /* should never happen */
return -EEXIST;
}
- return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m);
+ return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ pwrstst_reg_offs, m);
}
/**
@@ -1018,10 +785,11 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
* @pwrdm: struct powerdomain * to get previous memory bank power state
* @bank: memory bank number (0-3)
*
- * Return the powerdomain pwrdm's previous memory power state for bank
- * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
- * the target memory bank does not exist or is not controllable, or
- * returns the previous memory power state upon success.
+ * Return the powerdomain @pwrdm's previous memory power state for
+ * bank @bank. Returns -EINVAL if the powerdomain pointer is null,
+ * -EEXIST if the target memory bank does not exist or is not
+ * controllable, or returns the previous memory power state upon
+ * success.
*/
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
{
@@ -1065,13 +833,63 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
}
/**
+ * pwrdm_read_mem_retst - get next memory bank power state
+ * @pwrdm: struct powerdomain * to get mext memory bank power state
+ * @bank: memory bank number (0-3)
+ *
+ * Return the powerdomain pwrdm's next memory power state for bank
+ * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
+ * the target memory bank does not exist or is not controllable, or
+ * returns the next memory power state upon success.
+ */
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+ u32 m;
+
+ if (!pwrdm)
+ return -EINVAL;
+
+ if (pwrdm->banks < (bank + 1))
+ return -EEXIST;
+
+ /*
+ * The register bit names below may not correspond to the
+ * actual names of the bits in each powerdomain's register,
+ * but the type of value returned is the same for each
+ * powerdomain.
+ */
+ switch (bank) {
+ case 0:
+ m = OMAP_MEM0_RETSTATE_MASK;
+ break;
+ case 1:
+ m = OMAP_MEM1_RETSTATE_MASK;
+ break;
+ case 2:
+ m = OMAP_MEM2_RETSTATE_MASK;
+ break;
+ case 3:
+ m = OMAP_MEM3_RETSTATE_MASK;
+ break;
+ case 4:
+ m = OMAP_MEM4_RETSTATE_MASK;
+ default:
+ WARN_ON(1); /* should never happen */
+ return -EEXIST;
+ }
+
+ return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+ pwrstctrl_reg_offs, m);
+}
+
+/**
* pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
* @pwrdm: struct powerdomain * to clear
*
- * Clear the powerdomain's previous power state register. Clears the
- * entire register, including logic and memory bank previous power states.
- * Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon
- * success.
+ * Clear the powerdomain's previous power state register @pwrdm.
+ * Clears the entire register, including logic and memory bank
+ * previous power states. Returns -EINVAL if the powerdomain pointer
+ * is null, or returns 0 upon success.
*/
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{
@@ -1096,11 +914,11 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
* @pwrdm: struct powerdomain *
*
* Enable automatic context save-and-restore upon power state change
- * for some devices in a powerdomain. Warning: this only affects a
- * subset of devices in a powerdomain; check the TRM closely. Returns
- * -EINVAL if the powerdomain pointer is null or if the powerdomain
- * does not support automatic save-and-restore, or returns 0 upon
- * success.
+ * for some devices in the powerdomain @pwrdm. Warning: this only
+ * affects a subset of devices in a powerdomain; check the TRM
+ * closely. Returns -EINVAL if the powerdomain pointer is null or if
+ * the powerdomain does not support automatic save-and-restore, or
+ * returns 0 upon success.
*/
int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
{
@@ -1114,7 +932,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
pwrdm->name);
prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
- pwrdm->prcm_offs, PM_PWSTCTRL);
+ pwrdm->prcm_offs, pwrstctrl_reg_offs);
return 0;
}
@@ -1124,11 +942,11 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
* @pwrdm: struct powerdomain *
*
* Disable automatic context save-and-restore upon power state change
- * for some devices in a powerdomain. Warning: this only affects a
- * subset of devices in a powerdomain; check the TRM closely. Returns
- * -EINVAL if the powerdomain pointer is null or if the powerdomain
- * does not support automatic save-and-restore, or returns 0 upon
- * success.
+ * for some devices in the powerdomain @pwrdm. Warning: this only
+ * affects a subset of devices in a powerdomain; check the TRM
+ * closely. Returns -EINVAL if the powerdomain pointer is null or if
+ * the powerdomain does not support automatic save-and-restore, or
+ * returns 0 upon success.
*/
int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
{
@@ -1142,7 +960,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
pwrdm->name);
prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
- pwrdm->prcm_offs, PM_PWSTCTRL);
+ pwrdm->prcm_offs, pwrstctrl_reg_offs);
return 0;
}
@@ -1151,7 +969,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
* pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
* @pwrdm: struct powerdomain *
*
- * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
+ * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore
* for some devices, or 0 if it does not.
*/
bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
@@ -1163,7 +981,7 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
* pwrdm_wait_transition - wait for powerdomain power transition to finish
* @pwrdm: struct powerdomain * to wait for
*
- * If the powerdomain pwrdm is in the process of a state transition,
+ * If the powerdomain @pwrdm is in the process of a state transition,
* spin until it completes the power transition, or until an iteration
* bailout value is reached. Returns -EINVAL if the powerdomain
* pointer is null, -EAGAIN if the bailout value was reached, or
@@ -1183,10 +1001,10 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
*/
/* XXX Is this udelay() value meaningful? */
- while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) &
+ while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
OMAP_INTRANSITION) &&
(c++ < PWRDM_TRANSITION_BAILOUT))
- udelay(1);
+ udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
printk(KERN_ERR "powerdomain: waited too long for "
@@ -1213,12 +1031,6 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
return -EINVAL;
}
-int pwrdm_clk_state_switch(struct clk *clk)
-{
- if (clk != NULL && clk->clkdm != NULL)
- return pwrdm_clkdm_state_switch(clk->clkdm);
- return -EINVAL;
-}
int pwrdm_pre_transition(void)
{
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 057b2e3e2c3..105cbcaefd3 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -1,8 +1,8 @@
/*
* OMAP2/3 common powerdomain definitions
*
- * Copyright (C) 2007-8 Texas Instruments, Inc.
- * Copyright (C) 2007-8 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
@@ -12,26 +12,21 @@
* published by the Free Software Foundation.
*/
+/*
+ * To Do List
+ * -> Move the Sleep/Wakeup dependencies from Power Domain framework to
+ * Clock Domain Framework
+ */
+
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
/*
* This file contains all of the powerdomains that have some element
- * of software control for the OMAP24xx and OMAP34XX chips.
- *
- * A few notes:
+ * of software control for the OMAP24xx and OMAP34xx chips.
*
* This is not an exhaustive listing of powerdomains on the chips; only
* powerdomains that can be controlled in software.
- *
- * A useful validation rule for struct powerdomain:
- * Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
- * must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really
- * just software-controllable dependencies. Non-software-controllable
- * dependencies do exist, but they are not encoded below (yet).
- *
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
*/
/*
@@ -41,26 +36,17 @@
*
* On the 2420, this is a 'C55 DSP called, simply, the DSP. Its
* powerdomain is called the "DSP power domain." On the 2430, the
- * on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its
- * powerdomain is still called the "DSP power domain." On the 3430,
- * the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
- * its powerdomain is now called the "IVA2 power domain."
+ * on-board DSP is a 'C64 DSP, now called (along with its hardware
+ * accelerators) the IVA2 or IVA2.1. Its powerdomain is still called
+ * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the
+ * 2430, also known as the IVA2; but its powerdomain is now called the
+ * "IVA2 power domain."
*
* The 2420 also has something called the IVA, which is a separate ARM
* core, and has nothing to do with the DSP/IVA2.
*
* Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
* address offset is different between the C55 and C64 DSPs.
- *
- * The overly-specific dep_bit names are due to a bit name collision
- * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
- * value are the same for all powerdomains: 2
- */
-
-/*
- * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
- * sanity check?
- * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
*/
#include <plat/powerdomain.h>
@@ -68,69 +54,23 @@
#include "prcm-common.h"
#include "prm.h"
#include "cm.h"
-
-/* OMAP2/3-common powerdomains and wakeup dependencies */
-
-/*
- * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
- * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
- * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
- */
-static struct pwrdm_dep gfx_sgx_wkdeps[] = {
- {
- .pwrdm_name = "core_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "iva2_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
- CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
- CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-/*
- * 3430: CM_SLEEPDEP_CAM: MPU
- * 3430ES1: CM_SLEEPDEP_GFX: MPU
- * 3430ES2: CM_SLEEPDEP_SGX: MPU
- */
-static struct pwrdm_dep cam_gfx_sleepdeps[] = {
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-
#include "powerdomains24xx.h"
#include "powerdomains34xx.h"
+#include "powerdomains44xx.h"
+/* OMAP2/3-common powerdomains */
-/*
- * OMAP2/3 common powerdomains
- */
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
/*
* The GFX powerdomain is not present on 3430ES2, but currently we do not
* have a macro to filter it out at compile-time.
*/
-static struct powerdomain gfx_pwrdm = {
+static struct powerdomain gfx_omap2_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = GFX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430ES1),
- .wkdep_srcs = gfx_sgx_wkdeps,
- .sleepdep_srcs = cam_gfx_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
@@ -142,22 +82,24 @@ static struct powerdomain gfx_pwrdm = {
},
};
-static struct powerdomain wkup_pwrdm = {
+static struct powerdomain wkup_omap2_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = WKUP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
- .dep_bit = OMAP_EN_WKUP_SHIFT,
};
+#endif
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap[] __initdata = {
- &gfx_pwrdm,
- &wkup_pwrdm,
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ &wkup_omap2_pwrdm,
+ &gfx_omap2_pwrdm,
+#endif
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
&dsp_pwrdm,
&mpu_24xx_pwrdm,
&core_24xx_pwrdm,
@@ -167,12 +109,12 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
&mdm_pwrdm,
#endif
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
&iva2_pwrdm,
- &mpu_34xx_pwrdm,
+ &mpu_3xxx_pwrdm,
&neon_pwrdm,
- &core_34xx_pre_es3_1_pwrdm,
- &core_34xx_es3_1_pwrdm,
+ &core_3xxx_pre_es3_1_pwrdm,
+ &core_3xxx_es3_1_pwrdm,
&cam_pwrdm,
&dss_pwrdm,
&per_pwrdm,
@@ -186,6 +128,24 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
&dpll5_pwrdm,
#endif
+#ifdef CONFIG_ARCH_OMAP4
+ &core_44xx_pwrdm,
+ &gfx_44xx_pwrdm,
+ &abe_44xx_pwrdm,
+ &dss_44xx_pwrdm,
+ &tesla_44xx_pwrdm,
+ &wkup_44xx_pwrdm,
+ &cpu0_44xx_pwrdm,
+ &cpu1_44xx_pwrdm,
+ &emu_44xx_pwrdm,
+ &mpu_44xx_pwrdm,
+ &ivahd_44xx_pwrdm,
+ &cam_44xx_pwrdm,
+ &l3init_44xx_pwrdm,
+ &l4per_44xx_pwrdm,
+ &always_on_core_44xx_pwrdm,
+ &cefuse_44xx_pwrdm,
+#endif
NULL
};
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h
index bd249a495aa..775093add9b 100644
--- a/arch/arm/mach-omap2/powerdomains24xx.h
+++ b/arch/arm/mach-omap2/powerdomains24xx.h
@@ -2,7 +2,7 @@
* OMAP24XX powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
@@ -30,83 +30,7 @@
/* 24XX powerdomains and dependencies */
-#ifdef CONFIG_ARCH_OMAP24XX
-
-
-/* Wakeup dependency source arrays */
-
-/*
- * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP
- * 2430 PM_WKDEP_MDM: same as above
- */
-static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = {
- {
- .pwrdm_name = "core_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- { NULL },
-};
-
-/*
- * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
- * 2430 adds MDM
- */
-static struct pwrdm_dep mpu_24xx_wkdeps[] = {
- {
- .pwrdm_name = "core_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "dsp_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "mdm_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
- },
- { NULL },
-};
-
-/*
- * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
- * 2430 adds MDM
- */
-static struct pwrdm_dep core_24xx_wkdeps[] = {
- {
- .pwrdm_name = "dsp_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "gfx_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
- },
- {
- .pwrdm_name = "mdm_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
- },
- { NULL },
-};
-
+#ifdef CONFIG_ARCH_OMAP2
/* Powerdomains */
@@ -114,8 +38,6 @@ static struct powerdomain dsp_pwrdm = {
.name = "dsp_pwrdm",
.prcm_offs = OMAP24XX_DSP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
- .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
- .wkdep_srcs = dsp_mdm_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
@@ -131,8 +53,6 @@ static struct powerdomain mpu_24xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
- .dep_bit = OMAP24XX_EN_MPU_SHIFT,
- .wkdep_srcs = mpu_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@@ -148,9 +68,7 @@ static struct powerdomain core_24xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
- .wkdep_srcs = core_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
- .dep_bit = OMAP24XX_EN_CORE_SHIFT,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
@@ -164,7 +82,7 @@ static struct powerdomain core_24xx_pwrdm = {
},
};
-#endif /* CONFIG_ARCH_OMAP24XX */
+#endif /* CONFIG_ARCH_OMAP2 */
@@ -176,13 +94,10 @@ static struct powerdomain core_24xx_pwrdm = {
/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
-/* Another case of bit name collisions between several registers: EN_MDM */
static struct powerdomain mdm_pwrdm = {
.name = "mdm_pwrdm",
.prcm_offs = OMAP2430_MDM_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
- .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
- .wkdep_srcs = dsp_mdm_24xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 588f7e07d0e..bd87112beea 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -1,8 +1,8 @@
/*
- * OMAP34XX powerdomain definitions
+ * OMAP3 powerdomain definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2010 Nokia Corporation
*
* Written by Paul Walmsley
* Debugging and integration fixes by Jouni Högander
@@ -32,128 +32,7 @@
* 34XX-specific powerdomains, dependencies
*/
-#ifdef CONFIG_ARCH_OMAP34XX
-
-/*
- * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
- * (USBHOST is ES2 only)
- */
-static struct pwrdm_dep per_usbhost_wkdeps[] = {
- {
- .pwrdm_name = "core_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "iva2_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-/*
- * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
- */
-static struct pwrdm_dep mpu_34xx_wkdeps[] = {
- {
- .pwrdm_name = "core_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "iva2_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "dss_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "per_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-/*
- * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
- */
-static struct pwrdm_dep iva2_wkdeps[] = {
- {
- .pwrdm_name = "core_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "dss_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "per_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-
-/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
-static struct pwrdm_dep cam_dss_wkdeps[] = {
- {
- .pwrdm_name = "iva2_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "wkup_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-/* 3430: PM_WKDEP_NEON: MPU */
-static struct pwrdm_dep neon_wkdeps[] = {
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
-
-/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
-
-/*
- * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
- * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
- */
-static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
- {
- .pwrdm_name = "mpu_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- {
- .pwrdm_name = "iva2_pwrdm",
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
- },
- { NULL },
-};
-
+#ifdef CONFIG_ARCH_OMAP3
/*
* Powerdomains
@@ -163,8 +42,6 @@ static struct powerdomain iva2_pwrdm = {
.name = "iva2_pwrdm",
.prcm_offs = OMAP3430_IVA2_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
- .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
- .wkdep_srcs = iva2_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 4,
@@ -182,12 +59,10 @@ static struct powerdomain iva2_pwrdm = {
},
};
-static struct powerdomain mpu_34xx_pwrdm = {
+static struct powerdomain mpu_3xxx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = MPU_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
- .dep_bit = OMAP3430_EN_MPU_SHIFT,
- .wkdep_srcs = mpu_34xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_MPU_QUIRK,
@@ -200,15 +75,14 @@ static struct powerdomain mpu_34xx_pwrdm = {
},
};
-/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
+static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0),
.pwrsts = PWRSTS_OFF_RET_ON,
- .dep_bit = OMAP3430_EN_CORE_SHIFT,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
@@ -220,13 +94,12 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
},
};
-/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_es3_1_pwrdm = {
+static struct powerdomain core_3xxx_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
.pwrsts = PWRSTS_OFF_RET_ON,
- .dep_bit = OMAP3430_EN_CORE_SHIFT,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
.banks = 2,
.pwrsts_mem_ret = {
@@ -239,14 +112,10 @@ static struct powerdomain core_34xx_es3_1_pwrdm = {
},
};
-/* Another case of bit name collisions between several registers: EN_DSS */
static struct powerdomain dss_pwrdm = {
.name = "dss_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_DSS_MOD,
- .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
- .wkdep_srcs = cam_dss_wkdeps,
- .sleepdep_srcs = dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
@@ -267,8 +136,6 @@ static struct powerdomain sgx_pwrdm = {
.name = "sgx_pwrdm",
.prcm_offs = OMAP3430ES2_SGX_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
- .wkdep_srcs = gfx_sgx_wkdeps,
- .sleepdep_srcs = cam_gfx_sleepdeps,
/* XXX This is accurate for 3430 SGX, but what about GFX? */
.pwrsts = PWRSTS_OFF_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
@@ -285,8 +152,6 @@ static struct powerdomain cam_pwrdm = {
.name = "cam_pwrdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_CAM_MOD,
- .wkdep_srcs = cam_dss_wkdeps,
- .sleepdep_srcs = cam_gfx_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
@@ -302,9 +167,6 @@ static struct powerdomain per_pwrdm = {
.name = "per_pwrdm",
.prcm_offs = OMAP3430_PER_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
- .dep_bit = OMAP3430_EN_PER_SHIFT,
- .wkdep_srcs = per_usbhost_wkdeps,
- .sleepdep_srcs = dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
@@ -326,7 +188,6 @@ static struct powerdomain neon_pwrdm = {
.name = "neon_pwrdm",
.prcm_offs = OMAP3430_NEON_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
- .wkdep_srcs = neon_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
};
@@ -335,8 +196,6 @@ static struct powerdomain usbhost_pwrdm = {
.name = "usbhost_pwrdm",
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
- .wkdep_srcs = per_usbhost_wkdeps,
- .sleepdep_srcs = dss_per_usbhost_sleepdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
/*
@@ -386,7 +245,7 @@ static struct powerdomain dpll5_pwrdm = {
};
-#endif /* CONFIG_ARCH_OMAP34XX */
+#endif /* CONFIG_ARCH_OMAP3 */
#endif
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
new file mode 100644
index 00000000000..c1015147d57
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -0,0 +1,310 @@
+/*
+ * OMAP4 Power domains framework
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
+
+#include <plat/powerdomain.h>
+
+#include "prcm-common.h"
+#include "cm.h"
+#include "cm-regbits-44xx.h"
+#include "prm.h"
+#include "prm-regbits-44xx.h"
+
+#if defined(CONFIG_ARCH_OMAP4)
+
+/* core_44xx_pwrdm: CORE power domain */
+static struct powerdomain core_44xx_pwrdm = {
+ .name = "core_pwrdm",
+ .prcm_offs = OMAP4430_PRM_CORE_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 5,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRDM_POWER_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ducati_unicache */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRDM_POWER_ON, /* core_other_bank */
+ [3] = PWRDM_POWER_ON, /* ducati_l2ram */
+ [4] = PWRDM_POWER_ON, /* ducati_unicache */
+ },
+};
+
+/* gfx_44xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gfx_44xx_pwrdm = {
+ .name = "gfx_pwrdm",
+ .prcm_offs = OMAP4430_PRM_GFX_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* gfx_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* gfx_mem */
+ },
+};
+
+/* abe_44xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_44xx_pwrdm = {
+ .name = "abe_pwrdm",
+ .prcm_offs = OMAP4430_PRM_ABE_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRDM_POWER_OFF,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_RET, /* aessmem */
+ [1] = PWRDM_POWER_OFF, /* periphmem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* aessmem */
+ [1] = PWRDM_POWER_ON, /* periphmem */
+ },
+};
+
+/* dss_44xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_44xx_pwrdm = {
+ .name = "dss_pwrdm",
+ .prcm_offs = OMAP4430_PRM_DSS_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* dss_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* dss_mem */
+ },
+};
+
+/* tesla_44xx_pwrdm: Tesla processor power domain */
+static struct powerdomain tesla_44xx_pwrdm = {
+ .name = "tesla_pwrdm",
+ .prcm_offs = OMAP4430_PRM_TESLA_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_RET, /* tesla_edma */
+ [1] = PWRSTS_OFF_RET, /* tesla_l1 */
+ [2] = PWRSTS_OFF_RET, /* tesla_l2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* tesla_edma */
+ [1] = PWRDM_POWER_ON, /* tesla_l1 */
+ [2] = PWRDM_POWER_ON, /* tesla_l2 */
+ },
+};
+
+/* wkup_44xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkup_44xx_pwrdm = {
+ .name = "wkup_pwrdm",
+ .prcm_offs = OMAP4430_PRM_WKUP_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRDM_POWER_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* wkup_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* wkup_bank */
+ },
+};
+
+/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_44xx_pwrdm = {
+ .name = "cpu0_pwrdm",
+ .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* cpu0_l1 */
+ },
+};
+
+/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_44xx_pwrdm = {
+ .name = "cpu1_pwrdm",
+ .prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* cpu1_l1 */
+ },
+};
+
+/* emu_44xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_44xx_pwrdm = {
+ .name = "emu_pwrdm",
+ .prcm_offs = OMAP4430_PRM_EMU_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* emu_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* emu_bank */
+ },
+};
+
+/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_44xx_pwrdm = {
+ .name = "mpu_pwrdm",
+ .prcm_offs = OMAP4430_PRM_MPU_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l1 */
+ [1] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [2] = PWRDM_POWER_RET, /* mpu_ram */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* mpu_l1 */
+ [1] = PWRDM_POWER_ON, /* mpu_l2 */
+ [2] = PWRDM_POWER_ON, /* mpu_ram */
+ },
+};
+
+/* ivahd_44xx_pwrdm: IVA-HD power domain */
+static struct powerdomain ivahd_44xx_pwrdm = {
+ .name = "ivahd_pwrdm",
+ .prcm_offs = OMAP4430_PRM_IVAHD_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRDM_POWER_OFF,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* hwa_mem */
+ [1] = PWRDM_POWER_ON, /* sl2_mem */
+ [2] = PWRDM_POWER_ON, /* tcm1_mem */
+ [3] = PWRDM_POWER_ON, /* tcm2_mem */
+ },
+};
+
+/* cam_44xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_44xx_pwrdm = {
+ .name = "cam_pwrdm",
+ .prcm_offs = OMAP4430_PRM_CAM_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* cam_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* cam_mem */
+ },
+};
+
+/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
+static struct powerdomain l3init_44xx_pwrdm = {
+ .name = "l3init_pwrdm",
+ .prcm_offs = OMAP4430_PRM_L3INIT_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* l3init_bank1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* l3init_bank1 */
+ },
+};
+
+/* l4per_44xx_pwrdm: Target peripherals power domain */
+static struct powerdomain l4per_44xx_pwrdm = {
+ .name = "l4per_pwrdm",
+ .prcm_offs = OMAP4430_PRM_L4PER_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* nonretained_bank */
+ [1] = PWRDM_POWER_RET, /* retained_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRDM_POWER_ON, /* nonretained_bank */
+ [1] = PWRDM_POWER_ON, /* retained_bank */
+ },
+};
+
+/*
+ * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
+ * domain
+ */
+static struct powerdomain always_on_core_44xx_pwrdm = {
+ .name = "always_on_core_pwrdm",
+ .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRDM_POWER_ON,
+};
+
+/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain cefuse_44xx_pwrdm = {
+ .name = "cefuse_pwrdm",
+ .prcm_offs = OMAP4430_PRM_CEFUSE_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * always_on_iva
+ * always_on_mpu
+ * stdefuse
+ */
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 61ac2a418bd..90f603d434c 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -119,6 +119,15 @@
#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400
#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800
+/* Base Addresses for the OMAP4 */
+
+#define OMAP4430_CM1_BASE 0x4a004000
+#define OMAP4430_CM2_BASE 0x4a008000
+#define OMAP4430_PRM_BASE 0x4a306000
+#define OMAP4430_SCRM_BASE 0x4a30a000
+#define OMAP4430_CHIRONSS_BASE 0x48243000
+
+
/* 24XX register bits shared between CM & PRM registers */
/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 3ea8177ffb2..07a60f1204c 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -11,6 +11,7 @@
* Rajendra Nayak <rnayak@ti.com>
*
* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
+ * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -28,6 +29,7 @@
#include <plat/control.h>
#include "clock.h"
+#include "clock2xxx.h"
#include "cm.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
@@ -44,7 +46,6 @@ struct omap3_prcm_regs {
u32 iva2_cm_clksel2;
u32 cm_sysconfig;
u32 sgx_cm_clksel;
- u32 wkup_cm_clksel;
u32 dss_cm_clksel;
u32 cam_cm_clksel;
u32 per_cm_clksel;
@@ -53,7 +54,6 @@ struct omap3_prcm_regs {
u32 pll_cm_autoidle2;
u32 pll_cm_clksel4;
u32 pll_cm_clksel5;
- u32 pll_cm_clken;
u32 pll_cm_clken2;
u32 cm_polctrl;
u32 iva2_cm_fclken;
@@ -77,7 +77,6 @@ struct omap3_prcm_regs {
u32 usbhost_cm_iclken;
u32 iva2_cm_autiidle2;
u32 mpu_cm_autoidle2;
- u32 pll_cm_autoidle;
u32 iva2_cm_clkstctrl;
u32 mpu_cm_clkstctrl;
u32 core_cm_clkstctrl;
@@ -124,33 +123,46 @@ struct omap3_prcm_regs prcm_context;
u32 omap_prcm_get_reset_sources(void)
{
/* XXX This presumably needs modification for 34XX */
- return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+ if (cpu_is_omap44xx())
+ return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
+
+ return 0;
}
EXPORT_SYMBOL(omap_prcm_get_reset_sources);
/* Resets clock rates and reboots the system. Only called from system.h */
-void omap_prcm_arch_reset(char mode)
+void omap_prcm_arch_reset(char mode, const char *cmd)
{
- s16 prcm_offs;
- omap2_clk_prepare_for_reboot();
+ s16 prcm_offs = 0;
+
+ if (cpu_is_omap24xx()) {
+ omap2xxx_clk_prepare_for_reboot();
- if (cpu_is_omap24xx())
prcm_offs = WKUP_MOD;
- else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx()) {
u32 l;
prcm_offs = OMAP3430_GR_MOD;
- l = ('B' << 24) | ('M' << 16) | mode;
+ l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0);
/* Reserve the first word in scratchpad for communicating
* with the boot ROM. A pointer to a data structure
* describing the boot process can be stored there,
* cf. OMAP34xx TRM, Initialization / Software Booting
* Configuration. */
omap_writel(l, OMAP343X_SCRATCHPAD + 4);
- } else
+ } else if (cpu_is_omap44xx())
+ prcm_offs = OMAP4430_PRM_DEVICE_MOD;
+ else
WARN_ON(1);
- prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+ OMAP2_RM_RSTCTRL);
+ if (cpu_is_omap44xx())
+ prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+ OMAP4_RM_RSTCTRL);
}
static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
@@ -191,6 +203,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
return v;
}
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+ u32 v;
+
+ v = prm_read_mod_reg(domain, idx);
+ v &= mask;
+ v >>= __ffs(mask);
+
+ return v;
+}
+
/* Read a register in a CM module */
u32 cm_read_mod_reg(s16 module, u16 idx)
{
@@ -220,26 +244,22 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
* @reg: physical address of module IDLEST register
* @mask: value to mask against to determine if the module is active
+ * @idlest: idle state indicator (0 or 1) for the clock
* @name: name of the clock (for printk)
*
* Returns 1 if the module indicated readiness in time, or 0 if it
* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
*/
-int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+ const char *name)
{
int i = 0;
int ena = 0;
- /*
- * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
- * 34xx reverses this, just to keep us on our toes
- */
- if (cpu_is_omap24xx())
- ena = mask;
- else if (cpu_is_omap34xx())
+ if (idlest)
ena = 0;
else
- BUG();
+ ena = mask;
/* Wait for lock */
omap_test_timeout(((__raw_readl(reg) & mask) == ena),
@@ -257,9 +277,19 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
{
- prm_base = omap2_globals->prm;
- cm_base = omap2_globals->cm;
- cm2_base = omap2_globals->cm2;
+ /* Static mapping, never released */
+ if (omap2_globals->prm) {
+ prm_base = ioremap(omap2_globals->prm, SZ_8K);
+ WARN_ON(!prm_base);
+ }
+ if (omap2_globals->cm) {
+ cm_base = ioremap(omap2_globals->cm, SZ_8K);
+ WARN_ON(!cm_base);
+ }
+ if (omap2_globals->cm2) {
+ cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
+ WARN_ON(!cm2_base);
+ }
}
#ifdef CONFIG_ARCH_OMAP3
@@ -274,7 +304,6 @@ void omap3_prcm_save_context(void)
prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
prcm_context.sgx_cm_clksel =
cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
- prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
prcm_context.dss_cm_clksel =
cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
prcm_context.cam_cm_clksel =
@@ -284,15 +313,13 @@ void omap3_prcm_save_context(void)
prcm_context.emu_cm_clksel =
cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
prcm_context.emu_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.pll_cm_autoidle2 =
cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
prcm_context.pll_cm_clksel4 =
cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
prcm_context.pll_cm_clksel5 =
cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
- prcm_context.pll_cm_clken =
- cm_read_mod_reg(PLL_MOD, CM_CLKEN);
prcm_context.pll_cm_clken2 =
cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
@@ -338,26 +365,26 @@ void omap3_prcm_save_context(void)
cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
prcm_context.mpu_cm_autoidle2 =
cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
- prcm_context.pll_cm_autoidle =
- cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
prcm_context.iva2_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.mpu_cm_clkstctrl =
- cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.core_cm_clkstctrl =
- cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.sgx_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+ OMAP2_CM_CLKSTCTRL);
prcm_context.dss_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.cam_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.per_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.neon_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
prcm_context.usbhost_cm_clkstctrl =
- cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
+ cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ OMAP2_CM_CLKSTCTRL);
prcm_context.core_cm_autoidle1 =
cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
prcm_context.core_cm_autoidle2 =
@@ -431,7 +458,6 @@ void omap3_prcm_restore_context(void)
__raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
CM_CLKSEL);
- cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
CM_CLKSEL);
cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
@@ -441,14 +467,13 @@ void omap3_prcm_restore_context(void)
cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
CM_CLKSEL1);
cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
CM_AUTOIDLE2);
cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
OMAP3430ES2_CM_CLKSEL4);
cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
OMAP3430ES2_CM_CLKSEL5);
- cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
OMAP3430ES2_CM_CLKEN2);
__raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
@@ -487,24 +512,24 @@ void omap3_prcm_restore_context(void)
cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
CM_AUTOIDLE2);
cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
- cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
- CM_CLKSTCTRL);
- cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
+ cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
- CM_CLKSTCTRL);
+ OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
- OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
+ OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
CM_AUTOIDLE1);
cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 301c810fb26..597be4a2b9f 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -29,412 +29,412 @@
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT (1 << 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1
#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT (1 << 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2
#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_ABB_IVA_DONE_EN_SHIFT (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31
#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_ABB_IVA_DONE_ST_SHIFT (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31
#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_ABB_MPU_DONE_EN_SHIFT (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7
#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_ABB_MPU_DONE_ST_SHIFT (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7
#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_ACTIVE_FBB_SEL_SHIFT (1 << 2)
+#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2
#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_ACTIVE_RBB_SEL_SHIFT (1 << 1)
+#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1
#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1)
/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_AESSMEM_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16
#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_AESSMEM_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8
#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_ABE_PWRSTST */
-#define OMAP4430_AESSMEM_STATEST_SHIFT (1 << 4)
+#define OMAP4430_AESSMEM_STATEST_SHIFT 4
#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_AIPOFF_SHIFT (1 << 8)
+#define OMAP4430_AIPOFF_SHIFT 8
#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT (1 << 0)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0
#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT (1 << 4)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4
#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT (1 << 2)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2
#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3)
/* Used by PM_CAM_PWRSTCTRL */
-#define OMAP4430_CAM_MEM_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16
#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_CAM_PWRSTST */
-#define OMAP4430_CAM_MEM_STATEST_SHIFT (1 << 4)
+#define OMAP4430_CAM_MEM_STATEST_SHIFT 4
#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5)
/* Used by PRM_CLKREQCTRL */
-#define OMAP4430_CLKREQ_COND_SHIFT (1 << 0)
+#define OMAP4430_CLKREQ_COND_SHIFT 0
#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2)
/* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT (1 << 0)
+#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0
#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7)
/* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT (1 << 8)
+#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8
#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15)
/* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT (1 << 16)
+#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16
#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_CORE_L_SHIFT (1 << 4)
+#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_IVA_L_SHIFT (1 << 12)
+#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_MPU_L_SHIFT (1 << 17)
+#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT (1 << 18)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT (1 << 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9)
/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT (1 << 6)
+#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT (1 << 4)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5)
/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_DATA_SHIFT (1 << 16)
+#define OMAP4430_DATA_SHIFT 16
#define OMAP4430_DATA_MASK BITFIELD(16, 23)
/* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT (1 << 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0)
/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_DFILTEREN_SHIFT (1 << 6)
+#define OMAP4430_DFILTEREN_SHIFT 6
#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6)
/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
-#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4)
/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0)
/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6)
/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
-#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2)
/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1)
/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7)
/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5
#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5)
/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5
#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5)
/* Used by PM_DSS_PWRSTCTRL */
-#define OMAP4430_DSS_MEM_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_DSS_PWRSTCTRL */
-#define OMAP4430_DSS_MEM_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_DSS_PWRSTST */
-#define OMAP4430_DSS_MEM_STATEST_SHIFT (1 << 4)
+#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT (1 << 20)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT (1 << 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10)
/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT (1 << 8)
+#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT (1 << 22)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT (1 << 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11)
/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT (1 << 10)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11)
/* Used by RM_MPU_RSTST */
-#define OMAP4430_EMULATION_RST_SHIFT (1 << 0)
+#define OMAP4430_EMULATION_RST_SHIFT 0
#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0)
/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_EMULATION_RST1ST_SHIFT (1 << 3)
+#define OMAP4430_EMULATION_RST1ST_SHIFT 3
#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3)
/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_EMULATION_RST2ST_SHIFT (1 << 4)
+#define OMAP4430_EMULATION_RST2ST_SHIFT 4
#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4)
/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT (1 << 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3)
/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT (1 << 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4)
/* Used by PM_EMU_PWRSTCTRL */
-#define OMAP4430_EMU_BANK_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_EMU_PWRSTST */
-#define OMAP4430_EMU_BANK_STATEST_SHIFT (1 << 4)
+#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
*/
-#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT (1 << 0)
+#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0
#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_ENFUNC1_SHIFT (1 << 3)
+#define OMAP4430_ENFUNC1_SHIFT 3
#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_ENFUNC3_SHIFT (1 << 5)
+#define OMAP4430_ENFUNC3_SHIFT 5
#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_ENFUNC4_SHIFT (1 << 6)
+#define OMAP4430_ENFUNC4_SHIFT 6
#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
-#define OMAP4430_ENFUNC5_SHIFT (1 << 7)
+#define OMAP4430_ENFUNC5_SHIFT 7
#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_ERRORGAIN_SHIFT (1 << 16)
+#define OMAP4430_ERRORGAIN_SHIFT 16
#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_ERROROFFSET_SHIFT (1 << 24)
+#define OMAP4430_ERROROFFSET_SHIFT 24
#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31)
/* Used by PRM_RSTST */
-#define OMAP4430_EXTERNAL_WARM_RST_SHIFT (1 << 5)
+#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_FORCEUPDATE_SHIFT (1 << 1)
+#define OMAP4430_FORCEUPDATE_SHIFT 1
#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1)
/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP4430_FORCEUPDATEWAIT_SHIFT (1 << 8)
+#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8
#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
-#define OMAP4430_FORCEWKUP_EN_SHIFT (1 << 10)
+#define OMAP4430_FORCEWKUP_EN_SHIFT 10
#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_FORCEWKUP_ST_SHIFT (1 << 10)
+#define OMAP4430_FORCEWKUP_ST_SHIFT 10
#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10)
/* Used by PM_GFX_PWRSTCTRL */
-#define OMAP4430_GFX_MEM_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16
#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_GFX_PWRSTST */
-#define OMAP4430_GFX_MEM_STATEST_SHIFT (1 << 4)
+#define OMAP4430_GFX_MEM_STATEST_SHIFT 4
#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5)
/* Used by PRM_RSTST */
-#define OMAP4430_GLOBAL_COLD_RST_SHIFT (1 << 0)
+#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0)
/* Used by PRM_RSTST */
-#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT (1 << 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_GLOBAL_WUEN_SHIFT (1 << 16)
+#define OMAP4430_GLOBAL_WUEN_SHIFT 16
#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16)
/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_HSMCODE_SHIFT (1 << 0)
+#define OMAP4430_HSMCODE_SHIFT 0
#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2)
/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_HSMODEEN_SHIFT (1 << 3)
+#define OMAP4430_HSMODEEN_SHIFT 3
#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3)
/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_HSSCLH_SHIFT (1 << 16)
+#define OMAP4430_HSSCLH_SHIFT 16
#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23)
/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_HSSCLL_SHIFT (1 << 24)
+#define OMAP4430_HSSCLL_SHIFT 24
#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_HWA_MEM_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16
#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_HWA_MEM_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8
#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_HWA_MEM_STATEST_SHIFT (1 << 4)
+#define OMAP4430_HWA_MEM_STATEST_SHIFT 4
#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5)
/* Used by RM_MPU_RSTST */
-#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT (1 << 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1
#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1)
/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_ICECRUSHER_RST1ST_SHIFT (1 << 5)
+#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5
#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5)
/* Used by RM_DUCATI_RSTST */
-#define OMAP4430_ICECRUSHER_RST2ST_SHIFT (1 << 6)
+#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6
#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6)
/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT (1 << 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5
#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5)
/* Used by RM_IVAHD_RSTST */
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT (1 << 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6
#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6)
/* Used by PRM_RSTST */
-#define OMAP4430_ICEPICK_RST_SHIFT (1 << 9)
+#define OMAP4430_ICEPICK_RST_SHIFT 9
#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_INITVDD_SHIFT (1 << 2)
+#define OMAP4430_INITVDD_SHIFT 2
#define OMAP4430_INITVDD_MASK BITFIELD(2, 2)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_INITVOLTAGE_SHIFT (1 << 8)
+#define OMAP4430_INITVOLTAGE_SHIFT 8
#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15)
/*
@@ -442,47 +442,47 @@
* PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
* PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
*/
-#define OMAP4430_INTRANSITION_SHIFT (1 << 20)
+#define OMAP4430_INTRANSITION_SHIFT 20
#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_IO_EN_SHIFT (1 << 9)
+#define OMAP4430_IO_EN_SHIFT 9
#define OMAP4430_IO_EN_MASK BITFIELD(9, 9)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_IO_ON_STATUS_SHIFT (1 << 5)
+#define OMAP4430_IO_ON_STATUS_SHIFT 5
#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_IO_ST_SHIFT (1 << 9)
+#define OMAP4430_IO_ST_SHIFT 9
#define OMAP4430_IO_ST_MASK BITFIELD(9, 9)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOCLK_OVERRIDE_SHIFT (1 << 0)
+#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0
#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOCLK_STATUS_SHIFT (1 << 1)
+#define OMAP4430_ISOCLK_STATUS_SHIFT 1
#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOOVR_EXTEND_SHIFT (1 << 4)
+#define OMAP4430_ISOOVR_EXTEND_SHIFT 4
#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4)
/* Used by PRM_IO_COUNT */
-#define OMAP4430_ISO_2_ON_TIME_SHIFT (1 << 0)
+#define OMAP4430_ISO_2_ON_TIME_SHIFT 0
#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7)
/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16
#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8
#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_L3INIT_PWRSTST */
-#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT (1 << 4)
+#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4
#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5)
/*
@@ -490,7 +490,7 @@
* PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
* PM_IVAHD_PWRSTCTRL
*/
-#define OMAP4430_LOGICRETSTATE_SHIFT (1 << 2)
+#define OMAP4430_LOGICRETSTATE_SHIFT 2
#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2)
/*
@@ -498,7 +498,7 @@
* PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
* PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
*/
-#define OMAP4430_LOGICSTATEST_SHIFT (1 << 2)
+#define OMAP4430_LOGICSTATEST_SHIFT 2
#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2)
/*
@@ -537,7 +537,7 @@
* RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
* RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
*/
-#define OMAP4430_LOSTCONTEXT_DFF_SHIFT (1 << 0)
+#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0
#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0)
/*
@@ -558,58 +558,58 @@
* RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
* RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
*/
-#define OMAP4430_LOSTCONTEXT_RFF_SHIFT (1 << 1)
+#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1
#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1)
/* Used by RM_ABE_AESS_CONTEXT */
-#define OMAP4430_LOSTMEM_AESSMEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8
#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8)
/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
-#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8)
/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8)
/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT (1 << 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9
#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9)
/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8
#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8)
/*
* Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
* RM_SDMA_SDMA_CONTEXT
*/
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8)
/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
-#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8)
/* Used by RM_DUCATI_DUCATI_CONTEXT */
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT (1 << 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9
#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9)
/* Used by RM_DUCATI_DUCATI_CONTEXT */
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8
#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8)
/* Used by RM_EMU_DEBUGSS_CONTEXT */
-#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8)
/* Used by RM_GFX_GFX_CONTEXT */
-#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8)
/* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT (1 << 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10
#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10)
/*
@@ -619,19 +619,19 @@
* RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
* RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
*/
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8
#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8)
/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_L1_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8
#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8)
/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_L2_SHIFT (1 << 9)
+#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9
#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9)
/* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT (1 << 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10
#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10)
/*
@@ -639,14 +639,14 @@
* RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
* RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
*/
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8)
/*
* Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
* RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
*/
-#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8
#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8)
/*
@@ -654,35 +654,35 @@
* RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
* RM_L4SEC_CRYPTODMA_CONTEXT
*/
-#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8)
/* Used by RM_IVAHD_SL2_CONTEXT */
-#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8)
/* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8)
/* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT (1 << 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9
#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9)
/* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT (1 << 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10
#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10)
/* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8
#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8)
/* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT (1 << 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9
#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9)
/* Used by RM_WKUP_SARRAM_CONTEXT */
-#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT (1 << 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8)
/*
@@ -690,164 +690,164 @@
* PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
* PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
*/
-#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT (1 << 4)
+#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_MEMORYCHANGE_SHIFT (1 << 3)
+#define OMAP4430_MEMORYCHANGE_SHIFT 3
#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3)
/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_READY_SHIFT (1 << 1)
+#define OMAP4430_MODEM_READY_SHIFT 1
#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1)
/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT (1 << 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9)
/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_SLEEP_ST_SHIFT (1 << 16)
+#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16)
/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_WAKE_IRQ_SHIFT (1 << 8)
+#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8)
/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L1_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L1_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_L1_STATEST_SHIFT (1 << 4)
+#define OMAP4430_MPU_L1_STATEST_SHIFT 4
#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5)
/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L2_ONSTATE_SHIFT (1 << 18)
+#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19)
/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L2_RETSTATE_SHIFT (1 << 9)
+#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9)
/* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_L2_STATEST_SHIFT (1 << 6)
+#define OMAP4430_MPU_L2_STATEST_SHIFT 6
#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7)
/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_RAM_ONSTATE_SHIFT (1 << 20)
+#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21)
/* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_RAM_RETSTATE_SHIFT (1 << 10)
+#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10)
/* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_RAM_STATEST_SHIFT (1 << 8)
+#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9)
/* Used by PRM_RSTST */
-#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT (1 << 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2)
/* Used by PRM_RSTST */
-#define OMAP4430_MPU_WDT_RST_SHIFT (1 << 3)
+#define OMAP4430_MPU_WDT_RST_SHIFT 3
#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT (1 << 18)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19)
/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT (1 << 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9)
/* Used by PM_L4PER_PWRSTST */
-#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT (1 << 6)
+#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT (1 << 24)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25)
/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12)
/* Used by PM_CORE_PWRSTST */
-#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12
#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
-#define OMAP4430_OFF_SHIFT (1 << 0)
+#define OMAP4430_OFF_SHIFT 0
#define OMAP4430_OFF_MASK BITFIELD(0, 7)
/* Used by PRM_LDO_BANDGAP_CTRL */
-#define OMAP4430_OFF_ENABLE_SHIFT (1 << 0)
+#define OMAP4430_OFF_ENABLE_SHIFT 0
#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
-#define OMAP4430_ON_SHIFT (1 << 24)
+#define OMAP4430_ON_SHIFT 24
#define OMAP4430_ON_MASK BITFIELD(24, 31)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
-#define OMAP4430_ONLP_SHIFT (1 << 16)
+#define OMAP4430_ONLP_SHIFT 16
#define OMAP4430_ONLP_MASK BITFIELD(16, 23)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_OPP_CHANGE_SHIFT (1 << 2)
+#define OMAP4430_OPP_CHANGE_SHIFT 2
#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_OPP_SEL_SHIFT (1 << 0)
+#define OMAP4430_OPP_SEL_SHIFT 0
#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1)
/* Used by PRM_SRAM_COUNT */
-#define OMAP4430_PCHARGECNT_VALUE_SHIFT (1 << 0)
+#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0
#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5)
/* Used by PRM_PSCON_COUNT */
-#define OMAP4430_PCHARGE_TIME_SHIFT (1 << 0)
+#define OMAP4430_PCHARGE_TIME_SHIFT 0
#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7)
/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT (1 << 20)
+#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20
#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21)
/* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT (1 << 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10
#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10)
/* Used by PM_ABE_PWRSTST */
-#define OMAP4430_PERIPHMEM_STATEST_SHIFT (1 << 8)
+#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8
#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9)
/* Used by PRM_PHASE1_CNDP */
-#define OMAP4430_PHASE1_CNDP_SHIFT (1 << 0)
+#define OMAP4430_PHASE1_CNDP_SHIFT 0
#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31)
/* Used by PRM_PHASE2A_CNDP */
-#define OMAP4430_PHASE2A_CNDP_SHIFT (1 << 0)
+#define OMAP4430_PHASE2A_CNDP_SHIFT 0
#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31)
/* Used by PRM_PHASE2B_CNDP */
-#define OMAP4430_PHASE2B_CNDP_SHIFT (1 << 0)
+#define OMAP4430_PHASE2B_CNDP_SHIFT 0
#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31)
/* Used by PRM_PSCON_COUNT */
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT (1 << 8)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8
#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15)
/*
@@ -856,7 +856,7 @@
* PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
* PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
*/
-#define OMAP4430_POWERSTATE_SHIFT (1 << 0)
+#define OMAP4430_POWERSTATE_SHIFT 0
#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1)
/*
@@ -864,35 +864,35 @@
* PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
* PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
*/
-#define OMAP4430_POWERSTATEST_SHIFT (1 << 0)
+#define OMAP4430_POWERSTATEST_SHIFT 0
#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1)
/* Used by PRM_PWRREQCTRL */
-#define OMAP4430_PWRREQ_COND_SHIFT (1 << 0)
+#define OMAP4430_PWRREQ_COND_SHIFT 0
#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_CORE_L_SHIFT (1 << 3)
+#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3
#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_IVA_L_SHIFT (1 << 11)
+#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11
#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_MPU_L_SHIFT (1 << 20)
+#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20
#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_CORE_L_SHIFT (1 << 2)
+#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2
#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_IVA_L_SHIFT (1 << 10)
+#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10
#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_MPU_L_SHIFT (1 << 19)
+#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19
#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19)
/*
@@ -900,7 +900,7 @@
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
-#define OMAP4430_RAMP_DOWN_COUNT_SHIFT (1 << 16)
+#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21)
/*
@@ -908,7 +908,7 @@
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
-#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT (1 << 24)
+#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24
#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25)
/*
@@ -916,7 +916,7 @@
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
-#define OMAP4430_RAMP_UP_COUNT_SHIFT (1 << 0)
+#define OMAP4430_RAMP_UP_COUNT_SHIFT 0
#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5)
/*
@@ -924,1282 +924,1282 @@
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
-#define OMAP4430_RAMP_UP_PRESCAL_SHIFT (1 << 8)
+#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_CORE_L_SHIFT (1 << 1)
+#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1
#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_IVA_L_SHIFT (1 << 9)
+#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9
#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_MPU_L_SHIFT (1 << 18)
+#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18
#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18)
/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_REGADDR_SHIFT (1 << 8)
+#define OMAP4430_REGADDR_SHIFT 8
#define OMAP4430_REGADDR_MASK BITFIELD(8, 15)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
-#define OMAP4430_RET_SHIFT (1 << 8)
+#define OMAP4430_RET_SHIFT 8
#define OMAP4430_RET_MASK BITFIELD(8, 15)
/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16
#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8
#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_L4PER_PWRSTST */
-#define OMAP4430_RETAINED_BANK_STATEST_SHIFT (1 << 4)
+#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4
#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5)
/*
* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
* PRM_LDO_SRAM_MPU_CTRL
*/
-#define OMAP4430_RETMODE_ENABLE_SHIFT (1 << 0)
+#define OMAP4430_RETMODE_ENABLE_SHIFT 0
#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0)
/* Used by REVISION_PRM */
-#define OMAP4430_REV_SHIFT (1 << 0)
+#define OMAP4430_REV_SHIFT 0
#define OMAP4430_REV_MASK BITFIELD(0, 7)
/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST1_SHIFT (1 << 0)
+#define OMAP4430_RST1_SHIFT 0
#define OMAP4430_RST1_MASK BITFIELD(0, 0)
/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST1ST_SHIFT (1 << 0)
+#define OMAP4430_RST1ST_SHIFT 0
#define OMAP4430_RST1ST_MASK BITFIELD(0, 0)
/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST2_SHIFT (1 << 1)
+#define OMAP4430_RST2_SHIFT 1
#define OMAP4430_RST2_MASK BITFIELD(1, 1)
/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST2ST_SHIFT (1 << 1)
+#define OMAP4430_RST2ST_SHIFT 1
#define OMAP4430_RST2ST_MASK BITFIELD(1, 1)
/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST3_SHIFT (1 << 2)
+#define OMAP4430_RST3_SHIFT 2
#define OMAP4430_RST3_MASK BITFIELD(2, 2)
/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST3ST_SHIFT (1 << 2)
+#define OMAP4430_RST3ST_SHIFT 2
#define OMAP4430_RST3ST_MASK BITFIELD(2, 2)
/* Used by PRM_RSTTIME */
-#define OMAP4430_RSTTIME1_SHIFT (1 << 0)
+#define OMAP4430_RSTTIME1_SHIFT 0
#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9)
/* Used by PRM_RSTTIME */
-#define OMAP4430_RSTTIME2_SHIFT (1 << 10)
+#define OMAP4430_RSTTIME2_SHIFT 10
#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14)
/* Used by PRM_RSTCTRL */
-#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT (1 << 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1
#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1)
/* Used by PRM_RSTCTRL */
-#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT (1 << 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0
#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_SA_VDD_CORE_L_SHIFT (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_SHIFT 0
#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0)
/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0
#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_SA_VDD_IVA_L_SHIFT (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_SHIFT 8
#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8)
/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8
#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14)
/* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_SA_VDD_MPU_L_SHIFT (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_SHIFT 16
#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16)
/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16
#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22)
/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_SCLH_SHIFT (1 << 0)
+#define OMAP4430_SCLH_SHIFT 0
#define OMAP4430_SCLH_MASK BITFIELD(0, 7)
/* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_SCLL_SHIFT (1 << 8)
+#define OMAP4430_SCLL_SHIFT 8
#define OMAP4430_SCLL_MASK BITFIELD(8, 15)
/* Used by PRM_RSTST */
-#define OMAP4430_SECURE_WDT_RST_SHIFT (1 << 4)
+#define OMAP4430_SECURE_WDT_RST_SHIFT 4
#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_SL2_MEM_ONSTATE_SHIFT (1 << 18)
+#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18
#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_SL2_MEM_RETSTATE_SHIFT (1 << 9)
+#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9
#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9)
/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_SL2_MEM_STATEST_SHIFT (1 << 6)
+#define OMAP4430_SL2_MEM_STATEST_SHIFT 6
#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7)
/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_SLAVEADDR_SHIFT (1 << 0)
+#define OMAP4430_SLAVEADDR_SHIFT 0
#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SLEEP_RBB_SEL_SHIFT (1 << 3)
+#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3
#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3)
/* Used by PRM_SRAM_COUNT */
-#define OMAP4430_SLPCNT_VALUE_SHIFT (1 << 16)
+#define OMAP4430_SLPCNT_VALUE_SHIFT 16
#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23)
/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
-#define OMAP4430_SMPSWAITTIMEMAX_SHIFT (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23)
/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
-#define OMAP4430_SMPSWAITTIMEMIN_SHIFT (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SR2EN_SHIFT (1 << 0)
+#define OMAP4430_SR2EN_SHIFT 0
#define OMAP4430_SR2EN_MASK BITFIELD(0, 0)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_SR2_IN_TRANSITION_SHIFT (1 << 6)
+#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6
#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_SR2_STATUS_SHIFT (1 << 3)
+#define OMAP4430_SR2_STATUS_SHIFT 3
#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SR2_WTCNT_VALUE_SHIFT (1 << 8)
+#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8
#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15)
/*
* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
* PRM_LDO_SRAM_MPU_CTRL
*/
-#define OMAP4430_SRAMLDO_STATUS_SHIFT (1 << 8)
+#define OMAP4430_SRAMLDO_STATUS_SHIFT 8
#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8)
/*
* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
* PRM_LDO_SRAM_MPU_CTRL
*/
-#define OMAP4430_SRAM_IN_TRANSITION_SHIFT (1 << 9)
+#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9
#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9)
/* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_SRMODEEN_SHIFT (1 << 4)
+#define OMAP4430_SRMODEEN_SHIFT 4
#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4)
/* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP4430_STABLE_COUNT_SHIFT (1 << 0)
+#define OMAP4430_STABLE_COUNT_SHIFT 0
#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5)
/* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP4430_STABLE_PRESCAL_SHIFT (1 << 8)
+#define OMAP4430_STABLE_PRESCAL_SHIFT 8
#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT (1 << 20)
+#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20
#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT (1 << 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10
#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10)
/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_TCM1_MEM_STATEST_SHIFT (1 << 8)
+#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8
#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT (1 << 22)
+#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22
#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23)
/* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT (1 << 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11
#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11)
/* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_TCM2_MEM_STATEST_SHIFT (1 << 10)
+#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10
#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11)
/* Used by RM_TESLA_RSTST */
-#define OMAP4430_TESLASS_EMU_RSTST_SHIFT (1 << 2)
+#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2
#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2)
/* Used by RM_TESLA_RSTST */
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT (1 << 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3
#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3)
/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT (1 << 20)
+#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20
#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21)
/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT (1 << 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10
#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10)
/* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_EDMA_STATEST_SHIFT (1 << 8)
+#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8
#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9)
/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L1_ONSTATE_SHIFT (1 << 16)
+#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16
#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17)
/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L1_RETSTATE_SHIFT (1 << 8)
+#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8
#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8)
/* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_L1_STATEST_SHIFT (1 << 4)
+#define OMAP4430_TESLA_L1_STATEST_SHIFT 4
#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5)
/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L2_ONSTATE_SHIFT (1 << 18)
+#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18
#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19)
/* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L2_RETSTATE_SHIFT (1 << 9)
+#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9
#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9)
/* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_L2_STATEST_SHIFT (1 << 6)
+#define OMAP4430_TESLA_L2_STATEST_SHIFT 6
#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7)
/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP4430_TIMEOUT_SHIFT (1 << 0)
+#define OMAP4430_TIMEOUT_SHIFT 0
#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_TIMEOUTEN_SHIFT (1 << 3)
+#define OMAP4430_TIMEOUTEN_SHIFT 3
#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_TRANSITION_EN_SHIFT (1 << 8)
+#define OMAP4430_TRANSITION_EN_SHIFT 8
#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_TRANSITION_ST_SHIFT (1 << 8)
+#define OMAP4430_TRANSITION_ST_SHIFT 8
#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8)
/* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_VALID_SHIFT (1 << 24)
+#define OMAP4430_VALID_SHIFT 24
#define OMAP4430_VALID_MASK BITFIELD(24, 24)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_BYPASSACK_EN_SHIFT (1 << 14)
+#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14
#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_BYPASSACK_ST_SHIFT (1 << 14)
+#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14
#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_IVA_VPACK_EN_SHIFT (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30
#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_IVA_VPACK_ST_SHIFT (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30
#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VC_MPU_VPACK_EN_SHIFT (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6
#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VC_MPU_VPACK_ST_SHIFT (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6
#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_RAERR_EN_SHIFT (1 << 12)
+#define OMAP4430_VC_RAERR_EN_SHIFT 12
#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_RAERR_ST_SHIFT (1 << 12)
+#define OMAP4430_VC_RAERR_ST_SHIFT 12
#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_SAERR_EN_SHIFT (1 << 11)
+#define OMAP4430_VC_SAERR_EN_SHIFT 11
#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_SAERR_ST_SHIFT (1 << 11)
+#define OMAP4430_VC_SAERR_ST_SHIFT 11
#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_TOERR_EN_SHIFT (1 << 13)
+#define OMAP4430_VC_TOERR_EN_SHIFT 13
#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_TOERR_ST_SHIFT (1 << 13)
+#define OMAP4430_VC_TOERR_ST_SHIFT 13
#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13)
/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP4430_VDDMAX_SHIFT (1 << 24)
+#define OMAP4430_VDDMAX_SHIFT 24
#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31)
/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP4430_VDDMIN_SHIFT (1 << 16)
+#define OMAP4430_VDDMIN_SHIFT 16
#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT (1 << 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12
#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12)
/* Used by PRM_RSTST */
-#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT (1 << 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT (1 << 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14
#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_IVA_PRESENCE_SHIFT (1 << 9)
+#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9
#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9)
/* Used by PRM_RSTST */
-#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT (1 << 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT (1 << 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13
#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13)
/* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_MPU_PRESENCE_SHIFT (1 << 8)
+#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8
#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8)
/* Used by PRM_RSTST */
-#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT (1 << 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6)
/* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT (1 << 0)
+#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0
#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7)
/* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT (1 << 8)
+#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8
#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15)
/* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT (1 << 16)
+#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16
#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_VPENABLE_SHIFT (1 << 0)
+#define OMAP4430_VPENABLE_SHIFT 0
#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0)
/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
-#define OMAP4430_VPINIDLE_SHIFT (1 << 0)
+#define OMAP4430_VPINIDLE_SHIFT 0
#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0)
/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP4430_VPVOLTAGE_SHIFT (1 << 0)
+#define OMAP4430_VPVOLTAGE_SHIFT 0
#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20
#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20
#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18
#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18
#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17
#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17
#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19
#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19
#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21
#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21
#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28
#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28
#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26
#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26
#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25
#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25
#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27
#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27
#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24
#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24
#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29
#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29
#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4
#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4
#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2
#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2
#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1
#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1
#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3
#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3
#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0)
/* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5
#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5)
/* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5
#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5)
/* Used by PRM_SRAM_COUNT */
-#define OMAP4430_VSETUPCNT_VALUE_SHIFT (1 << 8)
+#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8
#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15)
/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
-#define OMAP4430_VSTEPMAX_SHIFT (1 << 0)
+#define OMAP4430_VSTEPMAX_SHIFT 0
#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7)
/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
-#define OMAP4430_VSTEPMIN_SHIFT (1 << 0)
+#define OMAP4430_VSTEPMIN_SHIFT 0
#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7)
/* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_WAKE_MODEM_SHIFT (1 << 0)
+#define OMAP4430_WAKE_MODEM_SHIFT 0
#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_DMTIMER10_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_DMTIMER11_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_DMTIMER11_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_DMTIMER2_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_DMTIMER3_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_DMTIMER3_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_DMTIMER4_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_DMTIMER4_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_DMTIMER9_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_DMTIMER9_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT (1 << 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5
#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT (1 << 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4
#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT (1 << 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9
#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT (1 << 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8
#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT (1 << 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11
#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT (1 << 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10
#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10)
/* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT (1 << 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT (1 << 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13
#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT (1 << 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12)
/* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT (1 << 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14
#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14)
/* Used by PM_L4PER_HECC1_WKDEP */
-#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_HECC2_WKDEP */
-#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_WKUP_KEYBOARD_WKDEP */
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L3INIT_PCIESS_WKDEP */
-#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_PCIESS_WKDEP */
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_WKUP_RTC_WKDEP */
-#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ALWON_SR_CORE_WKDEP */
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_ALWON_SR_CORE_WKDEP */
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ALWON_SR_IVA_WKDEP */
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_ALWON_SR_IVA_WKDEP */
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ALWON_SR_MPU_WKDEP */
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0)
/* Used by PM_WKUP_TIMER12_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0)
/* Used by PM_WKUP_TIMER1_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT (1 << 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2)
/* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_L3INIT_UNIPRO1_WKDEP */
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_UNIPRO1_WKDEP */
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_USB_HOST_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_USB_HOST_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_USB_OTG_WKDEP */
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_USB_OTG_WKDEP */
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_USB_TLL_WKDEP */
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_L3INIT_USB_TLL_WKDEP */
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0)
/* Used by PM_WKUP_USIM_WKDEP */
-#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0)
/* Used by PM_WKUP_USIM_WKDEP */
-#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT (1 << 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3)
/* Used by PM_WKUP_WDT2_WKDEP */
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1)
/* Used by PM_WKUP_WDT2_WKDEP */
-#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0)
/* Used by PM_ABE_WDT3_WKDEP */
-#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT (1 << 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0)
/* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT (1 << 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8
#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8)
/* Used by PM_L3INIT_XHPI_WKDEP */
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT (1 << 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_WUCLK_CTRL_SHIFT (1 << 8)
+#define OMAP4430_WUCLK_CTRL_SHIFT 8
#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8)
/* Used by PRM_IO_PMCTRL */
-#define OMAP4430_WUCLK_STATUS_SHIFT (1 << 9)
+#define OMAP4430_WUCLK_STATUS_SHIFT 9
#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9)
#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ea050ce188a..5fba2aa8932 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -24,6 +24,8 @@
OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
#define OMAP44XX_PRM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
+ OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
#include "prm44xx.h"
@@ -177,9 +179,11 @@
/* Registers appearing on both 24xx and 34xx */
-#define RM_RSTCTRL 0x0050
-#define RM_RSTTIME 0x0054
-#define RM_RSTST 0x0058
+#define OMAP2_RM_RSTCTRL 0x0050
+#define OMAP2_RM_RSTTIME 0x0054
+#define OMAP2_RM_RSTST 0x0058
+#define OMAP2_PM_PWSTCTRL 0x00e0
+#define OMAP2_PM_PWSTST 0x00e4
#define PM_WKEN 0x00a0
#define PM_WKEN1 PM_WKEN
@@ -189,8 +193,6 @@
#define PM_EVGENCTRL 0x00d4
#define PM_EVGENONTIM 0x00d8
#define PM_EVGENOFFTIM 0x00dc
-#define PM_PWSTCTRL 0x00e0
-#define PM_PWSTST 0x00e4
/* Omap2 specific registers */
#define OMAP24XX_PM_WKEN2 0x00a4
@@ -218,6 +220,13 @@
#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
+/* Omap4 specific registers */
+#define OMAP4_RM_RSTCTRL 0x0000
+#define OMAP4_RM_RSTTIME 0x0004
+#define OMAP4_RM_RSTST 0x0008
+#define OMAP4_PM_PWSTCTRL 0x0000
+#define OMAP4_PM_PWSTST 0x0004
+
#ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 89be97f0589..adb2558bb12 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -386,26 +386,26 @@
/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
-#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
+#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
-#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
+#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
-#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
+#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
-#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
-#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
-#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
-#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
-#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
-#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
+#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
#endif
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
new file mode 100644
index 00000000000..cd435291702
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
@@ -0,0 +1,51 @@
+/*
+ * SDRC register values for the Numonyx M65KXXXXAM
+ *
+ * Copyright (C) 2009 Integration Software and Electronic Engineering.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
+#define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
+
+#include <plat/sdrc.h>
+
+/* Numonyx M65KXXXXAM */
+static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
+ [0] = {
+ .rate = 200000000,
+ .actim_ctrla = 0xe321d4c6,
+ .actim_ctrlb = 0x00022328,
+ .rfr_ctrl = 0x0005e601,
+ .mr = 0x00000032,
+ },
+ [1] = {
+ .rate = 166000000,
+ .actim_ctrla = 0xba9dc485,
+ .actim_ctrlb = 0x00022321,
+ .rfr_ctrl = 0x0004dc01,
+ .mr = 0x00000032,
+ },
+ [2] = {
+ .rate = 133000000,
+ .actim_ctrla = 0x9a19b485,
+ .actim_ctrlb = 0x0002231b,
+ .rfr_ctrl = 0x0003de01,
+ .mr = 0x00000032,
+ },
+ [3] = {
+ .rate = 83000000,
+ .actim_ctrla = 0x594ca242,
+ .actim_ctrlb = 0x00022310,
+ .rfr_ctrl = 0x00025501,
+ .mr = 0x00000032,
+ },
+ [4] = {
+ .rate = 0
+ },
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index cbfbd142e94..4c65f5628b3 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -119,8 +119,15 @@ int omap2_sdrc_get_params(unsigned long r,
void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
{
- omap2_sdrc_base = omap2_globals->sdrc;
- omap2_sms_base = omap2_globals->sms;
+ /* Static mapping, never released */
+ if (omap2_globals->sdrc) {
+ omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K);
+ WARN_ON(!omap2_sdrc_base);
+ }
+ if (omap2_globals->sms) {
+ omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
+ WARN_ON(!omap2_sms_base);
+ }
}
/**
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 19805a7de06..3771254dfa8 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -23,6 +23,7 @@
#include <linux/serial_reg.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/delay.h>
#include <plat/common.h>
#include <plat/board.h>
@@ -36,7 +37,13 @@
#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
-#define DEFAULT_TIMEOUT (5 * HZ)
+/*
+ * NOTE: By default the serial timeout is disabled as it causes lost characters
+ * over the serial ports. This means that the UART clocks will stay on until
+ * disabled via sysfs. This also causes that any deeper omap sleep states are
+ * blocked.
+ */
+#define DEFAULT_TIMEOUT 0
struct omap_uart_state {
int num;
@@ -74,7 +81,6 @@ static LIST_HEAD(uart_list);
static struct plat_serial8250_port serial_platform_data0[] = {
{
- .mapbase = OMAP_UART1_BASE,
.irq = 72,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
@@ -87,7 +93,6 @@ static struct plat_serial8250_port serial_platform_data0[] = {
static struct plat_serial8250_port serial_platform_data1[] = {
{
- .mapbase = OMAP_UART2_BASE,
.irq = 73,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
@@ -100,7 +105,6 @@ static struct plat_serial8250_port serial_platform_data1[] = {
static struct plat_serial8250_port serial_platform_data2[] = {
{
- .mapbase = OMAP_UART3_BASE,
.irq = 74,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
@@ -111,10 +115,8 @@ static struct plat_serial8250_port serial_platform_data2[] = {
}
};
-#ifdef CONFIG_ARCH_OMAP4
static struct plat_serial8250_port serial_platform_data3[] = {
{
- .mapbase = OMAP_UART4_BASE,
.irq = 70,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
@@ -124,7 +126,22 @@ static struct plat_serial8250_port serial_platform_data3[] = {
.flags = 0
}
};
-#endif
+
+void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
+{
+ serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
+ serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
+ serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
+ serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
+}
+
+static inline unsigned int __serial_read_reg(struct uart_port *up,
+ int offset)
+{
+ offset <<= up->regshift;
+ return (unsigned int)__raw_readb(up->membase + offset);
+}
+
static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
int offset)
{
@@ -132,6 +149,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
return (unsigned int)__raw_readb(up->membase + offset);
}
+static inline void __serial_write_reg(struct uart_port *up, int offset,
+ int value)
+{
+ offset <<= up->regshift;
+ __raw_writeb(value, up->membase + offset);
+}
+
static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
int value)
{
@@ -415,7 +439,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
uart->timeout = DEFAULT_TIMEOUT;
setup_timer(&uart->timer, omap_uart_idle_timer,
(unsigned long) uart);
- mod_timer(&uart->timer, jiffies + uart->timeout);
+ if (uart->timeout)
+ mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
if (cpu_is_omap34xx()) {
@@ -513,7 +538,7 @@ static ssize_t sleep_timeout_store(struct device *dev,
unsigned int value;
if (sscanf(buf, "%u", &value) != 1) {
- printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
+ dev_err(dev, "sleep_timeout_store: Invalid value\n");
return -EINVAL;
}
@@ -560,7 +585,7 @@ static struct omap_uart_state omap_uart[] = {
},
},
},
-#ifdef CONFIG_ARCH_OMAP4
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
{
.pdev = {
.name = "serial8250",
@@ -583,51 +608,77 @@ static unsigned int serial_in_override(struct uart_port *up, int offset)
{
if (UART_RX == offset) {
unsigned int lsr;
- lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
+ lsr = __serial_read_reg(up, UART_LSR);
if (!(lsr & UART_LSR_DR))
return -EPERM;
}
- return serial_read_reg(omap_uart[up->line].p, offset);
+
+ return __serial_read_reg(up, offset);
}
+static void serial_out_override(struct uart_port *up, int offset, int value)
+{
+ unsigned int status, tmout = 10000;
+
+ status = __serial_read_reg(up, UART_LSR);
+ while (!(status & UART_LSR_THRE)) {
+ /* Wait up to 10ms for the character(s) to be sent. */
+ if (--tmout == 0)
+ break;
+ udelay(1);
+ status = __serial_read_reg(up, UART_LSR);
+ }
+ __serial_write_reg(up, offset, value);
+}
void __init omap_serial_early_init(void)
{
- int i;
+ int i, nr_ports;
char name[16];
+ if (!(cpu_is_omap3630() || cpu_is_omap4430()))
+ nr_ports = 3;
+ else
+ nr_ports = ARRAY_SIZE(omap_uart);
+
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
- for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
+ for (i = 0; i < nr_ports; i++) {
struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
struct plat_serial8250_port *p = dev->platform_data;
+ /* Don't map zero-based physical address */
+ if (p->mapbase == 0) {
+ dev_warn(dev, "no physical address for uart#%d,"
+ " so skipping early_init...\n", i);
+ continue;
+ }
/*
* Module 4KB + L4 interconnect 4KB
* Static mapping, never released
*/
p->membase = ioremap(p->mapbase, SZ_8K);
if (!p->membase) {
- printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
+ dev_err(dev, "ioremap failed for uart%i\n", i + 1);
continue;
}
- sprintf(name, "uart%d_ick", i+1);
+ sprintf(name, "uart%d_ick", i + 1);
uart->ick = clk_get(NULL, name);
if (IS_ERR(uart->ick)) {
- printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
+ dev_err(dev, "Could not get uart%d_ick\n", i + 1);
uart->ick = NULL;
}
sprintf(name, "uart%d_fck", i+1);
uart->fck = clk_get(NULL, name);
if (IS_ERR(uart->fck)) {
- printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
+ dev_err(dev, "Could not get uart%d_fck\n", i + 1);
uart->fck = NULL;
}
@@ -670,6 +721,13 @@ void __init omap_serial_init_port(int port)
pdev = &uart->pdev;
dev = &pdev->dev;
+ /* Don't proceed if there's no clocks available */
+ if (unlikely(!uart->ick || !uart->fck)) {
+ WARN(1, "%s: can't init uart%d, no clocks available\n",
+ kobject_name(&dev->kobj), port);
+ return;
+ }
+
omap_uart_enable_clocks(uart);
omap_uart_reset(uart);
@@ -686,15 +744,19 @@ void __init omap_serial_init_port(int port)
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
- /* omap44xx: Never read empty UART fifo
- * omap3xxx: Never read empty UART fifo on UARTs
- * with IP rev >=0x52
- */
- if (cpu_is_omap44xx())
- uart->p->serial_in = serial_in_override;
- else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
- >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
- uart->p->serial_in = serial_in_override;
+ /*
+ * omap44xx: Never read empty UART fifo
+ * omap3xxx: Never read empty UART fifo on UARTs
+ * with IP rev >=0x52
+ */
+ if (cpu_is_omap44xx()) {
+ uart->p->serial_in = serial_in_override;
+ uart->p->serial_out = serial_out_override;
+ } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+ >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
+ uart->p->serial_in = serial_in_override;
+ uart->p->serial_out = serial_out_override;
+ }
}
/**
@@ -706,8 +768,13 @@ void __init omap_serial_init_port(int port)
*/
void __init omap_serial_init(void)
{
- int i;
+ int i, nr_ports;
+
+ if (!(cpu_is_omap3630() || cpu_is_omap4430()))
+ nr_ports = 3;
+ else
+ nr_ports = ARRAY_SIZE(omap_uart);
- for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
+ for (i = 0; i < nr_ports; i++)
omap_serial_init_port(i);
}
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 15268f8b61d..d522cd70bf5 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -33,12 +33,14 @@
#include "prm.h"
#include "sdrc.h"
+#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c
+
#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \
OMAP3430_PM_PREPWSTST)
#define PM_PREPWSTST_CORE_P 0x48306AE8
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST)
-#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
+#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
#define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0
@@ -57,6 +59,37 @@
#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+ .text
+/* Function to aquire the semaphore in scratchpad */
+ENTRY(lock_scratchpad_sem)
+ stmfd sp!, {lr} @ save registers on stack
+wait_sem:
+ mov r0,#1
+ ldr r1, sdrc_scratchpad_sem
+wait_loop:
+ ldr r2, [r1] @ load the lock value
+ cmp r2, r0 @ is the lock free ?
+ beq wait_loop @ not free...
+ swp r2, r0, [r1] @ semaphore free so lock it and proceed
+ cmp r2, r0 @ did we succeed ?
+ beq wait_sem @ no - try again
+ ldmfd sp!, {pc} @ restore regs and return
+sdrc_scratchpad_sem:
+ .word SDRC_SCRATCHPAD_SEM_V
+ENTRY(lock_scratchpad_sem_sz)
+ .word . - lock_scratchpad_sem
+
+ .text
+/* Function to release the scratchpad semaphore */
+ENTRY(unlock_scratchpad_sem)
+ stmfd sp!, {lr} @ save registers on stack
+ ldr r3, sdrc_scratchpad_sem
+ mov r2,#0
+ str r2,[r3]
+ ldmfd sp!, {pc} @ restore regs and return
+ENTRY(unlock_scratchpad_sem_sz)
+ .word . - unlock_scratchpad_sem
+
.text
/* Function call to get the restore pointer for resume from OFF */
ENTRY(get_restore_pointer)
@@ -245,24 +278,45 @@ restore:
mov r1, #0 @ set task id for ROM code in r1
mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
- adr r3, write_aux_control_params @ r3 points to parameters
+ ldr r4, scratchpad_base
+ ldr r3, [r4, #0xBC] @ r3 points to parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
.word 0xE1600071 @ call SMI monitor (smi #1)
+#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+ /* Restore L2 aux control register */
+ @ set service ID for PPA
+ mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
+ mov r12, r0 @ copy service ID in r12
+ mov r1, #0 @ set task ID for ROM code in r1
+ mov r2, #4 @ set some flags in r2, r6
+ mov r6, #0xff
+ ldr r4, scratchpad_base
+ ldr r3, [r4, #0xBC]
+ adds r3, r3, #8 @ r3 points to parameters
+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
+ .word 0xE1600071 @ call SMI monitor (smi #1)
+#endif
b logic_l1_restore
l2_inv_api_params:
.word 0x1, 0x00
-write_aux_control_params:
- .word 0x1, 0x72
l2_inv_gp:
/* Execute smi to invalidate L2 cache */
mov r12, #0x1 @ set up to invalide L2
smi: .word 0xE1600070 @ Call SMI monitor (smieq)
/* Write to Aux control register to set some bits */
- mov r0, #0x72
+ ldr r4, scratchpad_base
+ ldr r3, [r4,#0xBC]
+ ldr r0, [r3,#4]
mov r12, #0x3
.word 0xE1600070 @ Call SMI monitor (smieq)
+ ldr r4, scratchpad_base
+ ldr r3, [r4,#0xBC]
+ ldr r0, [r3,#12]
+ mov r12, #0x2
+ .word 0xE1600070 @ Call SMI monitor (smieq)
logic_l1_restore:
mov r1, #0
/* Invalidate all instruction caches to PoU
@@ -271,6 +325,7 @@ logic_l1_restore:
ldr r4, scratchpad_base
ldr r3, [r4,#0xBC]
+ adds r3, r3, #16
ldmia r3!, {r4-r6}
mov sp, r4
msr spsr_cxsf, r5
@@ -387,6 +442,11 @@ usettbr0:
save_context_wfi:
/*b save_context_wfi*/ @ enable to debug save code
mov r8, r0 /* Store SDRAM address in r8 */
+ mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
+ mov r4, #0x1 @ Number of parameters for restore call
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+ mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
+ stmia r8!, {r4-r5} @ Push parameters for restore call
/* Check what that target sleep state is:stored in r1*/
/* 1 - Only L1 and logic lost */
/* 2 - Only L2 lost */
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index cd04deaa88c..74fbed8491f 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -85,8 +85,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
case CLOCK_EVT_MODE_PERIODIC:
period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
period -= 1;
- if (cpu_is_omap44xx())
- period = 0xff; /* FIXME: */
omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
break;
case CLOCK_EVT_MODE_ONESHOT:
@@ -150,9 +148,6 @@ static void __init omap2_gp_clockevent_init(void)
"timer-gp: omap_dm_timer_set_source() failed\n");
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
- if (cpu_is_omap44xx())
- /* Assuming 32kHz clk is driving GPT1 */
- tick_rate = 32768; /* FIXME: */
pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
gptimer_id, tick_rate);
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index c1a650a9910..954682e6439 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,7 +28,7 @@
*/
void __cpuinit local_timer_setup(struct clock_event_device *evt)
{
- evt->irq = INT_44XX_LOCALTIMER_IRQ;
+ evt->irq = OMAP44XX_IRQ_LOCALTIMER;
twd_timer_setup(evt);
}
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index f1df873d59d..ee9f548d5d8 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -70,7 +70,7 @@ static struct platform_device ehci_device = {
/*
* setup_ehci_io_mux - initialize IO pad mux for USBHOST
*/
-static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
+static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode)
{
switch (port_mode[0]) {
case EHCI_HCD_OMAP_MODE_PHY:
@@ -213,7 +213,7 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
return;
}
-void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
+void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata)
{
platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
@@ -229,7 +229,7 @@ void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
#else
-void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
+void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata)
{
}
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index a80441dd19b..6d41fa7b2ce 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -47,70 +47,11 @@ static struct resource musb_resources[] = {
},
};
-static int clk_on;
-
-static int musb_set_clock(struct clk *clk, int state)
-{
- if (state) {
- if (clk_on > 0)
- return -ENODEV;
-
- clk_enable(clk);
- clk_on = 1;
- } else {
- if (clk_on == 0)
- return -ENODEV;
-
- clk_disable(clk);
- clk_on = 0;
- }
-
- return 0;
-}
-
-static struct musb_hdrc_eps_bits musb_eps[] = {
- { "ep1_tx", 10, },
- { "ep1_rx", 10, },
- { "ep2_tx", 9, },
- { "ep2_rx", 9, },
- { "ep3_tx", 3, },
- { "ep3_rx", 3, },
- { "ep4_tx", 3, },
- { "ep4_rx", 3, },
- { "ep5_tx", 3, },
- { "ep5_rx", 3, },
- { "ep6_tx", 3, },
- { "ep6_rx", 3, },
- { "ep7_tx", 3, },
- { "ep7_rx", 3, },
- { "ep8_tx", 2, },
- { "ep8_rx", 2, },
- { "ep9_tx", 2, },
- { "ep9_rx", 2, },
- { "ep10_tx", 2, },
- { "ep10_rx", 2, },
- { "ep11_tx", 2, },
- { "ep11_rx", 2, },
- { "ep12_tx", 2, },
- { "ep12_rx", 2, },
- { "ep13_tx", 2, },
- { "ep13_rx", 2, },
- { "ep14_tx", 2, },
- { "ep14_rx", 2, },
- { "ep15_tx", 2, },
- { "ep15_rx", 2, },
-};
-
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
- .soft_con = 1,
- .dma = 1,
.num_eps = 16,
- .dma_channels = 7,
- .dma_req_chan = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
.ram_bits = 12,
- .eps_bits = musb_eps,
};
static struct musb_hdrc_platform_data musb_plat = {
@@ -122,7 +63,6 @@ static struct musb_hdrc_platform_data musb_plat = {
.mode = MUSB_PERIPHERAL,
#endif
/* .clock is set dynamically */
- .set_clock = musb_set_clock,
.config = &musb_config,
/* REVISIT charge pump on TWL4030 can supply up to
@@ -146,28 +86,34 @@ static struct platform_device musb_device = {
.resource = musb_resources,
};
-void __init usb_musb_init(void)
+void __init usb_musb_init(struct omap_musb_board_data *board_data)
{
- if (cpu_is_omap243x())
+ if (cpu_is_omap243x()) {
musb_resources[0].start = OMAP243X_HS_BASE;
- else
+ } else if (cpu_is_omap34xx()) {
musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
- musb_resources[0].end = musb_resources[0].start + SZ_8K - 1;
+ } else if (cpu_is_omap44xx()) {
+ musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
+ musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
+ musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
+ }
+ musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
/*
* REVISIT: This line can be removed once all the platforms using
* musb_core.c have been converted to use use clkdev.
*/
musb_plat.clock = "ick";
+ musb_plat.board_data = board_data;
+ musb_plat.power = board_data->power >> 1;
+ musb_plat.mode = board_data->mode;
- if (platform_device_register(&musb_device) < 0) {
+ if (platform_device_register(&musb_device) < 0)
printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
- return;
- }
}
#else
-void __init usb_musb_init(void)
+void __init usb_musb_init(struct omap_musb_board_data *board_data)
{
}
#endif /* CONFIG_USB_MUSB_SOC */