diff options
Diffstat (limited to 'arch/arm/mach-s3c2410')
76 files changed, 6 insertions, 9111 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 5261a7ed099..68d89cb96af 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -2,42 +2,6 @@ # # Licensed under GPLv2 -config CPU_S3C2410 - bool - depends on ARCH_S3C2410 - select CPU_ARM920T - select S3C2410_CLOCK - select CPU_LLSERIAL_S3C2410 - select S3C2410_PM if PM - select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX - help - Support for S3C2410 and S3C2410A family from the S3C24XX line - of Samsung Mobile CPUs. - -config CPU_S3C2410_DMA - bool - depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442) - default y if CPU_S3C2410 || CPU_S3C2442 - help - DMA device selection for S3C2410 and compatible CPUs - -config S3C2410_PM - bool - help - Power Management code common to S3C2410 and better - -config SIMTEC_NOR - bool - help - Internal node to specify machine has simtec NOR mapping - -config MACH_BAST_IDE - bool - select HAVE_PATA_PLATFORM - help - Internal node for machines with an BAST style IDE - interface - # cpu frequency scaling support config S3C2410_CPUFREQ @@ -54,121 +18,3 @@ config S3C2410_PLLTABLE help Select the PLL table for the S3C2410 -menu "S3C2410 Machines" - -config ARCH_SMDK2410 - bool "SMDK2410/A9M2410" - select CPU_S3C2410 - select MACH_SMDK - help - Say Y here if you are using the SMDK2410 or the derived module A9M2410 - <http://www.fsforth.de> - -config ARCH_H1940 - bool "IPAQ H1940" - select CPU_S3C2410 - select PM_H1940 if PM - select S3C_DEV_USB_HOST - select S3C_DEV_NAND - select S3C2410_SETUP_TS - help - Say Y here if you are using the HP IPAQ H1940 - -config H1940BT - tristate "Control the state of H1940 bluetooth chip" - depends on ARCH_H1940 - select RFKILL - help - This is a simple driver that is able to control - the state of built in bluetooth chip on h1940. - -config PM_H1940 - bool - help - Internal node for H1940 and related PM - -config MACH_N30 - bool "Acer N30 family" - select CPU_S3C2410 - select MACH_N35 - select S3C_DEV_USB_HOST - select S3C_DEV_NAND - help - Say Y here if you want suppt for the Acer N30, Acer N35, - Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. - -config MACH_N35 - bool - help - Internal node in order to enable support for Acer N35 if Acer N30 is - selected. - -config ARCH_BAST - bool "Simtec Electronics BAST (EB2410ITX)" - select CPU_S3C2410 - select S3C2410_IOTIMING if S3C2410_CPUFREQ - select PM_SIMTEC if PM - select SIMTEC_NOR - select MACH_BAST_IDE - select S3C24XX_DCLK - select ISA - select S3C_DEV_HWMON - select S3C_DEV_USB_HOST - select S3C_DEV_NAND - help - Say Y here if you are using the Simtec Electronics EB2410ITX - development board (also known as BAST) - -config MACH_OTOM - bool "NexVision OTOM Board" - select CPU_S3C2410 - select S3C_DEV_USB_HOST - select S3C_DEV_NAND - help - Say Y here if you are using the Nex Vision OTOM board - -config MACH_AML_M5900 - bool "AML M5900 Series" - select CPU_S3C2410 - select PM_SIMTEC if PM - select S3C_DEV_USB_HOST - help - Say Y here if you are using the American Microsystems M5900 Series - <http://www.amltd.com> - -config BAST_PC104_IRQ - bool "BAST PC104 IRQ support" - depends on ARCH_BAST - default y - help - Say Y here to enable the PC104 IRQ routing on the - Simtec BAST (EB2410ITX) - -config MACH_TCT_HAMMER - bool "TCT Hammer Board" - select CPU_S3C2410 - select S3C_DEV_USB_HOST - help - Say Y here if you are using the TinCanTools Hammer Board - <http://www.tincantools.com> - -config MACH_VR1000 - bool "Thorcom VR1000" - select PM_SIMTEC if PM - select S3C24XX_DCLK - select SIMTEC_NOR - select MACH_BAST_IDE - select CPU_S3C2410 - select S3C_DEV_USB_HOST - help - Say Y here if you are using the Thorcom VR1000 board. - -config MACH_QT2410 - bool "QT2410" - select CPU_S3C2410 - select S3C_DEV_USB_HOST - select S3C_DEV_NAND - help - Say Y here if you are using the Armzone QT2410 - -endmenu diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 782fd81144e..6b9a316e004 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -9,32 +9,6 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_CPU_S3C2410) += s3c2410.o -obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o -obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o -obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o -# Machine support - -obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o -obj-$(CONFIG_ARCH_H1940) += mach-h1940.o -obj-$(CONFIG_H1940BT) += h1940-bluetooth.o -obj-$(CONFIG_PM_H1940) += pm-h1940.o -obj-$(CONFIG_MACH_N30) += mach-n30.o -obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o -obj-$(CONFIG_MACH_OTOM) += mach-otom.o -obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o -obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o -obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o -obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o -obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o - -# Common bits of machine support - -obj-$(CONFIG_SIMTEC_NOR) += nor-simtec.o - -# machine additions - -obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot deleted file mode 100644 index 4457605ba04..00000000000 --- a/arch/arm/mach-s3c2410/Makefile.boot +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_PM_H1940),y) - zreladdr-y += 0x30108000 - params_phys-y := 0x30100100 -else - zreladdr-y += 0x30008000 - params_phys-y := 0x30000100 -endif diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c2410/bast-ide.c deleted file mode 100644 index 298ececfa36..00000000000 --- a/arch/arm/mach-s3c2410/bast-ide.c +++ /dev/null @@ -1,112 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/bast-ide.c - * - * Copyright 2007 Simtec Electronics - * http://www.simtec.co.uk/products/EB2410ITX/ - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/interrupt.h> - -#include <linux/platform_device.h> -#include <linux/ata_platform.h> - -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/map.h> -#include <mach/bast-map.h> -#include <mach/bast-irq.h> - -/* IDE ports */ - -static struct pata_platform_info bast_ide_platdata = { - .ioport_shift = 5, -}; - -#define IDE_CS S3C2410_CS5 - -static struct resource bast_ide0_resource[] = { - [0] = { - .start = IDE_CS + BAST_PA_IDEPRI, - .end = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) , - .end = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_IDE0, - .end = IRQ_IDE0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bast_device_ide0 = { - .name = "pata_platform", - .id = 0, - .num_resources = ARRAY_SIZE(bast_ide0_resource), - .resource = bast_ide0_resource, - .dev = { - .platform_data = &bast_ide_platdata, - .coherent_dma_mask = ~0, - } - -}; - -static struct resource bast_ide1_resource[] = { - [0] = { - .start = IDE_CS + BAST_PA_IDESEC, - .end = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), - .end = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_IDE1, - .end = IRQ_IDE1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bast_device_ide1 = { - .name = "pata_platform", - .id = 1, - .num_resources = ARRAY_SIZE(bast_ide1_resource), - .resource = bast_ide1_resource, - .dev = { - .platform_data = &bast_ide_platdata, - .coherent_dma_mask = ~0, - } -}; - -static struct platform_device *bast_ide_devices[] __initdata = { - &bast_device_ide0, - &bast_device_ide1, -}; - -static __init int bast_ide_init(void) -{ - if (machine_is_bast() || machine_is_vr1000()) - return platform_add_devices(bast_ide_devices, - ARRAY_SIZE(bast_ide_devices)); - - return 0; -} - -fs_initcall(bast_ide_init); diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c deleted file mode 100644 index ac7b2ad5c40..00000000000 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ /dev/null @@ -1,166 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/bast-irq.c - * - * Copyright 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://www.simtec.co.uk/products/EB2410ITX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/ioport.h> -#include <linux/device.h> -#include <linux/io.h> - -#include <asm/mach-types.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/irq.h> - -#include <mach/regs-irq.h> -#include <mach/bast-map.h> -#include <mach/bast-irq.h> - -#include <plat/irq.h> - -#if 0 -#include <asm/debug-ll.h> -#endif - -#define irqdbf(x...) -#define irqdbf2(x...) - - -/* handle PC104 ISA interrupts from the system CPLD */ - -/* table of ISA irq nos to the relevant mask... zero means - * the irq is not implemented -*/ -static unsigned char bast_pc104_irqmasks[] = { - 0, /* 0 */ - 0, /* 1 */ - 0, /* 2 */ - 1, /* 3 */ - 0, /* 4 */ - 2, /* 5 */ - 0, /* 6 */ - 4, /* 7 */ - 0, /* 8 */ - 0, /* 9 */ - 8, /* 10 */ - 0, /* 11 */ - 0, /* 12 */ - 0, /* 13 */ - 0, /* 14 */ - 0, /* 15 */ -}; - -static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 }; - -static void -bast_pc104_mask(struct irq_data *data) -{ - unsigned long temp; - - temp = __raw_readb(BAST_VA_PC104_IRQMASK); - temp &= ~bast_pc104_irqmasks[data->irq]; - __raw_writeb(temp, BAST_VA_PC104_IRQMASK); -} - -static void -bast_pc104_maskack(struct irq_data *data) -{ - struct irq_desc *desc = irq_desc + IRQ_ISA; - - bast_pc104_mask(data); - desc->irq_data.chip->irq_ack(&desc->irq_data); -} - -static void -bast_pc104_unmask(struct irq_data *data) -{ - unsigned long temp; - - temp = __raw_readb(BAST_VA_PC104_IRQMASK); - temp |= bast_pc104_irqmasks[data->irq]; - __raw_writeb(temp, BAST_VA_PC104_IRQMASK); -} - -static struct irq_chip bast_pc104_chip = { - .irq_mask = bast_pc104_mask, - .irq_unmask = bast_pc104_unmask, - .irq_ack = bast_pc104_maskack -}; - -static void -bast_irq_pc104_demux(unsigned int irq, - struct irq_desc *desc) -{ - unsigned int stat; - unsigned int irqno; - int i; - - stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf; - - if (unlikely(stat == 0)) { - /* ack if we get an irq with nothing (ie, startup) */ - - desc = irq_desc + IRQ_ISA; - desc->irq_data.chip->irq_ack(&desc->irq_data); - } else { - /* handle the IRQ */ - - for (i = 0; stat != 0; i++, stat >>= 1) { - if (stat & 1) { - irqno = bast_pc104_irqs[i]; - generic_handle_irq(irqno); - } - } - } -} - -static __init int bast_irq_init(void) -{ - unsigned int i; - - if (machine_is_bast()) { - printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n"); - - /* zap all the IRQs */ - - __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); - - irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); - - /* register our IRQs */ - - for (i = 0; i < 4; i++) { - unsigned int irqno = bast_pc104_irqs[i]; - - irq_set_chip_and_handler(irqno, &bast_pc104_chip, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - } - - return 0; -} - -arch_initcall(bast_irq_init); diff --git a/arch/arm/mach-s3c2410/common.h b/arch/arm/mach-s3c2410/common.h deleted file mode 100644 index f65dc806296..00000000000 --- a/arch/arm/mach-s3c2410/common.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Common Header for S3C2410 machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_S3C2410_COMMON_H -#define __ARCH_ARM_MACH_S3C2410_COMMON_H - -void s3c2410_restart(char mode, const char *cmd); - -#endif /* __ARCH_ARM_MACH_S3C2410_COMMON_H */ diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c index 7dc6c46b5e2..5404535da1a 100644 --- a/arch/arm/mach-s3c2410/cpu-freq.c +++ b/arch/arm/mach-s3c2410/cpu-freq.c @@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), }; -static int s3c2410_cpufreq_add(struct device *dev) +static int s3c2410_cpufreq_add(struct device *dev, + struct subsys_interface *sif) { return s3c_cpufreq_register(&s3c2410_cpufreq_info); } @@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void) arch_initcall(s3c2410_cpufreq_init); -static int s3c2410a_cpufreq_add(struct device *dev) +static int s3c2410a_cpufreq_add(struct device *dev, + struct subsys_interface *sif) { /* alter the maximum freq settings for S3C2410A. If a board knows * it only has a maximum of 200, then it should register its own @@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev) s3c2410_cpufreq_info.max.pclk = 66500000; s3c2410_cpufreq_info.name = "s3c2410a"; - return s3c2410_cpufreq_add(dev); + return s3c2410_cpufreq_add(dev, sif); } static struct subsys_interface s3c2410a_cpufreq_interface = { diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c deleted file mode 100644 index 2afd00014a7..00000000000 --- a/arch/arm/mach-s3c2410/dma.c +++ /dev/null @@ -1,185 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/dma.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 DMA selection - * - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/serial_core.h> - -#include <mach/map.h> -#include <mach/dma.h> - -#include <plat/cpu.h> -#include <plat/dma-s3c24xx.h> - -#include <plat/regs-serial.h> -#include <mach/regs-gpio.h> -#include <plat/regs-ac97.h> -#include <plat/regs-dma.h> -#include <mach/regs-mem.h> -#include <mach/regs-lcd.h> -#include <mach/regs-sdi.h> -#include <plat/regs-iis.h> -#include <plat/regs-spi.h> - -static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { - [DMACH_XD0] = { - .name = "xdreq0", - .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID, - }, - [DMACH_XD1] = { - .name = "xdreq1", - .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID, - }, - [DMACH_SDI] = { - .name = "sdi", - .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, - .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, - }, - [DMACH_SPI0] = { - .name = "spi0", - .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, - }, - [DMACH_SPI1] = { - .name = "spi1", - .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, - }, - [DMACH_UART0] = { - .name = "uart0", - .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, - }, - [DMACH_UART1] = { - .name = "uart1", - .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, - }, - [DMACH_UART2] = { - .name = "uart2", - .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, - }, - [DMACH_TIMER] = { - .name = "timer", - .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID, - .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID, - }, - [DMACH_I2S_IN] = { - .name = "i2s-sdi", - .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, - .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, - }, - [DMACH_I2S_OUT] = { - .name = "i2s-sdo", - .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, - }, - [DMACH_USB_EP1] = { - .name = "usb-ep1", - .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID, - }, - [DMACH_USB_EP2] = { - .name = "usb-ep2", - .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID, - }, - [DMACH_USB_EP3] = { - .name = "usb-ep3", - .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID, - }, - [DMACH_USB_EP4] = { - .name = "usb-ep4", - .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID, - }, -}; - -static void s3c2410_dma_select(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map) -{ - chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID; -} - -static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = { - .select = s3c2410_dma_select, - .dcon_mask = 7 << 24, - .map = s3c2410_dma_mappings, - .map_size = ARRAY_SIZE(s3c2410_dma_mappings), -}; - -static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { - .channels = { - [DMACH_SDI] = { - .list = { - [0] = 3 | DMA_CH_VALID, - [1] = 2 | DMA_CH_VALID, - [2] = 0 | DMA_CH_VALID, - }, - }, - [DMACH_I2S_IN] = { - .list = { - [0] = 1 | DMA_CH_VALID, - [1] = 2 | DMA_CH_VALID, - }, - }, - }, -}; - -static int __init s3c2410_dma_add(struct device *dev) -{ - s3c2410_dma_init(); - s3c24xx_dma_order_set(&s3c2410_dma_order); - return s3c24xx_dma_init_map(&s3c2410_dma_sel); -} - -#if defined(CONFIG_CPU_S3C2410) -static struct subsys_interface s3c2410_dma_interface = { - .name = "s3c2410_dma", - .subsys = &s3c2410_subsys, - .add_dev = s3c2410_dma_add, -}; - -static int __init s3c2410_dma_drvinit(void) -{ - return subsys_interface_register(&s3c2410_interface); -} - -arch_initcall(s3c2410_dma_drvinit); - -static struct subsys_interface s3c2410a_dma_interface = { - .name = "s3c2410a_dma", - .subsys = &s3c2410a_subsys, - .add_dev = s3c2410_dma_add, -}; - -static int __init s3c2410a_dma_drvinit(void) -{ - return subsys_interface_register(&s3c2410a_dma_interface); -} - -arch_initcall(s3c2410a_dma_drvinit); -#endif - -#if defined(CONFIG_CPU_S3C2442) -/* S3C2442 DMA contains the same selection table as the S3C2410 */ -static struct subsys_interface s3c2442_dma_interface = { - .name = "s3c2442_dma", - .subsys = &s3c2442_subsys, - .add_dev = s3c2410_dma_add, -}; - -static int __init s3c2442_dma_drvinit(void) -{ - return subsys_interface_register(&s3c2442_dma_interface); -} - -arch_initcall(s3c2442_dma_drvinit); -#endif - diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c deleted file mode 100644 index a5eeb62ce1c..00000000000 --- a/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * arch/arm/mach-s3c2410/h1940-bluetooth.c - * Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - * - * S3C2410 bluetooth "driver" - * - */ - -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/string.h> -#include <linux/ctype.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/rfkill.h> - -#include <mach/regs-gpio.h> -#include <mach/hardware.h> -#include <mach/h1940-latch.h> -#include <mach/h1940.h> - -#define DRV_NAME "h1940-bt" - -/* Bluetooth control */ -static void h1940bt_enable(int on) -{ - if (on) { - /* Power on the chip */ - gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1); - /* Reset the chip */ - mdelay(10); - - gpio_set_value(S3C2410_GPH(1), 1); - mdelay(10); - gpio_set_value(S3C2410_GPH(1), 0); - - h1940_led_blink_set(-EINVAL, GPIO_LED_BLINK, NULL, NULL); - } - else { - gpio_set_value(S3C2410_GPH(1), 1); - mdelay(10); - gpio_set_value(S3C2410_GPH(1), 0); - mdelay(10); - gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0); - - h1940_led_blink_set(-EINVAL, GPIO_LED_NO_BLINK_LOW, NULL, NULL); - } -} - -static int h1940bt_set_block(void *data, bool blocked) -{ - h1940bt_enable(!blocked); - return 0; -} - -static const struct rfkill_ops h1940bt_rfkill_ops = { - .set_block = h1940bt_set_block, -}; - -static int __devinit h1940bt_probe(struct platform_device *pdev) -{ - struct rfkill *rfk; - int ret = 0; - - ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev)); - if (ret) { - dev_err(&pdev->dev, "could not get GPH1\n"); - return ret; - } - - ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev)); - if (ret) { - gpio_free(S3C2410_GPH(1)); - dev_err(&pdev->dev, "could not get BT_POWER\n"); - return ret; - } - - /* Configures BT serial port GPIOs */ - s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); - s3c_gpio_setpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); - s3c_gpio_setpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); - s3c_gpio_setpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); - s3c_gpio_setpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE); - - rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH, - &h1940bt_rfkill_ops, NULL); - if (!rfk) { - ret = -ENOMEM; - goto err_rfk_alloc; - } - - ret = rfkill_register(rfk); - if (ret) - goto err_rfkill; - - platform_set_drvdata(pdev, rfk); - - return 0; - -err_rfkill: - rfkill_destroy(rfk); -err_rfk_alloc: - return ret; -} - -static int h1940bt_remove(struct platform_device *pdev) -{ - struct rfkill *rfk = platform_get_drvdata(pdev); - - platform_set_drvdata(pdev, NULL); - gpio_free(S3C2410_GPH(1)); - - if (rfk) { - rfkill_unregister(rfk); - rfkill_destroy(rfk); - } - rfk = NULL; - - h1940bt_enable(0); - - return 0; -} - - -static struct platform_driver h1940bt_driver = { - .driver = { - .name = DRV_NAME, - }, - .probe = h1940bt_probe, - .remove = h1940bt_remove, -}; - - -static int __init h1940bt_init(void) -{ - return platform_driver_register(&h1940bt_driver); -} - -static void __exit h1940bt_exit(void) -{ - platform_driver_unregister(&h1940bt_driver); -} - -module_init(h1940bt_init); -module_exit(h1940bt_exit); - -MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); -MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h deleted file mode 100644 index 1b614d5a81f..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_ANUBISCPLD_H -#define __ASM_ARCH_ANUBISCPLD_H - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define ANUBIS_CTRL1_NANDSEL (0x3) - -/* IDREG - revision */ - -#define ANUBIS_IDREG_REVMASK (0x7) - -#endif /* __ASM_ARCH_ANUBISCPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h deleted file mode 100644 index a2a328134e3..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_ANUBISIRQ_H -#define __ASM_ARCH_ANUBISIRQ_H - -#define IRQ_IDE0 IRQ_EINT2 -#define IRQ_IDE1 IRQ_EINT3 -#define IRQ_ASIX IRQ_EINT1 - -#endif /* __ASM_ARCH_ANUBISIRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c2410/include/mach/anubis-map.h deleted file mode 100644 index c9deb3a5b2c..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/anubis-map.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-map.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -#ifndef __ASM_ARCH_ANUBISMAP_H -#define __ASM_ARCH_ANUBISMAP_H - -/* start peripherals off after the S3C2410 */ - -#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) - -#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ -#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) - -#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ -#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23)) - -#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) -#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) -#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) -#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) - -#endif /* __ASM_ARCH_ANUBISMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h deleted file mode 100644 index bee2a7a932a..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * BAST - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTCPLD_H -#define __ASM_ARCH_BASTCPLD_H - -/* CTRL1 - Audio LR routing */ - -#define BAST_CPLD_CTRL1_LRCOFF (0x00) -#define BAST_CPLD_CTRL1_LRCADC (0x01) -#define BAST_CPLD_CTRL1_LRCDAC (0x02) -#define BAST_CPLD_CTRL1_LRCARM (0x03) -#define BAST_CPLD_CTRL1_LRMASK (0x03) - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define BAST_CPLD_CTRL2_WNAND (0x04) -#define BAST_CPLD_CTLR2_IDERST (0x08) - -/* CTRL3 - rom write control, CPLD identity */ - -#define BAST_CPLD_CTRL3_IDMASK (0x0e) -#define BAST_CPLD_CTRL3_ROMWEN (0x01) - -/* CTRL4 - 8bit LCD interface control/status */ - -#define BAST_CPLD_CTRL4_LLAT (0x01) -#define BAST_CPLD_CTRL4_LCDRW (0x02) -#define BAST_CPLD_CTRL4_LCDCMD (0x04) -#define BAST_CPLD_CTRL4_LCDE2 (0x01) - -/* CTRL5 - DMA routing */ - -#define BAST_CPLD_DMA0_PRIIDE (0<<0) -#define BAST_CPLD_DMA0_SECIDE (1<<0) -#define BAST_CPLD_DMA0_ISA15 (2<<0) -#define BAST_CPLD_DMA0_ISA36 (3<<0) - -#define BAST_CPLD_DMA1_PRIIDE (0<<2) -#define BAST_CPLD_DMA1_SECIDE (1<<2) -#define BAST_CPLD_DMA1_ISA15 (2<<2) -#define BAST_CPLD_DMA1_ISA36 (3<<2) - -#endif /* __ASM_ARCH_BASTCPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h deleted file mode 100644 index cac428c42e7..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h +++ /dev/null @@ -1,29 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-irq.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine BAST - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTIRQ_H -#define __ASM_ARCH_BASTIRQ_H - -/* irq numbers to onboard peripherals */ - -#define IRQ_USBOC IRQ_EINT18 -#define IRQ_IDE0 IRQ_EINT16 -#define IRQ_IDE1 IRQ_EINT17 -#define IRQ_PCSERIAL1 IRQ_EINT15 -#define IRQ_PCSERIAL2 IRQ_EINT14 -#define IRQ_PCPARALLEL IRQ_EINT13 -#define IRQ_ASIX IRQ_EINT11 -#define IRQ_DM9000 IRQ_EINT10 -#define IRQ_ISA IRQ_EINT9 -#define IRQ_SMALERT IRQ_EINT8 - -#endif /* __ASM_ARCH_BASTIRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h deleted file mode 100644 index 6e7dc9d0cf0..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-map.h +++ /dev/null @@ -1,146 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-map.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine BAST - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#ifndef __ASM_ARCH_BASTMAP_H -#define __ASM_ARCH_BASTMAP_H - -#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */ -#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */ -#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */ -#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */ -#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ -#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) - -#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ -#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) - -#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ -#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) - -#define BAST_PA_LCD_RCMD1 (0x8800000) -#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) - -#define BAST_PA_LCD_WCMD1 (0x8000000) -#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) - -#define BAST_PA_LCD_RDATA1 (0x9800000) -#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) - -#define BAST_PA_LCD_WDATA1 (0x9000000) -#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) - -#define BAST_PA_LCD_RCMD2 (0xA800000) -#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) - -#define BAST_PA_LCD_WCMD2 (0xA000000) -#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) - -#define BAST_PA_LCD_RDATA2 (0xB800000) -#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) - -#define BAST_PA_LCD_WDATA2 (0xB000000) -#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) - - -/* 0xE0000000 contains the IO space that is split by speed and - * wether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x00000000 to 0x01000000 16MB ISA IO space - * 0x01000000 to 0x02000000 16MB ISA memory space - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02400000 to 0x02500000 1MB ASIX ethernet controller - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller - * 0x02600000 to 0x02700000 1MB PC SuperIO controller - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) -#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) -#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) -#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) -#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) -#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) -#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) -#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) -#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VAM_CS2 (0x00000000) -#define BAST_VAM_CS3 (0x04000000) -#define BAST_VAM_CS4 (0x08000000) -#define BAST_VAM_CS5 (0x0C000000) - -/* physical offset addresses for the peripherals */ - -#define BAST_PA_ISAIO (0x00000000) -#define BAST_PA_ASIXNET (0x01000000) -#define BAST_PA_SUPERIO (0x01800000) -#define BAST_PA_IDEPRI (0x02000000) -#define BAST_PA_IDEPRIAUX (0x02800000) -#define BAST_PA_IDESEC (0x03000000) -#define BAST_PA_IDESECAUX (0x03800000) -#define BAST_PA_ISAMEM (0x04000000) -#define BAST_PA_DM9000 (0x05000000) - -/* some configurations for the peripherals */ - -#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) -/* */ - -#define BAST_ASIXNET_CS BAST_VAM_CS5 -#define BAST_IDE_CS BAST_VAM_CS5 -#define BAST_DM9000_CS BAST_VAM_CS4 - -#endif /* __ASM_ARCH_BASTMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h deleted file mode 100644 index 4c38b39b741..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h +++ /dev/null @@ -1,40 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * Vincent Sanders <vince@simtec.co.uk> - * - * Machine BAST - Power Management chip - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTPMU_H -#define __ASM_ARCH_BASTPMU_H "08_OCT_2004" - -#define BASTPMU_REG_IDENT (0x00) -#define BASTPMU_REG_VERSION (0x01) -#define BASTPMU_REG_DDCCTRL (0x02) -#define BASTPMU_REG_POWER (0x03) -#define BASTPMU_REG_RESET (0x04) -#define BASTPMU_REG_GWO (0x05) -#define BASTPMU_REG_WOL (0x06) -#define BASTPMU_REG_WOR (0x07) -#define BASTPMU_REG_UID (0x09) - -#define BASTPMU_EEPROM (0xC0) - -#define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0) -#define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8) -#define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9) - -#define BASTPMU_IDENT_0 0x53 -#define BASTPMU_IDENT_1 0x42 -#define BASTPMU_IDENT_2 0x50 -#define BASTPMU_IDENT_3 0x4d - -#define BASTPMU_RESET_GUARD (0x55) - -#endif /* __ASM_ARCH_BASTPMU_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S deleted file mode 100644 index 4135de87d1f..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S +++ /dev/null @@ -1,101 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Copyright (C) 2005 Simtec Electronics - * - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <plat/regs-serial.h> - -#define S3C2410_UART1_OFF (0x4000) -#define SHIFT_2440TXF (14-9) - - .macro addruart, rp, rv, tmp - ldr \rp, = S3C24XX_PA_UART - ldr \rv, = S3C24XX_VA_UART -#if CONFIG_DEBUG_S3C_UART != 0 - add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) - add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) -#endif - .endm - - .macro fifo_full_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 1004f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? -1004: - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - moveq \rd, \rd, lsr #SHIFT_2440TXF - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - - .macro fifo_full_s3c2410 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - tst \rd, #S3C2410_UFSTAT_TXFULL - .endm - -/* fifo level reading */ - - .macro fifo_level_s3c24xx rd, rx - @ check for arm920 vs arm926. currently assume all arm926 - @ devices have an 64 byte FIFO identical to the s3c2440 - mrc p15, 0, \rd, c0, c0 - and \rd, \rd, #0xff0 - teq \rd, #0x260 - beq 10000f - mrc p15, 0, \rd, c1, c0 - tst \rd, #1 - addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) - addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) - bic \rd, \rd, #0xff000 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] - and \rd, \rd, #0x00ff0000 - teq \rd, #0x00440000 @ is it 2440? - -10000: - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - andne \rd, \rd, #S3C2410_UFSTAT_TXMASK - andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK - .endm - - .macro fifo_level_s3c2410 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] - and \rd, \rd, #S3C2410_UFSTAT_TXMASK - .endm - -/* Select the correct implementation depending on the configuration. The - * S3C2440 will get selected by default, as these are the most widely - * used variants of these -*/ - -#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) -#define fifo_full fifo_full_s3c2410 -#define fifo_level fifo_level_s3c2410 -#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) -#define fifo_full fifo_full_s3c24xx -#define fifo_level fifo_level_s3c24xx -#endif - -/* include the reset of the code which will do the work */ - -#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h deleted file mode 100644 index acbdfecd418..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ /dev/null @@ -1,210 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/dma.h - * - * Copyright (C) 2003-2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Samsung S3C24XX DMA support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H __FILE__ - -#include <linux/device.h> - -#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ - -/* We use `virtual` dma channels to hide the fact we have only a limited - * number of DMA channels, and not of all of them (dependent on the device) - * can be attached to any DMA source. We therefore let the DMA core handle - * the allocation of hardware channels to clients. -*/ - -enum dma_ch { - DMACH_XD0, - DMACH_XD1, - DMACH_SDI, - DMACH_SPI0, - DMACH_SPI1, - DMACH_UART0, - DMACH_UART1, - DMACH_UART2, - DMACH_TIMER, - DMACH_I2S_IN, - DMACH_I2S_OUT, - DMACH_PCM_IN, - DMACH_PCM_OUT, - DMACH_MIC_IN, - DMACH_USB_EP1, - DMACH_USB_EP2, - DMACH_USB_EP3, - DMACH_USB_EP4, - DMACH_UART0_SRC2, /* s3c2412 second uart sources */ - DMACH_UART1_SRC2, - DMACH_UART2_SRC2, - DMACH_UART3, /* s3c2443 has extra uart */ - DMACH_UART3_SRC2, - DMACH_MAX, /* the end entry */ -}; - -static inline bool samsung_dma_has_circular(void) -{ - return false; -} - -static inline bool samsung_dma_is_dmadev(void) -{ - return false; -} - -#include <plat/dma.h> - -#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ - -/* we have 4 dma channels */ -#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416) -#define S3C_DMA_CHANNELS (4) -#else -#define S3C_DMA_CHANNELS (6) -#endif - -/* types */ - -enum s3c2410_dma_state { - S3C2410_DMA_IDLE, - S3C2410_DMA_RUNNING, - S3C2410_DMA_PAUSED -}; - -/* enum s3c2410_dma_loadst - * - * This represents the state of the DMA engine, wrt to the loaded / running - * transfers. Since we don't have any way of knowing exactly the state of - * the DMA transfers, we need to know the state to make decisions on wether - * we can - * - * S3C2410_DMA_NONE - * - * There are no buffers loaded (the channel should be inactive) - * - * S3C2410_DMA_1LOADED - * - * There is one buffer loaded, however it has not been confirmed to be - * loaded by the DMA engine. This may be because the channel is not - * yet running, or the DMA driver decided that it was too costly to - * sit and wait for it to happen. - * - * S3C2410_DMA_1RUNNING - * - * The buffer has been confirmed running, and not finisged - * - * S3C2410_DMA_1LOADED_1RUNNING - * - * There is a buffer waiting to be loaded by the DMA engine, and one - * currently running. -*/ - -enum s3c2410_dma_loadst { - S3C2410_DMALOAD_NONE, - S3C2410_DMALOAD_1LOADED, - S3C2410_DMALOAD_1RUNNING, - S3C2410_DMALOAD_1LOADED_1RUNNING, -}; - - -/* flags */ - -#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about - * waiting for reloads */ -#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ - -#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */ - -/* dma buffer */ - -struct s3c2410_dma_buf; - -/* s3c2410_dma_buf - * - * internally used buffer structure to describe a queued or running - * buffer. -*/ - -struct s3c2410_dma_buf { - struct s3c2410_dma_buf *next; - int magic; /* magic */ - int size; /* buffer size in bytes */ - dma_addr_t data; /* start of DMA data */ - dma_addr_t ptr; /* where the DMA got to [1] */ - void *id; /* client's id */ -}; - -/* [1] is this updated for both recv/send modes? */ - -struct s3c2410_dma_stats { - unsigned long loads; - unsigned long timeout_longest; - unsigned long timeout_shortest; - unsigned long timeout_avg; - unsigned long timeout_failed; -}; - -struct s3c2410_dma_map; - -/* struct s3c2410_dma_chan - * - * full state information for each DMA channel -*/ - -struct s3c2410_dma_chan { - /* channel state flags and information */ - unsigned char number; /* number of this dma channel */ - unsigned char in_use; /* channel allocated */ - unsigned char irq_claimed; /* irq claimed for channel */ - unsigned char irq_enabled; /* irq enabled for channel */ - unsigned char xfer_unit; /* size of an transfer */ - - /* channel state */ - - enum s3c2410_dma_state state; - enum s3c2410_dma_loadst load_state; - struct s3c2410_dma_client *client; - - /* channel configuration */ - enum dma_data_direction source; - enum dma_ch req_ch; - unsigned long dev_addr; - unsigned long load_timeout; - unsigned int flags; /* channel flags */ - - struct s3c24xx_dma_map *map; /* channel hw maps */ - - /* channel's hardware position and configuration */ - void __iomem *regs; /* channels registers */ - void __iomem *addr_reg; /* data address register */ - unsigned int irq; /* channel irq */ - unsigned long dcon; /* default value of DCON */ - - /* driver handles */ - s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ - s3c2410_dma_opfn_t op_fn; /* channel op callback */ - - /* stats gathering */ - struct s3c2410_dma_stats *stats; - struct s3c2410_dma_stats stats_store; - - /* buffer list and information */ - struct s3c2410_dma_buf *curr; /* current dma buffer */ - struct s3c2410_dma_buf *next; /* next buffer to load */ - struct s3c2410_dma_buf *end; /* end of queue */ - - /* system device */ - struct device dev; -}; - -typedef unsigned long dma_device_t; - -#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c2410/include/mach/entry-macro.S deleted file mode 100644 index 473b3cd37d9..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/entry-macro.S +++ /dev/null @@ -1,78 +0,0 @@ -/* - * arch/arm/mach-s3c2410/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for S3C2410-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. -*/ - -/* We have a problem that the INTOFFSET register does not always - * show one interrupt. Occasionally we get two interrupts through - * the prioritiser, and this causes the INTOFFSET register to show - * what looks like the logical-or of the two interrupt numbers. - * - * Thanks to Klaus, Shannon, et al for helping to debug this problem -*/ - -#define INTPND (0x10) -#define INTOFFSET (0x14) - -#include <mach/hardware.h> -#include <asm/irq.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #S3C24XX_VA_IRQ - - @@ try the interrupt offset register, since it is there - - ldr \irqstat, [ \base, #INTPND ] - teq \irqstat, #0 - beq 1002f - ldr \irqnr, [ \base, #INTOFFSET ] - mov \tmp, #1 - tst \irqstat, \tmp, lsl \irqnr - bne 1001f - - @@ the number specified is not a valid irq, so try - @@ and work it out for ourselves - - mov \irqnr, #0 @@ start here - - @@ work out which irq (if any) we got - - movs \tmp, \irqstat, lsl#16 - addeq \irqnr, \irqnr, #16 - moveq \irqstat, \irqstat, lsr#16 - tst \irqstat, #0xff - addeq \irqnr, \irqnr, #8 - moveq \irqstat, \irqstat, lsr#8 - tst \irqstat, #0xf - addeq \irqnr, \irqnr, #4 - moveq \irqstat, \irqstat, lsr#4 - tst \irqstat, #0x3 - addeq \irqnr, \irqnr, #2 - moveq \irqstat, \irqstat, lsr#2 - tst \irqstat, #0x1 - addeq \irqnr, \irqnr, #1 - - @@ we have the value -1001: - adds \irqnr, \irqnr, #IRQ_EINT0 -1002: - @@ exit here, Z flag unset if IRQ - - .endm - - /* currently don't need an disable_fiq macro */ - - .macro disable_fiq - .endm diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c2410/include/mach/fb.h deleted file mode 100644 index a957bc8ed44..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/fb.h +++ /dev/null @@ -1 +0,0 @@ -#include <plat/fb-s3c2410.h> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h deleted file mode 100644 index c53ad34c657..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ /dev/null @@ -1 +0,0 @@ -#include <plat/gpio-fns.h> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h deleted file mode 100644 index 019ea86057f..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ /dev/null @@ -1,118 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - GPIO bank numbering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __MACH_GPIONRS_H -#define __MACH_GPIONRS_H - -#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) - -#define S3C2410_GPIO_BANKG (32*6) -#define S3C2410_GPIO_BANKH (32*7) - -/* GPIO sizes for various SoCs: - * - * 2442 - * 2410 2412 2440 2443 2416 - * ---- ---- ---- ---- ---- - * A 23 22 25 16 25 - * B 11 11 11 11 9 - * C 16 15 16 16 16 - * D 16 16 16 16 16 - * E 16 16 16 16 16 - * F 8 8 8 8 8 - * G 16 16 16 16 8 - * H 11 11 9 15 15 - * J -- -- 13 16 -- - * K -- -- -- -- 16 - * L -- -- -- 15 7 - * M -- -- -- 2 2 - */ - -/* GPIO bank sizes */ -#define S3C2410_GPIO_A_NR (32) -#define S3C2410_GPIO_B_NR (32) -#define S3C2410_GPIO_C_NR (32) -#define S3C2410_GPIO_D_NR (32) -#define S3C2410_GPIO_E_NR (32) -#define S3C2410_GPIO_F_NR (32) -#define S3C2410_GPIO_G_NR (32) -#define S3C2410_GPIO_H_NR (32) -#define S3C2410_GPIO_J_NR (32) /* technically 16. */ -#define S3C2410_GPIO_K_NR (32) /* technically 16. */ -#define S3C2410_GPIO_L_NR (32) /* technically 15. */ -#define S3C2410_GPIO_M_NR (32) /* technically 2. */ - -#if CONFIG_S3C_GPIO_SPACE != 0 -#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment -#endif - -#define S3C2410_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) - -#ifndef __ASSEMBLY__ - -enum s3c_gpio_number { - S3C2410_GPIO_A_START = 0, - S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), - S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), - S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), - S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), - S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), - S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), - S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), - S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), - S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), - S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), - S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), -}; - -#endif /* __ASSEMBLY__ */ - -/* S3C2410 GPIO number definitions. */ - -#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) -#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) -#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) -#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) -#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) -#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) -#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) -#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) -#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) -#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) -#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) -#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) - -/* compatibility until drivers can be modified */ - -#define S3C2410_GPA0 S3C2410_GPA(0) -#define S3C2410_GPA1 S3C2410_GPA(1) -#define S3C2410_GPA3 S3C2410_GPA(3) -#define S3C2410_GPA7 S3C2410_GPA(7) - -#define S3C2410_GPE0 S3C2410_GPE(0) -#define S3C2410_GPE1 S3C2410_GPE(1) -#define S3C2410_GPE2 S3C2410_GPE(2) -#define S3C2410_GPE3 S3C2410_GPE(3) -#define S3C2410_GPE4 S3C2410_GPE(4) -#define S3C2410_GPE5 S3C2410_GPE(5) -#define S3C2410_GPE6 S3C2410_GPE(6) -#define S3C2410_GPE7 S3C2410_GPE(7) -#define S3C2410_GPE8 S3C2410_GPE(8) -#define S3C2410_GPE9 S3C2410_GPE(9) -#define S3C2410_GPE10 S3C2410_GPE(10) - -#define S3C2410_GPH10 S3C2410_GPH(10) - -#endif /* __MACH_GPIONRS_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h deleted file mode 100644 index c410a078622..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h +++ /dev/null @@ -1,33 +0,0 @@ -/* arch/arm/mach-s3c24100/include/mach/gpio-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C2410 - GPIO core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -#include <mach/regs-gpio.h> - -extern struct samsung_gpio_chip s3c24xx_gpios[]; - -static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) -{ - struct samsung_gpio_chip *chip; - - if (pin > S3C_GPIO_END) - return NULL; - - chip = &s3c24xx_gpios[pin/32]; - return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; -} - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h deleted file mode 100644 index 6fac70f3484..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ /dev/null @@ -1,35 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - GPIO lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* some boards require extra gpio capacity to support external - * devices that need GPIO. - */ - -#ifdef CONFIG_CPU_S3C244X -#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA) -#else -#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) -#endif - -#include <mach/gpio-nrs.h> -#include <mach/gpio-fns.h> - -#ifdef CONFIG_CPU_S3C244X -#define S3C_GPIO_END (S3C2410_GPJ(0) + 32) -#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define S3C_GPIO_END (S3C2410_GPM(0) + 32) -#else -#define S3C_GPIO_END (S3C2410_GPH(0) + 32) -#endif diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h deleted file mode 100644 index fc897d3a056..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h +++ /dev/null @@ -1,43 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h - * - * Copyright (c) 2005 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * iPAQ H1940 series - latch definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_H1940_LATCH_H -#define __ASM_ARCH_H1940_LATCH_H - -#include <asm/gpio.h> - -#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x)) - -/* SD layer latch */ - -#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0) -#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1) -#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2) -#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3) -#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4) -#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5) -#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6) -#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7) - -/* CPU layer latch */ - -#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8) -#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9) -#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10) -#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11) -#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12) -#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13) -#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14) -#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15) - -#endif /* __ASM_ARCH_H1940_LATCH_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c2410/include/mach/h1940.h deleted file mode 100644 index 2aa683c8d3d..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/h1940.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/h1940.h - * - * Copyright 2006 Ben Dooks <ben-linux@fluff.org> - * - * H1940 definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_H1940_H -#define __ASM_ARCH_H1940_H - -#define H1940_SUSPEND_CHECKSUM (0x30003ff8) -#define H1940_SUSPEND_RESUMEAT (0x30081000) -#define H1940_SUSPEND_CHECK (0x30080000) - -extern void h1940_pm_return(void); -extern int h1940_led_blink_set(unsigned gpio, int state, - unsigned long *delay_on, unsigned long *delay_off); - - -#endif /* __ASM_ARCH_H1940_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h deleted file mode 100644 index aef5631eac5..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/hardware.h +++ /dev/null @@ -1,42 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/hardware.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - hardware - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ - -extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); - -#ifdef CONFIG_CPU_S3C2440 - -extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); - -#endif /* CONFIG_CPU_S3C2440 */ - -#ifdef CONFIG_CPU_S3C2412 - -extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state); - -#endif /* CONFIG_CPU_S3C2412 */ - -#endif /* __ASSEMBLY__ */ - -#include <asm/sizes.h> -#include <mach/map.h> - -/* machine specific hardware definitions should go after this */ - -/* currently here until moved into config (todo) */ -#define CONFIG_NO_MULTIWORD_IO - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c2410/include/mach/idle.h deleted file mode 100644 index e9ddd706b16..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/idle.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/idle.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 CPU Idle controls -*/ - -#ifndef __ASM_ARCH_IDLE_H -#define __ASM_ARCH_IDLE_H __FILE__ - -/* This allows the over-ride of the default idle code, in case there - * is any other things to be done over idle (like DVS) -*/ - -extern void (*s3c24xx_idle)(void); - -extern void s3c24xx_default_idle(void); - -#endif /* __ASM_ARCH_IDLE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h deleted file mode 100644 index 118749f37c4..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/io.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28 - * and are translated to the start of IO. Note that all addresses are - * not shifted left! - */ - -#define __PORT_PCIO(x) ((x) < (1<<28)) - -#define PCIO_BASE (S3C24XX_VA_ISA_WORD) -#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE) -#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD) -#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD) -/* - * Dynamic IO functions - let the compiler - * optimize the expressions - */ - -#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \ -static inline void __out##fnsuffix (unsigned int val, unsigned int port) \ -{ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "cmp %2, #(1<<28)\n\t" \ - "mov %0, %2\n\t" \ - "addcc %0, %0, %3\n\t" \ - "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \ - : "=&r" (temp) \ - : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ - : "cc"); \ -} - - -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "cmp %2, #(1<<28)\n\t" \ - "mov %0, %2\n\t" \ - "addcc %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ - : "cc"); \ - return (unsigned sz)value; \ -} - -static inline void __iomem *__ioaddr (unsigned long port) -{ - return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port; -} - -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) \ - DECLARE_DYN_OUT(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"h") -DECLARE_IO(int,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions - * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. - */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, #0] @ outbc" \ - : : "r" (value), "r" ((port))); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, #0] @ inbc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) { \ - if ((port) < 256 && (port) > -256) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ - else if ((port) > 0) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v), \ - "r" (PCIO_BASE + ((port) & ~0xff)), \ - "Jr" (((port) & 0xff))); \ - else \ - __asm__ __volatile__( \ - "strh %0, [%1, #0] @ outwc" \ - : : "r" (v), \ - "r" (PCIO_BASE + (port))); \ - } else \ - __asm__ __volatile__( \ - "strh %0, [%1, #0] @ outwc" \ - : : "r" (v), "r" ((port))); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) { \ - if ((port) < 256 && (port) > -256 ) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE), \ - "Jr" ((port))); \ - else if ((port) > 0) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE + ((port) & ~0xff)), \ - "Jr" (((port) & 0xff))); \ - else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, #0] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE + ((port)))); \ - } else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, #0] @ inwc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, #0] @ outlc" \ - : : "r" (v), "r" ((port))); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, #0] @ inlc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port))) - -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) -#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) - -#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) -#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l) - -#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) -#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l) - -/* - * 1:1 mapping for ioremapped regions. - */ -#define __mem_pci(x) (x) - -#endif diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h deleted file mode 100644 index e53b2177319..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ /dev/null @@ -1,202 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/irqs.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -/* we keep the first set of CPU IRQs out of the range of - * the ISA space, so that the PC104 has them to itself - * and we don't end up having to do horrible things to the - * standard ISA drivers.... - */ - -#define S3C2410_CPUIRQ_OFFSET (16) - -#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) - -/* main cpu interrupts */ -#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ -#define IRQ_EINT1 S3C2410_IRQ(1) -#define IRQ_EINT2 S3C2410_IRQ(2) -#define IRQ_EINT3 S3C2410_IRQ(3) -#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ -#define IRQ_EINT8t23 S3C2410_IRQ(5) -#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ -#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ -#define IRQ_BATT_FLT S3C2410_IRQ(7) -#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ -#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ -#define IRQ_TIMER0 S3C2410_IRQ(10) -#define IRQ_TIMER1 S3C2410_IRQ(11) -#define IRQ_TIMER2 S3C2410_IRQ(12) -#define IRQ_TIMER3 S3C2410_IRQ(13) -#define IRQ_TIMER4 S3C2410_IRQ(14) -#define IRQ_UART2 S3C2410_IRQ(15) -#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ -#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ -#define IRQ_DMA1 S3C2410_IRQ(18) -#define IRQ_DMA2 S3C2410_IRQ(19) -#define IRQ_DMA3 S3C2410_IRQ(20) -#define IRQ_SDI S3C2410_IRQ(21) -#define IRQ_SPI0 S3C2410_IRQ(22) -#define IRQ_UART1 S3C2410_IRQ(23) -#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ -#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ -#define IRQ_USBD S3C2410_IRQ(25) -#define IRQ_USBH S3C2410_IRQ(26) -#define IRQ_IIC S3C2410_IRQ(27) -#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ -#define IRQ_SPI1 S3C2410_IRQ(29) -#define IRQ_RTC S3C2410_IRQ(30) -#define IRQ_ADCPARENT S3C2410_IRQ(31) - -/* interrupts generated from the external interrupts sources */ -#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ -#define IRQ_EINT5 S3C2410_IRQ(33) -#define IRQ_EINT6 S3C2410_IRQ(34) -#define IRQ_EINT7 S3C2410_IRQ(35) -#define IRQ_EINT8 S3C2410_IRQ(36) -#define IRQ_EINT9 S3C2410_IRQ(37) -#define IRQ_EINT10 S3C2410_IRQ(38) -#define IRQ_EINT11 S3C2410_IRQ(39) -#define IRQ_EINT12 S3C2410_IRQ(40) -#define IRQ_EINT13 S3C2410_IRQ(41) -#define IRQ_EINT14 S3C2410_IRQ(42) -#define IRQ_EINT15 S3C2410_IRQ(43) -#define IRQ_EINT16 S3C2410_IRQ(44) -#define IRQ_EINT17 S3C2410_IRQ(45) -#define IRQ_EINT18 S3C2410_IRQ(46) -#define IRQ_EINT19 S3C2410_IRQ(47) -#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ -#define IRQ_EINT21 S3C2410_IRQ(49) -#define IRQ_EINT22 S3C2410_IRQ(50) -#define IRQ_EINT23 S3C2410_IRQ(51) - -#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) -#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) - -#define IRQ_LCD_FIFO S3C2410_IRQ(52) -#define IRQ_LCD_FRAME S3C2410_IRQ(53) - -/* IRQs for the interal UARTs, and ADC - * these need to be ordered in number of appearance in the - * SUBSRC mask register -*/ - -#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) - -#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ -#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) -#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) - -#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ -#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) -#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) - -#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ -#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) -#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) - -#define IRQ_TC S3C2410_IRQSUB(9) -#define IRQ_ADC S3C2410_IRQSUB(10) - -/* extra irqs for s3c2412 */ - -#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) - -#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) -#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) - - -#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5) -#define IRQ_S3C2416_DMA S3C2410_IRQ(17) -#define IRQ_S3C2416_UART3 S3C2410_IRQ(18) -#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20) -#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21) - -#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17) -#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23) -#define IRQ_S32416_WDT S3C2410_IRQSUB(27) -#define IRQ_S32416_AC97 S3C2410_IRQSUB(28) - - -/* extra irqs for s3c2440 */ - -#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ -#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ -#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) -#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) - -/* irqs for s3c2443 */ - -#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ -#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ -#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ -#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ -#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ - -#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */ - -#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0 -#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC - -#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) -#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) -#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) -#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) - -#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) -#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) -#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) -#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) -#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) -#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) - -/* UART3 */ -#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) -#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) -#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) - -#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) -#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) - -#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) -#define NR_IRQS (IRQ_S3C2443_AC97+1) -#else -#define NR_IRQS (IRQ_S3C2440_AC97+1) -#endif - -/* compatibility define. */ -#define IRQ_UART3 IRQ_S3C2443_UART3 -#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 -#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 -#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 - -#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 -#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 - -#ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 -#else -#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 -#endif - -/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ -#define FIQ_START IRQ_EINT0 - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h deleted file mode 100644 index d8a7672519b..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h - * - * Copyright (c) 2006 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX - LEDs GPIO connector - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_LEDSGPIO_H -#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h" - -#define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */ -#define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */ - -struct s3c24xx_led_platdata { - unsigned int gpio; - unsigned int flags; - - char *name; - char *def_trigger; -}; - -#endif /* __ASM_ARCH_LEDSGPIO_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h deleted file mode 100644 index 78ae807f128..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ /dev/null @@ -1,165 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/map.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H - -#include <plat/map-base.h> - -/* - * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400. - * So need to define it, and here is to avoid redefinition warning. - */ -#define S3C_UART_OFFSET (0x4000) - -#include <plat/map-s3c.h> - -/* - * interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - -/* UARTs */ -#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) - -/* Timers */ -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* Clock and Power management */ -#define S3C24XX_SZ_CLKPWR SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M - -/* Standard size definitions for peripheral blocks. */ - -#define S3C24XX_SZ_UART SZ_1M -#define S3C24XX_SZ_IIS SZ_1M -#define S3C24XX_SZ_ADC SZ_1M -#define S3C24XX_SZ_SPI SZ_1M -#define S3C24XX_SZ_SDI SZ_1M -#define S3C24XX_SZ_NAND SZ_1M -#define S3C24XX_SZ_GPIO SZ_1M - -/* USB host controller */ -#define S3C2410_PA_USBHOST (0x49000000) - -/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ -#define S3C2416_PA_HSUDC (0x49800000) -#define S3C2416_SZ_HSUDC (SZ_4K) - -/* DMA controller */ -#define S3C2410_PA_DMA (0x4B000000) -#define S3C24XX_SZ_DMA SZ_1M - -/* Clock and Power management */ -#define S3C2410_PA_CLKPWR (0x4C000000) - -/* LCD controller */ -#define S3C2410_PA_LCD (0x4D000000) -#define S3C24XX_SZ_LCD SZ_1M - -/* NAND flash controller */ -#define S3C2410_PA_NAND (0x4E000000) - -/* IIC hardware controller */ -#define S3C2410_PA_IIC (0x54000000) - -/* IIS controller */ -#define S3C2410_PA_IIS (0x55000000) - -/* RTC */ -#define S3C2410_PA_RTC (0x57000000) -#define S3C24XX_SZ_RTC SZ_1M - -/* ADC */ -#define S3C2410_PA_ADC (0x58000000) - -/* SPI */ -#define S3C2410_PA_SPI (0x59000000) - -/* SDI */ -#define S3C2410_PA_SDI (0x5A000000) - -/* CAMIF */ -#define S3C2440_PA_CAMIF (0x4F000000) -#define S3C2440_SZ_CAMIF SZ_1M - -/* AC97 */ - -#define S3C2440_PA_AC97 (0x5B000000) -#define S3C2440_SZ_AC97 SZ_1M - -/* S3C2443/S3C2416 High-speed SD/MMC */ -#define S3C2443_PA_HSMMC (0x4A800000) -#define S3C2416_PA_HSMMC0 (0x4AC00000) - -#define S3C2443_PA_FB (0x4C800000) - -/* S3C2412 memory and IO controls */ -#define S3C2412_PA_SSMC (0x4F000000) - -#define S3C2412_PA_EBI (0x48800000) - -/* physical addresses of all the chip-select areas */ - -#define S3C2410_CS0 (0x00000000) -#define S3C2410_CS1 (0x08000000) -#define S3C2410_CS2 (0x10000000) -#define S3C2410_CS3 (0x18000000) -#define S3C2410_CS4 (0x20000000) -#define S3C2410_CS5 (0x28000000) -#define S3C2410_CS6 (0x30000000) -#define S3C2410_CS7 (0x38000000) - -#define S3C2410_SDRAM_PA (S3C2410_CS6) - -/* Use a single interface for common resources between S3C24XX cpus */ - -#define S3C24XX_PA_IRQ S3C2410_PA_IRQ -#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL -#define S3C24XX_PA_DMA S3C2410_PA_DMA -#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR -#define S3C24XX_PA_LCD S3C2410_PA_LCD -#define S3C24XX_PA_TIMER S3C2410_PA_TIMER -#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV -#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG -#define S3C24XX_PA_IIS S3C2410_PA_IIS -#define S3C24XX_PA_RTC S3C2410_PA_RTC -#define S3C24XX_PA_ADC S3C2410_PA_ADC -#define S3C24XX_PA_SPI S3C2410_PA_SPI -#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) -#define S3C24XX_PA_SDI S3C2410_PA_SDI -#define S3C24XX_PA_NAND S3C2410_PA_NAND - -#define S3C_PA_FB S3C2443_PA_FB -#define S3C_PA_IIC S3C2410_PA_IIC -#define S3C_PA_UART S3C24XX_PA_UART -#define S3C_PA_USBHOST S3C2410_PA_USBHOST -#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0 -#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC -#define S3C_PA_WDT S3C2410_PA_WATCHDOG -#define S3C_PA_NAND S3C24XX_PA_NAND - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h deleted file mode 100644 index e9e36b0abba..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h - * - * Copyright 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * OSIRIS - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_OSIRISCPLD_H -#define __ASM_ARCH_OSIRISCPLD_H - -/* CTRL0 - NAND WP control */ - -#define OSIRIS_CTRL0_NANDSEL (0x3) -#define OSIRIS_CTRL0_BOOT_INT (1<<3) -#define OSIRIS_CTRL0_PCMCIA (1<<4) -#define OSIRIS_CTRL0_FIX8 (1<<5) -#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) -#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) - -#define OSIRIS_CTRL1_FIX8 (1<<0) - -#define OSIRIS_ID_REVMASK (0x7) - -#endif /* __ASM_ARCH_OSIRISCPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h deleted file mode 100644 index 17380f84842..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h +++ /dev/null @@ -1,42 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/osiris-map.h - * - * Copyright 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * OSIRIS - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -#ifndef __ASM_ARCH_OSIRISMAP_H -#define __ASM_ARCH_OSIRISMAP_H - -/* start peripherals off after the S3C2410 */ - -#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000)) - -#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) -#define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) - -#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) -#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) - -#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) -#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) - -#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) -#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) - -#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) -#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) - -#endif /* __ASM_ARCH_OSIRISMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c2410/include/mach/otom-map.h deleted file mode 100644 index f9277a52c14..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/otom-map.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/otom-map.h - * - * (c) 2005 Guillaume GOURAT / NexVision - * guillaume.gourat@nexvision.fr - * - * NexVision OTOM board memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x01300000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. - */ - -#ifndef __ASM_ARCH_OTOMMAP_H -#define __ASM_ARCH_OTOMMAP_H - -#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */ -#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */ - -/* physical offset addresses for the peripherals */ - -#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */ - -#endif /* __ASM_ARCH_OTOMMAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h deleted file mode 100644 index 2eef7e6f767..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/pm-core.h +++ /dev/null @@ -1,67 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/include/pm-core.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -static inline void s3c_pm_debug_init_uart(void) -{ - unsigned long tmp = __raw_readl(S3C2410_CLKCON); - - /* re-start uart clocks */ - tmp |= S3C2410_CLKCON_UART0; - tmp |= S3C2410_CLKCON_UART1; - tmp |= S3C2410_CLKCON_UART2; - - __raw_writel(tmp, S3C2410_CLKCON); - udelay(10); -} - -static inline void s3c_pm_arch_prepare_irqs(void) -{ - __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); - __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); - - /* ack any outstanding external interrupts before we go to sleep */ - - __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); - __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); - __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - -} - -static inline void s3c_pm_arch_stop_clocks(void) -{ - __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ -} - -static void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask); - -static inline void s3c_pm_arch_show_resume_irqs(void) -{ - S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", - __raw_readl(S3C2410_SRCPND), - __raw_readl(S3C2410_EINTPEND)); - - s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), - s3c_irqwake_intmask); - - s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), - s3c_irqwake_eintmask); -} - -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ -} - -static inline void s3c_pm_restored_gpios(void) { } -static inline void samsung_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h deleted file mode 100644 index 3415b60082d..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h +++ /dev/null @@ -1,166 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-clock.h - * - * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 clock register definitions -*/ - -#ifndef __ASM_ARM_REGS_CLOCK -#define __ASM_ARM_REGS_CLOCK - -#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) - -#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) -#define S3C2410_MPLLCON S3C2410_CLKREG(0x04) -#define S3C2410_UPLLCON S3C2410_CLKREG(0x08) -#define S3C2410_CLKCON S3C2410_CLKREG(0x0C) -#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) -#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) - -#define S3C2410_CLKCON_IDLE (1<<2) -#define S3C2410_CLKCON_POWER (1<<3) -#define S3C2410_CLKCON_NAND (1<<4) -#define S3C2410_CLKCON_LCDC (1<<5) -#define S3C2410_CLKCON_USBH (1<<6) -#define S3C2410_CLKCON_USBD (1<<7) -#define S3C2410_CLKCON_PWMT (1<<8) -#define S3C2410_CLKCON_SDI (1<<9) -#define S3C2410_CLKCON_UART0 (1<<10) -#define S3C2410_CLKCON_UART1 (1<<11) -#define S3C2410_CLKCON_UART2 (1<<12) -#define S3C2410_CLKCON_GPIO (1<<13) -#define S3C2410_CLKCON_RTC (1<<14) -#define S3C2410_CLKCON_ADC (1<<15) -#define S3C2410_CLKCON_IIC (1<<16) -#define S3C2410_CLKCON_IIS (1<<17) -#define S3C2410_CLKCON_SPI (1<<18) - -/* DCLKCON register addresses in gpio.h */ - -#define S3C2410_DCLKCON_DCLK0EN (1<<0) -#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1) -#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) -#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) -#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) -#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) -#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) - -#define S3C2410_DCLKCON_DCLK1EN (1<<16) -#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) -#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) -#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) -#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) -#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) -#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) - -#define S3C2410_CLKDIVN_PDIVN (1<<0) -#define S3C2410_CLKDIVN_HDIVN (1<<1) - -#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) -#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) -#define S3C2410_CLKSLOW_SLOW (1<<4) -#define S3C2410_CLKSLOW_SLOWVAL(x) (x) -#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) - -/* extra registers */ -#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) - -#define S3C2440_CLKCON_CAMERA (1<<19) -#define S3C2440_CLKCON_AC97 (1<<20) - -#define S3C2440_CLKDIVN_PDIVN (1<<0) -#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) -#define S3C2440_CLKDIVN_HDIVN_1 (0<<1) -#define S3C2440_CLKDIVN_HDIVN_2 (1<<1) -#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) -#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) -#define S3C2440_CLKDIVN_UCLK (1<<3) - -#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) -#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) -#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) -#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) -#define S3C2440_CAMDIVN_DVSEN (1<<12) - -#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) - -#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ - -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) - -#define S3C2412_OSCSET S3C2410_CLKREG(0x18) -#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) - -#define S3C2412_PLLCON_OFF (1<<20) - -#define S3C2412_CLKDIVN_PDIVN (1<<2) -#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) -#define S3C2412_CLKDIVN_ARMDIVN (1<<3) -#define S3C2412_CLKDIVN_DVSEN (1<<4) -#define S3C2412_CLKDIVN_HALFHCLK (1<<5) -#define S3C2412_CLKDIVN_USB48DIV (1<<6) -#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) -#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) -#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) -#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) -#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) -#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) - -#define S3C2412_CLKCON_WDT (1<<28) -#define S3C2412_CLKCON_SPI (1<<27) -#define S3C2412_CLKCON_IIS (1<<26) -#define S3C2412_CLKCON_IIC (1<<25) -#define S3C2412_CLKCON_ADC (1<<24) -#define S3C2412_CLKCON_RTC (1<<23) -#define S3C2412_CLKCON_GPIO (1<<22) -#define S3C2412_CLKCON_UART2 (1<<21) -#define S3C2412_CLKCON_UART1 (1<<20) -#define S3C2412_CLKCON_UART0 (1<<19) -#define S3C2412_CLKCON_SDI (1<<18) -#define S3C2412_CLKCON_PWMT (1<<17) -#define S3C2412_CLKCON_USBD (1<<16) -#define S3C2412_CLKCON_CAMCLK (1<<15) -#define S3C2412_CLKCON_UARTCLK (1<<14) -/* missing 13 */ -#define S3C2412_CLKCON_USB_HOST48 (1<<12) -#define S3C2412_CLKCON_USB_DEV48 (1<<11) -#define S3C2412_CLKCON_HCLKdiv2 (1<<10) -#define S3C2412_CLKCON_HCLKx2 (1<<9) -#define S3C2412_CLKCON_SDRAM (1<<8) -/* missing 7 */ -#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH -#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC -#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND -#define S3C2412_CLKCON_DMA3 (1<<3) -#define S3C2412_CLKCON_DMA2 (1<<2) -#define S3C2412_CLKCON_DMA1 (1<<1) -#define S3C2412_CLKCON_DMA0 (1<<0) - -/* clock sourec controls */ - -#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) -#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) -#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) -#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) -#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) -#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) -#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) -#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) -#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) -#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) -#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) - -#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ - -#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28) - -#endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h deleted file mode 100644 index 98fd4a05587..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h +++ /dev/null @@ -1,220 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2440/S3C2412 Signal Drive Strength Control -*/ - - -#ifndef __ASM_ARCH_REGS_DSC_H -#define __ASM_ARCH_REGS_DSC_H "2440-dsc" - -#if defined(CONFIG_CPU_S3C2412) -#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) -#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) -#endif - -#if defined(CONFIG_CPU_S3C2416) -#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) -#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) -#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) -#define S3C2416_DSC3 S3C2410_GPIOREG(0x110) - -#define S3C2416_SELECT_DSC0 (0 << 30) -#define S3C2416_SELECT_DSC1 (1 << 30) -#define S3C2416_SELECT_DSC2 (2 << 30) -#define S3C2416_SELECT_DSC3 (3 << 30) - -#define S3C2416_DSC_GETSHIFT(x) (x & 30) - -#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) -#define S3C2416_DSC0_CF_5mA (0 << 28) -#define S3C2416_DSC0_CF_10mA (1 << 28) -#define S3C2416_DSC0_CF_15mA (2 << 28) -#define S3C2416_DSC0_CF_21mA (3 << 28) -#define S3C2416_DSC0_CF_MASK (3 << 28) - -#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) -#define S3C2416_DSC0_nRBE_5mA (0 << 26) -#define S3C2416_DSC0_nRBE_10mA (1 << 26) -#define S3C2416_DSC0_nRBE_15mA (2 << 26) -#define S3C2416_DSC0_nRBE_21mA (3 << 26) -#define S3C2416_DSC0_nRBE_MASK (3 << 26) - -#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) -#define S3C2416_DSC0_nROE_5mA (0 << 24) -#define S3C2416_DSC0_nROE_10mA (1 << 24) -#define S3C2416_DSC0_nROE_15mA (2 << 24) -#define S3C2416_DSC0_nROE_21mA (3 << 24) -#define S3C2416_DSC0_nROE_MASK (3 << 24) - -#endif - -#if defined(CONFIG_CPU_S3C244X) - -#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) -#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) - -#define S3C2440_SELECT_DSC0 (0) -#define S3C2440_SELECT_DSC1 (1<<31) - -#define S3C2440_DSC_GETSHIFT(x) ((x) & 31) - -#define S3C2440_DSC0_DISABLE (1<<31) - -#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) -#define S3C2440_DSC0_ADDR_12mA (0<<8) -#define S3C2440_DSC0_ADDR_10mA (1<<8) -#define S3C2440_DSC0_ADDR_8mA (2<<8) -#define S3C2440_DSC0_ADDR_6mA (3<<8) -#define S3C2440_DSC0_ADDR_MASK (3<<8) - -/* D24..D31 */ -#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) -#define S3C2440_DSC0_DATA3_12mA (0<<6) -#define S3C2440_DSC0_DATA3_10mA (1<<6) -#define S3C2440_DSC0_DATA3_8mA (2<<6) -#define S3C2440_DSC0_DATA3_6mA (3<<6) -#define S3C2440_DSC0_DATA3_MASK (3<<6) - -/* D16..D23 */ -#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) -#define S3C2440_DSC0_DATA2_12mA (0<<4) -#define S3C2440_DSC0_DATA2_10mA (1<<4) -#define S3C2440_DSC0_DATA2_8mA (2<<4) -#define S3C2440_DSC0_DATA2_6mA (3<<4) -#define S3C2440_DSC0_DATA2_MASK (3<<4) - -/* D8..D15 */ -#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) -#define S3C2440_DSC0_DATA1_12mA (0<<2) -#define S3C2440_DSC0_DATA1_10mA (1<<2) -#define S3C2440_DSC0_DATA1_8mA (2<<2) -#define S3C2440_DSC0_DATA1_6mA (3<<2) -#define S3C2440_DSC0_DATA1_MASK (3<<2) - -/* D0..D7 */ -#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) -#define S3C2440_DSC0_DATA0_12mA (0<<0) -#define S3C2440_DSC0_DATA0_10mA (1<<0) -#define S3C2440_DSC0_DATA0_8mA (2<<0) -#define S3C2440_DSC0_DATA0_6mA (3<<0) -#define S3C2440_DSC0_DATA0_MASK (3<<0) - -#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) -#define S3C2440_DSC1_SCK1_12mA (0<<28) -#define S3C2440_DSC1_SCK1_10mA (1<<28) -#define S3C2440_DSC1_SCK1_8mA (2<<28) -#define S3C2440_DSC1_SCK1_6mA (3<<28) -#define S3C2440_DSC1_SCK1_MASK (3<<28) - -#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) -#define S3C2440_DSC1_SCK0_12mA (0<<26) -#define S3C2440_DSC1_SCK0_10mA (1<<26) -#define S3C2440_DSC1_SCK0_8mA (2<<26) -#define S3C2440_DSC1_SCK0_6mA (3<<26) -#define S3C2440_DSC1_SCK0_MASK (3<<26) - -#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) -#define S3C2440_DSC1_SCKE_10mA (0<<24) -#define S3C2440_DSC1_SCKE_8mA (1<<24) -#define S3C2440_DSC1_SCKE_6mA (2<<24) -#define S3C2440_DSC1_SCKE_4mA (3<<24) -#define S3C2440_DSC1_SCKE_MASK (3<<24) - -/* SDRAM nRAS/nCAS */ -#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) -#define S3C2440_DSC1_SDR_10mA (0<<22) -#define S3C2440_DSC1_SDR_8mA (1<<22) -#define S3C2440_DSC1_SDR_6mA (2<<22) -#define S3C2440_DSC1_SDR_4mA (3<<22) -#define S3C2440_DSC1_SDR_MASK (3<<22) - -/* NAND Flash Controller */ -#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) -#define S3C2440_DSC1_NFC_10mA (0<<20) -#define S3C2440_DSC1_NFC_8mA (1<<20) -#define S3C2440_DSC1_NFC_6mA (2<<20) -#define S3C2440_DSC1_NFC_4mA (3<<20) -#define S3C2440_DSC1_NFC_MASK (3<<20) - -/* nBE[0..3] */ -#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) -#define S3C2440_DSC1_nBE_10mA (0<<18) -#define S3C2440_DSC1_nBE_8mA (1<<18) -#define S3C2440_DSC1_nBE_6mA (2<<18) -#define S3C2440_DSC1_nBE_4mA (3<<18) -#define S3C2440_DSC1_nBE_MASK (3<<18) - -#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) -#define S3C2440_DSC1_WOE_10mA (0<<16) -#define S3C2440_DSC1_WOE_8mA (1<<16) -#define S3C2440_DSC1_WOE_6mA (2<<16) -#define S3C2440_DSC1_WOE_4mA (3<<16) -#define S3C2440_DSC1_WOE_MASK (3<<16) - -#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) -#define S3C2440_DSC1_CS7_10mA (0<<14) -#define S3C2440_DSC1_CS7_8mA (1<<14) -#define S3C2440_DSC1_CS7_6mA (2<<14) -#define S3C2440_DSC1_CS7_4mA (3<<14) -#define S3C2440_DSC1_CS7_MASK (3<<14) - -#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) -#define S3C2440_DSC1_CS6_10mA (0<<12) -#define S3C2440_DSC1_CS6_8mA (1<<12) -#define S3C2440_DSC1_CS6_6mA (2<<12) -#define S3C2440_DSC1_CS6_4mA (3<<12) -#define S3C2440_DSC1_CS6_MASK (3<<12) - -#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) -#define S3C2440_DSC1_CS5_10mA (0<<10) -#define S3C2440_DSC1_CS5_8mA (1<<10) -#define S3C2440_DSC1_CS5_6mA (2<<10) -#define S3C2440_DSC1_CS5_4mA (3<<10) -#define S3C2440_DSC1_CS5_MASK (3<<10) - -#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) -#define S3C2440_DSC1_CS4_10mA (0<<8) -#define S3C2440_DSC1_CS4_8mA (1<<8) -#define S3C2440_DSC1_CS4_6mA (2<<8) -#define S3C2440_DSC1_CS4_4mA (3<<8) -#define S3C2440_DSC1_CS4_MASK (3<<8) - -#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) -#define S3C2440_DSC1_CS3_10mA (0<<6) -#define S3C2440_DSC1_CS3_8mA (1<<6) -#define S3C2440_DSC1_CS3_6mA (2<<6) -#define S3C2440_DSC1_CS3_4mA (3<<6) -#define S3C2440_DSC1_CS3_MASK (3<<6) - -#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) -#define S3C2440_DSC1_CS2_10mA (0<<4) -#define S3C2440_DSC1_CS2_8mA (1<<4) -#define S3C2440_DSC1_CS2_6mA (2<<4) -#define S3C2440_DSC1_CS2_4mA (3<<4) -#define S3C2440_DSC1_CS2_MASK (3<<4) - -#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) -#define S3C2440_DSC1_CS1_10mA (0<<2) -#define S3C2440_DSC1_CS1_8mA (1<<2) -#define S3C2440_DSC1_CS1_6mA (2<<2) -#define S3C2440_DSC1_CS1_4mA (3<<2) -#define S3C2440_DSC1_CS1_MASK (3<<2) - -#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) -#define S3C2440_DSC1_CS0_10mA (0<<0) -#define S3C2440_DSC1_CS0_8mA (1<<0) -#define S3C2440_DSC1_CS0_6mA (2<<0) -#define S3C2440_DSC1_CS0_4mA (3<<0) -#define S3C2440_DSC1_CS0_MASK (3<<0) - -#endif /* CONFIG_CPU_S3C2440 */ - -#endif /* __ASM_ARCH_REGS_DSC_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h deleted file mode 100644 index cac1ad6b582..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ /dev/null @@ -1,602 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h - * - * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 GPIO register definitions -*/ - - -#ifndef __ASM_ARCH_REGS_GPIO_H -#define __ASM_ARCH_REGS_GPIO_H - -#include <mach/gpio-nrs.h> - -#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) - -/* general configuration options */ - -#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) -#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ -#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) -#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ -#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ -#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ - -/* register address for the GPIO registers. - * S3C24XX_GPIOREG2 is for the second set of registers in the - * GPIO which move between s3c2410 and s3c2412 type systems */ - -#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) - - -/* configure GPIO ports A..G */ - -/* port A - S3C2410: 22bits, zero in bit X makes pin X output - * 1 makes port special function, this is default -*/ -#define S3C2410_GPACON S3C2410_GPIOREG(0x00) -#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) - -#define S3C2410_GPA0_ADDR0 (1<<0) -#define S3C2410_GPA1_ADDR16 (1<<1) -#define S3C2410_GPA2_ADDR17 (1<<2) -#define S3C2410_GPA3_ADDR18 (1<<3) -#define S3C2410_GPA4_ADDR19 (1<<4) -#define S3C2410_GPA5_ADDR20 (1<<5) -#define S3C2410_GPA6_ADDR21 (1<<6) -#define S3C2410_GPA7_ADDR22 (1<<7) -#define S3C2410_GPA8_ADDR23 (1<<8) -#define S3C2410_GPA9_ADDR24 (1<<9) -#define S3C2410_GPA10_ADDR25 (1<<10) -#define S3C2410_GPA11_ADDR26 (1<<11) -#define S3C2410_GPA12_nGCS1 (1<<12) -#define S3C2410_GPA13_nGCS2 (1<<13) -#define S3C2410_GPA14_nGCS3 (1<<14) -#define S3C2410_GPA15_nGCS4 (1<<15) -#define S3C2410_GPA16_nGCS5 (1<<16) -#define S3C2410_GPA17_CLE (1<<17) -#define S3C2410_GPA18_ALE (1<<18) -#define S3C2410_GPA19_nFWE (1<<19) -#define S3C2410_GPA20_nFRE (1<<20) -#define S3C2410_GPA21_nRSTOUT (1<<21) -#define S3C2410_GPA22_nFCE (1<<22) - -/* 0x08 and 0x0c are reserved on S3C2410 */ - -/* S3C2410: - * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. - * 00 = input, 01 = output, 10=special function, 11=reserved - - * bit 0,1 = pin 0, 2,3= pin 1... - * - * CPBUP = pull up resistor control, 1=disabled, 0=enabled -*/ - -#define S3C2410_GPBCON S3C2410_GPIOREG(0x10) -#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) -#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) - -/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ - -#define S3C2410_GPB0_TOUT0 (0x02 << 0) - -#define S3C2410_GPB1_TOUT1 (0x02 << 2) - -#define S3C2410_GPB2_TOUT2 (0x02 << 4) - -#define S3C2410_GPB3_TOUT3 (0x02 << 6) - -#define S3C2410_GPB4_TCLK0 (0x02 << 8) -#define S3C2410_GPB4_MASK (0x03 << 8) - -#define S3C2410_GPB5_nXBACK (0x02 << 10) -#define S3C2443_GPB5_XBACK (0x03 << 10) - -#define S3C2410_GPB6_nXBREQ (0x02 << 12) -#define S3C2443_GPB6_XBREQ (0x03 << 12) - -#define S3C2410_GPB7_nXDACK1 (0x02 << 14) -#define S3C2443_GPB7_XDACK1 (0x03 << 14) - -#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) - -#define S3C2410_GPB9_nXDACK0 (0x02 << 18) -#define S3C2443_GPB9_XDACK0 (0x03 << 18) - -#define S3C2410_GPB10_nXDRE0 (0x02 << 20) -#define S3C2443_GPB10_XDREQ0 (0x03 << 20) - -#define S3C2410_GPB_PUPDIS(x) (1<<(x)) - -/* Port C consits of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's sync/etc. -*/ - -#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) -#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) -#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) -#define S3C2410_GPC0_LEND (0x02 << 0) -#define S3C2410_GPC1_VCLK (0x02 << 2) -#define S3C2410_GPC2_VLINE (0x02 << 4) -#define S3C2410_GPC3_VFRAME (0x02 << 6) -#define S3C2410_GPC4_VM (0x02 << 8) -#define S3C2410_GPC5_LCDVF0 (0x02 << 10) -#define S3C2410_GPC6_LCDVF1 (0x02 << 12) -#define S3C2410_GPC7_LCDVF2 (0x02 << 14) -#define S3C2410_GPC8_VD0 (0x02 << 16) -#define S3C2410_GPC9_VD1 (0x02 << 18) -#define S3C2410_GPC10_VD2 (0x02 << 20) -#define S3C2410_GPC11_VD3 (0x02 << 22) -#define S3C2410_GPC12_VD4 (0x02 << 24) -#define S3C2410_GPC13_VD5 (0x02 << 26) -#define S3C2410_GPC14_VD6 (0x02 << 28) -#define S3C2410_GPC15_VD7 (0x02 << 30) -#define S3C2410_GPC_PUPDIS(x) (1<<(x)) - -/* - * S3C2410: Port D consists of 16 GPIO/Special function - * - * almost identical setup to port b, but the special functions are mostly - * to do with the video system's data. - * - * almost identical setup to port c -*/ - -#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) -#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) -#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) - -#define S3C2410_GPD0_VD8 (0x02 << 0) -#define S3C2442_GPD0_nSPICS1 (0x03 << 0) - -#define S3C2410_GPD1_VD9 (0x02 << 2) -#define S3C2442_GPD1_SPICLK1 (0x03 << 2) - -#define S3C2410_GPD2_VD10 (0x02 << 4) - -#define S3C2410_GPD3_VD11 (0x02 << 6) - -#define S3C2410_GPD4_VD12 (0x02 << 8) - -#define S3C2410_GPD5_VD13 (0x02 << 10) - -#define S3C2410_GPD6_VD14 (0x02 << 12) - -#define S3C2410_GPD7_VD15 (0x02 << 14) - -#define S3C2410_GPD8_VD16 (0x02 << 16) -#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) - -#define S3C2410_GPD9_VD17 (0x02 << 18) -#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) - -#define S3C2410_GPD10_VD18 (0x02 << 20) -#define S3C2440_GPD10_SPICLK1 (0x03 << 20) - -#define S3C2410_GPD11_VD19 (0x02 << 22) - -#define S3C2410_GPD12_VD20 (0x02 << 24) - -#define S3C2410_GPD13_VD21 (0x02 << 26) - -#define S3C2410_GPD14_VD22 (0x02 << 28) -#define S3C2410_GPD14_nSS1 (0x03 << 28) - -#define S3C2410_GPD15_VD23 (0x02 << 30) -#define S3C2410_GPD15_nSS0 (0x03 << 30) - -#define S3C2410_GPD_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port E consists of 16 GPIO/Special function - * - * again, the same as port B, but dealing with I2S, SDI, and - * more miscellaneous functions - * - * GPIO / interrupt inputs -*/ - -#define S3C2410_GPECON S3C2410_GPIOREG(0x40) -#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) -#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) - -#define S3C2410_GPE0_I2SLRCK (0x02 << 0) -#define S3C2443_GPE0_AC_nRESET (0x03 << 0) -#define S3C2410_GPE0_MASK (0x03 << 0) - -#define S3C2410_GPE1_I2SSCLK (0x02 << 2) -#define S3C2443_GPE1_AC_SYNC (0x03 << 2) -#define S3C2410_GPE1_MASK (0x03 << 2) - -#define S3C2410_GPE2_CDCLK (0x02 << 4) -#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) - -#define S3C2410_GPE3_I2SSDI (0x02 << 6) -#define S3C2443_GPE3_AC_SDI (0x03 << 6) -#define S3C2410_GPE3_nSS0 (0x03 << 6) -#define S3C2410_GPE3_MASK (0x03 << 6) - -#define S3C2410_GPE4_I2SSDO (0x02 << 8) -#define S3C2443_GPE4_AC_SDO (0x03 << 8) -#define S3C2410_GPE4_I2SSDI (0x03 << 8) -#define S3C2410_GPE4_MASK (0x03 << 8) - -#define S3C2410_GPE5_SDCLK (0x02 << 10) -#define S3C2443_GPE5_SD1_CLK (0x02 << 10) -#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) - -#define S3C2410_GPE6_SDCMD (0x02 << 12) -#define S3C2443_GPE6_SD1_CMD (0x02 << 12) -#define S3C2443_GPE6_AC_SDI (0x03 << 12) - -#define S3C2410_GPE7_SDDAT0 (0x02 << 14) -#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) -#define S3C2443_GPE7_AC_SDO (0x03 << 14) - -#define S3C2410_GPE8_SDDAT1 (0x02 << 16) -#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) -#define S3C2443_GPE8_AC_SYNC (0x03 << 16) - -#define S3C2410_GPE9_SDDAT2 (0x02 << 18) -#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) -#define S3C2443_GPE9_AC_nRESET (0x03 << 18) - -#define S3C2410_GPE10_SDDAT3 (0x02 << 20) -#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) - -#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) - -#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) - -#define S3C2410_GPE13_SPICLK0 (0x02 << 26) - -#define S3C2410_GPE14_IICSCL (0x02 << 28) -#define S3C2410_GPE14_MASK (0x03 << 28) - -#define S3C2410_GPE15_IICSDA (0x02 << 30) -#define S3C2410_GPE15_MASK (0x03 << 30) - -#define S3C2440_GPE0_ACSYNC (0x03 << 0) -#define S3C2440_GPE1_ACBITCLK (0x03 << 2) -#define S3C2440_GPE2_ACRESET (0x03 << 4) -#define S3C2440_GPE3_ACIN (0x03 << 6) -#define S3C2440_GPE4_ACOUT (0x03 << 8) - -#define S3C2410_GPE_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port F consists of 8 GPIO/Special function - * - * GPIO / interrupt inputs - * - * GPFCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined - * - * pull up works like all other ports. - * - * GPIO/serial/misc pins -*/ - -#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) -#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) -#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) - -#define S3C2410_GPF0_EINT0 (0x02 << 0) -#define S3C2410_GPF1_EINT1 (0x02 << 2) -#define S3C2410_GPF2_EINT2 (0x02 << 4) -#define S3C2410_GPF3_EINT3 (0x02 << 6) -#define S3C2410_GPF4_EINT4 (0x02 << 8) -#define S3C2410_GPF5_EINT5 (0x02 << 10) -#define S3C2410_GPF6_EINT6 (0x02 << 12) -#define S3C2410_GPF7_EINT7 (0x02 << 14) -#define S3C2410_GPF_PUPDIS(x) (1<<(x)) - -/* S3C2410: - * Port G consists of 8 GPIO/IRQ/Special function - * - * GPGCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) -#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) -#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) - -#define S3C2410_GPG0_EINT8 (0x02 << 0) - -#define S3C2410_GPG1_EINT9 (0x02 << 2) - -#define S3C2410_GPG2_EINT10 (0x02 << 4) -#define S3C2410_GPG2_nSS0 (0x03 << 4) - -#define S3C2410_GPG3_EINT11 (0x02 << 6) -#define S3C2410_GPG3_nSS1 (0x03 << 6) - -#define S3C2410_GPG4_EINT12 (0x02 << 8) -#define S3C2410_GPG4_LCDPWREN (0x03 << 8) -#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) - -#define S3C2410_GPG5_EINT13 (0x02 << 10) -#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ - -#define S3C2410_GPG6_EINT14 (0x02 << 12) -#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) - -#define S3C2410_GPG7_EINT15 (0x02 << 14) -#define S3C2410_GPG7_SPICLK1 (0x03 << 14) - -#define S3C2410_GPG8_EINT16 (0x02 << 16) - -#define S3C2410_GPG9_EINT17 (0x02 << 18) - -#define S3C2410_GPG10_EINT18 (0x02 << 20) - -#define S3C2410_GPG11_EINT19 (0x02 << 22) -#define S3C2410_GPG11_TCLK1 (0x03 << 22) -#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) - -#define S3C2410_GPG12_EINT20 (0x02 << 24) -#define S3C2410_GPG12_XMON (0x03 << 24) -#define S3C2442_GPG12_nSPICS0 (0x03 << 24) -#define S3C2443_GPG12_nINPACK (0x03 << 24) - -#define S3C2410_GPG13_EINT21 (0x02 << 26) -#define S3C2410_GPG13_nXPON (0x03 << 26) -#define S3C2443_GPG13_CF_nREG (0x03 << 26) - -#define S3C2410_GPG14_EINT22 (0x02 << 28) -#define S3C2410_GPG14_YMON (0x03 << 28) -#define S3C2443_GPG14_CF_RESET (0x03 << 28) - -#define S3C2410_GPG15_EINT23 (0x02 << 30) -#define S3C2410_GPG15_nYPON (0x03 << 30) -#define S3C2443_GPG15_CF_PWR (0x03 << 30) - -#define S3C2410_GPG_PUPDIS(x) (1<<(x)) - -/* Port H consists of11 GPIO/serial/Misc pins - * - * GPGCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func - * - * pull up works like all other ports. -*/ - -#define S3C2410_GPHCON S3C2410_GPIOREG(0x70) -#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) -#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) - -#define S3C2410_GPH0_nCTS0 (0x02 << 0) -#define S3C2416_GPH0_TXD0 (0x02 << 0) - -#define S3C2410_GPH1_nRTS0 (0x02 << 2) -#define S3C2416_GPH1_RXD0 (0x02 << 2) - -#define S3C2410_GPH2_TXD0 (0x02 << 4) -#define S3C2416_GPH2_TXD1 (0x02 << 4) - -#define S3C2410_GPH3_RXD0 (0x02 << 6) -#define S3C2416_GPH3_RXD1 (0x02 << 6) - -#define S3C2410_GPH4_TXD1 (0x02 << 8) -#define S3C2416_GPH4_TXD2 (0x02 << 8) - -#define S3C2410_GPH5_RXD1 (0x02 << 10) -#define S3C2416_GPH5_RXD2 (0x02 << 10) - -#define S3C2410_GPH6_TXD2 (0x02 << 12) -#define S3C2416_GPH6_TXD3 (0x02 << 12) -#define S3C2410_GPH6_nRTS1 (0x03 << 12) -#define S3C2416_GPH6_nRTS2 (0x03 << 12) - -#define S3C2410_GPH7_RXD2 (0x02 << 14) -#define S3C2416_GPH7_RXD3 (0x02 << 14) -#define S3C2410_GPH7_nCTS1 (0x03 << 14) -#define S3C2416_GPH7_nCTS2 (0x03 << 14) - -#define S3C2410_GPH8_UCLK (0x02 << 16) -#define S3C2416_GPH8_nCTS0 (0x02 << 16) - -#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) -#define S3C2442_GPH9_nSPICS0 (0x03 << 18) -#define S3C2416_GPH9_nRTS0 (0x02 << 18) - -#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) -#define S3C2416_GPH10_nCTS1 (0x02 << 20) - -#define S3C2416_GPH11_nRTS1 (0x02 << 22) - -#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) - -#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) - -#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) - -/* The S3C2412 and S3C2413 move the GPJ register set to after - * GPH, which means all registers after 0x80 are now offset by 0x10 - * for the 2412/2413 from the 2410/2440/2442 -*/ - -/* S3C2443 and above */ -#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) -#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) -#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) - -#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) -#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) -#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) - -#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) -#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) -#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) - -#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) -#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) -#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) - -/* miscellaneous control */ -#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) -#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) - -#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) - -/* see clock.h for dclk definitions */ - -/* pullup control on databus */ -#define S3C2410_MISCCR_SPUCR_HEN (0<<0) -#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) -#define S3C2410_MISCCR_SPUCR_LEN (0<<1) -#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) - -#define S3C2410_MISCCR_USBDEV (0<<3) -#define S3C2410_MISCCR_USBHOST (1<<3) - -#define S3C2410_MISCCR_CLK0_MPLL (0<<4) -#define S3C2410_MISCCR_CLK0_UPLL (1<<4) -#define S3C2410_MISCCR_CLK0_FCLK (2<<4) -#define S3C2410_MISCCR_CLK0_HCLK (3<<4) -#define S3C2410_MISCCR_CLK0_PCLK (4<<4) -#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) -#define S3C2410_MISCCR_CLK0_MASK (7<<4) - -#define S3C2412_MISCCR_CLK0_RTC (2<<4) - -#define S3C2410_MISCCR_CLK1_MPLL (0<<8) -#define S3C2410_MISCCR_CLK1_UPLL (1<<8) -#define S3C2410_MISCCR_CLK1_FCLK (2<<8) -#define S3C2410_MISCCR_CLK1_HCLK (3<<8) -#define S3C2410_MISCCR_CLK1_PCLK (4<<8) -#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) -#define S3C2410_MISCCR_CLK1_MASK (7<<8) - -#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) - -#define S3C2410_MISCCR_USBSUSPND0 (1<<12) -#define S3C2416_MISCCR_SEL_SUSPND (1<<12) -#define S3C2410_MISCCR_USBSUSPND1 (1<<13) - -#define S3C2410_MISCCR_nRSTCON (1<<16) - -#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) -#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) -#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ -#define S3C2410_MISCCR_SDSLEEP (7<<17) - -#define S3C2416_MISCCR_FLT_I2C (1<<24) -#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) - -/* external interrupt control... */ -/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 - * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 - * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 - * - * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 - * - * Samsung datasheet p9-25 -*/ -#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) -#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) -#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) - -#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) -#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) -#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) - -/* interrupt filtering conrrol for EINT16..EINT23 */ -#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) -#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) -#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) -#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) - -#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) -#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) -#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) -#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) - -/* values for interrupt filtering */ -#define S3C2410_EINTFLT_PCLK (0x00) -#define S3C2410_EINTFLT_EXTCLK (1<<7) -#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) - -/* removed EINTxxxx defs from here, not meant for this */ - -/* GSTATUS have miscellaneous information in them - * - * These move between s3c2410 and s3c2412 style systems. - */ - -#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) -#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) -#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) -#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) -#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) - -#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) -#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) -#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) -#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) -#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) - -#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) -#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) -#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) -#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) -#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) - -#define S3C2410_GSTATUS0_nWAIT (1<<3) -#define S3C2410_GSTATUS0_NCON (1<<2) -#define S3C2410_GSTATUS0_RnB (1<<1) -#define S3C2410_GSTATUS0_nBATTFLT (1<<0) - -#define S3C2410_GSTATUS1_IDMASK (0xffff0000) -#define S3C2410_GSTATUS1_2410 (0x32410000) -#define S3C2410_GSTATUS1_2412 (0x32412001) -#define S3C2410_GSTATUS1_2416 (0x32416003) -#define S3C2410_GSTATUS1_2440 (0x32440000) -#define S3C2410_GSTATUS1_2442 (0x32440aaa) -/* some 2416 CPUs report this value also */ -#define S3C2410_GSTATUS1_2450 (0x32450003) - -#define S3C2410_GSTATUS2_WTRESET (1<<2) -#define S3C2410_GSTATUS2_OFFRESET (1<<1) -#define S3C2410_GSTATUS2_PONRESET (1<<0) - -/* 2412/2413 sleep configuration registers */ - -#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) -#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) -#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) -#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) -#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) -#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) - -/* definitions for each pin bit */ -#define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) -#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) -#define S3C2412_GPIO_SLPCON_IN ( 0x02 ) -#define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) - -#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) -#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) -#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) -#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) -#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ -#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) - -#define S3C2412_SLPCON_ALL_LOW (0x0) -#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) -#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) -#define S3C2412_SLPCON_ALL_PULL (0x33333333) - -#endif /* __ASM_ARCH_REGS_GPIO_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h deleted file mode 100644 index 19575e06111..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h +++ /dev/null @@ -1,70 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2440 GPIO J register definitions -*/ - - -#ifndef __ASM_ARCH_REGS_GPIOJ_H -#define __ASM_ARCH_REGS_GPIOJ_H "gpioj" - -/* Port J consists of 13 GPIO/Camera pins - * - * GPJCON has 2 bits for each of the input pins on port F - * 00 = 0 input, 1 output, 2 Camera - * - * pull up works like all other ports. -*/ - -#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) -#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) -#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) -#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) - -#define S3C2440_GPJ0_OUTP (0x01 << 0) -#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) - -#define S3C2440_GPJ1_OUTP (0x01 << 2) -#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) - -#define S3C2440_GPJ2_OUTP (0x01 << 4) -#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) - -#define S3C2440_GPJ3_OUTP (0x01 << 6) -#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) - -#define S3C2440_GPJ4_OUTP (0x01 << 8) -#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) - -#define S3C2440_GPJ5_OUTP (0x01 << 10) -#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) - -#define S3C2440_GPJ6_OUTP (0x01 << 12) -#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) - -#define S3C2440_GPJ7_OUTP (0x01 << 14) -#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) - -#define S3C2440_GPJ8_OUTP (0x01 << 16) -#define S3C2440_GPJ8_CAMPCLK (0x02 << 16) - -#define S3C2440_GPJ9_OUTP (0x01 << 18) -#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) - -#define S3C2440_GPJ10_OUTP (0x01 << 20) -#define S3C2440_GPJ10_CAMHREF (0x02 << 20) - -#define S3C2440_GPJ11_OUTP (0x01 << 22) -#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) - -#define S3C2440_GPJ12_OUTP (0x01 << 24) -#define S3C2440_GPJ12_CAMRESET (0x02 << 24) - -#endif /* __ASM_ARCH_REGS_GPIOJ_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h deleted file mode 100644 index 0f07ba30b1f..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-irq.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - -#ifndef ___ASM_ARCH_REGS_IRQ_H -#define ___ASM_ARCH_REGS_IRQ_H - -/* interrupt controller */ - -#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) -#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) -#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) - -#define S3C2410_SRCPND S3C2410_IRQREG(0x000) -#define S3C2410_INTMOD S3C2410_IRQREG(0x004) -#define S3C2410_INTMSK S3C2410_IRQREG(0x008) -#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) -#define S3C2410_INTPND S3C2410_IRQREG(0x010) -#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) -#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) -#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) - -#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030) -#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034) -#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040) -#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044) -#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048) -#define S3C2416_INTPND2 S3C2410_IRQREG(0x050) -#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054) -#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070) -#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074) - -/* mask: 0=enable, 1=disable - * 1 bit EINT, 4=EINT4, 23=EINT23 - * EINT0,1,2,3 are not handled here. -*/ - -#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) -#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) -#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) -#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) - -#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) -#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) - -#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h deleted file mode 100644 index ee8f040aff5..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h +++ /dev/null @@ -1,162 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - - -#ifndef ___ASM_ARCH_REGS_LCD_H -#define ___ASM_ARCH_REGS_LCD_H - -#define S3C2410_LCDREG(x) (x) - -/* LCD control registers */ -#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) -#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) -#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) -#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) -#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) - -#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) - -#define S3C2410_LCDCON1_STN1BPP (0<<1) -#define S3C2410_LCDCON1_STN2GREY (1<<1) -#define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) -#define S3C2410_LCDCON1_STN12BPP (4<<1) - -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) -#define S3C2410_LCDCON1_TFT16BPP (12<<1) -#define S3C2410_LCDCON1_TFT24BPP (13<<1) - -#define S3C2410_LCDCON1_ENVID (1) - -#define S3C2410_LCDCON1_MODEMASK 0x1E - -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) -#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) - -#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) -#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) -#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) - -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) -#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) -#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) - -#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) -#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) - -/* LDCCON4 changes for STN mode on the S3C2412 */ - -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) - -#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) - -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) -#define S3C2410_LCDCON5_INVVLINE (1<<9) -#define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) -#define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) - -/* framebuffer start addressed */ -#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) -#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) -#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) - -#define S3C2410_LCDBANK(x) ((x) << 21) -#define S3C2410_LCDBASEU(x) (x) - -#define S3C2410_OFFSIZE(x) ((x) << 11) -#define S3C2410_PAGEWIDTH(x) (x) - -/* colour lookup and miscellaneous controls */ - -#define S3C2410_REDLUT S3C2410_LCDREG(0x20) -#define S3C2410_GREENLUT S3C2410_LCDREG(0x24) -#define S3C2410_BLUELUT S3C2410_LCDREG(0x28) - -#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) -#define S3C2410_TPAL S3C2410_LCDREG(0x50) - -#define S3C2410_TPAL_EN (1<<24) - -/* interrupt info */ -#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) -#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) -#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) -#define S3C2410_LCDINT_FIWSEL (1<<2) -#define S3C2410_LCDINT_FRSYNC (1<<1) -#define S3C2410_LCDINT_FICNT (1<<0) - -/* s3c2442 extra stn registers */ - -#define S3C2442_REDLUT S3C2410_LCDREG(0x20) -#define S3C2442_GREENLUT S3C2410_LCDREG(0x24) -#define S3C2442_BLUELUT S3C2410_LCDREG(0x28) -#define S3C2442_DITHMODE S3C2410_LCDREG(0x20) - -#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) - -#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) - -/* S3C2412 registers */ - -#define S3C2412_TPAL S3C2410_LCDREG(0x20) - -#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) -#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) -#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) - -#define S3C2412_TCONSEL S3C2410_LCDREG(0x30) - -#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) -#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) -#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) -#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) - -#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) -#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) -#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) - -#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) - -/* general registers */ - -/* base of the LCD registers, where INTPND, INTSRC and then INTMSK - * are available. */ - -#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) -#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) - -#define S3C24XX_LCDINTPND (0x00) -#define S3C24XX_LCDSRCPND (0x04) -#define S3C24XX_LCDINTMSK (0x08) - -#endif /* ___ASM_ARCH_REGS_LCD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h deleted file mode 100644 index e0c67b0163d..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ /dev/null @@ -1,202 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-mem.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Memory Control register definitions -*/ - -#ifndef __ASM_ARM_MEMREGS_H -#define __ASM_ARM_MEMREGS_H - -#ifndef S3C2410_MEMREG -#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif - -/* bus width, and wait state control */ -#define S3C2410_BWSCON S3C2410_MEMREG(0x0000) - -/* bank zero config - note, pinstrapped from OM pins! */ -#define S3C2410_BWSCON_DW0_16 (1<<1) -#define S3C2410_BWSCON_DW0_32 (2<<1) - -/* bank one configs */ -#define S3C2410_BWSCON_DW1_8 (0<<4) -#define S3C2410_BWSCON_DW1_16 (1<<4) -#define S3C2410_BWSCON_DW1_32 (2<<4) -#define S3C2410_BWSCON_WS1 (1<<6) -#define S3C2410_BWSCON_ST1 (1<<7) - -/* bank 2 configurations */ -#define S3C2410_BWSCON_DW2_8 (0<<8) -#define S3C2410_BWSCON_DW2_16 (1<<8) -#define S3C2410_BWSCON_DW2_32 (2<<8) -#define S3C2410_BWSCON_WS2 (1<<10) -#define S3C2410_BWSCON_ST2 (1<<11) - -/* bank 3 configurations */ -#define S3C2410_BWSCON_DW3_8 (0<<12) -#define S3C2410_BWSCON_DW3_16 (1<<12) -#define S3C2410_BWSCON_DW3_32 (2<<12) -#define S3C2410_BWSCON_WS3 (1<<14) -#define S3C2410_BWSCON_ST3 (1<<15) - -/* bank 4 configurations */ -#define S3C2410_BWSCON_DW4_8 (0<<16) -#define S3C2410_BWSCON_DW4_16 (1<<16) -#define S3C2410_BWSCON_DW4_32 (2<<16) -#define S3C2410_BWSCON_WS4 (1<<18) -#define S3C2410_BWSCON_ST4 (1<<19) - -/* bank 5 configurations */ -#define S3C2410_BWSCON_DW5_8 (0<<20) -#define S3C2410_BWSCON_DW5_16 (1<<20) -#define S3C2410_BWSCON_DW5_32 (2<<20) -#define S3C2410_BWSCON_WS5 (1<<22) -#define S3C2410_BWSCON_ST5 (1<<23) - -/* bank 6 configurations */ -#define S3C2410_BWSCON_DW6_8 (0<<24) -#define S3C2410_BWSCON_DW6_16 (1<<24) -#define S3C2410_BWSCON_DW6_32 (2<<24) -#define S3C2410_BWSCON_WS6 (1<<26) -#define S3C2410_BWSCON_ST6 (1<<27) - -/* bank 7 configurations */ -#define S3C2410_BWSCON_DW7_8 (0<<28) -#define S3C2410_BWSCON_DW7_16 (1<<28) -#define S3C2410_BWSCON_DW7_32 (2<<28) -#define S3C2410_BWSCON_WS7 (1<<30) -#define S3C2410_BWSCON_ST7 (1<<31) - -/* accesor functions for getting BANK(n) configuration. (n != 0) */ - -#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) - -#define S3C2410_BWSCON_DW8 (0) -#define S3C2410_BWSCON_DW16 (1) -#define S3C2410_BWSCON_DW32 (2) -#define S3C2410_BWSCON_WS (1 << 2) -#define S3C2410_BWSCON_ST (1 << 3) - -/* memory set (rom, ram) */ -#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) -#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) -#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C) -#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010) -#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014) -#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018) -#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C) -#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020) - -/* bank configuration registers */ - -#define S3C2410_BANKCON_PMCnorm (0x00) -#define S3C2410_BANKCON_PMC4 (0x01) -#define S3C2410_BANKCON_PMC8 (0x02) -#define S3C2410_BANKCON_PMC16 (0x03) - -/* bank configurations for banks 0..7, note banks - * 6 and 7 have different configurations depending on - * the memory type bits */ - -#define S3C2410_BANKCON_Tacp2 (0x0 << 2) -#define S3C2410_BANKCON_Tacp3 (0x1 << 2) -#define S3C2410_BANKCON_Tacp4 (0x2 << 2) -#define S3C2410_BANKCON_Tacp6 (0x3 << 2) -#define S3C2410_BANKCON_Tacp_SHIFT (2) - -#define S3C2410_BANKCON_Tcah0 (0x0 << 4) -#define S3C2410_BANKCON_Tcah1 (0x1 << 4) -#define S3C2410_BANKCON_Tcah2 (0x2 << 4) -#define S3C2410_BANKCON_Tcah4 (0x3 << 4) -#define S3C2410_BANKCON_Tcah_SHIFT (4) - -#define S3C2410_BANKCON_Tcoh0 (0x0 << 6) -#define S3C2410_BANKCON_Tcoh1 (0x1 << 6) -#define S3C2410_BANKCON_Tcoh2 (0x2 << 6) -#define S3C2410_BANKCON_Tcoh4 (0x3 << 6) -#define S3C2410_BANKCON_Tcoh_SHIFT (6) - -#define S3C2410_BANKCON_Tacc1 (0x0 << 8) -#define S3C2410_BANKCON_Tacc2 (0x1 << 8) -#define S3C2410_BANKCON_Tacc3 (0x2 << 8) -#define S3C2410_BANKCON_Tacc4 (0x3 << 8) -#define S3C2410_BANKCON_Tacc6 (0x4 << 8) -#define S3C2410_BANKCON_Tacc8 (0x5 << 8) -#define S3C2410_BANKCON_Tacc10 (0x6 << 8) -#define S3C2410_BANKCON_Tacc14 (0x7 << 8) -#define S3C2410_BANKCON_Tacc_SHIFT (8) - -#define S3C2410_BANKCON_Tcos0 (0x0 << 11) -#define S3C2410_BANKCON_Tcos1 (0x1 << 11) -#define S3C2410_BANKCON_Tcos2 (0x2 << 11) -#define S3C2410_BANKCON_Tcos4 (0x3 << 11) -#define S3C2410_BANKCON_Tcos_SHIFT (11) - -#define S3C2410_BANKCON_Tacs0 (0x0 << 13) -#define S3C2410_BANKCON_Tacs1 (0x1 << 13) -#define S3C2410_BANKCON_Tacs2 (0x2 << 13) -#define S3C2410_BANKCON_Tacs4 (0x3 << 13) -#define S3C2410_BANKCON_Tacs_SHIFT (13) - -#define S3C2410_BANKCON_SRAM (0x0 << 15) -#define S3C2410_BANKCON_SDRAM (0x3 << 15) - -/* next bits only for SDRAM in 6,7 */ -#define S3C2410_BANKCON_Trcd2 (0x00 << 2) -#define S3C2410_BANKCON_Trcd3 (0x01 << 2) -#define S3C2410_BANKCON_Trcd4 (0x02 << 2) - -/* control column address select */ -#define S3C2410_BANKCON_SCANb8 (0x00 << 0) -#define S3C2410_BANKCON_SCANb9 (0x01 << 0) -#define S3C2410_BANKCON_SCANb10 (0x02 << 0) - -#define S3C2410_REFRESH S3C2410_MEMREG(0x0024) -#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028) -#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C) -#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030) - -/* refresh control */ - -#define S3C2410_REFRESH_REFEN (1<<23) -#define S3C2410_REFRESH_SELF (1<<22) -#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1) - -#define S3C2410_REFRESH_TRP_MASK (3<<20) -#define S3C2410_REFRESH_TRP_2clk (0<<20) -#define S3C2410_REFRESH_TRP_3clk (1<<20) -#define S3C2410_REFRESH_TRP_4clk (2<<20) - -#define S3C2410_REFRESH_TSRC_MASK (3<<18) -#define S3C2410_REFRESH_TSRC_4clk (0<<18) -#define S3C2410_REFRESH_TSRC_5clk (1<<18) -#define S3C2410_REFRESH_TSRC_6clk (2<<18) -#define S3C2410_REFRESH_TSRC_7clk (3<<18) - - -/* mode select register(s) */ - -#define S3C2410_MRSRB_CL1 (0x00 << 4) -#define S3C2410_MRSRB_CL2 (0x02 << 4) -#define S3C2410_MRSRB_CL3 (0x03 << 4) - -/* bank size register */ -#define S3C2410_BANKSIZE_128M (0x2 << 0) -#define S3C2410_BANKSIZE_64M (0x1 << 0) -#define S3C2410_BANKSIZE_32M (0x0 << 0) -#define S3C2410_BANKSIZE_16M (0x7 << 0) -#define S3C2410_BANKSIZE_8M (0x6 << 0) -#define S3C2410_BANKSIZE_4M (0x5 << 0) -#define S3C2410_BANKSIZE_2M (0x4 << 0) -#define S3C2410_BANKSIZE_MASK (0x7 << 0) -#define S3C2410_BANKSIZE_SCLK_EN (1<<4) -#define S3C2410_BANKSIZE_SCKE_EN (1<<5) -#define S3C2410_BANKSIZE_BURST (1<<7) - -#endif /* __ASM_ARM_MEMREGS_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h deleted file mode 100644 index 4932b87bdf3..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-power.h +++ /dev/null @@ -1,40 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-power.h - * - * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C24XX power control register definitions -*/ - -#ifndef __ASM_ARM_REGS_PWR -#define __ASM_ARM_REGS_PWR __FILE__ - -#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) -#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) - -#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) -#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) -#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) -#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) - -#define S3C2412_PWRCFG_BATF_IRQ (1<<0) -#define S3C2412_PWRCFG_BATF_IGNORE (2<<0) -#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) -#define S3C2412_PWRCFG_BATF_MASK (3<<0) - -#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) -#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) -#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) -#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) -#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) - -#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) -#define S3C2412_PWRCFG_NAND_NORST (1<<9) - -#endif /* __ASM_ARM_REGS_PWR */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h deleted file mode 100644 index fb635251509..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h +++ /dev/null @@ -1,48 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2412_MEM -#define __ASM_ARM_REGS_S3C2412_MEM - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_BANKCFG S3C2412_MEMREG(0x00) -#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) -#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) -#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) -#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) - -/* EBI control registers */ - -#define S3C2412_EBI_PR S3C2412_EBIREG(0x00) -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) - -/* SSMC control registers */ - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) -#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) -#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) -#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) -#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) -#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) -#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) - -#endif /* __ASM_ARM_REGS_S3C2412_MEM */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h deleted file mode 100644 index aa69dc79bc3..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h +++ /dev/null @@ -1,23 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h - * - * Copyright 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 specific register definitions -*/ - -#ifndef __ASM_ARCH_REGS_S3C2412_H -#define __ASM_ARCH_REGS_S3C2412_H "s3c2412" - -#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) -#define S3C2412_SWRST_RESET (0x533C2412) - -/* see regs-power.h for the other registers in the power block. */ - -#endif /* __ASM_ARCH_REGS_S3C2412_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h deleted file mode 100644 index 2f31b74974a..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2416 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2416_MEM -#define __ASM_ARM_REGS_S3C2416_MEM - -#ifndef S3C2416_MEMREG -#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif - -#define S3C2416_BANKCFG S3C2416_MEMREG(0x00) -#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04) -#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08) -#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C) - -#define S3C2416_REFRESH S3C2416_MEMREG(0x10) -#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14) - -#endif /* __ASM_ARM_REGS_S3C2416_MEM */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h deleted file mode 100644 index e443167efb8..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2416 specific register definitions -*/ - -#ifndef __ASM_ARCH_REGS_S3C2416_H -#define __ASM_ARCH_REGS_S3C2416_H "s3c2416" - -#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44) -#define S3C2416_SWRST_RESET (0x533C2416) - -/* see regs-power.h for the other registers in the power block. */ - -#endif /* __ASM_ARCH_REGS_S3C2416_H */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h deleted file mode 100644 index c3feff3c048..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ /dev/null @@ -1,194 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h - * - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2443 clock register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2443_CLOCK -#define __ASM_ARM_REGS_S3C2443_CLOCK - -#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2443_PLLCON_MDIVSHIFT 16 -#define S3C2443_PLLCON_PDIVSHIFT 8 -#define S3C2443_PLLCON_SDIVSHIFT 0 -#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) -#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) -#define S3C2443_PLLCON_SDIVMASK (3) - -#define S3C2443_MPLLCON S3C2443_CLKREG(0x10) -#define S3C2443_EPLLCON S3C2443_CLKREG(0x18) -#define S3C2443_CLKSRC S3C2443_CLKREG(0x20) -#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) -#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) -#define S3C2443_HCLKCON S3C2443_CLKREG(0x30) -#define S3C2443_PCLKCON S3C2443_CLKREG(0x34) -#define S3C2443_SCLKCON S3C2443_CLKREG(0x38) -#define S3C2443_PWRMODE S3C2443_CLKREG(0x40) -#define S3C2443_SWRST S3C2443_CLKREG(0x44) -#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) -#define S3C2443_SYSID S3C2443_CLKREG(0x5C) -#define S3C2443_PWRCFG S3C2443_CLKREG(0x60) -#define S3C2443_RSTCON S3C2443_CLKREG(0x64) -#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80) -#define S3C2443_PHYPWR S3C2443_CLKREG(0x84) -#define S3C2443_URSTCON S3C2443_CLKREG(0x88) -#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) - -#define S3C2443_SWRST_RESET (0x533c2443) - -#define S3C2443_PLLCON_OFF (1<<24) - -#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) -#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) -#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) -#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) - -#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) - -#define S3C2443_CLKDIV0_HALF_HCLK (1<<3) -#define S3C2443_CLKDIV0_HALF_PCLK (1<<2) - -#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) - -#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) -#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) - -#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) -#define S3C2443_CLKDIV0_PREDIV_SHIFT (4) - -#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9) -#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) -#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) -#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) -#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) -#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) -#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) -#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) -#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) -#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) -#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) - -/* S3C2443_CLKDIV1 removed, only used in clock.c code */ - -#define S3C2443_CLKCON_NAND - -#define S3C2443_HCLKCON_DMA0 (1<<0) -#define S3C2443_HCLKCON_DMA1 (1<<1) -#define S3C2443_HCLKCON_DMA2 (1<<2) -#define S3C2443_HCLKCON_DMA3 (1<<3) -#define S3C2443_HCLKCON_DMA4 (1<<4) -#define S3C2443_HCLKCON_DMA5 (1<<5) -#define S3C2443_HCLKCON_CAMIF (1<<8) -#define S3C2443_HCLKCON_LCDC (1<<9) -#define S3C2443_HCLKCON_USBH (1<<11) -#define S3C2443_HCLKCON_USBD (1<<12) -#define S3C2416_HCLKCON_HSMMC0 (1<<15) -#define S3C2443_HCLKCON_HSMMC (1<<16) -#define S3C2443_HCLKCON_CFC (1<<17) -#define S3C2443_HCLKCON_SSMC (1<<18) -#define S3C2443_HCLKCON_DRAMC (1<<19) - -#define S3C2443_PCLKCON_UART0 (1<<0) -#define S3C2443_PCLKCON_UART1 (1<<1) -#define S3C2443_PCLKCON_UART2 (1<<2) -#define S3C2443_PCLKCON_UART3 (1<<3) -#define S3C2443_PCLKCON_IIC (1<<4) -#define S3C2443_PCLKCON_SDI (1<<5) -#define S3C2443_PCLKCON_HSSPI (1<<6) -#define S3C2443_PCLKCON_ADC (1<<7) -#define S3C2443_PCLKCON_AC97 (1<<8) -#define S3C2443_PCLKCON_IIS (1<<9) -#define S3C2443_PCLKCON_PWMT (1<<10) -#define S3C2443_PCLKCON_WDT (1<<11) -#define S3C2443_PCLKCON_RTC (1<<12) -#define S3C2443_PCLKCON_GPIO (1<<13) -#define S3C2443_PCLKCON_SPI0 (1<<14) -#define S3C2443_PCLKCON_SPI1 (1<<15) - -#define S3C2443_SCLKCON_DDRCLK (1<<16) -#define S3C2443_SCLKCON_SSMCCLK (1<<15) -#define S3C2443_SCLKCON_HSSPICLK (1<<14) -#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) -#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) -#define S3C2443_SCLKCON_CAMCLK (1<<11) -#define S3C2443_SCLKCON_DISPCLK (1<<10) -#define S3C2443_SCLKCON_I2SCLK (1<<9) -#define S3C2443_SCLKCON_UARTCLK (1<<8) -#define S3C2443_SCLKCON_USBHOST (1<<1) - -#define S3C2443_PWRCFG_SLEEP (1<<15) - -#define S3C2443_PWRCFG_USBPHY (1 << 4) - -#define S3C2443_URSTCON_FUNCRST (1 << 2) -#define S3C2443_URSTCON_PHYRST (1 << 0) - -#define S3C2443_PHYCTRL_CLKSEL (1 << 3) -#define S3C2443_PHYCTRL_EXTCLK (1 << 2) -#define S3C2443_PHYCTRL_PLLSEL (1 << 1) -#define S3C2443_PHYCTRL_DSPORT (1 << 0) - -#define S3C2443_PHYPWR_COMMON_ON (1 << 31) -#define S3C2443_PHYPWR_ANALOG_PD (1 << 4) -#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3) -#define S3C2443_PHYPWR_XO_ON (1 << 2) -#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1) -#define S3C2443_PHYPWR_FSUSPEND (1 << 0) - -#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31) -#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2) -#define S3C2443_UCLKCON_TCLKEN (1 << 0) - -#include <asm/div64.h> - -static inline unsigned int -s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); - do_div(fvco, pdiv << sdiv); - - return (unsigned int)fvco; -} - -static inline unsigned int -s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; - - mdiv &= S3C2443_PLLCON_MDIVMASK; - pdiv &= S3C2443_PLLCON_PDIVMASK; - sdiv &= S3C2443_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ - diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h deleted file mode 100644 index cbf2d8884e3..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h +++ /dev/null @@ -1,127 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 MMC/SDIO register definitions -*/ - -#ifndef __ASM_ARM_REGS_SDI -#define __ASM_ARM_REGS_SDI "regs-sdi.h" - -#define S3C2410_SDICON (0x00) -#define S3C2410_SDIPRE (0x04) -#define S3C2410_SDICMDARG (0x08) -#define S3C2410_SDICMDCON (0x0C) -#define S3C2410_SDICMDSTAT (0x10) -#define S3C2410_SDIRSP0 (0x14) -#define S3C2410_SDIRSP1 (0x18) -#define S3C2410_SDIRSP2 (0x1C) -#define S3C2410_SDIRSP3 (0x20) -#define S3C2410_SDITIMER (0x24) -#define S3C2410_SDIBSIZE (0x28) -#define S3C2410_SDIDCON (0x2C) -#define S3C2410_SDIDCNT (0x30) -#define S3C2410_SDIDSTA (0x34) -#define S3C2410_SDIFSTA (0x38) - -#define S3C2410_SDIDATA (0x3C) -#define S3C2410_SDIIMSK (0x40) - -#define S3C2440_SDIDATA (0x40) -#define S3C2440_SDIIMSK (0x3C) - -#define S3C2440_SDICON_SDRESET (1<<8) -#define S3C2440_SDICON_MMCCLOCK (1<<5) -#define S3C2410_SDICON_BYTEORDER (1<<4) -#define S3C2410_SDICON_SDIOIRQ (1<<3) -#define S3C2410_SDICON_RWAITEN (1<<2) -#define S3C2410_SDICON_FIFORESET (1<<1) -#define S3C2410_SDICON_CLOCKTYPE (1<<0) - -#define S3C2410_SDICMDCON_ABORT (1<<12) -#define S3C2410_SDICMDCON_WITHDATA (1<<11) -#define S3C2410_SDICMDCON_LONGRSP (1<<10) -#define S3C2410_SDICMDCON_WAITRSP (1<<9) -#define S3C2410_SDICMDCON_CMDSTART (1<<8) -#define S3C2410_SDICMDCON_SENDERHOST (1<<6) -#define S3C2410_SDICMDCON_INDEX (0x3f) - -#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) -#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) -#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) -#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) -#define S3C2410_SDICMDSTAT_XFERING (1<<8) -#define S3C2410_SDICMDSTAT_INDEX (0xff) - -#define S3C2440_SDIDCON_DS_BYTE (0<<22) -#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) -#define S3C2440_SDIDCON_DS_WORD (2<<22) -#define S3C2410_SDIDCON_IRQPERIOD (1<<21) -#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) -#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) -#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) -#define S3C2410_SDIDCON_BLOCKMODE (1<<17) -#define S3C2410_SDIDCON_WIDEBUS (1<<16) -#define S3C2410_SDIDCON_DMAEN (1<<15) -#define S3C2410_SDIDCON_STOP (1<<14) -#define S3C2440_SDIDCON_DATSTART (1<<14) -#define S3C2410_SDIDCON_DATMODE (3<<12) -#define S3C2410_SDIDCON_BLKNUM (0x7ff) - -/* constants for S3C2410_SDIDCON_DATMODE */ -#define S3C2410_SDIDCON_XFER_READY (0<<12) -#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) -#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) -#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) - -#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) -#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) - -#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) -#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) -#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ -#define S3C2410_SDIDSTA_CRCFAIL (1<<7) -#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) -#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) -#define S3C2410_SDIDSTA_XFERFINISH (1<<4) -#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) -#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ -#define S3C2410_SDIDSTA_TXDATAON (1<<1) -#define S3C2410_SDIDSTA_RXDATAON (1<<0) - -#define S3C2440_SDIFSTA_FIFORESET (1<<16) -#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ -#define S3C2410_SDIFSTA_TFDET (1<<13) -#define S3C2410_SDIFSTA_RFDET (1<<12) -#define S3C2410_SDIFSTA_TFHALF (1<<11) -#define S3C2410_SDIFSTA_TFEMPTY (1<<10) -#define S3C2410_SDIFSTA_RFLAST (1<<9) -#define S3C2410_SDIFSTA_RFFULL (1<<8) -#define S3C2410_SDIFSTA_RFHALF (1<<7) -#define S3C2410_SDIFSTA_COUNTMASK (0x7f) - -#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) -#define S3C2410_SDIIMSK_CMDSENT (1<<16) -#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) -#define S3C2410_SDIIMSK_RESPONSEND (1<<14) -#define S3C2410_SDIIMSK_READWAIT (1<<13) -#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) -#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) -#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) -#define S3C2410_SDIIMSK_DATACRC (1<<9) -#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) -#define S3C2410_SDIIMSK_DATAFINISH (1<<7) -#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) -#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ -#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) -#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) -#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) -#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) -#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) - -#endif /* __ASM_ARM_REGS_SDI */ diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h deleted file mode 100644 index 4d9588373aa..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/spi.h - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - SPI Controller platform_device info - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_SPI_H -#define __ASM_ARCH_SPI_H __FILE__ - -struct s3c2410_spi_info { - int pin_cs; /* simple gpio cs */ - unsigned int num_cs; /* total chipselects */ - int bus_num; /* bus number to use. */ - - unsigned int use_fiq:1; /* use fiq */ - - void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable); - void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); -}; - -/* Standard setup / suspend routines for SPI GPIO pins. */ - -extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, - int enable); - -extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, - int enable); - -extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, - int enable); - -#endif /* __ASM_ARCH_SPI_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h deleted file mode 100644 index 5e215c1a5c8..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/system.h +++ /dev/null @@ -1,54 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/system.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - System function defines and includes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/io.h> -#include <mach/hardware.h> - -#include <mach/map.h> -#include <mach/idle.h> - -#include <mach/regs-clock.h> - -void (*s3c24xx_idle)(void); - -void s3c24xx_default_idle(void) -{ - unsigned long tmp; - int i; - - /* idle the system by using the idle mode which will wait for an - * interrupt to happen before restarting the system. - */ - - /* Warning: going into idle state upsets jtag scanning */ - - __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, - S3C2410_CLKCON); - - /* the samsung port seems to do a loop and then unset idle.. */ - for (i = 0; i < 50; i++) { - tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ - } - - /* this bit is not cleared on re-start... */ - - __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, - S3C2410_CLKCON); -} - -static void arch_idle(void) -{ - if (s3c24xx_idle != NULL) - (s3c24xx_idle)(); - else - s3c24xx_default_idle(); -} diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c2410/include/mach/tick.h deleted file mode 100644 index 544da41979d..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/tick.h +++ /dev/null @@ -1,15 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/include/mach/tick.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C2410 - timer tick support - */ - -#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) - -static inline int s3c24xx_ostimer_pending(void) -{ - return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; -} diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h deleted file mode 100644 index fe9ca1ffd51..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/timex.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/timex.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - time parameters - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it - * a variable is useless. It seems as long as we make our timers an - * exact multiple of HZ, any value that makes a 1->1 correspondence - * for the time conversion functions to/from jiffies is acceptable. -*/ - -#define CLOCK_TICK_RATE 12000000 - -#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h deleted file mode 100644 index 8b283f847da..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ /dev/null @@ -1,54 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/uncompress.h - * - * Copyright (c) 2003-2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - uncompress code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/regs-gpio.h> -#include <mach/map.h> - -/* working in physical space... */ -#undef S3C2410_GPIOREG -#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) - -#include <plat/uncompress.h> - -static inline int is_arm926(void) -{ - unsigned int cpuid; - - asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); - - return ((cpuid & 0xff0) == 0x260); -} - -static void arch_detect_cpu(void) -{ - unsigned int cpuid; - - cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); - cpuid &= S3C2410_GSTATUS1_IDMASK; - - if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || - cpuid == S3C2410_GSTATUS1_2442 || - cpuid == S3C2410_GSTATUS1_2416 || - cpuid == S3C2410_GSTATUS1_2450) { - fifo_mask = S3C2440_UFSTAT_TXMASK; - fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; - } else { - fifo_mask = S3C2410_UFSTAT_TXMASK; - fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; - } -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h deleted file mode 100644 index e4119913d7c..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * VR1000 - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VR1000CPLD_H -#define __ASM_ARCH_VR1000CPLD_H - -#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ - -#endif /* __ASM_ARCH_VR1000CPLD_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h deleted file mode 100644 index 47add133b8e..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h +++ /dev/null @@ -1,26 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine VR1000 - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VR1000IRQ_H -#define __ASM_ARCH_VR1000IRQ_H - -/* irq numbers to onboard peripherals */ - -#define IRQ_USBOC IRQ_EINT19 -#define IRQ_IDE0 IRQ_EINT16 -#define IRQ_IDE1 IRQ_EINT17 -#define IRQ_VR1000_SERIAL IRQ_EINT12 -#define IRQ_VR1000_DM9000A IRQ_EINT10 -#define IRQ_VR1000_DM9000N IRQ_EINT9 -#define IRQ_SMALERT IRQ_EINT8 - -#endif /* __ASM_ARCH_VR1000IRQ_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h deleted file mode 100644 index 99612fcc4eb..00000000000 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h +++ /dev/null @@ -1,110 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine VR1000 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#ifndef __ASM_ARCH_VR1000MAP_H -#define __ASM_ARCH_VR1000MAP_H - -#include <mach/bast-map.h> - -#define VR1000_IOADDR(x) BAST_IOADDR(x) - -/* we put the CPLD registers next, to get them out of the way */ - -#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ -#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ -#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ -#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ -#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ -#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) - -#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ -#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) - -#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ -#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) - -/* 0xE0000000 contains the IO space that is split by speed and - * wether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers - * 0x02600000 to 0x02700000 1MB - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define VR1000_VA_MULTISPACE (0xE0000000) - -#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) -#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) -#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) -#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) -#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) -#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) -#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) -#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) -#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) - -/* physical offset addresses for the peripherals */ - -#define VR1000_PA_IDEPRI (0x02000000) -#define VR1000_PA_IDEPRIAUX (0x02800000) -#define VR1000_PA_IDESEC (0x03000000) -#define VR1000_PA_IDESECAUX (0x03800000) -#define VR1000_PA_DM9000 (0x05000000) - -#define VR1000_PA_SERIAL (0x11800000) -#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) - -/* VR1000 ram is in CS1, with A26..A24 = 2_101 */ -#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) - -/* some configurations for the peripherals */ - -#define VR1000_DM9000_CS VR1000_VAM_CS4 - -#endif /* __ASM_ARCH_VR1000MAP_H */ diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c deleted file mode 100644 index 4220cc60de3..00000000000 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ /dev/null @@ -1,247 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-amlm5900.c - * - * linux/arch/arm/mach-s3c2410/mach-amlm5900.c - * - * Copyright (c) 2006 American Microsystems Limited - * David Anders <danders@amltd.com> - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * @History: - * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by - * Ben Dooks <ben@simtec.co.uk> - * - ***********************************************************************/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/proc_fs.h> -#include <linux/serial_core.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/flash.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> -#include <mach/fb.h> - -#include <plat/regs-serial.h> -#include <mach/regs-lcd.h> -#include <mach/regs-gpio.h> - -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/gpio-cfg.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/map.h> -#include <linux/mtd/physmap.h> - -#include "common.h" - -static struct resource amlm5900_nor_resource = { - .start = 0x00000000, - .end = 0x01000000 - 1, - .flags = IORESOURCE_MEM, -}; - - - -static struct mtd_partition amlm5900_mtd_partitions[] = { - { - .name = "System", - .size = 0x240000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - .name = "Kernel", - .size = 0x100000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "Ramdisk", - .size = 0x300000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "JFFS2", - .size = 0x9A0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "Settings", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data amlm5900_flash_data = { - .width = 2, - .parts = amlm5900_mtd_partitions, - .nr_parts = ARRAY_SIZE(amlm5900_mtd_partitions), -}; - -static struct platform_device amlm5900_device_nor = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &amlm5900_flash_data, - }, - .num_resources = 1, - .resource = &amlm5900_nor_resource, -}; - -static struct map_desc amlm5900_iodesc[] __initdata = { -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg amlm5900_uartcfgs[] = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - - -static struct platform_device *amlm5900_devices[] __initdata = { -#ifdef CONFIG_FB_S3C2410 - &s3c_device_lcd, -#endif - &s3c_device_adc, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_ohci, - &s3c_device_rtc, - &s3c_device_usbgadget, - &s3c_device_sdi, - &amlm5900_device_nor, -}; - -static void __init amlm5900_map_io(void) -{ - s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); -} - -#ifdef CONFIG_FB_S3C2410 -static struct s3c2410fb_display __initdata amlm5900_lcd_info = { - .width = 160, - .height = 160, - - .type = S3C2410_LCDCON1_STN4, - - .pixclock = 680000, /* HCLK = 100MHz */ - .xres = 160, - .yres = 160, - .bpp = 4, - .left_margin = 1 << (4 + 3), - .right_margin = 8 << 3, - .hsync_len = 48, - .upper_margin = 0, - .lower_margin = 0, - - .lcdcon5 = 0x00000001, -}; - -static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = { - - .displays = &amlm5900_lcd_info, - .num_displays = 1, - .default_display = 0, - - .gpccon = 0xaaaaaaaa, - .gpccon_mask = 0xffffffff, - .gpcup = 0x0000ffff, - .gpcup_mask = 0xffffffff, - - .gpdcon = 0xaaaaaaaa, - .gpdcon_mask = 0xffffffff, - .gpdup = 0x0000ffff, - .gpdup_mask = 0xffffffff, -}; -#endif - -static irqreturn_t -amlm5900_wake_interrupt(int irq, void *ignored) -{ - return IRQ_HANDLED; -} - -static void amlm5900_init_pm(void) -{ - int ret = 0; - - ret = request_irq(IRQ_EINT9, &amlm5900_wake_interrupt, - IRQF_TRIGGER_RISING | IRQF_SHARED, - "amlm5900_wakeup", &amlm5900_wake_interrupt); - if (ret != 0) { - printk(KERN_ERR "AML-M5900: no wakeup irq, %d?\n", ret); - } else { - enable_irq_wake(IRQ_EINT9); - /* configure the suspend/resume status pin */ - s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); - s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP); - } -} -static void __init amlm5900_init(void) -{ - amlm5900_init_pm(); -#ifdef CONFIG_FB_S3C2410 - s3c24xx_fb_set_platdata(&amlm5900_fb_info); -#endif - s3c_i2c0_set_platdata(NULL); - platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); -} - -MACHINE_START(AML_M5900, "AML_M5900") - .atag_offset = 0x100, - .map_io = amlm5900_map_io, - .init_irq = s3c24xx_init_irq, - .init_machine = amlm5900_init, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c deleted file mode 100644 index feeaf73933d..00000000000 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ /dev/null @@ -1,645 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-bast.c - * - * Copyright 2003-2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://www.simtec.co.uk/products/EB2410ITX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/syscore_ops.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/dm9000.h> -#include <linux/ata_platform.h> -#include <linux/i2c.h> -#include <linux/io.h> - -#include <net/ax88796.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/bast-map.h> -#include <mach/bast-irq.h> -#include <mach/bast-cpld.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -//#include <asm/debug-ll.h> -#include <plat/regs-serial.h> -#include <mach/regs-gpio.h> -#include <mach/regs-mem.h> -#include <mach/regs-lcd.h> - -#include <plat/hwmon.h> -#include <plat/nand.h> -#include <plat/iic.h> -#include <mach/fb.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/partitions.h> - -#include <linux/serial_8250.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/cpu-freq.h> -#include <plat/gpio-cfg.h> -#include <plat/audio-simtec.h> - -#include "usb-simtec.h" -#include "nor-simtec.h" -#include "common.h" - -#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" - -/* macros for virtual address mods for the io space entries */ -#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) -#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) -#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) -#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) - -/* macros to modify the physical addresses for io space */ - -#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2)) -#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3)) -#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4)) -#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5)) - -static struct map_desc bast_iodesc[] __initdata = { - /* ISA IO areas */ - { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = PA_CS2(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, - }, - /* bast CPLD control registers, and external interrupt controls */ - { - .virtual = (u32)BAST_VA_CTRL1, - .pfn = __phys_to_pfn(BAST_PA_CTRL1), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_CTRL2, - .pfn = __phys_to_pfn(BAST_PA_CTRL2), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_CTRL3, - .pfn = __phys_to_pfn(BAST_PA_CTRL3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_CTRL4, - .pfn = __phys_to_pfn(BAST_PA_CTRL4), - .length = SZ_1M, - .type = MT_DEVICE, - }, - /* PC104 IRQ mux */ - { - .virtual = (u32)BAST_VA_PC104_IRQREQ, - .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_PC104_IRQRAW, - .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)BAST_VA_PC104_IRQMASK, - .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK), - .length = SZ_1M, - .type = MT_DEVICE, - }, - - /* peripheral space... one for each of fast/slow/byte/16bit */ - /* note, ide is only decoded in word space, even though some registers - * are only 8bit */ - - /* slow, byte */ - { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - - /* slow, word */ - { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - - /* fast, byte */ - { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, - - /* fast, word */ - { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, - { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, - { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - /* port 2 is not actually used */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -/* NAND Flash on BAST board */ - -#ifdef CONFIG_PM -static int bast_pm_suspend(void) -{ - /* ensure that an nRESET is not generated on resume. */ - gpio_direction_output(S3C2410_GPA(21), 1); - return 0; -} - -static void bast_pm_resume(void) -{ - s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); -} - -#else -#define bast_pm_suspend NULL -#define bast_pm_resume NULL -#endif - -static struct syscore_ops bast_pm_syscore_ops = { - .suspend = bast_pm_suspend, - .resume = bast_pm_resume, -}; - -static int smartmedia_map[] = { 0 }; -static int chip0_map[] = { 1 }; -static int chip1_map[] = { 2 }; -static int chip2_map[] = { 3 }; - -static struct mtd_partition __initdata bast_default_nand_part[] = { - [0] = { - .name = "Boot Agent", - .size = SZ_16K, - .offset = 0, - }, - [1] = { - .name = "/boot", - .size = SZ_4M - SZ_16K, - .offset = SZ_16K, - }, - [2] = { - .name = "user", - .offset = SZ_4M, - .size = MTDPART_SIZ_FULL, - } -}; - -/* the bast has 4 selectable slots for nand-flash, the three - * on-board chip areas, as well as the external SmartMedia - * slot. - * - * Note, there is no current hot-plug support for the SmartMedia - * socket. -*/ - -static struct s3c2410_nand_set __initdata bast_nand_sets[] = { - [0] = { - .name = "SmartMedia", - .nr_chips = 1, - .nr_map = smartmedia_map, - .options = NAND_SCAN_SILENT_NODEV, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - }, - [1] = { - .name = "chip0", - .nr_chips = 1, - .nr_map = chip0_map, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - }, - [2] = { - .name = "chip1", - .nr_chips = 1, - .nr_map = chip1_map, - .options = NAND_SCAN_SILENT_NODEV, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - }, - [3] = { - .name = "chip2", - .nr_chips = 1, - .nr_map = chip2_map, - .options = NAND_SCAN_SILENT_NODEV, - .nr_partitions = ARRAY_SIZE(bast_default_nand_part), - .partitions = bast_default_nand_part, - } -}; - -static void bast_nand_select(struct s3c2410_nand_set *set, int slot) -{ - unsigned int tmp; - - slot = set->nr_map[slot] & 3; - - pr_debug("bast_nand: selecting slot %d (set %p,%p)\n", - slot, set, set->nr_map); - - tmp = __raw_readb(BAST_VA_CTRL2); - tmp &= BAST_CPLD_CTLR2_IDERST; - tmp |= slot; - tmp |= BAST_CPLD_CTRL2_WNAND; - - pr_debug("bast_nand: ctrl2 now %02x\n", tmp); - - __raw_writeb(tmp, BAST_VA_CTRL2); -} - -static struct s3c2410_platform_nand __initdata bast_nand_info = { - .tacls = 30, - .twrph0 = 60, - .twrph1 = 60, - .nr_sets = ARRAY_SIZE(bast_nand_sets), - .sets = bast_nand_sets, - .select_chip = bast_nand_select, -}; - -/* DM9000 */ - -static struct resource bast_dm9k_resource[] = { - [0] = { - .start = S3C2410_CS5 + BAST_PA_DM9000, - .end = S3C2410_CS5 + BAST_PA_DM9000 + 3, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40, - .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_DM9000, - .end = IRQ_DM9000, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - } - -}; - -/* for the moment we limit ourselves to 16bit IO until some - * better IO routines can be written and tested -*/ - -static struct dm9000_plat_data bast_dm9k_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device bast_device_dm9k = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(bast_dm9k_resource), - .resource = bast_dm9k_resource, - .dev = { - .platform_data = &bast_dm9k_platdata, - } -}; - -/* serial devices */ - -#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO) -#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ) -#define SERIAL_CLK (1843200) - -static struct plat_serial8250_port bast_sio_data[] = { - [0] = { - .mapbase = SERIAL_BASE + 0x2f8, - .irq = IRQ_PCSERIAL1, - .flags = SERIAL_FLAGS, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = SERIAL_CLK, - }, - [1] = { - .mapbase = SERIAL_BASE + 0x3f8, - .irq = IRQ_PCSERIAL2, - .flags = SERIAL_FLAGS, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = SERIAL_CLK, - }, - { } -}; - -static struct platform_device bast_sio = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = &bast_sio_data, - }, -}; - -/* we have devices on the bus which cannot work much over the - * standard 100KHz i2c bus frequency -*/ - -static struct s3c2410_platform_i2c __initdata bast_i2c_info = { - .flags = 0, - .slave_addr = 0x10, - .frequency = 100*1000, -}; - -/* Asix AX88796 10/100 ethernet controller */ - -static struct ax_plat_data bast_asix_platdata = { - .flags = AXFLG_MAC_FROMDEV, - .wordlength = 2, - .dcr_val = 0x48, - .rcr_val = 0x40, -}; - -static struct resource bast_asix_resource[] = { - [0] = { - .start = S3C2410_CS5 + BAST_PA_ASIXNET, - .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), - .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_ASIX, - .end = IRQ_ASIX, - .flags = IORESOURCE_IRQ - } -}; - -static struct platform_device bast_device_asix = { - .name = "ax88796", - .id = 0, - .num_resources = ARRAY_SIZE(bast_asix_resource), - .resource = bast_asix_resource, - .dev = { - .platform_data = &bast_asix_platdata - } -}; - -/* Asix AX88796 10/100 ethernet controller parallel port */ - -static struct resource bast_asixpp_resource[] = { - [0] = { - .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), - .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device bast_device_axpp = { - .name = "ax88796-pp", - .id = 0, - .num_resources = ARRAY_SIZE(bast_asixpp_resource), - .resource = bast_asixpp_resource, -}; - -/* LCD/VGA controller */ - -static struct s3c2410fb_display __initdata bast_lcd_info[] = { - { - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 33333, - .xres = 640, - .yres = 480, - .bpp = 4, - .left_margin = 40, - .right_margin = 20, - .hsync_len = 88, - .upper_margin = 30, - .lower_margin = 32, - .vsync_len = 3, - - .lcdcon5 = 0x00014b02, - }, - { - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 33333, - .xres = 640, - .yres = 480, - .bpp = 8, - .left_margin = 40, - .right_margin = 20, - .hsync_len = 88, - .upper_margin = 30, - .lower_margin = 32, - .vsync_len = 3, - - .lcdcon5 = 0x00014b02, - }, - { - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 33333, - .xres = 640, - .yres = 480, - .bpp = 16, - .left_margin = 40, - .right_margin = 20, - .hsync_len = 88, - .upper_margin = 30, - .lower_margin = 32, - .vsync_len = 3, - - .lcdcon5 = 0x00014b02, - }, -}; - -/* LCD/VGA controller */ - -static struct s3c2410fb_mach_info __initdata bast_fb_info = { - - .displays = bast_lcd_info, - .num_displays = ARRAY_SIZE(bast_lcd_info), - .default_display = 1, -}; - -/* I2C devices fitted. */ - -static struct i2c_board_info bast_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, { - I2C_BOARD_INFO("simtec-pmu", 0x6b), - }, { - I2C_BOARD_INFO("ch7013", 0x75), - }, -}; - -static struct s3c_hwmon_pdata bast_hwmon_info = { - /* LCD contrast (0-6.6V) */ - .in[0] = &(struct s3c_hwmon_chcfg) { - .name = "lcd-contrast", - .mult = 3300, - .div = 512, - }, - /* LED current feedback */ - .in[1] = &(struct s3c_hwmon_chcfg) { - .name = "led-feedback", - .mult = 3300, - .div = 1024, - }, - /* LCD feedback (0-6.6V) */ - .in[2] = &(struct s3c_hwmon_chcfg) { - .name = "lcd-feedback", - .mult = 3300, - .div = 512, - }, - /* Vcore (1.8-2.0V), Vref 3.3V */ - .in[3] = &(struct s3c_hwmon_chcfg) { - .name = "vcore", - .mult = 3300, - .div = 1024, - }, -}; - -/* Standard BAST devices */ -// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 - -static struct platform_device *bast_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_rtc, - &s3c_device_nand, - &s3c_device_adc, - &s3c_device_hwmon, - &bast_device_dm9k, - &bast_device_asix, - &bast_device_axpp, - &bast_sio, -}; - -static struct clk *bast_clocks[] __initdata = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - -static struct s3c_cpufreq_board __initdata bast_cpufreq = { - .refresh = 7800, /* 7.8usec */ - .auto_io = 1, - .need_io = 1, -}; - -static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = { - .have_mic = 1, - .have_lout = 1, -}; - -static void __init bast_map_io(void) -{ - /* initialise the clocks */ - - s3c24xx_dclk0.parent = &clk_upll; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = &clk_upll; - s3c24xx_dclk1.rate = 24*1000*1000; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); - - s3c_hwmon_set_platdata(&bast_hwmon_info); - - s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); -} - -static void __init bast_init(void) -{ - register_syscore_ops(&bast_pm_syscore_ops); - - s3c_i2c0_set_platdata(&bast_i2c_info); - s3c_nand_set_platdata(&bast_nand_info); - s3c24xx_fb_set_platdata(&bast_fb_info); - platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); - - i2c_register_board_info(0, bast_i2c_devs, - ARRAY_SIZE(bast_i2c_devs)); - - usb_simtec_init(); - nor_simtec_init(); - simtec_audio_add(NULL, true, &bast_audio); - - WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset")); - - s3c_cpufreq_setboard(&bast_cpufreq); -} - -MACHINE_START(BAST, "Simtec-BAST") - /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ - .atag_offset = 0x100, - .map_io = bast_map_io, - .init_irq = s3c24xx_init_irq, - .init_machine = bast_init, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c deleted file mode 100644 index 41245a60398..00000000000 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ /dev/null @@ -1,757 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-h1940.c - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://www.handhelds.org/projects/h1940.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/memblock.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/gpio_keys.h> -#include <linux/pwm_backlight.h> -#include <linux/i2c.h> -#include <linux/leds.h> -#include <linux/pda_power.h> -#include <linux/s3c_adc_battery.h> -#include <linux/delay.h> - -#include <video/platform_lcd.h> - -#include <linux/mmc/host.h> -#include <linux/export.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <mach/regs-lcd.h> -#include <mach/regs-clock.h> - -#include <mach/regs-gpio.h> -#include <mach/gpio-fns.h> -#include <mach/gpio-nrs.h> - -#include <mach/h1940.h> -#include <mach/h1940-latch.h> -#include <mach/fb.h> -#include <plat/udc.h> -#include <plat/iic.h> - -#include <plat/gpio-cfg.h> -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/pll.h> -#include <plat/pm.h> -#include <plat/mci.h> -#include <plat/ts.h> - -#include <sound/uda1380.h> - -#include "common.h" - -#define H1940_LATCH ((void __force __iomem *)0xF8000000) - -#define H1940_PA_LATCH S3C2410_CS2 - -#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END)) - -static struct map_desc h1940_iodesc[] __initdata = { - [0] = { - .virtual = (unsigned long)H1940_LATCH, - .pfn = __phys_to_pfn(H1940_PA_LATCH), - .length = SZ_16K, - .type = MT_DEVICE - }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x3c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = 0x245, - .ulcon = 0x03, - .ufcon = 0x00, - }, - /* IR port */ - [2] = { - .hwport = 2, - .flags = 0, - .uart_flags = UPF_CONS_FLOW, - .ucon = 0x3c5, - .ulcon = 0x43, - .ufcon = 0x51, - } -}; - -/* Board control latch control */ - -static unsigned int latch_state; - -static void h1940_latch_control(unsigned int clear, unsigned int set) -{ - unsigned long flags; - - local_irq_save(flags); - - latch_state &= ~clear; - latch_state |= set; - - __raw_writel(latch_state, H1940_LATCH); - - local_irq_restore(flags); -} - -static inline int h1940_gpiolib_to_latch(int offset) -{ - return 1 << (offset + 16); -} - -static void h1940_gpiolib_latch_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - int latch_bit = h1940_gpiolib_to_latch(offset); - - h1940_latch_control(value ? 0 : latch_bit, - value ? latch_bit : 0); -} - -static int h1940_gpiolib_latch_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - h1940_gpiolib_latch_set(chip, offset, value); - return 0; -} - -static int h1940_gpiolib_latch_get(struct gpio_chip *chip, - unsigned offset) -{ - return (latch_state >> (offset + 16)) & 1; -} - -struct gpio_chip h1940_latch_gpiochip = { - .base = H1940_LATCH_GPIO(0), - .owner = THIS_MODULE, - .label = "H1940_LATCH", - .ngpio = 16, - .direction_output = h1940_gpiolib_latch_output, - .set = h1940_gpiolib_latch_set, - .get = h1940_gpiolib_latch_get, -}; - -static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { - .vbus_pin = S3C2410_GPG(5), - .vbus_pin_inverted = 1, - .pullup_pin = H1940_LATCH_USB_DP, -}; - -static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, - .cfg_gpio = s3c24xx_ts_cfg_gpio, -}; - -/** - * Set lcd on or off - **/ -static struct s3c2410fb_display h1940_lcd __initdata = { - .lcdcon5= S3C2410_LCDCON5_FRM565 | \ - S3C2410_LCDCON5_INVVLINE | \ - S3C2410_LCDCON5_HWSWP, - - .type = S3C2410_LCDCON1_TFT, - .width = 240, - .height = 320, - .pixclock = 260000, - .xres = 240, - .yres = 320, - .bpp = 16, - .left_margin = 8, - .right_margin = 20, - .hsync_len = 4, - .upper_margin = 8, - .lower_margin = 7, - .vsync_len = 1, -}; - -static struct s3c2410fb_mach_info h1940_fb_info __initdata = { - .displays = &h1940_lcd, - .num_displays = 1, - .default_display = 0, - - .lpcsel = 0x02, - .gpccon = 0xaa940659, - .gpccon_mask = 0xffffc0f0, - .gpcup = 0x0000ffff, - .gpcup_mask = 0xffffffff, - .gpdcon = 0xaa84aaa0, - .gpdcon_mask = 0xffffffff, - .gpdup = 0x0000faff, - .gpdup_mask = 0xffffffff, -}; - -static int power_supply_init(struct device *dev) -{ - return gpio_request(S3C2410_GPF(2), "cable plugged"); -} - -static int h1940_is_ac_online(void) -{ - return !gpio_get_value(S3C2410_GPF(2)); -} - -static void power_supply_exit(struct device *dev) -{ - gpio_free(S3C2410_GPF(2)); -} - -static char *h1940_supplicants[] = { - "main-battery", - "backup-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = h1940_is_ac_online, - .exit = power_supply_exit, - .supplied_to = h1940_supplicants, - .num_supplicants = ARRAY_SIZE(h1940_supplicants), -}; - -static struct resource power_supply_resources[] = { - [0] = { - .name = "ac", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | - IORESOURCE_IRQ_HIGHEDGE, - .start = IRQ_EINT2, - .end = IRQ_EINT2, - }, -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = - &power_supply_info, - }, - .resource = power_supply_resources, - .num_resources = ARRAY_SIZE(power_supply_resources), -}; - -static const struct s3c_adc_bat_thresh bat_lut_noac[] = { - { .volt = 4070, .cur = 162, .level = 100}, - { .volt = 4040, .cur = 165, .level = 95}, - { .volt = 4016, .cur = 164, .level = 90}, - { .volt = 3996, .cur = 166, .level = 85}, - { .volt = 3971, .cur = 168, .level = 80}, - { .volt = 3951, .cur = 168, .level = 75}, - { .volt = 3931, .cur = 170, .level = 70}, - { .volt = 3903, .cur = 172, .level = 65}, - { .volt = 3886, .cur = 172, .level = 60}, - { .volt = 3858, .cur = 176, .level = 55}, - { .volt = 3842, .cur = 176, .level = 50}, - { .volt = 3818, .cur = 176, .level = 45}, - { .volt = 3789, .cur = 180, .level = 40}, - { .volt = 3769, .cur = 180, .level = 35}, - { .volt = 3749, .cur = 184, .level = 30}, - { .volt = 3732, .cur = 184, .level = 25}, - { .volt = 3716, .cur = 184, .level = 20}, - { .volt = 3708, .cur = 184, .level = 15}, - { .volt = 3716, .cur = 96, .level = 10}, - { .volt = 3700, .cur = 96, .level = 5}, - { .volt = 3684, .cur = 96, .level = 0}, -}; - -static const struct s3c_adc_bat_thresh bat_lut_acin[] = { - { .volt = 4130, .cur = 0, .level = 100}, - { .volt = 3982, .cur = 0, .level = 50}, - { .volt = 3854, .cur = 0, .level = 10}, - { .volt = 3841, .cur = 0, .level = 0}, -}; - -int h1940_bat_init(void) -{ - int ret; - - ret = gpio_request(H1940_LATCH_SM803_ENABLE, "h1940-charger-enable"); - if (ret) - return ret; - gpio_direction_output(H1940_LATCH_SM803_ENABLE, 0); - - return 0; - -} - -void h1940_bat_exit(void) -{ - gpio_free(H1940_LATCH_SM803_ENABLE); -} - -void h1940_enable_charger(void) -{ - gpio_set_value(H1940_LATCH_SM803_ENABLE, 1); -} - -void h1940_disable_charger(void) -{ - gpio_set_value(H1940_LATCH_SM803_ENABLE, 0); -} - -static struct s3c_adc_bat_pdata h1940_bat_cfg = { - .init = h1940_bat_init, - .exit = h1940_bat_exit, - .enable_charger = h1940_enable_charger, - .disable_charger = h1940_disable_charger, - .gpio_charge_finished = S3C2410_GPF(3), - .gpio_inverted = 1, - .lut_noac = bat_lut_noac, - .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac), - .lut_acin = bat_lut_acin, - .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin), - .volt_channel = 0, - .current_channel = 1, - .volt_mult = 4056, - .current_mult = 1893, - .internal_impedance = 200, - .backup_volt_channel = 3, - /* TODO Check backup volt multiplier */ - .backup_volt_mult = 4056, - .backup_volt_min = 0, - .backup_volt_max = 4149288 -}; - -static struct platform_device h1940_battery = { - .name = "s3c-adc-battery", - .id = -1, - .dev = { - .parent = &s3c_device_adc.dev, - .platform_data = &h1940_bat_cfg, - }, -}; - -DEFINE_SPINLOCK(h1940_blink_spin); - -int h1940_led_blink_set(unsigned gpio, int state, - unsigned long *delay_on, unsigned long *delay_off) -{ - int blink_gpio, check_gpio1, check_gpio2; - - switch (gpio) { - case H1940_LATCH_LED_GREEN: - blink_gpio = S3C2410_GPA(7); - check_gpio1 = S3C2410_GPA(1); - check_gpio2 = S3C2410_GPA(3); - break; - case H1940_LATCH_LED_RED: - blink_gpio = S3C2410_GPA(1); - check_gpio1 = S3C2410_GPA(7); - check_gpio2 = S3C2410_GPA(3); - break; - default: - blink_gpio = S3C2410_GPA(3); - check_gpio1 = S3C2410_GPA(1); - check_gpio1 = S3C2410_GPA(7); - break; - } - - if (delay_on && delay_off && !*delay_on && !*delay_off) - *delay_on = *delay_off = 500; - - spin_lock(&h1940_blink_spin); - - switch (state) { - case GPIO_LED_NO_BLINK_LOW: - case GPIO_LED_NO_BLINK_HIGH: - if (!gpio_get_value(check_gpio1) && - !gpio_get_value(check_gpio2)) - gpio_set_value(H1940_LATCH_LED_FLASH, 0); - gpio_set_value(blink_gpio, 0); - if (gpio_is_valid(gpio)) - gpio_set_value(gpio, state); - break; - case GPIO_LED_BLINK: - if (gpio_is_valid(gpio)) - gpio_set_value(gpio, 0); - gpio_set_value(H1940_LATCH_LED_FLASH, 1); - gpio_set_value(blink_gpio, 1); - break; - } - - spin_unlock(&h1940_blink_spin); - - return 0; -} -EXPORT_SYMBOL(h1940_led_blink_set); - -static struct gpio_led h1940_leds_desc[] = { - { - .name = "Green", - .default_trigger = "main-battery-full", - .gpio = H1940_LATCH_LED_GREEN, - .retain_state_suspended = 1, - }, - { - .name = "Red", - .default_trigger - = "main-battery-charging-blink-full-solid", - .gpio = H1940_LATCH_LED_RED, - .retain_state_suspended = 1, - }, -}; - -static struct gpio_led_platform_data h1940_leds_pdata = { - .num_leds = ARRAY_SIZE(h1940_leds_desc), - .leds = h1940_leds_desc, - .gpio_blink_set = h1940_led_blink_set, -}; - -static struct platform_device h1940_device_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &h1940_leds_pdata, - }, -}; - -static struct platform_device h1940_device_bluetooth = { - .name = "h1940-bt", - .id = -1, -}; - -static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd) -{ - switch (power_mode) { - case MMC_POWER_OFF: - gpio_set_value(H1940_LATCH_SD_POWER, 0); - break; - case MMC_POWER_UP: - case MMC_POWER_ON: - gpio_set_value(H1940_LATCH_SD_POWER, 1); - break; - default: - break; - }; -} - -static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = { - .gpio_detect = S3C2410_GPF(5), - .gpio_wprotect = S3C2410_GPH(8), - .set_power = h1940_set_mmc_power, - .ocr_avail = MMC_VDD_32_33, -}; - -static int h1940_backlight_init(struct device *dev) -{ - gpio_request(S3C2410_GPB(0), "Backlight"); - - gpio_direction_output(S3C2410_GPB(0), 0); - s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); - gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1); - - return 0; -} - -static int h1940_backlight_notify(struct device *dev, int brightness) -{ - if (!brightness) { - gpio_direction_output(S3C2410_GPB(0), 1); - gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0); - } else { - gpio_direction_output(S3C2410_GPB(0), 0); - s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); - gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1); - } - return brightness; -} - -static void h1940_backlight_exit(struct device *dev) -{ - gpio_direction_output(S3C2410_GPB(0), 1); - gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0); -} - - -static struct platform_pwm_backlight_data backlight_data = { - .pwm_id = 0, - .max_brightness = 100, - .dft_brightness = 50, - /* tcnt = 0x31 */ - .pwm_period_ns = 36296, - .init = h1940_backlight_init, - .notify = h1940_backlight_notify, - .exit = h1940_backlight_exit, -}; - -static struct platform_device h1940_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &s3c_device_timer[0].dev, - .platform_data = &backlight_data, - }, - .id = -1, -}; - -static void h1940_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - int value, retries = 100; - - if (!power) { - gpio_set_value(S3C2410_GPC(0), 0); - /* wait for 3ac */ - do { - value = gpio_get_value(S3C2410_GPC(6)); - } while (value && retries--); - - gpio_set_value(H1940_LATCH_LCD_P2, 0); - gpio_set_value(H1940_LATCH_LCD_P3, 0); - gpio_set_value(H1940_LATCH_LCD_P4, 0); - - gpio_direction_output(S3C2410_GPC(1), 0); - gpio_direction_output(S3C2410_GPC(4), 0); - - gpio_set_value(H1940_LATCH_LCD_P1, 0); - gpio_set_value(H1940_LATCH_LCD_P0, 0); - - gpio_set_value(S3C2410_GPC(5), 0); - - } else { - gpio_set_value(H1940_LATCH_LCD_P0, 1); - gpio_set_value(H1940_LATCH_LCD_P1, 1); - - gpio_direction_input(S3C2410_GPC(1)); - gpio_direction_input(S3C2410_GPC(4)); - mdelay(10); - s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2)); - - gpio_set_value(S3C2410_GPC(5), 1); - gpio_set_value(S3C2410_GPC(0), 1); - - gpio_set_value(H1940_LATCH_LCD_P3, 1); - gpio_set_value(H1940_LATCH_LCD_P2, 1); - gpio_set_value(H1940_LATCH_LCD_P4, 1); - } -} - -static struct plat_lcd_data h1940_lcd_power_data = { - .set_power = h1940_lcd_power_set, -}; - -static struct platform_device h1940_lcd_powerdev = { - .name = "platform-lcd", - .dev.parent = &s3c_device_lcd.dev, - .dev.platform_data = &h1940_lcd_power_data, -}; - -static struct uda1380_platform_data uda1380_info = { - .gpio_power = H1940_LATCH_UDA_POWER, - .gpio_reset = S3C2410_GPA(12), - .dac_clk = UDA1380_DAC_CLK_SYSCLK, -}; - -static struct i2c_board_info h1940_i2c_devices[] = { - { - I2C_BOARD_INFO("uda1380", 0x1a), - .platform_data = &uda1380_info, - }, -}; - -#define DECLARE_BUTTON(p, k, n, w) \ - { \ - .gpio = p, \ - .code = k, \ - .desc = n, \ - .wakeup = w, \ - .active_low = 1, \ - } - -static struct gpio_keys_button h1940_buttons[] = { - DECLARE_BUTTON(S3C2410_GPF(0), KEY_POWER, "Power", 1), - DECLARE_BUTTON(S3C2410_GPF(6), KEY_ENTER, "Select", 1), - DECLARE_BUTTON(S3C2410_GPF(7), KEY_RECORD, "Record", 0), - DECLARE_BUTTON(S3C2410_GPG(0), KEY_F11, "Calendar", 0), - DECLARE_BUTTON(S3C2410_GPG(2), KEY_F12, "Contacts", 0), - DECLARE_BUTTON(S3C2410_GPG(3), KEY_MAIL, "Mail", 0), - DECLARE_BUTTON(S3C2410_GPG(6), KEY_LEFT, "Left_arrow", 0), - DECLARE_BUTTON(S3C2410_GPG(7), KEY_HOMEPAGE, "Home", 0), - DECLARE_BUTTON(S3C2410_GPG(8), KEY_RIGHT, "Right_arrow", 0), - DECLARE_BUTTON(S3C2410_GPG(9), KEY_UP, "Up_arrow", 0), - DECLARE_BUTTON(S3C2410_GPG(10), KEY_DOWN, "Down_arrow", 0), -}; - -static struct gpio_keys_platform_data h1940_buttons_data = { - .buttons = h1940_buttons, - .nbuttons = ARRAY_SIZE(h1940_buttons), -}; - -static struct platform_device h1940_dev_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &h1940_buttons_data, - } -}; - -static struct platform_device *h1940_devices[] __initdata = { - &h1940_dev_buttons, - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_iis, - &samsung_asoc_dma, - &s3c_device_usbgadget, - &h1940_device_leds, - &h1940_device_bluetooth, - &s3c_device_sdi, - &s3c_device_rtc, - &s3c_device_timer[0], - &h1940_backlight, - &h1940_lcd_powerdev, - &s3c_device_adc, - &s3c_device_ts, - &power_supply, - &h1940_battery, -}; - -static void __init h1940_map_io(void) -{ - s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); - - /* setup PM */ - -#ifdef CONFIG_PM_H1940 - memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); -#endif - s3c_pm_init(); - - /* Add latch gpio chip, set latch initial value */ - h1940_latch_control(0, 0); - WARN_ON(gpiochip_add(&h1940_latch_gpiochip)); -} - -/* H1940 and RX3715 need to reserve this for suspend */ -static void __init h1940_reserve(void) -{ - memblock_reserve(0x30003000, 0x1000); - memblock_reserve(0x30081000, 0x1000); -} - -static void __init h1940_init_irq(void) -{ - s3c24xx_init_irq(); -} - -static void __init h1940_init(void) -{ - u32 tmp; - - s3c24xx_fb_set_platdata(&h1940_fb_info); - s3c24xx_mci_set_platdata(&h1940_mmc_cfg); - s3c24xx_udc_set_platdata(&h1940_udc_cfg); - s3c24xx_ts_set_platdata(&h1940_ts_cfg); - s3c_i2c0_set_platdata(NULL); - - /* Turn off suspend on both USB ports, and switch the - * selectable USB port to USB device mode. */ - - s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | - S3C2410_MISCCR_USBSUSPND0 | - S3C2410_MISCCR_USBSUSPND1, 0x0); - - tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT) - | (0x02 << S3C24XX_PLL_PDIV_SHIFT) - | (0x03 << S3C24XX_PLL_SDIV_SHIFT); - writel(tmp, S3C2410_UPLLCON); - - gpio_request(S3C2410_GPC(0), "LCD power"); - gpio_request(S3C2410_GPC(1), "LCD power"); - gpio_request(S3C2410_GPC(4), "LCD power"); - gpio_request(S3C2410_GPC(5), "LCD power"); - gpio_request(S3C2410_GPC(6), "LCD power"); - gpio_request(H1940_LATCH_LCD_P0, "LCD power"); - gpio_request(H1940_LATCH_LCD_P1, "LCD power"); - gpio_request(H1940_LATCH_LCD_P2, "LCD power"); - gpio_request(H1940_LATCH_LCD_P3, "LCD power"); - gpio_request(H1940_LATCH_LCD_P4, "LCD power"); - gpio_request(H1940_LATCH_MAX1698_nSHUTDOWN, "LCD power"); - gpio_direction_output(S3C2410_GPC(0), 0); - gpio_direction_output(S3C2410_GPC(1), 0); - gpio_direction_output(S3C2410_GPC(4), 0); - gpio_direction_output(S3C2410_GPC(5), 0); - gpio_direction_input(S3C2410_GPC(6)); - gpio_direction_output(H1940_LATCH_LCD_P0, 0); - gpio_direction_output(H1940_LATCH_LCD_P1, 0); - gpio_direction_output(H1940_LATCH_LCD_P2, 0); - gpio_direction_output(H1940_LATCH_LCD_P3, 0); - gpio_direction_output(H1940_LATCH_LCD_P4, 0); - gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0); - - gpio_request(H1940_LATCH_SD_POWER, "SD power"); - gpio_direction_output(H1940_LATCH_SD_POWER, 0); - - platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); - - gpio_request(S3C2410_GPA(1), "Red LED blink"); - gpio_request(S3C2410_GPA(3), "Blue LED blink"); - gpio_request(S3C2410_GPA(7), "Green LED blink"); - gpio_request(H1940_LATCH_LED_FLASH, "LED blink"); - gpio_direction_output(S3C2410_GPA(1), 0); - gpio_direction_output(S3C2410_GPA(3), 0); - gpio_direction_output(S3C2410_GPA(7), 0); - gpio_direction_output(H1940_LATCH_LED_FLASH, 0); - - i2c_register_board_info(0, h1940_i2c_devices, - ARRAY_SIZE(h1940_i2c_devices)); -} - -MACHINE_START(H1940, "IPAQ-H1940") - /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ - .atag_offset = 0x100, - .map_io = h1940_map_io, - .reserve = h1940_reserve, - .init_irq = h1940_init_irq, - .init_machine = h1940_init, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c deleted file mode 100644 index 383d00ca8f6..00000000000 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ /dev/null @@ -1,608 +0,0 @@ -/* Machine specific code for the Acer n30, Acer N35, Navman PiN 570, - * Yakumo AlphaX and Airis NC05 PDAs. - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se> - * - * There is a wiki with more information about the n30 port at - * http://handhelds.org/moin/moin.cgi/AcerN30Documentation . - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/types.h> - -#include <linux/gpio_keys.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/timer.h> -#include <linux/io.h> -#include <linux/mmc/host.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <mach/fb.h> -#include <mach/leds-gpio.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> - -#include <plat/iic.h> -#include <plat/regs-serial.h> - -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/mci.h> -#include <plat/s3c2410.h> -#include <plat/udc.h> - -#include "common.h" - -static struct map_desc n30_iodesc[] __initdata = { - /* nothing here yet */ -}; - -static struct s3c2410_uartcfg n30_uartcfgs[] = { - /* Normal serial port */ - [0] = { - .hwport = 0, - .flags = 0, - .ucon = 0x2c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, - /* IR port */ - [1] = { - .hwport = 1, - .flags = 0, - .uart_flags = UPF_CONS_FLOW, - .ucon = 0x2c5, - .ulcon = 0x43, - .ufcon = 0x51, - }, - /* On the N30 the bluetooth controller is connected here. - * On the N35 and variants the GPS receiver is connected here. */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = 0x2c5, - .ulcon = 0x03, - .ufcon = 0x51, - }, -}; - -static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { - .vbus_pin = S3C2410_GPG(1), - .vbus_pin_inverted = 0, - .pullup_pin = S3C2410_GPB(3), -}; - -static struct gpio_keys_button n30_buttons[] = { - { - .gpio = S3C2410_GPF(0), - .code = KEY_POWER, - .desc = "Power", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(9), - .code = KEY_UP, - .desc = "Thumbwheel Up", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(8), - .code = KEY_DOWN, - .desc = "Thumbwheel Down", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(7), - .code = KEY_ENTER, - .desc = "Thumbwheel Press", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(7), - .code = KEY_HOMEPAGE, - .desc = "Home", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(6), - .code = KEY_CALENDAR, - .desc = "Calendar", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(5), - .code = KEY_ADDRESSBOOK, - .desc = "Contacts", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(4), - .code = KEY_MAIL, - .desc = "Mail", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data n30_button_data = { - .buttons = n30_buttons, - .nbuttons = ARRAY_SIZE(n30_buttons), -}; - -static struct platform_device n30_button_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &n30_button_data, - } -}; - -static struct gpio_keys_button n35_buttons[] = { - { - .gpio = S3C2410_GPF(0), - .code = KEY_POWER, - .type = EV_PWR, - .desc = "Power", - .active_low = 0, - .wakeup = 1, - }, - { - .gpio = S3C2410_GPG(9), - .code = KEY_UP, - .desc = "Joystick Up", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(8), - .code = KEY_DOWN, - .desc = "Joystick Down", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(6), - .code = KEY_DOWN, - .desc = "Joystick Left", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(5), - .code = KEY_DOWN, - .desc = "Joystick Right", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(7), - .code = KEY_ENTER, - .desc = "Joystick Press", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(7), - .code = KEY_HOMEPAGE, - .desc = "Home", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(6), - .code = KEY_CALENDAR, - .desc = "Calendar", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(5), - .code = KEY_ADDRESSBOOK, - .desc = "Contacts", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(4), - .code = KEY_MAIL, - .desc = "Mail", - .active_low = 0, - }, - { - .gpio = S3C2410_GPF(3), - .code = SW_RADIO, - .desc = "GPS Antenna", - .active_low = 0, - }, - { - .gpio = S3C2410_GPG(2), - .code = SW_HEADPHONE_INSERT, - .desc = "Headphone", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data n35_button_data = { - .buttons = n35_buttons, - .nbuttons = ARRAY_SIZE(n35_buttons), -}; - -static struct platform_device n35_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &n35_button_data, - } -}; - -/* This is the bluetooth LED on the device. */ -static struct s3c24xx_led_platdata n30_blue_led_pdata = { - .name = "blue_led", - .gpio = S3C2410_GPG(6), - .def_trigger = "", -}; - -/* This is the blue LED on the device. Originally used to indicate GPS activity - * by flashing. */ -static struct s3c24xx_led_platdata n35_blue_led_pdata = { - .name = "blue_led", - .gpio = S3C2410_GPD(8), - .def_trigger = "", -}; - -/* This LED is driven by the battery microcontroller, and is blinking - * red, blinking green or solid green when the battery is low, - * charging or full respectively. By driving GPD9 low, it's possible - * to force the LED to blink red, so call that warning LED. */ -static struct s3c24xx_led_platdata n30_warning_led_pdata = { - .name = "warning_led", - .flags = S3C24XX_LEDF_ACTLOW, - .gpio = S3C2410_GPD(9), - .def_trigger = "", -}; - -static struct s3c24xx_led_platdata n35_warning_led_pdata = { - .name = "warning_led", - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .gpio = S3C2410_GPD(9), - .def_trigger = "", -}; - -static struct platform_device n30_blue_led = { - .name = "s3c24xx_led", - .id = 1, - .dev = { - .platform_data = &n30_blue_led_pdata, - }, -}; - -static struct platform_device n35_blue_led = { - .name = "s3c24xx_led", - .id = 1, - .dev = { - .platform_data = &n35_blue_led_pdata, - }, -}; - -static struct platform_device n30_warning_led = { - .name = "s3c24xx_led", - .id = 2, - .dev = { - .platform_data = &n30_warning_led_pdata, - }, -}; - -static struct platform_device n35_warning_led = { - .name = "s3c24xx_led", - .id = 2, - .dev = { - .platform_data = &n35_warning_led_pdata, - }, -}; - -static struct s3c2410fb_display n30_display __initdata = { - .type = S3C2410_LCDCON1_TFT, - .width = 240, - .height = 320, - .pixclock = 170000, - - .xres = 240, - .yres = 320, - .bpp = 16, - .left_margin = 3, - .right_margin = 40, - .hsync_len = 40, - .upper_margin = 2, - .lower_margin = 3, - .vsync_len = 2, - - .lcdcon5 = S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME, -}; - -static struct s3c2410fb_mach_info n30_fb_info __initdata = { - .displays = &n30_display, - .num_displays = 1, - .default_display = 0, - .lpcsel = 0x06, -}; - -static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd) -{ - switch (power_mode) { - case MMC_POWER_ON: - case MMC_POWER_UP: - gpio_set_value(S3C2410_GPG(4), 1); - break; - case MMC_POWER_OFF: - default: - gpio_set_value(S3C2410_GPG(4), 0); - break; - } -} - -static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = { - .gpio_detect = S3C2410_GPF(1), - .gpio_wprotect = S3C2410_GPG(10), - .ocr_avail = MMC_VDD_32_33, - .set_power = n30_sdi_set_power, -}; - -static struct platform_device *n30_devices[] __initdata = { - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_iis, - &s3c_device_ohci, - &s3c_device_rtc, - &s3c_device_usbgadget, - &s3c_device_sdi, - &n30_button_device, - &n30_blue_led, - &n30_warning_led, -}; - -static struct platform_device *n35_devices[] __initdata = { - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_iis, - &s3c_device_rtc, - &s3c_device_usbgadget, - &s3c_device_sdi, - &n35_button_device, - &n35_blue_led, - &n35_warning_led, -}; - -static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { - .flags = 0, - .slave_addr = 0x10, - .frequency = 10*1000, -}; - -/* Lots of hardcoded stuff, but it sets up the hardware in a useful - * state so that we can boot Linux directly from flash. */ -static void __init n30_hwinit(void) -{ - /* GPA0-11 special functions -- unknown what they do - * GPA12 N30 special function -- unknown what it does - * N35/PiN output -- unknown what it does - * - * A12 is nGCS1 on the N30 and an output on the N35/PiN. I - * don't think it does anything useful on the N30, so I ought - * to make it an output there too since it always driven to 0 - * as far as I can tell. */ - if (machine_is_n30()) - __raw_writel(0x007fffff, S3C2410_GPACON); - if (machine_is_n35()) - __raw_writel(0x007fefff, S3C2410_GPACON); - __raw_writel(0x00000000, S3C2410_GPADAT); - - /* GPB0 TOUT0 backlight level - * GPB1 output 1=backlight on - * GPB2 output IrDA enable 0=transceiver enabled, 1=disabled - * GPB3 output USB D+ pull up 0=disabled, 1=enabled - * GPB4 N30 output -- unknown function - * N30/PiN GPS control 0=GPS enabled, 1=GPS disabled - * GPB5 output -- unknown function - * GPB6 input -- unknown function - * GPB7 output -- unknown function - * GPB8 output -- probably LCD driver enable - * GPB9 output -- probably LCD VSYNC driver enable - * GPB10 output -- probably LCD HSYNC driver enable - */ - __raw_writel(0x00154556, S3C2410_GPBCON); - __raw_writel(0x00000750, S3C2410_GPBDAT); - __raw_writel(0x00000073, S3C2410_GPBUP); - - /* GPC0 input RS232 DCD/DSR/RI - * GPC1 LCD - * GPC2 output RS232 DTR? - * GPC3 input RS232 DCD/DSR/RI - * GPC4 LCD - * GPC5 output 0=NAND write enabled, 1=NAND write protect - * GPC6 input -- unknown function - * GPC7 input charger status 0=charger connected - * this input can be triggered by power on the USB device - * port too, but will go back to disconnected soon after. - * GPC8 N30/N35 output -- unknown function, always driven to 1 - * PiN input -- unknown function, always read as 1 - * Make it an input with a pull up for all models. - * GPC9-15 LCD - */ - __raw_writel(0xaaa80618, S3C2410_GPCCON); - __raw_writel(0x0000014c, S3C2410_GPCDAT); - __raw_writel(0x0000fef2, S3C2410_GPCUP); - - /* GPD0 input -- unknown function - * GPD1-D7 LCD - * GPD8 N30 output -- unknown function - * N35/PiN output 1=GPS LED on - * GPD9 output 0=power led blinks red, 1=normal power led function - * GPD10 output -- unknown function - * GPD11-15 LCD drivers - */ - __raw_writel(0xaa95aaa4, S3C2410_GPDCON); - __raw_writel(0x00000601, S3C2410_GPDDAT); - __raw_writel(0x0000fbfe, S3C2410_GPDUP); - - /* GPE0-4 I2S audio bus - * GPE5-10 SD/MMC bus - * E11-13 outputs -- unknown function, probably power management - * E14-15 I2C bus connected to the battery controller - */ - __raw_writel(0xa56aaaaa, S3C2410_GPECON); - __raw_writel(0x0000efc5, S3C2410_GPEDAT); - __raw_writel(0x0000f81f, S3C2410_GPEUP); - - /* GPF0 input 0=power button pressed - * GPF1 input SD/MMC switch 0=card present - * GPF2 N30 1=reset button pressed (inverted compared to the rest) - * N35/PiN 0=reset button pressed - * GPF3 N30/PiN input -- unknown function - * N35 input GPS antenna position, 0=antenna closed, 1=open - * GPF4 input 0=button 4 pressed - * GPF5 input 0=button 3 pressed - * GPF6 input 0=button 2 pressed - * GPF7 input 0=button 1 pressed - */ - __raw_writel(0x0000aaaa, S3C2410_GPFCON); - __raw_writel(0x00000000, S3C2410_GPFDAT); - __raw_writel(0x000000ff, S3C2410_GPFUP); - - /* GPG0 input RS232 DCD/DSR/RI - * GPG1 input 1=USB gadget port has power from a host - * GPG2 N30 input -- unknown function - * N35/PiN input 0=headphones plugged in, 1=not plugged in - * GPG3 N30 output -- unknown function - * N35/PiN input with unknown function - * GPG4 N30 output 0=MMC enabled, 1=MMC disabled - * GPG5 N30 output 0=BlueTooth chip disabled, 1=enabled - * N35/PiN input joystick right - * GPG6 N30 output 0=blue led on, 1=off - * N35/PiN input joystick left - * GPG7 input 0=thumbwheel pressed - * GPG8 input 0=thumbwheel down - * GPG9 input 0=thumbwheel up - * GPG10 input SD/MMC write protect switch - * GPG11 N30 input -- unknown function - * N35 output 0=GPS antenna powered, 1=not powered - * PiN output -- unknown function - * GPG12-15 touch screen functions - * - * The pullups differ between the models, so enable all - * pullups that are enabled on any of the models. - */ - if (machine_is_n30()) - __raw_writel(0xff0a956a, S3C2410_GPGCON); - if (machine_is_n35()) - __raw_writel(0xff4aa92a, S3C2410_GPGCON); - __raw_writel(0x0000e800, S3C2410_GPGDAT); - __raw_writel(0x0000f86f, S3C2410_GPGUP); - - /* GPH0/1/2/3 RS232 serial port - * GPH4/5 IrDA serial port - * GPH6/7 N30 BlueTooth serial port - * N35/PiN GPS receiver - * GPH8 input -- unknown function - * GPH9 CLKOUT0 HCLK -- unknown use - * GPH10 CLKOUT1 FCLK -- unknown use - * - * The pull ups for H6/H7 are enabled on N30 but not on the - * N35/PiN. I suppose is useful for a budget model of the N30 - * with no bluetooh. It doesn't hurt to have the pull ups - * enabled on the N35, so leave them enabled for all models. - */ - __raw_writel(0x0028aaaa, S3C2410_GPHCON); - __raw_writel(0x000005ef, S3C2410_GPHDAT); - __raw_writel(0x0000063f, S3C2410_GPHUP); -} - -static void __init n30_map_io(void) -{ - s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc)); - n30_hwinit(); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); -} - -/* GPB3 is the line that controls the pull-up for the USB D+ line */ - -static void __init n30_init(void) -{ - WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power")); - - s3c24xx_fb_set_platdata(&n30_fb_info); - s3c24xx_udc_set_platdata(&n30_udc_cfg); - s3c24xx_mci_set_platdata(&n30_mci_cfg); - s3c_i2c0_set_platdata(&n30_i2ccfg); - - /* Turn off suspend on both USB ports, and switch the - * selectable USB port to USB device mode. */ - - s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | - S3C2410_MISCCR_USBSUSPND0 | - S3C2410_MISCCR_USBSUSPND1, 0x0); - - if (machine_is_n30()) { - /* Turn off suspend on both USB ports, and switch the - * selectable USB port to USB device mode. */ - s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | - S3C2410_MISCCR_USBSUSPND0 | - S3C2410_MISCCR_USBSUSPND1, 0x0); - - platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices)); - } - - if (machine_is_n35()) { - /* Turn off suspend and switch the selectable USB port - * to USB device mode. Turn on suspend for the host - * port since it is not connected on the N35. - * - * Actually, the host port is available at some pads - * on the back of the device, so it would actually be - * possible to add a USB device inside the N35 if you - * are willing to do some hardware modifications. */ - s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | - S3C2410_MISCCR_USBSUSPND0 | - S3C2410_MISCCR_USBSUSPND1, - S3C2410_MISCCR_USBSUSPND0); - - platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); - } -} - -MACHINE_START(N30, "Acer-N30") - /* Maintainer: Christer Weinigel <christer@weinigel.se>, - Ben Dooks <ben-linux@fluff.org> - */ - .atag_offset = 0x100, - .timer = &s3c24xx_timer, - .init_machine = n30_init, - .init_irq = s3c24xx_init_irq, - .map_io = n30_map_io, - .restart = s3c2410_restart, -MACHINE_END - -MACHINE_START(N35, "Acer-N35") - /* Maintainer: Christer Weinigel <christer@weinigel.se> - */ - .atag_offset = 0x100, - .timer = &s3c24xx_timer, - .init_machine = n30_init, - .init_irq = s3c24xx_init_irq, - .map_io = n30_map_io, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c deleted file mode 100644 index 5f1e0eeb38a..00000000000 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ /dev/null @@ -1,127 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-otom.c - * - * Copyright (c) 2004 Nex Vision - * Guillaume GOURAT <guillaume.gourat@nexvision.fr> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/otom-map.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <mach/regs-gpio.h> - -#include <plat/s3c2410.h> -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/iic.h> -#include <plat/cpu.h> - -#include "common.h" - -static struct map_desc otom11_iodesc[] __initdata = { - /* Device area */ - { (u32)OTOM_VA_CS8900A_BASE, OTOM_PA_CS8900A_BASE, SZ_16M, MT_DEVICE }, -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - /* port 2 is not actually used */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -/* NOR Flash on NexVision OTOM board */ - -static struct resource otom_nor_resource[] = { - [0] = { - .start = S3C2410_CS0, - .end = S3C2410_CS0 + (4*1024*1024) - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device otom_device_nor = { - .name = "mtd-flash", - .id = -1, - .num_resources = ARRAY_SIZE(otom_nor_resource), - .resource = otom_nor_resource, -}; - -/* Standard OTOM devices */ - -static struct platform_device *otom11_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_iis, - &s3c_device_rtc, - &otom_device_nor, -}; - -static void __init otom11_map_io(void) -{ - s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); -} - -static void __init otom11_init(void) -{ - s3c_i2c0_set_platdata(NULL); - platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); -} - -MACHINE_START(OTOM, "Nex Vision - Otom 1.1") - /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */ - .atag_offset = 0x100, - .map_io = otom11_map_io, - .init_machine = otom11_init, - .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c deleted file mode 100644 index 91c16d9d245..00000000000 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ /dev/null @@ -1,356 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-qt2410.c - * - * Copyright (C) 2006 by OpenMoko, Inc. - * Author: Harald Welte <laforge@openmoko.org> - * All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/spi/spi.h> -#include <linux/spi/spi_gpio.h> -#include <linux/io.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/partitions.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <mach/regs-gpio.h> -#include <mach/leds-gpio.h> -#include <mach/regs-lcd.h> -#include <plat/regs-serial.h> -#include <mach/fb.h> -#include <plat/nand.h> -#include <plat/udc.h> -#include <plat/iic.h> - -#include <plat/common-smdk.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/pm.h> - -#include "common.h" - -static struct map_desc qt2410_iodesc[] __initdata = { - { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk2410_uartcfgs[] = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -/* LCD driver info */ - -static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = { - { - /* Configuration for 640x480 SHARP LQ080V3DG01 */ - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - - .type = S3C2410_LCDCON1_TFT, - .width = 640, - .height = 480, - - .pixclock = 40000, /* HCLK/4 */ - .xres = 640, - .yres = 480, - .bpp = 16, - .left_margin = 44, - .right_margin = 116, - .hsync_len = 96, - .upper_margin = 19, - .lower_margin = 11, - .vsync_len = 15, - }, - { - /* Configuration for 480x640 toppoly TD028TTEC1 */ - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - - .type = S3C2410_LCDCON1_TFT, - .width = 480, - .height = 640, - .pixclock = 40000, /* HCLK/4 */ - .xres = 480, - .yres = 640, - .bpp = 16, - .left_margin = 8, - .right_margin = 24, - .hsync_len = 8, - .upper_margin = 2, - .lower_margin = 4, - .vsync_len = 2, - }, - { - /* Config for 240x320 LCD */ - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - - .type = S3C2410_LCDCON1_TFT, - .width = 240, - .height = 320, - .pixclock = 100000, /* HCLK/10 */ - .xres = 240, - .yres = 320, - .bpp = 16, - .left_margin = 13, - .right_margin = 8, - .hsync_len = 4, - .upper_margin = 2, - .lower_margin = 7, - .vsync_len = 4, - }, -}; - - -static struct s3c2410fb_mach_info qt2410_fb_info __initdata = { - .displays = qt2410_lcd_cfg, - .num_displays = ARRAY_SIZE(qt2410_lcd_cfg), - .default_display = 0, - - .lpcsel = ((0xCE6) & ~7) | 1<<4, -}; - -/* CS8900 */ - -static struct resource qt2410_cs89x0_resources[] = { - [0] = { - .start = 0x19000000, - .end = 0x19000000 + 16, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EINT9, - .end = IRQ_EINT9, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device qt2410_cs89x0 = { - .name = "cirrus-cs89x0", - .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources), - .resource = qt2410_cs89x0_resources, -}; - -/* LED */ - -static struct s3c24xx_led_platdata qt2410_pdata_led = { - .gpio = S3C2410_GPB(0), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .name = "led", - .def_trigger = "timer", -}; - -static struct platform_device qt2410_led = { - .name = "s3c24xx_led", - .id = 0, - .dev = { - .platform_data = &qt2410_pdata_led, - }, -}; - -/* SPI */ - -static struct spi_gpio_platform_data spi_gpio_cfg = { - .sck = S3C2410_GPG(7), - .mosi = S3C2410_GPG(6), - .miso = S3C2410_GPG(5), -}; - -static struct platform_device qt2410_spi = { - .name = "spi-gpio", - .id = 1, - .dev.platform_data = &spi_gpio_cfg, -}; - -/* Board devices */ - -static struct platform_device *qt2410_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_iis, - &s3c_device_sdi, - &s3c_device_usbgadget, - &qt2410_spi, - &qt2410_cs89x0, - &qt2410_led, -}; - -static struct mtd_partition __initdata qt2410_nand_part[] = { - [0] = { - .name = "U-Boot", - .size = 0x30000, - .offset = 0, - }, - [1] = { - .name = "U-Boot environment", - .offset = 0x30000, - .size = 0x4000, - }, - [2] = { - .name = "kernel", - .offset = 0x34000, - .size = SZ_2M, - }, - [3] = { - .name = "initrd", - .offset = 0x234000, - .size = SZ_4M, - }, - [4] = { - .name = "jffs2", - .offset = 0x634000, - .size = 0x39cc000, - }, -}; - -static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = { - [0] = { - .name = "NAND", - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(qt2410_nand_part), - .partitions = qt2410_nand_part, - }, -}; - -/* choose a set of timings which should suit most 512Mbit - * chips and beyond. - */ - -static struct s3c2410_platform_nand __initdata qt2410_nand_info = { - .tacls = 20, - .twrph0 = 60, - .twrph1 = 20, - .nr_sets = ARRAY_SIZE(qt2410_nand_sets), - .sets = qt2410_nand_sets, -}; - -/* UDC */ - -static struct s3c2410_udc_mach_info qt2410_udc_cfg = { -}; - -static char tft_type = 's'; - -static int __init qt2410_tft_setup(char *str) -{ - tft_type = str[0]; - return 1; -} - -__setup("tft=", qt2410_tft_setup); - -static void __init qt2410_map_io(void) -{ - s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); - s3c24xx_init_clocks(12*1000*1000); - s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); -} - -static void __init qt2410_machine_init(void) -{ - s3c_nand_set_platdata(&qt2410_nand_info); - - switch (tft_type) { - case 'p': /* production */ - qt2410_fb_info.default_display = 1; - break; - case 'b': /* big */ - qt2410_fb_info.default_display = 0; - break; - case 's': /* small */ - default: - qt2410_fb_info.default_display = 2; - break; - } - s3c24xx_fb_set_platdata(&qt2410_fb_info); - - s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB(0), 1); - - s3c24xx_udc_set_platdata(&qt2410_udc_cfg); - s3c_i2c0_set_platdata(NULL); - - WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs")); - gpio_direction_output(S3C2410_GPB(5), 1); - - platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); - s3c_pm_init(); -} - -MACHINE_START(QT2410, "QT2410") - .atag_offset = 0x100, - .map_io = qt2410_map_io, - .init_irq = s3c24xx_init_irq, - .init_machine = qt2410_machine_init, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c deleted file mode 100644 index bdc27e77287..00000000000 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ /dev/null @@ -1,122 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-smdk2410.c - * - * linux/arch/arm/mach-s3c2410/mach-smdk2410.c - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH - * All rights reserved. - * - * @Author: Jonas Dietsche - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * @History: - * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by - * Ben Dooks <ben@simtec.co.uk> - * - ***********************************************************************/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <plat/iic.h> - -#include <plat/devs.h> -#include <plat/cpu.h> - -#include <plat/common-smdk.h> - -#include "common.h" - -static struct map_desc smdk2410_iodesc[] __initdata = { - /* nothing here yet */ -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -static struct platform_device *smdk2410_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_iis, -}; - -static void __init smdk2410_map_io(void) -{ - s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); -} - -static void __init smdk2410_init(void) -{ - s3c_i2c0_set_platdata(NULL); - platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); - smdk_machine_init(); -} - -MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch - * to SMDK2410 */ - /* Maintainer: Jonas Dietsche */ - .atag_offset = 0x100, - .map_io = smdk2410_map_io, - .init_irq = s3c24xx_init_irq, - .init_machine = smdk2410_init, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c deleted file mode 100644 index 1114666f0ef..00000000000 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c +++ /dev/null @@ -1,157 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-tct_hammer.c - * - * Copyright (c) 2007 TinCanTools - * David Anders <danders@amltd.com> - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * @History: - * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by - * Ben Dooks <ben@simtec.co.uk> - * - ***********************************************************************/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/flash.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/map.h> -#include <linux/mtd/physmap.h> - -#include "common.h" - -static struct resource tct_hammer_nor_resource = { - .start = 0x00000000, - .end = 0x01000000 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct mtd_partition tct_hammer_mtd_partitions[] = { - { - .name = "System", - .size = 0x240000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - .name = "JFFS2", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data tct_hammer_flash_data = { - .width = 2, - .parts = tct_hammer_mtd_partitions, - .nr_parts = ARRAY_SIZE(tct_hammer_mtd_partitions), -}; - -static struct platform_device tct_hammer_device_nor = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &tct_hammer_flash_data, - }, - .num_resources = 1, - .resource = &tct_hammer_nor_resource, -}; - -static struct map_desc tct_hammer_iodesc[] __initdata = { -}; - -#define UCON S3C2410_UCON_DEFAULT -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - - -static struct platform_device *tct_hammer_devices[] __initdata = { - &s3c_device_adc, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_ohci, - &s3c_device_rtc, - &s3c_device_usbgadget, - &s3c_device_sdi, - &tct_hammer_device_nor, -}; - -static void __init tct_hammer_map_io(void) -{ - s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); -} - -static void __init tct_hammer_init(void) -{ - s3c_i2c0_set_platdata(NULL); - platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); -} - -MACHINE_START(TCT_HAMMER, "TCT_HAMMER") - .atag_offset = 0x100, - .map_io = tct_hammer_map_io, - .init_irq = s3c24xx_init_irq, - .init_machine = tct_hammer_init, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c deleted file mode 100644 index dbe668a803e..00000000000 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ /dev/null @@ -1,386 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/mach-vr1000.c - * - * Copyright (c) 2003-2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine support for Thorcom VR1000 board. Designed for Thorcom by - * Simtec Electronics, http://www.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/dm9000.h> -#include <linux/i2c.h> - -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_8250.h> -#include <linux/serial_reg.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/bast-map.h> -#include <mach/vr1000-map.h> -#include <mach/vr1000-irq.h> -#include <mach/vr1000-cpld.h> - -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <mach/regs-gpio.h> -#include <mach/leds-gpio.h> - -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/iic.h> -#include <plat/audio-simtec.h> - -#include "usb-simtec.h" -#include "nor-simtec.h" -#include "common.h" - -/* macros for virtual address mods for the io space entries */ -#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) -#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4) -#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3) -#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2) - -/* macros to modify the physical addresses for io space */ - -#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2)) -#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3)) -#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4)) -#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5)) - -static struct map_desc vr1000_iodesc[] __initdata = { - /* ISA IO areas */ - { - .virtual = (u32)S3C24XX_VA_ISA_BYTE, - .pfn = PA_CS2(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = (u32)S3C24XX_VA_ISA_WORD, - .pfn = PA_CS3(BAST_PA_ISAIO), - .length = SZ_16M, - .type = MT_DEVICE, - }, - - /* CPLD control registers, and external interrupt controls */ - { - .virtual = (u32)VR1000_VA_CTRL1, - .pfn = __phys_to_pfn(VR1000_PA_CTRL1), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)VR1000_VA_CTRL2, - .pfn = __phys_to_pfn(VR1000_PA_CTRL2), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)VR1000_VA_CTRL3, - .pfn = __phys_to_pfn(VR1000_PA_CTRL3), - .length = SZ_1M, - .type = MT_DEVICE, - }, { - .virtual = (u32)VR1000_VA_CTRL4, - .pfn = __phys_to_pfn(VR1000_PA_CTRL4), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - -#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK -#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB -#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE - -static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - }, - /* port 2 is not actually used */ - [2] = { - .hwport = 2, - .flags = 0, - .ucon = UCON, - .ulcon = ULCON, - .ufcon = UFCON, - } -}; - -/* definitions for the vr1000 extra 16550 serial ports */ - -#define VR1000_BAUDBASE (3692307) - -#define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5)) - -static struct plat_serial8250_port serial_platform_data[] = { - [0] = { - .mapbase = VR1000_SERIAL_MAPBASE(0), - .irq = IRQ_VR1000_SERIAL + 0, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = VR1000_BAUDBASE, - }, - [1] = { - .mapbase = VR1000_SERIAL_MAPBASE(1), - .irq = IRQ_VR1000_SERIAL + 1, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = VR1000_BAUDBASE, - }, - [2] = { - .mapbase = VR1000_SERIAL_MAPBASE(2), - .irq = IRQ_VR1000_SERIAL + 2, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = VR1000_BAUDBASE, - }, - [3] = { - .mapbase = VR1000_SERIAL_MAPBASE(3), - .irq = IRQ_VR1000_SERIAL + 3, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = VR1000_BAUDBASE, - }, - { }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -/* DM9000 ethernet devices */ - -static struct resource vr1000_dm9k0_resource[] = { - [0] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 3, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = IRQ_VR1000_DM9000A, - .end = IRQ_VR1000_DM9000A, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - } - -}; - -static struct resource vr1000_dm9k1_resource[] = { - [0] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83, - .flags = IORESOURCE_MEM - }, - [1] = { - .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, - .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF, - .flags = IORESOURCE_MEM - }, - [2] = { - .start = IRQ_VR1000_DM9000N, - .end = IRQ_VR1000_DM9000N, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - } -}; - -/* for the moment we limit ourselves to 16bit IO until some - * better IO routines can be written and tested -*/ - -static struct dm9000_plat_data vr1000_dm9k_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device vr1000_dm9k0 = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(vr1000_dm9k0_resource), - .resource = vr1000_dm9k0_resource, - .dev = { - .platform_data = &vr1000_dm9k_platdata, - } -}; - -static struct platform_device vr1000_dm9k1 = { - .name = "dm9000", - .id = 1, - .num_resources = ARRAY_SIZE(vr1000_dm9k1_resource), - .resource = vr1000_dm9k1_resource, - .dev = { - .platform_data = &vr1000_dm9k_platdata, - } -}; - -/* LEDS */ - -static struct s3c24xx_led_platdata vr1000_led1_pdata = { - .name = "led1", - .gpio = S3C2410_GPB(0), - .def_trigger = "", -}; - -static struct s3c24xx_led_platdata vr1000_led2_pdata = { - .name = "led2", - .gpio = S3C2410_GPB(1), - .def_trigger = "", -}; - -static struct s3c24xx_led_platdata vr1000_led3_pdata = { - .name = "led3", - .gpio = S3C2410_GPB(2), - .def_trigger = "", -}; - -static struct platform_device vr1000_led1 = { - .name = "s3c24xx_led", - .id = 1, - .dev = { - .platform_data = &vr1000_led1_pdata, - }, -}; - -static struct platform_device vr1000_led2 = { - .name = "s3c24xx_led", - .id = 2, - .dev = { - .platform_data = &vr1000_led2_pdata, - }, -}; - -static struct platform_device vr1000_led3 = { - .name = "s3c24xx_led", - .id = 3, - .dev = { - .platform_data = &vr1000_led3_pdata, - }, -}; - -/* I2C devices. */ - -static struct i2c_board_info vr1000_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, { - I2C_BOARD_INFO("tmp101", 0x48), - }, { - I2C_BOARD_INFO("m41st87", 0x68), - }, -}; - -/* devices for this board */ - -static struct platform_device *vr1000_devices[] __initdata = { - &s3c_device_ohci, - &s3c_device_lcd, - &s3c_device_wdt, - &s3c_device_i2c0, - &s3c_device_adc, - &serial_device, - &vr1000_dm9k0, - &vr1000_dm9k1, - &vr1000_led1, - &vr1000_led2, - &vr1000_led3, -}; - -static struct clk *vr1000_clocks[] __initdata = { - &s3c24xx_dclk0, - &s3c24xx_dclk1, - &s3c24xx_clkout0, - &s3c24xx_clkout1, - &s3c24xx_uclk, -}; - -static void vr1000_power_off(void) -{ - gpio_direction_output(S3C2410_GPB(9), 1); -} - -static void __init vr1000_map_io(void) -{ - /* initialise clock sources */ - - s3c24xx_dclk0.parent = &clk_upll; - s3c24xx_dclk0.rate = 12*1000*1000; - - s3c24xx_dclk1.parent = NULL; - s3c24xx_dclk1.rate = 3692307; - - s3c24xx_clkout0.parent = &s3c24xx_dclk0; - s3c24xx_clkout1.parent = &s3c24xx_dclk1; - - s3c24xx_uclk.parent = &s3c24xx_clkout1; - - s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks)); - - pm_power_off = vr1000_power_off; - - s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); - s3c24xx_init_clocks(0); - s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); -} - -static void __init vr1000_init(void) -{ - s3c_i2c0_set_platdata(NULL); - platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); - - i2c_register_board_info(0, vr1000_i2c_devs, - ARRAY_SIZE(vr1000_i2c_devs)); - - nor_simtec_init(); - simtec_audio_add(NULL, true, NULL); - - WARN_ON(gpio_request(S3C2410_GPB(9), "power off")); -} - -MACHINE_START(VR1000, "Thorcom-VR1000") - /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ - .atag_offset = 0x100, - .map_io = vr1000_map_io, - .init_machine = vr1000_init, - .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, - .restart = s3c2410_restart, -MACHINE_END diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c deleted file mode 100644 index ad9f750f1e5..00000000000 --- a/arch/arm/mach-s3c2410/nor-simtec.c +++ /dev/null @@ -1,87 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/nor-simtec.c - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * Simtec NOR mapping - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/map.h> -#include <mach/bast-map.h> -#include <mach/bast-cpld.h> - -#include "nor-simtec.h" - -static void simtec_nor_vpp(struct platform_device *pdev, int vpp) -{ - unsigned int val; - unsigned long flags; - - local_irq_save(flags); - val = __raw_readb(BAST_VA_CTRL3); - - printk(KERN_DEBUG "%s(%d)\n", __func__, vpp); - - if (vpp) - val |= BAST_CPLD_CTRL3_ROMWEN; - else - val &= ~BAST_CPLD_CTRL3_ROMWEN; - - __raw_writeb(val, BAST_VA_CTRL3); - local_irq_restore(flags); -} - -static struct physmap_flash_data simtec_nor_pdata = { - .width = 2, - .set_vpp = simtec_nor_vpp, - .nr_parts = 0, -}; - -static struct resource simtec_nor_resource[] = { - [0] = { - .start = S3C2410_CS1 + 0x4000000, - .end = S3C2410_CS1 + 0x4000000 + SZ_8M - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device simtec_device_nor = { - .name = "physmap-flash", - .id = -1, - .num_resources = ARRAY_SIZE(simtec_nor_resource), - .resource = simtec_nor_resource, - .dev = { - .platform_data = &simtec_nor_pdata, - }, -}; - -void __init nor_simtec_init(void) -{ - int ret; - - ret = platform_device_register(&simtec_device_nor); - if (ret < 0) - printk(KERN_ERR "failed to register physmap-flash device\n"); - else - simtec_nor_vpp(NULL, 1); -} diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c2410/nor-simtec.h deleted file mode 100644 index f619c1e0d0c..00000000000 --- a/arch/arm/mach-s3c2410/nor-simtec.h +++ /dev/null @@ -1,14 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/nor-simtec.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * Simtec NOR mapping - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern void nor_simtec_init(void); diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c index c07438bfc99..e0b3b347da8 100644 --- a/arch/arm/mach-s3c2410/pll.c +++ b/arch/arm/mach-s3c2410/pll.c @@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = { { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, }; -static int s3c2410_plls_add(struct device *dev) +static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) { return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); } diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S deleted file mode 100644 index c93bf2db9f4..00000000000 --- a/arch/arm/mach-s3c2410/pm-h1940.S +++ /dev/null @@ -1,33 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/pm-h1940.S - * - * Copyright (c) 2006 Ben Dooks <ben-linux@fluff.org> - * - * H1940 Suspend to RAM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/map.h> - -#include <mach/regs-gpio.h> - - .text - .global h1940_pm_return - -h1940_pm_return: - mov r0, #S3C2410_PA_GPIO - ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ] diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c deleted file mode 100644 index fda5385deff..00000000000 --- a/arch/arm/mach-s3c2410/pm.c +++ /dev/null @@ -1,180 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/pm.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/suspend.h> -#include <linux/errno.h> -#include <linux/time.h> -#include <linux/device.h> -#include <linux/syscore_ops.h> -#include <linux/gpio.h> -#include <linux/io.h> - -#include <mach/hardware.h> - -#include <asm/mach-types.h> - -#include <mach/regs-gpio.h> -#include <mach/h1940.h> - -#include <plat/cpu.h> -#include <plat/pm.h> - -static void s3c2410_pm_prepare(void) -{ - /* ensure at least GSTATUS3 has the resume address */ - - __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); - - S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); - S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); - - if (machine_is_h1940()) { - void *base = phys_to_virt(H1940_SUSPEND_CHECK); - unsigned long ptr; - unsigned long calc = 0; - - /* generate check for the bootloader to check on resume */ - - for (ptr = 0; ptr < 0x40000; ptr += 0x400) - calc += __raw_readl(base+ptr); - - __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); - } - - /* RX3715 and RX1950 use similar to H1940 code and the - * same offsets for resume and checksum pointers */ - - if (machine_is_rx3715() || machine_is_rx1950()) { - void *base = phys_to_virt(H1940_SUSPEND_CHECK); - unsigned long ptr; - unsigned long calc = 0; - - /* generate check for the bootloader to check on resume */ - - for (ptr = 0; ptr < 0x40000; ptr += 0x4) - calc += __raw_readl(base+ptr); - - __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); - } - - if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF(2), 1); - - if (machine_is_rx1950()) { - /* According to S3C2442 user's manual, page 7-17, - * when the system is operating in NAND boot mode, - * the hardware pin configuration - EINT[23:21] – - * must be set as input for starting up after - * wakeup from sleep mode - */ - s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT); - s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT); - s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT); - } -} - -static void s3c2410_pm_resume(void) -{ - unsigned long tmp; - - /* unset the return-from-sleep flag, to ensure reset */ - - tmp = __raw_readl(S3C2410_GSTATUS2); - tmp &= S3C2410_GSTATUS2_OFFRESET; - __raw_writel(tmp, S3C2410_GSTATUS2); - - if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF(2), 0); -} - -struct syscore_ops s3c2410_pm_syscore_ops = { - .resume = s3c2410_pm_resume, -}; - -static int s3c2410_pm_add(struct device *dev) -{ - pm_cpu_prep = s3c2410_pm_prepare; - pm_cpu_sleep = s3c2410_cpu_suspend; - - return 0; -} - -#if defined(CONFIG_CPU_S3C2410) -static struct subsys_interface s3c2410_pm_interface = { - .name = "s3c2410_pm", - .subsys = &s3c2410_subsys, - .add_dev = s3c2410_pm_add, -}; - -/* register ourselves */ - -static int __init s3c2410_pm_drvinit(void) -{ - return subsys_interface_register(&s3c2410_pm_interface); -} - -arch_initcall(s3c2410_pm_drvinit); - -static struct subsys_interface s3c2410a_pm_interface = { - .name = "s3c2410a_pm", - .subsys = &s3c2410a_subsys, - .add_dev = s3c2410_pm_add, -}; - -static int __init s3c2410a_pm_drvinit(void) -{ - return subsys_interface_register(&s3c2410a_pm_interface); -} - -arch_initcall(s3c2410a_pm_drvinit); -#endif - -#if defined(CONFIG_CPU_S3C2440) -static struct subsys_interface s3c2440_pm_interface = { - .name = "s3c2440_pm", - .subsys = &s3c2440_subsys, - .add_dev = s3c2410_pm_add, -}; - -static int __init s3c2440_pm_drvinit(void) -{ - return subsys_interface_register(&s3c2440_pm_interface); -} - -arch_initcall(s3c2440_pm_drvinit); -#endif - -#if defined(CONFIG_CPU_S3C2442) -static struct subsys_interface s3c2442_pm_interface = { - .name = "s3c2442_pm", - .subsys = &s3c2442_subsys, - .add_dev = s3c2410_pm_add, -}; - -static int __init s3c2442_pm_drvinit(void) -{ - return subsys_interface_register(&s3c2442_pm_interface); -} - -arch_initcall(s3c2442_pm_drvinit); -#endif diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c deleted file mode 100644 index 061b6bb1a55..00000000000 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ /dev/null @@ -1,206 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/s3c2410.c - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://www.simtec.co.uk/products/EB2410ITX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/device.h> -#include <linux/syscore_ops.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <plat/cpu-freq.h> - -#include <mach/regs-clock.h> -#include <plat/regs-serial.h> - -#include <plat/s3c2410.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/clock.h> -#include <plat/pll.h> -#include <plat/pm.h> -#include <plat/watchdog-reset.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -/* Initial IO mappings */ - -static struct map_desc s3c2410_iodesc[] __initdata = { - IODESC_ENT(CLKPWR), - IODESC_ENT(TIMER), - IODESC_ENT(WATCHDOG), -}; - -/* our uart devices */ - -/* uart registration process */ - -void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no); -} - -/* s3c2410_map_io - * - * register the standard cpu IO areas, and any passed in from the - * machine specific initialisation. -*/ - -void __init s3c2410_map_io(void) -{ - s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; - s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; - - iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); -} - -void __init_or_cpufreq s3c2410_setup_clocks(void) -{ - struct clk *xtal_clk; - unsigned long tmp; - unsigned long xtal; - unsigned long fclk; - unsigned long hclk; - unsigned long pclk; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - /* now we've got our machine bits initialised, work out what - * clocks we've got */ - - fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); - - tmp = __raw_readl(S3C2410_CLKDIVN); - - /* work out clock scalings */ - - hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); - pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); - - /* print brieft summary of clocks, etc */ - - printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - /* initialise the clocks here, to allow other things like the - * console to use them - */ - - s3c24xx_setup_clocks(fclk, hclk, pclk); -} - -/* fake ARMCLK for use with cpufreq, etc. */ - -static struct clk s3c2410_armclk = { - .name = "armclk", - .parent = &clk_f, - .id = -1, -}; - -static struct clk_lookup s3c2410_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), -}; - -void __init s3c2410_init_clocks(int xtal) -{ - s3c24xx_register_baseclocks(xtal); - s3c2410_setup_clocks(); - s3c2410_baseclk_add(); - s3c24xx_register_clock(&s3c2410_armclk); - clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); -} - -struct bus_type s3c2410_subsys = { - .name = "s3c2410-core", - .dev_name = "s3c2410-core", -}; - -/* Note, we would have liked to name this s3c2410-core, but we cannot - * register two subsystems with the same name. - */ -struct bus_type s3c2410a_subsys = { - .name = "s3c2410a-core", - .dev_name = "s3c2410a-core", -}; - -static struct device s3c2410_dev = { - .bus = &s3c2410_subsys, -}; - -/* need to register the subsystem before we actually register the device, and - * we also need to ensure that it has been initialised before any of the - * drivers even try to use it (even if not on an s3c2410 based system) - * as a driver which may support both 2410 and 2440 may try and use it. -*/ - -static int __init s3c2410_core_init(void) -{ - return subsys_system_register(&s3c2410_subsys, NULL); -} - -core_initcall(s3c2410_core_init); - -static int __init s3c2410a_core_init(void) -{ - return subsys_system_register(&s3c2410a_subsys, NULL); -} - -core_initcall(s3c2410a_core_init); - -int __init s3c2410_init(void) -{ - printk("S3C2410: Initialising architecture\n"); - -#ifdef CONFIG_PM - register_syscore_ops(&s3c2410_pm_syscore_ops); -#endif - register_syscore_ops(&s3c24xx_irq_syscore_ops); - - return device_register(&s3c2410_dev); -} - -int __init s3c2410a_init(void) -{ - s3c2410_dev.bus = &s3c2410a_subsys; - return s3c2410_init(); -} - -void s3c2410_restart(char mode, const char *cmd) -{ - if (mode == 's') { - soft_restart(0); - } - - arch_wdt_reset(); - - /* we'll take a jump through zero as a poor second */ - soft_restart(0); -} diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S deleted file mode 100644 index dd5b6388a5a..00000000000 --- a/arch/arm/mach-s3c2410/sleep.S +++ /dev/null @@ -1,68 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/sleep.S - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 Power Manager (Suspend-To-RAM) support - * - * Based on PXA/SA1100 sleep code by: - * Nicolas Pitre, (c) 2002 Monta Vista Software Inc - * Cliff Brake, (c) 2001 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/map.h> - -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> -#include <mach/regs-mem.h> -#include <plat/regs-serial.h> - - /* s3c2410_cpu_suspend - * - * put the cpu into sleep mode - */ - -ENTRY(s3c2410_cpu_suspend) - @@ prepare cpu to sleep - - ldr r4, =S3C2410_REFRESH - ldr r5, =S3C24XX_MISCCR - ldr r6, =S3C2410_CLKCON - ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) - ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) - ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) - - orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command - orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals - orr r9, r9, #S3C2410_CLKCON_POWER @ power down command - - teq pc, #0 @ first as a trial-run to load cache - bl s3c2410_do_sleep - teq r0, r0 @ now do it for real - b s3c2410_do_sleep @ - - @@ align next bit of code to cache line - .align 5 -s3c2410_do_sleep: - streq r7, [ r4 ] @ SDRAM sleep command - streq r8, [ r5 ] @ SDRAM power-down config - streq r9, [ r6 ] @ CPU sleep -1: beq 1b - mov pc, r14 diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c deleted file mode 100644 index 29bd3d987be..00000000000 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ /dev/null @@ -1,132 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/usb-simtec.c - * - * Copyright 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://www.simtec.co.uk/products/EB2410ITX/ - * - * Simtec BAST and Thorcom VR1000 USB port support functions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define DEBUG - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/gpio.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/bast-map.h> -#include <mach/bast-irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <plat/usb-control.h> -#include <plat/devs.h> - -#include "usb-simtec.h" - -/* control power and monitor over-current events on various Simtec - * designed boards. -*/ - -static unsigned int power_state[2]; - -static void -usb_simtec_powercontrol(int port, int to) -{ - pr_debug("usb_simtec_powercontrol(%d,%d)\n", port, to); - - power_state[port] = to; - - if (power_state[0] && power_state[1]) - gpio_set_value(S3C2410_GPB(4), 0); - else - gpio_set_value(S3C2410_GPB(4), 1); -} - -static irqreturn_t -usb_simtec_ocirq(int irq, void *pw) -{ - struct s3c2410_hcd_info *info = pw; - - if (gpio_get_value(S3C2410_GPG(10)) == 0) { - pr_debug("usb_simtec: over-current irq (oc detected)\n"); - s3c2410_usb_report_oc(info, 3); - } else { - pr_debug("usb_simtec: over-current irq (oc cleared)\n"); - s3c2410_usb_report_oc(info, 0); - } - - return IRQ_HANDLED; -} - -static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) -{ - int ret; - - if (on) { - ret = request_irq(IRQ_USBOC, usb_simtec_ocirq, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, - "USB Over-current", info); - if (ret != 0) { - printk(KERN_ERR "failed to request usb oc irq\n"); - } - } else { - free_irq(IRQ_USBOC, info); - } -} - -static struct s3c2410_hcd_info usb_simtec_info __initdata = { - .port[0] = { - .flags = S3C_HCDFLG_USED - }, - .port[1] = { - .flags = S3C_HCDFLG_USED - }, - - .power_control = usb_simtec_powercontrol, - .enable_oc = usb_simtec_enableoc, -}; - - -int usb_simtec_init(void) -{ - int ret; - - printk("USB Power Control, Copyright 2004 Simtec Electronics\n"); - - ret = gpio_request(S3C2410_GPB(4), "USB power control"); - if (ret < 0) { - pr_err("%s: failed to get GPB4\n", __func__); - return ret; - } - - ret = gpio_request(S3C2410_GPG(10), "USB overcurrent"); - if (ret < 0) { - pr_err("%s: failed to get GPG10\n", __func__); - gpio_free(S3C2410_GPB(4)); - return ret; - } - - /* turn power on */ - gpio_direction_output(S3C2410_GPB(4), 1); - gpio_direction_input(S3C2410_GPG(10)); - - s3c_ohci_set_platdata(&usb_simtec_info); - return 0; -} diff --git a/arch/arm/mach-s3c2410/usb-simtec.h b/arch/arm/mach-s3c2410/usb-simtec.h deleted file mode 100644 index 03842ede9e7..00000000000 --- a/arch/arm/mach-s3c2410/usb-simtec.h +++ /dev/null @@ -1,16 +0,0 @@ -/* linux/arch/arm/mach-s3c2410/usb-simtec.h - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://www.simtec.co.uk/products/EB2410ITX/ - * - * Simtec BAST and Thorcom VR1000 USB port support functions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -extern int usb_simtec_init(void); - |