diff options
Diffstat (limited to 'arch/arm/mach-s3c2443/clock.c')
| -rw-r--r-- | arch/arm/mach-s3c2443/clock.c | 62 |
1 files changed, 32 insertions, 30 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 603b5ea1dea..2785d69c95b 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -29,7 +29,6 @@ #include <linux/sysdev.h> #include <linux/clk.h> #include <linux/mutex.h> -#include <linux/delay.h> #include <linux/serial_core.h> #include <linux/io.h> @@ -39,9 +38,11 @@ #include <mach/regs-s3c2443-clock.h> -#include <asm/plat-s3c24xx/s3c2443.h> -#include <asm/plat-s3c24xx/clock.h> -#include <asm/plat-s3c24xx/cpu.h> +#include <plat/cpu-freq.h> + +#include <plat/s3c2443.h> +#include <plat/clock.h> +#include <plat/cpu.h> /* We currently have to assume that the system is running * from the XTPll input, and that all ***REFCLKs are being @@ -145,12 +146,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk, /* clock selections */ -/* CPU EXTCLK input */ -static struct clk clk_ext = { - .name = "ext", - .id = -1, -}; - static struct clk clk_mpllref = { .name = "mpllref", .parent = &clk_xtal, @@ -165,14 +160,6 @@ static struct clk clk_mpll = { }; #endif -static struct clk clk_epllref; - -static struct clk clk_epll = { - .name = "epll", - .parent = &clk_epllref, - .id = -1, -}; - static struct clk clk_i2s_ext = { .name = "i2s-ext", .id = -1, @@ -1011,39 +998,52 @@ static struct clk *clks[] __initdata = { &clk_prediv, }; -void __init s3c2443_init_clocks(int xtal) +void __init_or_cpufreq s3c2443_setup_clocks(void) { - unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); + struct clk *xtal_clk; + unsigned long xtal; unsigned long pll; unsigned long fclk; unsigned long hclk; unsigned long pclk; - struct clk *clkp; - int ret; - int ptr; - /* s3c2443 parents h and p clocks from prediv */ - clk_h.parent = &clk_prediv; - clk_p.parent = &clk_prediv; + xtal_clk = clk_get(NULL, "xtal"); + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); pll = s3c2443_get_mpll(mpllcon, xtal); clk_msysclk.rate = pll; fclk = pll / s3c2443_fclk_div(clkdiv0); hclk = s3c2443_prediv_getrate(&clk_prediv); - hclk = hclk / s3c2443_get_hdiv(clkdiv0); - hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1); + hclk /= s3c2443_get_hdiv(clkdiv0); pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c24xx_setup_clocks(fclk, hclk, pclk); printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(pll), print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + s3c24xx_setup_clocks(fclk, hclk, pclk); +} + +void __init s3c2443_init_clocks(int xtal) +{ + struct clk *clkp; + unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); + int ret; + int ptr; + + /* s3c2443 parents h and p clocks from prediv */ + clk_h.parent = &clk_prediv; + clk_p.parent = &clk_prediv; + + s3c24xx_register_baseclocks(xtal); + s3c2443_setup_clocks(); s3c2443_clk_initparents(); for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { @@ -1057,7 +1057,7 @@ void __init s3c2443_init_clocks(int xtal) } clk_epll.rate = s3c2443_get_epll(epllcon, xtal); - + clk_epll.parent = &clk_epllref; clk_usb_bus.parent = &clk_usb_bus_host; /* ensure usb bus clock is within correct rate of 48MHz */ @@ -1106,4 +1106,6 @@ void __init s3c2443_init_clocks(int xtal) (clkp->enable)(clkp, 0); } + + s3c_pwmclk_init(); } |