diff options
Diffstat (limited to 'arch/arm/mach-s3c24xx/irq.c')
| -rw-r--r-- | arch/arm/mach-s3c24xx/irq.c | 154 |
1 files changed, 154 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c index ddb6752e594..2bb4a97e527 100644 --- a/arch/arm/mach-s3c24xx/irq.c +++ b/arch/arm/mach-s3c24xx/irq.c @@ -626,6 +626,160 @@ void __init s3c24xx_init_irq(void) s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); } +#ifdef CONFIG_CPU_S3C2412 + +#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) +#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) + +/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by + * having them turn up in both the INT* and the EINT* registers. Whilst + * both show the status, they both now need to be acked when the IRQs + * go off. +*/ + +static void +s3c2412_irq_mask(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask | bitval, S3C2410_INTMSK); + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask | bitval, S3C2412_EINTMASK); +} + +static inline void +s3c2412_irq_ack(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + + __raw_writel(bitval, S3C2412_EINTPEND); + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static inline void +s3c2412_irq_maskack(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask|bitval, S3C2410_INTMSK); + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask | bitval, S3C2412_EINTMASK); + + __raw_writel(bitval, S3C2412_EINTPEND); + __raw_writel(bitval, S3C2410_SRCPND); + __raw_writel(bitval, S3C2410_INTPND); +} + +static void +s3c2412_irq_unmask(struct irq_data *data) +{ + unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); + unsigned long mask; + + mask = __raw_readl(S3C2412_EINTMASK); + __raw_writel(mask & ~bitval, S3C2412_EINTMASK); + + mask = __raw_readl(S3C2410_INTMSK); + __raw_writel(mask & ~bitval, S3C2410_INTMSK); +} + +static struct irq_chip s3c2412_irq_eint0t4 = { + .irq_ack = s3c2412_irq_ack, + .irq_mask = s3c2412_irq_mask, + .irq_unmask = s3c2412_irq_unmask, + .irq_set_wake = s3c_irq_wake, + .irq_set_type = s3c_irqext_type, +}; + +#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) + +/* CF and SDI sub interrupts */ + +static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + + if (subsrc & INTBIT(IRQ_S3C2412_SDI)) + generic_handle_irq(IRQ_S3C2412_SDI); + + if (subsrc & INTBIT(IRQ_S3C2412_CF)) + generic_handle_irq(IRQ_S3C2412_CF); +} + +#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) +#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) + +static void s3c2412_irq_cfsdi_mask(struct irq_data *data) +{ + s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_unmask(struct irq_data *data) +{ + s3c_irqsub_unmask(data->irq, INTMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_ack(struct irq_data *data) +{ + s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static struct irq_chip s3c2412_irq_cfsdi = { + .name = "s3c2412-cfsdi", + .irq_ack = s3c2412_irq_cfsdi_ack, + .irq_mask = s3c2412_irq_cfsdi_mask, + .irq_unmask = s3c2412_irq_cfsdi_unmask, +}; + +static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif) +{ + unsigned int irqno; + + for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { + irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, + handle_edge_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + /* add demux support for CF/SDI */ + + irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + + for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { + irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, + handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct subsys_interface s3c2412_irq_interface = { + .name = "s3c2412_irq", + .subsys = &s3c2412_subsys, + .add_dev = s3c2412_irq_add, +}; + +static int s3c2412_irq_init(void) +{ + return subsys_interface_register(&s3c2412_irq_interface); +} + +arch_initcall(s3c2412_irq_init); +#endif + #ifdef CONFIG_CPU_S3C2416 static struct s3c_irq_data init_s3c2416base[32] = { { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ |