diff options
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r-- | arch/arm/mach-s5pv210/Kconfig | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/clock.c | 174 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/cpu.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/cpufreq.c | 485 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/dev-audio.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/dev-spi.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/map.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/pm-core.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/regs-audss.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/regs-fb.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/mach-aquila.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/mach-goni.c | 12 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/mach-smdkv210.c | 57 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/pm.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/setup-fb-24bpp.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/sleep.S | 21 |
18 files changed, 114 insertions, 701 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 37b5a97594a..69dd87cd8e2 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -90,6 +90,7 @@ config MACH_GONI select S3C_DEV_HSMMC2 select S3C_DEV_I2C1 select S3C_DEV_I2C2 + select S5P_DEV_MFC select S3C_DEV_USB_HSOTG select S5P_DEV_ONENAND select SAMSUNG_DEV_KEYPAD @@ -134,6 +135,7 @@ config MACH_SMDKV210 select S3C_DEV_RTC select S3C_DEV_WDT select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_IDE select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_PWM diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 50907aca006..599a3c0e8f6 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -15,7 +15,6 @@ obj- := obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o -obj-$(CONFIG_CPU_FREQ) += cpufreq.o # machine support diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 2d599499cef..52a8e607bcc 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -36,7 +36,6 @@ static unsigned long xtal; static struct clksrc_clk clk_mout_apll = { .clk = { .name = "mout_apll", - .id = -1, }, .sources = &clk_src_apll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, @@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", - .id = -1, }, .sources = &clk_src_epll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, @@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", - .id = -1, }, .sources = &clk_src_mpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, @@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = { static struct clksrc_clk clk_armclk = { .clk = { .name = "armclk", - .id = -1, }, .sources = &clkset_armclk, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, @@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_hclk_msys = { .clk = { .name = "hclk_msys", - .id = -1, .parent = &clk_armclk.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, @@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = { static struct clksrc_clk clk_pclk_msys = { .clk = { .name = "pclk_msys", - .id = -1, .parent = &clk_hclk_msys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, @@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = { static struct clksrc_clk clk_sclk_a2m = { .clk = { .name = "sclk_a2m", - .id = -1, .parent = &clk_mout_apll.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, @@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = { static struct clksrc_clk clk_hclk_dsys = { .clk = { .name = "hclk_dsys", - .id = -1, }, .sources = &clkset_hclk_sys, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, @@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = { static struct clksrc_clk clk_pclk_dsys = { .clk = { .name = "pclk_dsys", - .id = -1, .parent = &clk_hclk_dsys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, @@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = { static struct clksrc_clk clk_hclk_psys = { .clk = { .name = "hclk_psys", - .id = -1, }, .sources = &clkset_hclk_sys, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, @@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = { static struct clksrc_clk clk_pclk_psys = { .clk = { .name = "pclk_psys", - .id = -1, .parent = &clk_hclk_psys.clk, }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, @@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", - .id = -1, .rate = 27000000, }; static struct clk clk_sclk_hdmiphy = { .name = "sclk_hdmiphy", - .id = -1, }; static struct clk clk_sclk_usbphy0 = { .name = "sclk_usbphy0", - .id = -1, }; static struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", - .id = -1, }; static struct clk clk_pcmcdclk0 = { .name = "pcmcdclk", - .id = -1, }; static struct clk clk_pcmcdclk1 = { .name = "pcmcdclk", - .id = -1, }; static struct clk clk_pcmcdclk2 = { .name = "pcmcdclk", - .id = -1, }; static struct clk *clkset_vpllsrc_list[] = { @@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = { static struct clksrc_clk clk_vpllsrc = { .clk = { .name = "vpll_src", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 7), }, @@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = { .clk = { .name = "sclk_vpll", - .id = -1, }, .sources = &clkset_sclk_vpll, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, @@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = { static struct clksrc_clk clk_mout_dmc0 = { .clk = { .name = "mout_dmc0", - .id = -1, }, .sources = &clkset_moutdmc0src, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, @@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = { static struct clksrc_clk clk_sclk_dmc0 = { .clk = { .name = "sclk_dmc0", - .id = -1, .parent = &clk_mout_dmc0.clk, }, .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, @@ -312,181 +290,175 @@ static struct clk_ops clk_fout_apll_ops = { static struct clk init_clocks_off[] = { { .name = "pdma", - .id = 0, + .devname = "s3c-pl330.0", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 3), }, { .name = "pdma", - .id = 1, + .devname = "s3c-pl330.1", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 4), }, { .name = "rot", - .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1<<29), }, { .name = "fimc", - .id = 0, + .devname = "s5pv210-fimc.0", .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 24), }, { .name = "fimc", - .id = 1, + .devname = "s5pv210-fimc.1", .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 25), }, { .name = "fimc", - .id = 2, + .devname = "s5pv210-fimc.2", .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 26), }, { + .name = "mfc", + .devname = "s5p-mfc", + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 16), + }, { .name = "otg", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<16), }, { .name = "usb-host", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { .name = "lcd", - .id = -1, .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<0), }, { .name = "cfcon", - .id = 0, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { .name = "hsmmc", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<16), }, { .name = "hsmmc", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<17), }, { .name = "hsmmc", - .id = 2, + .devname = "s3c-sdhci.2", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<18), }, { .name = "hsmmc", - .id = 3, + .devname = "s3c-sdhci.3", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<19), }, { .name = "systimer", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { .name = "watchdog", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<22), }, { .name = "rtc", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<15), }, { .name = "i2c", - .id = 0, + .devname = "s3c2440-i2c.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "i2c", - .id = 1, + .devname = "s3c2440-i2c.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 10), }, { .name = "i2c", - .id = 2, + .devname = "s3c2440-i2c.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { .name = "spi", - .id = 0, + .devname = "s3c64xx-spi.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", - .id = 1, + .devname = "s3c64xx-spi.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", - .id = 2, + .devname = "s3c64xx-spi.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), }, { .name = "timers", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<23), }, { .name = "adc", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<24), }, { .name = "keypad", - .id = -1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<21), }, { .name = "iis", - .id = 0, + .devname = "samsung-i2s.0", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<4), }, { .name = "iis", - .id = 1, + .devname = "samsung-i2s.1", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 5), }, { .name = "iis", - .id = 2, + .devname = "samsung-i2s.2", .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 6), }, { .name = "spdif", - .id = -1, .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 0), @@ -496,38 +468,36 @@ static struct clk init_clocks_off[] = { static struct clk init_clocks[] = { { .name = "hclk_imem", - .id = -1, .parent = &clk_hclk_msys.clk, .ctrlbit = (1 << 5), .enable = s5pv210_clk_ip0_ctrl, .ops = &clk_hclk_imem_ops, }, { .name = "uart", - .id = 0, + .devname = "s5pv210-uart.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 17), }, { .name = "uart", - .id = 1, + .devname = "s5pv210-uart.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 18), }, { .name = "uart", - .id = 2, + .devname = "s5pv210-uart.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 19), }, { .name = "uart", - .id = 3, + .devname = "s5pv210-uart.3", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 20), }, { .name = "sromc", - .id = -1, .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1 << 26), @@ -579,7 +549,6 @@ static struct clksrc_sources clkset_sclk_dac = { static struct clksrc_clk clk_sclk_dac = { .clk = { .name = "sclk_dac", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 2), }, @@ -590,7 +559,6 @@ static struct clksrc_clk clk_sclk_dac = { static struct clksrc_clk clk_sclk_pixel = { .clk = { .name = "sclk_pixel", - .id = -1, .parent = &clk_sclk_vpll.clk, }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, @@ -609,7 +577,6 @@ static struct clksrc_sources clkset_sclk_hdmi = { static struct clksrc_clk clk_sclk_hdmi = { .clk = { .name = "sclk_hdmi", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 0), }, @@ -647,7 +614,7 @@ static struct clksrc_sources clkset_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "sclk_audio", - .id = 0, + .devname = "soc-audio.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 24), }, @@ -676,7 +643,7 @@ static struct clksrc_sources clkset_sclk_audio1 = { static struct clksrc_clk clk_sclk_audio1 = { .clk = { .name = "sclk_audio", - .id = 1, + .devname = "soc-audio.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 25), }, @@ -705,7 +672,7 @@ static struct clksrc_sources clkset_sclk_audio2 = { static struct clksrc_clk clk_sclk_audio2 = { .clk = { .name = "sclk_audio", - .id = 2, + .devname = "soc-audio.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 26), }, @@ -725,48 +692,12 @@ static struct clksrc_sources clkset_sclk_spdif = { .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), }; -static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate) -{ - struct clk *pclk; - int ret; - - pclk = clk_get_parent(clk); - if (IS_ERR(pclk)) - return -EINVAL; - - ret = pclk->ops->set_rate(pclk, rate); - clk_put(pclk); - - return ret; -} - -static unsigned long s5pv210_spdif_get_rate(struct clk *clk) -{ - struct clk *pclk; - int rate; - - pclk = clk_get_parent(clk); - if (IS_ERR(pclk)) - return -EINVAL; - - rate = pclk->ops->get_rate(clk); - clk_put(pclk); - - return rate; -} - -static struct clk_ops s5pv210_sclk_spdif_ops = { - .set_rate = s5pv210_spdif_set_rate, - .get_rate = s5pv210_spdif_get_rate, -}; - static struct clksrc_clk clk_sclk_spdif = { .clk = { .name = "sclk_spdif", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 27), - .ops = &s5pv210_sclk_spdif_ops, + .ops = &s5p_sclk_spdif_ops, }, .sources = &clkset_sclk_spdif, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, @@ -793,7 +724,6 @@ static struct clksrc_clk clksrcs[] = { { .clk = { .name = "sclk_dmc", - .id = -1, }, .sources = &clkset_group1, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, @@ -801,7 +731,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_onenand", - .id = -1, }, .sources = &clkset_sclk_onenand, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, @@ -809,7 +738,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 0, + .devname = "s5pv210-uart.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 12), }, @@ -819,7 +748,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 1, + .devname = "s5pv210-uart.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 13), }, @@ -829,7 +758,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 2, + .devname = "s5pv210-uart.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 14), }, @@ -839,7 +768,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "uclk1", - .id = 3, + .devname = "s5pv210-uart.3", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 15), }, @@ -849,7 +778,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mixer", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 1), }, @@ -858,7 +786,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 0, + .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 2), }, @@ -868,7 +796,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 1, + .devname = "s5pv210-fimc.1", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 3), }, @@ -878,7 +806,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimc", - .id = 2, + .devname = "s5pv210-fimc.2", .enable = s5pv210_clk_mask1_ctrl, .ctrlbit = (1 << 4), }, @@ -888,7 +816,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_cam", - .id = 0, + .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 3), }, @@ -898,7 +826,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_cam", - .id = 1, + .devname = "s5pv210-fimc.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 4), }, @@ -908,7 +836,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_fimd", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 5), }, @@ -918,7 +845,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 0, + .devname = "s3c-sdhci.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 8), }, @@ -928,7 +855,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 1, + .devname = "s3c-sdhci.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 9), }, @@ -938,7 +865,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 2, + .devname = "s3c-sdhci.2", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 10), }, @@ -948,7 +875,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mmc", - .id = 3, + .devname = "s3c-sdhci.3", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 11), }, @@ -958,7 +885,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_mfc", - .id = -1, + .devname = "s5p-mfc", .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 16), }, @@ -968,7 +895,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_g2d", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 12), }, @@ -978,7 +904,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_g3d", - .id = -1, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 8), }, @@ -988,7 +913,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_csis", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 6), }, @@ -998,7 +922,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 0, + .devname = "s3c64xx-spi.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 16), }, @@ -1008,7 +932,7 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_spi", - .id = 1, + .devname = "s3c64xx-spi.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 17), }, @@ -1018,7 +942,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwi", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 29), }, @@ -1028,7 +951,6 @@ static struct clksrc_clk clksrcs[] = { }, { .clk = { .name = "sclk_pwm", - .id = -1, .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 19), }, diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 61e6c24b90a..79907ec78d4 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -126,7 +126,7 @@ void __init s5pv210_map_io(void) s5pv210_default_sdhci2(); s5pv210_default_sdhci3(); - s3c_adc_setname("s3c64xx-adc"); + s3c_adc_setname("samsung-adc-v3"); s3c_cfcon_setname("s5pv210-pata"); diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c deleted file mode 100644 index 153af8b359e..00000000000 --- a/arch/arm/mach-s5pv210/cpufreq.c +++ /dev/null @@ -1,485 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/cpufreq.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * CPU frequency scaling for S5PC110/S5PV210 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/cpufreq.h> - -#include <mach/map.h> -#include <mach/regs-clock.h> - -static struct clk *cpu_clk; -static struct clk *dmc0_clk; -static struct clk *dmc1_clk; -static struct cpufreq_freqs freqs; - -/* APLL M,P,S values for 1G/800Mhz */ -#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1) -#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1) - -/* - * DRAM configurations to calculate refresh counter for changing - * frequency of memory. - */ -struct dram_conf { - unsigned long freq; /* HZ */ - unsigned long refresh; /* DRAM refresh counter * 1000 */ -}; - -/* DRAM configuration (DMC0 and DMC1) */ -static struct dram_conf s5pv210_dram_conf[2]; - -enum perf_level { - L0, L1, L2, L3, L4, -}; - -enum s5pv210_mem_type { - LPDDR = 0x1, - LPDDR2 = 0x2, - DDR2 = 0x4, -}; - -enum s5pv210_dmc_port { - DMC0 = 0, - DMC1, -}; - -static struct cpufreq_frequency_table s5pv210_freq_table[] = { - {L0, 1000*1000}, - {L1, 800*1000}, - {L2, 400*1000}, - {L3, 200*1000}, - {L4, 100*1000}, - {0, CPUFREQ_TABLE_END}, -}; - -static u32 clkdiv_val[5][11] = { - /* - * Clock divider value for following - * { APLL, A2M, HCLK_MSYS, PCLK_MSYS, - * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, - * ONEDRAM, MFC, G3D } - */ - - /* L0 : [1000/200/100][166/83][133/66][200/200] */ - {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0}, - - /* L1 : [800/200/100][166/83][133/66][200/200] */ - {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0}, - - /* L2 : [400/200/100][166/83][133/66][200/200] */ - {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, - - /* L3 : [200/200/100][166/83][133/66][200/200] */ - {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, - - /* L4 : [100/100/100][83/83][66/66][100/100] */ - {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0}, -}; - -/* - * This function set DRAM refresh counter - * accoriding to operating frequency of DRAM - * ch: DMC port number 0 or 1 - * freq: Operating frequency of DRAM(KHz) - */ -static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq) -{ - unsigned long tmp, tmp1; - void __iomem *reg = NULL; - - if (ch == DMC0) { - reg = (S5P_VA_DMC0 + 0x30); - } else if (ch == DMC1) { - reg = (S5P_VA_DMC1 + 0x30); - } else { - printk(KERN_ERR "Cannot find DMC port\n"); - return; - } - - /* Find current DRAM frequency */ - tmp = s5pv210_dram_conf[ch].freq; - - do_div(tmp, freq); - - tmp1 = s5pv210_dram_conf[ch].refresh; - - do_div(tmp1, tmp); - - __raw_writel(tmp1, reg); -} - -int s5pv210_verify_speed(struct cpufreq_policy *policy) -{ - if (policy->cpu) - return -EINVAL; - - return cpufreq_frequency_table_verify(policy, s5pv210_freq_table); -} - -unsigned int s5pv210_getspeed(unsigned int cpu) -{ - if (cpu) - return 0; - - return clk_get_rate(cpu_clk) / 1000; -} - -static int s5pv210_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - unsigned long reg; - unsigned int index, priv_index; - unsigned int pll_changing = 0; - unsigned int bus_speed_changing = 0; - - freqs.old = s5pv210_getspeed(0); - - if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, - target_freq, relation, &index)) - return -EINVAL; - - freqs.new = s5pv210_freq_table[index].frequency; - freqs.cpu = 0; - - if (freqs.new == freqs.old) - return 0; - - /* Finding current running level index */ - if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, - freqs.old, relation, &priv_index)) - return -EINVAL; - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - - if (freqs.new > freqs.old) { - /* Voltage up: will be implemented */ - } - - /* Check if there need to change PLL */ - if ((index == L0) || (priv_index == L0)) - pll_changing = 1; - - /* Check if there need to change System bus clock */ - if ((index == L4) || (priv_index == L4)) - bus_speed_changing = 1; - - if (bus_speed_changing) { - /* - * Reconfigure DRAM refresh counter value for minimum - * temporary clock while changing divider. - * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 - */ - if (pll_changing) - s5pv210_set_refresh(DMC1, 83000); - else - s5pv210_set_refresh(DMC1, 100000); - - s5pv210_set_refresh(DMC0, 83000); - } - - /* - * APLL should be changed in this level - * APLL -> MPLL(for stable transition) -> APLL - * Some clock source's clock API are not prepared. - * Do not use clock API in below code. - */ - if (pll_changing) { - /* - * 1. Temporary Change divider for MFC and G3D - * SCLKA2M(200/1=200)->(200/4=50)Mhz - */ - reg = __raw_readl(S5P_CLK_DIV2); - reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); - reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) | - (3 << S5P_CLKDIV2_MFC_SHIFT); - __raw_writel(reg, S5P_CLK_DIV2); - - /* For MFC, G3D dividing */ - do { - reg = __raw_readl(S5P_CLKDIV_STAT0); - } while (reg & ((1 << 16) | (1 << 17))); - - /* - * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX - * (200/4=50)->(667/4=166)Mhz - */ - reg = __raw_readl(S5P_CLK_SRC2); - reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); - reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) | - (1 << S5P_CLKSRC2_MFC_SHIFT); - __raw_writel(reg, S5P_CLK_SRC2); - - do { - reg = __raw_readl(S5P_CLKMUX_STAT1); - } while (reg & ((1 << 7) | (1 << 3))); - - /* - * 3. DMC1 refresh count for 133Mhz if (index == L4) is - * true refresh counter is already programed in upper - * code. 0x287@83Mhz - */ - if (!bus_speed_changing) - s5pv210_set_refresh(DMC1, 133000); - - /* 4. SCLKAPLL -> SCLKMPLL */ - reg = __raw_readl(S5P_CLK_SRC0); - reg &= ~(S5P_CLKSRC0_MUX200_MASK); - reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT); - __raw_writel(reg, S5P_CLK_SRC0); - - do { - reg = __raw_readl(S5P_CLKMUX_STAT0); - } while (reg & (0x1 << 18)); - - } - - /* Change divider */ - reg = __raw_readl(S5P_CLK_DIV0); - - reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK | - S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK | - S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK | - S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK); - - reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) | - (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) | - (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) | - (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) | - (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) | - (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) | - (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) | - (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT)); - - __raw_writel(reg, S5P_CLK_DIV0); - - do { - reg = __raw_readl(S5P_CLKDIV_STAT0); - } while (reg & 0xff); - - /* ARM MCS value changed */ - reg = __raw_readl(S5P_ARM_MCS_CON); - reg &= ~0x3; - if (index >= L3) - reg |= 0x3; - else - reg |= 0x1; - - __raw_writel(reg, S5P_ARM_MCS_CON); - - if (pll_changing) { - /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ - __raw_writel(0x2cf, S5P_APLL_LOCK); - - /* - * 6. Turn on APLL - * 6-1. Set PMS values - * 6-2. Wait untile the PLL is locked - */ - if (index == L0) - __raw_writel(APLL_VAL_1000, S5P_APLL_CON); - else - __raw_writel(APLL_VAL_800, S5P_APLL_CON); - - do { - reg = __raw_readl(S5P_APLL_CON); - } while (!(reg & (0x1 << 29))); - - /* - * 7. Change souce clock from SCLKMPLL(667Mhz) - * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX - * (667/4=166)->(200/4=50)Mhz - */ - reg = __raw_readl(S5P_CLK_SRC2); - reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); - reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | - (0 << S5P_CLKSRC2_MFC_SHIFT); - __raw_writel(reg, S5P_CLK_SRC2); - - do { - reg = __raw_readl(S5P_CLKMUX_STAT1); - } while (reg & ((1 << 7) | (1 << 3))); - - /* - * 8. Change divider for MFC and G3D - * (200/4=50)->(200/1=200)Mhz - */ - reg = __raw_readl(S5P_CLK_DIV2); - reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); - reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) | - (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT); - __raw_writel(reg, S5P_CLK_DIV2); - - /* For MFC, G3D dividing */ - do { - reg = __raw_readl(S5P_CLKDIV_STAT0); - } while (reg & ((1 << 16) | (1 << 17))); - - /* 9. Change MPLL to APLL in MSYS_MUX */ - reg = __raw_readl(S5P_CLK_SRC0); - reg &= ~(S5P_CLKSRC0_MUX200_MASK); - reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); - __raw_writel(reg, S5P_CLK_SRC0); - - do { - reg = __raw_readl(S5P_CLKMUX_STAT0); - } while (reg & (0x1 << 18)); - - /* - * 10. DMC1 refresh counter - * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c - * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618 - */ - if (!bus_speed_changing) - s5pv210_set_refresh(DMC1, 200000); - } - - /* - * L4 level need to change memory bus speed, hence onedram clock divier - * and memory refresh parameter should be changed - */ - if (bus_speed_changing) { - reg = __raw_readl(S5P_CLK_DIV6); - reg &= ~S5P_CLKDIV6_ONEDRAM_MASK; - reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT); - __raw_writel(reg, S5P_CLK_DIV6); - - do { - reg = __raw_readl(S5P_CLKDIV_STAT1); - } while (reg & (1 << 15)); - - /* Reconfigure DRAM refresh counter value */ - if (index != L4) { - /* - * DMC0 : 166Mhz - * DMC1 : 200Mhz - */ - s5pv210_set_refresh(DMC0, 166000); - s5pv210_set_refresh(DMC1, 200000); - } else { - /* - * DMC0 : 83Mhz - * DMC1 : 100Mhz - */ - s5pv210_set_refresh(DMC0, 83000); - s5pv210_set_refresh(DMC1, 100000); - } - } - - if (freqs.new < freqs.old) { - /* Voltage down: will be implemented */ - } - - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - printk(KERN_DEBUG "Perf changed[L%d]\n", index); - - return 0; -} - -#ifdef CONFIG_PM -static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy) -{ - return 0; -} - -static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy) -{ - return 0; -} -#endif - -static int check_mem_type(void __iomem *dmc_reg) -{ - unsigned long val; - - val = __raw_readl(dmc_reg + 0x4); - val = (val & (0xf << 8)); - - return val >> 8; -} - -static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) -{ - unsigned long mem_type; - - cpu_clk = clk_get(NULL, "armclk"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - dmc0_clk = clk_get(NULL, "sclk_dmc0"); - if (IS_ERR(dmc0_clk)) { - clk_put(cpu_clk); - return PTR_ERR(dmc0_clk); - } - - dmc1_clk = clk_get(NULL, "hclk_msys"); - if (IS_ERR(dmc1_clk)) { - clk_put(dmc0_clk); - clk_put(cpu_clk); - return PTR_ERR(dmc1_clk); - } - - if (policy->cpu != 0) - return -EINVAL; - - /* - * check_mem_type : This driver only support LPDDR & LPDDR2. - * other memory type is not supported. - */ - mem_type = check_mem_type(S5P_VA_DMC0); - - if ((mem_type != LPDDR) && (mem_type != LPDDR2)) { - printk(KERN_ERR "CPUFreq doesn't support this memory type\n"); - return -EINVAL; - } - - /* Find current refresh counter and frequency each DMC */ - s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000); - s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk); - - s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000); - s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk); - - policy->cur = policy->min = policy->max = s5pv210_getspeed(0); - - cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu); - - policy->cpuinfo.transition_latency = 40000; - - return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table); -} - -static struct cpufreq_driver s5pv210_driver = { - .flags = CPUFREQ_STICKY, - .verify = s5pv210_verify_speed, - .target = s5pv210_target, - .get = s5pv210_getspeed, - .init = s5pv210_cpu_init, - .name = "s5pv210", -#ifdef CONFIG_PM - .suspend = s5pv210_cpufreq_suspend, - .resume = s5pv210_cpufreq_resume, -#endif -}; - -static int __init s5pv210_cpufreq_init(void) -{ - return cpufreq_register_driver(&s5pv210_driver); -} - -late_initcall(s5pv210_cpufreq_init); diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 8d58f192624..63f5d82004b 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -18,6 +18,7 @@ #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> +#include <mach/regs-audss.h> static const char *rclksrc[] = { [0] = "busclk", @@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = { .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR, .src_clk = rclksrc, + .idma_addr = S5PV210_AUDSS_INT_MEM, }, }, }; diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c index e3249a47e3b..eaf9a7bff7a 100644 --- a/arch/arm/mach-s5pv210/dev-spi.c +++ b/arch/arm/mach-s5pv210/dev-spi.c @@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = { .fifo_lvl_mask = 0x1ff, .rx_lvl_offset = 15, .high_speed = 1, + .tx_st_done = 25, }; static u64 spi_dmamask = DMA_BIT_MASK(32); @@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = { .fifo_lvl_mask = 0x7f, .rx_lvl_offset = 15, .high_speed = 1, + .tx_st_done = 25, }; struct platform_device s5pv210_device_spi1 = { diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h new file mode 100644 index 00000000000..7dffa83d23f --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_CLKDEV_H__ +#define __MACH_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do {} while (0) + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 1dd58836fd4..aac343c180b 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -59,6 +59,8 @@ #define S5PV210_PA_CFCON 0xE8200000 +#define S5PV210_PA_MFC 0xF1700000 + #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) #define S5PV210_PA_HSOTG 0xEC000000 @@ -107,6 +109,7 @@ #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS +#define S5P_PA_MFC S5PV210_PA_MFC #define S5P_PA_ONENAND S5PC110_PA_ONENAND #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA #define S5P_PA_SDRAM S5PV210_PA_SDRAM diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index e8d394f8b05..3e22109e1b7 100644 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, { /* nothing here yet */ } + +static inline void s3c_pm_restored_gpios(void) { } +static inline void s3c_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h new file mode 100644 index 00000000000..eacc1f79080 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s5pv210/include/mach/regs-audss.h + * + * Copyright (c) 2011 Samsung Electronics + * http://www.samsung.com + * + * S5PV210 Audio SubSystem clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_AUDSS_H +#define __PLAT_REGS_AUDSS_H __FILE__ + +#define S5PV210_AUDSS_INT_MEM (0xC0000000) + +#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h deleted file mode 100644 index 60d992989bd..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright 2010 Ben Dooks <ben-linux@fluff.org> - * - * Dummy framebuffer to allow build for the moment. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MACH_REGS_FB_H -#define __ASM_ARCH_MACH_REGS_FB_H __FILE__ - -#include <plat/regs-fb-v4.h> - -static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) -{ - return 0x2400 + (window * 256 *4 ) + reg; -} - -#endif /* __ASM_ARCH_MACH_REGS_FB_H */ diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 4e1d8ff5ae5..509627f2511 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -29,7 +29,6 @@ #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/regs-fb.h> #include <plat/gpio-cfg.h> #include <plat/regs-serial.h> @@ -40,6 +39,7 @@ #include <plat/fimc-core.h> #include <plat/sdhci.h> #include <plat/s5p-time.h> +#include <plat/regs-fb-v4.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 31d5aa76975..85c2d51a095 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -34,7 +34,6 @@ #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/regs-fb.h> #include <plat/gpio-cfg.h> #include <plat/regs-serial.h> @@ -47,6 +46,8 @@ #include <plat/sdhci.h> #include <plat/clock.h> #include <plat/s5p-time.h> +#include <plat/mfc.h> +#include <plat/regs-fb-v4.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -808,6 +809,9 @@ static struct platform_device *goni_devices[] __initdata = { &goni_i2c_gpio5, &mmc2_fixed_voltage, &goni_device_gpiokeys, + &s5p_device_mfc, + &s5p_device_mfc_l, + &s5p_device_mfc_r, &s3c_device_i2c0, &s5p_device_fimc0, &s5p_device_fimc1, @@ -841,6 +845,11 @@ static void __init goni_map_io(void) s5p_set_timer_source(S5P_PWM3, S5P_PWM4); } +static void __init goni_reserve(void) +{ + s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); +} + static void __init goni_machine_init(void) { /* Radio: call before I2C 1 registeration */ @@ -893,4 +902,5 @@ MACHINE_START(GONI, "GONI") .map_io = goni_map_io, .init_machine = goni_machine_init, .timer = &s5p_timer, + .reserve = &goni_reserve, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index c6a9e86c2d5..5e011fc6720 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -29,7 +29,6 @@ #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/regs-fb.h> #include <plat/regs-serial.h> #include <plat/regs-srom.h> @@ -45,6 +44,8 @@ #include <plat/pm.h> #include <plat/fb.h> #include <plat/s5p-time.h> +#include <plat/backlight.h> +#include <plat/regs-fb-v4.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -210,45 +211,6 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = { .setup_gpio = s5pv210_fb_gpio_setup_24bpp, }; -static int smdkv210_backlight_init(struct device *dev) -{ - int ret; - - ret = gpio_request(S5PV210_GPD0(3), "Backlight"); - if (ret) { - printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n"); - return ret; - } - - /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */ - s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2)); - - return 0; -} - -static void smdkv210_backlight_exit(struct device *dev) -{ - s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT); - gpio_free(S5PV210_GPD0(3)); -} - -static struct platform_pwm_backlight_data smdkv210_backlight_data = { - .pwm_id = 3, - .max_brightness = 255, - .dft_brightness = 255, - .pwm_period_ns = 78770, - .init = smdkv210_backlight_init, - .exit = smdkv210_backlight_exit, -}; - -static struct platform_device smdkv210_backlight_device = { - .name = "pwm-backlight", - .dev = { - .parent = &s3c_device_timer[3].dev, - .platform_data = &smdkv210_backlight_data, - }, -}; - static struct platform_device *smdkv210_devices[] __initdata = { &s3c_device_adc, &s3c_device_cfcon, @@ -267,11 +229,10 @@ static struct platform_device *smdkv210_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_spdif, &samsung_asoc_dma, + &samsung_asoc_idma, &samsung_device_keypad, &smdkv210_dm9000, &smdkv210_lcd_lte480wv, - &s3c_device_timer[3], - &smdkv210_backlight_device, }; static void __init smdkv210_dm9000_init(void) @@ -310,6 +271,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { .oversampling_shift = 2, }; +/* LCD Backlight data */ +static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = { + .no = S5PV210_GPD0(3), + .func = S3C_GPIO_SFN(2), +}; + +static struct platform_pwm_backlight_data smdkv210_bl_data = { + .pwm_id = 3, +}; + static void __init smdkv210_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -341,6 +312,8 @@ static void __init smdkv210_machine_init(void) s3c_fb_set_platdata(&smdkv210_lcd0_pdata); + samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data); + platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); } diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 24febae3d4c..f149d278377 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = { SAVE_ITEM(S3C2410_TCNTO(0)), }; -void s5pv210_cpu_suspend(void) +static int s5pv210_cpu_suspend(unsigned long arg) { unsigned long tmp; diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c index e932ebfac56..55103c8220b 100644 --- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c @@ -15,7 +15,6 @@ #include <linux/fb.h> #include <linux/gpio.h> -#include <mach/regs-fb.h> #include <mach/map.h> #include <plat/fb.h> #include <mach/regs-clock.h> diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index a3d649466fb..e3452ccd4b0 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -32,27 +32,6 @@ .text - /* s3c_cpu_save - * - * entry: - * r1 = v:p offset - */ - -ENTRY(s3c_cpu_save) - - stmfd sp!, { r3 - r12, lr } - ldr r3, =resume_with_mmu - bl cpu_suspend - - ldr r0, =pm_cpu_sleep - ldr r0, [ r0 ] - mov pc, r0 - -resume_with_mmu: - ldmfd sp!, { r3 - r12, pc } - - .ltorg - /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the * s3c_cpu_resume entry. |