diff options
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r-- | arch/arm/mach-s5pv210/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/Makefile | 7 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/clock.c | 833 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/cpu.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/dev-audio.c | 327 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/dma.c | 168 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/gpiolib.c | 261 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/dma.h | 26 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/gpio.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/map.h | 17 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/pwm-clock.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/mach-smdkc110.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/mach-smdkv210.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/setup-i2c0.c | 25 |
14 files changed, 1573 insertions, 137 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index af33a1a89b7..7601c28e240 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -12,6 +12,7 @@ if ARCH_S5PV210 config CPU_S5PV210 bool select PLAT_S5P + select S3C_PL330_DMA help Enable S5PV210 CPU support diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 8ebf51c52a0..99827813d29 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -12,9 +12,14 @@ obj- := # Core support for S5PV210 system -obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o +obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o +obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o # machine support obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o + +# device support + +obj-y += dev-audio.o diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index ccccae26235..154bca4abc0 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -31,6 +31,128 @@ #include <plat/clock-clksrc.h> #include <plat/s5pv210.h> +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, +}; + +static struct clk *clkset_armclk_list[] = { + [0] = &clk_mout_apll.clk, + [1] = &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clkset_armclk = { + .sources = clkset_armclk_list, + .nr_sources = ARRAY_SIZE(clkset_armclk_list), +}; + +static struct clksrc_clk clk_armclk = { + .clk = { + .name = "armclk", + .id = -1, + }, + .sources = &clkset_armclk, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk clk_hclk_msys = { + .clk = { + .name = "hclk_msys", + .id = -1, + .parent = &clk_armclk.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk clk_pclk_msys = { + .clk = { + .name = "pclk_msys", + .id = -1, + .parent = &clk_hclk_msys.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk clk_sclk_a2m = { + .clk = { + .name = "sclk_a2m", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, +}; + +static struct clk *clkset_hclk_sys_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_sclk_a2m.clk, +}; + +static struct clksrc_sources clkset_hclk_sys = { + .sources = clkset_hclk_sys_list, + .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list), +}; + +static struct clksrc_clk clk_hclk_dsys = { + .clk = { + .name = "hclk_dsys", + .id = -1, + }, + .sources = &clkset_hclk_sys, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk clk_pclk_dsys = { + .clk = { + .name = "pclk_dsys", + .id = -1, + .parent = &clk_hclk_dsys.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, +}; + +static struct clksrc_clk clk_hclk_psys = { + .clk = { + .name = "hclk_psys", + .id = -1, + }, + .sources = &clkset_hclk_sys, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, +}; + +static struct clksrc_clk clk_pclk_psys = { + .clk = { + .name = "pclk_psys", + .id = -1, + .parent = &clk_hclk_psys.clk, + }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, +}; + static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); @@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); } -static struct clk clk_h200 = { - .name = "hclk200", +static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); +} + +static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); +} + +static struct clk clk_sclk_hdmi27m = { + .name = "sclk_hdmi27m", .id = -1, + .rate = 27000000, }; -static struct clk clk_h100 = { - .name = "hclk100", +static struct clk clk_sclk_hdmiphy = { + .name = "sclk_hdmiphy", .id = -1, }; -static struct clk clk_h166 = { - .name = "hclk166", +static struct clk clk_sclk_usbphy0 = { + .name = "sclk_usbphy0", .id = -1, }; -static struct clk clk_h133 = { - .name = "hclk133", +static struct clk clk_sclk_usbphy1 = { + .name = "sclk_usbphy1", .id = -1, }; -static struct clk clk_p100 = { - .name = "pclk100", +static struct clk clk_pcmcdclk0 = { + .name = "pcmcdclk", .id = -1, }; -static struct clk clk_p83 = { - .name = "pclk83", +static struct clk clk_pcmcdclk1 = { + .name = "pcmcdclk", .id = -1, }; -static struct clk clk_p66 = { - .name = "pclk66", +static struct clk clk_pcmcdclk2 = { + .name = "pcmcdclk", .id = -1, }; -static struct clk *sys_clks[] = { - &clk_h200, - &clk_h100, - &clk_h166, - &clk_h133, - &clk_p100, - &clk_p83, - &clk_p66 +static struct clk *clkset_vpllsrc_list[] = { + [0] = &clk_fin_vpll, + [1] = &clk_sclk_hdmi27m, +}; + +static struct clksrc_sources clkset_vpllsrc = { + .sources = clkset_vpllsrc_list, + .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), +}; + +static struct clksrc_clk clk_vpllsrc = { + .clk = { + .name = "vpll_src", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 7), + }, + .sources = &clkset_vpllsrc, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, +}; + +static struct clk *clkset_sclk_vpll_list[] = { + [0] = &clk_vpllsrc.clk, + [1] = &clk_fout_vpll, +}; + +static struct clksrc_sources clkset_sclk_vpll = { + .sources = clkset_sclk_vpll_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), +}; + +static struct clksrc_clk clk_sclk_vpll = { + .clk = { + .name = "sclk_vpll", + .id = -1, + }, + .sources = &clkset_sclk_vpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, +}; + +static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static struct clk_ops clk_hclk_imem_ops = { + .get_rate = s5pv210_clk_imem_get_rate, }; static struct clk init_clocks_disable[] = { { .name = "rot", .id = -1, - .parent = &clk_h166, + .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1<<29), }, { .name = "otg", .id = -1, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<16), }, { .name = "usb-host", .id = -1, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<17), }, { .name = "lcd", .id = -1, - .parent = &clk_h166, + .parent = &clk_hclk_dsys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<0), }, { .name = "cfcon", .id = 0, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, .ctrlbit = (1<<25), }, { .name = "hsmmc", .id = 0, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<16), }, { .name = "hsmmc", .id = 1, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<17), }, { .name = "hsmmc", .id = 2, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<18), }, { .name = "hsmmc", .id = 3, - .parent = &clk_h133, + .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip2_ctrl, .ctrlbit = (1<<19), }, { .name = "systimer", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<16), }, { .name = "watchdog", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<22), }, { .name = "rtc", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<15), }, { .name = "i2c", .id = 0, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "i2c", .id = 1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<8), }, { .name = "i2c", .id = 2, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { .name = "spi", .id = 0, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", .id = 1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", .id = 2, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), }, { .name = "timers", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<23), }, { .name = "adc", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<24), }, { .name = "keypad", .id = -1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<21), }, { @@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = { static struct clk init_clocks[] = { { + .name = "hclk_imem", + .id = -1, + .parent = &clk_hclk_msys.clk, + .ctrlbit = (1 << 5), + .enable = s5pv210_clk_ip0_ctrl, + .ops = &clk_hclk_imem_ops, + }, { .name = "uart", .id = 0, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<7), }, { .name = "uart", .id = 1, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<8), }, { .name = "uart", .id = 2, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { .name = "uart", .id = 3, - .parent = &clk_p66, + .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<10), }, }; -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", +static struct clk *clkset_uart_list[] = { + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clk *clkset_group1_list[] = { + [0] = &clk_sclk_a2m.clk, + [1] = &clk_mout_mpll.clk, + [2] = &clk_mout_epll.clk, + [3] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_group1 = { + .sources = clkset_group1_list, + .nr_sources = ARRAY_SIZE(clkset_group1_list), +}; + +static struct clk *clkset_sclk_onenand_list[] = { + [0] = &clk_hclk_psys.clk, + [1] = &clk_hclk_dsys.clk, +}; + +static struct clksrc_sources clkset_sclk_onenand = { + .sources = clkset_sclk_onenand_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list), +}; + +static struct clk *clkset_sclk_dac_list[] = { + [0] = &clk_sclk_vpll.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_dac = { + .sources = clkset_sclk_dac_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), +}; + +static struct clksrc_clk clk_sclk_dac = { + .clk = { + .name = "sclk_dac", .id = -1, + .ctrlbit = (1 << 10), + .enable = s5pv210_clk_ip1_ctrl, }, - .sources = &clk_src_apll, - .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, + .sources = &clkset_sclk_dac, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, }; -static struct clksrc_clk clk_mout_epll = { - .clk = { - .name = "mout_epll", +static struct clksrc_clk clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", .id = -1, + .parent = &clk_sclk_vpll.clk, }, - .sources = &clk_src_epll, - .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, }; -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", +static struct clk *clkset_sclk_hdmi_list[] = { + [0] = &clk_sclk_pixel.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_hdmi = { + .sources = clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", .id = -1, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), }, - .sources = &clk_src_mpll, - .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, + .sources = &clkset_sclk_hdmi, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, }; -static struct clk *clkset_uart_list[] = { +static struct clk *clkset_sclk_mixer_list[] = { + [0] = &clk_sclk_dac.clk, + [1] = &clk_sclk_hdmi.clk, +}; + +static struct clksrc_sources clkset_sclk_mixer = { + .sources = clkset_sclk_mixer_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), +}; + +static struct clk *clkset_sclk_audio0_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_pcmcdclk0, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, [6] = &clk_mout_mpll.clk, [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, }; -static struct clksrc_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), +static struct clksrc_sources clkset_sclk_audio0 = { + .sources = clkset_sclk_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), +}; + +static struct clksrc_clk clk_sclk_audio0 = { + .clk = { + .name = "sclk_audio", + .id = 0, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_sclk_audio0, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, +}; + +static struct clk *clkset_sclk_audio1_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_pcmcdclk1, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio1 = { + .sources = clkset_sclk_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), +}; + +static struct clksrc_clk clk_sclk_audio1 = { + .clk = { + .name = "sclk_audio", + .id = 1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 5), + }, + .sources = &clkset_sclk_audio1, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 }, +}; + +static struct clk *clkset_sclk_audio2_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_pcmcdclk0, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_sclk_audio2 = { + .sources = clkset_sclk_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), +}; + +static struct clksrc_clk clk_sclk_audio2 = { + .clk = { + .name = "sclk_audio", + .id = 2, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 6), + }, + .sources = &clkset_sclk_audio2, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 }, +}; + +static struct clk *clkset_sclk_spdif_list[] = { + [0] = &clk_sclk_audio0.clk, + [1] = &clk_sclk_audio1.clk, + [2] = &clk_sclk_audio2.clk, +}; + +static struct clksrc_sources clkset_sclk_spdif = { + .sources = clkset_sclk_spdif_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), +}; + +static struct clk *clkset_group2_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_xusbxti, + [2] = &clk_sclk_hdmi27m, + [3] = &clk_sclk_usbphy0, + [4] = &clk_sclk_usbphy1, + [5] = &clk_sclk_hdmiphy, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_group2 = { + .sources = clkset_group2_list, + .nr_sources = ARRAY_SIZE(clkset_group2_list), }; static struct clksrc_clk clksrcs[] = { { .clk = { - .name = "uclk1", + .name = "sclk_dmc", .id = -1, + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_onenand", + .id = -1, + }, + .sources = &clkset_sclk_onenand, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, + }, { + .clk = { + .name = "uclk1", + .id = 0, .ctrlbit = (1<<17), .enable = s5pv210_clk_ip3_ctrl, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, - } + }, { + .clk = { + .name = "uclk1", + .id = 1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 18), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 2, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 19), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 3, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_mixer", + .id = -1, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), + }, + .sources = &clkset_sclk_mixer, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, + }, { + .clk = { + .name = "sclk_spdif", + .id = -1, + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 27), + }, + .sources = &clkset_sclk_spdif, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 0, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 25), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .id = 2, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 26), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam", + .id = 0, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam", + .id = 1, + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .id = -1, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 0, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 1, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 17), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 2, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 18), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_mmc", + .id = 3, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 19), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_mfc", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_g2d", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_g3d", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group1, + .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .id = -1, + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 31), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 0, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_spi", + .id = 1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 13), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_pwi", + .id = -1, + .enable = &s5pv210_clk_ip4_ctrl, + .ctrlbit = (1 << 2), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "sclk_pwm", + .id = -1, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 23), + }, + .sources = &clkset_group2, + .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, + }, }; /* Clock initialisation code */ -static struct clksrc_clk *init_parents[] = { +static struct clksrc_clk *sysclks[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, + &clk_armclk, + &clk_hclk_msys, + &clk_sclk_a2m, + &clk_hclk_dsys, + &clk_hclk_psys, + &clk_pclk_msys, + &clk_pclk_dsys, + &clk_pclk_psys, + &clk_vpllsrc, + &clk_sclk_vpll, + &clk_sclk_dac, + &clk_sclk_pixel, + &clk_sclk_hdmi, }; -#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) - void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; unsigned long xtal; + unsigned long vpllsrc; unsigned long armclk; - unsigned long hclk200; - unsigned long hclk166; - unsigned long hclk133; - unsigned long pclk100; - unsigned long pclk83; - unsigned long pclk66; + unsigned long hclk_msys; + unsigned long hclk_dsys; + unsigned long hclk_psys; + unsigned long pclk_msys; + unsigned long pclk_dsys; + unsigned long pclk_psys; unsigned long apll; unsigned long mpll; unsigned long epll; + unsigned long vpll; unsigned int ptr; u32 clkdiv0, clkdiv1; @@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); - - printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld", - apll, mpll, epll); - - armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL); - if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK) - hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200); - else - hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200); - - if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) { - hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); - hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166); - } else - hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166); - - if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) { - hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); - hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); - } else - hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); - - pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100); - pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83); - pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66); - - printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \ - HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", - armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66); + vpllsrc = clk_get_rate(&clk_vpllsrc.clk); + vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); clk_fout_apll.rate = apll; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; + clk_fout_vpll.rate = vpll; - clk_f.rate = armclk; - clk_h.rate = hclk133; - clk_p.rate = pclk66; - clk_p66.rate = pclk66; - clk_p83.rate = pclk83; - clk_h133.rate = hclk133; - clk_h166.rate = hclk166; - clk_h200.rate = hclk200; + printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", + apll, mpll, epll, vpll); + + armclk = clk_get_rate(&clk_armclk.clk); + hclk_msys = clk_get_rate(&clk_hclk_msys.clk); + hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); + hclk_psys = clk_get_rate(&clk_hclk_psys.clk); + pclk_msys = clk_get_rate(&clk_pclk_msys.clk); + pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); + pclk_psys = clk_get_rate(&clk_pclk_psys.clk); + + printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" + "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", + armclk, hclk_msys, hclk_dsys, hclk_psys, + pclk_msys, pclk_dsys, pclk_psys); - for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c_set_clksrc(init_parents[ptr], true); + clk_f.rate = armclk; + clk_h.rate = hclk_psys; + clk_p.rate = pclk_psys; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); } static struct clk *clks[] __initdata = { - &clk_mout_epll.clk, - &clk_mout_mpll.clk, + &clk_sclk_hdmi27m, + &clk_sclk_hdmiphy, + &clk_sclk_usbphy0, + &clk_sclk_usbphy1, + &clk_pcmcdclk0, + &clk_pcmcdclk1, + &clk_pcmcdclk2, }; void __init s5pv210_register_clocks(void) @@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void) if (ret > 0) printk(KERN_ERR "Failed to register %u clocks\n", ret); + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks)); - if (ret > 0) - printk(KERN_ERR "Failed to register system clocks\n"); - clkp = init_clocks_disable; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ret = s3c24xx_register_clock(clkp); diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 0e0f8fde2aa..2b776eb5d15 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void) s5p_init_irq(vic, ARRAY_SIZE(vic)); } -static struct sysdev_class s5pv210_sysclass = { +struct sysdev_class s5pv210_sysclass = { .name = "s5pv210-core", }; diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c new file mode 100644 index 00000000000..6e215330a1b --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -0,0 +1,327 @@ +/* linux/arch/arm/mach-s5pv210/dev-audio.c + * + * Copyright (c) 2010 Samsung Electronics Co. Ltd + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/gpio-cfg.h> +#include <plat/audio.h> + +#include <mach/gpio.h> +#include <mach/map.h> +#include <mach/dma.h> +#include <mach/irqs.h> + +static int s5pv210_cfg_i2s(struct platform_device *pdev) +{ + /* configure GPIO for i2s port */ + switch (pdev->id) { + case 1: + s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2)); + break; + + case 2: + s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4)); + break; + + case -1: + s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2)); + break; + + default: + printk(KERN_ERR "Invalid Device %d\n", pdev->id); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_i2s_pdata = { + .cfg_gpio = s5pv210_cfg_i2s, +}; + +static struct resource s5pv210_iis0_resource[] = { + [0] = { + .start = S5PV210_PA_IIS0, + .end = S5PV210_PA_IIS0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S0_TX, + .end = DMACH_I2S0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_RX, + .end = DMACH_I2S0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_iis0 = { + .name = "s3c64xx-iis-v4", + .id = -1, + .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), + .resource = s5pv210_iis0_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5pv210_iis1_resource[] = { + [0] = { + .start = S5PV210_PA_IIS1, + .end = S5PV210_PA_IIS1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S1_TX, + .end = DMACH_I2S1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_RX, + .end = DMACH_I2S1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_iis1 = { + .name = "s3c64xx-iis", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_iis1_resource), + .resource = s5pv210_iis1_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +static struct resource s5pv210_iis2_resource[] = { + [0] = { + .start = S5PV210_PA_IIS2, + .end = S5PV210_PA_IIS2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_I2S2_TX, + .end = DMACH_I2S2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S2_RX, + .end = DMACH_I2S2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_iis2 = { + .name = "s3c64xx-iis", + .id = 2, + .num_resources = ARRAY_SIZE(s5pv210_iis2_resource), + .resource = s5pv210_iis2_resource, + .dev = { + .platform_data = &s3c_i2s_pdata, + }, +}; + +/* PCM Controller platform_devices */ + +static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3)); + break; + case 1: + s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3)); + break; + case 2: + s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2)); + break; + default: + printk(KERN_DEBUG "Invalid PCM Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct s3c_audio_pdata s3c_pcm_pdata = { + .cfg_gpio = s5pv210_pcm_cfg_gpio, +}; + +static struct resource s5pv210_pcm0_resource[] = { + [0] = { + .start = S5PV210_PA_PCM0, + .end = S5PV210_PA_PCM0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM0_TX, + .end = DMACH_PCM0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM0_RX, + .end = DMACH_PCM0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_pcm0 = { + .name = "samsung-pcm", + .id = 0, + .num_resources = ARRAY_SIZE(s5pv210_pcm0_resource), + .resource = s5pv210_pcm0_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource s5pv210_pcm1_resource[] = { + [0] = { + .start = S5PV210_PA_PCM1, + .end = S5PV210_PA_PCM1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM1_TX, + .end = DMACH_PCM1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM1_RX, + .end = DMACH_PCM1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_pcm1 = { + .name = "samsung-pcm", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_pcm1_resource), + .resource = s5pv210_pcm1_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +static struct resource s5pv210_pcm2_resource[] = { + [0] = { + .start = S5PV210_PA_PCM2, + .end = S5PV210_PA_PCM2 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_PCM2_TX, + .end = DMACH_PCM2_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_PCM2_RX, + .end = DMACH_PCM2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device s5pv210_device_pcm2 = { + .name = "samsung-pcm", + .id = 2, + .num_resources = ARRAY_SIZE(s5pv210_pcm2_resource), + .resource = s5pv210_pcm2_resource, + .dev = { + .platform_data = &s3c_pcm_pdata, + }, +}; + +/* AC97 Controller platform devices */ + +static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4)); + + return 0; +} + +static struct resource s5pv210_ac97_resource[] = { + [0] = { + .start = S5PV210_PA_AC97, + .end = S5PV210_PA_AC97 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_AC97_PCMOUT, + .end = DMACH_AC97_PCMOUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_AC97_PCMIN, + .end = DMACH_AC97_PCMIN, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DMACH_AC97_MICIN, + .end = DMACH_AC97_MICIN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .start = IRQ_AC97, + .end = IRQ_AC97, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_audio_pdata s3c_ac97_pdata = { + .cfg_gpio = s5pv210_ac97_cfg_gpio, +}; + +static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pv210_device_ac97 = { + .name = "s3c-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(s5pv210_ac97_resource), + .resource = s5pv210_ac97_resource, + .dev = { + .platform_data = &s3c_ac97_pdata, + .dma_mask = &s5pv210_ac97_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c new file mode 100644 index 00000000000..778ad5fe231 --- /dev/null +++ b/arch/arm/mach-s5pv210/dma.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <plat/devs.h> +#include <plat/irqs.h> + +#include <mach/map.h> +#include <mach/irqs.h> + +#include <plat/s3c-pl330-pdata.h> + +static u64 dma_dmamask = DMA_BIT_MASK(32); + +static struct resource s5pv210_pdma0_resource[] = { + [0] = { + .start = S5PV210_PA_PDMA0, + .end = S5PV210_PA_PDMA0 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA0, + .end = IRQ_PDMA0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_MAX, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_MAX, + [15] = DMACH_MAX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_SPI1_RX, + [19] = DMACH_SPI1_TX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_AC97_MICIN, + [23] = DMACH_AC97_PCMIN, + [24] = DMACH_AC97_PCMOUT, + [25] = DMACH_MAX, + [26] = DMACH_PWM, + [27] = DMACH_SPDIF, + [28] = DMACH_MAX, + [29] = DMACH_MAX, + [30] = DMACH_MAX, + [31] = DMACH_MAX, + }, +}; + +static struct platform_device s5pv210_device_pdma0 = { + .name = "s3c-pl330", + .id = 1, + .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource), + .resource = s5pv210_pdma0_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_pdma0_pdata, + }, +}; + +static struct resource s5pv210_pdma1_resource[] = { + [0] = { + .start = S5PV210_PA_PDMA1, + .end = S5PV210_PA_PDMA1 + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PDMA1, + .end = IRQ_PDMA1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { + .peri = { + [0] = DMACH_UART0_RX, + [1] = DMACH_UART0_TX, + [2] = DMACH_UART1_RX, + [3] = DMACH_UART1_TX, + [4] = DMACH_UART2_RX, + [5] = DMACH_UART2_TX, + [6] = DMACH_UART3_RX, + [7] = DMACH_UART3_TX, + [8] = DMACH_MAX, + [9] = DMACH_I2S0_RX, + [10] = DMACH_I2S0_TX, + [11] = DMACH_I2S0S_TX, + [12] = DMACH_I2S1_RX, + [13] = DMACH_I2S1_TX, + [14] = DMACH_I2S2_RX, + [15] = DMACH_I2S2_TX, + [16] = DMACH_SPI0_RX, + [17] = DMACH_SPI0_TX, + [18] = DMACH_SPI1_RX, + [19] = DMACH_SPI1_TX, + [20] = DMACH_MAX, + [21] = DMACH_MAX, + [22] = DMACH_PCM0_RX, + [23] = DMACH_PCM0_TX, + [24] = DMACH_PCM1_RX, + [25] = DMACH_PCM1_TX, + [26] = DMACH_MSM_REQ0, + [27] = DMACH_MSM_REQ1, + [28] = DMACH_MSM_REQ2, + [29] = DMACH_MSM_REQ3, + [30] = DMACH_PCM2_RX, + [31] = DMACH_PCM2_TX, + }, +}; + +static struct platform_device s5pv210_device_pdma1 = { + .name = "s3c-pl330", + .id = 2, + .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), + .resource = s5pv210_pdma1_resource, + .dev = { + .dma_mask = &dma_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s5pv210_pdma1_pdata, + }, +}; + +static struct platform_device *s5pv210_dmacs[] __initdata = { + &s5pv210_device_pdma0, + &s5pv210_device_pdma1, +}; + +static int __init s5pv210_dma_init(void) +{ + platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs)); + + return 0; +} +arch_initcall(s5pv210_dma_init); diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c new file mode 100644 index 00000000000..9ea8972e023 --- /dev/null +++ b/arch/arm/mach-s5pv210/gpiolib.c @@ -0,0 +1,261 @@ +/* linux/arch/arm/mach-s5pv210/gpiolib.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> +#include <mach/map.h> + +static struct s3c_gpio_cfg gpio_cfg = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +/* GPIO bank's base address given the index of the bank in the + * list of all gpio banks. + */ +#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) + +/* + * Following are the gpio banks in v210. + * + * The 'config' member when left to NULL, is initialized to the default + * structure gpio_cfg in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of s3c_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ +static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { + { + .chip = { + .base = S5PV210_GPA0(0), + .ngpio = S5PV210_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .chip = { + .base = S5PV210_GPA1(0), + .ngpio = S5PV210_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .chip = { + .base = S5PV210_GPB(0), + .ngpio = S5PV210_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5PV210_GPC0(0), + .ngpio = S5PV210_GPIO_C0_NR, + .label = "GPC0", + }, + }, { + .chip = { + .base = S5PV210_GPC1(0), + .ngpio = S5PV210_GPIO_C1_NR, + .label = "GPC1", + }, + }, { + .chip = { + .base = S5PV210_GPD0(0), + .ngpio = S5PV210_GPIO_D0_NR, + .label = "GPD0", + }, + }, { + .chip = { + .base = S5PV210_GPD1(0), + .ngpio = S5PV210_GPIO_D1_NR, + .label = "GPD1", + }, + }, { + .chip = { + .base = S5PV210_GPE0(0), + .ngpio = S5PV210_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .chip = { + .base = S5PV210_GPE1(0), + .ngpio = S5PV210_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .chip = { + .base = S5PV210_GPF0(0), + .ngpio = S5PV210_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .chip = { + .base = S5PV210_GPF1(0), + .ngpio = S5PV210_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .chip = { + .base = S5PV210_GPF2(0), + .ngpio = S5PV210_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .chip = { + .base = S5PV210_GPF3(0), + .ngpio = S5PV210_GPIO_F3_NR, + .label = "GPF3", + }, + }, { + .chip = { + .base = S5PV210_GPG0(0), + .ngpio = S5PV210_GPIO_G0_NR, + .label = "GPG0", + }, + }, { + .chip = { + .base = S5PV210_GPG1(0), + .ngpio = S5PV210_GPIO_G1_NR, + .label = "GPG1", + }, + }, { + .chip = { + .base = S5PV210_GPG2(0), + .ngpio = S5PV210_GPIO_G2_NR, + .label = "GPG2", + }, + }, { + .chip = { + .base = S5PV210_GPG3(0), + .ngpio = S5PV210_GPIO_G3_NR, + .label = "GPG3", + }, + }, { + .chip = { + .base = S5PV210_GPI(0), + .ngpio = S5PV210_GPIO_I_NR, + .label = "GPI", + }, + }, { + .chip = { + .base = S5PV210_GPJ0(0), + .ngpio = S5PV210_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .chip = { + .base = S5PV210_GPJ1(0), + .ngpio = S5PV210_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .chip = { + .base = S5PV210_GPJ2(0), + .ngpio = S5PV210_GPIO_J2_NR, + .label = "GPJ2", + }, + }, { + .chip = { + .base = S5PV210_GPJ3(0), + .ngpio = S5PV210_GPIO_J3_NR, + .label = "GPJ3", + }, + }, { + .chip = { + .base = S5PV210_GPJ4(0), + .ngpio = S5PV210_GPIO_J4_NR, + .label = "GPJ4", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP01(0), + .ngpio = S5PV210_GPIO_MP01_NR, + .label = "MP01", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP02(0), + .ngpio = S5PV210_GPIO_MP02_NR, + .label = "MP02", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP03(0), + .ngpio = S5PV210_GPIO_MP03_NR, + .label = "MP03", + }, + }, { + .base = (S5P_VA_GPIO + 0xC00), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH0(0), + .ngpio = S5PV210_GPIO_H0_NR, + .label = "GPH0", + }, + }, { + .base = (S5P_VA_GPIO + 0xC20), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH1(0), + .ngpio = S5PV210_GPIO_H1_NR, + .label = "GPH1", + }, + }, { + .base = (S5P_VA_GPIO + 0xC40), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH2(0), + .ngpio = S5PV210_GPIO_H2_NR, + .label = "GPH2", + }, + }, { + .base = (S5P_VA_GPIO + 0xC60), + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_GPH3(0), + .ngpio = S5PV210_GPIO_H3_NR, + .label = "GPH3", + }, + }, +}; + +static __init int s5pv210_gpiolib_init(void) +{ + struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; + int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); + int i = 0; + + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) + chip->config = &gpio_cfg; + if (chip->base == NULL) + chip->base = S5PV210_BANK_BASE(i); + } + + samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); + + return 0; +} +core_initcall(s5pv210_gpiolib_init); diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h new file mode 100644 index 00000000000..81209eb1409 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/dma.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co. Ltd. + * Jaswinder Singh <jassi.brar@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* This platform uses the common S3C DMA API driver for PL330 */ +#include <plat/s3c-dma-pl330.h> + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index 533b020e21e..d6461ba2b71 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -18,6 +18,8 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq +/* Practically, GPIO banks upto MP03 are the configurable gpio banks */ + /* GPIO bank sizes */ #define S5PV210_GPIO_A0_NR (8) #define S5PV210_GPIO_A1_NR (4) @@ -47,6 +49,10 @@ #define S5PV210_GPIO_J3_NR (8) #define S5PV210_GPIO_J4_NR (5) +#define S5PV210_GPIO_MP01_NR (8) +#define S5PV210_GPIO_MP02_NR (4) +#define S5PV210_GPIO_MP03_NR (8) + /* GPIO bank numbers */ /* CONFIG_S3C_GPIO_SPACE allows the user to select extra @@ -85,6 +91,9 @@ enum s5p_gpio_number { S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1), S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2), S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3), + S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4), + S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01), + S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), }; /* S5PV210 GPIO number definitions */ @@ -115,13 +124,16 @@ enum s5p_gpio_number { #define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr)) #define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr)) #define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr)) +#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr)) +#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr)) +#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the GPJ4() range */ -#define ARCH_NR_GPIOS (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + \ +/* define the number of gpios we need to the one after the MP03() range */ +#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index c22694c8231..5adcb9f26e4 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -43,6 +43,10 @@ #define S5PV210_PA_SROMC (0xE8000000) +#define S5PV210_PA_MDMA 0xFA200000 +#define S5PV210_PA_PDMA0 0xE0900000 +#define S5PV210_PA_PDMA1 0xE0A00000 + #define S5PV210_PA_VIC0 (0xF2000000) #define S5P_PA_VIC0 S5PV210_PA_VIC0 @@ -58,6 +62,19 @@ #define S5PV210_PA_SDRAM (0x20000000) #define S5P_PA_SDRAM S5PV210_PA_SDRAM +/* I2S */ +#define S5PV210_PA_IIS0 0xEEE30000 +#define S5PV210_PA_IIS1 0xE2100000 +#define S5PV210_PA_IIS2 0xE2A00000 + +/* PCM */ +#define S5PV210_PA_PCM0 0xE2300000 +#define S5PV210_PA_PCM1 0xE1200000 +#define S5PV210_PA_PCM2 0xE2B00000 + +/* AC97 */ +#define S5PV210_PA_AC97 0xE2200000 + /* compatibiltiy defines. */ #define S3C_PA_UART S5PV210_PA_UART #define S3C_PA_IIC S5PV210_PA_IIC0 diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h index 69027fea987..f8a9f1b330e 100644 --- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h @@ -1,13 +1,14 @@ /* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h + * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h * * S5PV210 - pwm clock and timer support * @@ -21,14 +22,14 @@ /** * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @cfg: The timer TCFG1 register bits shifted down to 0. + * @tcfg: The timer TCFG1 register bits shifted down to 0. * * Return true if the given configuration from TCFG1 is a TCLK instead * any of the TDIV clocks. */ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) { - return tcfg == S3C2410_TCFG1_MUX_TCLK; + return tcfg == S3C64XX_TCFG1_MUX_TCLK; } /** @@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) */ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) { - return 1 << (1 + tcfg1); + return 1 << tcfg1; } /** @@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) */ static inline unsigned int pwm_tdiv_has_div1(void) { - return 0; + return 1; } /** @@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) */ static inline unsigned long pwm_tdiv_div_bits(unsigned int div) { - return ilog2(div) - 1; + return ilog2(div); } -#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK #endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index ab4869df30c..6f9fd3274e2 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { }; static struct platform_device *smdkc110_devices[] __initdata = { + &s5pv210_device_iis0, + &s5pv210_device_ac97, }; static void __init smdkc110_map_io(void) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index a2788325320..3c29e18528a 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { }; static struct platform_device *smdkv210_devices[] __initdata = { + &s5pv210_device_iis0, + &s5pv210_device_ac97, }; static void __init smdkv210_map_io(void) diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c new file mode 100644 index 00000000000..9ec6845840e --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/mach-s5pv210/setup-i2c0.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <plat/iic.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + /* Will be populated later */ +} |