diff options
Diffstat (limited to 'arch/arm/mach-tegra/Kconfig')
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 11680c532b3..9ff6f6ea361 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -4,42 +4,42 @@ comment "NVIDIA Tegra options" config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - select CPU_V7 - select ARM_GIC select ARCH_REQUIRE_GPIOLIB - select PINCTRL - select PINCTRL_TEGRA20 - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_ULPI if USB - select USB_ULPI_VIEWPORT if USB_SUPPORT select ARM_ERRATA_720789 select ARM_ERRATA_742230 select ARM_ERRATA_751472 select ARM_ERRATA_754327 select ARM_ERRATA_764369 if SMP + select ARM_GIC + select CPU_FREQ_TABLE if CPU_FREQ + select CPU_V7 + select PINCTRL + select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 - select CPU_FREQ_TABLE if CPU_FREQ + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB + select USB_ULPI_VIEWPORT if USB_SUPPORT help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" - select CPU_V7 - select ARM_GIC select ARCH_REQUIRE_GPIOLIB - select PINCTRL - select PINCTRL_TEGRA30 - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_ULPI if USB - select USB_ULPI_VIEWPORT if USB_SUPPORT select ARM_ERRATA_743622 select ARM_ERRATA_751472 select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP - select PL310_ERRATA_769419 if CACHE_L2X0 + select ARM_GIC select CPU_FREQ_TABLE if CPU_FREQ + select CPU_V7 + select PINCTRL + select PINCTRL_TEGRA30 + select PL310_ERRATA_769419 if CACHE_L2X0 + select USB_ARCH_HAS_EHCI if USB_SUPPORT + select USB_ULPI if USB + select USB_ULPI_VIEWPORT if USB_SUPPORT help Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |