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-rw-r--r--arch/arm/mach-tegra/common.c69
1 files changed, 19 insertions, 50 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 8f0ffe97ffe..5449a3f2977 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,6 +1,7 @@
/*
* arch/arm/mach-tegra/common.c
*
+ * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
* Copyright (C) 2010 Google, Inc.
*
* Author:
@@ -22,13 +23,13 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irqchip.h>
+#include <linux/clk/tegra.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/powergate.h>
#include "board.h"
-#include "clock.h"
#include "common.h"
#include "fuse.h"
#include "iomap.h"
@@ -59,6 +60,7 @@ u32 tegra_uart_config[4] = {
#ifdef CONFIG_OF
void __init tegra_dt_init_irq(void)
{
+ tegra_clocks_init();
tegra_init_irq();
irqchip_init();
}
@@ -74,43 +76,6 @@ void tegra_assert_system_reset(char mode, const char *cmd)
writel_relaxed(reg, reset);
}
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
- /* name parent rate enabled */
- { "clk_m", NULL, 0, true },
- { "pll_p", "clk_m", 216000000, true },
- { "pll_p_out1", "pll_p", 28800000, true },
- { "pll_p_out2", "pll_p", 48000000, true },
- { "pll_p_out3", "pll_p", 72000000, true },
- { "pll_p_out4", "pll_p", 24000000, true },
- { "pll_c", "clk_m", 600000000, true },
- { "pll_c_out1", "pll_c", 120000000, true },
- { "sclk", "pll_c_out1", 120000000, true },
- { "hclk", "sclk", 120000000, true },
- { "pclk", "hclk", 60000000, true },
- { "csite", NULL, 0, true },
- { "emc", NULL, 0, true },
- { "cpu", NULL, 0, true },
- { NULL, NULL, 0, 0},
-};
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
- /* name parent rate enabled */
- { "clk_m", NULL, 0, true },
- { "pll_p", "pll_ref", 408000000, true },
- { "pll_p_out1", "pll_p", 9600000, true },
- { "pll_p_out4", "pll_p", 102000000, true },
- { "sclk", "pll_p_out4", 102000000, true },
- { "hclk", "sclk", 102000000, true },
- { "pclk", "hclk", 51000000, true },
- { "csite", NULL, 0, true },
- { NULL, NULL, 0, 0},
-};
-#endif
-
-
static void __init tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
@@ -129,35 +94,39 @@ static void __init tegra_init_cache(void)
}
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void __init tegra20_init_early(void)
+static void __init tegra_init_early(void)
{
tegra_cpu_reset_handler_init();
tegra_apb_io_init();
tegra_init_fuse();
- tegra2_init_clocks();
- tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache();
tegra_pmc_init();
tegra_powergate_init();
+}
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra20_init_early(void)
+{
+ tegra_init_early();
tegra20_hotplug_init();
}
#endif
+
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void)
{
- tegra_cpu_reset_handler_init();
- tegra_apb_io_init();
- tegra_init_fuse();
- tegra30_init_clocks();
- tegra_clk_init_from_table(tegra30_clk_init_table);
- tegra_init_cache();
- tegra_pmc_init();
- tegra_powergate_init();
+ tegra_init_early();
tegra30_hotplug_init();
}
#endif
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void __init tegra114_init_early(void)
+{
+ tegra_init_early();
+}
+#endif
+
void __init tegra_init_late(void)
{
tegra_powergate_debugfs_init();