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-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--arch/arm/mm/alignment.c70
-rw-r--r--arch/arm/mm/fault.c6
-rw-r--r--arch/arm/mm/mm-armv.c48
-rw-r--r--arch/arm/mm/proc-arm6_7.S8
-rw-r--r--arch/arm/mm/proc-v6.S24
-rw-r--r--arch/arm/mm/proc-xscale.S136
7 files changed, 101 insertions, 193 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index afbbeb6f465..db5e47dfc30 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -384,7 +384,7 @@ config CPU_DCACHE_DISABLE
config CPU_DCACHE_WRITETHROUGH
bool "Force write through D-cache"
- depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
+ depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE
default y if CPU_ARM925T
help
Say Y here to use the data cache in writethrough mode. Unless you
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 81f4a8a2d34..4b39d867ac1 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -45,7 +45,7 @@
#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
-#define LDSTH_I_BIT(i) (i & (1 << 22)) /* half-word immed */
+#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
@@ -68,6 +68,7 @@ static unsigned long ai_sys;
static unsigned long ai_skipped;
static unsigned long ai_half;
static unsigned long ai_word;
+static unsigned long ai_dword;
static unsigned long ai_multi;
static int ai_usermode;
@@ -93,6 +94,8 @@ proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
p += sprintf(p, "Half:\t\t%lu\n", ai_half);
p += sprintf(p, "Word:\t\t%lu\n", ai_word);
+ if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
+ p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
usermode_action[ai_usermode]);
@@ -283,12 +286,6 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
{
unsigned int rd = RD_BITS(instr);
- if ((instr & 0x01f00ff0) == 0x01000090)
- goto swp;
-
- if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0)
- goto bad;
-
ai_half += 1;
if (user_mode(regs))
@@ -323,10 +320,47 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
return TYPE_LDST;
- swp:
- printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
- bad:
- return TYPE_ERROR;
+ fault:
+ return TYPE_FAULT;
+}
+
+static int
+do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
+ struct pt_regs *regs)
+{
+ unsigned int rd = RD_BITS(instr);
+
+ ai_dword += 1;
+
+ if (user_mode(regs))
+ goto user;
+
+ if ((instr & 0xf0) == 0xd0) {
+ unsigned long val;
+ get32_unaligned_check(val, addr);
+ regs->uregs[rd] = val;
+ get32_unaligned_check(val, addr+4);
+ regs->uregs[rd+1] = val;
+ } else {
+ put32_unaligned_check(regs->uregs[rd], addr);
+ put32_unaligned_check(regs->uregs[rd+1], addr+4);
+ }
+
+ return TYPE_LDST;
+
+ user:
+ if ((instr & 0xf0) == 0xd0) {
+ unsigned long val;
+ get32t_unaligned_check(val, addr);
+ regs->uregs[rd] = val;
+ get32t_unaligned_check(val, addr+4);
+ regs->uregs[rd+1] = val;
+ } else {
+ put32t_unaligned_check(regs->uregs[rd], addr);
+ put32t_unaligned_check(regs->uregs[rd+1], addr+4);
+ }
+
+ return TYPE_LDST;
fault:
return TYPE_FAULT;
@@ -617,12 +651,20 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
switch (CODING_BITS(instr)) {
- case 0x00000000: /* ldrh or strh */
- if (LDSTH_I_BIT(instr))
+ case 0x00000000: /* 3.13.4 load/store instruction extensions */
+ if (LDSTHD_I_BIT(instr))
offset.un = (instr & 0xf00) >> 4 | (instr & 15);
else
offset.un = regs->uregs[RM_BITS(instr)];
- handler = do_alignment_ldrhstrh;
+
+ if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
+ (instr & 0x001000f0) == 0x001000f0) /* LDRSH */
+ handler = do_alignment_ldrhstrh;
+ else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
+ (instr & 0x001000f0) == 0x000000f0) /* STRD */
+ handler = do_alignment_ldrdstrd;
+ else
+ goto bad;
break;
case 0x04000000: /* ldr or str immediate */
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 65bfe84b6d6..0b6c4db44e0 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -238,9 +238,9 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
up_read(&mm->mmap_sem);
/*
- * Handle the "normal" case first
+ * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
*/
- if (fault > 0)
+ if (fault >= VM_FAULT_MINOR)
return 0;
/*
@@ -261,7 +261,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
do_exit(SIGKILL);
return 0;
- case 0:
+ case VM_FAULT_SIGBUS:
/*
* We had some memory, but were unable to
* successfully fix up this page fault.
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index b19f00e99a2..d125a3dc061 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -275,11 +275,9 @@ alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
int i;
for (i = 0; i < 16; i += 1) {
- alloc_init_section(virt, phys & SUPERSECTION_MASK,
- prot | PMD_SECT_SUPER);
+ alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
virt += (PGDIR_SIZE / 2);
- phys += (PGDIR_SIZE / 2);
}
}
@@ -297,14 +295,10 @@ alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pg
pte_t *ptep;
if (pmd_none(*pmdp)) {
- unsigned long pmdval;
ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
sizeof(pte_t));
- pmdval = __pa(ptep) | prot_l1;
- pmdp[0] = __pmd(pmdval);
- pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
- flush_pmd_entry(pmdp);
+ __pmd_populate(pmdp, __pa(ptep) | prot_l1);
}
ptep = pte_offset_kernel(pmdp, virt);
@@ -383,6 +377,7 @@ static void __init build_mem_type_table(void)
{
struct cachepolicy *cp;
unsigned int cr = get_cr();
+ unsigned int user_pgprot;
int cpu_arch = cpu_architecture();
int i;
@@ -408,6 +403,9 @@ static void __init build_mem_type_table(void)
}
}
+ cp = &cache_policies[cachepolicy];
+ user_pgprot = cp->pte;
+
/*
* ARMv6 and above have extended page tables.
*/
@@ -425,9 +423,19 @@ static void __init build_mem_type_table(void)
mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
- }
- cp = &cache_policies[cachepolicy];
+ /*
+ * Mark the device area as "shared device"
+ */
+ mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
+ mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
+
+ /*
+ * User pages need to be mapped with the ASID
+ * (iow, non-global)
+ */
+ user_pgprot |= L_PTE_ASID;
+ }
if (cpu_arch >= CPU_ARCH_ARMv5) {
mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
@@ -445,7 +453,7 @@ static void __init build_mem_type_table(void)
for (i = 0; i < 16; i++) {
unsigned long v = pgprot_val(protection_map[i]);
- v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte;
+ v = (v & ~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot;
protection_map[i] = __pgprot(v);
}
@@ -569,23 +577,23 @@ static void __init create_mapping(struct map_desc *md)
*/
void setup_mm_for_reboot(char mode)
{
- unsigned long pmdval;
+ unsigned long base_pmdval;
pgd_t *pgd;
- pmd_t *pmd;
int i;
- int cpu_arch = cpu_architecture();
if (current->mm && current->mm->pgd)
pgd = current->mm->pgd;
else
pgd = init_mm.pgd;
- for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++) {
- pmdval = (i << PGDIR_SHIFT) |
- PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
- PMD_TYPE_SECT;
- if (cpu_arch <= CPU_ARCH_ARMv5TEJ)
- pmdval |= PMD_BIT4;
+ base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
+ if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ)
+ base_pmdval |= PMD_BIT4;
+
+ for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
+ unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
+ pmd_t *pmd;
+
pmd = pmd_off(pgd, i << PGDIR_SHIFT);
pmd[0] = __pmd(pmdval);
pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 0ee214b824f..189ef6a71ba 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -38,8 +38,8 @@ ENTRY(cpu_arm7_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r8, [r0] @ read arm instruction
- tst r8, #1 << 20 @ L = 1 -> write?
- orreq r1, r1, #1 << 8 @ yes.
+ tst r8, #1 << 20 @ L = 0 -> write?
+ orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24
add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
nop
@@ -71,8 +71,8 @@ ENTRY(cpu_arm6_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r8, [r2] @ read arm instruction
- tst r8, #1 << 20 @ L = 1 -> write?
- orreq r1, r1, #1 << 8 @ yes.
+ tst r8, #1 << 20 @ L = 0 -> write?
+ orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #14 << 24
teq r7, #8 << 24 @ was it ldm/stm
movne pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 352db98ee26..139a38670c5 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -105,18 +105,12 @@ ENTRY(cpu_v6_dcache_clean_area)
ENTRY(cpu_v6_switch_mm)
mov r2, #0
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
- mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
+ mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
mcr p15, 0, r1, c13, c0, 1 @ set context ID
mov pc, lr
-#define nG (1 << 11)
-#define APX (1 << 9)
-#define AP1 (1 << 5)
-#define AP0 (1 << 4)
-#define XN (1 << 0)
-
/*
* cpu_v6_set_pte(ptep, pte)
*
@@ -139,24 +133,24 @@ ENTRY(cpu_v6_switch_mm)
ENTRY(cpu_v6_set_pte)
str r1, [r0], #-2048 @ linux version
- bic r2, r1, #0x00000ff0
+ bic r2, r1, #0x000007f0
bic r2, r2, #0x00000003
- orr r2, r2, #AP0 | 2
+ orr r2, r2, #PTE_EXT_AP0 | 2
tst r1, #L_PTE_WRITE
tstne r1, #L_PTE_DIRTY
- orreq r2, r2, #APX
+ orreq r2, r2, #PTE_EXT_APX
tst r1, #L_PTE_USER
- orrne r2, r2, #AP1 | nG
- tstne r2, #APX
- bicne r2, r2, #APX | AP0
+ orrne r2, r2, #PTE_EXT_AP1
+ tstne r2, #PTE_EXT_APX
+ bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
tst r1, #L_PTE_YOUNG
- biceq r2, r2, #APX | AP1 | AP0
+ biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
@ tst r1, #L_PTE_EXEC
-@ orreq r2, r2, #XN
+@ orreq r2, r2, #PTE_EXT_XN
tst r1, #L_PTE_PRESENT
moveq r2, #0
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2d977b4eeea..b88de270014 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -370,142 +370,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
bhi 1b
mov pc, lr
-/* ================================ CACHE LOCKING============================
- *
- * The XScale MicroArchitecture implements support for locking entries into
- * the data and instruction cache. The following functions implement the core
- * low level instructions needed to accomplish the locking. The developer's
- * manual states that the code that performs the locking must be in non-cached
- * memory. To accomplish this, the code in xscale-cache-lock.c copies the
- * following functions from the cache into a non-cached memory region that
- * is allocated through consistent_alloc().
- *
- */
- .align 5
-/*
- * xscale_icache_lock
- *
- * r0: starting address to lock
- * r1: end address to lock
- */
-ENTRY(xscale_icache_lock)
-
-iLockLoop:
- bic r0, r0, #CACHELINESIZE - 1
- mcr p15, 0, r0, c9, c1, 0 @ lock into cache
- cmp r0, r1 @ are we done?
- add r0, r0, #CACHELINESIZE @ advance to next cache line
- bls iLockLoop
- mov pc, lr
-
-/*
- * xscale_icache_unlock
- */
-ENTRY(xscale_icache_unlock)
- mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
- mov pc, lr
-
-/*
- * xscale_dcache_lock
- *
- * r0: starting address to lock
- * r1: end address to lock
- */
-ENTRY(xscale_dcache_lock)
- mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
- mov r2, #1
- mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
- cpwait ip @ Wait for completion
-
- mrs r2, cpsr
- orr r3, r2, #PSR_F_BIT | PSR_I_BIT
-dLockLoop:
- msr cpsr_c, r3
- mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
- mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
- msr cpsr_c, r2
- ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
- @ location [r0]. Post-increment
- @ r3 to next cache line
- cmp r0, r1 @ Are we done?
- bls dLockLoop
-
- mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
- mov r2, #0
- mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
- cpwait_ret lr, ip
-
-/*
- * xscale_dcache_unlock
- */
-ENTRY(xscale_dcache_unlock)
- mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
- mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
- mov pc, lr
-
-/*
- * Needed to determine the length of the code that needs to be copied.
- */
- .align 5
-ENTRY(xscale_cache_dummy)
- mov pc, lr
-
-/* ================================ TLB LOCKING==============================
- *
- * The XScale MicroArchitecture implements support for locking entries into
- * the Instruction and Data TLBs. The following functions provide the
- * low level support for supporting these under Linux. xscale-lock.c
- * implements some higher level management code. Most of the following
- * is taken straight out of the Developer's Manual.
- */
-
-/*
- * Lock I-TLB entry
- *
- * r0: Virtual address to translate and lock
- */
- .align 5
-ENTRY(xscale_itlb_lock)
- mrs r2, cpsr
- orr r3, r2, #PSR_F_BIT | PSR_I_BIT
- msr cpsr_c, r3 @ Disable interrupts
- mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
- mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
- msr cpsr_c, r2 @ Restore interrupts
- cpwait_ret lr, ip
-
-/*
- * Lock D-TLB entry
- *
- * r0: Virtual address to translate and lock
- */
- .align 5
-ENTRY(xscale_dtlb_lock)
- mrs r2, cpsr
- orr r3, r2, #PSR_F_BIT | PSR_I_BIT
- msr cpsr_c, r3 @ Disable interrupts
- mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
- mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
- msr cpsr_c, r2 @ Restore interrupts
- cpwait_ret lr, ip
-
-/*
- * Unlock all I-TLB entries
- */
- .align 5
-ENTRY(xscale_itlb_unlock)
- mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
- mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
- cpwait_ret lr, ip
-
-/*
- * Unlock all D-TLB entries
- */
-ENTRY(xscale_dtlb_unlock)
- mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
- mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
- cpwait_ret lr, ip
-
/* =============================== PageTable ============================== */
#define PTE_CACHE_WRITE_ALLOCATE 0
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-02-27 09:29:13 +0000