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-rw-r--r--arch/arm/mm/Kconfig77
-rw-r--r--arch/arm/mm/Makefile10
-rw-r--r--arch/arm/mm/copypage-v3.S2
-rw-r--r--arch/arm/mm/init.c2
-rw-r--r--arch/arm/mm/iomap.c55
-rw-r--r--arch/arm/mm/ioremap.c47
-rw-r--r--arch/arm/mm/nommu.c39
-rw-r--r--arch/arm/mm/proc-arm1020.S9
-rw-r--r--arch/arm/mm/proc-arm1020e.S9
-rw-r--r--arch/arm/mm/proc-arm1022.S9
-rw-r--r--arch/arm/mm/proc-arm1026.S9
-rw-r--r--arch/arm/mm/proc-arm6_7.S15
-rw-r--r--arch/arm/mm/proc-arm720.S12
-rw-r--r--arch/arm/mm/proc-arm920.S9
-rw-r--r--arch/arm/mm/proc-arm922.S9
-rw-r--r--arch/arm/mm/proc-arm925.S10
-rw-r--r--arch/arm/mm/proc-arm926.S9
-rw-r--r--arch/arm/mm/proc-sa110.S11
-rw-r--r--arch/arm/mm/proc-sa1100.S11
-rw-r--r--arch/arm/mm/proc-v6.S39
20 files changed, 272 insertions, 121 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c55b739e10b..c4bca753165 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -15,8 +15,8 @@ config CPU_ARM610
select CPU_32v3
select CPU_CACHE_V3
select CPU_CACHE_VIVT
- select CPU_COPY_V3
- select CPU_TLB_V3
+ select CPU_COPY_V3 if MMU
+ select CPU_TLB_V3 if MMU
help
The ARM610 is the successor to the ARM3 processor
and was produced by VLSI Technology Inc.
@@ -31,8 +31,8 @@ config CPU_ARM710
select CPU_32v3
select CPU_CACHE_V3
select CPU_CACHE_VIVT
- select CPU_COPY_V3
- select CPU_TLB_V3
+ select CPU_COPY_V3 if MMU
+ select CPU_TLB_V3 if MMU
help
A 32-bit RISC microprocessor based on the ARM7 processor core
designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -50,8 +50,8 @@ config CPU_ARM720T
select CPU_ABRT_LV4T
select CPU_CACHE_V4
select CPU_CACHE_VIVT
- select CPU_COPY_V4WT
- select CPU_TLB_V4WT
+ select CPU_COPY_V4WT if MMU
+ select CPU_TLB_V4WT if MMU
help
A 32-bit RISC processor with 8kByte Cache, Write Buffer and
MMU built around an ARM7TDMI core.
@@ -61,15 +61,15 @@ config CPU_ARM720T
# ARM920T
config CPU_ARM920T
- bool "Support ARM920T processor" if !ARCH_S3C2410
- depends on ARCH_EP93XX || ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
- default y if ARCH_S3C2410 || ARCH_AT91RM9200
+ bool "Support ARM920T processor"
+ depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
+ default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
select CPU_32v4
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM920T is licensed to be produced by numerous vendors,
and is used in the Maverick EP9312 and the Samsung S3C2410.
@@ -89,8 +89,8 @@ config CPU_ARM922T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM922T is a version of the ARM920T, but with smaller
instruction and data caches. It is used in Altera's
@@ -108,8 +108,8 @@ config CPU_ARM925T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM925T is a mix between the ARM920T and ARM926T, but with
different instruction and data caches. It is used in TI's OMAP
@@ -121,13 +121,13 @@ config CPU_ARM925T
# ARM926T
config CPU_ARM926T
bool "Support ARM926T processor"
- depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB
- default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
+ depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412
+ default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412
select CPU_32v5
select CPU_ABRT_EV5TJ
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
This is a variant of the ARM920. It has slightly different
instruction sequences for cache and TLB operations. Curiously,
@@ -144,8 +144,8 @@ config CPU_ARM1020
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM1020 is the 32K cached version of the ARM10 processor,
with an addition of a floating-point unit.
@@ -161,8 +161,8 @@ config CPU_ARM1020E
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
depends on n
# ARM1022E
@@ -172,8 +172,8 @@ config CPU_ARM1022
select CPU_32v5
select CPU_ABRT_EV4T
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB # can probably do better
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU # can probably do better
+ select CPU_TLB_V4WBI if MMU
help
The ARM1022E is an implementation of the ARMv5TE architecture
based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
@@ -189,8 +189,8 @@ config CPU_ARM1026
select CPU_32v5
select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB # can probably do better
- select CPU_TLB_V4WBI
+ select CPU_COPY_V4WB if MMU # can probably do better
+ select CPU_TLB_V4WBI if MMU
help
The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
based upon the ARM10 integer core.
@@ -207,8 +207,8 @@ config CPU_SA110
select CPU_ABRT_EV4
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WB
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WB if MMU
help
The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
is available at five speeds ranging from 100 MHz to 233 MHz.
@@ -227,7 +227,7 @@ config CPU_SA1100
select CPU_ABRT_EV4
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
- select CPU_TLB_V4WB
+ select CPU_TLB_V4WB if MMU
# XScale
config CPU_XSCALE
@@ -237,7 +237,7 @@ config CPU_XSCALE
select CPU_32v5
select CPU_ABRT_EV5T
select CPU_CACHE_VIVT
- select CPU_TLB_V4WBI
+ select CPU_TLB_V4WBI if MMU
# XScale Core Version 3
config CPU_XSC3
@@ -247,7 +247,7 @@ config CPU_XSC3
select CPU_32v5
select CPU_ABRT_EV5T
select CPU_CACHE_VIVT
- select CPU_TLB_V4WBI
+ select CPU_TLB_V4WBI if MMU
select IO_36
# ARMv6
@@ -258,8 +258,8 @@ config CPU_V6
select CPU_ABRT_EV6
select CPU_CACHE_V6
select CPU_CACHE_VIPT
- select CPU_COPY_V6
- select CPU_TLB_V6
+ select CPU_COPY_V6 if MMU
+ select CPU_TLB_V6 if MMU
# ARMv6k
config CPU_32v6K
@@ -277,17 +277,17 @@ config CPU_32v6K
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
bool
- select TLS_REG_EMUL if SMP
+ select TLS_REG_EMUL if SMP || !MMU
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
config CPU_32v4
bool
- select TLS_REG_EMUL if SMP
+ select TLS_REG_EMUL if SMP || !MMU
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
config CPU_32v5
bool
- select TLS_REG_EMUL if SMP
+ select TLS_REG_EMUL if SMP || !MMU
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
config CPU_32v6
@@ -334,6 +334,7 @@ config CPU_CACHE_VIVT
config CPU_CACHE_VIPT
bool
+if MMU
# The copy-page model
config CPU_COPY_V3
bool
@@ -372,6 +373,8 @@ config CPU_TLB_V4WBI
config CPU_TLB_V6
bool
+endif
+
#
# CPU supports 36-bit I/O
#
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 07a53850578..21a2770226e 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -2,10 +2,16 @@
# Makefile for the linux arm-specific parts of the memory manager.
#
-obj-y := consistent.o extable.o fault-armv.o \
- fault.o flush.o init.o ioremap.o mmap.o \
+obj-y := consistent.o extable.o fault.o init.o \
+ iomap.o
+
+obj-$(CONFIG_MMU) += fault-armv.o flush.o ioremap.o mmap.o \
mm-armv.o
+ifneq ($(CONFIG_MMU),y)
+obj-y += nommu.o
+endif
+
obj-$(CONFIG_MODULES) += proc-syms.o
obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
diff --git a/arch/arm/mm/copypage-v3.S b/arch/arm/mm/copypage-v3.S
index 3c58ebbf035..2ee394b11bc 100644
--- a/arch/arm/mm/copypage-v3.S
+++ b/arch/arm/mm/copypage-v3.S
@@ -35,7 +35,7 @@ ENTRY(v3_copy_user_page)
stmia r0!, {r3, r4, ip, lr} @ 4
ldmneia r1!, {r3, r4, ip, lr} @ 4
bne 1b @ 1
- LOADREGS(fd, sp!, {r4, pc}) @ 3
+ ldmfd sp!, {r4, pc} @ 3
.align 5
/*
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9ea1f87a707..989fd681c82 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -26,8 +26,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#define TABLE_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t))
-
DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
new file mode 100644
index 00000000000..62066f3020c
--- /dev/null
+++ b/arch/arm/mm/iomap.c
@@ -0,0 +1,55 @@
+/*
+ * linux/arch/arm/mm/iomap.c
+ *
+ * Map IO port and PCI memory spaces so that {read,write}[bwl] can
+ * be used to access this memory.
+ */
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+
+#include <asm/io.h>
+
+#ifdef __io
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+ return __io(port);
+}
+EXPORT_SYMBOL(ioport_map);
+
+void ioport_unmap(void __iomem *addr)
+{
+}
+EXPORT_SYMBOL(ioport_unmap);
+#endif
+
+#ifdef CONFIG_PCI
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
+{
+ unsigned long start = pci_resource_start(dev, bar);
+ unsigned long len = pci_resource_len(dev, bar);
+ unsigned long flags = pci_resource_flags(dev, bar);
+
+ if (!len || !start)
+ return NULL;
+ if (maxlen && len > maxlen)
+ len = maxlen;
+ if (flags & IORESOURCE_IO)
+ return ioport_map(start, len);
+ if (flags & IORESOURCE_MEM) {
+ if (flags & IORESOURCE_CACHEABLE)
+ return ioremap(start, len);
+ return ioremap_nocache(start, len);
+ }
+ return NULL;
+}
+EXPORT_SYMBOL(pci_iomap);
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{
+ if ((unsigned long)addr >= VMALLOC_START &&
+ (unsigned long)addr < VMALLOC_END)
+ iounmap(addr);
+}
+EXPORT_SYMBOL(pci_iounmap);
+#endif
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index c1f7180c7be..7691cfdba56 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -176,50 +176,3 @@ void __iounmap(void __iomem *addr)
vunmap((void *)(PAGE_MASK & (unsigned long)addr));
}
EXPORT_SYMBOL(__iounmap);
-
-#ifdef __io
-void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
- return __io(port);
-}
-EXPORT_SYMBOL(ioport_map);
-
-void ioport_unmap(void __iomem *addr)
-{
-}
-EXPORT_SYMBOL(ioport_unmap);
-#endif
-
-#ifdef CONFIG_PCI
-#include <linux/pci.h>
-#include <linux/ioport.h>
-
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
- unsigned long start = pci_resource_start(dev, bar);
- unsigned long len = pci_resource_len(dev, bar);
- unsigned long flags = pci_resource_flags(dev, bar);
-
- if (!len || !start)
- return NULL;
- if (maxlen && len > maxlen)
- len = maxlen;
- if (flags & IORESOURCE_IO)
- return ioport_map(start, len);
- if (flags & IORESOURCE_MEM) {
- if (flags & IORESOURCE_CACHEABLE)
- return ioremap(start, len);
- return ioremap_nocache(start, len);
- }
- return NULL;
-}
-EXPORT_SYMBOL(pci_iomap);
-
-void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
-{
- if ((unsigned long)addr >= VMALLOC_START &&
- (unsigned long)addr < VMALLOC_END)
- iounmap(addr);
-}
-EXPORT_SYMBOL(pci_iounmap);
-#endif
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
new file mode 100644
index 00000000000..1464ed817b5
--- /dev/null
+++ b/arch/arm/mm/nommu.c
@@ -0,0 +1,39 @@
+/*
+ * linux/arch/arm/mm/nommu.c
+ *
+ * ARM uCLinux supporting functions.
+ */
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/pagemap.h>
+
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/page.h>
+
+void flush_dcache_page(struct page *page)
+{
+ __cpuc_flush_dcache_page(page_address(page));
+}
+EXPORT_SYMBOL(flush_dcache_page);
+
+void __iomem *__ioremap_pfn(unsigned long pfn, unsigned long offset,
+ size_t size, unsigned long flags)
+{
+ if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
+ return NULL;
+ return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
+}
+EXPORT_SYMBOL(__ioremap_pfn);
+
+void __iomem *__ioremap(unsigned long phys_addr, size_t size,
+ unsigned long flags)
+{
+ return (void __iomem *)phys_addr;
+}
+EXPORT_SYMBOL(__ioremap);
+
+void __iounmap(void __iomem *addr)
+{
+}
+EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 959588884fa..b9abbafca81 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -359,6 +362,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm1020_switch_mm)
+#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r3, c7, c10, 4
mov r1, #0xF @ 16 segments
@@ -383,6 +387,7 @@ ENTRY(cpu_arm1020_switch_mm)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
+#endif /* CONFIG_MMU */
mov pc, lr
/*
@@ -392,6 +397,7 @@ ENTRY(cpu_arm1020_switch_mm)
*/
.align 5
ENTRY(cpu_arm1020_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -421,6 +427,7 @@ ENTRY(cpu_arm1020_set_pte)
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
@@ -430,7 +437,9 @@ __arm1020_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1020_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index be6d081ff2b..bcd5ee022e0 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020e_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -344,6 +347,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm1020e_switch_mm)
+#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r3, c7, c10, 4
mov r1, #0xF @ 16 segments
@@ -367,6 +371,7 @@ ENTRY(cpu_arm1020e_switch_mm)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -376,6 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
*/
.align 5
ENTRY(cpu_arm1020e_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -403,6 +409,7 @@ ENTRY(cpu_arm1020e_set_pte)
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
@@ -412,7 +419,9 @@ __arm1020e_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1020e_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index f778545d57a..b0ccff4fadd 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm1022_switch_mm)
+#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm)
*/
.align 5
ENTRY(cpu_arm1022_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte)
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
@@ -394,7 +401,9 @@ __arm1022_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm1022_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 148c111fde7..abe850c9a64 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1026_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -327,6 +330,7 @@ ENTRY(cpu_arm1026_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm1026_switch_mm)
+#ifdef CONFIG_MMU
mov r1, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
@@ -338,6 +342,7 @@ ENTRY(cpu_arm1026_switch_mm)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -347,6 +352,7 @@ ENTRY(cpu_arm1026_switch_mm)
*/
.align 5
ENTRY(cpu_arm1026_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -374,6 +380,7 @@ ENTRY(cpu_arm1026_set_pte)
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
+#endif /* CONFIG_MMU */
mov pc, lr
@@ -384,8 +391,10 @@ __arm1026_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
mcr p15, 0, r4, c2, c0 @ load page table pointer
+#endif
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ explicitly disable writeback
mcr p15, 7, r0, c15, c0, 0
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 540359b475d..7a705edfa4b 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -2,6 +2,7 @@
* linux/arch/arm/mm/proc-arm6,7.S
*
* Copyright (C) 1997-2000 Russell King
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -199,10 +200,12 @@ ENTRY(cpu_arm7_do_idle)
*/
ENTRY(cpu_arm6_switch_mm)
ENTRY(cpu_arm7_switch_mm)
+#ifdef CONFIG_MMU
mov r1, #0
mcr p15, 0, r1, c7, c0, 0 @ flush cache
mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
+#endif
mov pc, lr
/*
@@ -214,6 +217,7 @@ ENTRY(cpu_arm7_switch_mm)
.align 5
ENTRY(cpu_arm6_set_pte)
ENTRY(cpu_arm7_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -232,6 +236,7 @@ ENTRY(cpu_arm7_set_pte)
movne r2, #0
str r2, [r0] @ hardware version
+#endif /* CONFIG_MMU */
mov pc, lr
/*
@@ -243,7 +248,9 @@ ENTRY(cpu_arm6_reset)
ENTRY(cpu_arm7_reset)
mov r1, #0
mcr p15, 0, r1, c7, c0, 0 @ flush cache
+#ifdef CONFIG_MMU
mcr p15, 0, r1, c5, c0, 0 @ flush TLB
+#endif
mov r1, #0x30
mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
mov pc, r0
@@ -253,19 +260,27 @@ ENTRY(cpu_arm7_reset)
.type __arm6_setup, #function
__arm6_setup: mov r0, #0
mcr p15, 0, r0, c7, c0 @ flush caches on v3
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
mov r0, #0x3d @ . ..RS BLDP WCAM
orr r0, r0, #0x100 @ . ..01 0011 1101
+#else
+ mov r0, #0x3c @ . ..RS BLDP WCA.
+#endif
mov pc, lr
.size __arm6_setup, . - __arm6_setup
.type __arm7_setup, #function
__arm7_setup: mov r0, #0
mcr p15, 0, r0, c7, c0 @ flush caches on v3
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
mcr p15, 0, r0, c3, c0 @ load domain access register
mov r0, #0x7d @ . ..RS BLDP WCAM
orr r0, r0, #0x100 @ . ..01 0111 1101
+#else
+ mov r0, #0x7c @ . ..RS BLDP WCA.
+#endif
mov pc, lr
.size __arm7_setup, . - __arm7_setup
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 26f00ee2ad9..86102467d37 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -4,6 +4,7 @@
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
* Rob Scott (rscott@mtrob.fdns.net)
* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2004.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,6 +30,7 @@
* out of 'proc-arm6,7.S' per RMK discussion
* 07-25-2000 SJH Added idle function.
* 08-25-2000 DBS Updated for integration of ARM Ltd version.
+ * 04-20-2004 HSC modified for non-paged memory management mode.
*/
#include <linux/linkage.h>
#include <linux/init.h>
@@ -75,10 +77,12 @@ ENTRY(cpu_arm720_do_idle)
* the new.
*/
ENTRY(cpu_arm720_switch_mm)
+#ifdef CONFIG_MMU
mov r1, #0
mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
+#endif
mov pc, lr
/*
@@ -89,6 +93,7 @@ ENTRY(cpu_arm720_switch_mm)
*/
.align 5
ENTRY(cpu_arm720_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -107,6 +112,7 @@ ENTRY(cpu_arm720_set_pte)
movne r2, #0
str r2, [r0] @ hardware version
+#endif
mov pc, lr
/*
@@ -117,7 +123,9 @@ ENTRY(cpu_arm720_set_pte)
ENTRY(cpu_arm720_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
+#endif
mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x2100 @ ..v....s........
@@ -130,7 +138,9 @@ ENTRY(cpu_arm720_reset)
__arm710_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
+#endif
mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm710_cr1_clear
bic r0, r0, r5
@@ -156,7 +166,9 @@ arm710_cr1_set:
__arm720_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
+#endif
mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm720_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index a17f79e0199..31dc839ba07 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 1999,2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -97,7 +98,9 @@ ENTRY(cpu_arm920_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -317,6 +320,7 @@ ENTRY(cpu_arm920_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm920_switch_mm)
+#ifdef CONFIG_MMU
mov ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -337,6 +341,7 @@ ENTRY(cpu_arm920_switch_mm)
mcr p15, 0, ip, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -346,6 +351,7 @@ ENTRY(cpu_arm920_switch_mm)
*/
.align 5
ENTRY(cpu_arm920_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -372,6 +378,7 @@ ENTRY(cpu_arm920_set_pte)
mov r0, r0
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
@@ -381,7 +388,9 @@ __arm920_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm920_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bbde4a024a4..9e57c34f5c0 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -4,6 +4,7 @@
* Copyright (C) 1999,2000 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
* Copyright (C) 2001 Altera Corporation
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -99,7 +100,9 @@ ENTRY(cpu_arm922_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -321,6 +324,7 @@ ENTRY(cpu_arm922_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm922_switch_mm)
+#ifdef CONFIG_MMU
mov ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm922_switch_mm)
mcr p15, 0, ip, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
*/
.align 5
ENTRY(cpu_arm922_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -376,6 +382,7 @@ ENTRY(cpu_arm922_set_pte)
mov r0, r0
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
@@ -385,7 +392,9 @@ __arm922_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, arm922_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 224ce226a01..8d47c9f3f93 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -9,6 +9,8 @@
* Update for Linux-2.6 and cache flush improvements
* Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
*
+ * hacked for non-paged-MM by Hyok S. Choi, 2004.
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -122,7 +124,9 @@ ENTRY(cpu_arm925_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -369,6 +373,7 @@ ENTRY(cpu_arm925_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm925_switch_mm)
+#ifdef CONFIG_MMU
mov ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -383,6 +388,7 @@ ENTRY(cpu_arm925_switch_mm)
mcr p15, 0, ip, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -392,6 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
*/
.align 5
ENTRY(cpu_arm925_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -420,6 +427,7 @@ ENTRY(cpu_arm925_set_pte)
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif /* CONFIG_MMU */
mov pc, lr
__INIT
@@ -438,7 +446,9 @@ __arm925_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ disable write-back on caches explicitly
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 4e2a087cf38..cb4d8f33d2a 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -3,6 +3,7 @@
*
* Copyright (C) 1999-2001 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -85,7 +86,9 @@ ENTRY(cpu_arm926_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -329,6 +332,7 @@ ENTRY(cpu_arm926_dcache_clean_area)
*/
.align 5
ENTRY(cpu_arm926_switch_mm)
+#ifdef CONFIG_MMU
mov ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm926_switch_mm)
mcr p15, 0, ip, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mov pc, lr
/*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm926_switch_mm)
*/
.align 5
ENTRY(cpu_arm926_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -378,6 +384,7 @@ ENTRY(cpu_arm926_set_pte)
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif
mov pc, lr
__INIT
@@ -387,7 +394,9 @@ __arm926_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index a2dd5ae1077..5a760a2c629 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -2,6 +2,7 @@
* linux/arch/arm/mm/proc-sa110.S
*
* Copyright (C) 1997-2002 Russell King
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -67,7 +68,9 @@ ENTRY(cpu_sa110_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -130,11 +133,15 @@ ENTRY(cpu_sa110_dcache_clean_area)
*/
.align 5
ENTRY(cpu_sa110_switch_mm)
+#ifdef CONFIG_MMU
str lr, [sp, #-4]!
bl v4wb_flush_kern_cache_all @ clears IP
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
ldr pc, [sp], #4
+#else
+ mov pc, lr
+#endif
/*
* cpu_sa110_set_pte(ptep, pte)
@@ -143,6 +150,7 @@ ENTRY(cpu_sa110_switch_mm)
*/
.align 5
ENTRY(cpu_sa110_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -164,6 +172,7 @@ ENTRY(cpu_sa110_set_pte)
mov r0, r0
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif
mov pc, lr
__INIT
@@ -173,7 +182,9 @@ __sa110_setup:
mov r10, #0
mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa110_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 777ad99c143..0a2107ad4c3 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -2,6 +2,7 @@
* linux/arch/arm/mm/proc-sa1100.S
*
* Copyright (C) 1997-2002 Russell King
+ * hacked for non-paged-MM by Hyok S. Choi, 2003.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -77,7 +78,9 @@ ENTRY(cpu_sa1100_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
+#endif
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x1100 @ ...i...s........
@@ -142,12 +145,16 @@ ENTRY(cpu_sa1100_dcache_clean_area)
*/
.align 5
ENTRY(cpu_sa1100_switch_mm)
+#ifdef CONFIG_MMU
str lr, [sp, #-4]!
bl v4wb_flush_kern_cache_all @ clears IP
mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
ldr pc, [sp], #4
+#else
+ mov pc, lr
+#endif
/*
* cpu_sa1100_set_pte(ptep, pte)
@@ -156,6 +163,7 @@ ENTRY(cpu_sa1100_switch_mm)
*/
.align 5
ENTRY(cpu_sa1100_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -177,6 +185,7 @@ ENTRY(cpu_sa1100_set_pte)
mov r0, r0
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+#endif
mov pc, lr
__INIT
@@ -186,7 +195,9 @@ __sa1100_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
+#endif
mrc p15, 0, r0, c1, c0 @ get control register v4
ldr r5, sa1100_cr1_clear
bic r0, r0, r5
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ee6f1529873..ca13d4d05f6 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -2,6 +2,7 @@
* linux/arch/arm/mm/proc-v6.S
*
* Copyright (C) 2001 Deep Blue Solutions Ltd.
+ * Modified by Catalin Marinas for noMMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -29,38 +30,6 @@
#define TTB_RGN_WT (2 << 3)
#define TTB_RGN_WB (3 << 3)
- .macro cpsie, flags
- .ifc \flags, f
- .long 0xf1080040
- .exitm
- .endif
- .ifc \flags, i
- .long 0xf1080080
- .exitm
- .endif
- .ifc \flags, if
- .long 0xf10800c0
- .exitm
- .endif
- .err
- .endm
-
- .macro cpsid, flags
- .ifc \flags, f
- .long 0xf10c0040
- .exitm
- .endif
- .ifc \flags, i
- .long 0xf10c0080
- .exitm
- .endif
- .ifc \flags, if
- .long 0xf10c00c0
- .exitm
- .endif
- .err
- .endm
-
ENTRY(cpu_v6_proc_init)
mov pc, lr
@@ -120,6 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
* - we are not using split page tables
*/
ENTRY(cpu_v6_switch_mm)
+#ifdef CONFIG_MMU
mov r2, #0
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
#ifdef CONFIG_SMP
@@ -129,6 +99,7 @@ ENTRY(cpu_v6_switch_mm)
mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
mcr p15, 0, r1, c13, c0, 1 @ set context ID
+#endif
mov pc, lr
/*
@@ -151,6 +122,7 @@ ENTRY(cpu_v6_switch_mm)
* 1111 0 1 1 r/w r/w
*/
ENTRY(cpu_v6_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
bic r2, r1, #0x000003f0
@@ -177,6 +149,7 @@ ENTRY(cpu_v6_set_pte)
str r2, [r0]
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
+#endif
mov pc, lr
@@ -226,12 +199,14 @@ __v6_setup:
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
mcr p15, 0, r0, c2, c0, 2 @ TTB control register
#ifdef CONFIG_SMP
orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
#endif
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
+#endif /* CONFIG_MMU */
#ifdef CONFIG_VFP
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #(0xf << 20)
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-11-17 23:32:18 +0000