diff options
Diffstat (limited to 'arch/arm/plat-iop')
| -rw-r--r-- | arch/arm/plat-iop/Makefile | 8 | ||||
| -rw-r--r-- | arch/arm/plat-iop/gpio.c | 48 | ||||
| -rw-r--r-- | arch/arm/plat-iop/i2c.c | 81 | ||||
| -rw-r--r-- | arch/arm/plat-iop/pci.c | 247 | ||||
| -rw-r--r-- | arch/arm/plat-iop/setup.c | 38 | ||||
| -rw-r--r-- | arch/arm/plat-iop/time.c | 98 |
6 files changed, 520 insertions, 0 deletions
diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile new file mode 100644 index 00000000000..23da00b1151 --- /dev/null +++ b/arch/arm/plat-iop/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := gpio.o i2c.o pci.o setup.o time.o +obj-m := +obj-n := +obj- := diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c new file mode 100644 index 00000000000..eda43608341 --- /dev/null +++ b/arch/arm/plat-iop/gpio.c @@ -0,0 +1,48 @@ +/* + * arch/arm/plat-iop/gpio.c + * GPIO handling for Intel IOP3xx processors. + * + * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include <linux/device.h> +#include <asm/hardware/iop3xx.h> + +void gpio_line_config(int line, int direction) +{ + unsigned long flags; + + local_irq_save(flags); + if (direction == GPIO_IN) { + *IOP3XX_GPOE |= 1 << line; + } else if (direction == GPIO_OUT) { + *IOP3XX_GPOE &= ~(1 << line); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_config); + +int gpio_line_get(int line) +{ + return !!(*IOP3XX_GPID & (1 << line)); +} +EXPORT_SYMBOL(gpio_line_get); + +void gpio_line_set(int line, int value) +{ + unsigned long flags; + + local_irq_save(flags); + if (value == GPIO_LOW) { + *IOP3XX_GPOD &= ~(1 << line); + } else if (value == GPIO_HIGH) { + *IOP3XX_GPOD |= 1 << line; + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_set); diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c new file mode 100644 index 00000000000..e99909bdba7 --- /dev/null +++ b/arch/arm/plat-iop/i2c.c @@ -0,0 +1,81 @@ +/* + * arch/arm/plat-iop/i2c.c + * + * Author: Nicolas Pitre <nico@cam.org> + * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/major.h> +#include <linux/fs.h> +#include <linux/platform_device.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_core.h> +#include <asm/io.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/system.h> +#include <asm/memory.h> +#include <asm/hardware.h> +#include <asm/hardware/iop3xx.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#ifdef CONFIG_ARCH_IOP32X +#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0 +#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1 +#endif +#ifdef CONFIG_ARCH_IOP33X +#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0 +#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1 +#endif + +static struct resource iop3xx_i2c0_resources[] = { + [0] = { + .start = 0xfffff680, + .end = 0xfffff697, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP3XX_I2C_0, + .end = IRQ_IOP3XX_I2C_0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device iop3xx_i2c0_device = { + .name = "IOP3xx-I2C", + .id = 0, + .num_resources = 2, + .resource = iop3xx_i2c0_resources, +}; + + +static struct resource iop3xx_i2c1_resources[] = { + [0] = { + .start = 0xfffff6a0, + .end = 0xfffff6b7, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IOP3XX_I2C_1, + .end = IRQ_IOP3XX_I2C_1, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device iop3xx_i2c1_device = { + .name = "IOP3xx-I2C", + .id = 1, + .num_resources = 2, + .resource = iop3xx_i2c1_resources, +}; diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c new file mode 100644 index 00000000000..e647812654f --- /dev/null +++ b/arch/arm/plat-iop/pci.c @@ -0,0 +1,247 @@ +/* + * arch/arm/plat-iop/pci.c + * + * PCI support for the Intel IOP32X and IOP33X processors + * + * Author: Rory Bolt <rorybolt@pacbell.net> + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/slab.h> +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/system.h> +#include <asm/hardware.h> +#include <asm/mach/pci.h> +#include <asm/hardware/iop3xx.h> + +// #define DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) do { } while (0) +#endif + +/* + * This routine builds either a type0 or type1 configuration command. If the + * bus is on the 803xx then a type0 made, else a type1 is created. + */ +static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) +{ + struct pci_sys_data *sys = bus->sysdata; + u32 addr; + + if (sys->busnr == bus->number) + addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); + else + addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; + + addr |= PCI_FUNC(devfn) << 8 | (where & ~3); + + return addr; +} + +/* + * This routine checks the status of the last configuration cycle. If an error + * was detected it returns a 1, else it returns a 0. The errors being checked + * are parity, master abort, target abort (master and target). These types of + * errors occure during a config cycle where there is no device, like during + * the discovery stage. + */ +static int iop3xx_pci_status(void) +{ + unsigned int status; + int ret = 0; + + /* + * Check the status registers. + */ + status = *IOP3XX_ATUSR; + if (status & 0xf900) { + DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); + *IOP3XX_ATUSR = status & 0xf900; + ret = 1; + } + + status = *IOP3XX_ATUISR; + if (status & 0x679f) { + DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); + *IOP3XX_ATUISR = status & 0x679f; + ret = 1; + } + + return ret; +} + +/* + * Simply write the address register and read the configuration + * data. Note that the 4 nop's ensure that we are able to handle + * a delayed abort (in theory.) + */ +static inline u32 iop3xx_read(unsigned long addr) +{ + u32 val; + + __asm__ __volatile__( + "str %1, [%2]\n\t" + "ldr %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : "=r" (val) + : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); + + return val; +} + +/* + * The read routines must check the error status of the last configuration + * cycle. If there was an error, the routine returns all hex f's. + */ +static int +iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + unsigned long addr = iop3xx_cfg_address(bus, devfn, where); + u32 val = iop3xx_read(addr) >> ((where & 3) * 8); + + if (iop3xx_pci_status()) + val = 0xffffffff; + + *value = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + unsigned long addr = iop3xx_cfg_address(bus, devfn, where); + u32 val; + + if (size != 4) { + val = iop3xx_read(addr); + if (iop3xx_pci_status()) + return PCIBIOS_SUCCESSFUL; + + where = (where & 3) * 8; + + if (size == 1) + val &= ~(0xff << where); + else + val &= ~(0xffff << where); + + *IOP3XX_OCCDR = val | value << where; + } else { + asm volatile( + "str %1, [%2]\n\t" + "str %0, [%3]\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + : + : "r" (value), "r" (addr), + "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops iop3xx_ops = { + .read = iop3xx_read_config, + .write = iop3xx_write_config, +}; + +/* + * When a PCI device does not exist during config cycles, the 80200 gets a + * bus error instead of returning 0xffffffff. This handler simply returns. + */ +static int +iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", + addr, fsr, regs->ARM_pc, regs->ARM_lr); + + /* + * If it was an imprecise abort, then we need to correct the + * return address to be _after_ the instruction. + */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + + return 0; +} + +int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if (nr != 0) + return 0; + + res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + res[0].start = IOP3XX_PCI_LOWER_IO_VA; + res[0].end = IOP3XX_PCI_LOWER_IO_VA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; + res[0].name = "IOP3XX PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + request_resource(&ioport_resource, &res[0]); + + res[1].start = IOP3XX_PCI_LOWER_MEM_PA; + res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; + res[1].name = "IOP3XX PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &res[1]); + + sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA; + sys->io_offset = IOP3XX_PCI_LOWER_IO_VA - IOP3XX_PCI_LOWER_IO_BA; + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + + return 1; +} + +struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); +} + +void iop3xx_pci_preinit(void) +{ + DBG("PCI: Intel 803xx PCI init code.\n"); + DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); + DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", + *IOP3XX_OMWTVR0, + *IOP3XX_OIOWTVR); + DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); + DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n", + *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); + DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0); + DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n", + *IOP3XX_IABAR1, *IOP3XX_IALR1); + DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n", + *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); + DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n", + *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); + DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n", + *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); + + hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); +} diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c new file mode 100644 index 00000000000..4689db638e9 --- /dev/null +++ b/arch/arm/plat-iop/setup.c @@ -0,0 +1,38 @@ +/* + * arch/arm/plat-iop/setup.c + * + * Author: Nicolas Pitre <nico@cam.org> + * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2004 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <asm/mach/map.h> +#include <asm/hardware/iop3xx.h> + +/* + * Standard IO mapping for all IOP3xx based systems + */ +static struct map_desc iop3xx_std_desc[] __initdata = { + { /* mem mapped registers */ + .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, + .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), + .length = IOP3XX_PERIPHERAL_SIZE, + .type = MT_DEVICE, + }, { /* PCI IO space */ + .virtual = IOP3XX_PCI_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA), + .length = IOP3XX_PCI_IO_WINDOW_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init iop3xx_map_io(void) +{ + iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc)); +} diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c new file mode 100644 index 00000000000..06282dffbdc --- /dev/null +++ b/arch/arm/plat-iop/time.c @@ -0,0 +1,98 @@ +/* + * arch/arm/plat-iop/time.c + * + * Timer code for IOP32x and IOP33x based systems + * + * Author: Deepak Saxena <dsaxena@mvista.com> + * + * Copyright 2002-2003 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/time.h> +#include <linux/init.h> +#include <linux/timex.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/uaccess.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> + +#ifdef CONFIG_ARCH_IOP32X +#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0 +#else +#ifdef CONFIG_ARCH_IOP33X +#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0 +#endif +#endif + +static unsigned long ticks_per_jiffy; +static unsigned long ticks_per_usec; +static unsigned long next_jiffy_time; + +unsigned long iop3xx_gettimeoffset(void) +{ + unsigned long offset; + + offset = next_jiffy_time - *IOP3XX_TU_TCR1; + + return offset / ticks_per_usec; +} + +static irqreturn_t +iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + write_seqlock(&xtime_lock); + + iop3xx_cp6_enable(); + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); + iop3xx_cp6_disable(); + + while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) + >= ticks_per_jiffy) { + timer_tick(regs); + next_jiffy_time -= ticks_per_jiffy; + } + + write_sequnlock(&xtime_lock); + + return IRQ_HANDLED; +} + +static struct irqaction iop3xx_timer_irq = { + .name = "IOP3XX Timer Tick", + .handler = iop3xx_timer_interrupt, + .flags = IRQF_DISABLED | IRQF_TIMER, +}; + +void __init iop3xx_init_time(unsigned long tick_rate) +{ + u32 timer_ctl; + + ticks_per_jiffy = (tick_rate + HZ/2) / HZ; + ticks_per_usec = tick_rate / 1000000; + next_jiffy_time = 0xffffffff; + + timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED | + IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1; + + /* + * We use timer 0 for our timer interrupt, and timer 1 as + * monotonic counter for tracking missed jiffies. + */ + iop3xx_cp6_enable(); + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); + asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); + asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); + iop3xx_cp6_disable(); + + setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); +} |