summaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/include/plat/irqs.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/include/plat/irqs.h')
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h102
1 files changed, 13 insertions, 89 deletions
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c0ab7c80f72..b65088a869e 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -28,6 +28,9 @@
#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
#define __ASM_ARCH_OMAP15XX_IRQS_H
+/* All OMAP4 specific defines are moved to irqs-44xx.h */
+#include "irqs-44xx.h"
+
/*
* IRQ numbers for interrupt handler 1
*
@@ -344,95 +347,16 @@
#define INT_34XX_BENCH_MPU_EMUL 3
-
-#define IRQ_GIC_START 32
-#define INT_44XX_LOCALTIMER_IRQ 29
-#define INT_44XX_LOCALWDT_IRQ 30
-
-#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
-#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
-#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
-#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
-#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
-#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
-#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
-#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
-#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
-#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
-#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
-#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
-#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
-#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
-#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
-#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
-#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
-#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
-#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
-#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
-#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
-#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
-#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
-#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
-#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
-#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
-#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
-
-#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
-#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
-#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
-#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
-#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
-#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
-
-#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
-#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
-#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
-#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
-#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
-#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
-#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
-#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
-#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
-#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
-#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
-#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
-#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
-#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
-#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
-#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
-#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
-#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
-
+#define INT_35XX_HECC0_IRQ 24
+#define INT_35XX_HECC1_IRQ 28
+#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
+#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68
+#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
+#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
+#define INT_35XX_USBOTG_IRQ 71
+#define INT_35XX_CCDC_VD0_IRQ 88
+#define INT_35XX_CCDC_VD1_IRQ 92
+#define INT_35XX_CCDC_VD2_IRQ 93
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
* 16 MPUIO lines */