summaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/include/plat/powerdomain.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/include/plat/powerdomain.h')
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h17
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 3d45ee1d3cf..0b960051eae 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -28,6 +28,8 @@
#define PWRDM_POWER_INACTIVE 0x2
#define PWRDM_POWER_ON 0x3
+#define PWRDM_MAX_PWRSTS 4
+
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
(1 << PWRDM_POWER_ON))
@@ -40,7 +42,10 @@
/* Powerdomain flags */
#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
-
+#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+ * in MEM bank 1 position. This is
+ * true for OMAP3430
+ */
/*
* Number of memory banks that are power-controllable. On OMAP3430, the
@@ -85,15 +90,15 @@ struct powerdomain {
/* Used to represent the OMAP chip types containing this pwrdm */
const struct omap_chip_id omap_chip;
- /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
- const u8 dep_bit;
-
/* Powerdomains that can be told to wake this powerdomain up */
struct pwrdm_dep *wkdep_srcs;
/* Powerdomains that can be told to keep this pwrdm from inactivity */
struct pwrdm_dep *sleepdep_srcs;
+ /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
+ const u8 dep_bit;
+
/* Possible powerdomain power states */
const u8 pwrsts;
@@ -118,11 +123,11 @@ struct powerdomain {
struct list_head node;
int state;
- unsigned state_counter[4];
+ unsigned state_counter[PWRDM_MAX_PWRSTS];
#ifdef CONFIG_PM_DEBUG
s64 timer;
- s64 state_timer[4];
+ s64 state_timer[PWRDM_MAX_PWRSTS];
#endif
};