diff options
Diffstat (limited to 'arch/arm/plat-omap/include')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/gpio.h | 29 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/hardware.h | 6 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/io.h | 277 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/keypad.h | 2 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/mcspi.h | 3 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap_device.h | 2 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/serial.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/tc.h | 17 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/usb.h | 41 |
9 files changed, 67 insertions, 311 deletions
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 9e86ee0aed0..cb75b657b04 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -162,13 +162,6 @@ IH_MPUIO_BASE + ((nr) & 0x0f) : \ IH_GPIO_BASE + (nr)) -#define METHOD_MPUIO 0 -#define METHOD_GPIO_1510 1 -#define METHOD_GPIO_1610 2 -#define METHOD_GPIO_7XX 3 -#define METHOD_GPIO_24XX 5 -#define METHOD_GPIO_44XX 6 - struct omap_gpio_dev_attr { int bank_width; /* GPIO bank width */ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ @@ -184,10 +177,21 @@ struct omap_gpio_reg_offs { u16 irqstatus; u16 irqstatus2; u16 irqenable; + u16 irqenable2; u16 set_irqenable; u16 clr_irqenable; u16 debounce; u16 debounce_en; + u16 ctrl; + u16 wkup_en; + u16 leveldetect0; + u16 leveldetect1; + u16 risingdetect; + u16 fallingdetect; + u16 irqctrl; + u16 edgectrl1; + u16 edgectrl2; + u16 pinctrl; bool irqenable_inv; }; @@ -198,19 +202,20 @@ struct omap_gpio_platform_data { int bank_width; /* GPIO bank width */ int bank_stride; /* Only needed for omap1 MPUIO */ bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ + bool loses_context; /* whether the bank would ever lose context */ + bool is_mpuio; /* whether the bank is of type MPUIO */ + u32 non_wakeup_gpios; struct omap_gpio_reg_offs *regs; -}; -/* TODO: Analyze removing gpio_bank_count usage from driver code */ -extern int gpio_bank_count; + /* Return context loss count due to PM states changing */ + int (*get_context_loss_count)(struct device *dev); +}; extern void omap2_gpio_prepare_for_idle(int off_mode); extern void omap2_gpio_resume_after_idle(void); extern void omap_set_gpio_debounce(int gpio, int enable); extern void omap_set_gpio_debounce_time(int gpio, int enable); -extern void omap_gpio_save_context(void); -extern void omap_gpio_restore_context(void); /*-------------------------------------------------------------------------*/ /* Wrappers for "new style" GPIO calls, using the new infrastructure diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index e897978371c..537b05ae1f5 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -43,6 +43,12 @@ #endif #include <plat/serial.h> +#ifdef __ASSEMBLER__ +#define IOMEM(x) (x) +#else +#define IOMEM(x) ((void __force __iomem *)(x)) +#endif + /* * --------------------------------------------------------------------------- * Common definitions for all OMAP processors diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h deleted file mode 100644 index 0696bae1818..00000000000 --- a/arch/arm/plat-omap/include/plat/io.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/io.h - * - * IO definitions for TI OMAP processors and boards - * - * Copied from arch/arm/mach-sa1100/include/mach/io.h - * Copyright (C) 1997-1999 Russell King - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We don't actually have real ISA nor PCI buses, but there is so many - * drivers out there that might just work if we fake them... - */ -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -/* - * ---------------------------------------------------------------------------- - * I/O mapping - * ---------------------------------------------------------------------------- - */ - -#ifdef __ASSEMBLER__ -#define IOMEM(x) (x) -#else -#define IOMEM(x) ((void __force __iomem *)(x)) -#endif - -#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ -#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) - -#define OMAP2_L3_IO_OFFSET 0x90000000 -#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ - - -#define OMAP2_L4_IO_OFFSET 0xb2000000 -#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ - -#define OMAP4_L3_IO_OFFSET 0xb4000000 -#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ - -#define AM33XX_L4_WK_IO_OFFSET 0xb5000000 -#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) - -#define OMAP4_L3_PER_IO_OFFSET 0xb1100000 -#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) - -#define OMAP4_GPMC_IO_OFFSET 0xa9000000 -#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) - -#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ -#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) - -/* - * ---------------------------------------------------------------------------- - * Omap1 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -#define OMAP1_IO_PHYS 0xFFFB0000 -#define OMAP1_IO_SIZE 0x40000 -#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) - -/* - * ---------------------------------------------------------------------------- - * Omap2 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -/* We map both L3 and L4 on OMAP2 */ -#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ -#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) -#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ -#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ -#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ - -#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ -#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_WK_243X_SIZE SZ_1M -#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE -#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) - /* 0x6e000000 --> 0xfe000000 */ -#define OMAP243X_GPMC_SIZE SZ_1M -#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE - /* 0x6D000000 --> 0xfd000000 */ -#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) -#define OMAP243X_SDRC_SIZE SZ_1M -#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE - /* 0x6c000000 --> 0xfc000000 */ -#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) -#define OMAP243X_SMS_SIZE SZ_1M - -/* 2420 IVA */ -#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE - /* 0x58000000 --> 0xfc100000 */ -#define DSP_MEM_2420_VIRT 0xfc100000 -#define DSP_MEM_2420_SIZE 0x28000 -#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE - /* 0x59000000 --> 0xfc128000 */ -#define DSP_IPI_2420_VIRT 0xfc128000 -#define DSP_IPI_2420_SIZE SZ_4K -#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE - /* 0x5a000000 --> 0xfc129000 */ -#define DSP_MMU_2420_VIRT 0xfc129000 -#define DSP_MMU_2420_SIZE SZ_4K - -/* 2430 IVA2.1 - currently unmapped */ - -/* - * ---------------------------------------------------------------------------- - * Omap3 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -/* We map both L3 and L4 on OMAP3 */ -#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ -#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) -#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ - -#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ -#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ - -/* - * ---------------------------------------------------------------------------- - * AM33XX specific IO mapping - * ---------------------------------------------------------------------------- - */ -#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE -#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET) -#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ - -/* - * Need to look at the Size 4M for L4. - * VPOM3430 was not working for Int controller - */ - -#define L4_PER_34XX_PHYS L4_PER_34XX_BASE - /* 0x49000000 --> 0xfb000000 */ -#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_PER_34XX_SIZE SZ_1M - -#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE - /* 0x54000000 --> 0xfe800000 */ -#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) -#define L4_EMU_34XX_SIZE SZ_8M - -#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE - /* 0x6e000000 --> 0xfe000000 */ -#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) -#define OMAP34XX_GPMC_SIZE SZ_1M - -#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE - /* 0x6c000000 --> 0xfc000000 */ -#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) -#define OMAP343X_SMS_SIZE SZ_1M - -#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE - /* 0x6D000000 --> 0xfd000000 */ -#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) -#define OMAP343X_SDRC_SIZE SZ_1M - -/* 3430 IVA - currently unmapped */ - -/* - * ---------------------------------------------------------------------------- - * Omap4 specific IO mapping - * ---------------------------------------------------------------------------- - */ - -/* We map both L3 and L4 on OMAP4 */ -#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ -#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) -#define L3_44XX_SIZE SZ_1M - -#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ -#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_44XX_SIZE SZ_4M - -#define L4_PER_44XX_PHYS L4_PER_44XX_BASE - /* 0x48000000 --> 0xfa000000 */ -#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_PER_44XX_SIZE SZ_4M - -#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE - /* 0x49000000 --> 0xfb000000 */ -#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) -#define L4_ABE_44XX_SIZE SZ_1M - -#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE - /* 0x54000000 --> 0xfe800000 */ -#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) -#define L4_EMU_44XX_SIZE SZ_8M - -#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE - /* 0x50000000 --> 0xf9000000 */ -#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) -#define OMAP44XX_GPMC_SIZE SZ_1M - - -#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE - /* 0x4c000000 --> 0xfd100000 */ -#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) -#define OMAP44XX_EMIF1_SIZE SZ_1M - -#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE - /* 0x4d000000 --> 0xfd200000 */ -#define OMAP44XX_EMIF2_SIZE SZ_1M -#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE) - -#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE - /* 0x4e000000 --> 0xfd300000 */ -#define OMAP44XX_DMM_SIZE SZ_1M -#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE) -/* - * ---------------------------------------------------------------------------- - * Omap specific register access - * ---------------------------------------------------------------------------- - */ - -#ifndef __ASSEMBLER__ - -/* - * NOTE: Please use ioremap + __raw_read/write where possible instead of these - */ - -extern u8 omap_readb(u32 pa); -extern u16 omap_readw(u32 pa); -extern u32 omap_readl(u32 pa); -extern void omap_writeb(u8 v, u32 pa); -extern void omap_writew(u16 v, u32 pa); -extern void omap_writel(u32 v, u32 pa); - -struct omap_sdrc_params; -extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1); - -extern void __init omap_init_consistent_dma_size(void); - -#endif - -#endif diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h index 793ce9d5329..a6b21eddb21 100644 --- a/arch/arm/plat-omap/include/plat/keypad.h +++ b/arch/arm/plat-omap/include/plat/keypad.h @@ -12,6 +12,8 @@ #ifndef CONFIG_ARCH_OMAP1 #warning Please update the board to use matrix-keypad driver +#define omap_readw(reg) 0 +#define omap_writew(val, reg) do {} while (0) #endif #include <linux/input/matrix_keypad.h> diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 3d51b18131c..a357eb26bd2 100644 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h @@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr { struct omap2_mcspi_device_config { unsigned turbo_mode:1; - - /* Do we want one channel enabled at the same time? */ - unsigned single_channel:1; }; #endif diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 05f7615b61f..4327b2c90c3 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -36,7 +36,7 @@ #include <plat/omap_hwmod.h> -extern struct device omap_device_parent; +extern struct dev_pm_domain omap_device_pm_domain; /* omap_device._state values */ #define OMAP_DEVICE_STATE_UNKNOWN 0 diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 198d1e6a4a6..b073e5f2b19 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -110,7 +110,6 @@ struct omap_board_data; struct omap_uart_port_info; extern void omap_serial_init(void); -extern int omap_uart_can_sleep(void); extern void omap_serial_board_init(struct omap_uart_port_info *platform_data); extern void omap_serial_init_port(struct omap_board_data *bdata, struct omap_uart_port_info *platform_data); diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h index d2fcd789bb9..1b4b2da8620 100644 --- a/arch/arm/plat-omap/include/plat/tc.h +++ b/arch/arm/plat-omap/include/plat/tc.h @@ -84,23 +84,6 @@ #define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) #define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) -/* Almost all documentation for chip and board memory maps assumes - * BM is clear. Most devel boards have a switch to control booting - * from NOR flash (using external chipselect 3) rather than mask ROM, - * which uses BM to interchange the physical CS0 and CS3 addresses. - */ -static inline u32 omap_cs0_phys(void) -{ - return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) - ? OMAP_CS3_PHYS : 0; -} - -static inline u32 omap_cs3_phys(void) -{ - return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) - ? 0 : OMAP_CS3_PHYS; -} - #endif /* __ASSEMBLER__ */ #endif /* __ASM_ARCH_TC_H */ diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index dc864b580da..d0fc9f4dc15 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -3,6 +3,7 @@ #ifndef __ASM_ARCH_OMAP_USB_H #define __ASM_ARCH_OMAP_USB_H +#include <linux/io.h> #include <linux/usb/musb.h> #include <plat/board.h> @@ -105,6 +106,46 @@ extern int omap4430_phy_set_clk(struct device *dev, int on); extern int omap4430_phy_init(struct device *dev); extern int omap4430_phy_exit(struct device *dev); extern int omap4430_phy_suspend(struct device *dev, int suspend); + +/* + * NOTE: Please update omap USB drivers to use ioremap + read/write + */ + +#define OMAP2_L4_IO_OFFSET 0xb2000000 +#define IOMEM(x) ((void __force __iomem *)(x)) +#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) + +static inline u8 omap_readb(u32 pa) +{ + return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); +} + +static inline u16 omap_readw(u32 pa) +{ + return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); +} + +static inline u32 omap_readl(u32 pa) +{ + return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); +} + +static inline void omap_writeb(u8 v, u32 pa) +{ + __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); +} + + +static inline void omap_writew(u16 v, u32 pa) +{ + __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); +} + +static inline void omap_writel(u32 v, u32 pa) +{ + __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); +} + #endif extern void am35x_musb_reset(void); |