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-rw-r--r--arch/arm/plat-s3c24xx/adc.c11
-rw-r--r--arch/arm/plat-s3c24xx/devs.c30
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c8
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h1
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm-core.h5
-rw-r--r--arch/arm/plat-s3c24xx/pm.c213
6 files changed, 20 insertions, 248 deletions
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index 91adfa71c17..ee1baf11ad9 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -45,7 +45,8 @@ struct s3c_adc_client {
unsigned char channel;
void (*select_cb)(unsigned selected);
- void (*convert_cb)(unsigned val1, unsigned val2);
+ void (*convert_cb)(unsigned val1, unsigned val2,
+ unsigned *samples_left);
};
struct adc_device {
@@ -158,7 +159,8 @@ static void s3c_adc_default_select(unsigned select)
struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned int selected),
- void (*conv)(unsigned d0, unsigned d1),
+ void (*conv)(unsigned d0, unsigned d1,
+ unsigned *samples_left),
unsigned int is_ts)
{
struct s3c_adc_client *client;
@@ -227,9 +229,10 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
data1 = readl(adc->regs + S3C2410_ADCDAT1);
adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
- (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff);
+ client->nr_samples--;
+ (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
- if (--client->nr_samples > 0) {
+ if (client->nr_samples > 0) {
/* fire another conversion for this */
client->select_cb(1);
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 16ac01d9b8a..4eb378c89a3 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src[4] = {
struct platform_device *s3c24xx_uart_devs[4] = {
};
-/* USB Host Controller */
-
-static struct resource s3c_usb_resource[] = {
- [0] = {
- .start = S3C24XX_PA_USBHOST,
- .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_USBH,
- .end = IRQ_USBH,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 s3c_device_usb_dmamask = 0xffffffffUL;
-
-struct platform_device s3c_device_usb = {
- .name = "s3c2410-ohci",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_usb_resource),
- .resource = s3c_usb_resource,
- .dev = {
- .dma_mask = &s3c_device_usb_dmamask,
- .coherent_dma_mask = 0xffffffffUL
- }
-};
-
-EXPORT_SYMBOL(s3c_device_usb);
-
/* LCD Controller */
static struct resource s3c_lcd_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 5c0491bf738..4bac12dc073 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -22,6 +22,7 @@
#include <mach/gpio-core.h>
#include <mach/hardware.h>
#include <asm/irq.h>
+#include <plat/pm.h>
#include <mach/regs-gpio.h>
@@ -78,6 +79,7 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
struct s3c_gpio_chip s3c24xx_gpios[] = {
[0] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
+ .pm = __gpio_pm(&s3c_gpio_pm_1bit),
.chip = {
.base = S3C2410_GPA0,
.owner = THIS_MODULE,
@@ -89,6 +91,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
[1] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPB0,
.owner = THIS_MODULE,
@@ -98,6 +101,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
[2] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPC0,
.owner = THIS_MODULE,
@@ -107,6 +111,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
[3] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPD0,
.owner = THIS_MODULE,
@@ -116,6 +121,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
[4] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPE0,
.label = "GPIOE",
@@ -125,6 +131,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
[5] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPF0,
.owner = THIS_MODULE,
@@ -135,6 +142,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
[6] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPG0,
.owner = THIS_MODULE,
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index eed8f78e759..c4d133436fc 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -58,7 +58,6 @@
#define S3C24XX_SZ_SPI SZ_1M
#define S3C24XX_SZ_SDI SZ_1M
#define S3C24XX_SZ_NAND SZ_1M
-#define S3C24XX_SZ_USBHOST SZ_1M
/* GPIO ports */
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
index c75882113e0..fb45dd9adca 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pm-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -57,3 +57,8 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
s3c_irqwake_eintmask);
}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+ struct pm_uart_save *save)
+{
+}
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 062a29339a9..5135c40a1b9 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -75,43 +75,10 @@ static struct sleep_save core_save[] = {
SAVE_ITEM(S3C2410_CLKSLOW),
};
-static struct gpio_sleep {
- void __iomem *base;
- unsigned int gpcon;
- unsigned int gpdat;
- unsigned int gpup;
-} gpio_save[] = {
- [0] = {
- .base = S3C2410_GPACON,
- },
- [1] = {
- .base = S3C2410_GPBCON,
- },
- [2] = {
- .base = S3C2410_GPCCON,
- },
- [3] = {
- .base = S3C2410_GPDCON,
- },
- [4] = {
- .base = S3C2410_GPECON,
- },
- [5] = {
- .base = S3C2410_GPFCON,
- },
- [6] = {
- .base = S3C2410_GPGCON,
- },
- [7] = {
- .base = S3C2410_GPHCON,
- },
-};
-
static struct sleep_save misc_save[] = {
SAVE_ITEM(S3C2410_DCLKCON),
};
-
/* s3c_pm_check_resume_pin
*
* check to see if the pin is configured correctly for sleep mode, and
@@ -165,186 +132,6 @@ void s3c_pm_configure_extint(void)
}
}
-/* offsets for CON/DAT/UP registers */
-
-#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
-#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
-#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
-
-/* s3c_pm_save_gpios()
- *
- * Save the state of the GPIOs
- */
-
-void s3c_pm_save_gpios(void)
-{
- struct gpio_sleep *gps = gpio_save;
- unsigned int gpio;
-
- for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
- void __iomem *base = gps->base;
-
- gps->gpcon = __raw_readl(base + OFFS_CON);
- gps->gpdat = __raw_readl(base + OFFS_DAT);
-
- if (gpio > 0)
- gps->gpup = __raw_readl(base + OFFS_UP);
-
- }
-}
-
-/* Test whether the given masked+shifted bits of an GPIO configuration
- * are one of the SFN (special function) modes. */
-
-static inline int is_sfn(unsigned long con)
-{
- return (con == 2 || con == 3);
-}
-
-/* Test if the given masked+shifted GPIO configuration is an input */
-
-static inline int is_in(unsigned long con)
-{
- return con == 0;
-}
-
-/* Test if the given masked+shifted GPIO configuration is an output */
-
-static inline int is_out(unsigned long con)
-{
- return con == 1;
-}
-
-/**
- * s3c2410_pm_restore_gpio() - restore the given GPIO bank
- * @index: The number of the GPIO bank being resumed.
- * @gps: The sleep confgiuration for the bank.
- *
- * Restore one of the GPIO banks that was saved during suspend. This is
- * not as simple as once thought, due to the possibility of glitches
- * from the order that the CON and DAT registers are set in.
- *
- * The three states the pin can be are {IN,OUT,SFN} which gives us 9
- * combinations of changes to check. Three of these, if the pin stays
- * in the same configuration can be discounted. This leaves us with
- * the following:
- *
- * { IN => OUT } Change DAT first
- * { IN => SFN } Change CON first
- * { OUT => SFN } Change CON first, so new data will not glitch
- * { OUT => IN } Change CON first, so new data will not glitch
- * { SFN => IN } Change CON first
- * { SFN => OUT } Change DAT first, so new data will not glitch [1]
- *
- * We do not currently deal with the UP registers as these control
- * weak resistors, so a small delay in change should not need to bring
- * these into the calculations.
- *
- * [1] this assumes that writing to a pin DAT whilst in SFN will set the
- * state for when it is next output.
- */
-
-static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
-{
- void __iomem *base = gps->base;
- unsigned long gps_gpcon = gps->gpcon;
- unsigned long gps_gpdat = gps->gpdat;
- unsigned long old_gpcon;
- unsigned long old_gpdat;
- unsigned long old_gpup = 0x0;
- unsigned long gpcon;
- int nr;
-
- old_gpcon = __raw_readl(base + OFFS_CON);
- old_gpdat = __raw_readl(base + OFFS_DAT);
-
- if (base == S3C2410_GPACON) {
- /* GPACON only has one bit per control / data and no PULLUPs.
- * GPACON[x] = 0 => Output, 1 => SFN */
-
- /* first set all SFN bits to SFN */
-
- gpcon = old_gpcon | gps->gpcon;
- __raw_writel(gpcon, base + OFFS_CON);
-
- /* now set all the other bits */
-
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
- } else {
- unsigned long old, new, mask;
- unsigned long change_mask = 0x0;
-
- old_gpup = __raw_readl(base + OFFS_UP);
-
- /* Create a change_mask of all the items that need to have
- * their CON value changed before their DAT value, so that
- * we minimise the work between the two settings.
- */
-
- for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
- old = (old_gpcon & mask) >> nr;
- new = (gps_gpcon & mask) >> nr;
-
- /* If there is no change, then skip */
-
- if (old == new)
- continue;
-
- /* If both are special function, then skip */
-
- if (is_sfn(old) && is_sfn(new))
- continue;
-
- /* Change is IN => OUT, do not change now */
-
- if (is_in(old) && is_out(new))
- continue;
-
- /* Change is SFN => OUT, do not change now */
-
- if (is_sfn(old) && is_out(new))
- continue;
-
- /* We should now be at the case of IN=>SFN,
- * OUT=>SFN, OUT=>IN, SFN=>IN. */
-
- change_mask |= mask;
- }
-
- /* Write the new CON settings */
-
- gpcon = old_gpcon & ~change_mask;
- gpcon |= gps_gpcon & change_mask;
-
- __raw_writel(gpcon, base + OFFS_CON);
-
- /* Now change any items that require DAT,CON */
-
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
- __raw_writel(gps->gpup, base + OFFS_UP);
- }
-
- S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
- index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
-}
-
-
-/** s3c2410_pm_restore_gpios()
- *
- * Restore the state of the GPIOs
- */
-
-void s3c_pm_restore_gpios(void)
-{
- struct gpio_sleep *gps = gpio_save;
- int gpio;
-
- for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
- s3c2410_pm_restore_gpio(gpio, gps);
- }
-}
void s3c_pm_restore_core(void)
{
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-18 01:57:50 +0000