diff options
Diffstat (limited to 'arch/arm/plat-s3c64xx')
| -rw-r--r-- | arch/arm/plat-s3c64xx/Kconfig | 10 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/Makefile | 11 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/clock.c | 19 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/cpu.c | 32 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/dma.c | 722 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/gpiolib.c | 10 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/dma-plat.h | 70 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/irqs.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/pm-core.h | 98 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/s3c6400.h | 3 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/irq-eint.c | 3 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/irq-pm.c | 111 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/irq.c | 9 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/pm.c | 175 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/s3c6400-clock.c | 106 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/setup-sdhci-gpio.c | 55 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/sleep.S | 144 |
18 files changed, 1572 insertions, 8 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 54375a00a7d..5ebd8b425a5 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -19,6 +19,7 @@ config PLAT_S3C64XX select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX select S3C_GPIO_CFG_S3C64XX + select USB_ARCH_HAS_OHCI help Base platform code for any Samsung S3C64XX device @@ -38,6 +39,10 @@ config CPU_S3C6400_CLOCK Common clock support code for the S3C6400 that is shared by other CPUs in the series, such as the S3C6410. +config S3C64XX_DMA + bool "S3C64XX DMA" + select S3C_DMA + # platform specific device setup config S3C64XX_SETUP_I2C0 @@ -59,4 +64,9 @@ config S3C64XX_SETUP_FB_24BPP help Common setup code for S3C64XX with an 24bpp RGB display helper. +config S3C64XX_SETUP_SDHCI_GPIO + bool + help + Common setup code for S3C64XX SDHCI GPIO configurations + endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 2e6d79bf8f3..2ed5df34f9e 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -24,8 +24,19 @@ obj-y += gpiolib.o obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o +# PM support + +obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += sleep.o +obj-$(CONFIG_PM) += irq-pm.o + +# DMA support + +obj-$(CONFIG_S3C64XX_DMA) += dma.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o +obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
\ No newline at end of file diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index ad1b9682c9c..0bc2fa1dfc4 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -27,6 +27,12 @@ #include <plat/devs.h> #include <plat/clock.h> +struct clk clk_h2 = { + .name = "hclk2", + .id = -1, + .rate = 0, +}; + struct clk clk_27m = { .name = "clk_27m", .id = -1, @@ -152,6 +158,18 @@ static struct clk init_clocks_disable[] = { .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, + }, { + .name = "dma0", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_DMA0, + }, { + .name = "dma1", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_DMA1, }, }; @@ -246,6 +264,7 @@ static struct clk *clks[] __initdata = { &clk_epll, &clk_27m, &clk_48m, + &clk_h2, }; void __init s3c64xx_register_clocks(void) diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index 91f49a3a665..b1fdd83940a 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> +#include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -101,9 +102,24 @@ static struct map_desc s3c_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, }, }; + +struct sysdev_class s3c64xx_sysclass = { + .name = "s3c64xx-core", +}; + +static struct sys_device s3c64xx_sysdev = { + .cls = &s3c64xx_sysclass, +}; + + /* read cpu identification code */ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) @@ -115,5 +131,21 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) iotable_init(mach_desc, size); idcode = __raw_readl(S3C_VA_SYS + 0x118); + if (!idcode) { + /* S3C6400 has the ID register in a different place, + * and needs a write before it can be read. */ + + __raw_writel(0x0, S3C_VA_SYS + 0xA1C); + idcode = __raw_readl(S3C_VA_SYS + 0xA1C); + } + s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); } + +static __init int s3c64xx_sysdev_init(void) +{ + sysdev_class_register(&s3c64xx_sysclass); + return sysdev_register(&s3c64xx_sysdev); +} + +core_initcall(s3c64xx_sysdev_init); diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/plat-s3c64xx/dma.c new file mode 100644 index 00000000000..67aa93dbb69 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dma.c @@ -0,0 +1,722 @@ +/* linux/arch/arm/plat-s3c64xx/dma.c + * + * Copyright 2009 Openmoko, Inc. + * Copyright 2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX DMA core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/dmapool.h> +#include <linux/sysdev.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <mach/dma.h> +#include <mach/map.h> +#include <mach/irqs.h> + +#include <plat/dma-plat.h> +#include <plat/regs-sys.h> + +#include <asm/hardware/pl080.h> + +/* dma channel state information */ + +struct s3c64xx_dmac { + struct sys_device sysdev; + struct clk *clk; + void __iomem *regs; + struct s3c2410_dma_chan *channels; + enum dma_ch chanbase; +}; + +/* pool to provide LLI buffers */ +static struct dma_pool *dma_pool; + +/* Debug configuration and code */ + +static unsigned char debug_show_buffs = 0; + +static void dbg_showchan(struct s3c2410_dma_chan *chan) +{ + pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n", + chan->number, + readl(chan->regs + PL080_CH_SRC_ADDR), + readl(chan->regs + PL080_CH_DST_ADDR), + readl(chan->regs + PL080_CH_LLI), + readl(chan->regs + PL080_CH_CONTROL), + readl(chan->regs + PL080S_CH_CONTROL2), + readl(chan->regs + PL080S_CH_CONFIG)); +} + +static void show_lli(struct pl080s_lli *lli) +{ + pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n", + lli, lli->src_addr, lli->dst_addr, lli->next_lli, + lli->control0, lli->control1); +} + +static void dbg_showbuffs(struct s3c2410_dma_chan *chan) +{ + struct s3c64xx_dma_buff *ptr; + struct s3c64xx_dma_buff *end; + + pr_debug("DMA%d: buffs next %p, curr %p, end %p\n", + chan->number, chan->next, chan->curr, chan->end); + + ptr = chan->next; + end = chan->end; + + if (debug_show_buffs) { + for (; ptr != NULL; ptr = ptr->next) { + pr_debug("DMA%d: %08x ", + chan->number, ptr->lli_dma); + show_lli(ptr->lli); + } + } +} + +/* End of Debug */ + +static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel) +{ + struct s3c2410_dma_chan *chan; + unsigned int start, offs; + + start = 0; + + if (channel >= DMACH_PCM1_TX) + start = 8; + + for (offs = 0; offs < 8; offs++) { + chan = &s3c2410_chans[start + offs]; + if (!chan->in_use) + goto found; + } + + return NULL; + +found: + s3c_dma_chan_map[channel] = chan; + return chan; +} + +int s3c2410_dma_config(unsigned int channel, int xferunit) +{ + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); + + if (chan == NULL) + return -EINVAL; + + switch (xferunit) { + case 1: + chan->hw_width = 0; + break; + case 2: + chan->hw_width = 1; + break; + case 4: + chan->hw_width = 2; + break; + default: + printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(s3c2410_dma_config); + +static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan, + struct pl080s_lli *lli, + dma_addr_t data, int size) +{ + dma_addr_t src, dst; + u32 control0, control1; + + switch (chan->source) { + case S3C2410_DMASRC_HW: + src = chan->dev_addr; + dst = data; + control0 = PL080_CONTROL_SRC_AHB2; + control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT; + control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT; + control0 |= PL080_CONTROL_DST_INCR; + break; + + case S3C2410_DMASRC_MEM: + src = data; + dst = chan->dev_addr; + control0 = PL080_CONTROL_DST_AHB2; + control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT; + control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT; + control0 |= PL080_CONTROL_SRC_INCR; + break; + default: + BUG(); + } + + /* note, we do not currently setup any of the burst controls */ + + control1 = size >> chan->hw_width; /* size in no of xfers */ + control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */ + control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */ + + lli->src_addr = src; + lli->dst_addr = dst; + lli->next_lli = 0; + lli->control0 = control0; + lli->control1 = control1; +} + +static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan, + struct pl080s_lli *lli) +{ + void __iomem *regs = chan->regs; + + pr_debug("%s: LLI %p => regs\n", __func__, lli); + show_lli(lli); + + writel(lli->src_addr, regs + PL080_CH_SRC_ADDR); + writel(lli->dst_addr, regs + PL080_CH_DST_ADDR); + writel(lli->next_lli, regs + PL080_CH_LLI); + writel(lli->control0, regs + PL080_CH_CONTROL); + writel(lli->control1, regs + PL080S_CH_CONTROL2); +} + +static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan) +{ + struct s3c64xx_dmac *dmac = chan->dmac; + u32 config; + u32 bit = chan->bit; + + dbg_showchan(chan); + + pr_debug("%s: clearing interrupts\n", __func__); + + /* clear interrupts */ + writel(bit, dmac->regs + PL080_TC_CLEAR); + writel(bit, dmac->regs + PL080_ERR_CLEAR); + + pr_debug("%s: starting channel\n", __func__); + + config = readl(chan->regs + PL080S_CH_CONFIG); + config |= PL080_CONFIG_ENABLE; + + pr_debug("%s: writing config %08x\n", __func__, config); + writel(config, chan->regs + PL080S_CH_CONFIG); + + return 0; +} + +static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan) +{ + u32 config; + int timeout; + + pr_debug("%s: stopping channel\n", __func__); + + dbg_showchan(chan); + + config = readl(chan->regs + PL080S_CH_CONFIG); + config |= PL080_CONFIG_HALT; + writel(config, chan->regs + PL080S_CH_CONFIG); + + timeout = 1000; + do { + config = readl(chan->regs + PL080S_CH_CONFIG); + pr_debug("%s: %d - config %08x\n", __func__, timeout, config); + if (config & PL080_CONFIG_ACTIVE) + udelay(10); + else + break; + } while (--timeout > 0); + + if (config & PL080_CONFIG_ACTIVE) { + printk(KERN_ERR "%s: channel still active\n", __func__); + return -EFAULT; + } + + config = readl(chan->regs + PL080S_CH_CONFIG); + config &= ~PL080_CONFIG_ENABLE; + writel(config, chan->regs + PL080S_CH_CONFIG); + + return 0; +} + +static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan, + struct s3c64xx_dma_buff *buf, + enum s3c2410_dma_buffresult result) +{ + if (chan->callback_fn != NULL) + (chan->callback_fn)(chan, buf->pw, 0, result); +} + +static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff) +{ + dma_pool_free(dma_pool, buff->lli, buff->lli_dma); + kfree(buff); +} + +static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan) +{ + struct s3c64xx_dma_buff *buff, *next; + u32 config; + + dbg_showchan(chan); + + pr_debug("%s: flushing channel\n", __func__); + + config = readl(chan->regs + PL080S_CH_CONFIG); + config &= ~PL080_CONFIG_ENABLE; + writel(config, chan->regs + PL080S_CH_CONFIG); + + /* dump all the buffers associated with this channel */ + + for (buff = chan->curr; buff != NULL; buff = next) { + next = buff->next; + pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next); + + s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT); + s3c64xx_dma_freebuff(buff); + } + + chan->curr = chan->next = chan->end = NULL; + + return 0; +} + +int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) +{ + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); + + WARN_ON(!chan); + if (!chan) + return -EINVAL; + + switch (op) { + case S3C2410_DMAOP_START: + return s3c64xx_dma_start(chan); + + case S3C2410_DMAOP_STOP: + return s3c64xx_dma_stop(chan); + + case S3C2410_DMAOP_FLUSH: + return s3c64xx_dma_flush(chan); + + /* belive PAUSE/RESUME are no-ops */ + case S3C2410_DMAOP_PAUSE: + case S3C2410_DMAOP_RESUME: + case S3C2410_DMAOP_STARTED: + case S3C2410_DMAOP_TIMEOUT: + return 0; + } + + return -ENOENT; +} +EXPORT_SYMBOL(s3c2410_dma_ctrl); + +/* s3c2410_dma_enque + * + */ + +int s3c2410_dma_enqueue(unsigned int channel, void *id, + dma_addr_t data, int size) +{ + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); + struct s3c64xx_dma_buff *next; + struct s3c64xx_dma_buff *buff; + struct pl080s_lli *lli; + int ret; + + WARN_ON(!chan); + if (!chan) + return -EINVAL; + + buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_KERNEL); + if (!buff) { + printk(KERN_ERR "%s: no memory for buffer\n", __func__); + return -ENOMEM; + } + + lli = dma_pool_alloc(dma_pool, GFP_KERNEL, &buff->lli_dma); + if (!lli) { + printk(KERN_ERR "%s: no memory for lli\n", __func__); + ret = -ENOMEM; + goto err_buff; + } + + pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n", + __func__, buff, data, lli, (u32)buff->lli_dma, size); + + buff->lli = lli; + buff->pw = id; + + s3c64xx_dma_fill_lli(chan, lli, data, size); + + if ((next = chan->next) != NULL) { + struct s3c64xx_dma_buff *end = chan->end; + struct pl080s_lli *endlli = end->lli; + + pr_debug("enquing onto channel\n"); + + end->next = buff; + endlli->next_lli = buff->lli_dma; + + if (chan->flags & S3C2410_DMAF_CIRCULAR) { + struct s3c64xx_dma_buff *curr = chan->curr; + lli->next_lli = curr->lli_dma; + } + + if (next == chan->curr) { + writel(buff->lli_dma, chan->regs + PL080_CH_LLI); + chan->next = buff; + } + + show_lli(endlli); + chan->end = buff; + } else { + pr_debug("enquing onto empty channel\n"); + + chan->curr = buff; + chan->next = buff; + chan->end = buff; + + s3c64xx_lli_to_regs(chan, lli); + } + + show_lli(lli); + + dbg_showchan(chan); + dbg_showbuffs(chan); + return 0; + +err_buff: + kfree(buff); + return ret; +} + +EXPORT_SYMBOL(s3c2410_dma_enqueue); + + +int s3c2410_dma_devconfig(int channel, + enum s3c2410_dmasrc source, + unsigned long devaddr) +{ + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); + u32 peripheral; + u32 config = 0; + + pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n", + __func__, channel, source, devaddr, chan); + + WARN_ON(!chan); + if (!chan) + return -EINVAL; + + peripheral = (chan->peripheral & 0xf); + chan->source = source; + chan->dev_addr = devaddr; + + pr_debug("%s: peripheral %d\n", __func__, peripheral); + + switch (source) { + case S3C2410_DMASRC_HW: + config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT; + config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT; + break; + case S3C2410_DMASRC_MEM: + config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT; + config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT; + break; + default: + printk(KERN_ERR "%s: bad source\n", __func__); + return -EINVAL; + } + + /* allow TC and ERR interrupts */ + config |= PL080_CONFIG_TC_IRQ_MASK; + config |= PL080_CONFIG_ERR_IRQ_MASK; + + pr_debug("%s: config %08x\n", __func__, config); + + writel(config, chan->regs + PL080S_CH_CONFIG); + + return 0; +} +EXPORT_SYMBOL(s3c2410_dma_devconfig); + + +int s3c2410_dma_getposition(unsigned int channel, + dma_addr_t *src, dma_addr_t *dst) +{ + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); + + WARN_ON(!chan); + if (!chan) + return -EINVAL; + + if (src != NULL) + *src = readl(chan->regs + PL080_CH_SRC_ADDR); + + if (dst != NULL) + *dst = readl(chan->regs + PL080_CH_DST_ADDR); + + return 0; +} +EXPORT_SYMBOL(s3c2410_dma_getposition); + +/* s3c2410_request_dma + * + * get control of an dma channel +*/ + +int s3c2410_dma_request(unsigned int channel, + struct s3c2410_dma_client *client, + void *dev) +{ + struct s3c2410_dma_chan *chan; + unsigned long flags; + + pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", + channel, client->name, dev); + + local_irq_save(flags); + + chan = s3c64xx_dma_map_channel(channel); + if (chan == NULL) { + local_irq_restore(flags); + return -EBUSY; + } + + dbg_showchan(chan); + + chan->client = client; + chan->in_use = 1; + chan->peripheral = channel; + + local_irq_restore(flags); + + /* need to setup */ + + pr_debug("%s: channel initialised, %p\n", __func__, chan); + + return chan->number | DMACH_LOW_LEVEL; +} + +EXPORT_SYMBOL(s3c2410_dma_request); + +/* s3c2410_dma_free + * + * release the given channel back to the system, will stop and flush + * any outstanding transfers, and ensure the channel is ready for the + * next claimant. + * + * Note, although a warning is currently printed if the freeing client + * info is not the same as the registrant's client info, the free is still + * allowed to go through. +*/ + +int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client) +{ + struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); + unsigned long flags; + + if (chan == NULL) + return -EINVAL; + + local_irq_save(flags); + + if (chan->client != client) { + printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", + channel, chan->client, client); + } + + /* sort out stopping and freeing the channel */ + + + chan->client = NULL; + chan->in_use = 0; + + if (!(channel & DMACH_LOW_LEVEL)) + s3c_dma_chan_map[channel] = NULL; + + local_irq_restore(flags); + + return 0; +} + +EXPORT_SYMBOL(s3c2410_dma_free); + + +static void s3c64xx_dma_tcirq(struct s3c64xx_dmac *dmac, int offs) +{ + struct s3c2410_dma_chan *chan = dmac->channels + offs; + + /* note, we currently do not bother to work out which buffer + * or buffers have been completed since the last tc-irq. */ + + if (chan->callback_fn) + (chan->callback_fn)(chan, chan->curr->pw, 0, S3C2410_RES_OK); +} + +static void s3c64xx_dma_errirq(struct s3c64xx_dmac *dmac, int offs) +{ + printk(KERN_DEBUG "%s: offs %d\n", __func__, offs); +} + +static irqreturn_t s3c64xx_dma_irq(int irq, void *pw) +{ + struct s3c64xx_dmac *dmac = pw; + u32 tcstat, errstat; + u32 bit; + int offs; + + tcstat = readl(dmac->regs + PL080_TC_STATUS); + errstat = readl(dmac->regs + PL080_ERR_STATUS); + + for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) { + if (tcstat & bit) { + writel(bit, dmac->regs + PL080_TC_CLEAR); + s3c64xx_dma_tcirq(dmac, offs); + } + + if (errstat & bit) { + s3c64xx_dma_errirq(dmac, offs); + writel(bit, dmac->regs + PL080_ERR_CLEAR); + } + } + + return IRQ_HANDLED; +} + +static struct sysdev_class dma_sysclass = { + .name = "s3c64xx-dma", +}; + +static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, + int irq, unsigned int base) +{ + struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno]; + struct s3c64xx_dmac *dmac; + char clkname[16]; + void __iomem *regs; + void __iomem *regptr; + int err, ch; + + dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL); + if (!dmac) { + printk(KERN_ERR "%s: failed to alloc mem\n", __func__); + return -ENOMEM; + } + + dmac->sysdev.id = chno / 8; + dmac->sysdev.cls = &dma_sysclass; + + err = sysdev_register(&dmac->sysdev); + if (err) { + printk(KERN_ERR "%s: failed to register sysdevice\n", __func__); + goto err_alloc; + } + + regs = ioremap(base, 0x200); + if (!regs) { + printk(KERN_ERR "%s: failed to ioremap()\n", __func__); + err = -ENXIO; + goto err_dev; + } + + snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id); + + dmac->clk = clk_get(NULL, clkname); + if (IS_ERR(dmac->clk)) { + printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname); + err = PTR_ERR(dmac->clk); + goto err_map; + } + + clk_enable(dmac->clk); + + dmac->regs = regs; + dmac->chanbase = chbase; + dmac->channels = chptr; + + err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac); + if (err < 0) { + printk(KERN_ERR "%s: failed to get irq\n", __func__); + goto err_clk; + } + + regptr = regs + PL080_Cx_BASE(0); + + for (ch = 0; ch < 8; ch++, chno++, chptr++) { + printk(KERN_INFO "%s: registering DMA %d (%p)\n", + __func__, chno, regptr); + + chptr->bit = 1 << ch; + chptr->number = chno; + chptr->dmac = dmac; + chptr->regs = regptr; + regptr += PL008_Cx_STRIDE; + } + + /* for the moment, permanently enable the controller */ + writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG); + + printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs); + + return 0; + +err_clk: + clk_disable(dmac->clk); + clk_put(dmac->clk); +err_map: + iounmap(regs); +err_dev: + sysdev_unregister(&dmac->sysdev); +err_alloc: + kfree(dmac); + return err; +} + +static int __init s3c64xx_dma_init(void) +{ + int ret; + + printk(KERN_INFO "%s: Registering DMA channels\n", __func__); + + dma_pool = dma_pool_create("DMA-LLI", NULL, 32, 16, 0); + if (!dma_pool) { + printk(KERN_ERR "%s: failed to create pool\n", __func__); + return -ENOMEM; + } + + ret = sysdev_class_register(&dma_sysclass); + if (ret) { + printk(KERN_ERR "%s: failed to create sysclass\n", __func__); + return -ENOMEM; + } + + /* Set all DMA configuration to be DMA, not SDMA */ + writel(0xffffff, S3C_SYSREG(0x110)); + + /* Register standard DMA controlers */ + s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); + s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000); + + return 0; +} + +arch_initcall(s3c64xx_dma_init); diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 78ee52cffc9..da7b60ee5e6 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -385,12 +385,19 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) { chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); } static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) { chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); +} + +static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) +{ + chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); } static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, @@ -412,7 +419,8 @@ static __init int s3c64xx_gpiolib_init(void) s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), s3c64xx_gpiolib_add_4bit2); - s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); + s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), + s3c64xx_gpiolib_add_2bit); return 0; } diff --git a/arch/arm/plat-s3c64xx/include/plat/dma-plat.h b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h new file mode 100644 index 00000000000..0c30dd98672 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h @@ -0,0 +1,70 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h + * + * Copyright 2009 Openmoko, Inc. + * Copyright 2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX DMA core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ + +struct s3c64xx_dma_buff; + +/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor + * @next: Pointer to next buffer in queue or ring. + * @pw: Client provided identifier + * @lli: Pointer to hardware descriptor this buffer is associated with. + * @lli_dma: Hardare address of the descriptor. + */ +struct s3c64xx_dma_buff { + struct s3c64xx_dma_buff *next; + + void *pw; + struct pl080_lli *lli; + dma_addr_t lli_dma; +}; + +struct s3c64xx_dmac; + +struct s3c2410_dma_chan { + unsigned char number; /* number of this dma channel */ + unsigned char in_use; /* channel allocated */ + unsigned char bit; /* bit for enable/disable/etc */ + unsigned char hw_width; + unsigned char peripheral; + + unsigned int flags; + enum s3c2410_dmasrc source; + + + dma_addr_t dev_addr; + + struct s3c2410_dma_client *client; + struct s3c64xx_dmac *dmac; /* pointer to controller */ + + void __iomem *regs; + + /* cdriver callbacks */ + s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ + s3c2410_dma_opfn_t op_fn; /* channel op callback */ + + /* buffer list and information */ + struct s3c64xx_dma_buff *curr; /* current dma buffer */ + struct s3c64xx_dma_buff *next; /* next buffer to load */ + struct s3c64xx_dma_buff *end; /* end of queue */ + + /* note, when channel is running in circular mode, curr is the + * first buffer enqueued, end is the last and curr is where the + * last buffer-done event is set-at. The buffers are not freed + * and the last buffer hardware descriptor points back to the + * first. + */ +}; + +#include <plat/dma-core.h> diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h index f865bf4d709..743a70094d0 100644 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -157,6 +157,7 @@ #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) #define IRQ_EINT(x) S3C_EINT(x) +#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) * that they are sourced from the GPIO pins but with a different scheme for diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/plat-s3c64xx/include/plat/pm-core.h new file mode 100644 index 00000000000..d347de3ba0d --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h @@ -0,0 +1,98 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <plat/regs-gpio.h> + +static inline void s3c_pm_debug_init_uart(void) +{ + u32 tmp = __raw_readl(S3C_PCLK_GATE); + + /* As a note, since the S3C64XX UARTs generally have multiple + * clock sources, we simply enable PCLK at the moment and hope + * that the resume settings for the UART are suitable for the + * use with PCLK. + */ + + tmp |= S3C_CLKCON_PCLK_UART0; + tmp |= S3C_CLKCON_PCLK_UART1; + tmp |= S3C_CLKCON_PCLK_UART2; + tmp |= S3C_CLKCON_PCLK_UART3; + + __raw_writel(tmp, S3C_PCLK_GATE); + udelay(10); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + /* VIC should have already been taken care of */ + + /* clear any pending EINT0 interrupts */ + __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ +} + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ +} + +/* make these defines, we currently do not have any need to change + * the IRQ wake controls depending on the CPU we are running on */ + +#define s3c_irqwake_eintallow ((1 << 28) - 1) +#define s3c_irqwake_intallow (0) + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ + u32 ucon = __raw_readl(regs + S3C2410_UCON); + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; + u32 new_ucon; + u32 delta; + + /* S3C64XX UART blocks only support level interrupts, so ensure that + * when we restore unused UART blocks we force the level interrupt + * settigs. */ + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; + + /* We have a constraint on changing the clock type of the UART + * between UCLKx and PCLK, so ensure that when we restore UCON + * that the CLK field is correctly modified if the bootloader + * has changed anything. + */ + if (ucon_clk != save_clk) { + new_ucon = save->ucon; + delta = ucon_clk ^ save_clk; + + /* change from UCLKx => wrong PCLK, + * either UCLK can be tested for by a bit-test + * with UCLK0 */ + if (ucon_clk & S3C6400_UCON_UCLK0 && + !(save_clk & S3C6400_UCON_UCLK0) && + delta & S3C6400_UCON_PCLK2) { + new_ucon &= ~S3C6400_UCON_UCLK0; + } else if (delta == S3C6400_UCON_PCLK2) { + /* as an precaution, don't change from + * PCLK2 => PCLK or vice-versa */ + new_ucon ^= S3C6400_UCON_PCLK2; + } + + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", + ucon, new_ucon, save->ucon); + save->ucon = new_ucon; + } +} diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index b1082c16324..52836d41e33 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -32,6 +32,7 @@ #define S3C_HCLK_GATE S3C_CLKREG(0x30) #define S3C_PCLK_GATE S3C_CLKREG(0x34) #define S3C_SCLK_GATE S3C_CLKREG(0x38) +#define S3C_MEM0_GATE S3C_CLKREG(0x3C) /* CLKDIV0 */ #define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h index 571eaa2e54f..11f2e1e119b 100644 --- a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h @@ -15,12 +15,13 @@ /* Common init code for S3C6400 related SoCs */ extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c6400_register_clocks(void); +extern void s3c6400_register_clocks(unsigned armclk_divlimit); extern void s3c6400_setup_clocks(void); #ifdef CONFIG_CPU_S3C6400 extern int s3c6400_init(void); +extern void s3c6400_init_irq(void); extern void s3c6400_map_io(void); extern void s3c6400_init_clocks(int xtal); diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index 47e5155bb13..f81b7b818ba 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/interrupt.h> +#include <linux/sysdev.h> #include <linux/gpio.h> #include <linux/irq.h> #include <linux/io.h> @@ -26,6 +27,7 @@ #include <mach/map.h> #include <plat/cpu.h> +#include <plat/pm.h> #define eint_offset(irq) ((irq) - IRQ_EINT(0)) #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) @@ -134,6 +136,7 @@ static struct irq_chip s3c_irq_eint = { .mask_ack = s3c_irq_eint_maskack, .ack = s3c_irq_eint_ack, .set_type = s3c_irq_eint_set_type, + .set_wake = s3c_irqext_wake, }; /* s3c_irq_demux_eint diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c new file mode 100644 index 00000000000..ca523b5d4c1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/irq-pm.c @@ -0,0 +1,111 @@ +/* arch/arm/plat-s3c64xx/irq-pm.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Interrupt handling Power Management + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <linux/serial_core.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/map.h> + +#include <plat/regs-serial.h> +#include <plat/regs-timer.h> +#include <plat/regs-gpio.h> +#include <plat/cpu.h> +#include <plat/pm.h> + +/* We handled all the IRQ types in this code, to save having to make several + * small files to handle each different type separately. Having the EINT_GRP + * code here shouldn't be as much bloat as the IRQ table space needed when + * they are enabled. The added benefit is we ensure that these registers are + * in the same state as we suspended. + */ + +static struct sleep_save irq_save[] = { + SAVE_ITEM(S3C64XX_PRIORITY), + SAVE_ITEM(S3C64XX_EINT0CON0), + SAVE_ITEM(S3C64XX_EINT0CON1), + SAVE_ITEM(S3C64XX_EINT0FLTCON0), + SAVE_ITEM(S3C64XX_EINT0FLTCON1), + SAVE_ITEM(S3C64XX_EINT0FLTCON2), + SAVE_ITEM(S3C64XX_EINT0FLTCON3), + SAVE_ITEM(S3C64XX_EINT0MASK), + SAVE_ITEM(S3C64XX_TINT_CSTAT), +}; + +static struct irq_grp_save { + u32 fltcon; + u32 con; + u32 mask; +} eint_grp_save[5]; + +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; + +static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: suspending IRQs\n", __func__); + + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); + grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); + grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); + } + + return 0; +} + +static int s3c64xx_irq_pm_resume(struct sys_device *dev) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: resuming IRQs\n", __func__); + + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4)); + __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); + __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); + } + + S3C_PMDBG("%s: IRQ configuration restored\n", __func__); + return 0; +} + +static struct sysdev_driver s3c64xx_irq_driver = { + .suspend = s3c64xx_irq_pm_suspend, + .resume = s3c64xx_irq_pm_resume, +}; + +static int __init s3c64xx_irq_pm_init(void) +{ + return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver); +} + +arch_initcall(s3c64xx_irq_pm_init); + diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index f22edf7c2d2..8dc5b6da978 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c @@ -14,12 +14,14 @@ #include <linux/kernel.h> #include <linux/interrupt.h> +#include <linux/serial_core.h> #include <linux/irq.h> #include <linux/io.h> #include <asm/hardware/vic.h> #include <mach/map.h> +#include <plat/regs-serial.h> #include <plat/regs-timer.h> #include <plat/cpu.h> @@ -135,9 +137,6 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq) } /* UART interrupt registers, not worth adding to seperate include header */ -#define S3C64XX_UINTP 0x30 -#define S3C64XX_UINTSP 0x34 -#define S3C64XX_UINTM 0x38 static void s3c_irq_uart_mask(unsigned int irq) { @@ -233,8 +232,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); - vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); + vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0); + vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0); /* add the timer sub-irqs */ diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c new file mode 100644 index 00000000000..07a6516a4f3 --- /dev/null +++ b/arch/arm/plat-s3c64xx/pm.c @@ -0,0 +1,175 @@ +/* linux/arch/arm/plat-s3c64xx/pm.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX CPU PM support. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/suspend.h> +#include <linux/serial_core.h> +#include <linux/io.h> + +#include <mach/map.h> + +#include <plat/pm.h> +#include <plat/regs-sys.h> +#include <plat/regs-gpio.h> +#include <plat/regs-clock.h> +#include <plat/regs-syscon-power.h> +#include <plat/regs-gpio-memport.h> + +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK +#include <plat/gpio-bank-n.h> + +void s3c_pm_debug_smdkled(u32 set, u32 clear) +{ + unsigned long flags; + u32 reg; + + local_irq_save(flags); + reg = __raw_readl(S3C64XX_GPNCON); + reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)); + reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15); + __raw_writel(reg, S3C64XX_GPNCON); + + reg = __raw_readl(S3C64XX_GPNDAT); + reg &= ~(clear << 12); + reg |= set << 12; + __raw_writel(reg, S3C64XX_GPNDAT); + + local_irq_restore(flags); +} +#endif + +static struct sleep_save core_save[] = { + SAVE_ITEM(S3C_APLL_LOCK), + SAVE_ITEM(S3C_MPLL_LOCK), + SAVE_ITEM(S3C_EPLL_LOCK), + SAVE_ITEM(S3C_CLK_SRC), + SAVE_ITEM(S3C_CLK_DIV0), + SAVE_ITEM(S3C_CLK_DIV1), + SAVE_ITEM(S3C_CLK_DIV2), + SAVE_ITEM(S3C_CLK_OUT), + SAVE_ITEM(S3C_HCLK_GATE), + SAVE_ITEM(S3C_PCLK_GATE), + SAVE_ITEM(S3C_SCLK_GATE), + SAVE_ITEM(S3C_MEM0_GATE), + + SAVE_ITEM(S3C_EPLL_CON1), + SAVE_ITEM(S3C_EPLL_CON0), + + SAVE_ITEM(S3C64XX_MEM0DRVCON), + SAVE_ITEM(S3C64XX_MEM1DRVCON), + +#ifndef CONFIG_CPU_FREQ + SAVE_ITEM(S3C_APLL_CON), + SAVE_ITEM(S3C_MPLL_CON), +#endif +}; + +static struct sleep_save misc_save[] = { + SAVE_ITEM(S3C64XX_AHB_CON0), + SAVE_ITEM(S3C64XX_AHB_CON1), + SAVE_ITEM(S3C64XX_AHB_CON2), + + SAVE_ITEM(S3C64XX_SPCON), + + SAVE_ITEM(S3C64XX_MEM0CONSTOP), + SAVE_ITEM(S3C64XX_MEM1CONSTOP), + SAVE_ITEM(S3C64XX_MEM0CONSLP0), + SAVE_ITEM(S3C64XX_MEM0CONSLP1), + SAVE_ITEM(S3C64XX_MEM1CONSLP), +}; + +void s3c_pm_configure_extint(void) +{ + __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); +} + +void s3c_pm_restore_core(void) +{ + __raw_writel(0, S3C64XX_EINT_MASK); + + s3c_pm_debug_smdkled(1 << 2, 0); + + s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); + s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); +} + +void s3c_pm_save_core(void) +{ + s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); + s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); +} + +/* since both s3c6400 and s3c6410 share the same sleep pm calls, we + * put the per-cpu code in here until any new cpu comes along and changes + * this. + */ + +#include <plat/regs-gpio.h> + +static void s3c64xx_cpu_suspend(void) +{ + unsigned long tmp; + + /* set our standby method to sleep */ + + tmp = __raw_readl(S3C64XX_PWR_CFG); + tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; + tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; + __raw_writel(tmp, S3C64XX_PWR_CFG); + + /* clear any old wakeup */ + + __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), + S3C64XX_WAKEUP_STAT); + + /* set the LED state to 0110 over sleep */ + s3c_pm_debug_smdkled(3 << 1, 0xf); + + /* issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case */ + + tmp = 0; + + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 5\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); + + /* we should never get past here */ + + panic("sleep resumed to originator?"); +} + +static void s3c64xx_pm_prepare(void) +{ + /* store address of resume. */ + __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); + + /* ensure previous wakeup state is cleared before sleeping */ + __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); +} + +static int s3c64xx_pm_init(void) +{ + pm_cpu_prep = s3c64xx_pm_prepare; + pm_cpu_sleep = s3c64xx_cpu_suspend; + pm_uart_udivslot = 1; + return 0; +} + +arch_initcall(s3c64xx_pm_init); diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 05b17528041..1debc1f9f98 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -133,6 +133,65 @@ static struct clksrc_clk clk_mout_mpll = { .sources = &clk_src_mpll, }; +static unsigned int armclk_mask; + +static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv; + + /* divisor mask starts at bit0, so no need to shift */ + clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask; + + return rate / (clkdiv + 1); +} + +static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + + if (parent < rate) + return rate; + + div = (parent / rate) - 1; + if (div > armclk_mask) + div = armclk_mask; + + return parent / (div + 1); +} + +static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + u32 val; + + if (rate < parent / (armclk_mask + 1)) + return -EINVAL; + + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; + + val = __raw_readl(S3C_CLK_DIV0); + val &= armclk_mask; + val |= (div - 1); + __raw_writel(val, S3C_CLK_DIV0); + + return 0; + +} + +static struct clk clk_arm = { + .name = "armclk", + .id = -1, + .parent = &clk_mout_apll.clk, + .get_rate = s3c64xx_clk_arm_get_rate, + .set_rate = s3c64xx_clk_arm_set_rate, + .round_rate = s3c64xx_clk_arm_round_rate, +}; + static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) { unsigned long rate = clk_get_rate(clk->parent); @@ -520,6 +579,33 @@ static struct clksrc_clk clk_irda = { .reg_divider = S3C_CLK_DIV2, }; +static struct clk *clkset_camif_list[] = { + &clk_h2, +}; + +static struct clk_sources clkset_camif = { + .sources = clkset_camif_list, + .nr_sources = ARRAY_SIZE(clkset_camif_list), +}; + +static struct clksrc_clk clk_camif = { + .clk = { + .name = "camera", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_CAM, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = 0, + .mask = 0, + .sources = &clkset_camif, + .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, + .reg_divider = S3C_CLK_DIV0, +}; + /* Clock initialisation code */ static struct clksrc_clk *init_parents[] = { @@ -536,6 +622,7 @@ static struct clksrc_clk *init_parents[] = { &clk_audio0, &clk_audio1, &clk_irda, + &clk_camif, }; static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) @@ -608,6 +695,7 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) clk_fout_epll.rate = epll; clk_fout_apll.rate = apll; + clk_h2.rate = hclk2; clk_h.rate = hclk; clk_p.rate = pclk; clk_f.rate = fclk; @@ -635,14 +723,30 @@ static struct clk *clks[] __initdata = { &clk_audio0.clk, &clk_audio1.clk, &clk_irda.clk, + &clk_camif.clk, + &clk_arm, }; -void __init s3c6400_register_clocks(void) +/** + * s3c6400_register_clocks - register clocks for s3c6400 and above + * @armclk_divlimit: Divisor mask for ARMCLK + * + * Register the clocks for the S3C6400 and above SoC range, such + * as ARMCLK and the clocks which have divider chains attached. + * + * This call does not setup the clocks, which is left to the + * s3c6400_setup_clocks() call which may be needed by the cpufreq + * or resume code to re-set the clocks if the bootloader has changed + * them. + */ +void __init s3c6400_register_clocks(unsigned armclk_divlimit) { struct clk *clkp; int ret; int ptr; + armclk_mask = armclk_divlimit; + for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { clkp = clks[ptr]; ret = s3c24xx_register_clock(clkp); diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c new file mode 100644 index 00000000000..5417123b0ac --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c @@ -0,0 +1,55 @@ +/* linux/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> + +void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPG(2 + width); + + /* Set all the necessary GPG pins to special-function 0 */ + for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); +} + +void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPH(2 + width); + + /* Set all the necessary GPG pins to special-function 0 */ + for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); +} diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S new file mode 100644 index 00000000000..8e71fe90a37 --- /dev/null +++ b/arch/arm/plat-s3c64xx/sleep.S @@ -0,0 +1,144 @@ +/* linux/0arch/arm/plat-s3c64xx/sleep.S + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX CPU sleep code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/map.h> + +#undef S3C64XX_VA_GPIO +#define S3C64XX_VA_GPIO (0x0) + +#include <plat/regs-gpio.h> +#include <plat/gpio-bank-n.h> + +#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) + + .text + + /* s3c_cpu_save + * + * Save enough processor state to allow the restart of the pm.c + * code after resume. + * + * entry: + * r0 = pointer to the save block + */ + +ENTRY(s3c_cpu_save) + stmfd sp!, { r4 - r12, lr } + + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls + + stmia r0, { r4 - r13 } @ Save CP registers and SP + + @@ save our state to ram + bl s3c_pm_cb_flushcache + + @@ call final suspend code + ldr r0, =pm_cpu_sleep + ldr pc, [r0] + + @@ return to the caller, after the MMU is turned on. + @@ restore the last bits of the stack and return. +resume_with_mmu: + ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save + + .data + + /* the next bit is code, but it requires easy access to the + * s3c_sleep_save_phys data before the MMU is switched on, so + * we store the code that needs this variable in the .data where + * the value can be written to (the .text segment is RO). + */ + + .global s3c_sleep_save_phys +s3c_sleep_save_phys: + .word 0 + + /* Sleep magic, the word before the resume entry point so that the + * bootloader can check for a resumeable image. */ + + .word 0x2bedf00d + + /* s3c_cpu_reusme + * + * This is the entry point, stored by whatever method the bootloader + * requires to get the kernel runnign again. This code expects to be + * entered with no caches live and the MMU disabled. It will then + * restore the MMU and other basic CP registers saved and restart + * the kernel C code to finish the resume code. + */ + +ENTRY(s3c_cpu_resume) + msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE + ldr r2, =LL_UART /* for debug */ + +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK + /* Initialise the GPIO state if we are debugging via the SMDK LEDs, + * as the uboot version supplied resets these to inputs during the + * resume checks. + */ + + ldr r3, =S3C64XX_PA_GPIO + ldr r0, [ r3, #S3C64XX_GPNCON ] + bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) + orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) + str r0, [ r3, #S3C64XX_GPNCON ] + + ldr r0, [ r3, #S3C64XX_GPNDAT ] + bic r0, r0, #0xf << 12 @ GPN12..15 + orr r0, r0, #1 << 15 @ GPN15 + str r0, [ r3, #S3C64XX_GPNDAT ] +#endif + + /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches + * are thoroughly cleaned just in case the bootloader didn't do it + * for us. */ + mov r0, #0 + mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs + @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches + + ldr r0, s3c_sleep_save_phys + ldmia r0, { r4 - r13 } + + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + + mov r0, #0 @ restore copro access controls + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls + mcr p15, 0, r0, c7, c5, 4 + + ldr r2, =resume_with_mmu + mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ + nop + mov pc, r2 /* jump back */ + + .end |