diff options
Diffstat (limited to 'arch/arm')
576 files changed, 29424 insertions, 11550 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e39caa8b0c9..16bc8eb4901 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -43,10 +43,6 @@ config SYS_SUPPORTS_APM_EMULATION config GENERIC_GPIO bool -config GENERIC_TIME - bool - default y - config ARCH_USES_GETTIMEOFFSET bool default n @@ -562,6 +558,18 @@ config ARCH_NUC93X Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a low-power and high performance MPEG-4/JPEG multimedia controller chip. +config ARCH_TEGRA + bool "NVIDIA Tegra" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select GENERIC_GPIO + select HAVE_CLK + select COMMON_CLKDEV + select ARCH_HAS_BARRIERS if CACHE_L2X0 + help + This enables support for NVIDIA Tegra based systems (Tegra APX, + Tegra 6xx and Tegra 2 series). + config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T @@ -636,6 +644,7 @@ config ARCH_S3C2410 select ARCH_HAS_CPUFREQ select HAVE_CLK select ARCH_USES_GETTIMEOFFSET + select HAVE_S3C2410_I2C help Samsung S3C2410X CPU based systems, such as the Simtec Electronics BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or @@ -665,6 +674,8 @@ config ARCH_S3C64XX select S3C_DEV_NAND select USB_ARCH_HAS_OHCI select SAMSUNG_GPIOLIB_4BIT + select HAVE_S3C2410_I2C + select HAVE_S3C2410_WATCHDOG help Samsung S3C64XX series based systems @@ -673,7 +684,10 @@ config ARCH_S5P6440 select CPU_V6 select GENERIC_GPIO select HAVE_CLK + select HAVE_S3C2410_WATCHDOG select ARCH_USES_GETTIMEOFFSET + select HAVE_S3C2410_I2C + select HAVE_S3C_RTC help Samsung S5P6440 CPU based systems @@ -683,6 +697,7 @@ config ARCH_S5P6442 select GENERIC_GPIO select HAVE_CLK select ARCH_USES_GETTIMEOFFSET + select HAVE_S3C2410_WATCHDOG help Samsung S5P6442 CPU based systems @@ -693,6 +708,9 @@ config ARCH_S5PC100 select CPU_V7 select ARM_L1_CACHE_SHIFT_6 select ARCH_USES_GETTIMEOFFSET + select HAVE_S3C2410_I2C + select HAVE_S3C_RTC + select HAVE_S3C2410_WATCHDOG help Samsung S5PC100 series based systems @@ -703,9 +721,21 @@ config ARCH_S5PV210 select HAVE_CLK select ARM_L1_CACHE_SHIFT_6 select ARCH_USES_GETTIMEOFFSET + select HAVE_S3C2410_I2C + select HAVE_S3C_RTC + select HAVE_S3C2410_WATCHDOG help Samsung S5PV210/S5PC110 series based systems +config ARCH_S5PV310 + bool "Samsung S5PV310/S5PC210" + select CPU_V7 + select GENERIC_GPIO + select HAVE_CLK + select GENERIC_CLOCKEVENTS + help + Samsung S5PV310 series based systems + config ARCH_SHARK bool "Shark" select CPU_SA110 @@ -907,10 +937,14 @@ source "arch/arm/mach-s5pc100/Kconfig" source "arch/arm/mach-s5pv210/Kconfig" +source "arch/arm/mach-s5pv310/Kconfig" + source "arch/arm/mach-shmobile/Kconfig" source "arch/arm/plat-stmp3xxx/Kconfig" +source "arch/arm/mach-tegra/Kconfig" + source "arch/arm/mach-u300/Kconfig" source "arch/arm/mach-ux500/Kconfig" @@ -1030,6 +1064,18 @@ config PL310_ERRATA_588369 is not correctly implemented in PL310 as clean lines are not invalidated as a result of these operations. Note that this errata uses Texas Instrument's secure monitor api. + +config ARM_ERRATA_720789 + bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 720789 Cortex-A9 (prior to + r2p0) erratum. A faulty ASID can be sent to the other CPUs for the + broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. + As a consequence of this erratum, some TLB entries which should be + invalidated are not, resulting in an incoherency in the system page + tables. The workaround changes the TLB flushing routines to invalidate + entries regardless of the ASID. endmenu source "arch/arm/common/Kconfig" @@ -1098,10 +1144,11 @@ config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4) + ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4) depends on GENERIC_CLOCKEVENTS select USE_GENERIC_SMP_HELPERS - select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4) + select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\ + ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -1171,9 +1218,10 @@ config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ - ARCH_U8500 || ARCH_VEXPRESS_CA9X4) + ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4) default y - select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500) + select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 || \ + ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system @@ -1184,7 +1232,8 @@ source kernel/Kconfig.preempt config HZ int - default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210 + default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \ + ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE @@ -1552,6 +1601,7 @@ config ZRELADDR ARCH_ORION5X ||\ ARCH_SPEAR3XX ||\ ARCH_SPEAR6XX ||\ + ARCH_TEGRA ||\ ARCH_U8500 ||\ ARCH_VERSATILE ||\ ARCH_W90X900 @@ -1573,7 +1623,8 @@ config ZRELADDR default 0x40008000 if ARCH_STMP378X ||\ ARCH_STMP37XX ||\ ARCH_SH7372 ||\ - ARCH_SH7377 + ARCH_SH7377 ||\ + ARCH_S5PV310 default 0x50008000 if ARCH_S3C64XX ||\ ARCH_SH7367 default 0x60008000 if ARCH_VEXPRESS diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 63d998e8c67..59c1ce858fc 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -21,6 +21,9 @@ GZFLAGS :=-9 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: KBUILD_CFLAGS +=$(call cc-option,-marm,) +# Never generate .eh_frame +KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + # Do not use arch/arm/defconfig - it's always outdated. # Select a platform tht is kept up-to-date KBUILD_DEFCONFIG := versatile_defconfig @@ -174,11 +177,13 @@ machine-$(CONFIG_ARCH_S5P6440) := s5p6440 machine-$(CONFIG_ARCH_S5P6442) := s5p6442 machine-$(CONFIG_ARCH_S5PC100) := s5pc100 machine-$(CONFIG_ARCH_S5PV210) := s5pv210 +machine-$(CONFIG_ARCH_S5PV310) := s5pv310 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_STMP378X) := stmp378x machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx +machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U8500) := ux500 machine-$(CONFIG_ARCH_VERSATILE) := versatile diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 7636c9b3f9a..68775e33476 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -33,7 +33,7 @@ ifeq ($(CONFIG_CPU_XSCALE),y) OBJS += head-xscale.o endif -ifeq ($(CONFIG_PXA_SHARPSL),y) +ifeq ($(CONFIG_PXA_SHARPSL_DETECT_MACH_ID),y) OBJS += head-sharpsl.o endif diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index abf4d65acf6..6af9907c3b5 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -170,9 +170,8 @@ not_angel: .text adr r0, LC0 - ARM( ldmia r0, {r1, r2, r3, r5, r6, r11, ip, sp}) - THUMB( ldmia r0, {r1, r2, r3, r5, r6, r11, ip} ) - THUMB( ldr sp, [r0, #32] ) + ldmia r0, {r1, r2, r3, r5, r6, r11, ip} + ldr sp, [r0, #28] #ifdef CONFIG_AUTO_ZRELADDR @ determine final kernel image address and r4, pc, #0xf8000000 diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index 7974baacafc..6c091356245 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -263,14 +263,6 @@ static int it8152_pci_platform_notify_remove(struct device *dev) return 0; } -int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) -{ - dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", - __func__, dma_addr, size); - return (dev->bus == &pci_bus_type) && - ((dma_addr + size - PHYS_OFFSET) >= SZ_64M); -} - int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) { it8152_io.start = IT8152_IO_BASE + 0x12000; diff --git a/arch/arm/configs/am3517_evm_defconfig b/arch/arm/configs/am3517_evm_defconfig deleted file mode 100644 index ad2bc503f2b..00000000000 --- a/arch/arm/configs/am3517_evm_defconfig +++ /dev/null @@ -1,127 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP3517EVM=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_CAN=y -CONFIG_CAN_RAW=y -CONFIG_CAN_BCM=y -CONFIG_CAN_VCAN=y -CONFIG_CAN_DEV=y -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_TI_HECC=y -CONFIG_CAN_DEBUG_DEVICES=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_TI_DAVINCI_EMAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=4 -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 -CONFIG_FB_OMAP2=y -CONFIG_PANEL_GENERIC=y -CONFIG_PANEL_SHARP_LQ043T1DG01=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/cm_t35_defconfig b/arch/arm/configs/cm_t35_defconfig deleted file mode 100644 index 8bb06334ce9..00000000000 --- a/arch/arm/configs/cm_t35_defconfig +++ /dev/null @@ -1,157 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_CM_T35=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_LIB80211=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_FW_LOADER=m -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_TWL4030=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_TEST=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/devkit8000_defconfig b/arch/arm/configs/devkit8000_defconfig deleted file mode 100644 index 786cbe49528..00000000000 --- a/arch/arm/configs/devkit8000_defconfig +++ /dev/null @@ -1,184 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_DEVKIT8000=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS2,115200n8 root=/dev/nfs nfsroot=192.168.1.1:home/nfsroot/current,home/nfsroot/current ip=dhcp rw noinitrd root delay=3" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_IRDA=y -CONFIG_BT=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=40960 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_MATRIX=y -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_SERIO_RAW=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_RAW_DRIVER=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_FB=y -CONFIG_FB_FOREIGN_ENDIAN=y -CONFIG_FB_OMAP_BOOTLOADER_INIT=y -CONFIG_OMAP2_DSS=y -CONFIG_FB_OMAP2=y -CONFIG_PANEL_GENERIC=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_STORAGE=m -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=m -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SPI=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_UBIFS_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_T10DIF=m -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/igep0020_defconfig b/arch/arm/configs/igep0020_defconfig deleted file mode 100644 index fcda057d584..00000000000 --- a/arch/arm/configs/igep0020_defconfig +++ /dev/null @@ -1,179 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_IGEP0020=y -CONFIG_ARM_THUMBEE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -CONFIG_CFG80211=y -CONFIG_MAC80211=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_MTD_ONENAND_2X_PROGRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_SDIO=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -CONFIG_POWER_SUPPLY=y -# CONFIG_HWMON is not set -CONFIG_SSB=m -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_VENC is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -CONFIG_PANEL_GENERIC=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_IGEP0020=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_OHCI_HCD=y -CONFIG_MMC=y -CONFIG_MMC_DEBUG=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_OMAP_HS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=m -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig deleted file mode 100644 index aa24172a3e2..00000000000 --- a/arch/arm/configs/omap3_beagle_defconfig +++ /dev/null @@ -1,134 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -# CONFIG_OMAP_MUX is not set -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP3_BEAGLE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_FB=y -CONFIG_FB_OMAP=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_RTC_CLASS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig deleted file mode 100644 index 3b072e8e71f..00000000000 --- a/arch/arm/configs/omap3_evm_defconfig +++ /dev/null @@ -1,160 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP3EVM=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_NAND=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=4 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -CONFIG_PANEL_GENERIC=y -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_TEST=y -CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap3_pandora_defconfig b/arch/arm/configs/omap3_pandora_defconfig deleted file mode 100644 index d5a62268937..00000000000 --- a/arch/arm/configs/omap3_pandora_defconfig +++ /dev/null @@ -1,158 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP3_PANDORA=y -CONFIG_ARM_THUMBEE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_MOUSE_PS2 is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_TWL4030_PWRBUTTON=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -CONFIG_OMAP2_DSS=y -CONFIG_FB_OMAP2=y -CONFIG_PANEL_TPO_TD043MTEA1=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_PERIPHERAL=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_CIFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/omap3_stalker_lks_defconfig b/arch/arm/configs/omap3_stalker_lks_defconfig deleted file mode 100644 index 1d1ab0b0b71..00000000000 --- a/arch/arm/configs/omap3_stalker_lks_defconfig +++ /dev/null @@ -1,150 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_SBC3530=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_NAND=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_TEST=y -CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap3_touchbook_defconfig b/arch/arm/configs/omap3_touchbook_defconfig deleted file mode 100644 index e988eccc93a..00000000000 --- a/arch/arm/configs/omap3_touchbook_defconfig +++ /dev/null @@ -1,621 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=15 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP3_TOUCHBOOK=y -CONFIG_ARM_THUMBEE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -CONFIG_KEXEC=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_VS_FTP=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP_DCCP=m -CONFIG_IP_SCTP=m -CONFIG_TIPC=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_WAN_ROUTER=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_IND=y -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HCIBTUSB=y -CONFIG_BT_HCIBTSDIO=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=y -CONFIG_BT_HCIBPA10X=y -CONFIG_BT_HCIBFUSB=y -CONFIG_AF_RXRPC=m -CONFIG_CFG80211=m -CONFIG_LIB80211=y -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_WIMAX=m -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_CDROM_PKTCDVD=m -CONFIG_EEPROM_93CX6=y -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -CONFIG_ISCSI_TCP=m -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_DELAY=m -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_ATM_DRIVERS is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL_TRAP=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_SPI_SPIDEV=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -CONFIG_POWER_SUPPLY=y -CONFIG_BATTERY_BQ27x00=y -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_FB=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SEQUENCER=m -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -# CONFIG_SND_ARM is not set -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_USB=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_OXU210HP_HCD=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -CONFIG_USB_TEST=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_ZERO=m -CONFIG_USB_ZERO_HNPTEST=y -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_USB_GPIO_VBUS=y -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_SDIO_UART=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SPI=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=m -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -CONFIG_JFS_FS=m -CONFIG_XFS_FS=m -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=y -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_EFI_PARTITION=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_2430sdp_defconfig b/arch/arm/configs/omap_2430sdp_defconfig deleted file mode 100644 index 0cf4147a936..00000000000 --- a/arch/arm/configs/omap_2430sdp_defconfig +++ /dev/null @@ -1,136 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -# CONFIG_OMAP_MUX_WARNINGS is not set -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP2430=y -CONFIG_MACH_OMAP_2430SDP=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IPV6 is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_SG=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_OMAP=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_USB=m -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_MON=m -CONFIG_USB_MUSB_HDRC=m -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_TIMER_STATS=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_DES=y -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig deleted file mode 100644 index 5dbe595999b..00000000000 --- a/arch/arm/configs/omap_3430sdp_defconfig +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP_3430SDP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/mmcblk0p3 rootwait debug" -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_NAND=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_NETDEVICES=y -CONFIG_PHYLIB=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_SERIO is not set -# CONFIG_CONSOLE_TRANSLATIONS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_FB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=4 -CONFIG_FB_OMAP2=y -CONFIG_PANEL_GENERIC=y -CONFIG_PANEL_SHARP_LS037V7DW01=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_TEST=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_SDIO_UART=y -CONFIG_MMC_OMAP_HS=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_3630sdp_defconfig b/arch/arm/configs/omap_3630sdp_defconfig deleted file mode 100644 index 8e8f4e94609..00000000000 --- a/arch/arm/configs/omap_3630sdp_defconfig +++ /dev/null @@ -1,154 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP_3630SDP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_VERBOSE=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_CONNECTOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_PHYLIB=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -CONFIG_W1=y -CONFIG_POWER_SUPPLY=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_STORAGE=y -CONFIG_USB_TEST=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_RTC_CLASS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig index 63e0c2d50f3..14c1e18c648 100644 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ b/arch/arm/configs/omap_4430sdp_defconfig @@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP4=y +# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set +# CONFIG_ARCH_OMAP2 is not set +# CONFIG_ARCH_OMAP3 is not set # CONFIG_OMAP_MUX is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_DM_TIMER=y diff --git a/arch/arm/configs/omap_apollon_2420_defconfig b/arch/arm/configs/omap_apollon_2420_defconfig deleted file mode 100644 index 0b24858f5d4..00000000000 --- a/arch/arm/configs/omap_apollon_2420_defconfig +++ /dev/null @@ -1,92 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_ARCH_OMAP2420=y -CONFIG_MACH_OMAP_APOLLON=y -# CONFIG_ARM_THUMB is not set -CONFIG_PREEMPT=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" -CONFIG_VFP=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_OMAP=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_HID is not set -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_MMC=y -CONFIG_MMC_OMAP=y -CONFIG_EXT2_FS=y -CONFIG_AUTOFS4_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_h4_2420_defconfig b/arch/arm/configs/omap_h4_2420_defconfig deleted file mode 100644 index 858f93aac2b..00000000000 --- a/arch/arm/configs/omap_h4_2420_defconfig +++ /dev/null @@ -1,107 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_ARCH_OMAP2420=y -CONFIG_MACH_OMAP_H4=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" -CONFIG_FPE_NWFPE=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IPV6 is not set -CONFIG_IRDA=y -CONFIG_IRLAN=y -CONFIG_IRCOMM=y -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_OMAP=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_I2C=y -CONFIG_I2C_OMAP=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_MENELAUS=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_OMAP=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_MMC=y -CONFIG_MMC_OMAP=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_ldp_defconfig b/arch/arm/configs/omap_ldp_defconfig deleted file mode 100644 index c7bb558316d..00000000000 --- a/arch/arm/configs/omap_ldp_defconfig +++ /dev/null @@ -1,135 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP_LDP=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_CONNECTOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -CONFIG_W1=y -CONFIG_POWER_SUPPLY=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_TWL4030_CORE=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FB_OMAP=y -CONFIG_FB_OMAP_LCD_VGA=y -CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4 -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_RTC_CLASS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig deleted file mode 100644 index 0a7ed449cde..00000000000 --- a/arch/arm/configs/omap_zoom2_defconfig +++ /dev/null @@ -1,143 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP_ZOOM2=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_VERBOSE=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_CONNECTOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -CONFIG_W1=y -CONFIG_POWER_SUPPLY=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_ZERO=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_RTC_CLASS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig deleted file mode 100644 index f8085b0b9ec..00000000000 --- a/arch/arm/configs/omap_zoom3_defconfig +++ /dev/null @@ -1,155 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP_ZOOM3=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_VERBOSE=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_CONNECTOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_TWL4030=y -CONFIG_W1=y -CONFIG_POWER_SUPPLY=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_STORAGE=y -CONFIG_USB_TEST=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_ZERO=m -CONFIG_USB_AUDIO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_MMC_OMAP_HS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/overo_defconfig b/arch/arm/configs/overo_defconfig deleted file mode 100644 index 6fa1b14a7a9..00000000000 --- a/arch/arm/configs/overo_defconfig +++ /dev/null @@ -1,275 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OVERO=y -CONFIG_ARM_THUMBEE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIBCM203X=y -CONFIG_BT_HCIBPA10X=y -CONFIG_CFG80211=y -CONFIG_MAC80211=y -CONFIG_MAC80211_RC_PID=y -CONFIG_MAC80211_RC_DEFAULT_PID=y -CONFIG_MAC80211_LEDS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_CDROM_PKTCDVD=m -CONFIG_EEPROM_LEGACY=y -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=m -CONFIG_SCSI_MULTI_LUN=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_DELAY=m -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_TUN=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_USB_ZD1201=m -CONFIG_RTL8187=m -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_USB=y -CONFIG_LIBERTAS_SDIO=y -CONFIG_LIBERTAS_DEBUG=y -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=y -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=m -CONFIG_PPP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_SUPPLY=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SEQUENCER=m -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_DEBUG=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SERIAL=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_LED=m -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_SDIO_UART=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_XFS_FS=m -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_FTRACE is not set -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig deleted file mode 100644 index ffaef43ec0b..00000000000 --- a/arch/arm/configs/rx51_defconfig +++ /dev/null @@ -1,222 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_NOKIA_RX51=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8" -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m -CONFIG_PHONET=y -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_CFG80211=y -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_OOPS=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_NETDEVICES=y -CONFIG_TUN=m -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=m -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=m -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -CONFIG_WATCHDOG=y -CONFIG_OMAP_WATCHDOG=m -CONFIG_TWL4030_WATCHDOG=m -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_FB=y -CONFIG_OMAP2_DSS=y -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_DPI is not set -# CONFIG_OMAP2_DSS_VENC is not set -CONFIG_OMAP2_DSS_SDI=y -CONFIG_FB_OMAP2=y -CONFIG_PANEL_ACX565AKM=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_HID=m -CONFIG_USB_HID=m -CONFIG_HID_A4TECH=m -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_EZKEY=m -CONFIG_HID_GYRATION=m -CONFIG_HID_LOGITECH=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_PANTHERLORD=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_HID_SUNPLUS=m -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_STORAGE=m -CONFIG_USB_LIBUSUAL=y -CONFIG_USB_TEST=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_ZERO=m -CONFIG_USB_FILE_STORAGE=m -CONFIG_USB_G_NOKIA=m -CONFIG_TWL4030_USB=y -CONFIG_MMC=m -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_OMAP_HS=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m -CONFIG_RTC_CLASS=m -CONFIG_RTC_DRV_TWL4030=m -CONFIG_EXT2_FS=m -CONFIG_EXT3_FS=m -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_UBIFS_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_TIMER_STATS=y -CONFIG_PROVE_LOCKING=y -CONFIG_LOCK_STAT=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SECURITY=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC7=m -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/s5pc110_defconfig b/arch/arm/configs/s5pc110_defconfig deleted file mode 100644 index 22c2d147f79..00000000000 --- a/arch/arm/configs/s5pc110_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_S5PV210=y -CONFIG_S3C_LOWLEVEL_UART_PORT=1 -CONFIG_MACH_SMDKC110=y -CONFIG_VMSPLIT_2G=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_HW_RANDOM=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_INOTIFY=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CRAMFS=y -CONFIG_ROMFS_FS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y -CONFIG_DEBUG_S3C_UART=1 -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index 1753836d005..0488a1eb4d7 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig @@ -7,6 +7,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_S5PV210=y CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_DEV_FB=y +CONFIG_S5PV210_SETUP_FB_24BPP=y +CONFIG_MACH_AQUILA=y +CONFIG_MACH_GONI=y +CONFIG_MACH_SMDKC110=y CONFIG_MACH_SMDKV210=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT=y diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 73237bd130a..6550db3aa5c 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -1,3 +1,3 @@ include include/asm-generic/Kbuild.asm -unifdef-y += hwcap.h +header-y += hwcap.h diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 66c160b8547..9d6122096fb 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -14,7 +14,7 @@ * cache before the transfer is done, causing old data to be seen by * the CPU. */ -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES /* * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 69ce0727edb..c226fe10553 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -144,16 +144,6 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask) return 0; } -static inline int dma_get_cache_alignment(void) -{ - return 32; -} - -static inline int dma_is_consistent(struct device *dev, dma_addr_t handle) -{ - return !!arch_is_coherent(); -} - /* * DMA errors are defined by all-bits-set in the DMA address. */ @@ -298,7 +288,15 @@ extern void dmabounce_unregister_dev(struct device *); * DMA access and 1 if the buffer needs to be bounced. * */ +#ifdef CONFIG_SA1111 extern int dma_needs_bounce(struct device*, dma_addr_t, size_t); +#else +static inline int dma_needs_bounce(struct device *dev, dma_addr_t addr, + size_t size) +{ + return 0; +} +#endif /* * The DMA API, implemented by dmabounce.c. See below for descriptions. diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 6750b8e45a4..5747a8baa41 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -59,6 +59,8 @@ typedef struct user_fp elf_fpregset_t; #define R_ARM_THM_CALL 10 #define R_ARM_THM_JUMP24 30 +#define R_ARM_THM_MOVW_ABS_NC 47 +#define R_ARM_THM_MOVT_ABS 48 /* * These are used to set parameters in the core dumps. diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index f82b25d4f73..212e47828c7 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -48,8 +48,6 @@ struct tracectx { /* CoreSight Component Registers */ #define CSCR_CLASS 0xff4 -#define CSCR_PRSR 0x314 - #define UNLOCK_MAGIC 0xc5acce55 /* ETM control register, "ETM Architecture", 3.3.1 */ @@ -132,6 +130,12 @@ struct tracectx { ETMCTRL_BRANCH_OUTPUT | \ ETMCTRL_DO_CONTEXTID) +/* ETM management registers, "ETM Architecture", 3.5.24 */ +#define ETMMR_OSLAR 0x300 +#define ETMMR_OSLSR 0x304 +#define ETMMR_OSSRR 0x308 +#define ETMMR_PDSR 0x314 + /* ETB registers, "CoreSight Components TRM", 9.3 */ #define ETBR_DEPTH 0x04 #define ETBR_STATUS 0x0c diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h index 6a6c66be7f6..f35b86e68dd 100644 --- a/arch/arm/include/asm/hardware/pl080.h +++ b/arch/arm/include/asm/hardware/pl080.h @@ -43,7 +43,7 @@ /* Per channel configuration registers */ -#define PL008_Cx_STRIDE (0x20) +#define PL080_Cx_STRIDE (0x20) #define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) #define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) #define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) @@ -68,6 +68,8 @@ #define PL080_CONTROL_TC_IRQ_EN (1 << 31) #define PL080_CONTROL_PROT_MASK (0x7 << 28) #define PL080_CONTROL_PROT_SHIFT (28) +#define PL080_CONTROL_PROT_CACHE (1 << 30) +#define PL080_CONTROL_PROT_BUFF (1 << 29) #define PL080_CONTROL_PROT_SYS (1 << 28) #define PL080_CONTROL_DST_INCR (1 << 27) #define PL080_CONTROL_SRC_INCR (1 << 26) diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h index 46492a63a7c..ebb3ceaa8fa 100644 --- a/arch/arm/include/asm/hardware/scoop.h +++ b/arch/arm/include/asm/hardware/scoop.h @@ -22,18 +22,23 @@ #define SCOOP_GPWR 0x24 #define SCOOP_GPRR 0x28 -#define SCOOP_GPCR_PA22 ( 1 << 12 ) -#define SCOOP_GPCR_PA21 ( 1 << 11 ) -#define SCOOP_GPCR_PA20 ( 1 << 10 ) -#define SCOOP_GPCR_PA19 ( 1 << 9 ) -#define SCOOP_GPCR_PA18 ( 1 << 8 ) -#define SCOOP_GPCR_PA17 ( 1 << 7 ) -#define SCOOP_GPCR_PA16 ( 1 << 6 ) -#define SCOOP_GPCR_PA15 ( 1 << 5 ) -#define SCOOP_GPCR_PA14 ( 1 << 4 ) -#define SCOOP_GPCR_PA13 ( 1 << 3 ) -#define SCOOP_GPCR_PA12 ( 1 << 2 ) -#define SCOOP_GPCR_PA11 ( 1 << 1 ) +#define SCOOP_CPR_OUT (1 << 7) +#define SCOOP_CPR_SD_3V (1 << 2) +#define SCOOP_CPR_CF_XV (1 << 1) +#define SCOOP_CPR_CF_3V (1 << 0) + +#define SCOOP_GPCR_PA22 (1 << 12) +#define SCOOP_GPCR_PA21 (1 << 11) +#define SCOOP_GPCR_PA20 (1 << 10) +#define SCOOP_GPCR_PA19 (1 << 9) +#define SCOOP_GPCR_PA18 (1 << 8) +#define SCOOP_GPCR_PA17 (1 << 7) +#define SCOOP_GPCR_PA16 (1 << 6) +#define SCOOP_GPCR_PA15 (1 << 5) +#define SCOOP_GPCR_PA14 (1 << 4) +#define SCOOP_GPCR_PA13 (1 << 3) +#define SCOOP_GPCR_PA12 (1 << 2) +#define SCOOP_GPCR_PA11 (1 << 1) struct scoop_config { unsigned short io_out; diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index feb988a7ec3..5aff5812660 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -36,7 +36,7 @@ extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte); extern void *kmap(struct page *page); extern void kunmap(struct page *page); extern void *kmap_atomic(struct page *page, enum km_type type); -extern void kunmap_atomic(void *kvaddr, enum km_type type); +extern void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type); extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); extern struct page *kmap_atomic_to_page(const void *ptr); #endif diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/asm/ioctls.h index 7f0b6d13296..0b30894b548 100644 --- a/arch/arm/include/asm/ioctls.h +++ b/arch/arm/include/asm/ioctls.h @@ -52,6 +52,7 @@ #define TCSETSF2 _IOW('T',0x2D, struct termios2) #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ +#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ #define TIOCGRS485 0x542E #define TIOCSRS485 0x542F @@ -81,6 +82,7 @@ #define TIOCPKT_START 8 #define TIOCPKT_NOSTOP 16 #define TIOCPKT_DOSTOP 32 +#define TIOCPKT_IOCTL 64 #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h index 67af4b84198..08265993227 100644 --- a/arch/arm/include/asm/kgdb.h +++ b/arch/arm/include/asm/kgdb.h @@ -70,11 +70,11 @@ extern int kgdb_fault_expected; #define _GP_REGS 16 #define _FP_REGS 8 #define _EXTRA_REGS 2 -#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS) +#define DBG_MAX_REG_NUM (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS) #define KGDB_MAX_NO_CPUS 1 #define BUFMAX 400 -#define NUMREGBYTES (GDB_MAX_REGS << 2) +#define NUMREGBYTES (DBG_MAX_REG_NUM << 2) #define NUMCRITREGBYTES (32 << 2) #define _R0 0 @@ -93,7 +93,7 @@ extern int kgdb_fault_expected; #define _SPT 13 #define _LR 14 #define _PC 15 -#define _CPSR (GDB_MAX_REGS - 1) +#define _CPSR (DBG_MAX_REG_NUM - 1) /* * So that we can denote the end of a frame for tracing, diff --git a/arch/arm/include/asm/local64.h b/arch/arm/include/asm/local64.h new file mode 100644 index 00000000000..36c93b5cc23 --- /dev/null +++ b/arch/arm/include/asm/local64.h @@ -0,0 +1 @@ +#include <asm-generic/local64.h> diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index c974be8913a..7ce15eb15f7 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -158,15 +158,24 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { - if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { - regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); - return 1; + unsigned long mode = regs->ARM_cpsr & MODE_MASK; + + /* + * Always clear the F (FIQ) and A (delayed abort) bits + */ + regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); + + if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { + if (mode == USR_MODE) + return 1; + if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE) + return 1; } /* * Force CPSR to something logical... */ - regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; + regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; if (!(elf_hwcap & HWCAP_26BIT)) regs->ARM_cpsr |= USR_MODE; diff --git a/arch/arm/include/asm/termbits.h b/arch/arm/include/asm/termbits.h index f784d11f40b..704135d28d1 100644 --- a/arch/arm/include/asm/termbits.h +++ b/arch/arm/include/asm/termbits.h @@ -177,6 +177,7 @@ struct ktermios { #define FLUSHO 0010000 #define PENDIN 0040000 #define IEXTEN 0100000 +#define EXTPROC 0200000 /* tcflow() and TCXONC use these */ #define TCOOFF 0 diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index bd863d8608c..33b546ae72d 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -378,7 +378,11 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_V6_I_ASID)) asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); if (tlb_flag(TLB_V7_UIS_ASID)) +#ifdef CONFIG_ARM_ERRATA_720789 + asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc"); +#else asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc"); +#endif if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ @@ -424,7 +428,11 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V7_UIS_PAGE)) +#ifdef CONFIG_ARM_ERRATA_720789 + asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc"); +#else asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc"); +#endif if (tlb_flag(TLB_BTB)) { /* flush the branch target cache */ diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index dd2bf53000f..d02cfb68348 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -392,6 +392,7 @@ #define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) #define __NR_perf_event_open (__NR_SYSCALL_BASE+364) #define __NR_recvmmsg (__NR_SYSCALL_BASE+365) +#define __NR_accept4 (__NR_SYSCALL_BASE+366) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 37ae301cc47..afeb71fa72c 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -375,6 +375,7 @@ CALL(sys_rt_tgsigqueueinfo) CALL(sys_perf_event_open) /* 365 */ CALL(sys_recvmmsg) + CALL(sys_accept4) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 2c1db77d784..f05a35a5969 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -92,75 +92,111 @@ ENDPROC(ret_from_fork) #define CALL(x) .long x #ifdef CONFIG_FUNCTION_TRACER +/* + * When compiling with -pg, gcc inserts a call to the mcount routine at the + * start of every function. In mcount, apart from the function's address (in + * lr), we need to get hold of the function's caller's address. + * + * Older GCCs (pre-4.4) inserted a call to a routine called mcount like this: + * + * bl mcount + * + * These versions have the limitation that in order for the mcount routine to + * be able to determine the function's caller's address, an APCS-style frame + * pointer (which is set up with something like the code below) is required. + * + * mov ip, sp + * push {fp, ip, lr, pc} + * sub fp, ip, #4 + * + * With EABI, these frame pointers are not available unless -mapcs-frame is + * specified, and if building as Thumb-2, not even then. + * + * Newer GCCs (4.4+) solve this problem by introducing a new version of mcount, + * with call sites like: + * + * push {lr} + * bl __gnu_mcount_nc + * + * With these compilers, frame pointers are not necessary. + * + * mcount can be thought of as a function called in the middle of a subroutine + * call. As such, it needs to be transparent for both the caller and the + * callee: the original lr needs to be restored when leaving mcount, and no + * registers should be clobbered. (In the __gnu_mcount_nc implementation, we + * clobber the ip register. This is OK because the ARM calling convention + * allows it to be clobbered in subroutines and doesn't use it to hold + * parameters.) + */ #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(mcount) - stmdb sp!, {r0-r3, lr} - mov r0, lr - sub r0, r0, #MCOUNT_INSN_SIZE + stmdb sp!, {r0-r3, lr} + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE .globl mcount_call mcount_call: - bl ftrace_stub - ldr lr, [fp, #-4] @ restore lr - ldmia sp!, {r0-r3, pc} + bl ftrace_stub + ldr lr, [fp, #-4] @ restore lr + ldmia sp!, {r0-r3, pc} ENTRY(ftrace_caller) - stmdb sp!, {r0-r3, lr} - ldr r1, [fp, #-4] - mov r0, lr - sub r0, r0, #MCOUNT_INSN_SIZE + stmdb sp!, {r0-r3, lr} + ldr r1, [fp, #-4] + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE .globl ftrace_call ftrace_call: - bl ftrace_stub - ldr lr, [fp, #-4] @ restore lr - ldmia sp!, {r0-r3, pc} + bl ftrace_stub + ldr lr, [fp, #-4] @ restore lr + ldmia sp!, {r0-r3, pc} #else ENTRY(__gnu_mcount_nc) - stmdb sp!, {r0-r3, lr} - ldr r0, =ftrace_trace_function - ldr r2, [r0] - adr r0, ftrace_stub - cmp r0, r2 - bne gnu_trace - ldmia sp!, {r0-r3, ip, lr} - mov pc, ip + stmdb sp!, {r0-r3, lr} + ldr r0, =ftrace_trace_function + ldr r2, [r0] + adr r0, ftrace_stub + cmp r0, r2 + bne gnu_trace + ldmia sp!, {r0-r3, ip, lr} + mov pc, ip gnu_trace: - ldr r1, [sp, #20] @ lr of instrumented routine - mov r0, lr - sub r0, r0, #MCOUNT_INSN_SIZE - mov lr, pc - mov pc, r2 - ldmia sp!, {r0-r3, ip, lr} - mov pc, ip + ldr r1, [sp, #20] @ lr of instrumented routine + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE + mov lr, pc + mov pc, r2 + ldmia sp!, {r0-r3, ip, lr} + mov pc, ip ENTRY(mcount) - stmdb sp!, {r0-r3, lr} - ldr r0, =ftrace_trace_function - ldr r2, [r0] - adr r0, ftrace_stub - cmp r0, r2 - bne trace - ldr lr, [fp, #-4] @ restore lr - ldmia sp!, {r0-r3, pc} + stmdb sp!, {r0-r3, lr} + ldr r0, =ftrace_trace_function + ldr r2, [r0] + adr r0, ftrace_stub + cmp r0, r2 + bne trace + ldr lr, [fp, #-4] @ restore lr + ldmia sp!, {r0-r3, pc} trace: - ldr r1, [fp, #-4] @ lr of instrumented routine - mov r0, lr - sub r0, r0, #MCOUNT_INSN_SIZE - mov lr, pc - mov pc, r2 - ldr lr, [fp, #-4] @ restore lr - ldmia sp!, {r0-r3, pc} + ldr r1, [fp, #-4] @ lr of instrumented routine + mov r0, lr + sub r0, r0, #MCOUNT_INSN_SIZE + mov lr, pc + mov pc, r2 + ldr lr, [fp, #-4] @ restore lr + ldmia sp!, {r0-r3, pc} #endif /* CONFIG_DYNAMIC_FTRACE */ .globl ftrace_stub ftrace_stub: - mov pc, lr + mov pc, lr #endif /* CONFIG_FUNCTION_TRACER */ diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 82775396630..33c7077174d 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -230,7 +230,7 @@ static void etm_dump(void) etb_lock(t); } -static void sysrq_etm_dump(int key, struct tty_struct *tty) +static void sysrq_etm_dump(int key) { dev_dbg(tracer.dev, "Dumping ETB buffer\n"); etm_dump(); @@ -543,7 +543,9 @@ static int __init etm_probe(struct amba_device *dev, struct amba_id *id) t->etm_portsz = 1; etm_unlock(t); - ret = etm_readl(t, CSCR_PRSR); + (void)etm_readl(t, ETMMR_PDSR); + /* dummy first read */ + (void)etm_readl(&tracer, ETMMR_OSSRR); t->ncmppairs = etm_readl(t, ETMR_CONFCODE) & 0xf; etm_writel(t, 0x440, ETMR_CTRL); diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c index c868a886411..d6e8b4d2e60 100644 --- a/arch/arm/kernel/kgdb.c +++ b/arch/arm/kernel/kgdb.c @@ -10,57 +10,62 @@ * Deepak Saxena <dsaxena@plexity.net> */ #include <linux/irq.h> +#include <linux/kdebug.h> #include <linux/kgdb.h> #include <asm/traps.h> -/* Make a local copy of the registers passed into the handler (bletch) */ -void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs) +struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { - int regno; - - /* Initialize all to zero. */ - for (regno = 0; regno < GDB_MAX_REGS; regno++) - gdb_regs[regno] = 0; + { "r0", 4, offsetof(struct pt_regs, ARM_r0)}, + { "r1", 4, offsetof(struct pt_regs, ARM_r1)}, + { "r2", 4, offsetof(struct pt_regs, ARM_r2)}, + { "r3", 4, offsetof(struct pt_regs, ARM_r3)}, + { "r4", 4, offsetof(struct pt_regs, ARM_r4)}, + { "r5", 4, offsetof(struct pt_regs, ARM_r5)}, + { "r6", 4, offsetof(struct pt_regs, ARM_r6)}, + { "r7", 4, offsetof(struct pt_regs, ARM_r7)}, + { "r8", 4, offsetof(struct pt_regs, ARM_r8)}, + { "r9", 4, offsetof(struct pt_regs, ARM_r9)}, + { "r10", 4, offsetof(struct pt_regs, ARM_r10)}, + { "fp", 4, offsetof(struct pt_regs, ARM_fp)}, + { "ip", 4, offsetof(struct pt_regs, ARM_ip)}, + { "sp", 4, offsetof(struct pt_regs, ARM_sp)}, + { "lr", 4, offsetof(struct pt_regs, ARM_lr)}, + { "pc", 4, offsetof(struct pt_regs, ARM_pc)}, + { "f0", 12, -1 }, + { "f1", 12, -1 }, + { "f2", 12, -1 }, + { "f3", 12, -1 }, + { "f4", 12, -1 }, + { "f5", 12, -1 }, + { "f6", 12, -1 }, + { "f7", 12, -1 }, + { "fps", 4, -1 }, + { "cpsr", 4, offsetof(struct pt_regs, ARM_cpsr)}, +}; - gdb_regs[_R0] = kernel_regs->ARM_r0; - gdb_regs[_R1] = kernel_regs->ARM_r1; - gdb_regs[_R2] = kernel_regs->ARM_r2; - gdb_regs[_R3] = kernel_regs->ARM_r3; - gdb_regs[_R4] = kernel_regs->ARM_r4; - gdb_regs[_R5] = kernel_regs->ARM_r5; - gdb_regs[_R6] = kernel_regs->ARM_r6; - gdb_regs[_R7] = kernel_regs->ARM_r7; - gdb_regs[_R8] = kernel_regs->ARM_r8; - gdb_regs[_R9] = kernel_regs->ARM_r9; - gdb_regs[_R10] = kernel_regs->ARM_r10; - gdb_regs[_FP] = kernel_regs->ARM_fp; - gdb_regs[_IP] = kernel_regs->ARM_ip; - gdb_regs[_SPT] = kernel_regs->ARM_sp; - gdb_regs[_LR] = kernel_regs->ARM_lr; - gdb_regs[_PC] = kernel_regs->ARM_pc; - gdb_regs[_CPSR] = kernel_regs->ARM_cpsr; +char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) +{ + if (regno >= DBG_MAX_REG_NUM || regno < 0) + return NULL; + + if (dbg_reg_def[regno].offset != -1) + memcpy(mem, (void *)regs + dbg_reg_def[regno].offset, + dbg_reg_def[regno].size); + else + memset(mem, 0, dbg_reg_def[regno].size); + return dbg_reg_def[regno].name; } -/* Copy local gdb registers back to kgdb regs, for later copy to kernel */ -void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs) +int dbg_set_reg(int regno, void *mem, struct pt_regs *regs) { - kernel_regs->ARM_r0 = gdb_regs[_R0]; - kernel_regs->ARM_r1 = gdb_regs[_R1]; - kernel_regs->ARM_r2 = gdb_regs[_R2]; - kernel_regs->ARM_r3 = gdb_regs[_R3]; - kernel_regs->ARM_r4 = gdb_regs[_R4]; - kernel_regs->ARM_r5 = gdb_regs[_R5]; - kernel_regs->ARM_r6 = gdb_regs[_R6]; - kernel_regs->ARM_r7 = gdb_regs[_R7]; - kernel_regs->ARM_r8 = gdb_regs[_R8]; - kernel_regs->ARM_r9 = gdb_regs[_R9]; - kernel_regs->ARM_r10 = gdb_regs[_R10]; - kernel_regs->ARM_fp = gdb_regs[_FP]; - kernel_regs->ARM_ip = gdb_regs[_IP]; - kernel_regs->ARM_sp = gdb_regs[_SPT]; - kernel_regs->ARM_lr = gdb_regs[_LR]; - kernel_regs->ARM_pc = gdb_regs[_PC]; - kernel_regs->ARM_cpsr = gdb_regs[_CPSR]; + if (regno >= DBG_MAX_REG_NUM || regno < 0) + return -EINVAL; + + if (dbg_reg_def[regno].offset != -1) + memcpy((void *)regs + dbg_reg_def[regno].offset, mem, + dbg_reg_def[regno].size); + return 0; } void @@ -74,7 +79,7 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task) return; /* Initialize to zero */ - for (regno = 0; regno < GDB_MAX_REGS; regno++) + for (regno = 0; regno < DBG_MAX_REG_NUM; regno++) gdb_regs[regno] = 0; /* Otherwise, we have only some registers from switch_to() */ @@ -176,6 +181,33 @@ void kgdb_roundup_cpus(unsigned long flags) local_irq_disable(); } +static int __kgdb_notify(struct die_args *args, unsigned long cmd) +{ + struct pt_regs *regs = args->regs; + + if (kgdb_handle_exception(1, args->signr, cmd, regs)) + return NOTIFY_DONE; + return NOTIFY_STOP; +} +static int +kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + ret = __kgdb_notify(ptr, cmd); + local_irq_restore(flags); + + return ret; +} + +static struct notifier_block kgdb_notifier = { + .notifier_call = kgdb_notify, + .priority = -INT_MAX, +}; + + /** * kgdb_arch_init - Perform any architecture specific initalization. * @@ -184,6 +216,11 @@ void kgdb_roundup_cpus(unsigned long flags) */ int kgdb_arch_init(void) { + int ret = register_die_notifier(&kgdb_notifier); + + if (ret != 0) + return ret; + register_undef_hook(&kgdb_brkpt_hook); register_undef_hook(&kgdb_compiled_brkpt_hook); @@ -200,6 +237,7 @@ void kgdb_arch_exit(void) { unregister_undef_hook(&kgdb_brkpt_hook); unregister_undef_hook(&kgdb_compiled_brkpt_hook); + unregister_die_notifier(&kgdb_notifier); } /* diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index c628bdf6c43..6b4605893f1 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -102,7 +102,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned long loc; Elf32_Sym *sym; s32 offset; +#ifdef CONFIG_THUMB2_KERNEL u32 upper, lower, sign, j1, j2; +#endif offset = ELF32_R_SYM(rel->r_info); if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) { @@ -185,6 +187,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, (offset & 0x0fff); break; +#ifdef CONFIG_THUMB2_KERNEL case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: upper = *(u16 *)loc; @@ -233,9 +236,40 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, *(u16 *)(loc + 2) = (u16)((lower & 0xd000) | (j1 << 13) | (j2 << 11) | ((offset >> 1) & 0x07ff)); + break; + + case R_ARM_THM_MOVW_ABS_NC: + case R_ARM_THM_MOVT_ABS: upper = *(u16 *)loc; lower = *(u16 *)(loc + 2); + + /* + * MOVT/MOVW instructions encoding in Thumb-2: + * + * i = upper[10] + * imm4 = upper[3:0] + * imm3 = lower[14:12] + * imm8 = lower[7:0] + * + * imm16 = imm4:i:imm3:imm8 + */ + offset = ((upper & 0x000f) << 12) | + ((upper & 0x0400) << 1) | + ((lower & 0x7000) >> 4) | (lower & 0x00ff); + offset = (offset ^ 0x8000) - 0x8000; + offset += sym->st_value; + + if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) + offset >>= 16; + + *(u16 *)loc = (u16)((upper & 0xfbf0) | + ((offset & 0xf000) >> 12) | + ((offset & 0x0800) >> 1)); + *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) | + ((offset & 0x0700) << 4) | + (offset & 0x00ff)); break; +#endif default: printk(KERN_ERR "%s: unknown relocation: %u\n", diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index de12536d687..417c392ddf1 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -164,20 +164,20 @@ armpmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx) { - s64 left = atomic64_read(&hwc->period_left); + s64 left = local64_read(&hwc->period_left); s64 period = hwc->sample_period; int ret = 0; if (unlikely(left <= -period)) { left = period; - atomic64_set(&hwc->period_left, left); + local64_set(&hwc->period_left, left); hwc->last_period = period; ret = 1; } if (unlikely(left <= 0)) { left += period; - atomic64_set(&hwc->period_left, left); + local64_set(&hwc->period_left, left); hwc->last_period = period; ret = 1; } @@ -185,7 +185,7 @@ armpmu_event_set_period(struct perf_event *event, if (left > (s64)armpmu->max_period) left = armpmu->max_period; - atomic64_set(&hwc->prev_count, (u64)-left); + local64_set(&hwc->prev_count, (u64)-left); armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); @@ -204,18 +204,18 @@ armpmu_event_update(struct perf_event *event, u64 delta; again: - prev_raw_count = atomic64_read(&hwc->prev_count); + prev_raw_count = local64_read(&hwc->prev_count); new_raw_count = armpmu->read_counter(idx); - if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, + if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, new_raw_count) != prev_raw_count) goto again; delta = (new_raw_count << shift) - (prev_raw_count << shift); delta >>= shift; - atomic64_add(delta, &event->count); - atomic64_sub(delta, &hwc->period_left); + local64_add(delta, &event->count); + local64_sub(delta, &hwc->period_left); return new_raw_count; } @@ -478,7 +478,7 @@ __hw_perf_event_init(struct perf_event *event) if (!hwc->sample_period) { hwc->sample_period = armpmu->max_period; hwc->last_period = hwc->sample_period; - atomic64_set(&hwc->period_left, hwc->sample_period); + local64_set(&hwc->period_left, hwc->sample_period); } err = 0; diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index c23501842b9..62e7c61d034 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -62,8 +62,9 @@ asmlinkage int sys_vfork(struct pt_regs *regs) /* sys_execve() executes a new program. * This is called indirectly via a small wrapper */ -asmlinkage int sys_execve(char __user *filenamei, char __user * __user *argv, - char __user * __user *envp, struct pt_regs *regs) +asmlinkage int sys_execve(const char __user *filenamei, + const char __user *const __user *argv, + const char __user *const __user *envp, struct pt_regs *regs) { int error; char * filename; @@ -78,14 +79,17 @@ out: return error; } -int kernel_execve(const char *filename, char *const argv[], char *const envp[]) +int kernel_execve(const char *filename, + const char *const argv[], + const char *const envp[]) { struct pt_regs regs; int ret; memset(®s, 0, sizeof(struct pt_regs)); - ret = do_execve((char *)filename, (char __user * __user *)argv, - (char __user * __user *)envp, ®s); + ret = do_execve(filename, + (const char __user *const __user *)argv, + (const char __user *const __user *)envp, ®s); if (ret < 0) goto out; diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 33ff678e32f..4ad8da15ef2 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -141,7 +141,7 @@ static long cp_oldabi_stat64(struct kstat *stat, return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; } -asmlinkage long sys_oabi_stat64(char __user * filename, +asmlinkage long sys_oabi_stat64(const char __user * filename, struct oldabi_stat64 __user * statbuf) { struct kstat stat; @@ -151,7 +151,7 @@ asmlinkage long sys_oabi_stat64(char __user * filename, return error; } -asmlinkage long sys_oabi_lstat64(char __user * filename, +asmlinkage long sys_oabi_lstat64(const char __user * filename, struct oldabi_stat64 __user * statbuf) { struct kstat stat; @@ -172,7 +172,7 @@ asmlinkage long sys_oabi_fstat64(unsigned long fd, } asmlinkage long sys_oabi_fstatat64(int dfd, - char __user *filename, + const char __user *filename, struct oldabi_stat64 __user *statbuf, int flag) { diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 02138af631e..44eb9f76493 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -75,7 +75,7 @@ static struct at91_usbh_data __initdata cam60_usbh_data = { * SPI devices. */ #if defined(CONFIG_MTD_DATAFLASH) -static struct mtd_partition __initdata cam60_spi_partitions[] = { +static struct mtd_partition cam60_spi_partitions[] = { { .name = "BOOT1", .offset = 0, @@ -98,14 +98,14 @@ static struct mtd_partition __initdata cam60_spi_partitions[] = { }, }; -static struct flash_platform_data __initdata cam60_spi_flash_platform_data = { +static struct flash_platform_data cam60_spi_flash_platform_data = { .name = "spi_flash", .parts = cam60_spi_partitions, .nr_parts = ARRAY_SIZE(cam60_spi_partitions) }; #endif -static struct spi_board_info cam60_spi_devices[] = { +static struct spi_board_info cam60_spi_devices[] __initdata = { #if defined(CONFIG_MTD_DATAFLASH) { /* DataFlash chip */ .modalias = "mtd_dataflash", diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index b3ebe9e4871..d0b7d870be9 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -69,13 +69,6 @@ #define SYSPLD_VIRT_BASE 0xfe000000 #define SYSPLD_BASE SYSPLD_VIRT_BASE -#ifndef __ASSEMBLER__ - -#define PCIO_BASE IO_BASE - -#endif - - #if defined (CONFIG_ARCH_AUTCPU12) #define CS89712_VIRT_BASE CLPS7111_VIRT_BASE diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 0316e201ada..71f90f86474 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365 select AINTC select ARCH_DAVINCI_DMx +config ARCH_DAVINCI_TNETV107X + select CPU_V6 + select CP_INTC + bool "TNETV107X based system" + comment "DaVinci Board Type" config MACH_DAVINCI_EVM @@ -173,6 +178,13 @@ config DA850_UI_RMII endchoice +config MACH_TNETV107X + bool "TI TNETV107X Reference Platform" + default ARCH_DAVINCI_TNETV107X + depends on ARCH_DAVINCI_TNETV107X + help + Say Y here to select the TI TNETV107X Evaluation Module. + config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 6aac880eb79..eab4c0fd667 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o +obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o @@ -30,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 212d97084bd..c3994f341e4 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -208,7 +208,7 @@ static struct snd_platform_data da830_evm_snd_data = { .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da830_iis_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, @@ -494,12 +494,42 @@ static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { .bus_delay = 0, /* usec */ }; +/* + * The following EDMA channels/slots are not being used by drivers (for + * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence + * they are being reserved for codecs on the DSP side. + */ +static const s16 da830_dma_rsv_chans[][2] = { + /* (offset, number) */ + { 8, 2}, + {12, 2}, + {24, 4}, + {30, 2}, + {-1, -1} +}; + +static const s16 da830_dma_rsv_slots[][2] = { + /* (offset, number) */ + { 8, 2}, + {12, 2}, + {24, 4}, + {30, 26}, + {-1, -1} +}; + +static struct edma_rsv_info da830_edma_rsv[] = { + { + .rsv_chans = da830_dma_rsv_chans, + .rsv_slots = da830_dma_rsv_slots, + }, +}; + static __init void da830_evm_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; int ret; - ret = da8xx_register_edma(); + ret = da830_register_edma(da830_edma_rsv); if (ret) pr_warning("da830_evm_init: edma registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index b280efb1fa1..fdc2cc500fc 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -343,7 +343,7 @@ static struct snd_platform_data da850_evm_snd_data = { .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da850_iis_serializer_direction, - .eventq_no = EVENTQ_1, + .asp_chan_q = EVENTQ_1, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, @@ -637,6 +637,56 @@ static int __init da850_evm_config_emac(void) } device_initcall(da850_evm_config_emac); +/* + * The following EDMA channels/slots are not being used by drivers (for + * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence + * they are being reserved for codecs on the DSP side. + */ +static const s16 da850_dma0_rsv_chans[][2] = { + /* (offset, number) */ + { 8, 6}, + {24, 4}, + {30, 2}, + {-1, -1} +}; + +static const s16 da850_dma0_rsv_slots[][2] = { + /* (offset, number) */ + { 8, 6}, + {24, 4}, + {30, 50}, + {-1, -1} +}; + +static const s16 da850_dma1_rsv_chans[][2] = { + /* (offset, number) */ + { 0, 28}, + {30, 2}, + {-1, -1} +}; + +static const s16 da850_dma1_rsv_slots[][2] = { + /* (offset, number) */ + { 0, 28}, + {30, 90}, + {-1, -1} +}; + +static struct edma_rsv_info da850_edma_cc0_rsv = { + .rsv_chans = da850_dma0_rsv_chans, + .rsv_slots = da850_dma0_rsv_slots, +}; + +static struct edma_rsv_info da850_edma_cc1_rsv = { + .rsv_chans = da850_dma1_rsv_chans, + .rsv_slots = da850_dma1_rsv_slots, +}; + +static struct edma_rsv_info *da850_edma_rsv[2] = { + &da850_edma_cc0_rsv, + &da850_edma_cc1_rsv, +}; + static __init void da850_evm_init(void) { int ret; @@ -646,7 +696,7 @@ static __init void da850_evm_init(void) pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n", ret); - ret = da8xx_register_edma(); + ret = da850_register_edma(da850_edma_rsv); if (ret) pr_warning("da850_evm_init: edma registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6d8889342c9..4502f346b2b 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -323,7 +323,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction), .tdm_slots = 2, .serial_dir = dm646x_iis_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, }, { .tx_dma_offset = 0x400, @@ -332,7 +332,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction), .tdm_slots = 32, .serial_dir = dm646x_dit_serializer_direction, - .eventq_no = EVENTQ_0, + .asp_chan_q = EVENTQ_0, }, }; @@ -721,6 +721,39 @@ static struct davinci_uart_config uart_config __initdata = { #define DM646X_EVM_PHY_MASK (0x2) #define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ +/* + * The following EDMA channels/slots are not being used by drivers (for + * example: Timer, GPIO, UART events etc) on dm646x, hence they are being + * reserved for codecs on the DSP side. + */ +static const s16 dm646x_dma_rsv_chans[][2] = { + /* (offset, number) */ + { 0, 4}, + {13, 3}, + {24, 4}, + {30, 2}, + {54, 3}, + {-1, -1} +}; + +static const s16 dm646x_dma_rsv_slots[][2] = { + /* (offset, number) */ + { 0, 4}, + {13, 3}, + {24, 4}, + {30, 2}, + {54, 3}, + {128, 384}, + {-1, -1} +}; + +static struct edma_rsv_info dm646x_edma_rsv[] = { + { + .rsv_chans = dm646x_dma_rsv_chans, + .rsv_slots = dm646x_dma_rsv_slots, + }, +}; + static __init void evm_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; @@ -732,6 +765,8 @@ static __init void evm_init(void) platform_device_register(&davinci_nand_device); + dm646x_init_edma(dm646x_edma_rsv); + if (HAS_ATA) davinci_init_ide(); diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c new file mode 100644 index 00000000000..fe2a9d9c8bb --- /dev/null +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -0,0 +1,174 @@ +/* + * Texas Instruments TNETV107X EVM Board Support + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/ratelimit.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <mach/irqs.h> +#include <mach/edma.h> +#include <mach/mux.h> +#include <mach/cp_intc.h> +#include <mach/tnetv107x.h> + +#define EVM_MMC_WP_GPIO 21 +#define EVM_MMC_CD_GPIO 24 + +static int initialize_gpio(int gpio, char *desc) +{ + int ret; + + ret = gpio_request(gpio, desc); + if (ret < 0) { + pr_err_ratelimited("cannot open %s gpio\n", desc); + return -ENOSYS; + } + gpio_direction_input(gpio); + return gpio; +} + +static int mmc_get_cd(int index) +{ + static int gpio; + + if (!gpio) + gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect"); + + if (gpio < 0) + return gpio; + + return gpio_get_value(gpio) ? 0 : 1; +} + +static int mmc_get_ro(int index) +{ + static int gpio; + + if (!gpio) + gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect"); + + if (gpio < 0) + return gpio; + + return gpio_get_value(gpio) ? 1 : 0; +} + +static struct davinci_mmc_config mmc_config = { + .get_cd = mmc_get_cd, + .get_ro = mmc_get_ro, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_1, +}; + +static const short sdio1_pins[] __initdata = { + TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1, + TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1, + TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1, + TNETV107X_GPIO21, TNETV107X_GPIO24, + -1 +}; + +static const short uart1_pins[] __initdata = { + TNETV107X_UART1_RD, TNETV107X_UART1_TD, + -1 +}; + +static struct mtd_partition nand_partitions[] = { + /* bootloader (U-Boot, etc) in first 12 sectors */ + { + .name = "bootloader", + .offset = 0, + .size = (12*SZ_128K), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_4M, + .mask_flags = 0, + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } +}; + +static struct davinci_nand_pdata nand_config = { + .mask_cle = 0x4000, + .mask_ale = 0x2000, + .parts = nand_partitions, + .nr_parts = ARRAY_SIZE(nand_partitions), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, + .ecc_bits = 1, +}; + +static struct davinci_uart_config serial_config __initconst = { + .enabled_uarts = BIT(1), +}; + +static struct tnetv107x_device_info evm_device_info __initconst = { + .serial_config = &serial_config, + .mmc_config[1] = &mmc_config, /* controller 1 */ + .nand_config[0] = &nand_config, /* chip select 0 */ +}; + +static __init void tnetv107x_evm_board_init(void) +{ + davinci_cfg_reg_list(sdio1_pins); + davinci_cfg_reg_list(uart1_pins); + + tnetv107x_devices_init(&evm_device_info); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init tnetv107x_evm_console_init(void) +{ + return add_preferred_console("ttyS", 0, "115200"); +} +console_initcall(tnetv107x_evm_console_init); +#endif + +MACHINE_START(TNETV107X, "TNETV107X EVM") + .phys_io = TNETV107X_IO_BASE, + .io_pg_offst = (TNETV107X_IO_VIRT >> 18) & 0xfffc, + .boot_params = (TNETV107X_DDR_BASE + 0x100), + .map_io = tnetv107x_init, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = tnetv107x_evm_board_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 23e9eda5a37..ec23ab47362 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -1024,7 +1024,6 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { [IRQ_DA8XX_EVTOUT4] = 7, [IRQ_DA8XX_EVTOUT5] = 7, [IRQ_DA8XX_EVTOUT6] = 7, - [IRQ_DA8XX_EVTOUT6] = 7, [IRQ_DA8XX_EVTOUT7] = 7, [IRQ_DA8XX_CCINT0] = 7, [IRQ_DA8XX_CCERRINT] = 7, @@ -1042,11 +1041,7 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = { [IRQ_DA8XX_TINT34_1] = 7, [IRQ_DA8XX_UARTINT0] = 7, [IRQ_DA8XX_KEYMGRINT] = 7, - [IRQ_DA8XX_SECINT] = 7, - [IRQ_DA8XX_SECKEYERR] = 7, [IRQ_DA830_MPUERR] = 7, - [IRQ_DA830_IOPUERR] = 7, - [IRQ_DA830_BOOTCFGERR] = 7, [IRQ_DA8XX_CHIPINT0] = 7, [IRQ_DA8XX_CHIPINT1] = 7, [IRQ_DA8XX_CHIPINT2] = 7, diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 6b8331bf8cf..68ed58a4825 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -643,7 +643,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA8XX_EVTOUT4] = 7, [IRQ_DA8XX_EVTOUT5] = 7, [IRQ_DA8XX_EVTOUT6] = 7, - [IRQ_DA8XX_EVTOUT6] = 7, [IRQ_DA8XX_EVTOUT7] = 7, [IRQ_DA8XX_CCINT0] = 7, [IRQ_DA8XX_CCERRINT] = 7, @@ -661,27 +660,7 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA8XX_TINT34_1] = 7, [IRQ_DA8XX_UARTINT0] = 7, [IRQ_DA8XX_KEYMGRINT] = 7, - [IRQ_DA8XX_SECINT] = 7, - [IRQ_DA8XX_SECKEYERR] = 7, [IRQ_DA850_MPUADDRERR0] = 7, - [IRQ_DA850_MPUPROTERR0] = 7, - [IRQ_DA850_IOPUADDRERR0] = 7, - [IRQ_DA850_IOPUPROTERR0] = 7, - [IRQ_DA850_IOPUADDRERR1] = 7, - [IRQ_DA850_IOPUPROTERR1] = 7, - [IRQ_DA850_IOPUADDRERR2] = 7, - [IRQ_DA850_IOPUPROTERR2] = 7, - [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7, - [IRQ_DA850_BOOTCFG_PROT_ERR] = 7, - [IRQ_DA850_MPUADDRERR1] = 7, - [IRQ_DA850_MPUPROTERR1] = 7, - [IRQ_DA850_IOPUADDRERR3] = 7, - [IRQ_DA850_IOPUPROTERR3] = 7, - [IRQ_DA850_IOPUADDRERR4] = 7, - [IRQ_DA850_IOPUPROTERR4] = 7, - [IRQ_DA850_IOPUADDRERR5] = 7, - [IRQ_DA850_IOPUPROTERR5] = 7, - [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7, [IRQ_DA8XX_CHIPINT0] = 7, [IRQ_DA8XX_CHIPINT1] = 7, [IRQ_DA8XX_CHIPINT2] = 7, @@ -722,8 +701,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA8XX_EHRPWM1] = 7, [IRQ_DA8XX_EHRPWM1TZ] = 7, [IRQ_DA850_SATAINT] = 7, - [IRQ_DA850_TINT12_2] = 7, - [IRQ_DA850_TINT34_2] = 7, [IRQ_DA850_TINTALL_2] = 7, [IRQ_DA8XX_ECAP0] = 7, [IRQ_DA8XX_ECAP1] = 7, @@ -751,8 +728,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA850_CCINT1] = 7, [IRQ_DA850_CCERRINT1] = 7, [IRQ_DA850_TCERRINT2] = 7, - [IRQ_DA850_TINT12_3] = 7, - [IRQ_DA850_TINT34_3] = 7, [IRQ_DA850_TINTALL_3] = 7, [IRQ_DA850_MCBSP0RINT] = 7, [IRQ_DA850_MCBSP0XINT] = 7, diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 8cda729be27..52bc7b1c6ca 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -111,19 +111,21 @@ static const s8 da850_queue_priority_mapping[][2] = { {-1, -1} }; -static struct edma_soc_info da830_edma_info[] = { - { - .n_channel = 32, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .n_cc = 1, - .queue_tc_mapping = da8xx_queue_tc_mapping, - .queue_priority_mapping = da8xx_queue_priority_mapping, - }, +static struct edma_soc_info da830_edma_cc0_info = { + .n_channel = 32, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .queue_tc_mapping = da8xx_queue_tc_mapping, + .queue_priority_mapping = da8xx_queue_priority_mapping, +}; + +static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { + &da830_edma_cc0_info, }; -static struct edma_soc_info da850_edma_info[] = { +static struct edma_soc_info da850_edma_cc_info[] = { { .n_channel = 32, .n_region = 4, @@ -144,6 +146,11 @@ static struct edma_soc_info da850_edma_info[] = { }, }; +static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { + &da850_edma_cc_info[0], + &da850_edma_cc_info[1], +}; + static struct resource da830_edma_resources[] = { { .name = "edma_cc0", @@ -248,18 +255,21 @@ static struct platform_device da850_edma_device = { .resource = da850_edma_resources, }; -int __init da8xx_register_edma(void) +int __init da830_register_edma(struct edma_rsv_info *rsv) { - struct platform_device *pdev; + da830_edma_cc0_info.rsv = rsv; - if (cpu_is_davinci_da830()) - pdev = &da830_edma_device; - else if (cpu_is_davinci_da850()) - pdev = &da850_edma_device; - else - return -ENODEV; + return platform_device_register(&da830_edma_device); +} - return platform_device_register(pdev); +int __init da850_register_edma(struct edma_rsv_info *rsv[2]) +{ + if (rsv) { + da850_edma_cc_info[0].rsv = rsv[0]; + da850_edma_cc_info[1].rsv = rsv[1]; + } + + return platform_device_register(&da850_edma_device); } static struct resource da8xx_i2c_resources0[] = { diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c new file mode 100644 index 00000000000..2718a3a90df --- /dev/null +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -0,0 +1,320 @@ +/* + * Texas Instruments TNETV107X SoC devices + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/clk.h> +#include <linux/slab.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/edma.h> +#include <mach/tnetv107x.h> + +#include "clock.h" + +/* Base addresses for on-chip devices */ +#define TNETV107X_TPCC_BASE 0x01c00000 +#define TNETV107X_TPTC0_BASE 0x01c10000 +#define TNETV107X_TPTC1_BASE 0x01c10400 +#define TNETV107X_WDOG_BASE 0x08086700 +#define TNETV107X_SDIO0_BASE 0x08088700 +#define TNETV107X_SDIO1_BASE 0x08088800 +#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 +#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 + +/* TNETV107X specific EDMA3 information */ +#define EDMA_TNETV107X_NUM_DMACH 64 +#define EDMA_TNETV107X_NUM_TCC 64 +#define EDMA_TNETV107X_NUM_PARAMENTRY 128 +#define EDMA_TNETV107X_NUM_EVQUE 2 +#define EDMA_TNETV107X_NUM_TC 2 +#define EDMA_TNETV107X_CHMAP_EXIST 0 +#define EDMA_TNETV107X_NUM_REGIONS 4 +#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u +#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu + +#define TNETV107X_DMACH_SDIO0_RX 26 +#define TNETV107X_DMACH_SDIO0_TX 27 +#define TNETV107X_DMACH_SDIO1_RX 28 +#define TNETV107X_DMACH_SDIO1_TX 29 + +static const s8 edma_tc_mapping[][2] = { + /* event queue no TC no */ + { 0, 0 }, + { 1, 1 }, + { -1, -1 } +}; + +static const s8 edma_priority_mapping[][2] = { + /* event queue no Prio */ + { 0, 3 }, + { 1, 7 }, + { -1, -1 } +}; + +static struct edma_soc_info edma_cc0_info = { + .n_channel = EDMA_TNETV107X_NUM_DMACH, + .n_region = EDMA_TNETV107X_NUM_REGIONS, + .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY, + .n_tc = EDMA_TNETV107X_NUM_TC, + .n_cc = 1, + .queue_tc_mapping = edma_tc_mapping, + .queue_priority_mapping = edma_priority_mapping, +}; + +static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = { + &edma_cc0_info, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc0", + .start = TNETV107X_TPCC_BASE, + .end = TNETV107X_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = TNETV107X_TPTC0_BASE, + .end = TNETV107X_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = TNETV107X_TPTC1_BASE, + .end = TNETV107X_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_TNETV107X_TPCC, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_TNETV107X_TPCC_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device edma_device = { + .name = "edma", + .id = -1, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, + .dev.platform_data = tnetv107x_edma_info, +}; + +static struct plat_serial8250_port serial_data[] = { + { + .mapbase = TNETV107X_UART0_BASE, + .irq = IRQ_TNETV107X_UART0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_FIXED_TYPE | UPF_IOREMAP, + .type = PORT_AR7, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .mapbase = TNETV107X_UART1_BASE, + .irq = IRQ_TNETV107X_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_FIXED_TYPE | UPF_IOREMAP, + .type = PORT_AR7, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .mapbase = TNETV107X_UART2_BASE, + .irq = IRQ_TNETV107X_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_FIXED_TYPE | UPF_IOREMAP, + .type = PORT_AR7, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .flags = 0, + }, +}; + +struct platform_device tnetv107x_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = serial_data, +}; + +static struct resource mmc0_resources[] = { + { /* Memory mapped registers */ + .start = TNETV107X_SDIO0_BASE, + .end = TNETV107X_SDIO0_BASE + 0x0ff, + .flags = IORESOURCE_MEM + }, + { /* MMC interrupt */ + .start = IRQ_TNETV107X_MMC0, + .flags = IORESOURCE_IRQ + }, + { /* SDIO interrupt */ + .start = IRQ_TNETV107X_SDIO0, + .flags = IORESOURCE_IRQ + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX), + .flags = IORESOURCE_DMA + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX), + .flags = IORESOURCE_DMA + }, +}; + +static struct resource mmc1_resources[] = { + { /* Memory mapped registers */ + .start = TNETV107X_SDIO1_BASE, + .end = TNETV107X_SDIO1_BASE + 0x0ff, + .flags = IORESOURCE_MEM + }, + { /* MMC interrupt */ + .start = IRQ_TNETV107X_MMC1, + .flags = IORESOURCE_IRQ + }, + { /* SDIO interrupt */ + .start = IRQ_TNETV107X_SDIO1, + .flags = IORESOURCE_IRQ + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX), + .flags = IORESOURCE_DMA + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX), + .flags = IORESOURCE_DMA + }, +}; + +static u64 mmc0_dma_mask = DMA_BIT_MASK(32); +static u64 mmc1_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device mmc_devices[2] = { + { + .name = "davinci_mmc", + .id = 0, + .dev = { + .dma_mask = &mmc0_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mmc0_resources), + .resource = mmc0_resources + }, + { + .name = "davinci_mmc", + .id = 1, + .dev = { + .dma_mask = &mmc1_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mmc1_resources), + .resource = mmc1_resources + }, +}; + +static const u32 emif_windows[] = { + TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE, + TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE, +}; + +static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M }; + +static struct resource wdt_resources[] = { + { + .start = TNETV107X_WDOG_BASE, + .end = TNETV107X_WDOG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device tnetv107x_wdt_device = { + .name = "tnetv107x_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static int __init nand_init(int chipsel, struct davinci_nand_pdata *data) +{ + struct resource res[2]; + struct platform_device *pdev; + u32 range; + int ret; + + /* Figure out the resource range from the ale/cle masks */ + range = max(data->mask_cle, data->mask_ale); + range = PAGE_ALIGN(range + 4) - 1; + + if (range >= emif_window_sizes[chipsel]) + return -EINVAL; + + pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); + if (!pdev) + return -ENOMEM; + + pdev->name = "davinci_nand"; + pdev->id = chipsel; + pdev->dev.platform_data = data; + + memset(res, 0, sizeof(res)); + + res[0].start = emif_windows[chipsel]; + res[0].end = res[0].start + range; + res[0].flags = IORESOURCE_MEM; + + res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE; + res[1].end = res[1].start + SZ_4K - 1; + res[1].flags = IORESOURCE_MEM; + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret < 0) { + kfree(pdev); + return ret; + } + + return platform_device_register(pdev); +} + +void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) +{ + int i; + + platform_device_register(&edma_device); + platform_device_register(&tnetv107x_wdt_device); + + if (info->serial_config) + davinci_serial_init(info->serial_config); + + for (i = 0; i < 2; i++) + if (info->mmc_config[i]) { + mmc_devices[i].dev.platform_data = info->mmc_config[i]; + platform_device_register(&mmc_devices[i]); + } + + for (i = 0; i < 4; i++) + if (info->nand_config[i]) + nand_init(i, info->nand_config[i]); +} diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 383478116ef..3d996b659ff 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -591,16 +591,18 @@ queue_priority_mapping[][2] = { {-1, -1}, }; -static struct edma_soc_info dm355_edma_info[] = { - { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .n_cc = 1, - .queue_tc_mapping = queue_tc_mapping, - .queue_priority_mapping = queue_priority_mapping, - }, +static struct edma_soc_info edma_cc0_info = { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, +}; + +static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = { + &edma_cc0_info, }; static struct resource edma_resources[] = { diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index a146849d78f..6b6f4c64370 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -822,17 +822,19 @@ dm365_queue_priority_mapping[][2] = { {-1, -1}, }; -static struct edma_soc_info dm365_edma_info[] = { - { - .n_channel = 64, - .n_region = 4, - .n_slot = 256, - .n_tc = 4, - .n_cc = 1, - .queue_tc_mapping = dm365_queue_tc_mapping, - .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, - }, +static struct edma_soc_info edma_cc0_info = { + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm365_queue_tc_mapping, + .queue_priority_mapping = dm365_queue_priority_mapping, + .default_queue = EVENTQ_3, +}; + +static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { + &edma_cc0_info, }; static struct resource edma_resources[] = { @@ -1020,6 +1022,8 @@ static struct davinci_timer_info dm365_timer_info = { .clocksource_id = T0_TOP, }; +#define DM365_UART1_BASE (IO_PHYS + 0x106000) + static struct plat_serial8250_port dm365_serial_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, @@ -1030,7 +1034,7 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { .regshift = 2, }, { - .mapbase = DAVINCI_UART1_BASE, + .mapbase = DM365_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 7ad15208b84..40fec315c99 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -492,16 +492,18 @@ queue_priority_mapping[][2] = { {-1, -1}, }; -static struct edma_soc_info dm644x_edma_info[] = { - { - .n_channel = 64, - .n_region = 4, - .n_slot = 128, - .n_tc = 2, - .n_cc = 1, - .queue_tc_mapping = queue_tc_mapping, - .queue_priority_mapping = queue_priority_mapping, - }, +static struct edma_soc_info edma_cc0_info = { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .n_cc = 1, + .queue_tc_mapping = queue_tc_mapping, + .queue_priority_mapping = queue_priority_mapping, +}; + +static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = { + &edma_cc0_info, }; static struct resource edma_resources[] = { diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 94045656cff..e4a3df1872a 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -529,16 +529,18 @@ dm646x_queue_priority_mapping[][2] = { {-1, -1}, }; -static struct edma_soc_info dm646x_edma_info[] = { - { - .n_channel = 64, - .n_region = 6, /* 0-1, 4-7 */ - .n_slot = 512, - .n_tc = 4, - .n_cc = 1, - .queue_tc_mapping = dm646x_queue_tc_mapping, - .queue_priority_mapping = dm646x_queue_priority_mapping, - }, +static struct edma_soc_info edma_cc0_info = { + .n_channel = 64, + .n_region = 6, /* 0-1, 4-7 */ + .n_slot = 512, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm646x_queue_tc_mapping, + .queue_priority_mapping = dm646x_queue_priority_mapping, +}; + +static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = { + &edma_cc0_info, }; static struct resource edma_resources[] = { @@ -877,6 +879,13 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config, platform_device_register(&vpif_capture_dev); } +int __init dm646x_init_edma(struct edma_rsv_info *rsv) +{ + edma_cc0_info.rsv = rsv; + + return platform_device_register(&dm646x_edma_device); +} + void __init dm646x_init(void) { dm646x_board_setup_refclk(&ref_clk); @@ -888,7 +897,6 @@ static int __init dm646x_init_devices(void) if (!cpu_is_davinci_dm646x()) return 0; - platform_device_register(&dm646x_edma_device); platform_device_register(&dm646x_emac_device); return 0; } diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index d33827aadda..2ede598b77d 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -99,8 +99,6 @@ #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_MAX_CC 2 - /*****************************************************************************/ @@ -207,6 +205,18 @@ static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); } +static inline void set_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + set_bit(offset + (len - 1), p); +} + +static inline void clear_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); +} + /*****************************************************************************/ /* actual number of DMA channels and slots on this silicon */ @@ -1376,11 +1386,13 @@ EXPORT_SYMBOL(edma_clear_event); static int __init edma_probe(struct platform_device *pdev) { - struct edma_soc_info *info = pdev->dev.platform_data; + struct edma_soc_info **info = pdev->dev.platform_data; const s8 (*queue_priority_mapping)[2]; const s8 (*queue_tc_mapping)[2]; - int i, j, found = 0; + int i, j, off, ln, found = 0; int status = -1; + const s16 (*rsv_chans)[2]; + const s16 (*rsv_slots)[2]; int irq[EDMA_MAX_CC] = {0, 0}; int err_irq[EDMA_MAX_CC] = {0, 0}; struct resource *r[EDMA_MAX_CC] = {NULL}; @@ -1395,7 +1407,7 @@ static int __init edma_probe(struct platform_device *pdev) sprintf(res_name, "edma_cc%d", j); r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name); - if (!r[j]) { + if (!r[j] || !info[j]) { if (found) break; else @@ -1426,13 +1438,14 @@ static int __init edma_probe(struct platform_device *pdev) } memset(edma_cc[j], 0, sizeof(struct edma)); - edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel, + edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, EDMA_MAX_DMACH); - edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot, + edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot, EDMA_MAX_PARAMENTRY); - edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC); + edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc, + EDMA_MAX_CC); - edma_cc[j]->default_queue = info[j].default_queue; + edma_cc[j]->default_queue = info[j]->default_queue; if (!edma_cc[j]->default_queue) edma_cc[j]->default_queue = EVENTQ_1; @@ -1447,6 +1460,31 @@ static int __init edma_probe(struct platform_device *pdev) memset(edma_cc[j]->edma_unused, 0xff, sizeof(edma_cc[j]->edma_unused)); + if (info[j]->rsv) { + + /* Clear the reserved channels in unused list */ + rsv_chans = info[j]->rsv->rsv_chans; + if (rsv_chans) { + for (i = 0; rsv_chans[i][0] != -1; i++) { + off = rsv_chans[i][0]; + ln = rsv_chans[i][1]; + clear_bits(off, ln, + edma_cc[j]->edma_unused); + } + } + + /* Set the reserved slots in inuse list */ + rsv_slots = info[j]->rsv->rsv_slots; + if (rsv_slots) { + for (i = 0; rsv_slots[i][0] != -1; i++) { + off = rsv_slots[i][0]; + ln = rsv_slots[i][1]; + set_bits(off, ln, + edma_cc[j]->edma_inuse); + } + } + } + sprintf(irq_name, "edma%d", j); irq[j] = platform_get_irq_byname(pdev, irq_name); edma_cc[j]->irq_res_start = irq[j]; @@ -1476,8 +1514,8 @@ static int __init edma_probe(struct platform_device *pdev) for (i = 0; i < edma_cc[j]->num_channels; i++) map_dmach_queue(j, i, EVENTQ_1); - queue_tc_mapping = info[j].queue_tc_mapping; - queue_priority_mapping = info[j].queue_priority_mapping; + queue_tc_mapping = info[j]->queue_tc_mapping; + queue_priority_mapping = info[j]->queue_priority_mapping; /* Event queue to TC mapping */ for (i = 0; queue_tc_mapping[i][0] != -1; i++) @@ -1496,7 +1534,7 @@ static int __init edma_probe(struct platform_device *pdev) if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) map_dmach_param(j); - for (i = 0; i < info[j].n_region; i++) { + for (i = 0; i < info[j]->n_region; i++) { edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); edma_write_array(j, EDMA_QRAE, i, 0x0); diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c new file mode 100644 index 00000000000..d10298620e2 --- /dev/null +++ b/arch/arm/mach-davinci/gpio-tnetv107x.c @@ -0,0 +1,205 @@ +/* + * Texas Instruments TNETV107X GPIO Controller + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> + +#include <mach/common.h> +#include <mach/tnetv107x.h> + +struct tnetv107x_gpio_regs { + u32 idver; + u32 data_in[3]; + u32 data_out[3]; + u32 direction[3]; + u32 enable[3]; +}; + +#define gpio_reg_index(gpio) ((gpio) >> 5) +#define gpio_reg_bit(gpio) BIT((gpio) & 0x1f) + +#define gpio_reg_rmw(reg, mask, val) \ + __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg)) + +#define gpio_reg_set_bit(reg, gpio) \ + gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio)) + +#define gpio_reg_clear_bit(reg, gpio) \ + gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0) + +#define gpio_reg_get_bit(reg, gpio) \ + (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio)) + +#define chip2controller(chip) \ + container_of(chip, struct davinci_gpio_controller, chip) + +#define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32) + +static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS]; + +static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + gpio_reg_set_bit(®s->enable, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); + + return 0; +} + +static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + gpio_reg_clear_bit(®s->enable, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); +} + +static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + gpio_reg_set_bit(®s->direction, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); + + return 0; +} + +static int tnetv107x_gpio_dir_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + if (value) + gpio_reg_set_bit(®s->data_out, gpio); + else + gpio_reg_clear_bit(®s->data_out, gpio); + + gpio_reg_clear_bit(®s->direction, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); + + return 0; +} + +static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + int ret; + + ret = gpio_reg_get_bit(®s->data_in, gpio); + + return ret ? 1 : 0; +} + +static void tnetv107x_gpio_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + if (value) + gpio_reg_set_bit(®s->data_out, gpio); + else + gpio_reg_clear_bit(®s->data_out, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); +} + +static int __init tnetv107x_gpio_setup(void) +{ + int i, base; + unsigned ngpio; + struct davinci_soc_info *soc_info = &davinci_soc_info; + struct tnetv107x_gpio_regs *regs; + struct davinci_gpio_controller *ctlr; + + if (soc_info->gpio_type != GPIO_TYPE_TNETV107X) + return 0; + + ngpio = soc_info->gpio_num; + if (ngpio == 0) { + pr_err("GPIO setup: how many GPIOs?\n"); + return -EINVAL; + } + + if (WARN_ON(TNETV107X_N_GPIO < ngpio)) + ngpio = TNETV107X_N_GPIO; + + regs = ioremap(soc_info->gpio_base, SZ_4K); + if (WARN_ON(!regs)) + return -EINVAL; + + for (i = 0, base = 0; base < ngpio; i++, base += 32) { + ctlr = &chips[i]; + + ctlr->chip.label = "tnetv107x"; + ctlr->chip.can_sleep = 0; + ctlr->chip.base = base; + ctlr->chip.ngpio = ngpio - base; + if (ctlr->chip.ngpio > 32) + ctlr->chip.ngpio = 32; + + ctlr->chip.request = tnetv107x_gpio_request; + ctlr->chip.free = tnetv107x_gpio_free; + ctlr->chip.direction_input = tnetv107x_gpio_dir_in; + ctlr->chip.get = tnetv107x_gpio_get; + ctlr->chip.direction_output = tnetv107x_gpio_dir_out; + ctlr->chip.set = tnetv107x_gpio_set; + + spin_lock_init(&ctlr->lock); + + ctlr->regs = regs; + ctlr->set_data = ®s->data_out[i]; + ctlr->clr_data = ®s->data_out[i]; + ctlr->in_data = ®s->data_in[i]; + + gpiochip_add(&ctlr->chip); + } + + soc_info->gpio_ctlrs = chips; + soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); + return 0; +} +pure_initcall(tnetv107x_gpio_setup); diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index 834725f1e81..9aa240909a2 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -52,7 +52,8 @@ struct snd_platform_data { u32 tx_dma_offset; u32 rx_dma_offset; - enum dma_event_q eventq_no; /* event queue number */ + enum dma_event_q asp_chan_q; /* event queue number for ASP channel */ + enum dma_event_q ram_chan_q; /* event queue number for RAM channel */ unsigned int codec_fmt; /* * Allowing this is more efficient and eliminates left and right swaps @@ -63,6 +64,49 @@ struct snd_platform_data { unsigned sram_size_playback; unsigned sram_size_capture; + /* + * If McBSP peripheral gets the clock from an external pin, + * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR + * and MCBSP_CLKS. + * Depending on different hardware connections it is possible + * to use this setting to change the behaviour of McBSP + * driver. The dm365_clk_input_pin enum is available for dm365 + */ + int clk_input_pin; + + /* + * This flag works when both clock and FS are outputs for the cpu + * and makes clock more accurate (FS is not symmetrical and the + * clock is very fast. + * The clock becoming faster is named + * i2s continuous serial clock (I2S_SCK) and it is an externally + * visible bit clock. + * + * first line : WordSelect + * second line : ContinuousSerialClock + * third line: SerialData + * + * SYMMETRICAL APPROACH: + * _______________________ LEFT + * _| RIGHT |______________________| + * _ _ _ _ _ _ _ _ + * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ + * _ _ _ _ _ _ _ _ + * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ + * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ + * + * ACCURATE CLOCK APPROACH: + * ______________ LEFT + * _| RIGHT |_______________________________| + * _ _ _ _ _ _ _ _ _ + * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | + * _ _ _ _ dummy cycles + * _/ \_ ... _/ \_/ \_ ... _/ \__________________ + * \_/ \_/ \_/ \_/ + * + */ + bool i2s_accurate_sck; + /* McASP specific fields */ int tdm_slots; u8 op_mode; @@ -78,6 +122,11 @@ enum { MCASP_VERSION_2, /* DA8xx/OMAPL1x */ }; +enum dm365_clk_input_pin { + MCBSP_CLKR = 0, /* DM365 */ + MCBSP_CLKS, +}; + #define INACTIVE_MODE 0 #define TX_MODE 1 #define RX_MODE 2 diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 1b31a9aa8fb..3c07059f526 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -67,7 +67,8 @@ extern void __iomem *da8xx_syscfg1_base; void __init da830_init(void); void __init da850_init(void); -int da8xx_register_edma(void); +int da830_register_edma(struct edma_rsv_info *rsv); +int da850_register_edma(struct edma_rsv_info *rsv[2]); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_watchdog(void); int da8xx_register_usb20(unsigned mA, unsigned potpgt); diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 3cd93a801d9..f761dfdb868 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -17,22 +17,50 @@ */ #include <linux/serial_reg.h> + +#include <asm/memory.h> + +#include <mach/serial.h> + #define UART_SHIFT 2 + .pushsection .data +davinci_uart_phys: .word 0 +davinci_uart_virt: .word 0 + .popsection + .macro addruart, rx, tmp + + /* Use davinci_uart_phys/virt if already configured */ +10: mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =__virt_to_phys(davinci_uart_phys) + ldrne \rx, =davinci_uart_virt + ldr \rx, [\rx] + cmp \rx, #0 @ is port configured? + bne 99f @ already configured + mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - moveq \rx, #0x01000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base -#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) -#error Cannot enable DaVinci and DA8XX platforms concurrently -#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ - defined(CONFIG_MACH_DAVINCI_DA850_EVM) - orr \rx, \rx, #0x00d00000 @ physical base address - orr \rx, \rx, #0x0000d000 @ of UART 2 -#else - orr \rx, \rx, #0x00c20000 @ UART 0 -#endif + + /* Copy uart phys address from decompressor uart info */ + ldreq \tmp, =__virt_to_phys(davinci_uart_phys) + ldrne \tmp, =davinci_uart_phys + ldreq \rx, =DAVINCI_UART_INFO + ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO) + ldr \rx, [\rx, #0] + str \rx, [\tmp] + + /* Copy uart virt address from decompressor uart info */ + ldreq \tmp, =__virt_to_phys(davinci_uart_virt) + ldrne \tmp, =davinci_uart_virt + ldreq \rx, =DAVINCI_UART_INFO + ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO) + ldr \rx, [\rx, #4] + str \rx, [\tmp] + + b 10b +99: .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index add6f794a36..0a27ee9a70e 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -32,6 +32,7 @@ void __init dm646x_init(void); void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); void __init dm646x_board_setup_refclk(struct clk *clk); +int __init dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index ced3092af5b..dc10ef6cf57 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -230,6 +230,8 @@ enum sync_dimension { #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 +#define EDMA_MAX_CC 2 + /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, void (*callback)(unsigned channel, u16 ch_status, void *data), @@ -269,6 +271,12 @@ void edma_clear_event(unsigned channel); void edma_pause(unsigned channel); void edma_resume(unsigned channel); +struct edma_rsv_info { + + const s16 (*rsv_chans)[2]; + const s16 (*rsv_slots)[2]; +}; + /* platform_data for EDMA driver */ struct edma_soc_info { @@ -280,6 +288,9 @@ struct edma_soc_info { unsigned n_cc; enum dma_event_q default_queue; + /* Resource reservation for other cores */ + struct edma_rsv_info *rsv; + const s8 (*queue_tc_mapping)[2]; const s8 (*queue_priority_mapping)[2]; }; diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 504cc180a60..fbece126c2b 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -25,6 +25,7 @@ enum davinci_gpio_type { GPIO_TYPE_DAVINCI = 0, + GPIO_TYPE_TNETV107X, }; /* @@ -87,9 +88,13 @@ static inline u32 __gpio_mask(unsigned gpio) return 1 << (gpio % 32); } -/* The get/set/clear functions will inline when called with constant +/* + * The get/set/clear functions will inline when called with constant * parameters referencing built-in GPIOs, for low-overhead bitbanging. * + * gpio_set_value() will inline only on traditional Davinci style controllers + * with distinct set/clear registers. + * * Otherwise, calls with variable parameters or referencing external * GPIOs (e.g. on GPIO expander chips) use outlined functions. */ @@ -100,12 +105,15 @@ static inline void gpio_set_value(unsigned gpio, int value) u32 mask; ctlr = __gpio_to_controller(gpio); - mask = __gpio_mask(gpio); - if (value) - __raw_writel(mask, ctlr->set_data); - else - __raw_writel(mask, ctlr->clr_data); - return; + + if (ctlr->set_data != ctlr->clr_data) { + mask = __gpio_mask(gpio); + if (value) + __raw_writel(mask, ctlr->set_data); + else + __raw_writel(mask, ctlr->clr_data); + return; + } } __gpio_set_value(gpio, value); diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index f6c4f34909a..8051110b8ac 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -11,8 +11,19 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H +#include <asm/memory.h> + #include <mach/hardware.h> +/* + * Stolen area that contains debug uart physical and virtual addresses. These + * addresses are filled in by the uncompress.h code, and are used by the debug + * macros in debug-macro.S. + * + * This area sits just below the page tables (see arch/arm/kernel/head.S). + */ +#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8) + #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) @@ -21,16 +32,26 @@ #define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) #define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) +#define TNETV107X_UART0_BASE 0x08108100 +#define TNETV107X_UART1_BASE 0x08088400 +#define TNETV107X_UART2_BASE 0x08108300 + +#define TNETV107X_UART0_VIRT IOMEM(0xfee08100) +#define TNETV107X_UART1_VIRT IOMEM(0xfed88400) +#define TNETV107X_UART2_VIRT IOMEM(0xfee08300) + /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 #define UART_DM646X_SCR_TX_WATERMARK 0x08 +#ifndef __ASSEMBLY__ struct davinci_uart_config { /* Bit field of UARTs present; bit 0 --> UART1 */ unsigned int enabled_uarts; }; extern int davinci_serial_init(struct davinci_uart_config *); +#endif #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h new file mode 100644 index 00000000000..c7206473312 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -0,0 +1,55 @@ +/* + * Texas Instruments TNETV107X SoC Specific Defines + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H +#define __ASM_ARCH_DAVINCI_TNETV107X_H + +#include <asm/sizes.h> + +#define TNETV107X_DDR_BASE 0x80000000 + +/* + * Fixed mapping for early init starts here. If low-level debug is enabled, + * this area also gets mapped via io_pg_offset and io_phys by the boot code. + * To fit in with the io_pg_offset calculation, the io base address selected + * here _must_ be a multiple of 2^20. + */ +#define TNETV107X_IO_BASE 0x08000000 +#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M) + +#define TNETV107X_N_GPIO 65 + +#ifndef __ASSEMBLY__ + +#include <linux/serial_8250.h> +#include <mach/mmc.h> +#include <mach/nand.h> +#include <mach/serial.h> + +struct tnetv107x_device_info { + struct davinci_uart_config *serial_config; + struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ + struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ +}; + +extern struct platform_device tnetv107x_wdt_device; +extern struct platform_device tnetv107x_serial_device; + +extern void __init tnetv107x_init(void); +extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *); +extern void __init tnetv107x_irq_init(void); + +#endif + +#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */ diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 33796b4db17..15a6192ad6e 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -1,8 +1,17 @@ /* * Serial port stubs for kernel decompress status messages * - * Author: Anant Gole - * (C) Copyright (C) 2006, Texas Instruments, Inc + * Initially based on: + * arch/arm/plat-omap/include/mach/uncompress.h + * + * Original copyrights follow. + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Rewritten by: + * Author: <source@mvista.com> + * 2004 (c) MontaVista Software, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -11,30 +20,17 @@ #include <linux/types.h> #include <linux/serial_reg.h> -#include <mach/serial.h> #include <asm/mach-types.h> -extern unsigned int __machine_arch_type; +#include <mach/serial.h> static u32 *uart; - -static u32 *get_uart_base(void) -{ - if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM || - __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) - return (u32 *)DA8XX_UART2_BASE; - else - return (u32 *)DAVINCI_UART0_BASE; -} +static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); /* PORT_16C550A, in polled non-fifo mode */ - static void putc(char c) { - if (!uart) - uart = get_uart_base(); - while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); uart[UART_TX] = c; @@ -42,12 +38,61 @@ static void putc(char c) static inline void flush(void) { - if (!uart) - uart = get_uart_base(); - while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); } -#define arch_decomp_setup() +static inline void set_uart_info(u32 phys, void * __iomem virt) +{ + uart = (u32 *)phys; + uart_info[0] = phys; + uart_info[1] = (u32)virt; +} + +#define _DEBUG_LL_ENTRY(machine, phys, virt) \ + if (machine_is_##machine()) { \ + set_uart_info(phys, virt); \ + break; \ + } + +#define DEBUG_LL_DAVINCI(machine, port) \ + _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE, \ + IO_ADDRESS(DAVINCI_UART##port##_BASE)) + +#define DEBUG_LL_DA8XX(machine, port) \ + _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE, \ + IO_ADDRESS(DA8XX_UART##port##_BASE)) + +#define DEBUG_LL_TNETV107X(machine, port) \ + _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE, \ + TNETV107X_UART##port##_VIRT) + +static inline void __arch_decomp_setup(unsigned long arch_id) +{ + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* Davinci boards */ + DEBUG_LL_DAVINCI(davinci_evm, 0); + DEBUG_LL_DAVINCI(sffsdr, 0); + DEBUG_LL_DAVINCI(neuros_osd2, 0); + DEBUG_LL_DAVINCI(davinci_dm355_evm, 0); + DEBUG_LL_DAVINCI(dm355_leopard, 0); + DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0); + DEBUG_LL_DAVINCI(davinci_dm365_evm, 0); + + /* DA8xx boards */ + DEBUG_LL_DA8XX(davinci_da830_evm, 2); + DEBUG_LL_DA8XX(davinci_da850_evm, 2); + + /* TNETV107x boards */ + DEBUG_LL_TNETV107X(tnetv107x, 1); + } while (0); +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) #define arch_decomp_wdog() diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c new file mode 100644 index 00000000000..864e60482c5 --- /dev/null +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -0,0 +1,753 @@ +/* + * Texas Instruments TNETV107X SoC Support + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/common.h> +#include <mach/time.h> +#include <mach/cputype.h> +#include <mach/psc.h> +#include <mach/cp_intc.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <mach/hardware.h> +#include <mach/tnetv107x.h> + +#include "clock.h" +#include "mux.h" + +/* Base addresses for on-chip devices */ +#define TNETV107X_INTC_BASE 0x03000000 +#define TNETV107X_TIMER0_BASE 0x08086500 +#define TNETV107X_TIMER1_BASE 0x08086600 +#define TNETV107X_CHIP_CFG_BASE 0x08087000 +#define TNETV107X_GPIO_BASE 0x08088000 +#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000 +#define TNETV107X_PSC_BASE 0x0808b000 + +/* Reference clock frequencies */ +#define OSC_FREQ_ONCHIP (24000 * 1000) +#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000) +#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000) +#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000) + +#define N_PLLS 3 + +/* Clock Control Registers */ +struct clk_ctrl_regs { + u32 pll_bypass; + u32 _reserved0; + u32 gem_lrst; + u32 _reserved1; + u32 pll_unlock_stat; + u32 sys_unlock; + u32 eth_unlock; + u32 tdm_unlock; +}; + +/* SSPLL Registers */ +struct sspll_regs { + u32 modes; + u32 post_div; + u32 pre_div; + u32 mult_factor; + u32 divider_range; + u32 bw_divider; + u32 spr_amount; + u32 spr_rate_div; + u32 diag; +}; + +/* Watchdog Timer Registers */ +struct wdt_regs { + u32 kick_lock; + u32 kick; + u32 change_lock; + u32 change ; + u32 disable_lock; + u32 disable; + u32 prescale_lock; + u32 prescale; +}; + +static struct clk_ctrl_regs __iomem *clk_ctrl_regs; + +static struct sspll_regs __iomem *sspll_regs[N_PLLS]; +static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 }; + +/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */ +static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) }; + +/* offchip (external) reference clock frequencies */ +static u32 pll_ext_freq[] = { + OSC_FREQ_OFFCHIP_SYS, + OSC_FREQ_OFFCHIP_TDM, + OSC_FREQ_OFFCHIP_ETH +}; + +/* PSC control registers */ +static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE }; + +/* Host map for interrupt controller */ +static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; + +static unsigned long clk_sspll_recalc(struct clk *clk); + +/* Level 1 - the PLLs */ +#define define_pll_clk(cname, pll, divmask, base) \ + static struct pll_data pll_##cname##_data = { \ + .num = pll, \ + .div_ratio_mask = divmask, \ + .phys_base = base + \ + TNETV107X_CLOCK_CONTROL_BASE, \ + }; \ + static struct clk pll_##cname##_clk = { \ + .name = "pll_" #cname "_clk", \ + .pll_data = &pll_##cname##_data, \ + .flags = CLK_PLL, \ + .recalc = clk_sspll_recalc, \ + } + +define_pll_clk(sys, 0, 0x1ff, 0x600); +define_pll_clk(tdm, 1, 0x0ff, 0x200); +define_pll_clk(eth, 2, 0x0ff, 0x400); + +/* Level 2 - divided outputs from the PLLs */ +#define define_pll_div_clk(pll, cname, div) \ + static struct clk pll##_##cname##_clk = { \ + .name = #pll "_" #cname "_clk",\ + .parent = &pll_##pll##_clk, \ + .flags = CLK_PLL, \ + .div_reg = PLLDIV##div, \ + } + +define_pll_div_clk(sys, arm1176, 1); +define_pll_div_clk(sys, dsp, 2); +define_pll_div_clk(sys, ddr, 3); +define_pll_div_clk(sys, full, 4); +define_pll_div_clk(sys, lcd, 5); +define_pll_div_clk(sys, vlynq_ref, 6); +define_pll_div_clk(sys, tsc, 7); +define_pll_div_clk(sys, half, 8); + +define_pll_div_clk(eth, 5mhz, 1); +define_pll_div_clk(eth, 50mhz, 2); +define_pll_div_clk(eth, 125mhz, 3); +define_pll_div_clk(eth, 250mhz, 4); +define_pll_div_clk(eth, 25mhz, 5); + +define_pll_div_clk(tdm, 0, 1); +define_pll_div_clk(tdm, extra, 2); +define_pll_div_clk(tdm, 1, 3); + + +/* Level 3 - LPSC gated clocks */ +#define __lpsc_clk(cname, _parent, mod, flg) \ + static struct clk clk_##cname = { \ + .name = #cname, \ + .parent = &_parent, \ + .lpsc = TNETV107X_LPSC_##mod,\ + .flags = flg, \ + } + +#define lpsc_clk_enabled(cname, parent, mod) \ + __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED) + +#define lpsc_clk(cname, parent, mod) \ + __lpsc_clk(cname, parent, mod, 0) + +lpsc_clk_enabled(arm, sys_arm1176_clk, ARM); +lpsc_clk_enabled(gem, sys_dsp_clk, GEM); +lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY); +lpsc_clk_enabled(tpcc, sys_full_clk, TPCC); +lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0); +lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1); +lpsc_clk_enabled(ram, sys_full_clk, RAM); +lpsc_clk_enabled(aemif, sys_full_clk, AEMIF); +lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG); +lpsc_clk_enabled(rom, sys_half_clk, ROM); +lpsc_clk_enabled(secctl, sys_half_clk, SECCTL); +lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR); +lpsc_clk_enabled(gpio, sys_half_clk, GPIO); +lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS); +lpsc_clk_enabled(system, sys_half_clk, SYSTEM); +lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); +lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); +lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); + +lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); +lpsc_clk(ethss, eth_125mhz_clk, ETHSS); +lpsc_clk(tsc, sys_tsc_clk, TSC); +lpsc_clk(uart0, sys_half_clk, UART0); +lpsc_clk(uart1, sys_half_clk, UART1); +lpsc_clk(uart2, sys_half_clk, UART2); +lpsc_clk(pktsec, sys_half_clk, PKTSEC); +lpsc_clk(keypad, sys_half_clk, KEYPAD); +lpsc_clk(mdio, sys_half_clk, MDIO); +lpsc_clk(sdio0, sys_half_clk, SDIO0); +lpsc_clk(sdio1, sys_half_clk, SDIO1); +lpsc_clk(timer0, sys_half_clk, TIMER0); +lpsc_clk(timer1, sys_half_clk, TIMER1); +lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); +lpsc_clk(ssp, sys_half_clk, SSP); +lpsc_clk(tdm0, tdm_0_clk, TDM0); +lpsc_clk(tdm1, tdm_1_clk, TDM1); +lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); +lpsc_clk(mcdma, sys_half_clk, MCDMA); +lpsc_clk(usb0, sys_half_clk, USB0); +lpsc_clk(usb1, sys_half_clk, USB1); +lpsc_clk(usbss, sys_half_clk, USBSS); +lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); +lpsc_clk(imcop, sys_dsp_clk, IMCOP); +lpsc_clk(spare, sys_half_clk, SPARE); + +/* LCD needs a full power down to clear controller state */ +__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE); + + +/* Level 4 - leaf clocks for LPSC modules shared across drivers */ +static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec }; +static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec }; + +static struct clk_lookup clks[] = { + CLK(NULL, "pll_sys_clk", &pll_sys_clk), + CLK(NULL, "pll_eth_clk", &pll_eth_clk), + CLK(NULL, "pll_tdm_clk", &pll_tdm_clk), + CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk), + CLK(NULL, "sys_dsp_clk", &sys_dsp_clk), + CLK(NULL, "sys_ddr_clk", &sys_ddr_clk), + CLK(NULL, "sys_full_clk", &sys_full_clk), + CLK(NULL, "sys_lcd_clk", &sys_lcd_clk), + CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk), + CLK(NULL, "sys_tsc_clk", &sys_tsc_clk), + CLK(NULL, "sys_half_clk", &sys_half_clk), + CLK(NULL, "eth_5mhz_clk", ð_5mhz_clk), + CLK(NULL, "eth_50mhz_clk", ð_50mhz_clk), + CLK(NULL, "eth_125mhz_clk", ð_125mhz_clk), + CLK(NULL, "eth_250mhz_clk", ð_250mhz_clk), + CLK(NULL, "eth_25mhz_clk", ð_25mhz_clk), + CLK(NULL, "tdm_0_clk", &tdm_0_clk), + CLK(NULL, "tdm_extra_clk", &tdm_extra_clk), + CLK(NULL, "tdm_1_clk", &tdm_1_clk), + CLK(NULL, "clk_arm", &clk_arm), + CLK(NULL, "clk_gem", &clk_gem), + CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy), + CLK(NULL, "clk_tpcc", &clk_tpcc), + CLK(NULL, "clk_tptc0", &clk_tptc0), + CLK(NULL, "clk_tptc1", &clk_tptc1), + CLK(NULL, "clk_ram", &clk_ram), + CLK(NULL, "clk_mbx_lite", &clk_mbx_lite), + CLK("tnetv107x-fb.0", NULL, &clk_lcd), + CLK(NULL, "clk_ethss", &clk_ethss), + CLK(NULL, "aemif", &clk_aemif), + CLK(NULL, "clk_chipcfg", &clk_chipcfg), + CLK("tnetv107x-ts.0", NULL, &clk_tsc), + CLK(NULL, "clk_rom", &clk_rom), + CLK(NULL, "uart2", &clk_uart2), + CLK(NULL, "clk_pktsec", &clk_pktsec), + CLK("tnetv107x-rng.0", NULL, &clk_rng), + CLK("tnetv107x-pka.0", NULL, &clk_pka), + CLK(NULL, "clk_secctl", &clk_secctl), + CLK(NULL, "clk_keymgr", &clk_keymgr), + CLK("tnetv107x-keypad.0", NULL, &clk_keypad), + CLK(NULL, "clk_gpio", &clk_gpio), + CLK(NULL, "clk_mdio", &clk_mdio), + CLK("davinci_mmc.0", NULL, &clk_sdio0), + CLK(NULL, "uart0", &clk_uart0), + CLK(NULL, "uart1", &clk_uart1), + CLK(NULL, "timer0", &clk_timer0), + CLK(NULL, "timer1", &clk_timer1), + CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), + CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), + CLK("ti-ssp.0", NULL, &clk_ssp), + CLK(NULL, "clk_tdm0", &clk_tdm0), + CLK(NULL, "clk_vlynq", &clk_vlynq), + CLK(NULL, "clk_mcdma", &clk_mcdma), + CLK(NULL, "clk_usb0", &clk_usb0), + CLK(NULL, "clk_tdm1", &clk_tdm1), + CLK(NULL, "clk_debugss", &clk_debugss), + CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), + CLK(NULL, "clk_system", &clk_system), + CLK(NULL, "clk_imcop", &clk_imcop), + CLK(NULL, "clk_spare", &clk_spare), + CLK("davinci_mmc.1", NULL, &clk_sdio1), + CLK(NULL, "clk_usb1", &clk_usb1), + CLK(NULL, "clk_usbss", &clk_usbss), + CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), + CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), + CLK(NULL, NULL, NULL), +}; + +static const struct mux_config pins[] = { +#ifdef CONFIG_DAVINCI_MUX + MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false) +#endif +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = { + /* fill in default priority 7 */ + [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7, + /* now override as needed, e.g. [xxx] = 5 */ +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id ids[] = { + { + .variant = 0x0, + .part_no = 0xb8a1, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_TNETV107X, + .name = "tnetv107x rev1.0", + }, +}; + +static struct davinci_timer_instance timer_instance[2] = { + { + .base = TNETV107X_TIMER0_BASE, + .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12, + .top_irq = IRQ_TNETV107X_TIMER_0_TINT34, + }, + { + .base = TNETV107X_TIMER1_BASE, + .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12, + .top_irq = IRQ_TNETV107X_TIMER_1_TINT34, + }, +}; + +static struct davinci_timer_info timer_info = { + .timers = timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +/* + * TNETV107X platforms do not use the static mappings from Davinci + * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses, + * and changing IO_PHYS would break away from existing Davinci SOCs. + * + * The primary impact of the current model is that IO_ADDRESS() is not to be + * used to map registers on TNETV107X. + * + * 1. The first chunk is for INTC: This needs to be mapped in via iotable + * because ioremap() does not seem to be operational at the time when + * irqs are initialized. Without this, consistent dma init bombs. + * + * 2. The second chunk maps in register areas that need to be populated into + * davinci_soc_info. Note that alignment restrictions come into play if + * low-level debug is enabled (see note in <mach/tnetv107x.h>). + */ +static struct map_desc io_desc[] = { + { /* INTC */ + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(TNETV107X_INTC_BASE), + .length = SZ_16K, + .type = MT_DEVICE + }, + { /* Most of the rest */ + .virtual = TNETV107X_IO_VIRT, + .pfn = __phys_to_pfn(TNETV107X_IO_BASE), + .length = IO_SIZE - SZ_1M, + .type = MT_DEVICE + }, +}; + +static unsigned long clk_sspll_recalc(struct clk *clk) +{ + int pll; + unsigned long mult = 0, prediv = 1, postdiv = 1; + unsigned long ref = OSC_FREQ_ONCHIP, ret; + u32 tmp; + + if (WARN_ON(!clk->pll_data)) + return clk->rate; + + if (!clk_ctrl_regs) { + void __iomem *tmp; + + tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K); + + if (WARN(!tmp, "failed ioremap for clock control regs\n")) + return clk->parent ? clk->parent->rate : 0; + + for (pll = 0; pll < N_PLLS; pll++) + sspll_regs[pll] = tmp + sspll_regs_base[pll]; + + clk_ctrl_regs = tmp; + } + + pll = clk->pll_data->num; + + tmp = __raw_readl(&clk_ctrl_regs->pll_bypass); + if (!(tmp & bypass_mask[pll])) { + mult = __raw_readl(&sspll_regs[pll]->mult_factor); + prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1; + postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1; + } + + tmp = __raw_readl(clk->pll_data->base + PLLCTL); + if (tmp & PLLCTL_CLKMODE) + ref = pll_ext_freq[pll]; + + clk->pll_data->input_rate = ref; + + tmp = __raw_readl(clk->pll_data->base + PLLCTL); + if (!(tmp & PLLCTL_PLLEN)) + return ref; + + ret = ref; + if (mult) + ret += ((unsigned long long)ref * mult) / 256; + + ret /= (prediv * postdiv); + + return ret; +} + +static void tnetv107x_watchdog_reset(struct platform_device *pdev) +{ + struct wdt_regs __iomem *regs; + + regs = ioremap(pdev->resource[0].start, SZ_4K); + + /* disable watchdog */ + __raw_writel(0x7777, ®s->disable_lock); + __raw_writel(0xcccc, ®s->disable_lock); + __raw_writel(0xdddd, ®s->disable_lock); + __raw_writel(0, ®s->disable); + + /* program prescale */ + __raw_writel(0x5a5a, ®s->prescale_lock); + __raw_writel(0xa5a5, ®s->prescale_lock); + __raw_writel(0, ®s->prescale); + + /* program countdown */ + __raw_writel(0x6666, ®s->change_lock); + __raw_writel(0xbbbb, ®s->change_lock); + __raw_writel(1, ®s->change); + + /* enable watchdog */ + __raw_writel(0x7777, ®s->disable_lock); + __raw_writel(0xcccc, ®s->disable_lock); + __raw_writel(0xdddd, ®s->disable_lock); + __raw_writel(1, ®s->disable); + + /* kick */ + __raw_writel(0x5555, ®s->kick_lock); + __raw_writel(0xaaaa, ®s->kick_lock); + __raw_writel(1, ®s->kick); +} + +static struct davinci_soc_info tnetv107x_soc_info = { + .io_desc = io_desc, + .io_desc_num = ARRAY_SIZE(io_desc), + .ids = ids, + .ids_num = ARRAY_SIZE(ids), + .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018, + .cpu_clks = clks, + .psc_bases = psc_regs, + .psc_bases_num = ARRAY_SIZE(psc_regs), + .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150, + .pinmux_pins = pins, + .pinmux_pins_num = ARRAY_SIZE(pins), + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_base = TNETV107X_INTC_BASE, + .intc_irq_prios = irq_prios, + .intc_irq_num = TNETV107X_N_CP_INTC_IRQ, + .intc_host_map = intc_host_map, + .gpio_base = TNETV107X_GPIO_BASE, + .gpio_type = GPIO_TYPE_TNETV107X, + .gpio_num = TNETV107X_N_GPIO, + .timer_info = &timer_info, + .serial_dev = &tnetv107x_serial_device, + .reset = tnetv107x_watchdog_reset, + .reset_device = &tnetv107x_wdt_device, +}; + +void __init tnetv107x_init(void) +{ + davinci_common_init(&tnetv107x_soc_info); +} diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 7f3039761d9..8bf3cec98cf 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -43,7 +43,8 @@ static unsigned long get_uart_rate(struct clk *clk); static int set_keytchclk_rate(struct clk *clk, unsigned long rate); static int set_div_rate(struct clk *clk, unsigned long rate); - +static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate); +static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate); static struct clk clk_xtali = { .rate = EP93XX_EXT_CLK_RATE, @@ -112,6 +113,29 @@ static struct clk clk_video = { .set_rate = set_div_rate, }; +static struct clk clk_i2s_mclk = { + .sw_locked = 1, + .enable_reg = EP93XX_SYSCON_I2SCLKDIV, + .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, + .set_rate = set_div_rate, +}; + +static struct clk clk_i2s_sclk = { + .sw_locked = 1, + .parent = &clk_i2s_mclk, + .enable_reg = EP93XX_SYSCON_I2SCLKDIV, + .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, + .set_rate = set_i2s_sclk_rate, +}; + +static struct clk clk_i2s_lrclk = { + .sw_locked = 1, + .parent = &clk_i2s_sclk, + .enable_reg = EP93XX_SYSCON_I2SCLKDIV, + .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA, + .set_rate = set_i2s_lrclk_rate, +}; + /* DMA Clocks */ static struct clk clk_m2p0 = { .parent = &clk_h, @@ -191,6 +215,9 @@ static struct clk_lookup clocks[] = { INIT_CK("ep93xx-keypad", NULL, &clk_keypad), INIT_CK("ep93xx-fb", NULL, &clk_video), INIT_CK("ep93xx-spi.0", NULL, &clk_spi), + INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk), + INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk), + INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk), INIT_CK(NULL, "pwm_clk", &clk_pwm), INIT_CK(NULL, "m2p0", &clk_m2p0), INIT_CK(NULL, "m2p1", &clk_m2p1), @@ -401,6 +428,44 @@ static int set_div_rate(struct clk *clk, unsigned long rate) return 0; } +static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned val = __raw_readl(clk->enable_reg); + + if (rate == clk_i2s_mclk.rate / 2) + ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, + clk->enable_reg); + else if (rate == clk_i2s_mclk.rate / 4) + ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, + clk->enable_reg); + else + return -EINVAL; + + clk_i2s_sclk.rate = rate; + return 0; +} + +static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned val = __raw_readl(clk->enable_reg) & + ~EP93XX_I2SCLKDIV_LRDIV_MASK; + + if (rate == clk_i2s_sclk.rate / 32) + ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32, + clk->enable_reg); + else if (rate == clk_i2s_sclk.rate / 64) + ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64, + clk->enable_reg); + else if (rate == clk_i2s_sclk.rate / 128) + ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128, + clk->enable_reg); + else + return -EINVAL; + + clk_i2s_lrclk.rate = rate; + return 0; +} + int clk_set_rate(struct clk *clk, unsigned long rate) { if (clk->set_rate) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 8e37a045188..4cb55d3902f 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -758,6 +758,73 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev) } EXPORT_SYMBOL(ep93xx_keypad_release_gpio); +/************************************************************************* + * EP93xx I2S audio peripheral handling + *************************************************************************/ +static struct resource ep93xx_i2s_resource[] = { + { + .start = EP93XX_I2S_PHYS_BASE, + .end = EP93XX_I2S_PHYS_BASE + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ep93xx_i2s_device = { + .name = "ep93xx-i2s", + .id = -1, + .num_resources = ARRAY_SIZE(ep93xx_i2s_resource), + .resource = ep93xx_i2s_resource, +}; + +void __init ep93xx_register_i2s(void) +{ + platform_device_register(&ep93xx_i2s_device); +} + +#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ + EP93XX_SYSCON_DEVCFG_I2SONAC97) + +#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ + EP93XX_SYSCON_I2SCLKDIV_SPOL) + +int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config) +{ + unsigned val; + + /* Sanity check */ + if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK) + return -EINVAL; + if (i2s_config & ~EP93XX_I2SCLKDIV_MASK) + return -EINVAL; + + /* Must have only one of I2SONSSP/I2SONAC97 set */ + if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) == + (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97)) + return -EINVAL; + + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); + ep93xx_devcfg_set_bits(i2s_pins); + + /* + * This is potentially racy with the clock api for i2s_mclk, sclk and + * lrclk. Since the i2s driver is the only user of those clocks we + * rely on it to prevent parallel use of this function and the + * clock api for the i2s clocks. + */ + val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); + val &= ~EP93XX_I2SCLKDIV_MASK; + val |= i2s_config; + ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); + + return 0; +} +EXPORT_SYMBOL(ep93xx_i2s_acquire); + +void ep93xx_i2s_release(void) +{ + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); +} +EXPORT_SYMBOL(ep93xx_i2s_release); extern void ep93xx_gpio_init(void); diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index b1e096f0c2d..c54b3e56ba6 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -93,6 +93,7 @@ /* APB peripherals */ #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) +#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000) #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) @@ -194,6 +195,15 @@ #define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) #define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 +#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c) +#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31) +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29) +#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19) +#define EP93XX_I2SCLKDIV_SDIV (1 << 16) +#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17) +#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17) +#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) +#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31) #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16) diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index a6c09176334..3330b36d79e 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -58,6 +58,9 @@ void ep93xx_pwm_release_gpio(struct platform_device *pdev); void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data); int ep93xx_keypad_acquire_gpio(struct platform_device *pdev); void ep93xx_keypad_release_gpio(struct platform_device *pdev); +void ep93xx_register_i2s(void); +int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config); +void ep93xx_i2s_release(void); void ep93xx_init_devices(void); extern struct sys_timer ep93xx_timer; diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index 38deaee4039..a12c8930129 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -157,6 +157,7 @@ static void __init snappercl15_init_machine(void) ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data, ARRAY_SIZE(snappercl15_i2c_data)); ep93xx_register_fb(&snappercl15_fb_info); + ep93xx_register_i2s(); platform_device_register(&snappercl15_nand_device); } diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig index 515b75cf2e8..6f066ee4bf2 100644 --- a/arch/arm/mach-gemini/Kconfig +++ b/arch/arm/mach-gemini/Kconfig @@ -2,6 +2,13 @@ if ARCH_GEMINI menu "Cortina Systems Gemini Implementations" +config MACH_NAS4220B + bool "Raidsonic NAS-4220-B" + select GEMINI_MEM_SWAP + help + Say Y here if you intend to run this kernel on a + Raidsonic NAS-4220-B. + config MACH_RUT100 bool "Teltonika RUT100" select GEMINI_MEM_SWAP @@ -9,6 +16,20 @@ config MACH_RUT100 Say Y here if you intend to run this kernel on a Teltonika 3G Router RUT100. +config MACH_WBD111 + bool "Wiliboard WBD-111" + select GEMINI_MEM_SWAP + help + Say Y here if you intend to run this kernel on a + Wiliboard WBD-111. + +config MACH_WBD222 + bool "Wiliboard WBD-222" + select GEMINI_MEM_SWAP + help + Say Y here if you intend to run this kernel on a + Wiliboard WBD-222. + endmenu config GEMINI_MEM_SWAP diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile index 719505b8182..c5b24b95a76 100644 --- a/arch/arm/mach-gemini/Makefile +++ b/arch/arm/mach-gemini/Makefile @@ -7,4 +7,7 @@ obj-y := irq.o mm.o time.o devices.o gpio.o # Board-specific support +obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o +obj-$(CONFIG_MACH_WBD111) += board-wbd111.o +obj-$(CONFIG_MACH_WBD222) += board-wbd222.o diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c new file mode 100644 index 00000000000..01f1d6daab4 --- /dev/null +++ b/arch/arm/mach-gemini/board-nas4220b.c @@ -0,0 +1,111 @@ +/* + * Support for Raidsonic NAS-4220-B + * + * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com> + * + * based on rut1xx.c + * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/mdio-gpio.h> +#include <linux/io.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/global_reg.h> + +#include "common.h" + +static struct sys_timer ib4220b_timer = { + .init = gemini_timer_init, +}; + +static struct gpio_led ib4220b_leds[] = { + { + .name = "nas4220b:orange:hdd", + .default_trigger = "none", + .gpio = 60, + }, + { + .name = "nas4220b:green:os", + .default_trigger = "heartbeat", + .gpio = 62, + }, +}; + +static struct gpio_led_platform_data ib4220b_leds_data = { + .num_leds = ARRAY_SIZE(ib4220b_leds), + .leds = ib4220b_leds, +}; + +static struct platform_device ib4220b_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &ib4220b_leds_data, + }, +}; + +static struct gpio_keys_button ib4220b_keys[] = { + { + .code = KEY_SETUP, + .gpio = 61, + .active_low = 1, + .desc = "Backup Button", + .type = EV_KEY, + }, + { + .code = KEY_RESTART, + .gpio = 63, + .active_low = 1, + .desc = "Softreset Button", + .type = EV_KEY, + }, +}; + +static struct gpio_keys_platform_data ib4220b_keys_data = { + .buttons = ib4220b_keys, + .nbuttons = ARRAY_SIZE(ib4220b_keys), +}; + +static struct platform_device ib4220b_key_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &ib4220b_keys_data, + }, +}; + +static void __init ib4220b_init(void) +{ + gemini_gpio_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); + platform_device_register(&ib4220b_key_device); +} + +MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") + .phys_io = 0x7fffc000, + .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc, + .boot_params = 0x100, + .map_io = gemini_map_io, + .init_irq = gemini_init_irq, + .timer = &ib4220b_timer, + .init_machine = ib4220b_init, +MACHINE_END diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c new file mode 100644 index 00000000000..36538c15b3c --- /dev/null +++ b/arch/arm/mach-gemini/board-wbd111.c @@ -0,0 +1,143 @@ +/* + * Support for Wiliboard WBD-111 + * + * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/input.h> +#include <linux/skbuff.h> +#include <linux/gpio_keys.h> +#include <linux/mdio-gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + + +#include "common.h" + +static struct gpio_keys_button wbd111_keys[] = { + { + .code = KEY_SETUP, + .gpio = 5, + .active_low = 1, + .desc = "reset", + .type = EV_KEY, + }, +}; + +static struct gpio_keys_platform_data wbd111_keys_data = { + .buttons = wbd111_keys, + .nbuttons = ARRAY_SIZE(wbd111_keys), +}; + +static struct platform_device wbd111_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &wbd111_keys_data, + }, +}; + +static struct gpio_led wbd111_leds[] = { + { + .name = "L3red", + .gpio = 1, + }, + { + .name = "L4green", + .gpio = 2, + }, + { + .name = "L4red", + .gpio = 3, + }, + { + .name = "L3green", + .gpio = 5, + }, +}; + +static struct gpio_led_platform_data wbd111_leds_data = { + .num_leds = ARRAY_SIZE(wbd111_leds), + .leds = wbd111_leds, +}; + +static struct platform_device wbd111_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &wbd111_leds_data, + }, +}; + +static struct sys_timer wbd111_timer = { + .init = gemini_timer_init, +}; + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition wbd111_partitions[] = { + { + .name = "RedBoot", + .offset = 0, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "kernel", + .offset = 0x020000, + .size = 0x100000, + } , { + .name = "rootfs", + .offset = 0x120000, + .size = 0x6a0000, + } , { + .name = "VCTL", + .offset = 0x7c0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "cfg", + .offset = 0x7d0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "FIS", + .offset = 0x7e0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } +}; +#define wbd111_num_partitions ARRAY_SIZE(wbd111_partitions) +#else +#define wbd111_partitions NULL +#define wbd111_num_partitions 0 +#endif /* CONFIG_MTD_PARTITIONS */ + +static void __init wbd111_init(void) +{ + gemini_gpio_init(); + platform_register_uart(); + platform_register_pflash(SZ_8M, wbd111_partitions, + wbd111_num_partitions); + platform_device_register(&wbd111_leds_device); + platform_device_register(&wbd111_keys_device); +} + +MACHINE_START(WBD111, "Wiliboard WBD-111") + .phys_io = 0x7fffc000, + .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc, + .boot_params = 0x100, + .map_io = gemini_map_io, + .init_irq = gemini_init_irq, + .timer = &wbd111_timer, + .init_machine = wbd111_init, +MACHINE_END diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c new file mode 100644 index 00000000000..ece8b4c6511 --- /dev/null +++ b/arch/arm/mach-gemini/board-wbd222.c @@ -0,0 +1,143 @@ +/* + * Support for Wiliboard WBD-222 + * + * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/leds.h> +#include <linux/input.h> +#include <linux/skbuff.h> +#include <linux/gpio_keys.h> +#include <linux/mdio-gpio.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + + +#include "common.h" + +static struct gpio_keys_button wbd222_keys[] = { + { + .code = KEY_SETUP, + .gpio = 5, + .active_low = 1, + .desc = "reset", + .type = EV_KEY, + }, +}; + +static struct gpio_keys_platform_data wbd222_keys_data = { + .buttons = wbd222_keys, + .nbuttons = ARRAY_SIZE(wbd222_keys), +}; + +static struct platform_device wbd222_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &wbd222_keys_data, + }, +}; + +static struct gpio_led wbd222_leds[] = { + { + .name = "L3red", + .gpio = 1, + }, + { + .name = "L4green", + .gpio = 2, + }, + { + .name = "L4red", + .gpio = 3, + }, + { + .name = "L3green", + .gpio = 5, + }, +}; + +static struct gpio_led_platform_data wbd222_leds_data = { + .num_leds = ARRAY_SIZE(wbd222_leds), + .leds = wbd222_leds, +}; + +static struct platform_device wbd222_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &wbd222_leds_data, + }, +}; + +static struct sys_timer wbd222_timer = { + .init = gemini_timer_init, +}; + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition wbd222_partitions[] = { + { + .name = "RedBoot", + .offset = 0, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "kernel", + .offset = 0x020000, + .size = 0x100000, + } , { + .name = "rootfs", + .offset = 0x120000, + .size = 0x6a0000, + } , { + .name = "VCTL", + .offset = 0x7c0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "cfg", + .offset = 0x7d0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "FIS", + .offset = 0x7e0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } +}; +#define wbd222_num_partitions ARRAY_SIZE(wbd222_partitions) +#else +#define wbd222_partitions NULL +#define wbd222_num_partitions 0 +#endif /* CONFIG_MTD_PARTITIONS */ + +static void __init wbd222_init(void) +{ + gemini_gpio_init(); + platform_register_uart(); + platform_register_pflash(SZ_8M, wbd222_partitions, + wbd222_num_partitions); + platform_device_register(&wbd222_leds_device); + platform_device_register(&wbd222_keys_device); +} + +MACHINE_START(WBD222, "Wiliboard WBD-222") + .phys_io = 0x7fffc000, + .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc, + .boot_params = 0x100, + .map_io = gemini_map_io, + .init_irq = gemini_init_irq, + .timer = &wbd222_timer, + .init_machine = wbd222_init, +MACHINE_END diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h index 6c19156e2a4..c55a52c6541 100644 --- a/arch/arm/mach-h720x/include/mach/hardware.h +++ b/arch/arm/mach-h720x/include/mach/hardware.h @@ -182,8 +182,6 @@ #define SERIAL_ENABLE_EN (1<<0) /* General defines to pacify gcc */ -#define PCIO_BASE (0) /* for inb, outb and friends */ -#define PCIO_VIRT PCIO_BASE #define __ASM_ARCH_HARDWARE_INCMACH_H #include "boards.h" diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 575ff1ae85a..339150ab0ea 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -279,13 +279,13 @@ static void __init eukrea_cpuimx27_init(void) #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg_host, &otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_usbh2, &usbh2_pdata); #endif diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 6c92deaf468..23c9e1f37b9 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -408,7 +408,7 @@ static void __init pca100_init(void) mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); spi_register_board_info(pca100_spi_board_info, ARRAY_SIZE(pca100_spi_board_info)); - imx27_add_spi_imx0(&pca100_spi_0_data); + imx27_add_spi_imx0(&pca100_spi0_data); #endif gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); @@ -419,13 +419,13 @@ static void __init pca100_init(void) #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg_host, &otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_usbh2, &usbh2_pdata); #endif diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h index 8e26360ce9a..57f51ba1125 100644 --- a/arch/arm/mach-integrator/include/mach/hardware.h +++ b/arch/arm/mach-integrator/include/mach/hardware.h @@ -32,7 +32,6 @@ #define IO_SIZE 0x0B000000 // How much? #define IO_START INTEGRATOR_HDR_BASE // PA of IO -#define PCIO_BASE PCI_IO_VADDR #define PCIMEM_BASE PCI_MEMORY_VADDR #define pcibios_assign_all_busses() 1 diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h index c3192009a88..57b508bfe28 100644 --- a/arch/arm/mach-ixp23xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp23xx/include/mach/hardware.h @@ -15,7 +15,6 @@ #define __ASM_ARCH_HARDWARE_H /* PCI IO info */ -#define PCIO_BASE IXP23XX_PCI_IO_VIRT #define PCIBIOS_MIN_IO 0x00000000 #define PCIBIOS_MIN_MEM 0xe0000000 diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 9e5070da17a..6f991c5ae86 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -140,6 +140,14 @@ config MACH_FSG FSG-3 device. For more information on this platform, see http://www.nslu2-linux.org/wiki/FSG3/HomePage +config MACH_ARCOM_VULCAN + bool + prompt "Arcom/Eurotech Vulcan" + select PCI + help + Say 'Y' here if you want your kernel to support Arcom's + Vulcan board. + # # Certain registers and IRQs are only enabled if supporting IXP465 CPUs # diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 47d1f60d23f..d807fc367dd 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -16,6 +16,7 @@ obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o +obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o obj-y += common.o @@ -31,6 +32,7 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o obj-$(CONFIG_MACH_FSG) += fsg-setup.o obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o +obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S index 893873eb2a0..3fc66d6d00a 100644 --- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S +++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S @@ -16,8 +16,10 @@ moveq \rx, #0xc8000000 movne \rx, #0xff000000 orrne \rx, \rx, #0x00b00000 +#ifdef __ARMEB__ add \rx,\rx,#3 @ Uart regs are at off set of 3 if @ byte writes used - Big Endian. +#endif .endm #define UART_SHIFT 2 diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 6ea7e2fb270..de274a1f19d 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -353,7 +353,7 @@ static inline unsigned int ioread8(const void __iomem *addr) return (unsigned int)inb(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - return (unsigned int)__raw_readb(port); + return (unsigned int)__raw_readb(addr); #else return (unsigned int)__indirect_readb(addr); #endif @@ -381,7 +381,7 @@ static inline unsigned int ioread16(const void __iomem *addr) return (unsigned int)inw(port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - return le16_to_cpu(__raw_readw((u32)port)); + return le16_to_cpu((__force __le16)__raw_readw(addr)); #else return (unsigned int)__indirect_readw(addr); #endif @@ -440,7 +440,7 @@ static inline void iowrite8(u8 value, void __iomem *addr) outb(value, port & PIO_MASK); else #ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writeb(value, port); + __raw_writeb(value, addr); #else __indirect_writeb(value, addr); #endif diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 827cbc4402f..ea9ee4ed0a3 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -100,6 +100,7 @@ ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) static struct platform_nand_data ixdp425_flash_nand_data = { .chip = { + .nr_chips = 1, .chip_delay = 30, .options = NAND_NO_AUTOINCR, #ifdef CONFIG_MTD_PARTITIONS diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c new file mode 100644 index 00000000000..f3111c6840e --- /dev/null +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -0,0 +1,73 @@ +/* + * arch/arch/mach-ixp4xx/vulcan-pci.c + * + * Vulcan board-level PCI initialization + * + * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org> + * + * based on ixdp425-pci.c: + * Copyright (C) 2002 Intel Corporation. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <asm/mach/pci.h> +#include <asm/mach-types.h> + +/* PCI controller GPIO to IRQ pin mappings */ +#define INTA 2 +#define INTB 3 + +void __init vulcan_pci_preinit(void) +{ +#ifndef CONFIG_IXP4XX_INDIRECT_PCI + /* + * Cardbus bridge wants way more than the SoC can actually offer, + * and leaves the whole PCI bus in a mess. Artificially limit it + * to 8MB per region. Of course indirect mode doesn't have this + * limitation... + */ + pci_cardbus_mem_size = SZ_8M; + pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", + (int)(pci_cardbus_mem_size >> 20)); +#endif + set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); +} + +static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (slot == 1) + return IXP4XX_GPIO_IRQ(INTA); + + if (slot == 2) + return IXP4XX_GPIO_IRQ(INTB); + + return -1; +} + +struct hw_pci vulcan_pci __initdata = { + .nr_controllers = 1, + .preinit = vulcan_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, + .map_irq = vulcan_map_irq, +}; + +int __init vulcan_pci_init(void) +{ + if (machine_is_arcom_vulcan()) + pci_common_init(&vulcan_pci); + return 0; +} + +subsys_initcall(vulcan_pci_init); diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c new file mode 100644 index 00000000000..465cc5cce68 --- /dev/null +++ b/arch/arm/mach-ixp4xx/vulcan-setup.c @@ -0,0 +1,246 @@ +/* + * arch/arm/mach-ixp4xx/vulcan-setup.c + * + * Arcom/Eurotech Vulcan board-setup + * + * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org> + * + * based on fsg-setup.c: + * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au> + */ + +#include <linux/if_ether.h> +#include <linux/irq.h> +#include <linux/serial.h> +#include <linux/serial_8250.h> +#include <linux/io.h> +#include <linux/w1-gpio.h> +#include <linux/mtd/plat-ram.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> + +static struct flash_platform_data vulcan_flash_data = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct resource vulcan_flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device vulcan_flash = { + .name = "IXP4XX-Flash", + .id = 0, + .dev = { + .platform_data = &vulcan_flash_data, + }, + .resource = &vulcan_flash_resource, + .num_resources = 1, +}; + +static struct platdata_mtd_ram vulcan_sram_data = { + .mapname = "Vulcan SRAM", + .bankwidth = 1, +}; + +static struct resource vulcan_sram_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device vulcan_sram = { + .name = "mtd-ram", + .id = 0, + .dev = { + .platform_data = &vulcan_sram_data, + }, + .resource = &vulcan_sram_resource, + .num_resources = 1, +}; + +static struct resource vulcan_uart_resources[] = { + [0] = { + .start = IXP4XX_UART1_BASE_PHYS, + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IXP4XX_UART2_BASE_PHYS, + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [2] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct plat_serial8250_port vulcan_uart_data[] = { + [0] = { + .mapbase = IXP4XX_UART1_BASE_PHYS, + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + [1] = { + .mapbase = IXP4XX_UART2_BASE_PHYS, + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + [2] = { + .irq = IXP4XX_GPIO_IRQ(4), + .irqflags = IRQF_TRIGGER_LOW, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .uartclk = 1843200, + }, + [3] = { + .irq = IXP4XX_GPIO_IRQ(4), + .irqflags = IRQF_TRIGGER_LOW, + .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .uartclk = 1843200, + }, + { } +}; + +static struct platform_device vulcan_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = vulcan_uart_data, + }, + .resource = vulcan_uart_resources, + .num_resources = ARRAY_SIZE(vulcan_uart_resources), +}; + +static struct eth_plat_info vulcan_plat_eth[] = { + [0] = { + .phy = 0, + .rxq = 3, + .txreadyq = 20, + }, + [1] = { + .phy = 1, + .rxq = 4, + .txreadyq = 21, + }, +}; + +static struct platform_device vulcan_eth[] = { + [0] = { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev = { + .platform_data = &vulcan_plat_eth[0], + }, + }, + [1] = { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev = { + .platform_data = &vulcan_plat_eth[1], + }, + }, +}; + +static struct resource vulcan_max6369_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device vulcan_max6369 = { + .name = "max6369_wdt", + .id = -1, + .resource = &vulcan_max6369_resource, + .num_resources = 1, +}; + +static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = { + .pin = 14, +}; + +static struct platform_device vulcan_w1_gpio = { + .name = "w1-gpio", + .id = 0, + .dev = { + .platform_data = &vulcan_w1_gpio_pdata, + }, +}; + +static struct platform_device *vulcan_devices[] __initdata = { + &vulcan_uart, + &vulcan_flash, + &vulcan_sram, + &vulcan_max6369, + &vulcan_eth[0], + &vulcan_eth[1], + &vulcan_w1_gpio, +}; + +static void __init vulcan_init(void) +{ + ixp4xx_sys_init(); + + /* Flash is spread over both CS0 and CS1 */ + vulcan_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); + vulcan_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; + *IXP4XX_EXP_CS0 = IXP4XX_EXP_BUS_CS_EN | + IXP4XX_EXP_BUS_STROBE_T(3) | + IXP4XX_EXP_BUS_SIZE(0xF) | + IXP4XX_EXP_BUS_BYTE_RD16 | + IXP4XX_EXP_BUS_WR_EN; + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; + + /* SRAM on CS2, (256kB, 8bit, writable) */ + vulcan_sram_resource.start = IXP4XX_EXP_BUS_BASE(2); + vulcan_sram_resource.end = IXP4XX_EXP_BUS_BASE(2) + SZ_256K - 1; + *IXP4XX_EXP_CS2 = IXP4XX_EXP_BUS_CS_EN | + IXP4XX_EXP_BUS_STROBE_T(1) | + IXP4XX_EXP_BUS_HOLD_T(2) | + IXP4XX_EXP_BUS_SIZE(9) | + IXP4XX_EXP_BUS_SPLT_EN | + IXP4XX_EXP_BUS_WR_EN | + IXP4XX_EXP_BUS_BYTE_EN; + + /* XR16L2551 on CS3 (Moto style, 512 bytes, 8bits, writable) */ + vulcan_uart_resources[2].start = IXP4XX_EXP_BUS_BASE(3); + vulcan_uart_resources[2].end = IXP4XX_EXP_BUS_BASE(3) + 16 - 1; + vulcan_uart_data[2].mapbase = vulcan_uart_resources[2].start; + vulcan_uart_data[3].mapbase = vulcan_uart_data[2].mapbase + 8; + *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN | + IXP4XX_EXP_BUS_STROBE_T(3) | + IXP4XX_EXP_BUS_CYCLES(IXP4XX_EXP_BUS_CYCLES_MOTOROLA)| + IXP4XX_EXP_BUS_WR_EN | + IXP4XX_EXP_BUS_BYTE_EN; + + /* GPIOS on CS4 (512 bytes, 8bits, writable) */ + *IXP4XX_EXP_CS4 = IXP4XX_EXP_BUS_CS_EN | + IXP4XX_EXP_BUS_WR_EN | + IXP4XX_EXP_BUS_BYTE_EN; + + /* max6369 on CS5 (512 bytes, 8bits, writable) */ + vulcan_max6369_resource.start = IXP4XX_EXP_BUS_BASE(5); + vulcan_max6369_resource.end = IXP4XX_EXP_BUS_BASE(5); + *IXP4XX_EXP_CS5 = IXP4XX_EXP_BUS_CS_EN | + IXP4XX_EXP_BUS_WR_EN | + IXP4XX_EXP_BUS_BYTE_EN; + + platform_add_devices(vulcan_devices, ARRAY_SIZE(vulcan_devices)); +} + +MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan") + /* Maintainer: Marc Zyngier <maz@misterjones.org> */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .boot_params = 0x0100, + .init_machine = vulcan_init, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 9dd67c7b445..1c82d4290da 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -25,6 +25,7 @@ #include <asm/mach/time.h> #include <mach/kirkwood.h> #include <mach/bridge-regs.h> +#include <plat/audio.h> #include <plat/cache-feroceon-l2.h> #include <plat/ehci-orion.h> #include <plat/mvsdio.h> @@ -871,6 +872,42 @@ struct sys_timer kirkwood_timer = { .init = kirkwood_timer_init, }; +/***************************************************************************** + * Audio + ****************************************************************************/ +static struct resource kirkwood_i2s_resources[] = { + [0] = { + .start = AUDIO_PHYS_BASE, + .end = AUDIO_PHYS_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_KIRKWOOD_I2S, + .end = IRQ_KIRKWOOD_I2S, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { + .dram = &kirkwood_mbus_dram_info, + .burst = 128, +}; + +static struct platform_device kirkwood_i2s_device = { + .name = "kirkwood-i2s", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_i2s_resources), + .resource = kirkwood_i2s_resources, + .dev = { + .platform_data = &kirkwood_i2s_data, + }, +}; + +void __init kirkwood_audio_init(void) +{ + kirkwood_clk_ctrl |= CGC_AUDIO; + platform_device_register(&kirkwood_i2s_device); +} /***************************************************************************** * General @@ -939,6 +976,7 @@ void __init kirkwood_init(void) kirkwood_spi_plat_data.tclk = kirkwood_tclk; kirkwood_uart0_data[0].uartclk = kirkwood_tclk; kirkwood_uart1_data[0].uartclk = kirkwood_tclk; + kirkwood_i2s_data.tclk = kirkwood_tclk; /* * Disable propagation of mbus errors to the CPU local bus, diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 5b2c1c18d64..95bb0a73adf 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -17,6 +17,7 @@ struct mv_sata_platform_data; struct mvsdio_platform_data; struct mtd_partition; struct mtd_info; +struct kirkwood_asoc_platform_data; #define KW_PCIE0 (1 << 0) #define KW_PCIE1 (1 << 1) @@ -46,6 +47,7 @@ void kirkwood_uart0_init(void); void kirkwood_uart1_init(void); void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay); void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); +void kirkwood_audio_init(void); extern int kirkwood_tclk; extern struct sys_timer kirkwood_timer; diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index d141af4c274..93fc2ec95e7 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -111,6 +111,9 @@ #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) +#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) +#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) + /* * Supported devices and revisions. */ diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index fd64cd2b4e0..fd06be61881 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -15,6 +15,7 @@ #include <linux/mtd/partitions.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> +#include <linux/i2c.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/kirkwood.h> @@ -60,6 +61,12 @@ static unsigned int openrd_mpp_config[] __initdata = { 0 }; +static struct i2c_board_info i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("cs42l51", 0x4a), + }, +}; + static void __init openrd_init(void) { /* @@ -86,6 +93,12 @@ static void __init openrd_init(void) kirkwood_sdio_init(&openrd_mvsdio_data); kirkwood_i2c_init(); + + if (machine_is_openrd_client()) { + i2c_register_board_info(0, i2c_board_info, + ARRAY_SIZE(i2c_board_info)); + kirkwood_audio_init(); + } } static int __init openrd_pci_init(void) diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index 244655d323e..0629394a5fb 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -150,9 +150,8 @@ static void __init common_init(void) MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = pxa168_init_irq, .timer = &pxa168_timer, .init_machine = common_init, @@ -160,9 +159,8 @@ MACHINE_END MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = pxa168_init_irq, .timer = &pxa168_timer, .init_machine = common_init, diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c index 8c3fa5d14f4..69bcba11f53 100644 --- a/arch/arm/mach-mmp/avengers_lite.c +++ b/arch/arm/mach-mmp/avengers_lite.c @@ -42,9 +42,8 @@ static void __init avengers_lite_init(void) MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = pxa168_init_irq, .timer = &pxa168_timer, .init_machine = avengers_lite_init, diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c index e1e66c18b44..3b29fa7e9b0 100644 --- a/arch/arm/mach-mmp/common.c +++ b/arch/arm/mach-mmp/common.c @@ -31,7 +31,7 @@ static struct map_desc standard_io_desc[] __initdata = { }, }; -void __init pxa_map_io(void) +void __init mmp_map_io(void) { iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); } diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index b4a0ba05a0f..ec8d65ded25 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -3,15 +3,6 @@ struct sys_timer; extern void timer_init(int irq); -extern void mmp2_clear_pmic_int(void); - -extern struct sys_timer pxa168_timer; -extern struct sys_timer pxa910_timer; -extern struct sys_timer mmp2_timer; -extern void __init pxa168_init_irq(void); -extern void __init pxa910_init_irq(void); -extern void __init mmp2_init_icu(void); -extern void __init mmp2_init_irq(void); extern void __init icu_init_irq(void); -extern void __init pxa_map_io(void); +extern void __init mmp_map_io(void); diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c index 4ec7709a346..e4312d238ea 100644 --- a/arch/arm/mach-mmp/flint.c +++ b/arch/arm/mach-mmp/flint.c @@ -114,9 +114,8 @@ static void __init flint_init(void) MACHINE_START(FLINT, "Flint Development Platform") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = mmp2_init_irq, .timer = &mmp2_timer, .init_machine = flint_init, diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index 1fa0a492454..d0ec7dae88e 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -1,3 +1,6 @@ +#ifndef __MACH_DEVICE_H +#define __MACH_DEVICE_H + #include <linux/types.h> #define MAX_RESOURCE_DMA 2 @@ -47,3 +50,4 @@ struct pxa_device_desc mmp2_device_##_name __initdata = { \ } extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); +#endif /* __MACH_DEVICE_H */ diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index fec220bd504..dbba6e8a60c 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -1,6 +1,13 @@ #ifndef __ASM_MACH_MMP2_H #define __ASM_MACH_MMP2_H +struct sys_timer; + +extern struct sys_timer mmp2_timer; +extern void __init mmp2_init_icu(void); +extern void __init mmp2_init_irq(void); +extern void mmp2_clear_pmic_int(void); + #include <linux/i2c.h> #include <mach/devices.h> #include <plat/i2c.h> diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 3b2bd5d5eb0..27e1bc75862 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -1,6 +1,11 @@ #ifndef __ASM_MACH_PXA168_H #define __ASM_MACH_PXA168_H +struct sys_timer; + +extern struct sys_timer pxa168_timer; +extern void __init pxa168_init_irq(void); + #include <linux/i2c.h> #include <mach/devices.h> #include <plat/i2c.h> diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index 4f0b4ec6f5d..f13c49d6f8d 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -1,6 +1,11 @@ #ifndef __ASM_MACH_PXA910_H #define __ASM_MACH_PXA910_H +struct sys_timer; + +extern struct sys_timer pxa910_timer; +extern void __init pxa910_init_irq(void); + #include <linux/i2c.h> #include <mach/devices.h> #include <plat/i2c.h> diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index cb18221c0af..01342be91c3 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -16,6 +16,7 @@ #include <linux/io.h> #include <mach/regs-icu.h> +#include <mach/mmp2.h> #include "common.h" diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c index d77dd41d60e..80c3e7ab1e1 100644 --- a/arch/arm/mach-mmp/jasper.c +++ b/arch/arm/mach-mmp/jasper.c @@ -135,9 +135,8 @@ static void __init jasper_init(void) MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = mmp2_init_irq, .timer = &mmp2_timer, .init_machine = jasper_init, diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 7f5eb059bb0..daf3993349f 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -17,6 +17,7 @@ #include <asm/hardware/cache-tauros2.h> +#include <asm/mach/time.h> #include <mach/addr-map.h> #include <mach/regs-apbc.h> #include <mach/regs-apmu.h> @@ -26,6 +27,7 @@ #include <mach/mfp.h> #include <mach/gpio.h> #include <mach/devices.h> +#include <mach/mmp2.h> #include "common.h" #include "clock.h" @@ -158,6 +160,26 @@ static int __init mmp2_init(void) } postcore_initcall(mmp2_init); +static void __init mmp2_timer_init(void) +{ + unsigned long clk_rst; + + __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + + /* + * enable bus/functional clock, enable 6.5MHz (divider 4), + * release reset + */ + clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); + __raw_writel(clk_rst, APBC_MMP2_TIMERS); + + timer_init(IRQ_MMP2_TIMER1); +} + +struct sys_timer mmp2_timer = { + .init = mmp2_timer_init, +}; + /* on-chip devices */ MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c index 0e0c9220eab..e81db742821 100644 --- a/arch/arm/mach-mmp/tavorevb.c +++ b/arch/arm/mach-mmp/tavorevb.c @@ -100,9 +100,8 @@ static void __init tavorevb_init(void) MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = pxa910_init_irq, .timer = &pxa910_timer, .init_machine = tavorevb_init, diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index cf75694e968..66528193f93 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -200,24 +200,3 @@ void __init timer_init(int irq) clocksource_register(&cksrc); clockevents_register_device(&ckevt); } - -static void __init mmp2_timer_init(void) -{ - unsigned long clk_rst; - - __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); - - /* - * enable bus/functional clock, enable 6.5MHz (divider 4), - * release reset - */ - clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); - __raw_writel(clk_rst, APBC_MMP2_TIMERS); - - timer_init(IRQ_MMP2_TIMER1); -} - -struct sys_timer mmp2_timer = { - .init = mmp2_timer_init, -}; - diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index b22dec4abf7..ee65e05f0cf 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -123,9 +123,8 @@ static void __init ttc_dkb_init(void) MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") .phys_io = APB_PHYS_BASE, - .boot_params = 0x00000100, .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, - .map_io = pxa_map_io, + .map_io = mmp_map_io, .init_irq = pxa910_init_irq, .timer = &pxa910_timer, .init_machine = ttc_dkb_init, diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 7ff8020d4d2..704610648a2 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o -obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o +obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c index f060a3959a7..7ffbd987eb5 100644 --- a/arch/arm/mach-msm/acpuclock-arm11.c +++ b/arch/arm/mach-msm/acpuclock-arm11.c @@ -17,7 +17,6 @@ * */ -#include <linux/version.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/list.h> diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index 523d213bf79..c50f3afc313 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -15,10 +15,20 @@ #include <linux/module.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/interrupt.h> #include <linux/gpio.h> #include "board-trout.h" +static uint8_t trout_int_mask[2] = { + [0] = 0xff, /* mask all interrupts */ + [1] = 0xff, +}; +static uint8_t trout_sleep_int_mask[] = { + [0] = 0xff, + [1] = 0xff, +}; + struct msm_gpio_chip { struct gpio_chip chip; void __iomem *reg; /* Base of register bank */ @@ -95,16 +105,121 @@ static struct msm_gpio_chip msm_gpio_banks[] = { TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0), }; +static void trout_gpio_irq_ack(unsigned int irq) +{ + int bank = TROUT_INT_TO_BANK(irq); + uint8_t mask = TROUT_INT_TO_MASK(irq); + int reg = TROUT_BANK_TO_STAT_REG(bank); + /*printk(KERN_INFO "trout_gpio_irq_ack irq %d\n", irq);*/ + writeb(mask, TROUT_CPLD_BASE + reg); +} + +static void trout_gpio_irq_mask(unsigned int irq) +{ + unsigned long flags; + uint8_t reg_val; + int bank = TROUT_INT_TO_BANK(irq); + uint8_t mask = TROUT_INT_TO_MASK(irq); + int reg = TROUT_BANK_TO_MASK_REG(bank); + + local_irq_save(flags); + reg_val = trout_int_mask[bank] |= mask; + /*printk(KERN_INFO "trout_gpio_irq_mask irq %d => %d:%02x\n", + irq, bank, reg_val);*/ + writeb(reg_val, TROUT_CPLD_BASE + reg); + local_irq_restore(flags); +} + +static void trout_gpio_irq_unmask(unsigned int irq) +{ + unsigned long flags; + uint8_t reg_val; + int bank = TROUT_INT_TO_BANK(irq); + uint8_t mask = TROUT_INT_TO_MASK(irq); + int reg = TROUT_BANK_TO_MASK_REG(bank); + + local_irq_save(flags); + reg_val = trout_int_mask[bank] &= ~mask; + /*printk(KERN_INFO "trout_gpio_irq_unmask irq %d => %d:%02x\n", + irq, bank, reg_val);*/ + writeb(reg_val, TROUT_CPLD_BASE + reg); + local_irq_restore(flags); +} + +int trout_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + unsigned long flags; + int bank = TROUT_INT_TO_BANK(irq); + uint8_t mask = TROUT_INT_TO_MASK(irq); + + local_irq_save(flags); + if(on) + trout_sleep_int_mask[bank] &= ~mask; + else + trout_sleep_int_mask[bank] |= mask; + local_irq_restore(flags); + return 0; +} + +static void trout_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + int j, m; + unsigned v; + int bank; + int stat_reg; + int int_base = TROUT_INT_START; + uint8_t int_mask; + + for (bank = 0; bank < 2; bank++) { + stat_reg = TROUT_BANK_TO_STAT_REG(bank); + v = readb(TROUT_CPLD_BASE + stat_reg); + int_mask = trout_int_mask[bank]; + if (v & int_mask) { + writeb(v & int_mask, TROUT_CPLD_BASE + stat_reg); + printk(KERN_ERR "trout_gpio_irq_handler: got masked " + "interrupt: %d:%02x\n", bank, v & int_mask); + } + v &= ~int_mask; + while (v) { + m = v & -v; + j = fls(m) - 1; + /*printk(KERN_INFO "msm_gpio_irq_handler %d:%02x %02x b" + "it %d irq %d\n", bank, v, m, j, int_base + j);*/ + v &= ~m; + generic_handle_irq(int_base + j); + } + int_base += TROUT_INT_BANK0_COUNT; + } + desc->chip->ack(irq); +} + +static struct irq_chip trout_gpio_irq_chip = { + .name = "troutgpio", + .ack = trout_gpio_irq_ack, + .mask = trout_gpio_irq_mask, + .unmask = trout_gpio_irq_unmask, + .set_wake = trout_gpio_irq_set_wake, +}; + /* * Called from the processor-specific init to enable GPIO pin support. */ int __init trout_init_gpio(void) { int i; + for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { + set_irq_chip(i, &trout_gpio_irq_chip); + set_irq_handler(i, handle_edge_irq); + set_irq_flags(i, IRQF_VALID); + } for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) gpiochip_add(&msm_gpio_banks[i].chip); + set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); + set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); + set_irq_wake(MSM_GPIO_TO_INT(17), 1); + return 0; } diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c new file mode 100644 index 00000000000..44be8464657 --- /dev/null +++ b/arch/arm/mach-msm/board-trout-mmc.c @@ -0,0 +1,186 @@ +/* linux/arch/arm/mach-msm/board-trout-mmc.c +** Author: Brian Swetland <swetland@google.com> +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sdio_ids.h> +#include <linux/err.h> +#include <linux/debugfs.h> + +#include <asm/gpio.h> +#include <asm/io.h> + +#include <mach/vreg.h> + +#include <mach/mmc.h> + +#include "devices.h" + +#include "board-trout.h" + +#include "proc_comm.h" + +#define DEBUG_SDSLOT_VDD 1 + +/* ---- COMMON ---- */ +static void config_gpio_table(uint32_t *table, int len) +{ + int n; + unsigned id; + for(n = 0; n < len; n++) { + id = table[n]; + msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, 0); + } +} + +/* ---- SDCARD ---- */ + +static uint32_t sdcard_on_gpio_table[] = { + PCOM_GPIO_CFG(62, 2, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA), /* CLK */ + PCOM_GPIO_CFG(63, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* CMD */ + PCOM_GPIO_CFG(64, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT3 */ + PCOM_GPIO_CFG(65, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA), /* DAT2 */ + PCOM_GPIO_CFG(66, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT1 */ + PCOM_GPIO_CFG(67, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA), /* DAT0 */ +}; + +static uint32_t sdcard_off_gpio_table[] = { + PCOM_GPIO_CFG(62, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CLK */ + PCOM_GPIO_CFG(63, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* CMD */ + PCOM_GPIO_CFG(64, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT3 */ + PCOM_GPIO_CFG(65, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT2 */ + PCOM_GPIO_CFG(66, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT1 */ + PCOM_GPIO_CFG(67, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA), /* DAT0 */ +}; + +static uint opt_disable_sdcard; + +static int __init trout_disablesdcard_setup(char *str) +{ + int cal = simple_strtol(str, NULL, 0); + + opt_disable_sdcard = cal; + return 1; +} + +__setup("board_trout.disable_sdcard=", trout_disablesdcard_setup); + +static struct vreg *vreg_sdslot; /* SD slot power */ + +struct mmc_vdd_xlat { + int mask; + int level; +}; + +static struct mmc_vdd_xlat mmc_vdd_table[] = { + { MMC_VDD_165_195, 1800 }, + { MMC_VDD_20_21, 2050 }, + { MMC_VDD_21_22, 2150 }, + { MMC_VDD_22_23, 2250 }, + { MMC_VDD_23_24, 2350 }, + { MMC_VDD_24_25, 2450 }, + { MMC_VDD_25_26, 2550 }, + { MMC_VDD_26_27, 2650 }, + { MMC_VDD_27_28, 2750 }, + { MMC_VDD_28_29, 2850 }, + { MMC_VDD_29_30, 2950 }, +}; + +static unsigned int sdslot_vdd = 0xffffffff; +static unsigned int sdslot_vreg_enabled; + +static uint32_t trout_sdslot_switchvdd(struct device *dev, unsigned int vdd) +{ + int i, rc; + + BUG_ON(!vreg_sdslot); + + if (vdd == sdslot_vdd) + return 0; + + sdslot_vdd = vdd; + + if (vdd == 0) { +#if DEBUG_SDSLOT_VDD + printk("%s: Disabling SD slot power\n", __func__); +#endif + config_gpio_table(sdcard_off_gpio_table, + ARRAY_SIZE(sdcard_off_gpio_table)); + vreg_disable(vreg_sdslot); + sdslot_vreg_enabled = 0; + return 0; + } + + if (!sdslot_vreg_enabled) { + rc = vreg_enable(vreg_sdslot); + if (rc) { + printk(KERN_ERR "%s: Error enabling vreg (%d)\n", + __func__, rc); + } + config_gpio_table(sdcard_on_gpio_table, + ARRAY_SIZE(sdcard_on_gpio_table)); + sdslot_vreg_enabled = 1; + } + + for (i = 0; i < ARRAY_SIZE(mmc_vdd_table); i++) { + if (mmc_vdd_table[i].mask == (1 << vdd)) { +#if DEBUG_SDSLOT_VDD + printk("%s: Setting level to %u\n", + __func__, mmc_vdd_table[i].level); +#endif + rc = vreg_set_level(vreg_sdslot, + mmc_vdd_table[i].level); + if (rc) { + printk(KERN_ERR + "%s: Error setting vreg level (%d)\n", + __func__, rc); + } + return 0; + } + } + + printk(KERN_ERR "%s: Invalid VDD %d specified\n", __func__, vdd); + return 0; +} + +static unsigned int trout_sdslot_status(struct device *dev) +{ + unsigned int status; + + status = (unsigned int) gpio_get_value(TROUT_GPIO_SDMC_CD_N); + return (!status); +} + +#define TROUT_MMC_VDD MMC_VDD_165_195 | MMC_VDD_20_21 | MMC_VDD_21_22 \ + | MMC_VDD_22_23 | MMC_VDD_23_24 | MMC_VDD_24_25 \ + | MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 \ + | MMC_VDD_28_29 | MMC_VDD_29_30 + +static struct msm_mmc_platform_data trout_sdslot_data = { + .ocr_mask = TROUT_MMC_VDD, + .status = trout_sdslot_status, + .translate_vdd = trout_sdslot_switchvdd, +}; + +int __init trout_init_mmc(unsigned int sys_rev) +{ + sdslot_vreg_enabled = 0; + + vreg_sdslot = vreg_get(0, "gp6"); + if (IS_ERR(vreg_sdslot)) + return PTR_ERR(vreg_sdslot); + + set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); + + if (!opt_disable_sdcard) + msm_add_sdcc(2, &trout_sdslot_data, + TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 0); + else + printk(KERN_INFO "trout: SD-Card interface disabled\n"); + return 0; +} + diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index e69a1502e4e..469e0be3499 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -30,6 +30,8 @@ #include "devices.h" #include "board-trout.h" +extern int trout_init_mmc(unsigned int); + static struct platform_device *devices[] __initdata = { &msm_device_uart3, &msm_device_smd, @@ -55,7 +57,16 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags, static void __init trout_init(void) { + int rc; + platform_add_devices(devices, ARRAY_SIZE(devices)); + +#ifdef CONFIG_MMC + rc = trout_init_mmc(system_rev); + if (rc) + printk(KERN_CRIT "%s: MMC init failure (%d)\n", __func__, rc); +#endif + } static struct map_desc trout_io_desc[] __initdata = { diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index 9cb1276ab74..c57210f4f06 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -14,7 +14,6 @@ * */ -#include <linux/version.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index fde9d8f69f1..4e8c0bcdc92 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -322,7 +322,8 @@ static struct platform_device *msm_sdcc_devices[] __initdata = { &msm_device_sdc4, }; -int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat, +int __init msm_add_sdcc(unsigned int controller, + struct msm_mmc_platform_data *plat, unsigned int stat_irq, unsigned long stat_irq_flags) { struct platform_device *pdev; diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h index e302fbdc439..5a79bcf5041 100644 --- a/arch/arm/mach-msm/include/mach/board.h +++ b/arch/arm/mach-msm/include/mach/board.h @@ -18,6 +18,7 @@ #define __ASM_ARCH_MSM_BOARD_H #include <linux/types.h> +#include <mach/mmc.h> /* platform device data structures */ @@ -40,5 +41,8 @@ void __init msm_init_irq(void); void __init msm_init_gpio(void); void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks); void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); +int __init msm_add_sdcc(unsigned int controller, + struct msm_mmc_platform_data *plat, + unsigned int stat_irq, unsigned long stat_irq_flags); #endif diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h index 0ecf2542628..d54b6b086cf 100644 --- a/arch/arm/mach-msm/include/mach/mmc.h +++ b/arch/arm/mach-msm/include/mach/mmc.h @@ -15,7 +15,7 @@ struct embedded_sdio_data { int num_funcs; }; -struct mmc_platform_data { +struct msm_mmc_platform_data { unsigned int ocr_mask; /* available voltages */ u32 (*translate_vdd)(struct device *, unsigned int); unsigned int (*status)(struct device *); diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index cf11d414b42..f07dc7c738f 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c @@ -997,7 +997,7 @@ int smd_core_init(void) return 0; } -static int __init msm_smd_probe(struct platform_device *pdev) +static int __devinit msm_smd_probe(struct platform_device *pdev) { pr_info("smd_init()\n"); diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c index 56b2e26d23b..a5f0174290b 100644 --- a/arch/arm/mach-mx25/mach-cpuimx25.c +++ b/arch/arm/mach-mx25/mach-cpuimx25.c @@ -138,7 +138,7 @@ static void __init eukrea_cpuimx25_init(void) #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg, &otg_pdata); } diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 96aadcadb4f..68879c996a5 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -551,9 +551,9 @@ static void __init armadillo5x0_init(void) /* USB */ #if defined(CONFIG_USB_ULPI) usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg_host, &usbotg_pdata); mxc_register_device(&mxc_usbh2, &usbh2_pdata); diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 63f970f340a..9770a6a973b 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -192,7 +192,7 @@ static void __init mxc_board_init(void) #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg_host, &otg_pdata); } diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 8f66f65e80e..7c37daabb75 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -245,9 +245,9 @@ static struct mxc_usbh_platform_data usbh2_pdata = { static void lilly1131_usb_init(void) { usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_usbh1, &usbh1_pdata); mxc_register_device(&mxc_usbh2, &usbh2_pdata); diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index da236c497d2..f66a9576d8c 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -256,7 +256,7 @@ static void __init mxc_board_init(void) #if defined(CONFIG_USB_ULPI) /* USB */ usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_usbh2, &usbh2_pdata); #endif diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 67776bc61c3..7a075e8bf2d 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -412,7 +412,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = { static int __init moboard_usbh2_init(void) { usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); return mxc_register_device(&mxc_usbh2, &usbh2_pdata); } diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 8a292dd1a71..214de11b20b 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -654,13 +654,13 @@ static void __init mxc_board_init(void) #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg_host, &otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_usbh2, &usbh2_pdata); #endif diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 47f5311b301..28886f0e62f 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -378,7 +378,7 @@ static void __init mxc_board_init(void) #if defined(CONFIG_USB_ULPI) if (otg_mode_host) { otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); mxc_register_device(&mxc_otg_host, &otg_pdata); } diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c index d44ac70222a..c8c380eef74 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -165,6 +165,7 @@ static void qong_nand_select_chip(struct mtd_info *mtd, int chip) static struct platform_nand_data qong_nand_data = { .chip = { + .nr_chips = 1, .chip_delay = 20, .options = 0, }, diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 40c3e7564cb..417757e78c6 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -134,7 +134,7 @@ static struct mxc_usbh_platform_data otg_host_pdata = { static int __init smartbot_otg_host_init(void) { otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, - USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); return mxc_register_device(&mxc_otg_host, &otg_host_pdata); } diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index b18d7c28ab7..3b02d3b944a 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -1,3 +1,7 @@ +if ARCH_OMAP1 + +menu "TI OMAP1 specific features" + comment "OMAP Core Type" depends on ARCH_OMAP1 @@ -224,6 +228,12 @@ config OMAP_ARM_120MHZ help Enable 120MHz clock for OMAP CPU. If unsure, say N. +config OMAP_ARM_96MHZ + bool "OMAP ARM 96 MHz CPU" + depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) + help + Enable 96MHz clock for OMAP CPU. If unsure, say N. + config OMAP_ARM_60MHZ bool "OMAP ARM 60 MHz CPU" depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) @@ -237,3 +247,6 @@ config OMAP_ARM_30MHZ help Enable 30MHz clock for OMAP CPU. If unsure, say N. +endmenu + +endif diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index ea231c7a550..facfaeb1ae5 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -23,6 +23,9 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) led-y := leds.o +usb-fs-$(CONFIG_USB) := usb.o +obj-y += $(usb-fs-m) $(usb-fs-y) + # Specific board support obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 0a9d61d2d22..41992ab7196 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -235,7 +235,7 @@ static void __init ams_delta_init(void) /* Clear latch2 (NAND, LCD, modem enable) */ ams_delta_latch2_write(~0, 0); - omap_usb_init(&ams_delta_usb_config); + omap1_usb_init(&ams_delta_usb_config); platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); #ifdef CONFIG_AMS_DELTA_FIQ diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 059bac60b35..180ce79e5ea 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -292,6 +292,18 @@ static void __init omap_fsample_init(void) omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); + /* Mux pins for keypad */ + omap_cfg_reg(E2_7XX_KBR0); + omap_cfg_reg(J7_7XX_KBR1); + omap_cfg_reg(E1_7XX_KBR2); + omap_cfg_reg(F3_7XX_KBR3); + omap_cfg_reg(D2_7XX_KBR4); + omap_cfg_reg(C2_7XX_KBC0); + omap_cfg_reg(D3_7XX_KBC1); + omap_cfg_reg(E4_7XX_KBC2); + omap_cfg_reg(F4_7XX_KBC3); + omap_cfg_reg(E3_7XX_KBC4); + platform_add_devices(devices, ARRAY_SIZE(devices)); omap_board_config = fsample_config; diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 7a65684d2a1..93b9ab8fc3b 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -72,12 +72,12 @@ static void __init omap_generic_init(void) omap_cfg_reg(UART3_TX); omap_cfg_reg(UART3_RX); - omap_usb_init(&generic1510_usb_config); + omap1_usb_init(&generic1510_usb_config); } #endif #if defined(CONFIG_ARCH_OMAP16XX) if (!cpu_is_omap1510()) { - omap_usb_init(&generic1610_usb_config); + omap1_usb_init(&generic1610_usb_config); } #endif diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 68b2beda8b9..d2cda58bcc4 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -292,15 +292,6 @@ static struct platform_device h2_kp_device = { #define H2_IRDA_FIRSEL_GPIO_PIN 17 -#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) -static int h2_transceiver_mode(struct device *dev, int state) -{ - /* SIR when low, else MIR/FIR when HIGH */ - gpio_set_value(H2_IRDA_FIRSEL_GPIO_PIN, !(state & IR_SIRMODE)); - return 0; -} -#endif - static struct omap_irda_config h2_irda_data = { .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, .rx_channel = OMAP_DMA_UART3_RX, @@ -437,14 +428,18 @@ static void __init h2_init(void) /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ - /* Irda */ -#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) - omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A); - if (gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "IRDA mode") < 0) - BUG(); - gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN, 0); - h2_irda_data.transceiver_mode = h2_transceiver_mode; -#endif + /* Mux pins for keypad */ + omap_cfg_reg(F18_1610_KBC0); + omap_cfg_reg(D20_1610_KBC1); + omap_cfg_reg(D19_1610_KBC2); + omap_cfg_reg(E18_1610_KBC3); + omap_cfg_reg(C21_1610_KBC4); + omap_cfg_reg(G18_1610_KBR0); + omap_cfg_reg(F19_1610_KBR1); + omap_cfg_reg(H14_1610_KBR2); + omap_cfg_reg(E20_1610_KBR3); + omap_cfg_reg(E19_1610_KBR4); + omap_cfg_reg(N19_1610_KBR5); platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); omap_board_config = h2_config; @@ -452,7 +447,7 @@ static void __init h2_init(void) omap_serial_init(); omap_register_i2c_bus(1, 100, h2_i2c_board_info, ARRAY_SIZE(h2_i2c_board_info)); - omap_usb_init(&h2_usb_config); + omap1_usb_init(&h2_usb_config); h2_mmc_init(); } diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 0b0825fe675..c2ef4ff846c 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -397,6 +397,19 @@ static void __init h3_init(void) /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ omap_cfg_reg(V2_1710_GPIO10); + /* Mux pins for keypad */ + omap_cfg_reg(F18_1610_KBC0); + omap_cfg_reg(D20_1610_KBC1); + omap_cfg_reg(D19_1610_KBC2); + omap_cfg_reg(E18_1610_KBC3); + omap_cfg_reg(C21_1610_KBC4); + omap_cfg_reg(G18_1610_KBR0); + omap_cfg_reg(F19_1610_KBR1); + omap_cfg_reg(H14_1610_KBR2); + omap_cfg_reg(E20_1610_KBR3); + omap_cfg_reg(E19_1610_KBR4); + omap_cfg_reg(N19_1610_KBR5); + platform_add_devices(devices, ARRAY_SIZE(devices)); spi_register_board_info(h3_spi_board_info, ARRAY_SIZE(h3_spi_board_info)); @@ -405,7 +418,7 @@ static void __init h3_init(void) omap_serial_init(); omap_register_i2c_bus(1, 100, h3_i2c_board_info, ARRAY_SIZE(h3_i2c_board_info)); - omap_usb_init(&h3_usb_config); + omap1_usb_init(&h3_usb_config); h3_mmc_init(); } diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index d70a4f0923f..311899ff5ff 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -287,7 +287,7 @@ static void __init htcherald_init(void) htcherald_disable_watchdog(); htcherald_usb_enable(); - omap_usb_init(&htcherald_usb_config); + omap1_usb_init(&htcherald_usb_config); } static void __init htcherald_init_irq(void) diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 91064b37859..3daf87ad257 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -422,13 +422,13 @@ static void __init innovator_init(void) #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { - omap_usb_init(&innovator1510_usb_config); + omap1_usb_init(&innovator1510_usb_config); innovator_config[1].data = &innovator1510_lcd_config; } #endif #ifdef CONFIG_ARCH_OMAP16XX if (cpu_is_omap1610()) { - omap_usb_init(&h2_usb_config); + omap1_usb_init(&h2_usb_config); innovator_config[1].data = &innovator1610_lcd_config; } #endif diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8c28b10f3da..51a4539aecf 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -32,7 +32,6 @@ #include <plat/board.h> #include <plat/keypad.h> #include <plat/common.h> -#include <plat/dsp_common.h> #include <plat/hwa742.h> #include <plat/lcd_mipid.h> #include <plat/mmc.h> @@ -242,138 +241,6 @@ static inline void nokia770_mmc_init(void) } #endif -#if defined(CONFIG_OMAP_DSP) -/* - * audio power control - */ -#define HEADPHONE_GPIO 14 -#define AMPLIFIER_CTRL_GPIO 58 - -static struct clk *dspxor_ck; -static DEFINE_MUTEX(audio_pwr_lock); -/* - * audio_pwr_state - * +--+-------------------------+---------------------------------------+ - * |-1|down |power-up request -> 0 | - * +--+-------------------------+---------------------------------------+ - * | 0|up |power-down(1) request -> 1 | - * | | |power-down(2) request -> (ignore) | - * +--+-------------------------+---------------------------------------+ - * | 1|up, |power-up request -> 0 | - * | |received down(1) request |power-down(2) request -> -1 | - * +--+-------------------------+---------------------------------------+ - */ -static int audio_pwr_state = -1; - -static inline void aic23_power_up(void) -{ -} -static inline void aic23_power_down(void) -{ -} - -/* - * audio_pwr_up / down should be called under audio_pwr_lock - */ -static void nokia770_audio_pwr_up(void) -{ - clk_enable(dspxor_ck); - - /* Turn on codec */ - aic23_power_up(); - - if (gpio_get_value(HEADPHONE_GPIO)) - /* HP not connected, turn on amplifier */ - gpio_set_value(AMPLIFIER_CTRL_GPIO, 1); - else - /* HP connected, do not turn on amplifier */ - printk("HP connected\n"); -} - -static void codec_delayed_power_down(struct work_struct *work) -{ - mutex_lock(&audio_pwr_lock); - if (audio_pwr_state == -1) - aic23_power_down(); - clk_disable(dspxor_ck); - mutex_unlock(&audio_pwr_lock); -} - -static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down); - -static void nokia770_audio_pwr_down(void) -{ - /* Turn off amplifier */ - gpio_set_value(AMPLIFIER_CTRL_GPIO, 0); - - /* Turn off codec: schedule delayed work */ - schedule_delayed_work(&codec_power_down_work, HZ / 20); /* 50ms */ -} - -static int -nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage) -{ - mutex_lock(&audio_pwr_lock); - if (audio_pwr_state == -1) - nokia770_audio_pwr_up(); - /* force audio_pwr_state = 0, even if it was 1. */ - audio_pwr_state = 0; - mutex_unlock(&audio_pwr_lock); - return 0; -} - -static int -nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage) -{ - mutex_lock(&audio_pwr_lock); - switch (stage) { - case 1: - if (audio_pwr_state == 0) - audio_pwr_state = 1; - break; - case 2: - if (audio_pwr_state == 1) { - nokia770_audio_pwr_down(); - audio_pwr_state = -1; - } - break; - } - mutex_unlock(&audio_pwr_lock); - return 0; -} - -static struct dsp_kfunc_device nokia770_audio_device = { - .name = "audio", - .type = DSP_KFUNC_DEV_TYPE_AUDIO, - .enable = nokia770_audio_pwr_up_request, - .disable = nokia770_audio_pwr_down_request, -}; - -static __init int omap_dsp_init(void) -{ - int ret; - - dspxor_ck = clk_get(0, "dspxor_ck"); - if (IS_ERR(dspxor_ck)) { - printk(KERN_ERR "couldn't acquire dspxor_ck\n"); - return PTR_ERR(dspxor_ck); - } - - ret = dsp_kfunc_device_register(&nokia770_audio_device); - if (ret) { - printk(KERN_ERR - "KFUNC device registration faild: %s\n", - nokia770_audio_device.name); - goto out; - } - return 0; - out: - return ret; -} -#else -#define omap_dsp_init() do {} while (0) -#endif /* CONFIG_OMAP_DSP */ - static void __init omap_nokia770_init(void) { platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); @@ -382,11 +249,10 @@ static void __init omap_nokia770_init(void) omap_gpio_init(); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); - omap_dsp_init(); hwa742_dev_init(); ads7846_dev_init(); mipid_dev_init(); - omap_usb_init(&nokia770_usb_config); + omap1_usb_init(&nokia770_usb_config); nokia770_mmc_init(); } diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index e2a72af3089..679740cc1e9 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -560,7 +560,7 @@ static void __init osk_init(void) l |= (3 << 1); omap_writel(l, USB_TRANSCEIVER_CTRL); - omap_usb_init(&osk_usb_config); + omap1_usb_init(&osk_usb_config); /* irq for tps65010 chip */ /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 61a2321b973..782bb257a85 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -213,90 +213,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = { .ctrl_name = "internal", }; -#ifdef CONFIG_APM -/* - * Values measured in 10 minute intervals averaged over 10 samples. - * May differ slightly from device to device but should be accurate - * enough to give basic idea of battery life left and trigger - * potential alerts. - */ -static const int palmte_battery_sample[] = { - 2194, 2157, 2138, 2120, - 2104, 2089, 2075, 2061, - 2048, 2038, 2026, 2016, - 2008, 1998, 1989, 1980, - 1970, 1958, 1945, 1928, - 1910, 1888, 1860, 1827, - 1791, 1751, 1709, 1656, -}; - -#define INTERVAL 10 -#define BATTERY_HIGH_TRESHOLD 66 -#define BATTERY_LOW_TRESHOLD 33 - -static void palmte_get_power_status(struct apm_power_info *info, int *battery) -{ - int charging, batt, hi, lo, mid; - - charging = !gpio_get_value(PALMTE_DC_GPIO); - batt = battery[0]; - if (charging) - batt -= 60; - - hi = ARRAY_SIZE(palmte_battery_sample); - lo = 0; - - info->battery_flag = 0; - info->units = APM_UNITS_MINS; - - if (batt > palmte_battery_sample[lo]) { - info->battery_life = 100; - info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample); - } else if (batt <= palmte_battery_sample[hi - 1]) { - info->battery_life = 0; - info->time = 0; - } else { - while (hi > lo + 1) { - mid = (hi + lo) >> 1; - if (batt <= palmte_battery_sample[mid]) - lo = mid; - else - hi = mid; - } - - mid = palmte_battery_sample[lo] - palmte_battery_sample[hi]; - hi = palmte_battery_sample[lo] - batt; - info->battery_life = 100 - (100 * lo + 100 * hi / mid) / - ARRAY_SIZE(palmte_battery_sample); - info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) - - lo) - INTERVAL * hi / mid; - } - - if (charging) { - info->ac_line_status = APM_AC_ONLINE; - info->battery_status = APM_BATTERY_STATUS_CHARGING; - info->battery_flag |= APM_BATTERY_FLAG_CHARGING; - } else { - info->ac_line_status = APM_AC_OFFLINE; - if (info->battery_life > BATTERY_HIGH_TRESHOLD) - info->battery_status = APM_BATTERY_STATUS_HIGH; - else if (info->battery_life > BATTERY_LOW_TRESHOLD) - info->battery_status = APM_BATTERY_STATUS_LOW; - else - info->battery_status = APM_BATTERY_STATUS_CRITICAL; - } - - if (info->battery_life > BATTERY_HIGH_TRESHOLD) - info->battery_flag |= APM_BATTERY_FLAG_HIGH; - else if (info->battery_life > BATTERY_LOW_TRESHOLD) - info->battery_flag |= APM_BATTERY_FLAG_LOW; - else - info->battery_flag |= APM_BATTERY_FLAG_CRITICAL; -} -#else -#define palmte_get_power_status NULL -#endif - static struct omap_board_config_kernel palmte_config[] __initdata = { { OMAP_TAG_LCD, &palmte_lcd_config }, }; @@ -359,7 +275,7 @@ static void __init omap_palmte_init(void) spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); palmte_misc_gpio_setup(); omap_serial_init(); - omap_usb_init(&palmte_usb_config); + omap1_usb_init(&palmte_usb_config); omap_register_i2c_bus(1, 100, NULL, 0); } diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 21c01c6afcc..0b35ef54a64 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -307,7 +307,7 @@ static void __init omap_palmtt_init(void) spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); omap_serial_init(); - omap_usb_init(&palmtt_usb_config); + omap1_usb_init(&palmtt_usb_config); omap_register_i2c_bus(1, 100, NULL, 0); } diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index f3249245153..66362903b6e 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -325,7 +325,7 @@ omap_palmz71_init(void) spi_register_board_info(palmz71_boardinfo, ARRAY_SIZE(palmz71_boardinfo)); - omap_usb_init(&palmz71_usb_config); + omap1_usb_init(&palmz71_usb_config); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); palmz71_gpio_setup(0); diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 8b5ab1fcc40..34ab354758b 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -260,6 +260,18 @@ static void __init omap_perseus2_init(void) omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); + /* Mux pins for keypad */ + omap_cfg_reg(E2_7XX_KBR0); + omap_cfg_reg(J7_7XX_KBR1); + omap_cfg_reg(E1_7XX_KBR2); + omap_cfg_reg(F3_7XX_KBR3); + omap_cfg_reg(D2_7XX_KBR4); + omap_cfg_reg(C2_7XX_KBC0); + omap_cfg_reg(D3_7XX_KBC1); + omap_cfg_reg(E4_7XX_KBC2); + omap_cfg_reg(F4_7XX_KBC3); + omap_cfg_reg(E3_7XX_KBC4); + platform_add_devices(devices, ARRAY_SIZE(devices)); omap_board_config = perseus2_config; diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 995566b862b..2eb148b8de9 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -392,7 +392,7 @@ static void __init omap_sx1_init(void) omap_board_config_size = ARRAY_SIZE(sx1_config); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); - omap_usb_init(&sx1_usb_config); + omap1_usb_init(&sx1_usb_config); sx1_mmc_init(); /* turn on USB power */ diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 4c483dc1de5..6b3cf14bc75 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -198,7 +198,7 @@ static void __init voiceblue_init(void) omap_board_config = voiceblue_config; omap_board_config_size = ARRAY_SIZE(voiceblue_config); omap_serial_init(); - omap_usb_init(&voiceblue_usb_config); + omap1_usb_init(&voiceblue_usb_config); omap_register_i2c_bus(1, 100, NULL, 0); /* There is a good chance board is going up, so enable power LED diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 6bbb1b8b829..b8c7fb9d792 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -11,7 +11,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <linux/module.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/errno.h> @@ -34,9 +33,9 @@ __u32 arm_idlect1_mask; struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; -/*------------------------------------------------------------------------- +/* * Omap1 specific clock functions - *-------------------------------------------------------------------------*/ + */ unsigned long omap1_uart_recalc(struct clk *clk) { @@ -523,7 +522,8 @@ const struct clkops clkops_dspck = { .disable = omap1_clk_disable_dsp_domain, }; -static int omap1_clk_enable_uart_functional(struct clk *clk) +/* XXX SYSC register handling does not belong in the clock framework */ +static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) { int ret; struct uart_clk *uclk; @@ -539,7 +539,8 @@ static int omap1_clk_enable_uart_functional(struct clk *clk) return ret; } -static void omap1_clk_disable_uart_functional(struct clk *clk) +/* XXX SYSC register handling does not belong in the clock framework */ +static void omap1_clk_disable_uart_functional_16xx(struct clk *clk) { struct uart_clk *uclk; @@ -550,9 +551,10 @@ static void omap1_clk_disable_uart_functional(struct clk *clk) omap1_clk_disable_generic(clk); } -const struct clkops clkops_uart = { - .enable = omap1_clk_enable_uart_functional, - .disable = omap1_clk_disable_uart_functional, +/* XXX SYSC register handling does not belong in the clock framework */ +const struct clkops clkops_uart_16xx = { + .enable = omap1_clk_enable_uart_functional_16xx, + .disable = omap1_clk_disable_uart_functional_16xx, }; long omap1_clk_round_rate(struct clk *clk, unsigned long rate) @@ -572,9 +574,9 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate) return ret; } -/*------------------------------------------------------------------------- +/* * Omap1 clock reset and init functions - *-------------------------------------------------------------------------*/ + */ #ifdef CONFIG_OMAP_RESET_CLOCKS diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 75d0d7d90bf..eaf09efb91c 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -107,7 +107,7 @@ extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; extern const struct clkops clkops_dspck; extern const struct clkops clkops_dummy; -extern const struct clkops clkops_uart; +extern const struct clkops clkops_uart_16xx; extern const struct clkops clkops_generic; #endif diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index aa8558adbf1..af54114b8f0 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -8,6 +8,10 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * To do: + * - Clocks that are only available on some chips should be marked with the + * chips that they are present on. */ #include <linux/kernel.h> @@ -23,9 +27,49 @@ #include "clock.h" -/*------------------------------------------------------------------------ +/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ +#define IDL_CLKOUT_ARM_SHIFT 12 +#define IDLTIM_ARM_SHIFT 9 +#define IDLAPI_ARM_SHIFT 8 +#define IDLIF_ARM_SHIFT 6 +#define IDLLB_ARM_SHIFT 4 /* undocumented? */ +#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ +#define IDLPER_ARM_SHIFT 2 +#define IDLXORP_ARM_SHIFT 1 +#define IDLWDT_ARM_SHIFT 0 + +/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ +#define CONF_MOD_UART3_CLK_MODE_R 31 +#define CONF_MOD_UART2_CLK_MODE_R 30 +#define CONF_MOD_UART1_CLK_MODE_R 29 +#define CONF_MOD_MMC_SD_CLK_REQ_R 23 +#define CONF_MOD_MCBSP3_AUXON 20 + +/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ +#define CONF_MOD_SOSSI_CLK_EN_R 16 + +/* Some OTG_SYSCON_2-specific bit fields */ +#define OTG_SYSCON_2_UHOST_EN_SHIFT 8 + +/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ +#define SOFT_MMC2_DPLL_REQ_SHIFT 13 +#define SOFT_MMC_DPLL_REQ_SHIFT 12 +#define SOFT_UART3_DPLL_REQ_SHIFT 11 +#define SOFT_UART2_DPLL_REQ_SHIFT 10 +#define SOFT_UART1_DPLL_REQ_SHIFT 9 +#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 +#define SOFT_CAM_DPLL_REQ_SHIFT 7 +#define SOFT_COM_MCKO_REQ_SHIFT 6 +#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ +#define USB_REQ_EN_SHIFT 4 +#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ +#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ +#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ +#define SOFT_DPLL_REQ_SHIFT 0 + +/* * Omap1 clocks - *-------------------------------------------------------------------------*/ + */ static struct clk ck_ref = { .name = "ck_ref", @@ -54,7 +98,7 @@ static struct arm_idlect1_clk ck_dpll1out = { .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, }, - .idlect_shift = 12, + .idlect_shift = IDL_CLKOUT_ARM_SHIFT, }; static struct clk sossi_ck = { @@ -63,7 +107,7 @@ static struct clk sossi_ck = { .parent = &ck_dpll1out.clk, .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), - .enable_bit = 16, + .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, .recalc = &omap1_sossi_recalc, .set_rate = &omap1_set_sossi_rate, }; @@ -91,7 +135,7 @@ static struct arm_idlect1_clk armper_ck = { .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }, - .idlect_shift = 2, + .idlect_shift = IDLPER_ARM_SHIFT, }; /* @@ -118,7 +162,7 @@ static struct arm_idlect1_clk armxor_ck = { .enable_bit = EN_XORPCK, .recalc = &followparent_recalc, }, - .idlect_shift = 1, + .idlect_shift = IDLXORP_ARM_SHIFT, }; static struct arm_idlect1_clk armtim_ck = { @@ -131,7 +175,7 @@ static struct arm_idlect1_clk armtim_ck = { .enable_bit = EN_TIMCK, .recalc = &followparent_recalc, }, - .idlect_shift = 9, + .idlect_shift = IDLTIM_ARM_SHIFT, }; static struct arm_idlect1_clk armwdt_ck = { @@ -145,7 +189,7 @@ static struct arm_idlect1_clk armwdt_ck = { .fixed_div = 14, .recalc = &omap_fixed_divisor_recalc, }, - .idlect_shift = 0, + .idlect_shift = IDLWDT_ARM_SHIFT, }; static struct clk arminth_ck16xx = { @@ -212,7 +256,6 @@ static struct clk dsptim_ck = { .recalc = &followparent_recalc, }; -/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ static struct arm_idlect1_clk tc_ck = { .clk = { .name = "tc_ck", @@ -224,7 +267,7 @@ static struct arm_idlect1_clk tc_ck = { .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }, - .idlect_shift = 6, + .idlect_shift = IDLIF_ARM_SHIFT, }; static struct clk arminth_ck1510 = { @@ -304,7 +347,7 @@ static struct arm_idlect1_clk api_ck = { .enable_bit = EN_APICK, .recalc = &followparent_recalc, }, - .idlect_shift = 8, + .idlect_shift = IDLAPI_ARM_SHIFT, }; static struct arm_idlect1_clk lb_ck = { @@ -317,7 +360,7 @@ static struct arm_idlect1_clk lb_ck = { .enable_bit = EN_LBCK, .recalc = &followparent_recalc, }, - .idlect_shift = 4, + .idlect_shift = IDLLB_ARM_SHIFT, }; static struct clk rhea1_ck = { @@ -359,9 +402,15 @@ static struct arm_idlect1_clk lcd_ck_1510 = { .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }, - .idlect_shift = 3, + .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, }; +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX does this need SYSC register handling? + */ static struct clk uart1_1510 = { .name = "uart1_ck", .ops = &clkops_null, @@ -370,25 +419,37 @@ static struct clk uart1_1510 = { .rate = 12000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ + .enable_bit = CONF_MOD_UART1_CLK_MODE_R, .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, }; +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX SYSC register handling does not belong in the clock framework + */ static struct uart_clk uart1_16xx = { .clk = { .name = "uart1_ck", - .ops = &clkops_uart, + .ops = &clkops_uart_16xx, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 29, + .enable_bit = CONF_MOD_UART1_CLK_MODE_R, }, .sysc_addr = 0xfffb0054, }; +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX does this need SYSC register handling? + */ static struct clk uart2_ck = { .name = "uart2_ck", .ops = &clkops_null, @@ -397,11 +458,17 @@ static struct clk uart2_ck = { .rate = 12000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ + .enable_bit = CONF_MOD_UART2_CLK_MODE_R, .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, }; +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX does this need SYSC register handling? + */ static struct clk uart3_1510 = { .name = "uart3_ck", .ops = &clkops_null, @@ -410,21 +477,27 @@ static struct clk uart3_1510 = { .rate = 12000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ + .enable_bit = CONF_MOD_UART3_CLK_MODE_R, .set_rate = &omap1_set_uart_rate, .recalc = &omap1_uart_recalc, }; +/* + * XXX The enable_bit here is misused - it simply switches between 12MHz + * and 48MHz. Reimplement with clksel. + * + * XXX SYSC register handling does not belong in the clock framework + */ static struct uart_clk uart3_16xx = { .clk = { .name = "uart3_ck", - .ops = &clkops_uart, + .ops = &clkops_uart_16xx, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 31, + .enable_bit = CONF_MOD_UART3_CLK_MODE_R, }, .sysc_addr = 0xfffb9854, }; @@ -457,7 +530,7 @@ static struct clk usb_hhc_ck16xx = { /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ .flags = ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ - .enable_bit = 8 /* UHOST_EN */, + .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT }; static struct clk usb_dc_ck = { @@ -466,7 +539,7 @@ static struct clk usb_dc_ck = { /* Direct from ULPD, no parent */ .rate = 48000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 4, + .enable_bit = USB_REQ_EN_SHIFT, }; static struct clk usb_dc_ck7xx = { @@ -475,7 +548,25 @@ static struct clk usb_dc_ck7xx = { /* Direct from ULPD, no parent */ .rate = 48000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 8, + .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, +}; + +static struct clk uart1_7xx = { + .name = "uart1_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 12000000, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 9, +}; + +static struct clk uart2_7xx = { + .name = "uart2_ck", + .ops = &clkops_generic, + /* Direct from ULPD, no parent */ + .rate = 12000000, + .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), + .enable_bit = 11, }; static struct clk mclk_1510 = { @@ -484,7 +575,7 @@ static struct clk mclk_1510 = { /* Direct from ULPD, no parent. May be enabled by ext hardware. */ .rate = 12000000, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 6, + .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, }; static struct clk mclk_16xx = { @@ -524,9 +615,13 @@ static struct clk mmc1_ck = { .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), - .enable_bit = 23, + .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, }; +/* + * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as + * CONF_MOD_MCBSP3_AUXON ?? + */ static struct clk mmc2_ck = { .name = "mmc2_ck", .ops = &clkops_generic, @@ -546,7 +641,7 @@ static struct clk mmc3_ck = { .rate = 48000000, .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = 12, + .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, }; static struct clk virtual_ck_mpu = { @@ -620,7 +715,9 @@ static struct omap_clk omap_clks[] = { /* ULPD clocks */ CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), + CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), + CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 379100c1763..aa0725608fb 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -63,44 +63,7 @@ static void omap_init_rtc(void) static inline void omap_init_rtc(void) {} #endif -#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) - -#if defined(CONFIG_ARCH_OMAP15XX) -# define OMAP1_MBOX_SIZE 0x23 -# define INT_DSP_MAILBOX1 INT_1510_DSP_MAILBOX1 -#elif defined(CONFIG_ARCH_OMAP16XX) -# define OMAP1_MBOX_SIZE 0x2f -# define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 -#endif - -#define OMAP1_MBOX_BASE OMAP16XX_MAILBOX_BASE - -static struct resource mbox_resources[] = { - { - .start = OMAP1_MBOX_BASE, - .end = OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_DSP_MAILBOX1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mbox_device = { - .name = "omap1-mailbox", - .id = -1, - .num_resources = ARRAY_SIZE(mbox_resources), - .resource = mbox_resources, -}; - -static inline void omap_init_mbox(void) -{ - platform_device_register(&mbox_device); -} -#else static inline void omap_init_mbox(void) { } -#endif /*-------------------------------------------------------------------------*/ @@ -230,42 +193,7 @@ static inline void omap_init_spi100k(void) /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_OMAP_STI) - -#define OMAP1_STI_BASE 0xfffea000 -#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400) - -static struct resource sti_resources[] = { - { - .start = OMAP1_STI_BASE, - .end = OMAP1_STI_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP1_STI_CHANNEL_BASE, - .end = OMAP1_STI_CHANNEL_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_1610_STI, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device sti_device = { - .name = "sti", - .id = -1, - .num_resources = ARRAY_SIZE(sti_resources), - .resource = sti_resources, -}; - -static inline void omap_init_sti(void) -{ - platform_device_register(&sti_device); -} -#else static inline void omap_init_sti(void) {} -#endif /*-------------------------------------------------------------------------*/ diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index e8a8cf36b7f..671408eb4ab 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -33,7 +33,7 @@ omap_uart_virt: .word 0x0 /* Use omap_uart_phys/virt if already configured */ 9: mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =omap_uart_phys @ physical base address + ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address ldrne \rx, =omap_uart_virt @ virtual base ldr \rx, [\rx, #0] cmp \rx, #0 @ is port configured? @@ -68,11 +68,15 @@ omap_uart_virt: .word 0x0 /* Store both phys and virt address for the uart */ 98: add \rx, \rx, #0xff000000 @ phys base - ldr \tmp, =omap_uart_phys + mrc p15, 0, \tmp, c1, c0 + tst \tmp, #1 @ MMU enabled? + ldreq \tmp, =__virt_to_phys(omap_uart_phys) + ldrne \tmp, =omap_uart_phys str \rx, [\tmp, #0] sub \rx, \rx, #0xff000000 @ phys base add \rx, \rx, #0xfe000000 @ virt base - ldr \tmp, =omap_uart_virt + ldreq \tmp, =__virt_to_phys(omap_uart_virt) + ldrne \tmp, =omap_uart_virt str \rx, [\tmp, #0] b 9b 99: diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 4f5b3da3d55..1a85a421007 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -1,5 +1,5 @@ /* - * Mailbox reservation modules for DSP + * Mailbox reservation modules for OMAP1 * * Copyright (C) 2006-2009 Nokia Corporation * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> @@ -9,13 +9,10 @@ * for more details. */ -#include <linux/kernel.h> -#include <linux/resource.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> #include <plat/mailbox.h> -#include <mach/irqs.h> #define MAILBOX_ARM2DSP1 0x00 #define MAILBOX_ARM2DSP1b 0x04 @@ -83,7 +80,7 @@ static int omap1_mbox_fifo_full(struct omap_mbox *mbox) struct omap_mbox1_fifo *fifo = &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; - return (mbox_read_reg(fifo->flag)); + return mbox_read_reg(fifo->flag); } /* irq */ @@ -141,47 +138,37 @@ struct omap_mbox mbox_dsp_info = { .ops = &omap1_mbox_ops, .priv = &omap1_mbox_dsp_priv, }; -EXPORT_SYMBOL(mbox_dsp_info); + +struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; static int __devinit omap1_mbox_probe(struct platform_device *pdev) { - struct resource *res; + struct resource *mem; + int ret; + int i; + struct omap_mbox **list; - if (pdev->num_resources != 2) { - dev_err(&pdev->dev, "invalid number of resources: %d\n", - pdev->num_resources); - return -ENODEV; - } + list = omap1_mboxes; + list[0]->irq = platform_get_irq_byname(pdev, "dsp"); - /* MBOX base */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid mem resource\n"); - return -ENODEV; - } + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox_base = ioremap(mem->start, resource_size(mem)); + if (!mbox_base) + return -ENOMEM; - mbox_base = ioremap(res->start, resource_size(res)); - if (!mbox_base) { - dev_err(&pdev->dev, "ioremap failed\n"); - return -ENODEV; - } - - /* DSP IRQ */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid irq resource\n"); + ret = omap_mbox_register(&pdev->dev, list); + if (ret) { iounmap(mbox_base); - return -ENODEV; + return ret; } - mbox_dsp_info.irq = res->start; - return omap_mbox_register(&pdev->dev, &mbox_dsp_info); + return 0; } static int __devexit omap1_mbox_remove(struct platform_device *pdev) { - omap_mbox_unregister(&mbox_dsp_info); - + omap_mbox_unregister(); + iounmap(mbox_base); return 0; } @@ -189,7 +176,7 @@ static struct platform_driver omap1_mbox_driver = { .probe = omap1_mbox_probe, .remove = __devexit_p(omap1_mbox_remove), .driver = { - .name = "omap1-mailbox", + .name = "omap-mailbox", }, }; diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index e9bdff192f8..b3a796a6da0 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -23,7 +23,6 @@ #include <plat/mux.h> #include <plat/cpu.h> #include <plat/mcbsp.h> -#include <plat/dsp_common.h> #define DPS_RSTCT2_PER_EN (1 << 0) #define DSP_RSTCT2_WD_PER_EN (1 << 1) @@ -46,7 +45,6 @@ static void omap1_mcbsp_request(unsigned int id) clk_enable(api_clk); clk_enable(dsp_clk); - omap_dsp_request_mem(); /* * DSP external peripheral reset * FIXME: This should be moved to dsp code @@ -62,7 +60,6 @@ static void omap1_mcbsp_free(unsigned int id) { if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { if (--dsp_use == 0) { - omap_dsp_release_mem(); if (!IS_ERR(api_clk)) { clk_disable(api_clk); clk_put(api_clk); diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 84341377232..7835add0034 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -70,6 +70,10 @@ MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0) MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0) MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0) MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0) + +/* UART pins */ +MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0) +MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0) }; #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) #else @@ -440,7 +444,7 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) } #endif -#ifdef CONFIG_OMAP_MUX_ERRORS +#ifdef CONFIG_OMAP_MUX_WARNINGS return warn ? -ETXTBSY : 0; #else return 0; diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 349de90194e..b78d0749f13 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -122,6 +122,13 @@ void __init omap_serial_init(void) for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) { + /* Don't look at UARTs higher than 2 for omap7xx */ + if (cpu_is_omap7xx() && i > 1) { + serial_platform_data[i].membase = NULL; + serial_platform_data[i].mapbase = 0; + continue; + } + /* Static mapping, never released */ serial_platform_data[i].membase = ioremap(serial_platform_data[i].mapbase, SZ_2K); diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c new file mode 100644 index 00000000000..19de03b074e --- /dev/null +++ b/arch/arm/mach-omap1/usb.c @@ -0,0 +1,530 @@ +/* + * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx + * + * Copyright (C) 2004 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <asm/irq.h> + +#include <plat/mux.h> +#include <plat/usb.h> + +/* These routines should handle the standard chip-specific modes + * for usb0/1/2 ports, covering basic mux and transceiver setup. + * + * Some board-*.c files will need to set up additional mux options, + * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. + */ + +/* TESTED ON: + * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables + * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables + * - 5912 OSK UDC, with *nonstandard* A-to-A cable + * - 1510 Innovator UDC with bundled usb0 cable + * - 1510 Innovator OHCI with bundled usb1/usb2 cable + * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS + * - 1710 custom development board using alternate pin group + * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables + */ + +#define INT_USB_IRQ_GEN IH2_BASE + 20 +#define INT_USB_IRQ_NISO IH2_BASE + 30 +#define INT_USB_IRQ_ISO IH2_BASE + 29 +#define INT_USB_IRQ_HGEN INT_USB_HHC_1 +#define INT_USB_IRQ_OTG IH2_BASE + 8 + +#ifdef CONFIG_USB_GADGET_OMAP + +static struct resource udc_resources[] = { + /* order is significant! */ + { /* registers */ + .start = UDC_BASE, + .end = UDC_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { /* general IRQ */ + .start = INT_USB_IRQ_GEN, + .flags = IORESOURCE_IRQ, + }, { /* PIO IRQ */ + .start = INT_USB_IRQ_NISO, + .flags = IORESOURCE_IRQ, + }, { /* SOF IRQ */ + .start = INT_USB_IRQ_ISO, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 udc_dmamask = ~(u32)0; + +static struct platform_device udc_device = { + .name = "omap_udc", + .id = -1, + .dev = { + .dma_mask = &udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(udc_resources), + .resource = udc_resources, +}; + +static inline void udc_device_init(struct omap_usb_config *pdata) +{ + /* IRQ numbers for omap7xx */ + if(cpu_is_omap7xx()) { + udc_resources[1].start = INT_7XX_USB_GENI; + udc_resources[2].start = INT_7XX_USB_NON_ISO; + udc_resources[3].start = INT_7XX_USB_ISO; + } + pdata->udc_device = &udc_device; +} + +#else + +static inline void udc_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = ~(u32)0; + +static struct resource ohci_resources[] = { + { + .start = OMAP_OHCI_BASE, + .end = OMAP_OHCI_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_IRQ_HGEN, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci_device = { + .name = "ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(ohci_resources), + .resource = ohci_resources, +}; + +static inline void ohci_device_init(struct omap_usb_config *pdata) +{ + if (cpu_is_omap7xx()) + ohci_resources[1].start = INT_7XX_USB_HHC_1; + pdata->ohci_device = &ohci_device; +} + +#else + +static inline void ohci_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) + +static struct resource otg_resources[] = { + /* order is significant! */ + { + .start = OTG_BASE, + .end = OTG_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = INT_USB_IRQ_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device otg_device = { + .name = "omap_otg", + .id = -1, + .num_resources = ARRAY_SIZE(otg_resources), + .resource = otg_resources, +}; + +static inline void otg_device_init(struct omap_usb_config *pdata) +{ + if (cpu_is_omap7xx()) + otg_resources[1].start = INT_7XX_USB_OTG; + pdata->otg_device = &otg_device; +} + +#else + +static inline void otg_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) +{ + u32 syscon1 = 0; + + if (nwires == 0) { + if (!cpu_is_omap15xx()) { + u32 l; + + /* pulldown D+/D- */ + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~(3 << 1); + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + return 0; + } + + if (is_device) { + if (cpu_is_omap7xx()) { + omap_cfg_reg(AA17_7XX_USB_DM); + omap_cfg_reg(W16_7XX_USB_PU_EN); + omap_cfg_reg(W17_7XX_USB_VBUSI); + omap_cfg_reg(W18_7XX_USB_DMCK_OUT); + omap_cfg_reg(W19_7XX_USB_DCRST); + } else + omap_cfg_reg(W4_USB_PUEN); + } + + if (nwires == 2) { + u32 l; + + // omap_cfg_reg(P9_USB_DP); + // omap_cfg_reg(R8_USB_DM); + + if (cpu_is_omap15xx()) { + /* This works on 1510-Innovator */ + return 0; + } + + /* NOTES: + * - peripheral should configure VBUS detection! + * - only peripherals may use the internal D+/D- pulldowns + * - OTG support on this port not yet written + */ + + /* Don't do this for omap7xx -- it causes USB to not work correctly */ + if (!cpu_is_omap7xx()) { + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~(7 << 4); + if (!is_device) + l |= (3 << 1); + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + + return 3 << 16; + } + + /* alternate pin config, external transceiver */ + if (cpu_is_omap15xx()) { + printk(KERN_ERR "no usb0 alt pin config on 15xx\n"); + return 0; + } + + omap_cfg_reg(V6_USB0_TXD); + omap_cfg_reg(W9_USB0_TXEN); + omap_cfg_reg(W5_USB0_SE0); + if (nwires != 3) + omap_cfg_reg(Y5_USB0_RCV); + + /* NOTE: SPEED and SUSP aren't configured here. OTG hosts + * may be able to use I2C requests to set those bits along + * with VBUS switching and overcurrent detection. + */ + + if (nwires != 6) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + + switch (nwires) { + case 3: + syscon1 = 2; + break; + case 4: + syscon1 = 1; + break; + case 6: + syscon1 = 3; + { + u32 l; + + omap_cfg_reg(AA9_USB0_VP); + omap_cfg_reg(R9_USB0_VM); + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + break; + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 0, nwires); + } + + return syscon1 << 16; +} + +u32 __init omap1_usb1_init(unsigned nwires) +{ + u32 syscon1 = 0; + + if (!cpu_is_omap15xx() && nwires != 6) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~CONF_USB1_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + if (nwires == 0) + return 0; + + /* external transceiver */ + omap_cfg_reg(USB1_TXD); + omap_cfg_reg(USB1_TXEN); + if (nwires != 3) + omap_cfg_reg(USB1_RCV); + + if (cpu_is_omap15xx()) { + omap_cfg_reg(USB1_SEO); + omap_cfg_reg(USB1_SPEED); + // SUSP + } else if (cpu_is_omap1610() || cpu_is_omap5912()) { + omap_cfg_reg(W13_1610_USB1_SE0); + omap_cfg_reg(R13_1610_USB1_SPEED); + // SUSP + } else if (cpu_is_omap1710()) { + omap_cfg_reg(R13_1710_USB1_SE0); + // SUSP + } else { + pr_debug("usb%d cpu unrecognized\n", 1); + return 0; + } + + switch (nwires) { + case 2: + goto bad; + case 3: + syscon1 = 2; + break; + case 4: + syscon1 = 1; + break; + case 6: + syscon1 = 3; + omap_cfg_reg(USB1_VP); + omap_cfg_reg(USB1_VM); + if (!cpu_is_omap15xx()) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= CONF_USB1_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + break; + default: +bad: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 1, nwires); + } + + return syscon1 << 20; +} + +u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) +{ + u32 syscon1 = 0; + + /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ + if (alt_pingroup || nwires == 0) + return 0; + + if (!cpu_is_omap15xx() && nwires != 6) { + u32 l; + + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + + /* external transceiver */ + if (cpu_is_omap15xx()) { + omap_cfg_reg(USB2_TXD); + omap_cfg_reg(USB2_TXEN); + omap_cfg_reg(USB2_SEO); + if (nwires != 3) + omap_cfg_reg(USB2_RCV); + /* there is no USB2_SPEED */ + } else if (cpu_is_omap16xx()) { + omap_cfg_reg(V6_USB2_TXD); + omap_cfg_reg(W9_USB2_TXEN); + omap_cfg_reg(W5_USB2_SE0); + if (nwires != 3) + omap_cfg_reg(Y5_USB2_RCV); + // FIXME omap_cfg_reg(USB2_SPEED); + } else { + pr_debug("usb%d cpu unrecognized\n", 1); + return 0; + } + + // omap_cfg_reg(USB2_SUSP); + + switch (nwires) { + case 2: + goto bad; + case 3: + syscon1 = 2; + break; + case 4: + syscon1 = 1; + break; + case 5: + goto bad; + case 6: + syscon1 = 3; + if (cpu_is_omap15xx()) { + omap_cfg_reg(USB2_VP); + omap_cfg_reg(USB2_VM); + } else { + u32 l; + + omap_cfg_reg(AA9_USB2_VP); + omap_cfg_reg(R9_USB2_VM); + l = omap_readl(USB_TRANSCEIVER_CTRL); + l |= CONF_USB2_UNI_R; + omap_writel(l, USB_TRANSCEIVER_CTRL); + } + break; + default: +bad: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 2, nwires); + } + + return syscon1 << 24; +} + +#ifdef CONFIG_ARCH_OMAP15XX + +/* ULPD_DPLL_CTRL */ +#define DPLL_IOB (1 << 13) +#define DPLL_PLL_ENABLE (1 << 4) +#define DPLL_LOCK (1 << 0) + +/* ULPD_APLL_CTRL */ +#define APLL_NDPLL_SWITCH (1 << 0) + +static void __init omap_1510_usb_init(struct omap_usb_config *config) +{ + unsigned int val; + u16 w; + + config->usb0_init(config->pins[0], is_usb0_device(config)); + config->usb1_init(config->pins[1]); + config->usb2_init(config->pins[2], 0); + + val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1); + val |= (config->hmc_mode << 1); + omap_writel(val, MOD_CONF_CTRL_0); + + printk("USB: hmc %d", config->hmc_mode); + if (config->pins[0]) + printk(", usb0 %d wires%s", config->pins[0], + is_usb0_device(config) ? " (dev)" : ""); + if (config->pins[1]) + printk(", usb1 %d wires", config->pins[1]); + if (config->pins[2]) + printk(", usb2 %d wires", config->pins[2]); + printk("\n"); + + /* use DPLL for 48 MHz function clock */ + pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), + omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ)); + + w = omap_readw(ULPD_APLL_CTRL); + w &= ~APLL_NDPLL_SWITCH; + omap_writew(w, ULPD_APLL_CTRL); + + w = omap_readw(ULPD_DPLL_CTRL); + w |= DPLL_IOB | DPLL_PLL_ENABLE; + omap_writew(w, ULPD_DPLL_CTRL); + + w = omap_readw(ULPD_SOFT_REQ); + w |= SOFT_UDC_REQ | SOFT_DPLL_REQ; + omap_writew(w, ULPD_SOFT_REQ); + + while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) + cpu_relax(); + +#ifdef CONFIG_USB_GADGET_OMAP + if (config->register_dev) { + int status; + + udc_device.dev.platform_data = config; + status = platform_device_register(&udc_device); + if (status) + pr_debug("can't register UDC device, %d\n", status); + /* udc driver gates 48MHz by D+ pullup */ + } +#endif + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + if (config->register_host) { + int status; + + ohci_device.dev.platform_data = config; + status = platform_device_register(&ohci_device); + if (status) + pr_debug("can't register OHCI device, %d\n", status); + /* hcd explicitly gates 48MHz */ + } +#endif +} + +#else +static inline void omap_1510_usb_init(struct omap_usb_config *config) {} +#endif + +void __init omap1_usb_init(struct omap_usb_config *pdata) +{ + pdata->usb0_init = omap1_usb0_init; + pdata->usb1_init = omap1_usb1_init; + pdata->usb2_init = omap1_usb2_init; + udc_device_init(pdata); + ohci_device_init(pdata); + otg_device_init(pdata); + + if (cpu_is_omap7xx() || cpu_is_omap16xx()) + omap_otg_init(pdata); + else if (cpu_is_omap15xx()) + omap_1510_usb_init(pdata); + else + printk(KERN_ERR "USB: No init for your chip yet\n"); +} diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b31b6f12312..b48bacf0a7a 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -1,22 +1,77 @@ +if ARCH_OMAP2PLUS + +menu "TI OMAP2/3/4 Specific Features" + +config ARCH_OMAP2PLUS_TYPICAL + bool "Typical OMAP configuration" + default y + select AEABI + select REGULATOR + select PM + select PM_RUNTIME + select VFP + select NEON if ARCH_OMAP3 || ARCH_OMAP4 + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE + select I2C + select I2C_OMAP + select MFD + select MENELAUS if ARCH_OMAP2 + select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 + select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 + help + Compile a kernel suitable for booting most boards + +config ARCH_OMAP2 + bool "TI OMAP2" + depends on ARCH_OMAP2PLUS + default y + select CPU_V6 + +config ARCH_OMAP3 + bool "TI OMAP3" + depends on ARCH_OMAP2PLUS + default y + select CPU_V7 + select USB_ARCH_HAS_EHCI + select ARM_L1_CACHE_SHIFT_6 + +config ARCH_OMAP4 + bool "TI OMAP4" + default y + depends on ARCH_OMAP2PLUS + select CPU_V7 + select ARM_GIC + comment "OMAP Core Type" depends on ARCH_OMAP2 config ARCH_OMAP2420 bool "OMAP2420 support" depends on ARCH_OMAP2 + default y select OMAP_DM_TIMER select ARCH_OMAP_OTG config ARCH_OMAP2430 bool "OMAP2430 support" depends on ARCH_OMAP2 + default y select ARCH_OMAP_OTG config ARCH_OMAP3430 bool "OMAP3430 support" depends on ARCH_OMAP3 + default y select ARCH_OMAP_OTG +config OMAP_PACKAGE_ZAF + bool + +config OMAP_PACKAGE_ZAC + bool + config OMAP_PACKAGE_CBC bool @@ -35,6 +90,7 @@ comment "OMAP Board Type" config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP2 + default y config MACH_OMAP2_TUSB6010 bool @@ -44,60 +100,75 @@ config MACH_OMAP2_TUSB6010 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" depends on ARCH_OMAP2 + default y + select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" depends on ARCH_OMAP2 + default y + select OMAP_PACKAGE_ZAC config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" depends on ARCH_OMAP2 + default y + select OMAP_PACKAGE_ZAC config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_DEVKIT8000 bool "DEVKIT8000 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_OMAP_LDP bool "OMAP3 LDP board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3EVM bool "OMAP 3530 EVM board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" depends on ARCH_OMAP3 + default y select BACKLIGHT_CLASS_DEVICE config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_NOKIA_N800 @@ -112,6 +183,8 @@ config MACH_NOKIA_N810_WIMAX config MACH_NOKIA_N8X0 bool "Nokia N800/N810" depends on ARCH_OMAP2420 + default y + select OMAP_PACKAGE_ZAC select MACH_NOKIA_N800 select MACH_NOKIA_N810 select MACH_NOKIA_N810_WIMAX @@ -119,42 +192,55 @@ config MACH_NOKIA_N8X0 config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM2 bool "OMAP3 Zoom2 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBP config MACH_CM_T35 bool "CompuLab CM-T35 module" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBP config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" + default y + depends on ARCH_OMAP4 + +config MACH_OMAP4_PANDA + bool "OMAP4 Panda Board" + default y depends on ARCH_OMAP4 config OMAP3_EMU @@ -176,3 +262,6 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +endmenu + +endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ea52b034e96..88d3a1e920f 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ @@ -15,15 +15,17 @@ clock-common = clock.o clock_common_data.o \ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o +obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o +AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a # Functions loaded to SRAM @@ -36,6 +38,8 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6 AFLAGS_sram34xx.o :=-Wa,-march=armv7-a # Pin multiplexing +obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o +obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o # SMS/SDRC @@ -47,6 +51,7 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 @@ -89,7 +94,10 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o -obj-$(CONFIG_OMAP_IOMMU) := iommu2.o omap-iommu.o +obj-$(CONFIG_OMAP_IOMMU) += iommu2.o + +iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o +obj-y += $(iommu-m) $(iommu-y) i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) @@ -105,6 +113,7 @@ obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ + board-flash.o \ hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o @@ -114,7 +123,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ hsmmc.o \ - board-sdp-flash.o + board-flash.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-sdram.o \ @@ -123,14 +132,17 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o @@ -140,12 +152,16 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ hsmmc.o +obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ hsmmc.o # Platform specific device init code +usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o +obj-y += $(usbfs-m) $(usbfs-y) obj-y += usb-musb.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o obj-y += usb-ehci.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 42f49f785c9..8538e4131d2 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -31,13 +31,13 @@ #include <asm/mach/map.h> #include <mach/gpio.h> -#include <plat/mux.h> #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> #include <plat/usb.h> #include <plat/gpmc-smc91x.h> +#include "mux.h" #include "hsmmc.h" #define SDP2430_CS0_BASE 0x04000000 @@ -122,11 +122,7 @@ static struct omap_smc91x_platform_data board_smc91x_data = { static void __init board_smc91x_init(void) { - if (omap_rev() > OMAP3430_REV_ES1_0) - board_smc91x_data.gpio_irq = 6; - else - board_smc91x_data.gpio_irq = 29; - + omap_mux_init_gpio(149, OMAP_PIN_INPUT); gpmc_smc91x_init(&board_smc91x_data); } @@ -217,17 +213,30 @@ static struct omap_usb_config sdp2430_usb_config __initdata = { .pins[0] = 3, }; +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_2430sdp_init(void) { int ret; + omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); + omap2430_i2c_init(); platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); omap_serial_init(); omap2_hsmmc_init(mmc); - omap_usb_init(&sdp2430_usb_config); + omap2_usbfs_init(&sdp2430_usb_config); + + omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); usb_musb_init(&musb_board_data); + board_smc91x_init(); /* Turn off secondary LCD backlight */ diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index dd9c03171a1..67b95b5f1a2 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -41,7 +41,7 @@ #include <plat/control.h> #include <plat/gpmc-smc91x.h> -#include <mach/board-sdp.h> +#include <mach/board-flash.h> #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" @@ -667,6 +667,18 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +/* + * SDP3430 V2 Board CS organization + * Different from SDP3430 V1. Now 4 switches used to specify CS + * + * See also the Switch S8 settings in the comments. + */ +static char chip_sel_3430[][GPMC_CS_NUM] = { + {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ + {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ + {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ +}; + static struct mtd_partition sdp_nor_partitions[] = { /* bootloader (U-Boot, etc) in first sector */ { @@ -797,24 +809,18 @@ static void __init omap_3430sdp_init(void) omap_serial_init(); usb_musb_init(&musb_board_data); board_smc91x_init(); - sdp_flash_init(sdp_flash_partitions); + board_flash_init(sdp_flash_partitions, chip_sel_3430); sdp3430_display_init(); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); } -static void __init omap_3430sdp_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") /* Maintainer: Syed Khasim - Texas Instruments Inc */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_3430sdp_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_3430sdp_init_irq, .init_machine = omap_3430sdp_init, diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 57290fb3fcd..b359c3f7bb3 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -18,10 +18,10 @@ #include <plat/common.h> #include <plat/board.h> #include <plat/gpmc-smc91x.h> -#include <plat/mux.h> #include <plat/usb.h> #include <mach/board-zoom.h> +#include <mach/board-flash.h> #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" @@ -66,12 +66,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -static void __init omap_sdp_map_io(void) -{ - omap2_set_globals_36xx(); - omap34xx_map_common_io(); -} - static struct omap_board_config_kernel sdp_config[] __initdata = { }; @@ -93,12 +87,131 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +/* + * SDP3630 CS organization + * See also the Switch S8 settings in the comments. + */ +static char chip_sel_sdp[][GPMC_CS_NUM] = { + {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ + {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ + {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ +}; + +static struct mtd_partition sdp_nor_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "Bootloader-NOR", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "Params-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "Kernel-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "Filesystem-NOR", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct mtd_partition sdp_onenand_partitions[] = { + { + .name = "X-Loader-OneNAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot Environment-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 1 * (64 * 2048), + }, + { + .name = "Kernel-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 16 * (64 * 2048), + }, + { + .name = "File System-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition sdp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 6 * (64 * 2048), + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 40 * (64 * 2048), + }, + { + .name = "File System - NAND", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ + }, +}; + +static struct flash_partitions sdp_flash_partitions[] = { + { + .parts = sdp_nor_partitions, + .nr_parts = ARRAY_SIZE(sdp_nor_partitions), + }, + { + .parts = sdp_onenand_partitions, + .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), + }, + { + .parts = sdp_nand_partitions, + .nr_parts = ARRAY_SIZE(sdp_nand_partitions), + }, +}; + static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_serial_init(); zoom_peripherals_init(); board_smc91x_init(); + board_flash_init(sdp_flash_partitions, chip_sel_sdp); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); } @@ -107,7 +220,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_sdp_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_sdp_init_irq, .init_machine = omap_sdp_init, diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 4bb2c5d151e..9447644774c 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -21,6 +21,7 @@ #include <linux/spi/spi.h> #include <linux/i2c/twl.h> #include <linux/regulator/machine.h> +#include <linux/leds.h> #include <mach/hardware.h> #include <mach/omap4-common.h> @@ -40,6 +41,54 @@ #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +static struct gpio_led sdp4430_gpio_leds[] = { + { + .name = "omap4:green:debug0", + .gpio = 61, + }, + { + .name = "omap4:green:debug1", + .gpio = 30, + }, + { + .name = "omap4:green:debug2", + .gpio = 7, + }, + { + .name = "omap4:green:debug3", + .gpio = 8, + }, + { + .name = "omap4:green:debug4", + .gpio = 50, + }, + { + .name = "omap4:blue:user", + .gpio = 169, + }, + { + .name = "omap4:red:user", + .gpio = 170, + }, + { + .name = "omap4:green:user", + .gpio = 139, + }, + +}; + +static struct gpio_led_platform_data sdp4430_led_data = { + .leds = sdp4430_gpio_leds, + .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), +}; + +static struct platform_device sdp4430_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &sdp4430_led_data, + }, +}; static struct spi_board_info sdp4430_spi_board_info[] __initdata = { { .modalias = "ks8851", @@ -112,6 +161,7 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, + &sdp4430_leds_gpio, }; static struct omap_lcd_config sdp4430_lcd_config __initdata = { @@ -156,14 +206,16 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { +static struct regulator_consumer_supply sdp4430_vaux_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", + .dev_name = "mmci-omap-hs.1", }, +}; +static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", + .dev_name = "mmci-omap-hs.0", }, }; @@ -210,6 +262,8 @@ static struct regulator_init_data sdp4430_vaux1 = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, + .num_consumer_supplies = 1, + .consumer_supplies = sdp4430_vaux_supply, }; static struct regulator_init_data sdp4430_vaux2 = { @@ -250,7 +304,7 @@ static struct regulator_init_data sdp4430_vmmc = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 2, + .num_consumer_supplies = 1, .consumer_supplies = sdp4430_vmmc_supply, }; @@ -353,6 +407,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { .platform_data = &sdp4430_twldata, }, }; +static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { + { + I2C_BOARD_INFO("tmp105", 0x48), + }, +}; static int __init omap4_i2c_init(void) { /* @@ -362,7 +421,8 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo, ARRAY_SIZE(sdp4430_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, + ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); omap_register_i2c_bus(4, 400, NULL, 0); return 0; } diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 7da92defcde..4d0f5859286 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -461,17 +461,11 @@ static void __init am3517_evm_init(void) am3517_evm_ethernet_init(&am3517_evm_emac_pdata); } -static void __init am3517_evm_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = am3517_evm_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = am3517_evm_init_irq, .init_machine = am3517_evm_init, diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index bd75642aee6..c6421a72514 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -35,13 +35,14 @@ #include <mach/gpio.h> #include <plat/led.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> #include <plat/control.h> +#include "mux.h" + /* LED & Switch macros */ #define LED0_GPIO13 13 #define LED1_GPIO14 14 @@ -244,7 +245,7 @@ static inline void __init apollon_init_smc91x(void) apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); - omap_cfg_reg(W4__24XX_GPIO74); + omap_mux_init_gpio(74, 0); if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); @@ -286,15 +287,15 @@ static void __init omap_apollon_init_irq(void) static void __init apollon_led_init(void) { /* LED0 - AA10 */ - omap_cfg_reg(AA10_242X_GPIO13); + omap_mux_init_signal("vlynq_clk.gpio_13", 0); gpio_request(LED0_GPIO13, "LED0"); gpio_direction_output(LED0_GPIO13, 0); /* LED1 - AA6 */ - omap_cfg_reg(AA6_242X_GPIO14); + omap_mux_init_signal("vlynq_rx1.gpio_14", 0); gpio_request(LED1_GPIO14, "LED1"); gpio_direction_output(LED1_GPIO14, 0); /* LED2 - AA4 */ - omap_cfg_reg(AA4_242X_GPIO15); + omap_mux_init_signal("vlynq_rx0.gpio_15", 0); gpio_request(LED2_GPIO15, "LED2"); gpio_direction_output(LED2_GPIO15, 0); } @@ -303,22 +304,35 @@ static void __init apollon_usb_init(void) { /* USB device */ /* DEVICE_SUSPEND */ - omap_cfg_reg(P21_242X_GPIO12); + omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); gpio_request(12, "USB suspend"); gpio_direction_output(12, 0); - omap_usb_init(&apollon_usb_config); + omap2_usbfs_init(&apollon_usb_config); } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_apollon_init(void) { u32 v; + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); + apollon_led_init(); apollon_flash_init(); apollon_usb_init(); /* REVISIT: where's the correct place */ - omap_cfg_reg(W19_24XX_SYS_NIRQ); + omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); + + /* LCD PWR_EN */ + omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index bc4c3f80706..e10bc109415 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -61,8 +61,6 @@ #define SB_T35_SMSC911X_GPIO 65 #define NAND_BLOCK_SIZE SZ_128K -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS0_BASE_ADDR (OMAP34XX_GPMC_VIRT + GPMC_CS0_BASE) #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> @@ -223,28 +221,12 @@ static struct omap_nand_platform_data cm_t35_nand_data = { .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), .dma_channel = -1, /* disable DMA in OMAP NAND driver */ .cs = 0, - .gpmc_cs_baseaddr = (void __iomem *)GPMC_CS0_BASE_ADDR, - .gpmc_baseaddr = (void __iomem *)OMAP34XX_GPMC_VIRT, }; -static struct resource cm_t35_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device cm_t35_nand_device = { - .name = "omap2-nand", - .id = -1, - .num_resources = 1, - .resource = &cm_t35_nand_resource, - .dev = { - .platform_data = &cm_t35_nand_data, - }, -}; - static void __init cm_t35_init_nand(void) { - if (platform_device_register(&cm_t35_nand_device) < 0) + if (gpmc_nand_init(&cm_t35_nand_data) < 0) pr_err("CM-T35: Unable to register NAND device\n"); } #else @@ -708,12 +690,6 @@ static void __init cm_t35_init_irq(void) omap_gpio_init(); } -static void __init cm_t35_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - static struct omap_board_mux board_mux[] __initdata = { /* nCS and IRQ for CM-T35 ethernet */ OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), @@ -836,7 +812,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = cm_t35_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = cm_t35_init_irq, .init_machine = cm_t35_init, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 922b7464807..a07086d6a0b 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -33,6 +33,7 @@ #include <linux/i2c/twl.h> #include <mach/hardware.h> +#include <mach/id.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -58,9 +59,6 @@ #include "mux.h" #include "hsmmc.h" -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K #define OMAP_DM9000_GPIO_IRQ 25 @@ -104,20 +102,6 @@ static struct omap_nand_platform_data devkit8000_nand_data = { .dma_channel = -1, /* disable DMA in OMAP NAND driver */ }; -static struct resource devkit8000_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device devkit8000_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &devkit8000_nand_data, - }, - .num_resources = 1, - .resource = &devkit8000_nand_resource, -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -126,54 +110,50 @@ static struct omap2_hsmmc_info mmc[] = { }, {} /* Terminator */ }; -static struct omap_board_config_kernel devkit8000_config[] __initdata = { -}; static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) { twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1); twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 1); return 0; } static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) { + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 0); } + static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) { + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 1); return 0; } static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) { + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 0); } -static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev) -{ +static struct regulator_consumer_supply devkit8000_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); - return 0; -} - -static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev) -{ -} - - -static struct regulator_consumer_supply devkit8000_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply devkit8000_vsim_supply = { - .supply = "vmmc_aux", -}; +/* ads7846 on SPI */ +static struct regulator_consumer_supply devkit8000_vio_supply = + REGULATOR_SUPPLY("vcc", "spi2.0"); static struct omap_dss_device devkit8000_lcd_device = { .name = "lcd", - .driver_name = "innolux_at_panel", + .driver_name = "generic_panel", .type = OMAP_DISPLAY_TYPE_DPI, .phy.dpi.data_lines = 24, + .reset_gpio = -EINVAL, /* will be replaced */ .platform_enable = devkit8000_panel_enable_lcd, .platform_disable = devkit8000_panel_disable_lcd, }; @@ -182,6 +162,7 @@ static struct omap_dss_device devkit8000_dvi_device = { .driver_name = "generic_panel", .type = OMAP_DISPLAY_TYPE_DPI, .phy.dpi.data_lines = 24, + .reset_gpio = -EINVAL, /* will be replaced */ .platform_enable = devkit8000_panel_enable_dvi, .platform_disable = devkit8000_panel_disable_dvi, }; @@ -191,8 +172,6 @@ static struct omap_dss_device devkit8000_tv_device = { .driver_name = "venc", .type = OMAP_DISPLAY_TYPE_VENC, .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, - .platform_enable = devkit8000_panel_enable_tv, - .platform_disable = devkit8000_panel_disable_tv, }; @@ -216,10 +195,8 @@ static struct platform_device devkit8000_dss_device = { }, }; -static struct regulator_consumer_supply devkit8000_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &devkit8000_dss_device.dev, -}; +static struct regulator_consumer_supply devkit8000_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); static int board_keymap[] = { KEY(0, 0, KEY_1), @@ -266,7 +243,21 @@ static int devkit8000_twl_gpio_setup(struct device *dev, /* link regulators to MMC adapters */ devkit8000_vmmc1_supply.dev = mmc[0].dev; - devkit8000_vsim_supply.dev = mmc[0].dev; + + /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ + gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; + + /* gpio + 1 is "LCD_PWREN" (out, active high) */ + devkit8000_lcd_device.reset_gpio = gpio + 1; + gpio_request(devkit8000_lcd_device.reset_gpio, "LCD_PWREN"); + /* Disable until needed */ + gpio_direction_output(devkit8000_lcd_device.reset_gpio, 0); + + /* gpio + 7 is "DVI_PD" (out, active low) */ + devkit8000_dvi_device.reset_gpio = gpio + 7; + gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown"); + /* Disable until needed */ + gpio_direction_output(devkit8000_dvi_device.reset_gpio, 0); return 0; } @@ -282,16 +273,8 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { .setup = devkit8000_twl_gpio_setup, }; -static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = { - { - .supply = "vdvi", - .dev = &devkit8000_lcd_device.dev, - }, - { - .supply = "vdds_dsi", - .dev = &devkit8000_dss_device.dev, - } -}; +static struct regulator_consumer_supply devkit8000_vpll1_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data devkit8000_vmmc1 = { @@ -308,21 +291,6 @@ static struct regulator_init_data devkit8000_vmmc1 = { .consumer_supplies = &devkit8000_vmmc1_supply, }; -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data devkit8000_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &devkit8000_vsim_supply, -}; - /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ static struct regulator_init_data devkit8000_vdac = { .constraints = { @@ -337,10 +305,9 @@ static struct regulator_init_data devkit8000_vdac = { .consumer_supplies = &devkit8000_vdda_dac_supply, }; -/* VPLL2 for digital video outputs */ -static struct regulator_init_data devkit8000_vpll2 = { +/* VPLL1 for digital video outputs */ +static struct regulator_init_data devkit8000_vpll1 = { .constraints = { - .name = "VDVI", .min_uV = 1800000, .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL @@ -348,8 +315,23 @@ static struct regulator_init_data devkit8000_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll2_supplies), - .consumer_supplies = devkit8000_vpll2_supplies, + .num_consumer_supplies = 1, + .consumer_supplies = &devkit8000_vpll1_supply, +}; + +/* VAUX4 for ads7846 and nubs */ +static struct regulator_init_data devkit8000_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &devkit8000_vio_supply, }; static struct twl4030_usb_data devkit8000_usb_data = { @@ -374,15 +356,15 @@ static struct twl4030_platform_data devkit8000_twldata = { .gpio = &devkit8000_gpio_data, .codec = &devkit8000_codec_data, .vmmc1 = &devkit8000_vmmc1, - .vsim = &devkit8000_vsim, .vdac = &devkit8000_vdac, - .vpll2 = &devkit8000_vpll2, + .vpll1 = &devkit8000_vpll1, + .vio = &devkit8000_vio, .keypad = &devkit8000_kp_data, }; static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = { { - I2C_BOARD_INFO("twl4030", 0x48), + I2C_BOARD_INFO("tps65930", 0x48), .flags = I2C_CLIENT_WAKE, .irq = INT_34XX_SYS_NIRQ, .platform_data = &devkit8000_twldata, @@ -464,8 +446,6 @@ static struct platform_device keys_gpio = { static void __init devkit8000_init_irq(void) { - omap_board_config = devkit8000_config; - omap_board_config_size = ARRAY_SIZE(devkit8000_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); @@ -560,6 +540,9 @@ static struct platform_device omap_dm9000_dev = { static void __init omap_dm9000_init(void) { + unsigned char *eth_addr = omap_dm9000_platdata.dev_addr; + struct omap_die_id odi; + if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n", OMAP_DM9000_GPIO_IRQ); @@ -567,6 +550,16 @@ static void __init omap_dm9000_init(void) } gpio_direction_input(OMAP_DM9000_GPIO_IRQ); + + /* init the mac address using DIE id */ + omap_get_die_id(&odi); + + eth_addr[0] = 0x02; /* locally administered */ + eth_addr[1] = odi.id_1 & 0xff; + eth_addr[2] = (odi.id_0 & 0xff000000) >> 24; + eth_addr[3] = (odi.id_0 & 0x00ff0000) >> 16; + eth_addr[4] = (odi.id_0 & 0x0000ff00) >> 8; + eth_addr[5] = (odi.id_0 & 0x000000ff); } static struct platform_device *devkit8000_devices[] __initdata = { @@ -581,8 +574,6 @@ static void __init devkit8000_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -604,13 +595,9 @@ static void __init devkit8000_flash_init(void) if (nandcs < GPMC_CS_NUM) { devkit8000_nand_data.cs = nandcs; - devkit8000_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - devkit8000_nand_data.gpmc_baseaddr = (void *) - (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&devkit8000_nand_device) < 0) + if (gpmc_nand_init(&devkit8000_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -797,8 +784,6 @@ static void __init devkit8000_init(void) devkit8000_i2c_init(); platform_add_devices(devkit8000_devices, ARRAY_SIZE(devkit8000_devices)); - omap_board_config = devkit8000_config; - omap_board_config_size = ARRAY_SIZE(devkit8000_config); spi_register_board_info(devkit8000_spi_board_info, ARRAY_SIZE(devkit8000_spi_board_info)); @@ -814,17 +799,11 @@ static void __init devkit8000_init(void) omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); } -static void __init devkit8000_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = devkit8000_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = devkit8000_init_irq, .init_machine = devkit8000_init, diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-flash.c index 2d026328e38..ac834aa7abf 100644 --- a/arch/arm/mach-omap2/board-sdp-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -21,7 +21,7 @@ #include <plat/nand.h> #include <plat/onenand.h> #include <plat/tc.h> -#include <mach/board-sdp.h> +#include <mach/board-flash.h> #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 @@ -29,72 +29,53 @@ #define DEBUG_BASE 0x08000000 /* debug board */ -#define PDC_NOR 1 -#define PDC_NAND 2 -#define PDC_ONENAND 3 -#define DBG_MPDB 4 - /* various memory sizes */ #define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ #define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ -/* - * SDP3430 V2 Board CS organization - * Different from SDP3430 V1. Now 4 switches used to specify CS - * - * See also the Switch S8 settings in the comments. - * - * REVISIT: Add support for 2430 SDP - */ -static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = { - {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ - {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ - {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ -}; - -static struct physmap_flash_data sdp_nor_data = { +static struct physmap_flash_data board_nor_data = { .width = 2, }; -static struct resource sdp_nor_resource = { +static struct resource board_nor_resource = { .flags = IORESOURCE_MEM, }; -static struct platform_device sdp_nor_device = { +static struct platform_device board_nor_device = { .name = "physmap-flash", .id = 0, .dev = { - .platform_data = &sdp_nor_data, + .platform_data = &board_nor_data, }, .num_resources = 1, - .resource = &sdp_nor_resource, + .resource = &board_nor_resource, }; static void -__init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs) +__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) { int err; - sdp_nor_data.parts = sdp_nor_parts.parts; - sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts; + board_nor_data.parts = nor_parts; + board_nor_data.nr_parts = nr_parts; /* Configure start address and size of NOR device */ if (omap_rev() >= OMAP3430_REV_ES1_0) { err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, - (unsigned long *)&sdp_nor_resource.start); - sdp_nor_resource.end = sdp_nor_resource.start + (unsigned long *)&board_nor_resource.start); + board_nor_resource.end = board_nor_resource.start + FLASH_SIZE_SDPV2 - 1; } else { err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, - (unsigned long *)&sdp_nor_resource.start); - sdp_nor_resource.end = sdp_nor_resource.start + (unsigned long *)&board_nor_resource.start); + board_nor_resource.end = board_nor_resource.start + FLASH_SIZE_SDPV1 - 1; } if (err < 0) { printk(KERN_ERR "NOR: Can't request GPMC CS\n"); return; } - if (platform_device_register(&sdp_nor_device) < 0) + if (platform_device_register(&board_nor_device) < 0) printk(KERN_ERR "Unable to register NOR device\n"); } @@ -105,17 +86,18 @@ static struct omap_onenand_platform_data board_onenand_data = { }; static void -__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) +__init board_onenand_init(struct mtd_partition *onenand_parts, + u8 nr_parts, u8 cs) { board_onenand_data.cs = cs; - board_onenand_data.parts = sdp_onenand_parts.parts; - board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts; + board_onenand_data.parts = onenand_parts; + board_onenand_data.nr_parts = nr_parts; gpmc_onenand_init(&board_onenand_data); } #else static void -__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) +__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) { } #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ @@ -147,7 +129,7 @@ static struct gpmc_timings nand_timings = { .wr_data_mux_bus = 0, }; -static struct omap_nand_platform_data sdp_nand_data = { +static struct omap_nand_platform_data board_nand_data = { .nand_setup = NULL, .gpmc_t = &nand_timings, .dma_channel = -1, /* disable DMA in OMAP NAND driver */ @@ -155,23 +137,18 @@ static struct omap_nand_platform_data sdp_nand_data = { .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ }; -static void -__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) +void +__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) { - sdp_nand_data.cs = cs; - sdp_nand_data.parts = sdp_nand_parts.parts; - sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts; + board_nand_data.cs = cs; + board_nand_data.parts = nand_parts; + board_nand_data.nr_parts = nr_parts; - sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + - GPMC_CS0_BASE + - cs * GPMC_CS_SIZE); - sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); - - gpmc_nand_init(&sdp_nand_data); + gpmc_nand_init(&board_nand_data); } #else -static void -__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) +void +__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) { } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ @@ -215,7 +192,8 @@ unmap: * * @return - void. */ -void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) +void board_flash_init(struct flash_partitions partition_info[], + char chip_sel_board[][GPMC_CS_NUM]) { u8 cs = 0; u8 norcs = GPMC_CS_NUM + 1; @@ -232,7 +210,7 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); return; } - config_sel = (unsigned char *)(chip_sel_sdp[idx]); + config_sel = (unsigned char *)(chip_sel_board[idx]); while (cs < GPMC_CS_NUM) { switch (config_sel[cs]) { @@ -256,17 +234,20 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) printk(KERN_INFO "NOR: Unable to find configuration " "in GPMC\n"); else - board_nor_init(sdp_partition_info[0], norcs); + board_nor_init(partition_info[0].parts, + partition_info[0].nr_parts, norcs); if (onenandcs > GPMC_CS_NUM) printk(KERN_INFO "OneNAND: Unable to find configuration " "in GPMC\n"); else - board_onenand_init(sdp_partition_info[1], onenandcs); + board_onenand_init(partition_info[1].parts, + partition_info[1].nr_parts, onenandcs); if (nandcs > GPMC_CS_NUM) printk(KERN_INFO "NAND: Unable to find configuration " "in GPMC\n"); else - board_nand_init(sdp_partition_info[2], nandcs); + board_nand_init(partition_info[2].parts, + partition_info[2].nr_parts, nandcs); } diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9242902d3a4..3482b99e8c8 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -26,7 +26,6 @@ #include <asm/mach/map.h> #include <mach/gpio.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 16703fdb351..e09bd686389 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -33,7 +33,6 @@ #include <plat/control.h> #include <mach/gpio.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> @@ -42,6 +41,8 @@ #include <plat/dma.h> #include <plat/gpmc.h> +#include "mux.h" + #define H4_FLASH_CS 0 #define H4_SMC91X_CS 1 @@ -246,7 +247,7 @@ static inline void __init h4_init_debug(void) udelay(100); - omap_cfg_reg(M15_24XX_GPIO92); + omap_mux_init_gpio(92, 0); if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) gpmc_cs_free(eth_cs); @@ -272,27 +273,6 @@ static struct omap_lcd_config h4_lcd_config __initdata = { }; static struct omap_usb_config h4_usb_config __initdata = { -#ifdef CONFIG_MACH_OMAP2_H4_USB1 - /* NOTE: usb1 could also be used with 3 wire signaling */ - .pins[1] = 4, -#endif - -#ifdef CONFIG_MACH_OMAP_H4_OTG - /* S1.10 ON -- USB OTG port - * usb0 switched to Mini-AB port and isp1301 transceiver; - * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging - */ - .otg = 1, - .pins[0] = 4, -#ifdef CONFIG_USB_GADGET_OMAP - /* use OTG cable, or standard A-to-MiniB */ - .hmc_mode = 0x14, /* 0:dev/otg 1:host 2:disable */ -#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* use OTG cable, or NONSTANDARD (B-to-MiniB) */ - .hmc_mode = 0x11, /* 0:host 1:host 2:disable */ -#endif /* XX */ - -#else /* S1.10 OFF -- usb "download port" * usb0 switched to Mini-B port and isp1105 transceiver; * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging @@ -301,7 +281,6 @@ static struct omap_usb_config h4_usb_config __initdata = { .pins[0] = 3, /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ -#endif }; static struct omap_board_config_kernel h4_config[] = { @@ -338,31 +317,54 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = { }, }; +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_h4_init(void) { + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); + /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on * if not needed. */ -#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) - omap_cfg_reg(K15_24XX_UART3_TX); - omap_cfg_reg(K14_24XX_UART3_RX); -#endif #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) + omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); if (omap_has_menelaus()) { + omap_mux_init_signal("sdrc_a14.gpio0", + OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_signal("vlynq_rx0.gpio_15", 0); + omap_mux_init_signal("gpio_98", 0); row_gpios[5] = 0; col_gpios[2] = 15; col_gpios[6] = 18; + } else { + omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_signal("gpio_100", 0); + omap_mux_init_signal("gpio_98", 0); } + omap_mux_init_signal("gpio_90", 0); + omap_mux_init_signal("gpio_91", 0); + omap_mux_init_signal("gpio_36", 0); + omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); + omap_mux_init_signal("gpio_97", 0); #endif i2c_register_board_info(1, h4_i2c_board_info, ARRAY_SIZE(h4_i2c_board_info)); platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); - omap_usb_init(&h4_usb_config); + omap2_usbfs_init(&h4_usb_config); omap_serial_init(); } diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 759e39d1a70..175f0433976 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -532,17 +532,11 @@ static void __init igep2_init(void) pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); } -static void __init igep2_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(IGEP0020, "IGEP v2 board") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = igep2_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = igep2_init_irq, .init_machine = igep2_init, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 9cd2669113e..00d9b13b01c 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -38,6 +38,7 @@ #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> +#include <mach/board-zoom.h> #include <asm/delay.h> #include <plat/control.h> @@ -388,6 +389,38 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; +static struct mtd_partition ldp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "File System - NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = MTDPART_SIZ_FULL, /* 96MB, 0x6000000 */ + }, + +}; + static void __init omap_ldp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -400,23 +433,19 @@ static void __init omap_ldp_init(void) ads7846_dev_init(); omap_serial_init(); usb_musb_init(&musb_board_data); + board_nand_init(ldp_nand_partitions, + ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ ldp_vmmc1_supply.dev = mmc[0].dev; } -static void __init omap_ldp_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP_LDP, "OMAP LDP board") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_ldp_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_ldp_init_irq, .init_machine = omap_ldp_init, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 2565ff08a22..a3e2b49aa39 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -33,6 +33,8 @@ #include <plat/mmc.h> #include <plat/serial.h> +#include "mux.h" + static int slot1_cover_open; static int slot2_cover_open; static struct device *mmc_device; @@ -649,8 +651,17 @@ static void __init n8x0_init_irq(void) omap_gpio_init(); } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init n8x0_init_machine(void) { + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 0ab0c26db4d..87969c7df65 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -48,9 +48,6 @@ #include "mux.h" #include "hsmmc.h" -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K static struct mtd_partition omap3beagle_nand_partitions[] = { @@ -93,20 +90,6 @@ static struct omap_nand_platform_data omap3beagle_nand_data = { .dev_ready = NULL, }; -static struct resource omap3beagle_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3beagle_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3beagle_nand_data, - }, - .num_resources = 1, - .resource = &omap3beagle_nand_resource, -}; - /* DSS */ static int beagle_enable_dvi(struct omap_dss_device *dssdev) @@ -424,8 +407,6 @@ static void __init omap3beagle_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -447,12 +428,9 @@ static void __init omap3beagle_flash_init(void) if (nandcs < GPMC_CS_NUM) { omap3beagle_nand_data.cs = nandcs; - omap3beagle_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3beagle_nand_device) < 0) + if (gpmc_nand_init(&omap3beagle_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -507,18 +485,12 @@ static void __init omap3_beagle_init(void) beagle_display_init(); } -static void __init omap3_beagle_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_beagle_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3_beagle_init_irq, .init_machine = omap3_beagle_init, diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index a3d2e285e11..f76d9c0a47a 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -514,14 +514,11 @@ static struct regulator_init_data omap3_evm_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_evm_vpll2_supply = { - .supply = "vdvi", - .dev = &omap3_evm_lcd_device.dev, -}; +static struct regulator_consumer_supply omap3_evm_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_init_data omap3_evm_vpll2 = { .constraints = { - .name = "VDVI", .min_uV = 1800000, .max_uV = 1800000, .apply_uV = true, @@ -715,18 +712,12 @@ static void __init omap3_evm_init(void) omap3_evm_display_init(); } -static void __init omap3_evm_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3EVM, "OMAP3 EVM") /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_evm_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3_evm_init_irq, .init_machine = omap3_evm_init, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index c0f4f12eba5..dd3af2be13b 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -25,10 +25,14 @@ #include <linux/spi/ads7846.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> +#include <linux/spi/wl12xx.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> #include <linux/leds.h> #include <linux/input.h> #include <linux/input/matrix_keypad.h> #include <linux/gpio_keys.h> +#include <linux/mmc/card.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -41,15 +45,49 @@ #include <plat/mcspi.h> #include <plat/usb.h> #include <plat/display.h> +#include <plat/nand.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" +#define PANDORA_WIFI_IRQ_GPIO 21 +#define PANDORA_WIFI_NRESET_GPIO 23 #define OMAP3_PANDORA_TS_GPIO 94 -/* hardware debounce: (value + 1) * 31us */ -#define GPIO_DEBOUNCE_TIME 127 +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition omap3pandora_nand_partitions[] = { + { + .name = "xloader", + .offset = 0, + .size = 4 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = 15 * NAND_BLOCK_SIZE, + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = 1 * NAND_BLOCK_SIZE, + }, { + .name = "boot", + .offset = MTDPART_OFS_APPEND, + .size = 80 * NAND_BLOCK_SIZE, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_nand_platform_data pandora_nand_data = { + .cs = 0, + .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ + .parts = omap3pandora_nand_partitions, + .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), +}; static struct gpio_led pandora_gpio_leds[] = { { @@ -88,6 +126,7 @@ static struct platform_device pandora_leds_gpio = { .type = ev_type, \ .code = ev_code, \ .active_low = act_low, \ + .debounce_interval = 4, \ .desc = "btn " descr, \ } @@ -99,14 +138,14 @@ static struct gpio_keys_button pandora_gpio_keys[] = { GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), - GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"), - GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"), - GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"), - GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"), - GPIO_BUTTON_LOW(102, BTN_TL, "l"), - GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), - GPIO_BUTTON_LOW(105, BTN_TR, "r"), - GPIO_BUTTON_LOW(107, BTN_TR2, "r2"), + GPIO_BUTTON_LOW(109, KEY_PAGEUP, "game 1"), + GPIO_BUTTON_LOW(111, KEY_END, "game 2"), + GPIO_BUTTON_LOW(106, KEY_PAGEDOWN, "game 3"), + GPIO_BUTTON_LOW(101, KEY_HOME, "game 4"), + GPIO_BUTTON_LOW(102, KEY_RIGHTSHIFT, "l"), + GPIO_BUTTON_LOW(97, KEY_KPPLUS, "l2"), + GPIO_BUTTON_LOW(105, KEY_RIGHTCTRL, "r"), + GPIO_BUTTON_LOW(107, KEY_KPMINUS, "r2"), GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), @@ -127,14 +166,7 @@ static struct platform_device pandora_keys_gpio = { }, }; -static void __init pandora_keys_gpio_init(void) -{ - /* set debounce time for GPIO banks 4 and 6 */ - gpio_set_debounce(32 * 3, GPIO_DEBOUNCE_TIME); - gpio_set_debounce(32 * 5, GPIO_DEBOUNCE_TIME); -} - -static int board_keymap[] = { +static const uint32_t board_keymap[] = { /* row, col, code */ KEY(0, 0, KEY_9), KEY(0, 1, KEY_8), @@ -227,6 +259,20 @@ static struct platform_device pandora_dss_device = { }, }; +static void pandora_wl1251_init_card(struct mmc_card *card) +{ + /* + * We have TI wl1251 attached to MMC3. Pass this information to + * SDIO core because it can't be probed by normal methods. + */ + card->quirks |= MMC_QUIRK_NONSTD_SDIO; + card->cccr.wide_bus = 1; + card->cis.vendor = 0x104c; + card->cis.device = 0x9066; + card->cis.blksize = 512; + card->cis.max_dtr = 20000000; +} + static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, @@ -248,6 +294,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, + .init_card = pandora_wl1251_init_card, }, {} /* Terminator */ }; @@ -255,12 +302,33 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { static int omap3pandora_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int ret, gpio_32khz; + /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ omap3pandora_mmc[0].gpio_cd = gpio + 0; omap3pandora_mmc[1].gpio_cd = gpio + 1; omap2_hsmmc_init(omap3pandora_mmc); + /* gpio + 13 drives 32kHz buffer for wifi module */ + gpio_32khz = gpio + 13; + ret = gpio_request(gpio_32khz, "wifi 32kHz"); + if (ret < 0) { + pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret); + goto fail; + } + + ret = gpio_direction_output(gpio_32khz, 1); + if (ret < 0) { + pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret); + goto fail_direction; + } + return 0; + +fail_direction: + gpio_free(gpio_32khz); +fail: + return -ENODEV; } static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { @@ -539,10 +607,67 @@ static void __init omap3pandora_init_irq(void) omap_gpio_init(); } +static void pandora_wl1251_set_power(bool enable) +{ + /* + * Keep power always on until wl1251_sdio driver learns to re-init + * the chip after powering it down and back up. + */ +} + +static struct wl12xx_platform_data pandora_wl1251_pdata = { + .set_power = pandora_wl1251_set_power, + .use_eeprom = true, +}; + +static struct platform_device pandora_wl1251_data = { + .name = "wl1251_data", + .id = -1, + .dev = { + .platform_data = &pandora_wl1251_pdata, + }, +}; + +static void pandora_wl1251_init(void) +{ + int ret; + + ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq"); + if (ret < 0) + goto fail; + + ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO); + if (ret < 0) + goto fail_irq; + + pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO); + if (pandora_wl1251_pdata.irq < 0) + goto fail_irq; + + ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); + if (ret < 0) + goto fail_irq; + + /* start powered so that it probes with MMC subsystem */ + ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); + if (ret < 0) + goto fail_nreset; + + return; + +fail_nreset: + gpio_free(PANDORA_WIFI_NRESET_GPIO); +fail_irq: + gpio_free(PANDORA_WIFI_IRQ_GPIO); +fail: + printk(KERN_ERR "wl1251 board initialisation failed\n"); +} + static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_leds_gpio, &pandora_keys_gpio, &pandora_dss_device, + &pandora_wl1251_data, }; static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -575,6 +700,7 @@ static void __init omap3pandora_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3pandora_i2c_init(); + pandora_wl1251_init(); platform_add_devices(omap3pandora_devices, ARRAY_SIZE(omap3pandora_devices)); omap_serial_init(); @@ -582,25 +708,19 @@ static void __init omap3pandora_init(void) ARRAY_SIZE(omap3pandora_spi_board_info)); omap3pandora_ads7846_init(); usb_ehci_init(&ehci_pdata); - pandora_keys_gpio_init(); usb_musb_init(&musb_board_data); + gpmc_nand_init(&pandora_nand_data); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); } -static void __init omap3pandora_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3pandora_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3pandora_init_irq, .init_machine = omap3pandora_init, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index a04cffd691c..bcd01d278c6 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -652,18 +652,12 @@ static void __init omap3_stalker_init(void) omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); } -static void __init omap3_stalker_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(SBC3530, "OMAP3 STALKER") /* Maintainer: Jason Lam -lzg@ema-tech.com */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_stalker_map_io, + .map_io = omap3_map_io, .init_irq = omap3_stalker_init_irq, .init_machine = omap3_stalker_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index f05b867c585..663c62d271e 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -54,9 +54,6 @@ #include <asm/setup.h> -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K #define OMAP3_AC_GPIO 136 @@ -106,20 +103,6 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { .dev_ready = NULL, }; -static struct resource omap3touchbook_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3touchbook_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3touchbook_nand_data, - }, - .num_resources = 1, - .resource = &omap3touchbook_nand_resource, -}; - #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -458,8 +441,6 @@ static void __init omap3touchbook_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -481,13 +462,9 @@ static void __init omap3touchbook_flash_init(void) if (nandcs < GPMC_CS_NUM) { omap3touchbook_nand_data.cs = nandcs; - omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3touchbook_nand_data.gpmc_baseaddr = - (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3touchbook_nand_device) < 0) + if (gpmc_nand_init(&omap3touchbook_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -559,18 +536,12 @@ static void __init omap3_touchbook_init(void) omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); } -static void __init omap3_touchbook_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_touchbook_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3_touchbook_init_irq, .init_machine = omap3_touchbook_init, diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c new file mode 100644 index 00000000000..c03d1d56db5 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -0,0 +1,304 @@ +/* + * Board support file for OMAP4430 based PandaBoard. + * + * Copyright (C) 2010 Texas Instruments + * + * Author: David Anders <x0132446@ti.com> + * + * Based on mach-omap2/board-4430sdp.c + * + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Based on mach-omap2/board-3430sdp.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/usb/otg.h> +#include <linux/i2c/twl.h> +#include <linux/regulator/machine.h> + +#include <mach/hardware.h> +#include <mach/omap4-common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <plat/board.h> +#include <plat/common.h> +#include <plat/control.h> +#include <plat/timer-gp.h> +#include <plat/usb.h> +#include <plat/mmc.h> +#include "hsmmc.h" + + +static void __init omap4_panda_init_irq(void) +{ + omap2_init_common_hw(NULL, NULL); + gic_init_irq(); + omap_gpio_init(); +} + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_UTMI, + .mode = MUSB_PERIPHERAL, + .power = 100, +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .wires = 8, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.0", + }, + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", + }, +}; + +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) + pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + + MMCDETECT_INTR_OFFSET; + return ret; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata = dev->platform_data; + + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap2_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) + omap4_twl6030_hsmmc_set_late_init(c->dev); + + return 0; +} + +static struct regulator_init_data omap4_panda_vaux1 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vaux2 = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vaux3 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VMMC1 for MMC1 card */ +static struct regulator_init_data omap4_panda_vmmc = { + .constraints = { + .min_uV = 1200000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 2, + .consumer_supplies = omap4_panda_vmmc_supply, +}; + +static struct regulator_init_data omap4_panda_vpp = { + .constraints = { + .min_uV = 1800000, + .max_uV = 2500000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vusim = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2900000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vana = { + .constraints = { + .min_uV = 2100000, + .max_uV = 2100000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vcxio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vusb = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct twl4030_platform_data omap4_panda_twldata = { + .irq_base = TWL6030_IRQ_BASE, + .irq_end = TWL6030_IRQ_END, + + /* Regulators */ + .vmmc = &omap4_panda_vmmc, + .vpp = &omap4_panda_vpp, + .vusim = &omap4_panda_vusim, + .vana = &omap4_panda_vana, + .vcxio = &omap4_panda_vcxio, + .vdac = &omap4_panda_vdac, + .vusb = &omap4_panda_vusb, + .vaux1 = &omap4_panda_vaux1, + .vaux2 = &omap4_panda_vaux2, + .vaux3 = &omap4_panda_vaux3, +}; + +static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl6030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = OMAP44XX_IRQ_SYS_1N, + .platform_data = &omap4_panda_twldata, + }, +}; +static int __init omap4_panda_i2c_init(void) +{ + /* + * Phoenix Audio IC needs I2C1 to + * start with 400 KHz or less + */ + omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo, + ARRAY_SIZE(omap4_panda_i2c_boardinfo)); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(4, 400, NULL, 0); + return 0; +} +static void __init omap4_panda_init(void) +{ + int status; + + omap4_panda_i2c_init(); + omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); + /* OMAP4 Panda uses internal transceiver so register nop transceiver */ + usb_nop_xceiv_register(); + /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ + if (!cpu_is_omap44xx()) + usb_musb_init(&musb_board_data); +} + +static void __init omap4_panda_map_io(void) +{ + omap2_set_globals_443x(); + omap44xx_map_common_io(); +} + +MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") + /* Maintainer: David Anders - Texas Instruments Inc */ + .phys_io = 0x48000000, + .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap4_panda_map_io, + .init_irq = omap4_panda_init_irq, + .init_machine = omap4_panda_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 87acb2f198e..4c484361835 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -58,8 +58,6 @@ #define OVERO_GPIO_USBH_NRESET 183 #define NAND_BLOCK_SIZE SZ_128K -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 #define OVERO_SMSC911X_CS 5 #define OVERO_SMSC911X_GPIO 176 @@ -166,9 +164,26 @@ static struct platform_device overo_smsc911x_device = { }, }; +static struct platform_device overo_smsc911x2_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(overo_smsc911x2_resources), + .resource = overo_smsc911x2_resources, + .dev = { + .platform_data = &overo_smsc911x_config, + }, +}; + +static struct platform_device *smsc911x_devices[] = { + &overo_smsc911x_device, + &overo_smsc911x2_device, +}; + static inline void __init overo_init_smsc911x(void) { - unsigned long cs_mem_base; + unsigned long cs_mem_base, cs_mem_base2; + + /* set up first smsc911x chip */ if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) { printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n"); @@ -189,7 +204,28 @@ static inline void __init overo_init_smsc911x(void) overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO); overo_smsc911x_resources[1].end = 0; - platform_device_register(&overo_smsc911x_device); + /* set up second smsc911x chip */ + + if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) { + printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n"); + return; + } + + overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0; + overo_smsc911x2_resources[0].end = cs_mem_base2 + 0xff; + + if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) && + (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) { + gpio_export(OVERO_SMSC911X2_GPIO, 0); + } else { + printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n"); + return; + } + + overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO); + overo_smsc911x2_resources[1].end = 0; + + platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices)); } #else @@ -231,28 +267,11 @@ static struct omap_nand_platform_data overo_nand_data = { .dma_channel = -1, /* disable DMA in OMAP NAND driver */ }; -static struct resource overo_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device overo_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &overo_nand_data, - }, - .num_resources = 1, - .resource = &overo_nand_resource, -}; - - static void __init overo_flash_init(void) { u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -274,12 +293,9 @@ static void __init overo_flash_init(void) if (nandcs < GPMC_CS_NUM) { overo_nand_data.cs = nandcs; - overo_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&overo_nand_device) < 0) + if (gpmc_nand_init(&overo_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -484,17 +500,11 @@ static void __init overo_init(void) "OVERO_GPIO_USBH_CPEN\n"); } -static void __init overo_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OVERO, "Gumstix Overo") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = overo_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = overo_init_irq, .init_machine = overo_init, diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 03483920ed6..9a5eb87425f 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -25,7 +25,6 @@ #include <linux/mmc/host.h> #include <plat/mcspi.h> -#include <plat/mux.h> #include <plat/board.h> #include <plat/common.h> #include <plat/dma.h> @@ -33,6 +32,11 @@ #include <plat/onenand.h> #include <plat/gpmc-smc91x.h> +#include <sound/tlv320aic3x.h> +#include <sound/tpa6130a2-plat.h> + +#include <../drivers/staging/iio/light/tsl2563.h> + #include "mux.h" #include "hsmmc.h" @@ -51,6 +55,12 @@ enum { static struct wl12xx_platform_data wl1251_pdata; +#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) +static struct tsl2563_platform_data rx51_tsl2563_platform_data = { + .cover_comp_gain = 16, +}; +#endif + static struct omap2_mcspi_device_config wl1251_mcspi_config = { .turbo_mode = 0, .single_channel = 1, @@ -311,48 +321,29 @@ static struct omap2_hsmmc_info mmc[] __initdata = { {} /* Terminator */ }; -static struct regulator_consumer_supply rx51_vmmc1_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", -}; +static struct regulator_consumer_supply rx51_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -static struct regulator_consumer_supply rx51_vaux3_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply rx51_vaux3_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -static struct regulator_consumer_supply rx51_vsim_supply = { - .supply = "vmmc_aux", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply rx51_vsim_supply = + REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tlv320aic3x analog supplies */ - { - .supply = "AVDD", - .dev_name = "2-0018", - }, - { - .supply = "DRVDD", - .dev_name = "2-0018", - }, + REGULATOR_SUPPLY("AVDD", "2-0018"), + REGULATOR_SUPPLY("DRVDD", "2-0018"), + /* tpa6130a2 */ + REGULATOR_SUPPLY("Vdd", "2-0060"), /* Keep vmmc as last item. It is not iterated for newer boards */ - { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", - }, + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), }; static struct regulator_consumer_supply rx51_vio_supplies[] = { /* tlv320aic3x digital supplies */ - { - .supply = "IOVDD", - .dev_name = "2-0018" - }, - { - .supply = "DVDD", - .dev_name = "2-0018" - }, + REGULATOR_SUPPLY("IOVDD", "2-0018"), + REGULATOR_SUPPLY("DVDD", "2-0018"), }; #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) @@ -373,6 +364,7 @@ static struct regulator_init_data rx51_vaux1 = { .name = "V28", .min_uV = 2800000, .max_uV = 2800000, + .always_on = true, /* due battery cover sensor */ .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -718,6 +710,15 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vio = &rx51_vio, }; +static struct aic3x_pdata rx51_aic3x_data __initdata = { + .gpio_reset = 60, +}; + +static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { + .id = TPA6130A2, + .power_gpio = 98, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { { I2C_BOARD_INFO("twl5030", 0x48), @@ -730,7 +731,18 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { { I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &rx51_aic3x_data, + }, +#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) + { + I2C_BOARD_INFO("tsl2563", 0x29), + .platform_data = &rx51_tsl2563_platform_data, }, +#endif + { + I2C_BOARD_INFO("tpa6130a2", 0x60), + .platform_data = &rx51_tpa6130a2_data, + } }; static int __init rx51_i2c_init(void) diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index b743a4f4264..5a1005ba981 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -16,7 +16,6 @@ #include <linux/mm.h> #include <asm/mach-types.h> -#include <plat/mux.h> #include <plat/display.h> #include <plat/vram.h> #include <plat/mcspi.h> diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 3bd956f9e19..a58e8cb1a7f 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -143,7 +143,7 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { - omap2_set_globals_343x(); + omap2_set_globals_3xxx(); rx51_video_mem_init(); omap34xx_map_common_io(); } diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index ffe188cb18e..3ad9ecf7f5e 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -71,30 +71,80 @@ static struct twl4030_platform_data zoom2_twldata = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else #define board_mux NULL #endif +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + static void __init omap_zoom2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); zoom_peripherals_init(); + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); } -static void __init omap_zoom2_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .phys_io = ZOOM_UART_BASE, .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_zoom2_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_zoom2_init_irq, .init_machine = omap_zoom2_init, diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 5b605eba3e7..6ca0b834161 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -25,15 +25,50 @@ #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" -static void __init omap_zoom_map_io(void) -{ - omap2_set_globals_36xx(); - omap34xx_map_common_io(); -} - static struct omap_board_config_kernel zoom_config[] __initdata = { }; +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + static void __init omap_zoom_init_irq(void) { omap_board_config = zoom_config; @@ -46,6 +81,19 @@ static void __init omap_zoom_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -66,6 +114,8 @@ static void __init omap_zoom_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); zoom_peripherals_init(); + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); @@ -76,7 +126,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .phys_io = ZOOM_UART_BASE, .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_zoom_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_zoom_init_irq, .init_machine = omap_zoom_init, diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d33744117ce..dfdce2d8277 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -1408,7 +1408,7 @@ static struct clk ts_fck = { static struct clk usbtll_fck = { .name = "usbtll_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_dflt_wait, .parent = &dpll5_m2_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, @@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void) struct omap_clk *c; u32 cpu_clkflg = CK_3XXX; - if (cpu_is_omap34xx()) { + if (cpu_is_omap3517()) { + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; + cpu_clkflg |= CK_3517; + } else if (cpu_is_omap3505()) { + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; + cpu_clkflg |= CK_3505; + } else if (cpu_is_omap34xx()) { cpu_mask = RATE_IN_3XXX; cpu_clkflg |= CK_343X; @@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void) cpu_mask |= RATE_IN_3430ES2PLUS; cpu_clkflg |= CK_3430ES2; } - } else if (cpu_is_omap3517()) { - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3517; - } else if (cpu_is_omap3505()) { - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; - cpu_clkflg |= CK_3505; } if (omap3_has_192mhz_clk()) diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c index 2d83565d2be..721c3b66740 100644 --- a/arch/arm/mach-omap2/cm.c +++ b/arch/arm/mach-omap2/cm.c @@ -50,15 +50,15 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; + mask = 1 << idlest_shift; + if (cpu_is_omap24xx()) - ena = idlest_shift; + ena = mask; else if (cpu_is_omap34xx()) ena = 0; else BUG(); - mask = 1 << idlest_shift; - /* XXX should be OMAP2 CM */ omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), MAX_MODULE_READY_TIME, i); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 03e6c9ed82a..2dbb265bedd 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -25,7 +25,6 @@ #include <plat/control.h> #include <plat/tc.h> #include <plat/board.h> -#include <plat/mux.h> #include <mach/gpio.h> #include <plat/mmc.h> #include <plat/dma.h> @@ -153,10 +152,12 @@ static struct resource omap2_mbox_resources[] = { { .start = INT_24XX_MAIL_U0_MPU, .flags = IORESOURCE_IRQ, + .name = "dsp", }, { .start = INT_24XX_MAIL_U3_MPU, .flags = IORESOURCE_IRQ, + .name = "iva", }, }; static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); @@ -175,6 +176,7 @@ static struct resource omap3_mbox_resources[] = { { .start = INT_24XX_MAIL_U0_MPU, .flags = IORESOURCE_IRQ, + .name = "dsp", }, }; static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); @@ -196,6 +198,7 @@ static struct resource omap4_mbox_resources[] = { { .start = OMAP44XX_IRQ_MAIL_U0, .flags = IORESOURCE_IRQ, + .name = "mbox", }, }; static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); @@ -205,7 +208,7 @@ static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); #endif static struct platform_device mbox_device = { - .name = "omap2-mailbox", + .name = "omap-mailbox", .id = -1, }; @@ -230,64 +233,7 @@ static inline void omap_init_mbox(void) static inline void omap_init_mbox(void) { } #endif /* CONFIG_OMAP_MBOX_FWK */ -#if defined(CONFIG_OMAP_STI) - -#if defined(CONFIG_ARCH_OMAP2) - -#define OMAP2_STI_BASE 0x48068000 -#define OMAP2_STI_CHANNEL_BASE 0x54000000 -#define OMAP2_STI_IRQ 4 - -static struct resource sti_resources[] = { - { - .start = OMAP2_STI_BASE, - .end = OMAP2_STI_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP2_STI_CHANNEL_BASE, - .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP2_STI_IRQ, - .flags = IORESOURCE_IRQ, - } -}; -#elif defined(CONFIG_ARCH_OMAP3) - -#define OMAP3_SDTI_BASE 0x54500000 -#define OMAP3_SDTI_CHANNEL_BASE 0x54600000 - -static struct resource sti_resources[] = { - { - .start = OMAP3_SDTI_BASE, - .end = OMAP3_SDTI_BASE + 0xFFF, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3_SDTI_CHANNEL_BASE, - .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, - .flags = IORESOURCE_MEM, - } -}; - -#endif - -static struct platform_device sti_device = { - .name = "sti", - .id = -1, - .num_resources = ARRAY_SIZE(sti_resources), - .resource = sti_resources, -}; - -static inline void omap_init_sti(void) -{ - platform_device_register(&sti_device); -} -#else static inline void omap_init_sti(void) {} -#endif #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) @@ -672,19 +618,19 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, OMAP_PIN_INPUT_PULLUP); if (cpu_is_omap2420() && controller_nr == 0) { - omap_cfg_reg(H18_24XX_MMC_CMD); - omap_cfg_reg(H15_24XX_MMC_CLKI); - omap_cfg_reg(G19_24XX_MMC_CLKO); - omap_cfg_reg(F20_24XX_MMC_DAT0); - omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); - omap_cfg_reg(G18_24XX_MMC_CMD_DIR); + omap_mux_init_signal("sdmmc_cmd", 0); + omap_mux_init_signal("sdmmc_clki", 0); + omap_mux_init_signal("sdmmc_clko", 0); + omap_mux_init_signal("sdmmc_dat0", 0); + omap_mux_init_signal("sdmmc_dat_dir0", 0); + omap_mux_init_signal("sdmmc_cmd_dir", 0); if (mmc_controller->slots[0].wires == 4) { - omap_cfg_reg(H14_24XX_MMC_DAT1); - omap_cfg_reg(E19_24XX_MMC_DAT2); - omap_cfg_reg(D19_24XX_MMC_DAT3); - omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); - omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); - omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); + omap_mux_init_signal("sdmmc_dat1", 0); + omap_mux_init_signal("sdmmc_dat2", 0); + omap_mux_init_signal("sdmmc_dat3", 0); + omap_mux_init_signal("sdmmc_dat_dir1", 0); + omap_mux_init_signal("sdmmc_dat_dir2", 0); + omap_mux_init_signal("sdmmc_dat_dir3", 0); } /* diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index e57fb29ff85..72220960192 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -19,8 +19,6 @@ #include <plat/board.h> #include <plat/gpmc.h> -#define WR_RD_PIN_MONITORING 0x00600000 - static struct omap_nand_platform_data *gpmc_nand_data; static struct resource gpmc_nand_resource = { @@ -71,10 +69,10 @@ static int omap2_nand_gpmc_retime(void) t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); /* Configure GPMC */ - gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | - GPMC_CONFIG1_DEVICETYPE_NAND); - + gpmc_cs_configure(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); + gpmc_cs_configure(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; @@ -82,27 +80,13 @@ static int omap2_nand_gpmc_retime(void) return 0; } -static int gpmc_nand_setup(void) -{ - struct device *dev = &gpmc_nand_device.dev; - - /* Set timings in GPMC */ - if (omap2_nand_gpmc_retime() < 0) { - dev_err(dev, "Unable to set gpmc timings\n"); - return -EINVAL; - } - - return 0; -} - int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) { - unsigned int val; int err = 0; struct device *dev = &gpmc_nand_device.dev; gpmc_nand_data = _nand_data; - gpmc_nand_data->nand_setup = gpmc_nand_setup; + gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime; gpmc_nand_device.dev.platform_data = gpmc_nand_data; err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, @@ -112,19 +96,16 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) return err; } - err = gpmc_nand_setup(); + /* Set timings in GPMC */ + err = omap2_nand_gpmc_retime(); if (err < 0) { - dev_err(dev, "NAND platform setup failed: %d\n", err); + dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } /* Enable RD PIN Monitoring Reg */ if (gpmc_nand_data->dev_ready) { - val = gpmc_cs_read_reg(gpmc_nand_data->cs, - GPMC_CS_CONFIG1); - val |= WR_RD_PIN_MONITORING; - gpmc_cs_write_reg(gpmc_nand_data->cs, - GPMC_CS_CONFIG1, val); + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); } err = platform_device_register(&gpmc_nand_device); diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5bc3ca03551..f46933bc937 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -46,8 +46,9 @@ #define GPMC_ECC_CONFIG 0x1f4 #define GPMC_ECC_CONTROL 0x1f8 #define GPMC_ECC_SIZE_CONFIG 0x1fc +#define GPMC_ECC1_RESULT 0x200 -#define GPMC_CS0 0x60 +#define GPMC_CS0_OFFSET 0x60 #define GPMC_CS_SIZE 0x30 #define GPMC_MEM_START 0x00000000 @@ -92,7 +93,8 @@ struct omap3_gpmc_regs { static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); -static unsigned gpmc_cs_map; +static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ +static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ static void __iomem *gpmc_base; @@ -108,11 +110,27 @@ static u32 gpmc_read_reg(int idx) return __raw_readl(gpmc_base + idx); } +static void gpmc_cs_write_byte(int cs, int idx, u8 val) +{ + void __iomem *reg_addr; + + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; + __raw_writeb(val, reg_addr); +} + +static u8 gpmc_cs_read_byte(int cs, int idx) +{ + void __iomem *reg_addr; + + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; + return __raw_readb(reg_addr); +} + void gpmc_cs_write_reg(int cs, int idx, u32 val) { void __iomem *reg_addr; - reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; __raw_writel(val, reg_addr); } @@ -120,7 +138,7 @@ u32 gpmc_cs_read_reg(int cs, int idx) { void __iomem *reg_addr; - reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; return __raw_readl(reg_addr); } @@ -419,8 +437,157 @@ void gpmc_cs_free(int cs) EXPORT_SYMBOL(gpmc_cs_free); /** + * gpmc_read_status - read access request to get the different gpmc status + * @cmd: command type + * @return status + */ +int gpmc_read_status(int cmd) +{ + int status = -EINVAL; + u32 regval = 0; + + switch (cmd) { + case GPMC_GET_IRQ_STATUS: + status = gpmc_read_reg(GPMC_IRQSTATUS); + break; + + case GPMC_PREFETCH_FIFO_CNT: + regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); + status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); + break; + + case GPMC_PREFETCH_COUNT: + regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); + status = GPMC_PREFETCH_STATUS_COUNT(regval); + break; + + case GPMC_STATUS_BUFFER: + regval = gpmc_read_reg(GPMC_STATUS); + /* 1 : buffer is available to write */ + status = regval & GPMC_STATUS_BUFF_EMPTY; + break; + + default: + printk(KERN_ERR "gpmc_read_status: Not supported\n"); + } + return status; +} +EXPORT_SYMBOL(gpmc_read_status); + +/** + * gpmc_cs_configure - write request to configure gpmc + * @cs: chip select number + * @cmd: command type + * @wval: value to write + * @return status of the operation + */ +int gpmc_cs_configure(int cs, int cmd, int wval) +{ + int err = 0; + u32 regval = 0; + + switch (cmd) { + case GPMC_SET_IRQ_STATUS: + gpmc_write_reg(GPMC_IRQSTATUS, wval); + break; + + case GPMC_CONFIG_WP: + regval = gpmc_read_reg(GPMC_CONFIG); + if (wval) + regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ + else + regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ + gpmc_write_reg(GPMC_CONFIG, regval); + break; + + case GPMC_CONFIG_RDY_BSY: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + if (wval) + regval |= WR_RD_PIN_MONITORING; + else + regval &= ~WR_RD_PIN_MONITORING; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + case GPMC_CONFIG_DEV_SIZE: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + regval |= GPMC_CONFIG1_DEVICESIZE(wval); + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + case GPMC_CONFIG_DEV_TYPE: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + regval |= GPMC_CONFIG1_DEVICETYPE(wval); + if (wval == GPMC_DEVICETYPE_NOR) + regval |= GPMC_CONFIG1_MUXADDDATA; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + default: + printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); + err = -EINVAL; + } + + return err; +} +EXPORT_SYMBOL(gpmc_cs_configure); + +/** + * gpmc_nand_read - nand specific read access request + * @cs: chip select number + * @cmd: command type + */ +int gpmc_nand_read(int cs, int cmd) +{ + int rval = -EINVAL; + + switch (cmd) { + case GPMC_NAND_DATA: + rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); + break; + + default: + printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); + } + return rval; +} +EXPORT_SYMBOL(gpmc_nand_read); + +/** + * gpmc_nand_write - nand specific write request + * @cs: chip select number + * @cmd: command type + * @wval: value to write + */ +int gpmc_nand_write(int cs, int cmd, int wval) +{ + int err = 0; + + switch (cmd) { + case GPMC_NAND_COMMAND: + gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); + break; + + case GPMC_NAND_ADDRESS: + gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); + break; + + case GPMC_NAND_DATA: + gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); + + default: + printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); + err = -EINVAL; + } + return err; +} +EXPORT_SYMBOL(gpmc_nand_write); + + + +/** * gpmc_prefetch_enable - configures and starts prefetch transfer - * @cs: nand cs (chip select) number + * @cs: cs (chip select) number * @dma_mode: dma mode enable (1) or disable (0) * @u32_count: number of bytes to be transferred * @is_write: prefetch read(0) or write post(1) mode @@ -428,7 +595,6 @@ EXPORT_SYMBOL(gpmc_cs_free); int gpmc_prefetch_enable(int cs, int dma_mode, unsigned int u32_count, int is_write) { - uint32_t prefetch_config1; if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { /* Set the amount of bytes to be prefetched */ @@ -437,17 +603,17 @@ int gpmc_prefetch_enable(int cs, int dma_mode, /* Set dma/mpu mode, the prefetch read / post write and * enable the engine. Set which cs is has requested for. */ - prefetch_config1 = ((cs << CS_NUM_SHIFT) | + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | PREFETCH_FIFOTHRESHOLD | ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | - (0x1 & is_write)); - gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1); + (0x1 & is_write))); + + /* Start the prefetch engine */ + gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); } else { return -EBUSY; } - /* Start the prefetch engine */ - gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); return 0; } @@ -456,24 +622,24 @@ EXPORT_SYMBOL(gpmc_prefetch_enable); /** * gpmc_prefetch_reset - disables and stops the prefetch engine */ -void gpmc_prefetch_reset(void) +int gpmc_prefetch_reset(int cs) { + u32 config1; + + /* check if the same module/cs is trying to reset */ + config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); + if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) + return -EINVAL; + /* Stop the PFPW engine */ gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); /* Reset/disable the PFPW engine */ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); -} -EXPORT_SYMBOL(gpmc_prefetch_reset); -/** - * gpmc_prefetch_status - reads prefetch status of engine - */ -int gpmc_prefetch_status(void) -{ - return gpmc_read_reg(GPMC_PREFETCH_STATUS); + return 0; } -EXPORT_SYMBOL(gpmc_prefetch_status); +EXPORT_SYMBOL(gpmc_prefetch_reset); static void __init gpmc_mem_init(void) { @@ -615,3 +781,79 @@ void omap3_gpmc_restore_context(void) } } #endif /* CONFIG_ARCH_OMAP3 */ + +/** + * gpmc_enable_hwecc - enable hardware ecc functionality + * @cs: chip select number + * @mode: read/write mode + * @dev_width: device bus width(1 for x16, 0 for x8) + * @ecc_size: bytes for which ECC will be generated + */ +int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) +{ + unsigned int val; + + /* check if ecc module is in used */ + if (gpmc_ecc_used != -EINVAL) + return -EINVAL; + + gpmc_ecc_used = cs; + + /* clear ecc and enable bits */ + val = ((0x00000001<<8) | 0x00000001); + gpmc_write_reg(GPMC_ECC_CONTROL, val); + + /* program ecc and result sizes */ + val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); + gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); + + switch (mode) { + case GPMC_ECC_READ: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); + break; + case GPMC_ECC_READSYN: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x100); + break; + case GPMC_ECC_WRITE: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); + break; + default: + printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); + break; + } + + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1); + gpmc_write_reg(GPMC_ECC_CONFIG, val); + return 0; +} + +/** + * gpmc_calculate_ecc - generate non-inverted ecc bytes + * @cs: chip select number + * @dat: data pointer over which ecc is computed + * @ecc_code: ecc code buffer + * + * Using non-inverted ECC is considered ugly since writing a blank + * page (padding) will clear the ECC bytes. This is not a problem as long + * no one is trying to write data on the seemingly unused page. Reading + * an erased page will produce an ECC mismatch between generated and read + * ECC bytes that has to be dealt with separately. + */ +int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) +{ + unsigned int val = 0x0; + + if (gpmc_ecc_used != cs) + return -EINVAL; + + /* read ecc result */ + val = gpmc_read_reg(GPMC_ECC1_RESULT); + *ecc_code++ = val; /* P128e, ..., P1e */ + *ecc_code++ = val >> 16; /* P128o, ..., P1o */ + /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ + *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); + + gpmc_ecc_used = -EINVAL; + return 0; +} diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1ef54b03610..c8f647b6205 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -268,6 +268,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; + mmc->slots[0].init_card = c->init_card; if (c->cover_only) mmc->slots[0].cover = 1; diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8d89e..1fe6f018717 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +struct mmc_card; + struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ u8 wires; /* 1/4/8 wires */ @@ -23,6 +25,8 @@ struct omap2_hsmmc_info { int ocr_mask; /* temporary HACK */ /* Remux (pad configuation) when powering on/off */ void (*remux)(struct device *dev, int slot, int power_on); + /* init some special card */ + void (*init_card)(struct mmc_card *card); }; #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index 7951ae1447e..79c478c4cb1 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -21,32 +21,19 @@ #include <plat/cpu.h> #include <plat/i2c.h> -#include <plat/mux.h> #include "mux.h" void __init omap2_i2c_mux_pins(int bus_id) { - if (cpu_is_omap24xx()) { - const int omap24xx_pins[][2] = { - { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, - { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, - }; - int scl, sda; - - scl = omap24xx_pins[bus_id - 1][0]; - sda = omap24xx_pins[bus_id - 1][1]; - omap_cfg_reg(sda); - omap_cfg_reg(scl); - } + char mux_name[sizeof("i2c2_scl.i2c2_scl")]; /* First I2C bus is not muxable */ - if (cpu_is_omap34xx() && bus_id > 1) { - char mux_name[sizeof("i2c2_scl.i2c2_scl")]; + if (bus_id == 1) + return; - sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); - omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); - sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); - omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); - } + sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); + omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); + sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); + omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); } diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a4adf..9a879f95950 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -25,6 +25,8 @@ #include <plat/control.h> #include <plat/cpu.h> +#include <mach/id.h> + static struct omap_chip_id omap_chip; static unsigned int omap_revision; @@ -102,30 +104,36 @@ static struct omap_id omap_ids[] __initdata = { static void __iomem *tap_base; static u16 tap_prod_id; -void __init omap24xx_check_revision(void) +void omap_get_die_id(struct omap_die_id *odi) +{ + odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); + odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); + odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); + odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); +} + +static void __init omap24xx_check_revision(void) { int i, j; u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; + struct omap_die_id odi; idcode = read_tap_reg(OMAP_TAP_IDCODE); prod_id = read_tap_reg(tap_prod_id); hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0x0f; dev_type = (prod_id >> 16) & 0x0f; + omap_get_die_id(&odi); pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); - pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_0)); + pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", - read_tap_reg(OMAP_TAP_DIE_ID_1), - (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); - pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_2)); - pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_3)); + odi.id_1, (odi.id_1 >> 28) & 0xf); + pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); + pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", prod_id, dev_type); @@ -164,7 +172,7 @@ void __init omap24xx_check_revision(void) omap3_features |= OMAP3_HAS_ ##feat; \ } -void __init omap3_check_features(void) +static void __init omap3_check_features(void) { u32 status; @@ -179,6 +187,8 @@ void __init omap3_check_features(void) OMAP3_CHECK_FEATURE(status, ISP); if (cpu_is_omap3630()) omap3_features |= OMAP3_HAS_192MHZ_CLK; + if (!cpu_is_omap3505() && !cpu_is_omap3517()) + omap3_features |= OMAP3_HAS_IO_WAKEUP; /* * TODO: Get additional info (where applicable) @@ -186,7 +196,7 @@ void __init omap3_check_features(void) */ } -void __init omap3_check_revision(void) +static void __init omap3_check_revision(void) { u32 cpuid, idcode; u16 hawkeye; @@ -259,15 +269,31 @@ void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: - /* FALLTHROUGH */ + /* Handle 36xx devices */ + omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + default: + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + } + break; default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP3630ES1; + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } } -void __init omap4_check_revision(void) +static void __init omap4_check_revision(void) { u32 idcode; u16 hawkeye; @@ -297,7 +323,7 @@ void __init omap4_check_revision(void) if (omap3_has_ ##feat()) \ printk(#feat" "); -void __init omap3_cpuinfo(void) +static void __init omap3_cpuinfo(void) { u8 rev = GET_OMAP_REVISION(); char cpu_name[16], cpu_rev[16]; @@ -339,6 +365,12 @@ void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-flash.h index 465169c0908..b2242ae2bb6 100644 --- a/arch/arm/mach-omap2/include/mach/board-sdp.h +++ b/arch/arm/mach-omap2/include/mach/board-flash.h @@ -12,10 +12,17 @@ */ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <plat/gpmc.h> + +#define PDC_NOR 1 +#define PDC_NAND 2 +#define PDC_ONENAND 3 +#define DBG_MPDB 4 struct flash_partitions { struct mtd_partition *parts; int nr_parts; }; -extern void sdp_flash_init(struct flash_partitions []); +extern void board_flash_init(struct flash_partitions [], + char chip_sel[][GPMC_CS_NUM]); diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index c93b29e21b7..3af69d2c3dc 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,5 +1,11 @@ /* * Defines for zoom boards */ +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#define ZOOM_NAND_CS 0 + +extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 35b24409a0c..09331bbbda5 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -36,7 +36,7 @@ omap_uart_lsr: .word 0 /* Use omap_uart_phys/virt if already configured */ 10: mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =omap_uart_phys @ physical base address + ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address ldrne \rx, =omap_uart_virt @ virtual base address ldr \rx, [\rx, #0] cmp \rx, #0 @ is port configured? @@ -89,26 +89,36 @@ omap_uart_lsr: .word 0 44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) b 98f 95: ldr \rx, =ZOOM_UART_BASE - ldr \tmp, =omap_uart_phys + mrc p15, 0, \tmp, c1, c0 + tst \tmp, #1 @ MMU enabled? + ldreq \tmp, =__virt_to_phys(omap_uart_phys) + ldrne \tmp, =omap_uart_phys str \rx, [\tmp, #0] ldr \rx, =ZOOM_UART_VIRT - ldr \tmp, =omap_uart_virt + ldreq \tmp, =__virt_to_phys(omap_uart_virt) + ldrne \tmp, =omap_uart_virt str \rx, [\tmp, #0] mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) - ldr \tmp, =omap_uart_lsr + ldreq \tmp, =__virt_to_phys(omap_uart_lsr) + ldrne \tmp, =omap_uart_lsr str \rx, [\tmp, #0] b 10b /* Store both phys and virt address for the uart */ 98: add \rx, \rx, #0x48000000 @ phys base - ldr \tmp, =omap_uart_phys + mrc p15, 0, \tmp, c1, c0 + tst \tmp, #1 @ MMU enabled? + ldreq \tmp, =__virt_to_phys(omap_uart_phys) + ldrne \tmp, =omap_uart_phys str \rx, [\tmp, #0] sub \rx, \rx, #0x48000000 @ phys base add \rx, \rx, #0xfa000000 @ virt base - ldr \tmp, =omap_uart_virt + ldreq \tmp, =__virt_to_phys(omap_uart_virt) + ldrne \tmp, =omap_uart_virt str \rx, [\tmp, #0] mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) - ldr \tmp, =omap_uart_lsr + ldreq \tmp, =__virt_to_phys(omap_uart_lsr) + ldrne \tmp, =omap_uart_lsr str \rx, [\tmp, #0] b 10b @@ -120,7 +130,10 @@ omap_uart_lsr: .word 0 .endm .macro busyuart,rd,rx -1001: ldr \rd, =omap_uart_lsr +1001: mrc p15, 0, \rd, c1, c0 + tst \rd, #1 @ MMU enabled? + ldreq \rd, =__virt_to_phys(omap_uart_lsr) + ldrne \rd, =omap_uart_lsr ldr \rd, [\rd, #0] ldrb \rd, [\rx, \rd] and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 50fd7491664..06e64e1fc28 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -177,7 +177,10 @@ omap_irq_base: .word 0 cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr .endm +#endif +#endif /* MULTI_OMAP2 */ +#ifdef CONFIG_SMP /* We assume that irqstat (the raw value of the IRQ acknowledge * register) is preserved from the macro above. * If there is an IPI, we immediately signal end of interrupt @@ -205,8 +208,7 @@ omap_irq_base: .word 0 streq \irqstat, [\base, #GIC_CPU_EOI] cmp \tmp, #0 .endm -#endif -#endif /* MULTI_OMAP2 */ +#endif /* CONFIG_SMP */ .macro irq_prio_table .endm diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h new file mode 100644 index 00000000000..02ed3aa56f1 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/id.h @@ -0,0 +1,22 @@ +/* + * OMAP2 CPU identification code + * + * Copyright (C) 2010 Kan-Ru Chen <kanru@0xlab.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP2_ARCH_ID_H +#define OMAP2_ARCH_ID_H + +struct omap_die_id { + u32 id_0; + u32 id_1; + u32 id_2; + u32 id_3; +}; + +void omap_get_die_id(struct omap_die_id *odi); + +#endif diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index 423af3a6dd3..2744dfee1ff 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -13,6 +13,13 @@ #ifndef OMAP_ARCH_OMAP4_COMMON_H #define OMAP_ARCH_OMAP4_COMMON_H +/* + * wfi used in low power code. Directly opcode is used instead + * of instruction to avoid mulit-omap build break + */ +#define do_wfi() \ + __asm__ __volatile__ (".word 0xe320f003" : : : "memory") + #ifdef CONFIG_CACHE_L2X0 extern void __iomem *l2cache_base; #endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4e1f53d0b88..b9ea70bce56 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -28,7 +28,6 @@ #include <asm/mach/map.h> -#include <plat/mux.h> #include <plat/sram.h> #include <plat/sdrc.h> #include <plat/gpmc.h> @@ -44,6 +43,7 @@ #include <plat/clockdomain.h> #include "clockdomains.h" + #include <plat/omap_hwmod.h> /* @@ -313,6 +313,8 @@ static int __init _omap2_init_reprogram_sdrc(void) void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { + u8 skip_setup_idle = 0; + pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_autodeps); if (cpu_is_omap242x()) @@ -321,7 +323,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); - omap2_mux_init(); /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); @@ -337,9 +338,13 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, pr_err("Could not init clock framework - unknown CPU\n"); omap_serial_early_init(); + +#ifndef CONFIG_PM_RUNTIME + skip_setup_idle = 1; +#endif if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ - omap_hwmod_late_init(); - omap_pm_if_init(); + omap_hwmod_late_init(skip_setup_idle); + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index e82da680d90..14ee686b649 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -44,9 +44,13 @@ #define MMU_IRQ_EMUMISS (1 << 2) #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) #define MMU_IRQ_TLBMISS (1 << 0) -#define MMU_IRQ_MASK \ - (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ - MMU_IRQ_TRANSLATIONFAULT) + +#define __MMU_IRQ_FAULT \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) +#define MMU_IRQ_MASK \ + (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) +#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) +#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) /* MMU_CNTL */ #define MMU_CNTL_SHIFT 1 @@ -61,6 +65,26 @@ ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) + +static void __iommu_set_twl(struct iommu *obj, bool on) +{ + u32 l = iommu_read_reg(obj, MMU_CNTL); + + if (on) + iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); + else + iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); + + l &= ~MMU_CNTL_MASK; + if (on) + l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); + else + l |= (MMU_CNTL_MMU_EN); + + iommu_write_reg(obj, l, MMU_CNTL); +} + + static int omap2_iommu_enable(struct iommu *obj) { u32 l, pa; @@ -96,13 +120,9 @@ static int omap2_iommu_enable(struct iommu *obj) l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); iommu_write_reg(obj, pa, MMU_TTB); - l = iommu_read_reg(obj, MMU_CNTL); - l &= ~MMU_CNTL_MASK; - l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); - iommu_write_reg(obj, l, MMU_CNTL); + __iommu_set_twl(obj, true); return 0; } @@ -118,6 +138,11 @@ static void omap2_iommu_disable(struct iommu *obj) dev_dbg(obj->dev, "%s is shutting down\n", obj->name); } +static void omap2_iommu_set_twl(struct iommu *obj, bool on) +{ + __iommu_set_twl(obj, false); +} + static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) { int i; @@ -147,7 +172,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) printk("\n"); iommu_write_reg(obj, stat, MMU_IRQSTATUS); - omap2_iommu_disable(obj); + return stat; } @@ -300,6 +325,7 @@ static const struct iommu_functions omap2_iommu_ops = { .enable = omap2_iommu_enable, .disable = omap2_iommu_disable, + .set_twl = omap2_iommu_set_twl, .fault_isr = omap2_iommu_fault_isr, .tlb_read_cr = omap2_tlb_read_cr, diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 318f3638653..42dbfa46e65 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -10,7 +10,6 @@ * for more details. */ -#include <linux/kernel.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/platform_device.h> @@ -18,8 +17,6 @@ #include <plat/mailbox.h> #include <mach/irqs.h> -#define DRV_NAME "omap2-mailbox" - #define MAILBOX_REVISION 0x000 #define MAILBOX_SYSCONFIG 0x010 #define MAILBOX_SYSSTATUS 0x014 @@ -131,7 +128,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) } l = mbox_read_reg(MAILBOX_REVISION); - pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); + pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); if (cpu_is_omap44xx()) l = OMAP4_SMARTIDLE; @@ -283,6 +280,8 @@ static struct omap_mbox_ops omap2_mbox_ops = { */ /* FIXME: the following structs should be filled automatically by the user id */ + +#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420) /* DSP */ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { .tx_fifo = { @@ -300,10 +299,46 @@ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { .irqdisable = MAILBOX_IRQENABLE(0), }; +struct omap_mbox mbox_dsp_info = { + .name = "dsp", + .ops = &omap2_mbox_ops, + .priv = &omap2_mbox_dsp_priv, +}; +#endif + +#if defined(CONFIG_ARCH_OMAP3430) +struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; +#endif + +#if defined(CONFIG_ARCH_OMAP2420) +/* IVA */ +static struct omap_mbox2_priv omap2_mbox_iva_priv = { + .tx_fifo = { + .msg = MAILBOX_MESSAGE(2), + .fifo_stat = MAILBOX_FIFOSTATUS(2), + }, + .rx_fifo = { + .msg = MAILBOX_MESSAGE(3), + .msg_stat = MAILBOX_MSGSTATUS(3), + }, + .irqenable = MAILBOX_IRQENABLE(3), + .irqstatus = MAILBOX_IRQSTATUS(3), + .notfull_bit = MAILBOX_IRQ_NOTFULL(2), + .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), + .irqdisable = MAILBOX_IRQENABLE(3), +}; + +static struct omap_mbox mbox_iva_info = { + .name = "iva", + .ops = &omap2_mbox_ops, + .priv = &omap2_mbox_iva_priv, +}; +struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL }; +#endif -/* OMAP4 specific data structure. Use the cpu_is_omap4xxx() -to use this*/ +#if defined(CONFIG_ARCH_OMAP4) +/* OMAP4 */ static struct omap_mbox2_priv omap2_mbox_1_priv = { .tx_fifo = { .msg = MAILBOX_MESSAGE(0), @@ -325,14 +360,6 @@ struct omap_mbox mbox_1_info = { .ops = &omap2_mbox_ops, .priv = &omap2_mbox_1_priv, }; -EXPORT_SYMBOL(mbox_1_info); - -struct omap_mbox mbox_dsp_info = { - .name = "dsp", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_dsp_priv, -}; -EXPORT_SYMBOL(mbox_dsp_info); static struct omap_mbox2_priv omap2_mbox_2_priv = { .tx_fifo = { @@ -355,110 +382,64 @@ struct omap_mbox mbox_2_info = { .ops = &omap2_mbox_ops, .priv = &omap2_mbox_2_priv, }; -EXPORT_SYMBOL(mbox_2_info); - - -#if defined(CONFIG_ARCH_OMAP2420) /* IVA */ -static struct omap_mbox2_priv omap2_mbox_iva_priv = { - .tx_fifo = { - .msg = MAILBOX_MESSAGE(2), - .fifo_stat = MAILBOX_FIFOSTATUS(2), - }, - .rx_fifo = { - .msg = MAILBOX_MESSAGE(3), - .msg_stat = MAILBOX_MSGSTATUS(3), - }, - .irqenable = MAILBOX_IRQENABLE(3), - .irqstatus = MAILBOX_IRQSTATUS(3), - .notfull_bit = MAILBOX_IRQ_NOTFULL(2), - .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), - .irqdisable = MAILBOX_IRQENABLE(3), -}; -static struct omap_mbox mbox_iva_info = { - .name = "iva", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_iva_priv, -}; +struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL }; #endif static int __devinit omap2_mbox_probe(struct platform_device *pdev) { - struct resource *res; + struct resource *mem; int ret; + struct omap_mbox **list; - /* MBOX base */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid mem resource\n"); - return -ENODEV; + if (false) + ; +#if defined(CONFIG_ARCH_OMAP3430) + else if (cpu_is_omap3430()) { + list = omap3_mboxes; + + list[0]->irq = platform_get_irq_byname(pdev, "dsp"); } - mbox_base = ioremap(res->start, resource_size(res)); - if (!mbox_base) - return -ENOMEM; +#endif +#if defined(CONFIG_ARCH_OMAP2420) + else if (cpu_is_omap2420()) { + list = omap2_mboxes; - /* DSP or IVA2 IRQ */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + list[0]->irq = platform_get_irq_byname(pdev, "dsp"); + list[1]->irq = platform_get_irq_byname(pdev, "iva"); + } +#endif +#if defined(CONFIG_ARCH_OMAP4) + else if (cpu_is_omap44xx()) { + list = omap4_mboxes; - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid irq resource\n"); - ret = -ENODEV; - goto err_dsp; + list[0]->irq = list[1]->irq = + platform_get_irq_byname(pdev, "mbox"); } - if (cpu_is_omap44xx()) { - mbox_1_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_1_info); - } else { - mbox_dsp_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); +#endif + else { + pr_err("%s: platform not supported\n", __func__); + return -ENODEV; } - if (ret) - goto err_dsp; - if (cpu_is_omap44xx()) { - mbox_2_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_2_info); - if (ret) { - omap_mbox_unregister(&mbox_1_info); - goto err_dsp; - } - } -#if defined(CONFIG_ARCH_OMAP2420) /* IVA */ - if (cpu_is_omap2420()) { - /* IVA IRQ */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid irq resource\n"); - ret = -ENODEV; - omap_mbox_unregister(&mbox_dsp_info); - goto err_dsp; - } - mbox_iva_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_iva_info); - if (ret) { - omap_mbox_unregister(&mbox_dsp_info); - goto err_dsp; - } + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox_base = ioremap(mem->start, resource_size(mem)); + if (!mbox_base) + return -ENOMEM; + + ret = omap_mbox_register(&pdev->dev, list); + if (ret) { + iounmap(mbox_base); + return ret; } -#endif return 0; -err_dsp: - iounmap(mbox_base); return ret; } static int __devexit omap2_mbox_remove(struct platform_device *pdev) { -#if defined(CONFIG_ARCH_OMAP2420) - omap_mbox_unregister(&mbox_iva_info); -#endif - - if (cpu_is_omap44xx()) { - omap_mbox_unregister(&mbox_2_info); - omap_mbox_unregister(&mbox_1_info); - } else - omap_mbox_unregister(&mbox_dsp_info); + omap_mbox_unregister(); iounmap(mbox_base); return 0; } @@ -467,7 +448,7 @@ static struct platform_driver omap2_mbox_driver = { .probe = omap2_mbox_probe, .remove = __devexit_p(omap2_mbox_remove), .driver = { - .name = DRV_NAME, + .name = "omap-mailbox", }, }; @@ -486,5 +467,6 @@ module_exit(omap2_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions"); -MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt"); -MODULE_ALIAS("platform:"DRV_NAME); +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); +MODULE_AUTHOR("Paul Mundt"); +MODULE_ALIAS("platform:omap2-mailbox"); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index c29337074ad..467aae24578 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -20,17 +20,18 @@ #include <mach/irqs.h> #include <plat/dma.h> -#include <plat/mux.h> #include <plat/cpu.h> #include <plat/mcbsp.h> +#include "mux.h" + static void omap2_mcbsp2_mux_setup(void) { - omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); - omap_cfg_reg(R14_24XX_MCBSP2_FSX); - omap_cfg_reg(W15_24XX_MCBSP2_DR); - omap_cfg_reg(V15_24XX_MCBSP2_DX); - omap_cfg_reg(V14_24XX_GPIO117); + omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); + omap_mux_init_gpio(117, OMAP_PULL_ENA); /* * TODO: Need to add MUX settings for OMAP 2430 SDP */ @@ -133,7 +134,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { .phys_base = OMAP34XX_MCBSP2_BASE, @@ -143,7 +144,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x3FF, + .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { .phys_base = OMAP34XX_MCBSP3_BASE, @@ -153,7 +154,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { .phys_base = OMAP34XX_MCBSP4_BASE, @@ -162,7 +163,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { .phys_base = OMAP34XX_MCBSP5_BASE, @@ -171,7 +172,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 8b3d26935a3..ab403b2ed26 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -37,12 +37,12 @@ #include <asm/system.h> #include <plat/control.h> -#include <plat/mux.h> #include "mux.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ #define OMAP_MUX_BASE_SZ 0x5ca +#define MUXABLE_GPIO_MODE3 BIT(0) struct omap_mux_entry { struct omap_mux mux; @@ -51,6 +51,7 @@ struct omap_mux_entry { static unsigned long mux_phys; static void __iomem *mux_base; +static u8 omap_mux_flags; u16 omap_mux_read(u16 reg) { @@ -76,301 +77,6 @@ void omap_mux_write_array(struct omap_board_mux *board_mux) } } -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX) - -static struct omap_mux_cfg arch_mux_cfg; - -/* NOTE: See mux.h for the enumeration */ - -static struct pin_config __initdata_or_module omap24xx_pins[] = { -/* - * description mux mux pull pull debug - * offset mode ena type - */ - -/* 24xx I2C */ -MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1) -MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1) -MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1) - -/* Menelaus interrupt */ -MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) - -/* 24xx clocks */ -MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) - -/* 24xx GPMC chipselects, wait pin monitoring */ -MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) -MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) -MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) -MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) -MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) -MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1) - -/* 24xx McBSP */ -MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1) -MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1) -MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1) -MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) - -/* 24xx GPIO */ -MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) -MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) -MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) -MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) -MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) -MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) -MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) -MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) -MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) -MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1) -MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) -MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1) -MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1) -MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1) -MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) -MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) -MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) - -/* 242x DBG GPIO */ -MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1) -MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1) -MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1) -MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1) -MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1) -MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1) -MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1) -MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1) -MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1) -MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1) - -/* 24xx external DMA requests */ -MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) -MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) -MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) -MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) -MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) - -/* UART3 */ -MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) -MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) - -/* MMC/SDIO */ -MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1) -MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1) -MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1) -MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1) -MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1) -MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1) -MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1) -MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1) -MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1) -MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1) -MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1) -MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1) - -/* Full speed USB */ -MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1) -MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1) -MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1) -MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1) -MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1) -MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1) -MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1) - -MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1) -MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1) -MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1) -MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1) -MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1) -MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1) -MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1) -MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1) - -MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1) -MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1) -MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1) -MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1) -MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1) - -/* Keypad GPIO*/ -MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) -MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) -MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1) -MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1) -MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1) -MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1) -MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1) -MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1) -MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1) -MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1) -MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1) -MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1) -MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1) - -/* 24xx Menelaus Keypad GPIO */ -MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1) -MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) -MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) - -/* 2430 USB */ -MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1) -MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1) -MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1) -MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1) -MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1) -MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1) -MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1) -MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1) -MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1) -MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1) -MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1) - -/* 2430 HS-USB */ -MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1) -MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1) -MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1) -MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1) -MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1) -MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1) -MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1) -MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1) -MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1) -MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1) -MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1) -MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) - -/* 2430 McBSP */ -MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1) - -MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1) -MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1) -MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1) -MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1) -MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1) -MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1) - -MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) -MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) -MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) -MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1) -MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1) -MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) -MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) -MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) - -MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1) -MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1) -MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1) -MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1) - -MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1) -MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1) -MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1) -MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1) - -MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1) -MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1) -MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1) -MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1) - -/* 2430 MCSPI1 */ -MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1) -MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1) -MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1) -MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1) - -/* Touchscreen GPIO */ -MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1) - -}; - -#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) - -#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) - -static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg) -{ - u16 orig; - u8 warn = 0, debug = 0; - - orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET); - -#ifdef CONFIG_OMAP_MUX_DEBUG - debug = cfg->debug; -#endif - warn = (orig != reg); - if (debug || warn) - printk(KERN_WARNING - "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n", - cfg->name, omap_ctrl_base_get() + cfg->mux_reg, - orig, reg); -} -#else -#define omap2_cfg_debug(x, y) do {} while (0) -#endif - -static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) -{ - static DEFINE_SPINLOCK(mux_spin_lock); - unsigned long flags; - u8 reg = 0; - - spin_lock_irqsave(&mux_spin_lock, flags); - reg |= cfg->mask & 0x7; - if (cfg->pull_val) - reg |= OMAP2_PULL_ENA; - if (cfg->pu_pd_val) - reg |= OMAP2_PULL_UP; - omap2_cfg_debug(cfg, reg); - omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET); - spin_unlock_irqrestore(&mux_spin_lock, flags); - - return 0; -} - -int __init omap2_mux_init(void) -{ - u32 mux_pbase; - - if (cpu_is_omap2420()) - mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET; - else if (cpu_is_omap2430()) - mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET; - else - return -ENODEV; - - mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ); - if (!mux_base) { - printk(KERN_ERR "mux: Could not ioremap\n"); - return -ENODEV; - } - - if (cpu_is_omap24xx()) { - arch_mux_cfg.pins = omap24xx_pins; - arch_mux_cfg.size = OMAP24XX_PINS_SZ; - arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; - - return omap_mux_register(&arch_mux_cfg); - } - - return 0; -} - -#else -int __init omap2_mux_init(void) -{ - return 0; -} -#endif /* CONFIG_OMAP_MUX */ - -/*----------------------------------------------------------------------------*/ - -#ifdef CONFIG_ARCH_OMAP3 static LIST_HEAD(muxmodes); static DEFINE_MUTEX(muxmode_mutex); @@ -381,6 +87,9 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; + struct omap_mux *gpio_mux; + u16 old_mode; + u16 mux_mode; int found = 0; if (!gpio) @@ -389,31 +98,33 @@ int __init omap_mux_init_gpio(int gpio, int val) list_for_each_entry(e, &muxmodes, node) { struct omap_mux *m = &e->mux; if (gpio == m->gpio) { - u16 old_mode; - u16 mux_mode; - - old_mode = omap_mux_read(m->reg_offset); - mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); - mux_mode |= OMAP_MUX_MODE4; - printk(KERN_DEBUG "mux: Setting signal " - "%s.gpio%i 0x%04x -> 0x%04x\n", - m->muxnames[0], gpio, old_mode, mux_mode); - omap_mux_write(mux_mode, m->reg_offset); + gpio_mux = m; found++; } } - if (found == 1) - return 0; + if (found == 0) { + printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + return -ENODEV; + } if (found > 1) { - printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio); + printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", + found, gpio); return -EINVAL; } - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + old_mode = omap_mux_read(gpio_mux->reg_offset); + mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); + if (omap_mux_flags & MUXABLE_GPIO_MODE3) + mux_mode |= OMAP_MUX_MODE3; + else + mux_mode |= OMAP_MUX_MODE4; + printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", + gpio_mux->muxnames[0], gpio, old_mode, mux_mode); + omap_mux_write(mux_mode, gpio_mux->reg_offset); - return -ENODEV; + return 0; } int __init omap_mux_init_signal(char *muxname, int val) @@ -1032,6 +743,9 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, return -ENODEV; } + if (cpu_is_omap24xx()) + omap_mux_flags = MUXABLE_GPIO_MODE3; + omap_mux_init_package(superset, package_subset, package_balls); omap_mux_init_list(superset); omap_mux_init_signals(board_mux); @@ -1039,5 +753,3 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, return 0; } -#endif /* CONFIG_ARCH_OMAP3 */ - diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 480abc56e60..a8e040c2c7e 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -7,6 +7,8 @@ * published by the Free Software Foundation. */ +#include "mux2420.h" +#include "mux2430.h" #include "mux34xx.h" #define OMAP_MUX_TERMINATOR 0xffff @@ -56,10 +58,12 @@ /* Flags for omap_mux_init */ #define OMAP_PACKAGE_MASK 0xffff -#define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */ -#define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */ -#define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */ -#define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */ +#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ +#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ +#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ +#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */ +#define OMAP_PACKAGE_ZAC 2 /* 24xx 447-pin POP */ +#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ #define OMAP_MUX_NR_MODES 8 /* Available modes */ @@ -102,7 +106,7 @@ struct omap_board_mux { u16 value; }; -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_OMAP_MUX) /** * omap_mux_init_gpio - initialize a signal based on the GPIO number @@ -171,6 +175,20 @@ void omap_mux_write(u16 val, u16 mux_offset); void omap_mux_write_array(struct omap_board_mux *board_mux); /** + * omap2420_mux_init() - initialize mux system with board specific set + * @board_mux: Board specific mux table + * @flags: OMAP package type used for the board + */ +int omap2420_mux_init(struct omap_board_mux *board_mux, int flags); + +/** + * omap2430_mux_init() - initialize mux system with board specific set + * @board_mux: Board specific mux table + * @flags: OMAP package type used for the board + */ +int omap2430_mux_init(struct omap_board_mux *board_mux, int flags); + +/** * omap3_mux_init() - initialize mux system with board specific set * @board_mux: Board specific mux table * @flags: OMAP package type used for the board diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c new file mode 100644 index 00000000000..fdb04a7eb8a --- /dev/null +++ b/arch/arm/mach-omap2/mux2420.c @@ -0,0 +1,688 @@ +/* + * Copyright (C) 2010 Nokia + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> + +#include "mux.h" + +#ifdef CONFIG_OMAP_MUX + +#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +} + +#else + +#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ +} + +#endif + +#define _OMAP2420_BALLENTRY(M0, bb, bt) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ + .balls = { bb, bt }, \ +} + +/* + * Superset of all mux modes for omap2420 + */ +static struct omap_mux __initdata omap2420_muxmodes[] = { + _OMAP2420_MUXENTRY(CAM_D0, 54, + "cam_d0", "hw_dbg2", "sti_dout", "gpio_54", + NULL, NULL, "etk_d2", NULL), + _OMAP2420_MUXENTRY(CAM_D1, 53, + "cam_d1", "hw_dbg3", "sti_din", "gpio_53", + NULL, NULL, "etk_d3", NULL), + _OMAP2420_MUXENTRY(CAM_D2, 52, + "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52", + NULL, NULL, "etk_d4", NULL), + _OMAP2420_MUXENTRY(CAM_D3, 51, + "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51", + NULL, NULL, "etk_d5", NULL), + _OMAP2420_MUXENTRY(CAM_D4, 50, + "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50", + NULL, NULL, "etk_d6", NULL), + _OMAP2420_MUXENTRY(CAM_D5, 49, + "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49", + NULL, NULL, "etk_d7", NULL), + _OMAP2420_MUXENTRY(CAM_D6, 0, + "cam_d6", "hw_dbg8", NULL, NULL, + NULL, NULL, "etk_d8", NULL), + _OMAP2420_MUXENTRY(CAM_D7, 0, + "cam_d7", "hw_dbg9", NULL, NULL, + NULL, NULL, "etk_d9", NULL), + _OMAP2420_MUXENTRY(CAM_D8, 54, + "cam_d8", "hw_dbg10", NULL, "gpio_54", + NULL, NULL, "etk_d10", NULL), + _OMAP2420_MUXENTRY(CAM_D9, 53, + "cam_d9", "hw_dbg11", NULL, "gpio_53", + NULL, NULL, "etk_d11", NULL), + _OMAP2420_MUXENTRY(CAM_HS, 55, + "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55", + NULL, NULL, "etk_d1", NULL), + _OMAP2420_MUXENTRY(CAM_LCLK, 57, + "cam_lclk", NULL, "mcbsp_clks", "gpio_57", + NULL, NULL, "etk_c1", NULL), + _OMAP2420_MUXENTRY(CAM_VS, 56, + "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56", + NULL, NULL, "etk_d0", NULL), + _OMAP2420_MUXENTRY(CAM_XCLK, 0, + "cam_xclk", NULL, "sti_clk", NULL, + NULL, NULL, "etk_c2", NULL), + _OMAP2420_MUXENTRY(DSS_ACBIAS, 48, + "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA10, 40, + "dss_data10", NULL, NULL, "gpio_40", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA11, 41, + "dss_data11", NULL, NULL, "gpio_41", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA12, 42, + "dss_data12", NULL, NULL, "gpio_42", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA13, 43, + "dss_data13", NULL, NULL, "gpio_43", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA14, 44, + "dss_data14", NULL, NULL, "gpio_44", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA15, 45, + "dss_data15", NULL, NULL, "gpio_45", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA16, 46, + "dss_data16", NULL, NULL, "gpio_46", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA17, 47, + "dss_data17", NULL, NULL, "gpio_47", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA8, 38, + "dss_data8", NULL, NULL, "gpio_38", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA9, 39, + "dss_data9", NULL, NULL, "gpio_39", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_DIN, 115, + "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116, + "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_FS, 114, + "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117, + "eac_ac_mclk", NULL, NULL, "gpio_117", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_RST, 118, + "eac_ac_rst", "eac_bt_din", NULL, "gpio_118", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113, + "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_BT_DIN, 73, + "eac_bt_din", NULL, NULL, "gpio_73", + NULL, NULL, "etk_d9", NULL), + _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74, + "eac_bt_dout", NULL, "sti_clk", "gpio_74", + NULL, NULL, "etk_d8", NULL), + _OMAP2420_MUXENTRY(EAC_BT_FS, 72, + "eac_bt_fs", NULL, NULL, "gpio_72", + NULL, NULL, "etk_d10", NULL), + _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71, + "eac_bt_sclk", NULL, NULL, "gpio_71", + NULL, NULL, "etk_d11", NULL), + _OMAP2420_MUXENTRY(GPIO_119, 119, + "gpio_119", NULL, "sti_din", "gpio_119", + NULL, "sys_boot0", "etk_d12", NULL), + _OMAP2420_MUXENTRY(GPIO_120, 120, + "gpio_120", NULL, "sti_dout", "gpio_120", + "cam_d9", "sys_boot1", "etk_d13", NULL), + _OMAP2420_MUXENTRY(GPIO_121, 121, + "gpio_121", NULL, NULL, "gpio_121", + "jtag_emu2", "sys_boot2", "etk_d14", NULL), + _OMAP2420_MUXENTRY(GPIO_122, 122, + "gpio_122", NULL, NULL, "gpio_122", + "jtag_emu3", "sys_boot3", "etk_d15", NULL), + _OMAP2420_MUXENTRY(GPIO_124, 124, + "gpio_124", NULL, NULL, "gpio_124", + NULL, "sys_boot5", NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_125, 125, + "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_36, 36, + "gpio_36", NULL, NULL, "gpio_36", + NULL, "sys_boot4", NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_62, 62, + "gpio_62", "uart1_rx", "usb1_dat", "gpio_62", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_6, 6, + "gpio_6", "tv_detpulse", NULL, "gpio_6", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A10, 3, + "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A1, 12, + "gpmc_a1", "dss_data18", NULL, "gpio_12", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A2, 11, + "gpmc_a2", "dss_data19", NULL, "gpio_11", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A3, 10, + "gpmc_a3", "dss_data20", NULL, "gpio_10", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A4, 9, + "gpmc_a4", "dss_data21", NULL, "gpio_9", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A5, 8, + "gpmc_a5", "dss_data22", NULL, "gpio_8", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A6, 7, + "gpmc_a6", "dss_data23", NULL, "gpio_7", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A7, 6, + "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A8, 5, + "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A9, 4, + "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_CLK, 21, + "gpmc_clk", NULL, NULL, "gpio_21", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D10, 18, + "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D11, 17, + "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D12, 16, + "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D13, 15, + "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D14, 14, + "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D15, 13, + "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D8, 20, + "gpmc_d8", NULL, NULL, "gpio_20", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D9, 19, + "gpmc_d9", "ssi2_wake", NULL, "gpio_19", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NBE0, 29, + "gpmc_nbe0", NULL, NULL, "gpio_29", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NBE1, 30, + "gpmc_nbe1", NULL, NULL, "gpio_30", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS1, 22, + "gpmc_ncs1", NULL, NULL, "gpio_22", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS2, 23, + "gpmc_ncs2", NULL, NULL, "gpio_23", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS3, 24, + "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS4, 25, + "gpmc_ncs4", NULL, NULL, "gpio_25", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS5, 26, + "gpmc_ncs5", NULL, NULL, "gpio_26", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS6, 27, + "gpmc_ncs6", NULL, NULL, "gpio_27", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS7, 28, + "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NWP, 31, + "gpmc_nwp", NULL, NULL, "gpio_31", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_WAIT1, 33, + "gpmc_wait1", NULL, NULL, "gpio_33", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_WAIT2, 34, + "gpmc_wait2", NULL, NULL, "gpio_34", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_WAIT3, 35, + "gpmc_wait3", NULL, NULL, "gpio_35", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(HDQ_SIO, 101, + "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(I2C2_SCL, 99, + "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(I2C2_SDA, 100, + "i2c2_sda", NULL, "spi2_ncs1", "gpio_100", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(JTAG_EMU0, 127, + "jtag_emu0", NULL, NULL, "gpio_127", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(JTAG_EMU1, 126, + "jtag_emu1", NULL, NULL, "gpio_126", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92, + "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98, + "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_DR, 95, + "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_DX, 94, + "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_FSR, 93, + "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93", + "spi2_ncs1", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_FSX, 97, + "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12, + "mcbsp2_clkx", NULL, "dss_data23", "gpio_12", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP2_DR, 11, + "mcbsp2_dr", NULL, "dss_data22", "gpio_11", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP_CLKS, 96, + "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CLKI, 59, + "sdmmc_clki", "ms_clki", NULL, "gpio_59", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CLKO, 0, + "sdmmc_clko", "ms_clko", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8, + "sdmmc_cmd_dir", NULL, NULL, "gpio_8", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CMD, 0, + "sdmmc_cmd", "ms_bs", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7, + "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT0, 0, + "sdmmc_dat0", "ms_dat0", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78, + "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT1, 75, + "sdmmc_dat1", "ms_dat1", NULL, "gpio_75", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79, + "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT2, 76, + "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80, + "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT3, 77, + "sdmmc_dat3", "ms_dat3", NULL, "gpio_77", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_A12, 2, + "sdrc_a12", NULL, NULL, "gpio_2", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_A13, 1, + "sdrc_a13", NULL, NULL, "gpio_1", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_A14, 0, + "sdrc_a14", NULL, NULL, "gpio_0", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_CKE1, 38, + "sdrc_cke1", NULL, NULL, "gpio_38", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_NCS1, 37, + "sdrc_ncs1", NULL, NULL, "gpio_37", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_CLK, 81, + "spi1_clk", NULL, NULL, "gpio_81", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS0, 84, + "spi1_ncs0", NULL, NULL, "gpio_84", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS1, 85, + "spi1_ncs1", NULL, NULL, "gpio_85", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS2, 86, + "spi1_ncs2", NULL, NULL, "gpio_86", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS3, 87, + "spi1_ncs3", NULL, NULL, "gpio_87", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_SIMO, 82, + "spi1_simo", NULL, NULL, "gpio_82", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_SOMI, 83, + "spi1_somi", NULL, NULL, "gpio_83", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_CLK, 88, + "spi2_clk", NULL, NULL, "gpio_88", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_NCS0, 91, + "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_SIMO, 89, + "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_SOMI, 90, + "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63, + "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59, + "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64, + "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25, + "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65, + "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61, + "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_WAKE, 66, + "ssi1_wake", "eac_md_fs", NULL, "gpio_66", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SYS_CLKOUT, 123, + "sys_clkout", NULL, NULL, "gpio_123", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SYS_CLKREQ, 52, + "sys_clkreq", NULL, NULL, "gpio_52", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SYS_NIRQ, 60, + "sys_nirq", NULL, NULL, "gpio_60", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_CTS, 32, + "uart1_cts", NULL, "dss_data18", "gpio_32", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_RTS, 8, + "uart1_rts", NULL, "dss_data19", "gpio_8", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_RX, 10, + "uart1_rx", NULL, "dss_data21", "gpio_10", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_TX, 9, + "uart1_tx", NULL, "dss_data20", "gpio_9", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_CTS, 67, + "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_RTS, 68, + "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_RX, 70, + "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_TX, 69, + "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102, + "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_RTS_SD, 103, + "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105, + "uart3_rx_irrx", NULL, NULL, "gpio_105", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104, + "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_DAT, 112, + "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112", + "uart2_tx", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_PUEN, 106, + "usb0_puen", "mcbsp2_dx", NULL, "gpio_106", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_RCV, 109, + "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109", + "uart2_cts", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_SE0, 111, + "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111", + "uart2_rx", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_TXEN, 110, + "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_VM, 108, + "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108", + "uart2_rx", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_VP, 107, + "usb0_vp", "mcbsp2_dr", NULL, "gpio_107", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_CLK, 13, + "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_NLA, 58, + "vlynq_nla", NULL, NULL, "gpio_58", + "cam_d6", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_RX0, 15, + "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15", + "cam_d7", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_RX1, 14, + "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14", + "cam_d8", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_TX0, 17, + "vlynq_tx0", "usb2_txen", NULL, "gpio_17", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_TX1, 16, + "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16", + NULL, NULL, NULL, NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 447-pin POP package + */ +#ifdef CONFIG_DEBUG_FS +struct omap_ball __initdata omap2420_pop_ball[] = { + _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), + _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), + _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), + _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL), + _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL), + _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL), + _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL), + _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL), + _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL), + _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL), + _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL), + _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL), + _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL), + _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL), + _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL), + _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL), + _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL), + _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL), + _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL), + _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL), + _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL), + _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL), + _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL), + _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL), + _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL), + _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL), + _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL), + _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL), + _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL), + _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL), + _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL), + _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL), + _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL), + _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL), + _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL), + _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL), + _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL), + _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL), + _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL), + _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL), + _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL), + _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL), + _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL), + _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL), + _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL), + _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL), + _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL), + _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL), + _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL), + _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL), + _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"), + _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"), + _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"), + _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"), + _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"), + _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"), + _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"), + _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"), + _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"), + _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"), + _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"), + _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL), + _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"), + _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"), + _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL), + _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL), + _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL), + _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL), + _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL), + _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL), + _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL), + _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL), + _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL), + _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL), + _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL), + _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL), + _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL), + _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL), + _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL), + _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL), + _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL), + _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL), + _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL), + _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL), + _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL), + _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL), + _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL), + _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL), + _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"), + _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"), + _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"), + _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"), + _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"), + _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL), + _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL), + _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL), + _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL), + _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL), + _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL), + _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL), + _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL), + _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL), + _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL), + _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL), + _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL), + _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL), + _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL), + _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL), + _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL), + _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL), + _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL), + _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL), + _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL), + _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL), + _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL), + _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL), + _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL), + _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL), + _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL), + _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL), + _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL), + _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL), + _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL), + _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL), + _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL), + _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL), + _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL), + _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL), + _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL), + _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL), + _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL), + _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL), + _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL), + _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL), + _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap2420_pop_ball NULL +#endif + +int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) +{ + struct omap_ball *package_balls = NULL; + + switch (flags & OMAP_PACKAGE_MASK) { + case OMAP_PACKAGE_ZAC: + package_balls = omap2420_pop_ball; + break; + case OMAP_PACKAGE_ZAF: + /* REVISIT: Please add data */ + default: + pr_warning("mux: No ball data available for omap2420 package\n"); + } + + return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, + OMAP2420_CONTROL_PADCONF_MUX_SIZE, + omap2420_muxmodes, NULL, board_subset, + package_balls); +} diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h new file mode 100644 index 00000000000..0f555aa847b --- /dev/null +++ b/arch/arm/mach-omap2/mux2420.h @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2009 Nokia + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU + +#define OMAP2420_MUX(mode0, mux_value) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \ + .value = (mux_value), \ +} + +/* + * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing + * + * Extracted from the TRM. Add 0x48000030 to these values to get the + * absolute addresses. The name in the macro is the mode-0 name of + * the pin. NOTE: These registers are 8-bits wide. + */ +#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000 +#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001 +#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002 +#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003 +#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004 +#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005 +#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006 +#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007 +#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008 +#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009 +#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a +#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b +#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c +#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d +#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e +#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f +#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010 +#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021 +#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022 +#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023 +#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024 +#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025 +#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026 +#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027 +#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028 +#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029 +#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a +#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b +#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c +#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d +#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e +#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f +#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030 +#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031 +#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032 +#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033 +#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034 +#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035 +#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036 +#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037 +#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038 +#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039 +#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a +#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b +#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c +#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d +#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e +#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f +#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040 +#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041 +#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042 +#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043 +#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044 +#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045 +#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046 +#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047 +#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048 +#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049 +#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a +#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b +#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c +#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d +#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e +#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f +#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050 +#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051 +#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052 +#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053 +#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054 +#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055 +#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056 +#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057 +#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058 +#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059 +#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a +#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060 +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061 +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062 +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063 +#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064 +#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065 +#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066 +#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067 +#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068 +#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069 +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d +#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e +#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f +#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070 +#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071 +#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072 +#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073 +#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074 +#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075 +#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080 +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081 +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a +#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b +#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c +#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d +#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e +#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f +#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094 +#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095 +#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096 +#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097 +#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098 +#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099 +#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a +#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b +#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c +#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d +#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e +#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f +#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0 +#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1 +#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2 +#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3 +#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4 +#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5 +#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6 +#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7 +#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8 +#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9 +#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa +#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab +#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac +#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad +#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae +#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af +#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0 +#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1 +#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2 +#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3 +#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba +#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb +#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc +#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd +#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be +#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf +#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0 +#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1 +#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2 +#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3 +#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc +#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd +#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce +#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf +#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0 +#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5 +#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6 +#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7 +#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8 +#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9 +#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da +#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db +#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc +#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd +#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de +#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df +#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0 +#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1 +#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2 +#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3 +#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4 +#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5 +#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6 +#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7 +#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8 +#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9 +#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea +#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb +#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec +#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed +#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee +#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef +#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0 +#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1 +#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2 +#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9 +#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa +#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb +#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc +#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd +#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe +#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff +#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100 +#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101 +#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102 +#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103 +#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104 +#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105 +#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106 +#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107 +#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108 +#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109 +#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a +#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b +#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c +#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d +#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e +#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f +#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110 +#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111 +#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112 + +#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \ + (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c new file mode 100644 index 00000000000..7dcaaa8af32 --- /dev/null +++ b/arch/arm/mach-omap2/mux2430.c @@ -0,0 +1,791 @@ +/* + * Copyright (C) 2010 Nokia + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> + +#include "mux.h" + +#ifdef CONFIG_OMAP_MUX + +#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +} + +#else + +#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ +} + +#endif + +#define _OMAP2430_BALLENTRY(M0, bb, bt) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ + .balls = { bb, bt }, \ +} + +/* + * Superset of all mux modes for omap2430 + */ +static struct omap_mux __initdata omap2430_muxmodes[] = { + _OMAP2430_MUXENTRY(CAM_D0, 133, + "cam_d0", "hw_dbg0", "sti_dout", "gpio_133", + NULL, NULL, "etk_d2", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D10, 146, + "cam_d10", NULL, NULL, "gpio_146", + NULL, NULL, "etk_d12", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D11, 145, + "cam_d11", NULL, NULL, "gpio_145", + NULL, NULL, "etk_d13", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D1, 132, + "cam_d1", "hw_dbg1", "sti_din", "gpio_132", + NULL, NULL, "etk_d3", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D2, 129, + "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129", + NULL, NULL, "etk_d4", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D3, 128, + "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128", + NULL, NULL, "etk_d5", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D4, 143, + "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143", + NULL, NULL, "etk_d6", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D5, 112, + "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112", + NULL, NULL, "etk_d7", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D6, 137, + "cam_d6", "hw_dbg6", NULL, "gpio_137", + NULL, NULL, "etk_d8", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D7, 136, + "cam_d7", "hw_dbg7", NULL, "gpio_136", + NULL, NULL, "etk_d9", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D8, 135, + "cam_d8", "hw_dbg8", NULL, "gpio_135", + NULL, NULL, "etk_d10", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D9, 134, + "cam_d9", "hw_dbg9", NULL, "gpio_134", + NULL, NULL, "etk_d11", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_HS, 11, + "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11", + NULL, NULL, "etk_d1", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_LCLK, 0, + "cam_lclk", NULL, "mcbsp_clks", NULL, + NULL, NULL, "etk_c1", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_VS, 12, + "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12", + NULL, NULL, "etk_d0", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_XCLK, 0, + "cam_xclk", NULL, "sti_clk", NULL, + NULL, NULL, "etk_c2", NULL), + _OMAP2430_MUXENTRY(DSS_ACBIAS, 48, + "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA0, 40, + "dss_data0", "uart1_cts", NULL, "gpio_40", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA10, 128, + "dss_data10", "sdi_data1n", NULL, "gpio_128", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA11, 129, + "dss_data11", "sdi_data1p", NULL, "gpio_129", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA12, 130, + "dss_data12", "sdi_data2n", NULL, "gpio_130", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA13, 131, + "dss_data13", "sdi_data2p", NULL, "gpio_131", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA14, 132, + "dss_data14", "sdi_data3n", NULL, "gpio_132", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA15, 133, + "dss_data15", "sdi_data3p", NULL, "gpio_133", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA16, 46, + "dss_data16", NULL, NULL, "gpio_46", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA17, 47, + "dss_data17", NULL, NULL, "gpio_47", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA1, 41, + "dss_data1", "uart1_rts", NULL, "gpio_41", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA2, 42, + "dss_data2", "uart1_tx", NULL, "gpio_42", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA3, 43, + "dss_data3", "uart1_rx", NULL, "gpio_43", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA4, 44, + "dss_data4", "uart3_rx_irrx", NULL, "gpio_44", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA5, 45, + "dss_data5", "uart3_tx_irtx", NULL, "gpio_45", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA6, 144, + "dss_data6", NULL, NULL, "gpio_144", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA7, 147, + "dss_data7", NULL, NULL, "gpio_147", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA8, 38, + "dss_data8", NULL, NULL, "gpio_38", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA9, 39, + "dss_data9", NULL, NULL, "gpio_39", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_HSYNC, 110, + "dss_hsync", NULL, NULL, "gpio_110", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_113, 113, + "gpio_113", "mcbsp2_clkx", NULL, "gpio_113", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_114, 114, + "gpio_114", "mcbsp2_fsx", NULL, "gpio_114", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_115, 115, + "gpio_115", "mcbsp2_dr", NULL, "gpio_115", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_116, 116, + "gpio_116", "mcbsp2_dx", NULL, "gpio_116", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_128, 128, + "gpio_128", NULL, "sti_din", "gpio_128", + NULL, "sys_boot0", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_129, 129, + "gpio_129", NULL, "sti_dout", "gpio_129", + NULL, "sys_boot1", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_130, 130, + "gpio_130", NULL, NULL, "gpio_130", + "jtag_emu2", "sys_boot2", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_131, 131, + "gpio_131", NULL, NULL, "gpio_131", + "jtag_emu3", "sys_boot3", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_132, 132, + "gpio_132", NULL, NULL, "gpio_132", + NULL, "sys_boot4", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_133, 133, + "gpio_133", NULL, NULL, "gpio_133", + NULL, "sys_boot5", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_134, 134, + "gpio_134", "ccp_datn", NULL, "gpio_134", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_135, 135, + "gpio_135", "ccp_datp", NULL, "gpio_135", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_136, 136, + "gpio_136", "ccp_clkn", NULL, "gpio_136", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_137, 137, + "gpio_137", "ccp_clkp", NULL, "gpio_137", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_138, 138, + "gpio_138", "spi3_clk", NULL, "gpio_138", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_139, 139, + "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_140, 140, + "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140", + NULL, NULL, "etk_d14", "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_141, 141, + "gpio_141", "spi3_somi", NULL, "gpio_141", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_142, 142, + "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142", + NULL, NULL, "etk_d15", "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_148, 148, + "gpio_148", "mcbsp5_fsx", NULL, "gpio_148", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_149, 149, + "gpio_149", "mcbsp5_dx", NULL, "gpio_149", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_150, 150, + "gpio_150", "mcbsp5_dr", NULL, "gpio_150", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_151, 151, + "gpio_151", "sys_pwrok", NULL, "gpio_151", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_152, 152, + "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_153, 153, + "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_154, 154, + "gpio_154", "mcbsp5_clkx", NULL, "gpio_154", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_63, 63, + "gpio_63", "mcbsp4_clkx", NULL, "gpio_63", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_78, 78, + "gpio_78", NULL, "uart2_rts", "gpio_78", + "uart3_rts_sd", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_79, 79, + "gpio_79", "secure_indicator", "uart2_tx", "gpio_79", + "uart3_tx_irtx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_7, 7, + "gpio_7", NULL, "uart2_cts", "gpio_7", + "uart3_cts_rctx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_80, 80, + "gpio_80", NULL, "uart2_rx", "gpio_80", + "uart3_rx_irrx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A10, 3, + "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A1, 31, + "gpmc_a1", NULL, NULL, "gpio_31", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A2, 30, + "gpmc_a2", NULL, NULL, "gpio_30", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A3, 29, + "gpmc_a3", NULL, NULL, "gpio_29", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A4, 49, + "gpmc_a4", NULL, NULL, "gpio_49", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A5, 53, + "gpmc_a5", NULL, NULL, "gpio_53", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A6, 52, + "gpmc_a6", NULL, NULL, "gpio_52", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A7, 6, + "gpmc_a7", NULL, NULL, "gpio_6", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A8, 5, + "gpmc_a8", NULL, NULL, "gpio_5", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A9, 4, + "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_CLK, 21, + "gpmc_clk", NULL, NULL, "gpio_21", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D10, 18, + "gpmc_d10", NULL, NULL, "gpio_18", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D11, 57, + "gpmc_d11", NULL, NULL, "gpio_57", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D12, 77, + "gpmc_d12", NULL, NULL, "gpio_77", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D13, 76, + "gpmc_d13", NULL, NULL, "gpio_76", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D14, 55, + "gpmc_d14", NULL, NULL, "gpio_55", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D15, 54, + "gpmc_d15", NULL, NULL, "gpio_54", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D8, 20, + "gpmc_d8", NULL, NULL, "gpio_20", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D9, 19, + "gpmc_d9", NULL, NULL, "gpio_19", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS1, 22, + "gpmc_ncs1", NULL, NULL, "gpio_22", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS2, 23, + "gpmc_ncs2", NULL, NULL, "gpio_23", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS3, 24, + "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS4, 25, + "gpmc_ncs4", NULL, NULL, "gpio_25", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS5, 26, + "gpmc_ncs5", NULL, NULL, "gpio_26", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS6, 27, + "gpmc_ncs6", NULL, NULL, "gpio_27", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS7, 28, + "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_WAIT1, 33, + "gpmc_wait1", NULL, NULL, "gpio_33", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_WAIT2, 34, + "gpmc_wait2", NULL, NULL, "gpio_34", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_WAIT3, 35, + "gpmc_wait3", NULL, NULL, "gpio_35", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(HDQ_SIO, 101, + "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", + "uart3_rx_irrx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C1_SCL, 50, + "i2c1_scl", NULL, NULL, "gpio_50", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C1_SDA, 51, + "i2c1_sda", NULL, NULL, "gpio_51", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C2_SCL, 99, + "i2c2_scl", NULL, NULL, "gpio_99", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C2_SDA, 100, + "i2c2_sda", NULL, NULL, "gpio_100", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(JTAG_EMU0, 127, + "jtag_emu0", "secure_indicator", NULL, "gpio_127", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(JTAG_EMU1, 126, + "jtag_emu1", NULL, NULL, "gpio_126", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92, + "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98, + "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_DR, 95, + "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_DX, 94, + "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_FSR, 93, + "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93", + "spi2_cs1", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_FSX, 97, + "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147, + "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP2_DR, 144, + "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71, + "mcbsp3_clkx", NULL, NULL, "gpio_71", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_DR, 73, + "mcbsp3_dr", NULL, NULL, "gpio_73", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_DX, 74, + "mcbsp3_dx", NULL, "sti_clk", "gpio_74", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_FSX, 72, + "mcbsp3_fsx", NULL, NULL, "gpio_72", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP_CLKS, 96, + "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0, + "sdmmc1_clko", "ms_clko", NULL, NULL, + NULL, "hw_dbg9", "hw_dbg3", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_CMD, 0, + "sdmmc1_cmd", "ms_bs", NULL, NULL, + NULL, "hw_dbg8", "hw_dbg2", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0, + "sdmmc1_dat0", "ms_dat0", NULL, NULL, + NULL, "hw_dbg7", "hw_dbg1", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75, + "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75", + NULL, "hw_dbg6", "hw_dbg0", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0, + "sdmmc1_dat2", "ms_dat2", NULL, NULL, + NULL, "hw_dbg5", "hw_dbg10", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0, + "sdmmc1_dat3", "ms_dat3", NULL, NULL, + NULL, "hw_dbg4", "hw_dbg11", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13, + "sdmmc2_clko", NULL, NULL, "gpio_13", + NULL, "spi3_clk", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_CMD, 15, + "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15", + NULL, "spi3_simo", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16, + "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16", + NULL, "spi3_somi", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58, + "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17, + "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17", + NULL, "spi3_cs1", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14, + "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14", + NULL, "spi3_cs0", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_A12, 2, + "sdrc_a12", NULL, NULL, "gpio_2", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_A13, 1, + "sdrc_a13", NULL, NULL, "gpio_1", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_A14, 0, + "sdrc_a14", NULL, NULL, "gpio_0", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_CKE1, 36, + "sdrc_cke1", NULL, NULL, "gpio_36", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_NCS1, 37, + "sdrc_ncs1", NULL, NULL, "gpio_37", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CLK, 81, + "spi1_clk", NULL, NULL, "gpio_81", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS0, 84, + "spi1_cs0", NULL, NULL, "gpio_84", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS1, 85, + "spi1_cs1", NULL, NULL, "gpio_85", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS2, 86, + "spi1_cs2", NULL, NULL, "gpio_86", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS3, 87, + "spi1_cs3", "spi2_cs1", NULL, "gpio_87", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_SIMO, 82, + "spi1_simo", NULL, NULL, "gpio_82", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_SOMI, 83, + "spi1_somi", NULL, NULL, "gpio_83", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_CLK, 88, + "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_CS0, 91, + "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_SIMO, 89, + "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_SOMI, 90, + "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62, + "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59, + "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64, + "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60, + "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65, + "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61, + "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_WAKE, 66, + "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_CLKOUT, 111, + "sys_clkout", NULL, NULL, "gpio_111", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118, + "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_NIRQ0, 56, + "sys_nirq0", NULL, NULL, "gpio_56", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_NIRQ1, 125, + "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_CTS, 32, + "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32", + "mcbsp5_clkx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_RTS, 8, + "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8", + "mcbsp5_fsx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_RX, 10, + "uart1_rx", "sdi_stp", "dss_data21", "gpio_10", + "mcbsp5_dr", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_TX, 9, + "uart1_tx", "sdi_den", "dss_data20", "gpio_9", + "mcbsp5_dx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_CTS, 67, + "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_RTS, 68, + "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_RX, 70, + "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_TX, 69, + "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102, + "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_RTS_SD, 103, + "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105, + "uart3_rx_irrx", NULL, NULL, "gpio_105", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104, + "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_CLK, 120, + "usb0hs_clk", NULL, NULL, "gpio_120", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA0, 0, + "usb0hs_data0", "uart3_tx_irtx", NULL, NULL, + "usb0_txen", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA1, 0, + "usb0hs_data1", "uart3_rx_irrx", NULL, NULL, + "usb0_dat", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA2, 0, + "usb0hs_data2", "uart3_rts_sd", NULL, NULL, + "usb0_se0", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA3, 106, + "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106", + "usb0_puen", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA4, 107, + "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107", + "usb0_vp", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA5, 108, + "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108", + "usb0_vm", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA6, 109, + "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109", + "usb0_rcv", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA7, 124, + "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DIR, 121, + "usb0hs_dir", NULL, NULL, "gpio_121", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_NXT, 123, + "usb0hs_nxt", NULL, NULL, "gpio_123", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_STP, 122, + "usb0hs_stp", NULL, NULL, "gpio_122", + NULL, NULL, NULL, "safe_mode"), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for POP package + * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) + */ +#ifdef CONFIG_DEBUG_FS +struct omap_ball __initdata omap2430_pop_ball[] = { + _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), + _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), + _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), + _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL), + _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL), + _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL), + _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL), + _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL), + _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL), + _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL), + _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL), + _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL), + _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL), + _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL), + _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL), + _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL), + _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL), + _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL), + _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL), + _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL), + _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL), + _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL), + _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL), + _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL), + _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL), + _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL), + _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL), + _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL), + _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL), + _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL), + _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL), + _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL), + _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL), + _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL), + _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL), + _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL), + _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL), + _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL), + _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL), + _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL), + _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL), + _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL), + _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL), + _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL), + _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL), + _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL), + _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL), + _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL), + _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL), + _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL), + _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL), + _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL), + _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL), + _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL), + _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL), + _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL), + _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL), + _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL), + _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL), + _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL), + _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL), + _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL), + _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL), + _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL), + _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL), + _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL), + _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL), + _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL), + _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL), + _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL), + _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL), + _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL), + _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL), + _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"), + _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"), + _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"), + _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"), + _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"), + _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"), + _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"), + _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"), + _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"), + _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"), + _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL), + _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"), + _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL), + _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL), + _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL), + _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL), + _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL), + _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL), + _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL), + _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL), + _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL), + _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL), + _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL), + _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL), + _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL), + _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL), + _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL), + _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL), + _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL), + _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL), + _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL), + _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL), + _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL), + _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL), + _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL), + _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL), + _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL), + _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL), + _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"), + _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"), + _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"), + _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"), + _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"), + _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL), + _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL), + _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL), + _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL), + _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL), + _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL), + _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL), + _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL), + _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL), + _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL), + _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL), + _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL), + _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL), + _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL), + _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL), + _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL), + _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL), + _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL), + _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL), + _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL), + _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL), + _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL), + _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL), + _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL), + _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL), + _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL), + _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL), + _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL), + _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL), + _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL), + _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL), + _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL), + _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL), + _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL), + _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL), + _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL), + _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL), + _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap2430_pop_ball NULL +#endif + +int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) +{ + struct omap_ball *package_balls = NULL; + + switch (flags & OMAP_PACKAGE_MASK) { + case OMAP_PACKAGE_ZAC: + package_balls = omap2430_pop_ball; + break; + default: + pr_warning("mux: No ball data available for omap2420 package\n"); + } + + return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, + OMAP2430_CONTROL_PADCONF_MUX_SIZE, + omap2430_muxmodes, NULL, board_subset, + package_balls); +} diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h new file mode 100644 index 00000000000..adbea0d03e0 --- /dev/null +++ b/arch/arm/mach-omap2/mux2430.h @@ -0,0 +1,370 @@ +/* + * Copyright (C) 2009 Nokia + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU + +#define OMAP2430_MUX(mode0, mux_value) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \ + .value = (mux_value), \ +} + +/* + * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing + * + * Extracted from the TRM. Add 0x49002030 to these values to get the + * absolute addresses. The name in the macro is the mode-0 name of + * the pin. NOTE: These registers are 8-bits wide. + * + * Note that these defines use SDMMC instead of MMC for compability + * with signal names used in 3630. + */ +#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008 +#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009 +#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a +#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b +#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c +#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d +#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010 +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011 +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012 +#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016 +#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017 +#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018 +#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a +#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b +#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c +#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d +#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e +#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020 +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021 +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022 +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023 +#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024 +#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025 +#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026 +#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027 +#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028 +#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029 +#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a +#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b +#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c +#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d +#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e +#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f +#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030 +#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031 +#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032 +#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033 +#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034 +#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035 +#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036 +#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037 +#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 +#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039 +#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a +#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b +#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c +#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d +#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e +#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f +#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040 +#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041 +#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042 +#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043 +#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044 +#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045 +#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046 +#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047 +#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048 +#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049 +#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a +#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b +#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c +#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d +#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e +#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f +#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050 +#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051 +#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052 +#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053 +#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054 +#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055 +#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056 +#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057 +#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058 +#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059 +#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a +#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b +#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c +#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d +#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e +#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f +#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060 +#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061 +#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062 +#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063 +#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064 +#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065 +#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066 +#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067 +#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068 +#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069 +#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a +#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b +#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c +#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d +#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e +#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f +#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a +#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b +#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c +#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d +#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e +#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f +#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080 +#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081 +#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082 +#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083 +#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084 +#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085 +#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086 +#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087 +#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088 +#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089 +#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a +#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b +#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c +#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d +#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e +#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f +#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090 +#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091 +#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092 +#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093 +#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094 +#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095 +#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096 +#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097 +#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098 +#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099 +#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a +#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b +#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c +#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d +#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e +#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f +#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0 +#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1 +#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2 +#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3 +#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4 +#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5 +#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6 +#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7 +#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8 +#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9 +#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa +#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab +#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac +#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad +#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae +#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af +#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0 +#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1 +#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2 +#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3 +#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4 +#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5 +#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6 +#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7 +#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8 +#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9 +#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba +#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb +#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc +#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd +#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be +#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf +#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0 +#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1 +#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8 +#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9 +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca +#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce +#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf +#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0 +#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1 +#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6 +#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7 +#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8 +#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9 +#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da +#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db +#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc +#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd +#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de +#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df +#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0 +#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5 +#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6 +#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7 +#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8 +#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9 +#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea +#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb +#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec +#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed +#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee +#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef +#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0 +#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1 +#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2 +#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3 +#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4 +#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5 +#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6 +#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7 +#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8 +#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9 +#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa +#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb +#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc +#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd +#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe +#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff +#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100 +#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101 +#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109 +#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a +#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b +#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c +#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e +#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f +#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110 +#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111 +#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112 +#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139 +#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a +#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b +#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c +#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d +#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e +#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f +#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140 +#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a +#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b +#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c +#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d +#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e +#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f +#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150 +#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151 +#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152 +#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153 + +#define OMAP2430_CONTROL_PADCONF_MUX_SIZE \ + (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 2ff4dce95ee..f64d7eea345 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -2032,19 +2032,19 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) struct omap_ball *package_balls; switch (flags & OMAP_PACKAGE_MASK) { - case (OMAP_PACKAGE_CBC): + case OMAP_PACKAGE_CBC: package_subset = omap3_cbc_subset; package_balls = omap3_cbc_ball; break; - case (OMAP_PACKAGE_CBB): + case OMAP_PACKAGE_CBB: package_subset = omap3_cbb_subset; package_balls = omap3_cbb_ball; break; - case (OMAP_PACKAGE_CUS): + case OMAP_PACKAGE_CUS: package_subset = omap3_cus_subset; package_balls = omap3_cus_ball; break; - case (OMAP_PACKAGE_CBP): + case OMAP_PACKAGE_CBP: package_subset = omap36xx_cbp_subset; package_balls = omap36xx_cbp_ball; break; diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index ef0e7a00dd6..6ae937a06cc 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -47,19 +47,3 @@ hold: ldr r12,=0x103 b secondary_startup END(omap_secondary_startup) - -ENTRY(omap_modify_auxcoreboot0) - stmfd sp!, {r1-r12, lr} - ldr r12, =0x104 - dsb - smc #0 - ldmfd sp!, {r1-r12, pc} -END(omap_modify_auxcoreboot0) - -ENTRY(omap_auxcoreboot_addr) - stmfd sp!, {r2-r12, lr} - ldr r12, =0x105 - dsb - smc #0 - ldmfd sp!, {r2-r12, pc} -END(omap_auxcoreboot_addr) diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c new file mode 100644 index 00000000000..6cee456ca54 --- /dev/null +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -0,0 +1,79 @@ +/* + * OMAP4 SMP cpu-hotplug support + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Platform file needed for the OMAP4 SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2002 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <linux/completion.h> + +#include <asm/cacheflush.h> +#include <mach/omap4-common.h> + +static DECLARE_COMPLETION(cpu_killed); + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + pr_crit("platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } + pr_notice("CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + flush_cache_all(); + dsb(); + + /* + * we're ready for shutdown now, so do it + */ + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) + printk(KERN_CRIT "Secure clear status failed\n"); + + for (;;) { + /* + * Execute WFI + */ + do_wfi(); + + if (omap_read_auxcoreboot0() == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + pr_debug("CPU%u: spurious wakeup call\n", cpu); + } +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index eb9bee73e0c..f5a1aad1a5c 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -59,7 +59,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; static struct iommu_device omap4_devices[] = { { .base = OMAP4_MMU1_BASE, - .irq = INT_44XX_DUCATI_MMU_IRQ, + .irq = OMAP44XX_IRQ_DUCATI_MMU, .pdata = { .name = "ducati", .nr_tlb_entries = 32, diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 1cf52313759..9e9f70e18e3 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -73,9 +73,10 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ - omap_modify_auxcoreboot0(0x200, 0x0); + omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); + smp_cross_call(cpumask_of(cpu)); /* * Now the secondary core is starting up let it run its @@ -101,8 +102,7 @@ static void __init wakeup_secondary(void) * Send a 'sev' to wake the secondary core from WFE. * Drain the outstanding writes to memory */ - dsb(); - set_event(); + dsb_sev(); mb(); } diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S index f61c7771ca4..1980dc31a1a 100644 --- a/arch/arm/mach-omap2/omap44xx-smc.S +++ b/arch/arm/mach-omap2/omap44xx-smc.S @@ -30,3 +30,28 @@ ENTRY(omap_smc1) smc #0 ldmfd sp!, {r2-r12, pc} END(omap_smc1) + +ENTRY(omap_modify_auxcoreboot0) + stmfd sp!, {r1-r12, lr} + ldr r12, =0x104 + dsb + smc #0 + ldmfd sp!, {r1-r12, pc} +END(omap_modify_auxcoreboot0) + +ENTRY(omap_auxcoreboot_addr) + stmfd sp!, {r2-r12, lr} + ldr r12, =0x105 + dsb + smc #0 + ldmfd sp!, {r2-r12, pc} +END(omap_auxcoreboot_addr) + +ENTRY(omap_read_auxcoreboot0) + stmfd sp!, {r2-r12, lr} + ldr r12, =0x103 + dsb + smc #0 + mov r0, r0, lsr #9 + ldmfd sp!, {r2-r12, pc} +END(omap_read_auxcoreboot0) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index b7a4133267d..cb911d7d1a3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1,7 +1,7 @@ /* * omap_hwmod implementation for OMAP2/3/4 * - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley, Benoît Cousson, Kevin Hilman * @@ -423,7 +423,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clk - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk * for the the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -764,6 +764,7 @@ static struct omap_hwmod *_lookup(const char *name) /** * _init_clocks - clk_get() all clocks associated with this hwmod * @oh: struct omap_hwmod * + * @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Must be called @@ -771,7 +772,7 @@ static struct omap_hwmod *_lookup(const char *name) * has not yet been registered or if the clocks have already been * initialized, 0 on success, or a non-zero error on failure. */ -static int _init_clocks(struct omap_hwmod *oh) +static int _init_clocks(struct omap_hwmod *oh, void *data) { int ret = 0; @@ -886,7 +887,7 @@ static int _reset(struct omap_hwmod *oh) } /** - * _enable - enable an omap_hwmod + * _omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's @@ -894,7 +895,7 @@ static int _reset(struct omap_hwmod *oh) * Returns -EINVAL if the hwmod is in the wrong state or passes along * the return value of _wait_target_ready(). */ -static int _enable(struct omap_hwmod *oh) +int _omap_hwmod_enable(struct omap_hwmod *oh) { int r; @@ -939,7 +940,7 @@ static int _enable(struct omap_hwmod *oh) * no further work. Returns -EINVAL if the hwmod is in the wrong * state or returns 0. */ -static int _idle(struct omap_hwmod *oh) +int _omap_hwmod_idle(struct omap_hwmod *oh) { if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from " @@ -996,19 +997,25 @@ static int _shutdown(struct omap_hwmod *oh) /** * _setup - do initial configuration of omap_hwmod * @oh: struct omap_hwmod * + * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex - * held. Returns -EINVAL if the hwmod is in the wrong state or returns - * 0. + * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. + * @skip_setup_idle is intended to be used on a system that will not + * call omap_hwmod_enable() to enable devices (e.g., a system without + * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or + * returns 0. */ -static int _setup(struct omap_hwmod *oh) +static int _setup(struct omap_hwmod *oh, void *data) { int i, r; + u8 skip_setup_idle; - if (!oh) + if (!oh || !data) return -EINVAL; + skip_setup_idle = *(u8 *)data; + /* Set iclk autoidle mode */ if (oh->slaves_cnt > 0) { for (i = 0; i < oh->slaves_cnt; i++) { @@ -1029,7 +1036,7 @@ static int _setup(struct omap_hwmod *oh) oh->_state = _HWMOD_STATE_INITIALIZED; - r = _enable(oh); + r = _omap_hwmod_enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", oh->name, oh->_state); @@ -1041,7 +1048,7 @@ static int _setup(struct omap_hwmod *oh) * XXX Do the OCP_SYSCONFIG bits need to be * reprogrammed after a reset? If not, then this can * be removed. If they do, then probably the - * _enable() function should be split to avoid the + * _omap_hwmod_enable() function should be split to avoid the * rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { @@ -1050,8 +1057,8 @@ static int _setup(struct omap_hwmod *oh) } } - if (!(oh->flags & HWMOD_INIT_NO_IDLE)) - _idle(oh); + if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) + _omap_hwmod_idle(oh); return 0; } @@ -1062,14 +1069,29 @@ static int _setup(struct omap_hwmod *oh) u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) { - return __raw_readl(oh->_rt_va + reg_offs); + return __raw_readl(oh->_mpu_rt_va + reg_offs); } void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) { - __raw_writel(v, oh->_rt_va + reg_offs); + __raw_writel(v, oh->_mpu_rt_va + reg_offs); } +/** + * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode + * @oh: struct omap_hwmod * + * @idlemode: SIDLEMODE field bits (shifted to bit 0) + * + * Sets the IP block's OCP slave idlemode in hardware, and updates our + * local copy. Intended to be used by drivers that have some erratum + * that requires direct manipulation of the SIDLEMODE bits. Returns + * -EINVAL if @oh is null, or passes along the return value from + * _set_slave_idlemode(). + * + * XXX Does this function have any current users? If not, we should + * remove it; it is better to let the rest of the hwmod code handle this. + * Any users of this function should be scrutinized carefully. + */ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) { u32 v; @@ -1124,7 +1146,7 @@ int omap_hwmod_register(struct omap_hwmod *oh) ms_id = _find_mpu_port_index(oh); if (!IS_ERR_VALUE(ms_id)) { oh->_mpu_port_index = ms_id; - oh->_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); + oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); } else { oh->_int_flags |= _HWMOD_NO_MPU_PORT; } @@ -1164,6 +1186,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) /** * omap_hwmod_for_each - call function for each registered omap_hwmod * @fn: pointer to a callback function + * @data: void * data to pass to callback function * * Call @fn for each registered omap_hwmod, passing @data to each * function. @fn must return 0 for success or any other value for @@ -1172,7 +1195,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) * caller of omap_hwmod_for_each(). @fn is called with * omap_hwmod_for_each() held. */ -int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), + void *data) { struct omap_hwmod *temp_oh; int ret; @@ -1182,7 +1206,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) mutex_lock(&omap_hwmod_mutex); list_for_each_entry(temp_oh, &omap_hwmod_list, node) { - ret = (*fn)(temp_oh); + ret = (*fn)(temp_oh, data); if (ret) break; } @@ -1229,24 +1253,28 @@ int omap_hwmod_init(struct omap_hwmod **ohs) /** * omap_hwmod_late_init - do some post-clock framework initialization + * @skip_setup_idle: if 1, do not idle hwmods in _setup() * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -int omap_hwmod_late_init(void) +int omap_hwmod_late_init(u8 skip_setup_idle) { int r; /* XXX check return value */ - r = omap_hwmod_for_each(_init_clocks); + r = omap_hwmod_for_each(_init_clocks, NULL); WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", MPU_INITIATOR_NAME); - omap_hwmod_for_each(_setup); + if (skip_setup_idle) + pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); + + omap_hwmod_for_each(_setup, &skip_setup_idle); return 0; } @@ -1270,7 +1298,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: unregistering\n", oh->name); mutex_lock(&omap_hwmod_mutex); - iounmap(oh->_rt_va); + iounmap(oh->_mpu_rt_va); list_del(&oh->node); mutex_unlock(&omap_hwmod_mutex); @@ -1292,12 +1320,13 @@ int omap_hwmod_enable(struct omap_hwmod *oh) return -EINVAL; mutex_lock(&omap_hwmod_mutex); - r = _enable(oh); + r = _omap_hwmod_enable(oh); mutex_unlock(&omap_hwmod_mutex); return r; } + /** * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * @@ -1311,7 +1340,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) return -EINVAL; mutex_lock(&omap_hwmod_mutex); - _idle(oh); + _omap_hwmod_idle(oh); mutex_unlock(&omap_hwmod_mutex); return 0; @@ -1413,7 +1442,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh) mutex_lock(&omap_hwmod_mutex); r = _reset(oh); if (!r) - r = _enable(oh); + r = _omap_hwmod_enable(oh); mutex_unlock(&omap_hwmod_mutex); return r; @@ -1530,6 +1559,29 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) } /** + * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) + * @oh: struct omap_hwmod * + * + * Returns the virtual address corresponding to the beginning of the + * module's register target, in the address range that is intended to + * be used by the MPU. Returns the virtual address upon success or NULL + * upon error. + */ +void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) +{ + if (!oh) + return NULL; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return NULL; + + if (oh->_state == _HWMOD_STATE_UNKNOWN) + return NULL; + + return oh->_mpu_rt_va; +} + +/** * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh * @oh: struct omap_hwmod * * @init_oh: struct omap_hwmod * (initiator) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index e5530c51f77..3cc768e8bc0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -30,42 +30,44 @@ */ static struct omap_hwmod omap2420_mpu_hwmod; -static struct omap_hwmod omap2420_l3_hwmod; +static struct omap_hwmod omap2420_iva_hwmod; +static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; /* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2420_l3__l4_core = { - .master = &omap2420_l3_hwmod, +static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { + .master = &omap2420_l3_main_hwmod, .slave = &omap2420_l4_core_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2420_mpu__l3 = { +static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { .master = &omap2420_mpu_hwmod, - .slave = &omap2420_l3_hwmod, + .slave = &omap2420_l3_main_hwmod, .user = OCP_USER_MPU, }; /* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = { - &omap2420_mpu__l3, +static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { + &omap2420_mpu__l3_main, }; /* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = { - &omap2420_l3__l4_core, +static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { + &omap2420_l3_main__l4_core, }; /* L3 */ -static struct omap_hwmod omap2420_l3_hwmod = { - .name = "l3_hwmod", +static struct omap_hwmod omap2420_l3_main_hwmod = { + .name = "l3_main", .class = &l3_hwmod_class, - .masters = omap2420_l3_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), - .slaves = omap2420_l3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + .masters = omap2420_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), + .slaves = omap2420_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, }; static struct omap_hwmod omap2420_l4_wkup_hwmod; @@ -79,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { - &omap2420_l3__l4_core, + &omap2420_l3_main__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ @@ -89,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { /* L4 CORE */ static struct omap_hwmod omap2420_l4_core_hwmod = { - .name = "l4_core_hwmod", + .name = "l4_core", .class = &l4_hwmod_class, .masters = omap2420_l4_core_masters, .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), .slaves = omap2420_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_WKUP interconnect */ @@ -109,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { /* L4 WKUP */ static struct omap_hwmod omap2420_l4_wkup_hwmod = { - .name = "l4_wkup_hwmod", + .name = "l4_wkup", .class = &l4_hwmod_class, .masters = omap2420_l4_wkup_masters, .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), .slaves = omap2420_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, }; /* Master interfaces on the MPU device */ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { - &omap2420_mpu__l3, + &omap2420_mpu__l3_main, }; /* MPU */ @@ -133,11 +137,40 @@ static struct omap_hwmod omap2420_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* + * IVA1 interface data + */ + +/* IVA <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__iva = { + .master = &omap2420_l3_main_hwmod, + .slave = &omap2420_iva_hwmod, + .clk = "iva1_ifck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { + &omap2420_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap2420_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap2420_iva_masters, + .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { - &omap2420_l3_hwmod, + &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, + &omap2420_iva_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0852d954da4..4526628ed28 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -30,47 +30,47 @@ */ static struct omap_hwmod omap2430_mpu_hwmod; -static struct omap_hwmod omap2430_l3_hwmod; +static struct omap_hwmod omap2430_iva_hwmod; +static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; /* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2430_l3__l4_core = { - .master = &omap2430_l3_hwmod, +static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { + .master = &omap2430_l3_main_hwmod, .slave = &omap2430_l4_core_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2430_mpu__l3 = { +static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { .master = &omap2430_mpu_hwmod, - .slave = &omap2430_l3_hwmod, + .slave = &omap2430_l3_main_hwmod, .user = OCP_USER_MPU, }; /* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = { - &omap2430_mpu__l3, +static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { + &omap2430_mpu__l3_main, }; /* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = { - &omap2430_l3__l4_core, +static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { + &omap2430_l3_main__l4_core, }; /* L3 */ -static struct omap_hwmod omap2430_l3_hwmod = { - .name = "l3_hwmod", +static struct omap_hwmod omap2430_l3_main_hwmod = { + .name = "l3_main", .class = &l3_hwmod_class, - .masters = omap2430_l3_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), - .slaves = omap2430_l3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + .masters = omap2430_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), + .slaves = omap2430_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, }; static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_mmc1_hwmod; -static struct omap_hwmod omap2430_mmc2_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -81,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { - &omap2430_l3__l4_core, + &omap2430_l3_main__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ @@ -91,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { /* L4 CORE */ static struct omap_hwmod omap2430_l4_core_hwmod = { - .name = "l4_core_hwmod", + .name = "l4_core", .class = &l4_hwmod_class, .masters = omap2430_l4_core_masters, .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), .slaves = omap2430_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_WKUP interconnect */ @@ -111,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { /* L4 WKUP */ static struct omap_hwmod omap2430_l4_wkup_hwmod = { - .name = "l4_wkup_hwmod", + .name = "l4_wkup", .class = &l4_hwmod_class, .masters = omap2430_l4_wkup_masters, .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), .slaves = omap2430_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, }; /* Master interfaces on the MPU device */ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { - &omap2430_mpu__l3, + &omap2430_mpu__l3_main, }; /* MPU */ @@ -135,11 +137,40 @@ static struct omap_hwmod omap2430_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* + * IVA2_1 interface data + */ + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2430_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "dsp_fck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { + &omap2430_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap2430_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap2430_iva_masters, + .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { - &omap2430_l3_hwmod, + &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, + &omap2430_iva_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 39b0c0eaa37..5d8eb58ba5e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -32,51 +32,53 @@ */ static struct omap_hwmod omap3xxx_mpu_hwmod; -static struct omap_hwmod omap3xxx_l3_hwmod; +static struct omap_hwmod omap3xxx_iva_hwmod; +static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; /* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = { - .master = &omap3xxx_l3_hwmod, +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_l4_core_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* L3 -> L4_PER interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = { - .master = &omap3xxx_l3_hwmod, +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { + .master = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_l4_per_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = { +static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_hwmod, + .slave = &omap3xxx_l3_main_hwmod, .user = OCP_USER_MPU, }; /* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = { - &omap3xxx_mpu__l3, +static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { + &omap3xxx_mpu__l3_main, }; /* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = { - &omap3xxx_l3__l4_core, - &omap3xxx_l3__l4_per, +static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { + &omap3xxx_l3_main__l4_core, + &omap3xxx_l3_main__l4_per, }; /* L3 */ -static struct omap_hwmod omap3xxx_l3_hwmod = { - .name = "l3_hwmod", +static struct omap_hwmod omap3xxx_l3_main_hwmod = { + .name = "l3_main", .class = &l3_hwmod_class, - .masters = omap3xxx_l3_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters), - .slaves = omap3xxx_l3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .masters = omap3xxx_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), + .slaves = omap3xxx_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; @@ -90,7 +92,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { - &omap3xxx_l3__l4_core, + &omap3xxx_l3_main__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ @@ -100,18 +102,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { /* L4 CORE */ static struct omap_hwmod omap3xxx_l4_core_hwmod = { - .name = "l4_core_hwmod", + .name = "l4_core", .class = &l4_hwmod_class, .masters = omap3xxx_l4_core_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), .slaves = omap3xxx_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { - &omap3xxx_l3__l4_per, + &omap3xxx_l3_main__l4_per, }; /* Master interfaces on the L4_PER interconnect */ @@ -120,13 +123,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { /* L4 PER */ static struct omap_hwmod omap3xxx_l4_per_hwmod = { - .name = "l4_per_hwmod", + .name = "l4_per", .class = &l4_hwmod_class, .masters = omap3xxx_l4_per_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), .slaves = omap3xxx_l4_per_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_WKUP interconnect */ @@ -140,18 +144,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { /* L4 WKUP */ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { - .name = "l4_wkup_hwmod", + .name = "l4_wkup", .class = &l4_hwmod_class, .masters = omap3xxx_l4_wkup_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), .slaves = omap3xxx_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; /* Master interfaces on the MPU device */ static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { - &omap3xxx_mpu__l3, + &omap3xxx_mpu__l3_main, }; /* MPU */ @@ -164,12 +169,41 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; +/* + * IVA2_2 interface data + */ + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_iva_hwmod, + .clk = "iva2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { + &omap3xxx_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap3xxx_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap3xxx_iva_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { - &omap3xxx_l3_hwmod, + &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, + &omap3xxx_iva_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 1e80b914fa1..08a134243ec 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -66,3 +66,6 @@ struct omap_hwmod_class mpu_hwmod_class = { .name = "mpu" }; +struct omap_hwmod_class iva_hwmod_class = { + .name = "iva" +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 3645a28c7c2..c34e98bf124 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -20,5 +20,6 @@ extern struct omap_hwmod_class l3_hwmod_class; extern struct omap_hwmod_class l4_hwmod_class; extern struct omap_hwmod_class mpu_hwmod_class; +extern struct omap_hwmod_class iva_hwmod_class; #endif diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c new file mode 100644 index 00000000000..68f9f2e9589 --- /dev/null +++ b/arch/arm/mach-omap2/pm.c @@ -0,0 +1,84 @@ +/* + * pm.c - Common OMAP2+ power management-related code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/err.h> + +#include <plat/omap-pm.h> +#include <plat/omap_device.h> +#include <plat/common.h> + +static struct omap_device_pm_latency *pm_lats; + +static struct device *mpu_dev; +static struct device *dsp_dev; +static struct device *l3_dev; + +struct device *omap2_get_mpuss_device(void) +{ + WARN_ON_ONCE(!mpu_dev); + return mpu_dev; +} + +struct device *omap2_get_dsp_device(void) +{ + WARN_ON_ONCE(!dsp_dev); + return dsp_dev; +} + +struct device *omap2_get_l3_device(void) +{ + WARN_ON_ONCE(!l3_dev); + return l3_dev; +} + +/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ +static int _init_omap_device(char *name, struct device **new_dev) +{ + struct omap_hwmod *oh; + struct omap_device *od; + + oh = omap_hwmod_lookup(name); + if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", + __func__, name)) + return -ENODEV; + + od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); + if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n", + __func__, name)) + return -ENODEV; + + *new_dev = &od->pdev.dev; + + return 0; +} + +/* + * Build omap_devices for processors and bus. + */ +static void omap2_init_processor_devices(void) +{ + _init_omap_device("mpu", &mpu_dev); + _init_omap_device("iva", &dsp_dev); + _init_omap_device("l3_main", &l3_dev); +} + +static int __init omap2_common_pm_init(void) +{ + omap2_init_processor_devices(); + omap_pm_if_init(); + + return 0; +} +device_initcall(omap2_common_pm_init); + diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index e321281ab6e..6aeedeacdad 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -39,7 +39,6 @@ #include <plat/clock.h> #include <plat/sram.h> #include <plat/control.h> -#include <plat/mux.h> #include <plat/dma.h> #include <plat/board.h> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index b88737fd6cf..7b03426c72a 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -385,8 +385,9 @@ void omap_sram_idle(void) /* Enable IO-PAD and IO-CHAIN wakeups */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); - if (per_next_state < PWRDM_POWER_ON || - core_next_state < PWRDM_POWER_ON) { + if (omap3_has_io_wakeup() && \ + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -479,7 +480,9 @@ void omap_sram_idle(void) } /* Disable IO-PAD and IO-CHAIN wakeup */ - if (core_next_state < PWRDM_POWER_ON) { + if (omap3_has_io_wakeup() && + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_disable_io_chain(); } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c new file mode 100644 index 00000000000..54544b4fc76 --- /dev/null +++ b/arch/arm/mach-omap2/pm44xx.c @@ -0,0 +1,135 @@ +/* + * OMAP4 Power Management Routines + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/pm.h> +#include <linux/suspend.h> +#include <linux/module.h> +#include <linux/list.h> +#include <linux/err.h> +#include <linux/slab.h> + +#include <plat/powerdomain.h> +#include <mach/omap4-common.h> + +struct power_state { + struct powerdomain *pwrdm; + u32 next_state; +#ifdef CONFIG_SUSPEND + u32 saved_state; +#endif + struct list_head node; +}; + +static LIST_HEAD(pwrst_list); + +#ifdef CONFIG_SUSPEND +static int omap4_pm_prepare(void) +{ + disable_hlt(); + return 0; +} + +static int omap4_pm_suspend(void) +{ + do_wfi(); + return 0; +} + +static int omap4_pm_enter(suspend_state_t suspend_state) +{ + int ret = 0; + + switch (suspend_state) { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + ret = omap4_pm_suspend(); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static void omap4_pm_finish(void) +{ + enable_hlt(); + return; +} + +static int omap4_pm_begin(suspend_state_t state) +{ + return 0; +} + +static void omap4_pm_end(void) +{ + return; +} + +static struct platform_suspend_ops omap_pm_ops = { + .begin = omap4_pm_begin, + .end = omap4_pm_end, + .prepare = omap4_pm_prepare, + .enter = omap4_pm_enter, + .finish = omap4_pm_finish, + .valid = suspend_valid_only_mem, +}; +#endif /* CONFIG_SUSPEND */ + +static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) +{ + struct power_state *pwrst; + + if (!pwrdm->pwrsts) + return 0; + + pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); + if (!pwrst) + return -ENOMEM; + pwrst->pwrdm = pwrdm; + pwrst->next_state = PWRDM_POWER_ON; + list_add(&pwrst->node, &pwrst_list); + + return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state); +} + +/** + * omap4_pm_init - Init routine for OMAP4 PM + * + * Initializes all powerdomain and clockdomain target states + * and all PRCM settings. + */ +static int __init omap4_pm_init(void) +{ + int ret; + + if (!cpu_is_omap44xx()) + return -ENODEV; + + pr_err("Power Management for TI OMAP4.\n"); + +#ifdef CONFIG_PM + ret = pwrdm_for_each(pwrdms_setup, NULL); + if (ret) { + pr_err("Failed to setup powerdomains\n"); + goto err2; + } +#endif + +#ifdef CONFIG_SUSPEND + suspend_set_ops(&omap_pm_ops); +#endif /* CONFIG_SUSPEND */ + +err2: + return ret; +} +late_initcall(omap4_pm_init); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index a2904aa7065..6527ec30dc1 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -875,6 +875,7 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) break; case 4: m = OMAP_MEM4_RETSTATE_MASK; + break; default: WARN_ON(1); /* should never happen */ return -EEXIST; diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index bd87112beea..fa904861668 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = { }, }; +/* + * The USBTLL Save-and-Restore mechanism is broken on + * 3430s upto ES3.0 and 3630ES1.0. Hence this feature + * needs to be disabled on these chips. + * Refer: 3430 errata ID i459 and 3630 errata ID i579 + */ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0), + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3630ES1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, @@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { static struct powerdomain core_3xxx_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | + CHIP_GE_OMAP3630ES1_1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 3771254dfa8..566e991ede8 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -37,6 +37,9 @@ #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ +#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) +#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) + /* * NOTE: By default the serial timeout is disabled as it causes lost characters * over the serial ports. This means that the UART clocks will stay on until @@ -64,6 +67,7 @@ struct omap_uart_state { struct list_head node; struct platform_device pdev; + u32 errata; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) int context_valid; @@ -74,6 +78,7 @@ struct omap_uart_state { u16 sysc; u16 scr; u16 wer; + u16 mcr; #endif }; @@ -180,6 +185,42 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) +/* + * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) + * The access to uart register after MDR1 Access + * causes UART to corrupt data. + * + * Need a delay = + * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) + * give 10 times as much + */ +static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, + u8 fcr_val) +{ + struct plat_serial8250_port *p = uart->p; + u8 timeout = 255; + + serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); + udelay(2); + serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | + UART_FCR_CLEAR_RCVR); + /* + * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and + * TX_FIFO_E bit is 1. + */ + while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & + (UART_LSR_THRE | UART_LSR_DR))) { + timeout--; + if (!timeout) { + /* Should *never* happen. we warn and carry on */ + dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", + serial_read_reg(p, UART_LSR)); + break; + } + udelay(1); + } +} + static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; @@ -197,6 +238,9 @@ static void omap_uart_save_context(struct omap_uart_state *uart) uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); uart->scr = serial_read_reg(p, UART_OMAP_SCR); uart->wer = serial_read_reg(p, UART_OMAP_WER); + serial_write_reg(p, UART_LCR, 0x80); + uart->mcr = serial_read_reg(p, UART_MCR); + serial_write_reg(p, UART_LCR, lcr); uart->context_valid = 1; } @@ -214,7 +258,10 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; - serial_write_reg(p, UART_OMAP_MDR1, 0x7); + if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) + omap_uart_mdr1_errataset(uart, 0x07, 0xA0); + else + serial_write_reg(p, UART_OMAP_MDR1, 0x7); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ efr = serial_read_reg(p, UART_EFR); serial_write_reg(p, UART_EFR, UART_EFR_ECB); @@ -225,14 +272,18 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(p, UART_DLM, uart->dlh); serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_FCR, 0xA1); + serial_write_reg(p, UART_LCR, 0x80); + serial_write_reg(p, UART_MCR, uart->mcr); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ serial_write_reg(p, UART_EFR, efr); serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); serial_write_reg(p, UART_OMAP_SCR, uart->scr); serial_write_reg(p, UART_OMAP_WER, uart->wer); serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) + omap_uart_mdr1_errataset(uart, 0x00, 0xA1); + else + serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -489,8 +540,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) } uart->wk_mask = wk_mask; } else { - uart->wk_en = 0; - uart->wk_st = 0; + uart->wk_en = NULL; + uart->wk_st = NULL; uart->wk_mask = 0; uart->padconf = 0; } @@ -552,7 +603,8 @@ static ssize_t sleep_timeout_store(struct device *dev, return n; } -DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); +static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, + sleep_timeout_store); #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} @@ -749,14 +801,20 @@ void __init omap_serial_init_port(int port) * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ - if (cpu_is_omap44xx()) { - uart->p->serial_in = serial_in_override; - uart->p->serial_out = serial_out_override; - } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { + if (cpu_is_omap44xx()) + uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; + else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) + >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) + uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; + + if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { uart->p->serial_in = serial_in_override; uart->p->serial_out = serial_out_override; } + + /* Enable the MDR1 errata for OMAP3 */ + if (cpu_is_omap34xx()) + uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; } /** diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index d72d1ac3033..b11bf385d36 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c @@ -23,7 +23,6 @@ #include <linux/dma-mapping.h> #include <asm/io.h> -#include <plat/mux.h> #include <mach/hardware.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c new file mode 100644 index 00000000000..a216d88b04b --- /dev/null +++ b/arch/arm/mach-omap2/usb-fs.c @@ -0,0 +1,359 @@ +/* + * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx + * + * Copyright (C) 2004 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/irq.h> + +#include <plat/control.h> +#include <plat/usb.h> +#include <plat/board.h> + +#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN +#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO +#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO +#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN +#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG + +#include "mux.h" + +#if defined(CONFIG_ARCH_OMAP2) + +#ifdef CONFIG_USB_GADGET_OMAP + +static struct resource udc_resources[] = { + /* order is significant! */ + { /* registers */ + .start = UDC_BASE, + .end = UDC_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { /* general IRQ */ + .start = INT_USB_IRQ_GEN, + .flags = IORESOURCE_IRQ, + }, { /* PIO IRQ */ + .start = INT_USB_IRQ_NISO, + .flags = IORESOURCE_IRQ, + }, { /* SOF IRQ */ + .start = INT_USB_IRQ_ISO, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 udc_dmamask = ~(u32)0; + +static struct platform_device udc_device = { + .name = "omap_udc", + .id = -1, + .dev = { + .dma_mask = &udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(udc_resources), + .resource = udc_resources, +}; + +static inline void udc_device_init(struct omap_usb_config *pdata) +{ + pdata->udc_device = &udc_device; +} + +#else + +static inline void udc_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = ~(u32)0; + +static struct resource ohci_resources[] = { + { + .start = OMAP_OHCI_BASE, + .end = OMAP_OHCI_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_IRQ_HGEN, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci_device = { + .name = "ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(ohci_resources), + .resource = ohci_resources, +}; + +static inline void ohci_device_init(struct omap_usb_config *pdata) +{ + pdata->ohci_device = &ohci_device; +} + +#else + +static inline void ohci_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) + +static struct resource otg_resources[] = { + /* order is significant! */ + { + .start = OTG_BASE, + .end = OTG_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = INT_USB_IRQ_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device otg_device = { + .name = "omap_otg", + .id = -1, + .num_resources = ARRAY_SIZE(otg_resources), + .resource = otg_resources, +}; + +static inline void otg_device_init(struct omap_usb_config *pdata) +{ + pdata->otg_device = &otg_device; +} + +#else + +static inline void otg_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +static void omap2_usb_devconf_clear(u8 port, u32 mask) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r &= ~USBTXWRMODEI(port, mask); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb_devconf_set(u8 port, u32 mask) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r |= USBTXWRMODEI(port, mask); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb2_disable_5pinbitll(void) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb2_enable_5pinunitll(void) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device) +{ + u32 syscon1 = 0; + + omap2_usb_devconf_clear(0, USB_BIDIR_TLL); + + if (nwires == 0) + return 0; + + if (is_device) + omap_mux_init_signal("usb0_puen", 0); + + omap_mux_init_signal("usb0_dat", 0); + omap_mux_init_signal("usb0_txen", 0); + omap_mux_init_signal("usb0_se0", 0); + if (nwires != 3) + omap_mux_init_signal("usb0_rcv", 0); + + switch (nwires) { + case 3: + syscon1 = 2; + omap2_usb_devconf_set(0, USB_BIDIR); + break; + case 4: + syscon1 = 1; + omap2_usb_devconf_set(0, USB_BIDIR); + break; + case 6: + syscon1 = 3; + omap_mux_init_signal("usb0_vp", 0); + omap_mux_init_signal("usb0_vm", 0); + omap2_usb_devconf_set(0, USB_UNIDIR); + break; + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 0, nwires); + } + + return syscon1 << 16; +} + +static u32 __init omap2_usb1_init(unsigned nwires) +{ + u32 syscon1 = 0; + + omap2_usb_devconf_clear(1, USB_BIDIR_TLL); + + if (nwires == 0) + return 0; + + /* NOTE: board-specific code must set up pin muxing for usb1, + * since each signal could come out on either of two balls. + */ + + switch (nwires) { + case 2: + /* NOTE: board-specific code must override this setting if + * this TLL link is not using DP/DM + */ + syscon1 = 1; + omap2_usb_devconf_set(1, USB_BIDIR_TLL); + break; + case 3: + syscon1 = 2; + omap2_usb_devconf_set(1, USB_BIDIR); + break; + case 4: + syscon1 = 1; + omap2_usb_devconf_set(1, USB_BIDIR); + break; + case 6: + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 1, nwires); + } + + return syscon1 << 20; +} + +static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup) +{ + u32 syscon1 = 0; + + omap2_usb2_disable_5pinbitll(); + alt_pingroup = 0; + + /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ + if (alt_pingroup || nwires == 0) + return 0; + + omap_mux_init_signal("usb2_dat", 0); + omap_mux_init_signal("usb2_se0", 0); + if (nwires > 2) + omap_mux_init_signal("usb2_txen", 0); + if (nwires > 3) + omap_mux_init_signal("usb2_rcv", 0); + + switch (nwires) { + case 2: + /* NOTE: board-specific code must override this setting if + * this TLL link is not using DP/DM + */ + syscon1 = 1; + omap2_usb_devconf_set(2, USB_BIDIR_TLL); + break; + case 3: + syscon1 = 2; + omap2_usb_devconf_set(2, USB_BIDIR); + break; + case 4: + syscon1 = 1; + omap2_usb_devconf_set(2, USB_BIDIR); + break; + case 5: + /* NOTE: board-specific code must mux this setting depending + * on TLL link using DP/DM. Something must also + * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} + * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0 + * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0 + */ + + syscon1 = 3; + omap2_usb2_enable_5pinunitll(); + break; + case 6: + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 2, nwires); + } + + return syscon1 << 24; +} + +void __init omap2_usbfs_init(struct omap_usb_config *pdata) +{ + struct clk *ick; + + if (!cpu_is_omap24xx()) + return; + + ick = clk_get(NULL, "usb_l4_ick"); + if (IS_ERR(ick)) + return; + + clk_enable(ick); + pdata->usb0_init = omap2_usb0_init; + pdata->usb1_init = omap2_usb1_init; + pdata->usb2_init = omap2_usb2_init; + udc_device_init(pdata); + ohci_device_init(pdata); + otg_device_init(pdata); + omap_otg_init(pdata); + clk_disable(ick); + clk_put(ick); +} + +#endif diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 96f6787e00b..33a5cde1c22 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -28,7 +28,6 @@ #include <mach/hardware.h> #include <mach/irqs.h> -#include <plat/mux.h> #include <plat/usb.h> #ifdef CONFIG_USB_MUSB_SOC diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 10a2013c110..64a0112b70a 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -17,8 +17,8 @@ #include <linux/usb/musb.h> #include <plat/gpmc.h> -#include <plat/mux.h> +#include "mux.h" static u8 async_cs, sync_cs; static unsigned refclk_psec; @@ -325,17 +325,17 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, else { /* assume OMAP 2420 ES2.0 and later */ if (dmachan & (1 << 0)) - omap_cfg_reg(AA10_242X_DMAREQ0); + omap_mux_init_signal("sys_ndmareq0", 0); if (dmachan & (1 << 1)) - omap_cfg_reg(AA6_242X_DMAREQ1); + omap_mux_init_signal("sys_ndmareq1", 0); if (dmachan & (1 << 2)) - omap_cfg_reg(E4_242X_DMAREQ2); + omap_mux_init_signal("sys_ndmareq2", 0); if (dmachan & (1 << 3)) - omap_cfg_reg(G4_242X_DMAREQ3); + omap_mux_init_signal("sys_ndmareq3", 0); if (dmachan & (1 << 4)) - omap_cfg_reg(D3_242X_DMAREQ4); + omap_mux_init_signal("sys_ndmareq4", 0); if (dmachan & (1 << 5)) - omap_cfg_reg(E3_242X_DMAREQ5); + omap_mux_init_signal("sys_ndmareq5", 0); } /* so far so good ... register the device */ diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 5041d1bc26b..696b1a97f9e 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -216,6 +216,7 @@ static struct mtd_partition ts78xx_ts_nand_parts[] = { static struct platform_nand_data ts78xx_ts_nand_data = { .chip = { + .nr_chips = 1, .part_probe_types = ts_nand_part_probes, .partitions = ts78xx_ts_nand_parts, .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts), diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 3b51741a481..7aefb907485 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -238,6 +238,17 @@ config MACH_COLIBRI bool "Toradex Colibri PXA270" select PXA27x +config MACH_COLIBRI_PXA270_EVALBOARD + bool "Toradex Colibri Evaluation Carrier Board support (PXA270)" + depends on MACH_COLIBRI + +config MACH_COLIBRI_PXA270_INCOME + bool "Income s.r.o. PXA270 SBC" + depends on MACH_COLIBRI + select PXA27x + select HAVE_PWM + select PXA_HAVE_BOARD_IRQS + config MACH_COLIBRI300 bool "Toradex Colibri PXA300/310" select PXA3xx @@ -336,6 +347,9 @@ config ARCH_PXA_PALM bool "PXA based Palm PDAs" select HAVE_PWM +config MACH_PALM27X + bool + config MACH_PALMTE2 bool "Palm Tungsten|E2" default y @@ -360,6 +374,7 @@ config MACH_PALMT5 depends on ARCH_PXA_PALM select PXA27x select IWMMXT + select MACH_PALM27X help Say Y here if you intend to run this kernel on a Palm Tungsten|T5 handheld computer. @@ -370,6 +385,7 @@ config MACH_PALMTX depends on ARCH_PXA_PALM select PXA27x select IWMMXT + select MACH_PALM27X help Say Y here if you intend to run this kernel on a Palm T|X handheld computer. @@ -380,6 +396,7 @@ config MACH_PALMZ72 depends on ARCH_PXA_PALM select PXA27x select IWMMXT + select MACH_PALM27X help Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. @@ -390,6 +407,7 @@ config MACH_PALMLD depends on ARCH_PXA_PALM select PXA27x select IWMMXT + select MACH_PALM27X help Say Y here if you intend to run this kernel on a Palm LifeDrive handheld computer. @@ -447,16 +465,13 @@ config PXA_SHARPSL SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) handheld computer. -config SHARPSL_PM - bool - select APM_EMULATION - select SHARPSL_PM_MAX1111 - -config SHARPSL_PM_MAX1111 - bool - depends on !CORGI_SSP_DEPRECATED - select HWMON - select SENSORS_MAX1111 +config PXA_SHARPSL_DETECT_MACH_ID + bool "Detect machine ID at run-time in the decompressor" + depends on PXA_SHARPSL + help + Say Y here if you want the zImage decompressor to detect + the Zaurus machine ID at run-time. For latest kexec-based + boot loader, this is not necessary. config MACH_POODLE bool "Enable Sharp SL-5600 (Poodle) Support" @@ -510,6 +525,25 @@ config MACH_TOSA select PXA25x select PXA_HAVE_BOARD_IRQS +config TOSA_BT + tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" + depends on MACH_TOSA + select RFKILL + help + This is a simple driver that is able to control + the state of built in bluetooth chip on tosa. + +config TOSA_USE_EXT_KEYCODES + bool "Tosa keyboard: use extended keycodes" + depends on MACH_TOSA + default n + help + Say Y here to enable the tosa keyboard driver to generate extended + (>= 127) keycodes. Be aware, that they can't be correctly interpreted + by either console keyboard driver or by Kdrive keybd driver. + + Say Y only if you know, what you are doing! + config MACH_ICONTROL bool "TMT iControl/SafeTCam based on the MXM-8x10 CoM" select CPU_PXA320 @@ -648,25 +682,15 @@ config PXA_SHARP_Cxx00 help Enable common support for Sharp Cxx00 models -config TOSA_BT - tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" - depends on MACH_TOSA - select RFKILL - help - This is a simple driver that is able to control - the state of built in bluetooth chip on tosa. - -config TOSA_USE_EXT_KEYCODES - bool "Tosa keyboard: use extended keycodes" - depends on MACH_TOSA - default n - help - Say Y here to enable the tosa keyboard driver to generate extended - (>= 127) keycodes. Be aware, that they can't be correctly interpreted - by either console keyboard driver or by Kdrive keybd driver. - - Say Y only if you know, what you are doing! +config SHARPSL_PM + bool + select APM_EMULATION + select SHARPSL_PM_MAX1111 +config SHARPSL_PM_MAX1111 + bool + select HWMON + select SENSORS_MAX1111 config PXA_HAVE_BOARD_IRQS bool diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index b8f1f4bc7ca..85c7fb324db 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -51,14 +51,16 @@ obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o -obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o +obj-$(CONFIG_MACH_INTELMOTE2) += stargate2.o obj-$(CONFIG_MACH_STARGATE2) += stargate2.o obj-$(CONFIG_MACH_XCEP) += xcep.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_PCM027) += pcm027.o obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o -obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o +obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o +obj-$(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) += colibri-pxa270-evalboard.o +obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o obj-$(CONFIG_MACH_VPAC270) += vpac270.o @@ -73,6 +75,7 @@ obj-$(CONFIG_PXA_EZX) += ezx.o obj-$(CONFIG_MACH_MP900C) += mp900.o obj-$(CONFIG_MACH_PALMTE2) += palmte2.o obj-$(CONFIG_MACH_PALMTC) += palmtc.o +obj-$(CONFIG_MACH_PALM27X) += palm27x.o obj-$(CONFIG_MACH_PALMT5) += palmt5.o obj-$(CONFIG_MACH_PALMTX) += palmtx.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o @@ -84,12 +87,6 @@ obj-$(CONFIG_MACH_POODLE) += poodle.o obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o -obj-$(CONFIG_MACH_E330) += e330.o -obj-$(CONFIG_MACH_E350) += e350.o -obj-$(CONFIG_MACH_E740) += e740.o -obj-$(CONFIG_MACH_E750) += e750.o -obj-$(CONFIG_MACH_E400) += e400.o -obj-$(CONFIG_MACH_E800) += e800.o obj-$(CONFIG_MACH_RAUMFELD_RC) += raumfeld.o obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index f3b5ace815e..9041340fee1 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -22,9 +22,14 @@ #include <linux/fb.h> #include <linux/gpio.h> #include <linux/ioport.h> +#include <linux/ucb1400.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/types.h> +#include <linux/i2c/pcf857x.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/physmap.h> +#include <linux/regulator/max1586.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -51,6 +56,59 @@ #include "generic.h" #include "devices.h" +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static unsigned long balloon3_pin_config[] __initdata = { + /* Select BTUART 'COM1/ttyS0' as IO option for pins 42/43/44/45 */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + GPIO45_BTUART_RTS, + + /* Reset, configured as GPIO wakeup source */ + GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, + + /* LEDs */ + GPIO9_GPIO, /* NAND activity LED */ + GPIO10_GPIO, /* Heartbeat LED */ + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO113_AC97_nRESET, + GPIO95_GPIO, + + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + + /* USB Host */ + GPIO88_USBH1_PWR, + GPIO89_USBH1_PEN, + + /* PC Card */ + GPIO48_nPOE, + GPIO49_nPWE, + GPIO50_nPIOR, + GPIO51_nPIOW, + GPIO85_nPCE_1, + GPIO54_nPCE_2, + GPIO79_PSKTSEL, + GPIO55_nPREG, + GPIO56_nPWAIT, + GPIO57_nIOIS16, +}; + +/****************************************************************************** + * Compatibility: Parameter parsing + ******************************************************************************/ static unsigned long balloon3_irq_enabled; static unsigned long balloon3_features_present = @@ -73,6 +131,321 @@ int __init parse_balloon3_features(char *arg) } early_param("balloon3_features", parse_balloon3_features); +/****************************************************************************** + * NOR Flash + ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition balloon3_nor_partitions[] = { + { + .name = "Flash", + .offset = 0x00000000, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data balloon3_flash_data[] = { + { + .width = 2, /* bankwidth in bytes */ + .parts = balloon3_nor_partitions, + .nr_parts = ARRAY_SIZE(balloon3_nor_partitions) + } +}; + +static struct resource balloon3_flash_resource = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device balloon3_flash = { + .name = "physmap-flash", + .id = 0, + .resource = &balloon3_flash_resource, + .num_resources = 1, + .dev = { + .platform_data = balloon3_flash_data, + }, +}; +static void __init balloon3_nor_init(void) +{ + platform_device_register(&balloon3_flash); +} +#else +static inline void balloon3_nor_init(void) {} +#endif + +/****************************************************************************** + * Audio and Touchscreen + ******************************************************************************/ +#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \ + defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) +static struct ucb1400_pdata vpac270_ucb1400_pdata = { + .irq = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ), +}; + + +static struct platform_device balloon3_ucb1400_device = { + .name = "ucb1400_core", + .id = -1, + .dev = { + .platform_data = &vpac270_ucb1400_pdata, + }, +}; + +static void __init balloon3_ts_init(void) +{ + if (!balloon3_has(BALLOON3_FEATURE_AUDIO)) + return; + + pxa_set_ac97_info(NULL); + platform_device_register(&balloon3_ucb1400_device); +} +#else +static inline void balloon3_ts_init(void) {} +#endif + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +static struct pxafb_mode_info balloon3_lcd_modes[] = { + { + .pixclock = 38000, + .xres = 480, + .yres = 640, + .bpp = 16, + .hsync_len = 8, + .left_margin = 8, + .right_margin = 8, + .vsync_len = 2, + .upper_margin = 4, + .lower_margin = 5, + .sync = 0, + }, +}; + +static struct pxafb_mach_info balloon3_lcd_screen = { + .modes = balloon3_lcd_modes, + .num_modes = ARRAY_SIZE(balloon3_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +static void balloon3_backlight_power(int on) +{ + gpio_set_value(BALLOON3_GPIO_RUN_BACKLIGHT, on); +} + +static void __init balloon3_lcd_init(void) +{ + int ret; + + if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY)) + return; + + ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON"); + if (ret) { + pr_err("Requesting BKL-ON GPIO failed!\n"); + goto err; + } + + ret = gpio_direction_output(BALLOON3_GPIO_RUN_BACKLIGHT, 1); + if (ret) { + pr_err("Setting BKL-ON GPIO direction failed!\n"); + goto err2; + } + + balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power; + set_pxa_fb_info(&balloon3_lcd_screen); + return; + +err2: + gpio_free(BALLOON3_GPIO_RUN_BACKLIGHT); +err: + return; +} +#else +static inline void balloon3_lcd_init(void) {} +#endif + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +static struct pxamci_platform_data balloon3_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, + .detect_delay_ms = 200, +}; + +static void __init balloon3_mmc_init(void) +{ + pxa_set_mci_info(&balloon3_mci_platform_data); +} +#else +static inline void balloon3_mmc_init(void) {} +#endif + +/****************************************************************************** + * USB Gadget + ******************************************************************************/ +#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) +static void balloon3_udc_command(int cmd) +{ + if (cmd == PXA2XX_UDC_CMD_CONNECT) + UP2OCR |= UP2OCR_DPPUE | UP2OCR_DPPUBE; + else if (cmd == PXA2XX_UDC_CMD_DISCONNECT) + UP2OCR &= ~UP2OCR_DPPUE; +} + +static int balloon3_udc_is_connected(void) +{ + return 1; +} + +static struct pxa2xx_udc_mach_info balloon3_udc_info __initdata = { + .udc_command = balloon3_udc_command, + .udc_is_connected = balloon3_udc_is_connected, + .gpio_pullup = -1, +}; + +static void __init balloon3_udc_init(void) +{ + pxa_set_udc_info(&balloon3_udc_info); + platform_device_register(&balloon3_gpio_vbus); +} +#else +static inline void balloon3_udc_init(void) {} +#endif + +/****************************************************************************** + * IrDA + ******************************************************************************/ +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) +static struct pxaficp_platform_data balloon3_ficp_platform_data = { + .transceiver_cap = IR_FIRMODE | IR_SIRMODE | IR_OFF, +}; + +static void __init balloon3_irda_init(void) +{ + pxa_set_ficp_info(&balloon3_ficp_platform_data); +} +#else +static inline void balloon3_irda_init(void) {} +#endif + +/****************************************************************************** + * USB Host + ******************************************************************************/ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static struct pxaohci_platform_data balloon3_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, +}; + +static void __init balloon3_uhc_init(void) +{ + if (!balloon3_has(BALLOON3_FEATURE_OHCI)) + return; + pxa_set_ohci_info(&balloon3_ohci_info); +} +#else +static inline void balloon3_uhc_init(void) {} +#endif + +/****************************************************************************** + * LEDs + ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +struct gpio_led balloon3_gpio_leds[] = { + { + .name = "balloon3:green:idle", + .default_trigger = "heartbeat", + .gpio = BALLOON3_GPIO_LED_IDLE, + .active_low = 1, + }, { + .name = "balloon3:green:nand", + .default_trigger = "nand-disk", + .gpio = BALLOON3_GPIO_LED_NAND, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data balloon3_gpio_led_info = { + .leds = balloon3_gpio_leds, + .num_leds = ARRAY_SIZE(balloon3_gpio_leds), +}; + +static struct platform_device balloon3_leds = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &balloon3_gpio_led_info, + } +}; + +struct gpio_led balloon3_pcf_gpio_leds[] = { + { + .name = "balloon3:green:led0", + .gpio = BALLOON3_PCF_GPIO_LED0, + .active_low = 1, + }, { + .name = "balloon3:green:led1", + .gpio = BALLOON3_PCF_GPIO_LED1, + .active_low = 1, + }, { + .name = "balloon3:orange:led2", + .gpio = BALLOON3_PCF_GPIO_LED2, + .active_low = 1, + }, { + .name = "balloon3:orange:led3", + .gpio = BALLOON3_PCF_GPIO_LED3, + .active_low = 1, + }, { + .name = "balloon3:orange:led4", + .gpio = BALLOON3_PCF_GPIO_LED4, + .active_low = 1, + }, { + .name = "balloon3:orange:led5", + .gpio = BALLOON3_PCF_GPIO_LED5, + .active_low = 1, + }, { + .name = "balloon3:red:led6", + .gpio = BALLOON3_PCF_GPIO_LED6, + .active_low = 1, + }, { + .name = "balloon3:red:led7", + .gpio = BALLOON3_PCF_GPIO_LED7, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data balloon3_pcf_gpio_led_info = { + .leds = balloon3_pcf_gpio_leds, + .num_leds = ARRAY_SIZE(balloon3_pcf_gpio_leds), +}; + +static struct platform_device balloon3_pcf_leds = { + .name = "leds-gpio", + .id = 1, + .dev = { + .platform_data = &balloon3_pcf_gpio_led_info, + } +}; + +static void __init balloon3_leds_init(void) +{ + platform_device_register(&balloon3_leds); + platform_device_register(&balloon3_pcf_leds); +} +#else +static inline void balloon3_leds_init(void) {} +#endif + +/****************************************************************************** + * FPGA IRQ + ******************************************************************************/ static void balloon3_mask_irq(unsigned int irq) { int balloon3_irq = (irq - BALLOON3_IRQ(0)); @@ -98,7 +471,6 @@ static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) & balloon3_irq_enabled; - do { /* clear useless edge notification */ if (desc->chip->ack) @@ -132,201 +504,259 @@ static void __init balloon3_init_irq(void) "enabled\n", __func__, BALLOON3_AUX_NIRQ); } -static unsigned long balloon3_ac97_pin_config[] = { - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, - GPIO113_AC97_nRESET, -}; - -static void balloon3_backlight_power(int on) -{ - pr_debug("%s: power is %s\n", __func__, on ? "on" : "off"); - gpio_set_value(BALLOON3_GPIO_RUN_BACKLIGHT, on); -} - -static unsigned long balloon3_lcd_pin_config[] = { - /* LCD - 16bpp Active TFT */ - GPIOxx_LCD_TFT_16BPP, - - GPIO99_GPIO, /* Backlight */ +/****************************************************************************** + * GPIO expander + ******************************************************************************/ +#if defined(CONFIG_GPIO_PCF857X) || defined(CONFIG_GPIO_PCF857X_MODULE) +static struct pcf857x_platform_data balloon3_pcf857x_pdata = { + .gpio_base = BALLOON3_PCF_GPIO_BASE, + .n_latch = 0, + .setup = NULL, + .teardown = NULL, + .context = NULL, }; -static struct pxafb_mode_info balloon3_lcd_modes[] = { +static struct i2c_board_info __initdata balloon3_i2c_devs[] = { { - .pixclock = 38000, - .xres = 480, - .yres = 640, - .bpp = 16, - .hsync_len = 8, - .left_margin = 8, - .right_margin = 8, - .vsync_len = 2, - .upper_margin = 4, - .lower_margin = 5, - .sync = 0, + I2C_BOARD_INFO("pcf8574a", 0x38), + .platform_data = &balloon3_pcf857x_pdata, }, }; -static struct pxafb_mach_info balloon3_pxafb_info = { - .modes = balloon3_lcd_modes, - .num_modes = ARRAY_SIZE(balloon3_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, - .pxafb_backlight_power = balloon3_backlight_power, -}; +static void __init balloon3_i2c_init(void) +{ + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(balloon3_i2c_devs)); +} +#else +static inline void balloon3_i2c_init(void) {} +#endif + +/****************************************************************************** + * NAND + ******************************************************************************/ +#if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE) +static uint16_t balloon3_ctl = + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | + BALLOON3_NAND_CONTROL_FLWP; + +static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; -static unsigned long balloon3_mmc_pin_config[] = { - GPIO32_MMC_CLK, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - GPIO112_MMC_CMD, -}; + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) + balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE; + else + balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE; -static void balloon3_mci_setpower(struct device *dev, unsigned int vdd) -{ - struct pxamci_platform_data *p_d = dev->platform_data; - - if ((1 << vdd) & p_d->ocr_mask) { - pr_debug("%s: on\n", __func__); - /* FIXME something to prod here? */ - } else { - pr_debug("%s: off\n", __func__); - /* FIXME something to prod here? */ + if (ctrl & NAND_ALE) + balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE; + else + balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE; + + __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } -static struct pxamci_platform_data balloon3_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .setpower = balloon3_mci_setpower, -}; +static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip) +{ + if (chip < 0 || chip > 3) + return; -static int balloon3_udc_is_connected(void) + balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 | + BALLOON3_NAND_CONTROL_FLCE1 | + BALLOON3_NAND_CONTROL_FLCE2 | + BALLOON3_NAND_CONTROL_FLCE3; + + /* Deassert correct nCE line */ + balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip); + + __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); +} + +static int balloon3_nand_probe(struct platform_device *pdev) { - pr_debug("%s: udc connected\n", __func__); - return 1; + void __iomem *temp_map; + uint16_t ver; + int ret; + + __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG); + + ver = __raw_readw(BALLOON3_FPGA_VER); + if (ver > 0x0201) + pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. " + "NAND support might be broken in this version!", ver); + + /* Power up the NAND chips */ + ret = gpio_request(BALLOON3_GPIO_RUN_NAND, "NAND"); + if (ret) + goto err1; + + ret = gpio_direction_output(BALLOON3_GPIO_RUN_NAND, 1); + if (ret) + goto err2; + + gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1); + + /* Deassert all nCE lines and write protect line */ + __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); + return 0; + +err2: + gpio_free(BALLOON3_GPIO_RUN_NAND); +err1: + return ret; } -static void balloon3_udc_command(int cmd) +static void balloon3_nand_remove(struct platform_device *pdev) { - switch (cmd) { - case PXA2XX_UDC_CMD_CONNECT: - UP2OCR |= (UP2OCR_DPPUE + UP2OCR_DPPUBE); - pr_debug("%s: connect\n", __func__); - break; - case PXA2XX_UDC_CMD_DISCONNECT: - UP2OCR &= ~UP2OCR_DPPUE; - pr_debug("%s: disconnect\n", __func__); - break; - } + /* Power down the NAND chips */ + gpio_set_value(BALLOON3_GPIO_RUN_NAND, 0); + gpio_free(BALLOON3_GPIO_RUN_NAND); } -static struct pxa2xx_udc_mach_info balloon3_udc_info = { - .udc_is_connected = balloon3_udc_is_connected, - .udc_command = balloon3_udc_command, +static struct mtd_partition balloon3_partition_info[] = { + [0] = { + .name = "Boot", + .offset = 0, + .size = SZ_4M, + }, + [1] = { + .name = "RootFS", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, }; -static struct pxaficp_platform_data balloon3_ficp_platform_data = { - .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, -}; +static const char *balloon3_part_probes[] = { "cmdlinepart", NULL }; -static unsigned long balloon3_ohci_pin_config[] = { - GPIO88_USBH1_PWR, - GPIO89_USBH1_PEN, +struct platform_nand_data balloon3_nand_pdata = { + .chip = { + .nr_chips = 4, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(balloon3_partition_info), + .partitions = balloon3_partition_info, + .chip_delay = 50, + .part_probe_types = balloon3_part_probes, + }, + .ctrl = { + .hwcontrol = 0, + .dev_ready = 0, + .select_chip = balloon3_nand_select_chip, + .cmd_ctrl = balloon3_nand_cmd_ctl, + .probe = balloon3_nand_probe, + .remove = balloon3_nand_remove, + }, }; -static struct pxaohci_platform_data balloon3_ohci_platform_data = { - .port_mode = PMM_PERPORT_MODE, - .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, +static struct resource balloon3_nand_resource[] = { + [0] = { + .start = BALLOON3_NAND_BASE, + .end = BALLOON3_NAND_BASE + 0x4, + .flags = IORESOURCE_MEM, + }, }; -static unsigned long balloon3_pin_config[] __initdata = { - /* Select BTUART 'COM1/ttyS0' as IO option for pins 42/43/44/45 */ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - GPIO45_BTUART_RTS, - - /* Wakeup GPIO */ - GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, - - /* NAND & IDLE LED GPIOs */ - GPIO9_GPIO, - GPIO10_GPIO, +static struct platform_device balloon3_nand = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(balloon3_nand_resource), + .resource = balloon3_nand_resource, + .id = -1, + .dev = { + .platform_data = &balloon3_nand_pdata, + } }; -static struct gpio_led balloon3_gpio_leds[] = { +static void __init balloon3_nand_init(void) +{ + platform_device_register(&balloon3_nand); +} +#else +static inline void balloon3_nand_init(void) {} +#endif + +/****************************************************************************** + * Core power regulator + ******************************************************************************/ +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +static struct regulator_consumer_supply balloon3_max1587a_consumers[] = { { - .name = "balloon3:green:idle", - .default_trigger = "heartbeat", - .gpio = BALLOON3_GPIO_LED_IDLE, - .active_low = 1, + .supply = "vcc_core", + } +}; + +static struct regulator_init_data balloon3_max1587a_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 900000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, }, + .consumer_supplies = balloon3_max1587a_consumers, + .num_consumer_supplies = ARRAY_SIZE(balloon3_max1587a_consumers), +}; + +static struct max1586_subdev_data balloon3_max1587a_subdevs[] = { { - .name = "balloon3:green:nand", - .default_trigger = "nand-disk", - .gpio = BALLOON3_GPIO_LED_NAND, - .active_low = 1, - }, + .name = "vcc_core", + .id = MAX1586_V3, + .platform_data = &balloon3_max1587a_v3_info, + } }; -static struct gpio_led_platform_data balloon3_gpio_leds_platform_data = { - .leds = balloon3_gpio_leds, - .num_leds = ARRAY_SIZE(balloon3_gpio_leds), +static struct max1586_platform_data balloon3_max1587a_info = { + .subdevs = balloon3_max1587a_subdevs, + .num_subdevs = ARRAY_SIZE(balloon3_max1587a_subdevs), + .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */ }; -static struct platform_device balloon3led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &balloon3_gpio_leds_platform_data, +static struct i2c_board_info __initdata balloon3_pi2c_board_info[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &balloon3_max1587a_info, }, }; -static void __init balloon3_init(void) +static void __init balloon3_pmic_init(void) { - pr_info("Initialising Balloon3\n"); + pxa27x_set_i2c_power_info(NULL); + i2c_register_board_info(1, ARRAY_AND_SIZE(balloon3_pi2c_board_info)); +} +#else +static inline void balloon3_pmic_init(void) {} +#endif - /* system bus arbiter setting - * - Core_Park - * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 - */ +/****************************************************************************** + * Machine init + ******************************************************************************/ +static void __init balloon3_init(void) +{ ARB_CNTRL = ARB_CORE_PARK | 0x234; + pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_pin_config)); + pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - pxa_set_i2c_info(NULL); - if (balloon3_has(BALLOON3_FEATURE_AUDIO)) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config)); - pxa_set_ac97_info(NULL); - } - - if (balloon3_has(BALLOON3_FEATURE_TOPPOLY)) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config)); - gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, - "LCD Backlight Power"); - gpio_direction_output(BALLOON3_GPIO_RUN_BACKLIGHT, 1); - set_pxa_fb_info(&balloon3_pxafb_info); - } - - if (balloon3_has(BALLOON3_FEATURE_MMC)) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config)); - pxa_set_mci_info(&balloon3_mci_platform_data); - } - pxa_set_ficp_info(&balloon3_ficp_platform_data); - if (balloon3_has(BALLOON3_FEATURE_OHCI)) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ohci_pin_config)); - pxa_set_ohci_info(&balloon3_ohci_platform_data); - } - pxa_set_udc_info(&balloon3_udc_info); - - pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_pin_config)); - - platform_device_register(&balloon3led_device); + balloon3_i2c_init(); + balloon3_irda_init(); + balloon3_lcd_init(); + balloon3_leds_init(); + balloon3_mmc_init(); + balloon3_nand_init(); + balloon3_nor_init(); + balloon3_pmic_init(); + balloon3_ts_init(); + balloon3_udc_init(); + balloon3_uhc_init(); } static struct map_desc balloon3_io_desc[] __initdata = { diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index fdda6be6c39..c70e6c2f4e7 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -689,6 +689,7 @@ static void __init cm_x300_init_da9030(void) { pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); i2c_register_board_info(1, &cm_x300_pmic_info, 1); + set_irq_wake(IRQ_WAKEUP0, 1); } static void __init cm_x300_init_wi2wi(void) @@ -745,9 +746,10 @@ static void __init cm_x300_init(void) { cm_x300_init_mfp(); - pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); + if (cpu_is_pxa300()) + pxa_set_ffuart_info(NULL); cm_x300_init_da9030(); cm_x300_init_dm9000(); diff --git a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c b/arch/arm/mach-pxa/colibri-pxa270-evalboard.c new file mode 100644 index 00000000000..0f3b632c3b1 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa270-evalboard.c @@ -0,0 +1,111 @@ +/* + * linux/arch/arm/mach-pxa/colibri-pxa270-evalboard.c + * + * Support for Toradex PXA270 based Colibri Evaluation Carrier Board + * Daniel Mack <daniel@caiaq.de> + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <asm/mach/arch.h> + +#include <mach/pxa27x.h> +#include <mach/colibri.h> +#include <mach/mmc.h> +#include <mach/ohci.h> +#include <mach/pxa27x-udc.h> + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO0_GPIO, /* SD detect */ + + /* FFUART */ + GPIO39_FFUART_TXD, + GPIO34_FFUART_RXD, + + /* UHC */ + GPIO88_USBH1_PWR, + GPIO89_USBH1_PEN, + GPIO119_USBH2_PWR, + GPIO120_USBH2_PEN, +}; + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +static struct pxamci_platform_data colibri_pxa270_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_power = -1, + .gpio_card_detect = GPIO0_COLIBRI_PXA270_SD_DETECT, + .gpio_card_ro = -1, + .detect_delay_ms = 200, +}; + +static void __init colibri_pxa270_mmc_init(void) +{ + pxa_set_mci_info(&colibri_pxa270_mci_platform_data); +} +#else +static inline void colibri_pxa270_mmc_init(void) {} +#endif + +/****************************************************************************** + * USB Host + ******************************************************************************/ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static int colibri_pxa270_ohci_init(struct device *dev) +{ + UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; + return 0; +} + +static struct pxaohci_platform_data colibri_pxa270_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT1 | ENABLE_PORT2 | + POWER_CONTROL_LOW | POWER_SENSE_LOW, + .init = colibri_pxa270_ohci_init, +}; + +static void __init colibri_pxa270_uhc_init(void) +{ + pxa_set_ohci_info(&colibri_pxa270_ohci_info); +} +#else +static inline void colibri_pxa270_uhc_init(void) {} +#endif + +void __init colibri_pxa270_evalboard_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_evalboard_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + + colibri_pxa270_mmc_init(); + colibri_pxa270_uhc_init(); +} + diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c new file mode 100644 index 00000000000..37f0f3ed7c6 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -0,0 +1,272 @@ +/* + * linux/arch/arm/mach-pxa/income.c + * + * Support for Income s.r.o. SH-Dmaster PXA270 SBC + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * Pavel Revak <palo@bielyvlk.sk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <linux/sysdev.h> + +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include <mach/hardware.h> +#include <mach/mmc.h> +#include <mach/ohci.h> +#include <mach/pxa27x.h> +#include <mach/pxa27x-udc.h> +#include <mach/pxafb.h> + +#include <plat/i2c.h> + +#include "devices.h" +#include "generic.h" + +#define GPIO114_INCOME_ETH_IRQ (114) +#define GPIO0_INCOME_SD_DETECT (0) +#define GPIO0_INCOME_SD_RO (1) +#define GPIO54_INCOME_LED_A (54) +#define GPIO55_INCOME_LED_B (55) +#define GPIO113_INCOME_TS_IRQ (113) + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static mfp_cfg_t income_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO0_GPIO, /* SD detect */ + GPIO1_GPIO, /* SD read-only */ + + /* FFUART */ + GPIO39_FFUART_TXD, + GPIO34_FFUART_RXD, + + /* BFUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO45_BTUART_RTS, + + /* STUART */ + GPIO46_STUART_RXD, + GPIO47_STUART_TXD, + + /* UHC */ + GPIO88_USBH1_PWR, + GPIO89_USBH1_PEN, + + /* LCD */ + GPIOxx_LCD_TFT_16BPP, + + /* PWM */ + GPIO16_PWM0_OUT, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* LED */ + GPIO54_GPIO, /* LED A */ + GPIO55_GPIO, /* LED B */ +}; + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +static struct pxamci_platform_data income_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_power = -1, + .gpio_card_detect = GPIO0_INCOME_SD_DETECT, + .gpio_card_ro = GPIO0_INCOME_SD_RO, + .detect_delay_ms = 200, +}; + +static void __init income_mmc_init(void) +{ + pxa_set_mci_info(&income_mci_platform_data); +} +#else +static inline void income_mmc_init(void) {} +#endif + +/****************************************************************************** + * USB Host + ******************************************************************************/ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static struct pxaohci_platform_data income_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, +}; + +static void __init income_uhc_init(void) +{ + pxa_set_ohci_info(&income_ohci_info); +} +#else +static inline void income_uhc_init(void) {} +#endif + +/****************************************************************************** + * LED + ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +struct gpio_led income_gpio_leds[] = { + { + .name = "income:green:leda", + .default_trigger = "none", + .gpio = GPIO54_INCOME_LED_A, + .active_low = 1, + }, + { + .name = "income:green:ledb", + .default_trigger = "none", + .gpio = GPIO55_INCOME_LED_B, + .active_low = 1, + } +}; + +static struct gpio_led_platform_data income_gpio_led_info = { + .leds = income_gpio_leds, + .num_leds = ARRAY_SIZE(income_gpio_leds), +}; + +static struct platform_device income_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &income_gpio_led_info, + } +}; + +static void __init income_led_init(void) +{ + platform_device_register(&income_leds); +} +#else +static inline void income_led_init(void) {} +#endif + +/****************************************************************************** + * I2C + ******************************************************************************/ +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) +static struct i2c_board_info __initdata income_i2c_devs[] = { + { + I2C_BOARD_INFO("ds1340", 0x68), + }, { + I2C_BOARD_INFO("lm75", 0x4f), + }, +}; + +static void __init income_i2c_init(void) +{ + pxa_set_i2c_info(NULL); + pxa27x_set_i2c_power_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(income_i2c_devs)); +} +#else +static inline void income_i2c_init(void) {} +#endif + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +static struct pxafb_mode_info income_lcd_modes[] = { +{ + .pixclock = 144700, + .xres = 320, + .yres = 240, + .bpp = 32, + .depth = 18, + + .left_margin = 10, + .right_margin = 10, + .upper_margin = 7, + .lower_margin = 8, + + .hsync_len = 20, + .vsync_len = 2, + + .sync = FB_SYNC_VERT_HIGH_ACT, +}, +}; + +static struct pxafb_mach_info income_lcd_screen = { + .modes = income_lcd_modes, + .num_modes = ARRAY_SIZE(income_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_18BPP | LCD_PCLK_EDGE_FALL, +}; + +static void __init income_lcd_init(void) +{ + set_pxa_fb_info(&income_lcd_screen); +} +#else +static inline void income_lcd_init(void) {} +#endif + +/****************************************************************************** + * Backlight + ******************************************************************************/ +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM__MODULE) +static struct platform_pwm_backlight_data income_backlight_data = { + .pwm_id = 0, + .max_brightness = 0x3ff, + .dft_brightness = 0x1ff, + .pwm_period_ns = 1000000, +}; + +static struct platform_device income_backlight = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &income_backlight_data, + }, +}; + +static void __init income_pwm_init(void) +{ + platform_device_register(&income_backlight); +} +#else +static inline void income_pwm_init(void) {} +#endif + +void __init colibri_pxa270_income_boardinit(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + + income_mmc_init(); + income_uhc_init(); + income_led_init(); + income_i2c_init(); + income_lcd_init(); + income_pwm_init(); +} + diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 061c45316de..98673ac6efd 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -3,6 +3,7 @@ * * Support for Toradex PXA270 based Colibri module * Daniel Mack <daniel@caiaq.de> + * Marek Vasut <marek.vasut@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -10,49 +11,55 @@ */ #include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/delay.h> +#include <linux/kernel.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/sizes.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/ucb1400.h> + #include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> #include <asm/mach/flash.h> +#include <asm/mach-types.h> +#include <asm/sizes.h> -#include <mach/pxa27x.h> +#include <mach/audio.h> #include <mach/colibri.h> +#include <mach/pxa27x.h> -#include "generic.h" #include "devices.h" +#include "generic.h" -/* - * GPIO configuration - */ +/****************************************************************************** + * Pin configuration + ******************************************************************************/ static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = { + /* Ethernet */ GPIO78_nCS_2, /* Ethernet CS */ GPIO114_GPIO, /* Ethernet IRQ */ + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO95_AC97_nRESET, + GPIO98_AC97_SYSCLK, + GPIO113_GPIO, /* Touchscreen IRQ */ }; -/* - * NOR flash - */ +/****************************************************************************** + * NOR Flash + ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition colibri_partitions[] = { { .name = "Bootloader", .offset = 0x00000000, .size = 0x00040000, - .mask_flags = MTD_WRITEABLE /* force read-only */ + .mask_flags = MTD_WRITEABLE /* force read-only */ }, { .name = "Kernel", .offset = 0x00040000, @@ -90,50 +97,113 @@ static struct platform_device colibri_pxa270_flash_device = { .num_resources = 1, }; -/* - * DM9000 Ethernet - */ -#if defined(CONFIG_DM9000) -static struct resource dm9000_resources[] = { - [0] = { - .start = COLIBRI_PXA270_ETH_PHYS, - .end = COLIBRI_PXA270_ETH_PHYS + 3, +static void __init colibri_pxa270_nor_init(void) +{ + platform_device_register(&colibri_pxa270_flash_device); +} +#else +static inline void colibri_pxa270_nor_init(void) {} +#endif + +/****************************************************************************** + * Ethernet + ******************************************************************************/ +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) +static struct resource colibri_pxa270_dm9000_resources[] = { + { + .start = PXA_CS2_PHYS, + .end = PXA_CS2_PHYS + 3, .flags = IORESOURCE_MEM, }, - [1] = { - .start = COLIBRI_PXA270_ETH_PHYS + 4, - .end = COLIBRI_PXA270_ETH_PHYS + 4 + 500, + { + .start = PXA_CS2_PHYS + 4, + .end = PXA_CS2_PHYS + 4 + 500, .flags = IORESOURCE_MEM, }, - [2] = { - .start = COLIBRI_PXA270_ETH_IRQ, - .end = COLIBRI_PXA270_ETH_IRQ, + { + .start = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .end = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, }, }; -static struct platform_device dm9000_device = { +static struct platform_device colibri_pxa270_dm9000_device = { .name = "dm9000", .id = -1, - .num_resources = ARRAY_SIZE(dm9000_resources), - .resource = dm9000_resources, + .num_resources = ARRAY_SIZE(colibri_pxa270_dm9000_resources), + .resource = colibri_pxa270_dm9000_resources, }; -#endif /* CONFIG_DM9000 */ -static struct platform_device *colibri_pxa270_devices[] __initdata = { - &colibri_pxa270_flash_device, -#if defined(CONFIG_DM9000) - &dm9000_device, +static void __init colibri_pxa270_eth_init(void) +{ + platform_device_register(&colibri_pxa270_dm9000_device); +} +#else +static inline void colibri_pxa270_eth_init(void) {} #endif + +/****************************************************************************** + * Audio and Touchscreen + ******************************************************************************/ +#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \ + defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) +static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = { + .reset_gpio = 95, +}; + +static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = { + .irq = gpio_to_irq(GPIO113_COLIBRI_PXA270_TS_IRQ), +}; + +static struct platform_device colibri_pxa270_ucb1400_device = { + .name = "ucb1400_core", + .id = -1, + .dev = { + .platform_data = &colibri_pxa270_ucb1400_pdata, + }, }; +static void __init colibri_pxa270_tsc_init(void) +{ + pxa_set_ac97_info(&colibri_pxa270_ac97_pdata); + platform_device_register(&colibri_pxa270_ucb1400_device); +} +#else +static inline void colibri_pxa270_tsc_init(void) {} +#endif + +static int colibri_pxa270_baseboard; +core_param(colibri_pxa270_baseboard, colibri_pxa270_baseboard, int, 0444); + static void __init colibri_pxa270_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config)); - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices)); + + colibri_pxa270_nor_init(); + colibri_pxa270_eth_init(); + colibri_pxa270_tsc_init(); + + switch (colibri_pxa270_baseboard) { + case COLIBRI_PXA270_EVALBOARD: + colibri_pxa270_evalboard_init(); + break; + case COLIBRI_PXA270_INCOME: + colibri_pxa270_income_boardinit(); + break; + default: + printk(KERN_ERR "Illegal colibri_pxa270_baseboard type %d\n", + colibri_pxa270_baseboard); + } +} + +/* The "Income s.r.o. SH-Dmaster PXA270 SBC" board can be booted either + * with the INCOME mach type or with COLIBRI and the kernel parameter + * "colibri_pxa270_baseboard=1" + */ +static void __init colibri_pxa270_income_init(void) +{ + colibri_pxa270_baseboard = COLIBRI_PXA270_INCOME; + colibri_pxa270_init(); } MACHINE_START(COLIBRI, "Toradex Colibri PXA270") @@ -146,3 +216,13 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270") .timer = &pxa_timer, MACHINE_END +MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .init_machine = colibri_pxa270_income_init, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, +MACHINE_END + diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index ae835fad7d1..99e850d8471 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -16,6 +16,7 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/interrupt.h> +#include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> #include <asm/sizes.h> @@ -28,6 +29,8 @@ #include <mach/pxafb.h> #include <mach/ohci.h> #include <mach/audio.h> +#include <mach/pxa27x-udc.h> +#include <mach/udc.h> #include "generic.h" #include "devices.h" @@ -101,6 +104,42 @@ void __init colibri_pxa320_init_ohci(void) static inline void colibri_pxa320_init_ohci(void) {} #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ +#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) +static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = { + .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96), + .gpio_pullup = -1, +}; + +static struct platform_device colibri_pxa320_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &colibri_pxa320_gpio_vbus_info, + }, +}; + +static void colibri_pxa320_udc_command(int cmd) +{ + if (cmd == PXA2XX_UDC_CMD_CONNECT) + UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE; + else if (cmd == PXA2XX_UDC_CMD_DISCONNECT) + UP2OCR = UP2OCR_HXOE; +} + +static struct pxa2xx_udc_mach_info colibri_pxa320_udc_info __initdata = { + .udc_command = colibri_pxa320_udc_command, + .gpio_pullup = -1, +}; + +static void __init colibri_pxa320_init_udc(void) +{ + pxa_set_udc_info(&colibri_pxa320_udc_info); + platform_device_register(&colibri_pxa320_gpio_vbus); +} +#else +static inline void colibri_pxa320_init_udc(void) {} +#endif + static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = { GPIO22_MMC1_CLK, GPIO23_MMC1_CMD, @@ -212,6 +251,7 @@ void __init colibri_pxa320_init(void) colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config), mfp_to_gpio(MFP_PIN_GPIO28)); colibri_pxa320_init_uart(); + colibri_pxa320_init_udc(); } MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 461ba408015..3fb0fc09908 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -50,14 +50,13 @@ #include <mach/udc.h> #include <mach/pxa2xx_spi.h> #include <mach/corgi.h> -#include <mach/sharpsl.h> +#include <mach/sharpsl_pm.h> #include <asm/mach/sharpsl_param.h> #include <asm/hardware/scoop.h> #include "generic.h" #include "devices.h" -#include "sharpsl.h" static unsigned long corgi_pin_config[] __initdata = { /* Static Memory I/O */ @@ -185,8 +184,6 @@ static struct scoop_pcmcia_config corgi_pcmcia_config = { .num_devs = 1, }; -EXPORT_SYMBOL(corgiscoop_device); - static struct w100_mem_info corgi_fb_mem = { .ext_cntl = 0x00040003, .sdram_mode_reg = 0x00650021, diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index 3f1dc74ac04..29034778bfd 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -23,12 +23,11 @@ #include <asm/mach-types.h> #include <mach/hardware.h> -#include <mach/sharpsl.h> #include <mach/corgi.h> #include <mach/pxa2xx-regs.h> +#include <mach/sharpsl_pm.h> #include "generic.h" -#include "sharpsl.h" #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ #define SHARPSL_CHARGE_ON_TEMP 0xe0 /* 2.9V */ @@ -134,11 +133,11 @@ unsigned long corgipm_read_devdata(int type) case SHARPSL_STATUS_ACIN: return ((GPLR(CORGI_GPIO_AC_IN) & GPIO_bit(CORGI_GPIO_AC_IN)) != 0); case SHARPSL_STATUS_LOCK: - return READ_GPIO_BIT(sharpsl_pm.machinfo->gpio_batlock); + return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock); case SHARPSL_STATUS_CHRGFULL: - return READ_GPIO_BIT(sharpsl_pm.machinfo->gpio_batfull); + return gpio_get_value(sharpsl_pm.machinfo->gpio_batfull); case SHARPSL_STATUS_FATAL: - return READ_GPIO_BIT(sharpsl_pm.machinfo->gpio_fatal); + return gpio_get_value(sharpsl_pm.machinfo->gpio_fatal); case SHARPSL_ACIN_VOLT: return sharpsl_pm_pxa_read_max1111(MAX1111_ACIN_VOLT); case SHARPSL_BATT_TEMP: @@ -165,8 +164,6 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = { .should_wakeup = corgi_should_wakeup, #if defined(CONFIG_LCD_CORGI) .backlight_limit = corgi_lcd_limit_intensity, -#elif defined(CONFIG_BACKLIGHT_CORGI) - .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 8e10db148f1..65447dc736c 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -4,6 +4,7 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <asm/pmu.h> #include <mach/udc.h> #include <mach/pxafb.h> #include <mach/mmc.h> @@ -31,6 +32,19 @@ void __init pxa_register_device(struct platform_device *dev, void *data) dev_err(&dev->dev, "unable to register device: %d\n", ret); } +static struct resource pxa_resource_pmu = { + .start = IRQ_PMU, + .end = IRQ_PMU, + .flags = IORESOURCE_IRQ, +}; + +struct platform_device pxa_device_pmu = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .resource = &pxa_resource_pmu, + .num_resources = 1, +}; + static struct resource pxamci_resources[] = { [0] = { .start = 0x41100000, diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 93817d99761..50353ea49ba 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -1,3 +1,4 @@ +extern struct platform_device pxa_device_pmu; extern struct platform_device pxa_device_mci; extern struct platform_device pxa3xx_device_mci2; extern struct platform_device pxa3xx_device_mci3; diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c deleted file mode 100644 index 8fde3387279..00000000000 --- a/arch/arm/mach-pxa/e330.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Hardware definitions for the Toshiba e330 PDAs - * - * Copyright (c) 2003 Ian Molton <spyro@f2s.com> - * - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/platform_device.h> -#include <linux/mfd/tc6387xb.h> - -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/pxa25x.h> -#include <mach/eseries-gpio.h> -#include <mach/udc.h> - -#include "generic.h" -#include "eseries.h" -#include "clock.h" - -/* -------------------- e330 tc6387xb parameters -------------------- */ - -static struct tc6387xb_platform_data e330_tc6387xb_info = { - .enable = &eseries_tmio_enable, - .disable = &eseries_tmio_disable, - .suspend = &eseries_tmio_suspend, - .resume = &eseries_tmio_resume, -}; - -static struct platform_device e330_tc6387xb_device = { - .name = "tc6387xb", - .id = -1, - .dev = { - .platform_data = &e330_tc6387xb_info, - }, - .num_resources = 2, - .resource = eseries_tmio_resources, -}; - -/* --------------------------------------------------------------- */ - -static struct platform_device *devices[] __initdata = { - &e330_tc6387xb_device, -}; - -static void __init e330_init(void) -{ - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - eseries_register_clks(); - eseries_get_tmio_gpios(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); -} - -MACHINE_START(E330, "Toshiba e330") - /* Maintainer: Ian Molton (spyro@f2s.com) */ - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa25x_init_irq, - .fixup = eseries_fixup, - .init_machine = e330_init, - .timer = &pxa_timer, -MACHINE_END - diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c deleted file mode 100644 index f50f055f572..00000000000 --- a/arch/arm/mach-pxa/e350.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Hardware definitions for the Toshiba e350 PDAs - * - * Copyright (c) 2003 Ian Molton <spyro@f2s.com> - * - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/platform_device.h> -#include <linux/mfd/t7l66xb.h> - -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/irqs.h> -#include <mach/pxa25x.h> -#include <mach/eseries-gpio.h> -#include <mach/udc.h> - -#include "generic.h" -#include "eseries.h" -#include "clock.h" - -/* -------------------- e350 t7l66xb parameters -------------------- */ - -static struct t7l66xb_platform_data e350_t7l66xb_info = { - .irq_base = IRQ_BOARD_START, - .enable = &eseries_tmio_enable, - .suspend = &eseries_tmio_suspend, - .resume = &eseries_tmio_resume, -}; - -static struct platform_device e350_t7l66xb_device = { - .name = "t7l66xb", - .id = -1, - .dev = { - .platform_data = &e350_t7l66xb_info, - }, - .num_resources = 2, - .resource = eseries_tmio_resources, -}; - -/* ---------------------------------------------------------- */ - -static struct platform_device *devices[] __initdata = { - &e350_t7l66xb_device, -}; - -static void __init e350_init(void) -{ - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - eseries_register_clks(); - eseries_get_tmio_gpios(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); -} - -MACHINE_START(E350, "Toshiba e350") - /* Maintainer: Ian Molton (spyro@f2s.com) */ - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa25x_init_irq, - .fixup = eseries_fixup, - .init_machine = e350_init, - .timer = &pxa_timer, -MACHINE_END - diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c deleted file mode 100644 index 55b950f1284..00000000000 --- a/arch/arm/mach-pxa/e400.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Hardware definitions for the Toshiba eseries PDAs - * - * Copyright (c) 2003 Ian Molton <spyro@f2s.com> - * - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/platform_device.h> -#include <linux/mfd/t7l66xb.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/partitions.h> - -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/pxa25x.h> -#include <mach/eseries-gpio.h> -#include <mach/pxafb.h> -#include <mach/udc.h> -#include <mach/irqs.h> - -#include "generic.h" -#include "eseries.h" -#include "clock.h" - -/* ------------------------ E400 LCD definitions ------------------------ */ - -static struct pxafb_mode_info e400_pxafb_mode_info = { - .pixclock = 140703, - .xres = 240, - .yres = 320, - .bpp = 16, - .hsync_len = 4, - .left_margin = 28, - .right_margin = 8, - .vsync_len = 3, - .upper_margin = 5, - .lower_margin = 6, - .sync = 0, -}; - -static struct pxafb_mach_info e400_pxafb_mach_info = { - .modes = &e400_pxafb_mode_info, - .num_modes = 1, - .lcd_conn = LCD_COLOR_TFT_16BPP, - .lccr3 = 0, - .pxafb_backlight_power = NULL, -}; - -/* ------------------------ E400 MFP config ----------------------------- */ - -static unsigned long e400_pin_config[] __initdata = { - /* Chip selects */ - GPIO15_nCS_1, /* CS1 - Flash */ - GPIO80_nCS_4, /* CS4 - TMIO */ - - /* Clocks */ - GPIO12_32KHz, - - /* BTUART */ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - - /* TMIO controller */ - GPIO19_GPIO, /* t7l66xb #PCLR */ - GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ - - /* wakeup */ - GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, -}; - -/* ---------------------------------------------------------------------- */ - -static struct mtd_partition partition_a = { - .name = "Internal NAND flash", - .offset = 0, - .size = MTDPART_SIZ_FULL, -}; - -static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; - -static struct nand_bbt_descr e400_t7l66xb_nand_bbt = { - .options = 0, - .offs = 4, - .len = 2, - .pattern = scan_ff_pattern -}; - -static struct tmio_nand_data e400_t7l66xb_nand_config = { - .num_partitions = 1, - .partition = &partition_a, - .badblock_pattern = &e400_t7l66xb_nand_bbt, -}; - -static struct t7l66xb_platform_data e400_t7l66xb_info = { - .irq_base = IRQ_BOARD_START, - .enable = &eseries_tmio_enable, - .suspend = &eseries_tmio_suspend, - .resume = &eseries_tmio_resume, - - .nand_data = &e400_t7l66xb_nand_config, -}; - -static struct platform_device e400_t7l66xb_device = { - .name = "t7l66xb", - .id = -1, - .dev = { - .platform_data = &e400_t7l66xb_info, - }, - .num_resources = 2, - .resource = eseries_tmio_resources, -}; - -/* ---------------------------------------------------------- */ - -static struct platform_device *devices[] __initdata = { - &e400_t7l66xb_device, -}; - -static void __init e400_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - /* Fixme - e400 may have a switched clock */ - eseries_register_clks(); - eseries_get_tmio_gpios(); - set_pxa_fb_info(&e400_pxafb_mach_info); - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); -} - -MACHINE_START(E400, "Toshiba e400") - /* Maintainer: Ian Molton (spyro@f2s.com) */ - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa25x_init_irq, - .fixup = eseries_fixup, - .init_machine = e400_init, - .timer = &pxa_timer, -MACHINE_END - diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c deleted file mode 100644 index d578021d1a1..00000000000 --- a/arch/arm/mach-pxa/e740.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Hardware definitions for the Toshiba eseries PDAs - * - * Copyright (c) 2003 Ian Molton <spyro@f2s.com> - * - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/fb.h> -#include <linux/clk.h> -#include <linux/mfd/t7l66xb.h> - -#include <video/w100fb.h> - -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/pxa25x.h> -#include <mach/eseries-gpio.h> -#include <mach/udc.h> -#include <mach/irda.h> -#include <mach/irqs.h> -#include <mach/audio.h> - -#include "generic.h" -#include "eseries.h" -#include "clock.h" -#include "devices.h" - -/* ------------------------ e740 video support --------------------------- */ - -static struct w100_gen_regs e740_lcd_regs = { - .lcd_format = 0x00008023, - .lcdd_cntl1 = 0x0f000000, - .lcdd_cntl2 = 0x0003ffff, - .genlcd_cntl1 = 0x00ffff03, - .genlcd_cntl2 = 0x003c0f03, - .genlcd_cntl3 = 0x000143aa, -}; - -static struct w100_mode e740_lcd_mode = { - .xres = 240, - .yres = 320, - .left_margin = 20, - .right_margin = 28, - .upper_margin = 9, - .lower_margin = 8, - .crtc_ss = 0x80140013, - .crtc_ls = 0x81150110, - .crtc_gs = 0x80050005, - .crtc_vpos_gs = 0x000a0009, - .crtc_rev = 0x0040010a, - .crtc_dclk = 0xa906000a, - .crtc_gclk = 0x80050108, - .crtc_goe = 0x80050108, - .pll_freq = 57, - .pixclk_divider = 4, - .pixclk_divider_rotated = 4, - .pixclk_src = CLK_SRC_XTAL, - .sysclk_divider = 1, - .sysclk_src = CLK_SRC_PLL, - .crtc_ps1_active = 0x41060010, -}; - -static struct w100_gpio_regs e740_w100_gpio_info = { - .init_data1 = 0x21002103, - .gpio_dir1 = 0xffffdeff, - .gpio_oe1 = 0x03c00643, - .init_data2 = 0x003f003f, - .gpio_dir2 = 0xffffffff, - .gpio_oe2 = 0x000000ff, -}; - -static struct w100fb_mach_info e740_fb_info = { - .modelist = &e740_lcd_mode, - .num_modes = 1, - .regs = &e740_lcd_regs, - .gpio = &e740_w100_gpio_info, - .xtal_freq = 14318000, - .xtal_dbl = 1, -}; - -static struct resource e740_fb_resources[] = { - [0] = { - .start = 0x0c000000, - .end = 0x0cffffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device e740_fb_device = { - .name = "w100fb", - .id = -1, - .dev = { - .platform_data = &e740_fb_info, - }, - .num_resources = ARRAY_SIZE(e740_fb_resources), - .resource = e740_fb_resources, -}; - -/* --------------------------- MFP Pin config -------------------------- */ - -static unsigned long e740_pin_config[] __initdata = { - /* Chip selects */ - GPIO15_nCS_1, /* CS1 - Flash */ - GPIO79_nCS_3, /* CS3 - IMAGEON */ - GPIO80_nCS_4, /* CS4 - TMIO */ - - /* Clocks */ - GPIO12_32KHz, - - /* BTUART */ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - - /* TMIO controller */ - GPIO19_GPIO, /* t7l66xb #PCLR */ - GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ - - /* UDC */ - GPIO13_GPIO, - GPIO3_GPIO, - - /* IrDA */ - GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, - - /* AC97 */ - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, - - /* Audio power control */ - GPIO16_GPIO, /* AC97 codec AVDD2 supply (analogue power) */ - GPIO40_GPIO, /* Mic amp power */ - GPIO41_GPIO, /* Headphone amp power */ - - /* PC Card */ - GPIO8_GPIO, /* CD0 */ - GPIO44_GPIO, /* CD1 */ - GPIO11_GPIO, /* IRQ0 */ - GPIO6_GPIO, /* IRQ1 */ - GPIO27_GPIO, /* RST0 */ - GPIO24_GPIO, /* RST1 */ - GPIO20_GPIO, /* PWR0 */ - GPIO23_GPIO, /* PWR1 */ - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO52_nPCE_1, - GPIO53_nPCE_2, - GPIO54_nPSKTSEL, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - - /* wakeup */ - GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, -}; - -/* -------------------- e740 t7l66xb parameters -------------------- */ - -static struct t7l66xb_platform_data e740_t7l66xb_info = { - .irq_base = IRQ_BOARD_START, - .enable = &eseries_tmio_enable, - .suspend = &eseries_tmio_suspend, - .resume = &eseries_tmio_resume, -}; - -static struct platform_device e740_t7l66xb_device = { - .name = "t7l66xb", - .id = -1, - .dev = { - .platform_data = &e740_t7l66xb_info, - }, - .num_resources = 2, - .resource = eseries_tmio_resources, -}; - -/* ----------------------------------------------------------------------- */ - -static struct platform_device *devices[] __initdata = { - &e740_fb_device, - &e740_t7l66xb_device, -}; - -static void __init e740_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - eseries_register_clks(); - clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, - "UDCCLK", &pxa25x_device_udc.dev), - eseries_get_tmio_gpios(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); - pxa_set_ac97_info(NULL); - pxa_set_ficp_info(&e7xx_ficp_platform_data); -} - -MACHINE_START(E740, "Toshiba e740") - /* Maintainer: Ian Molton (spyro@f2s.com) */ - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa25x_init_irq, - .fixup = eseries_fixup, - .init_machine = e740_init, - .timer = &pxa_timer, -MACHINE_END - diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c deleted file mode 100644 index af83caa52dd..00000000000 --- a/arch/arm/mach-pxa/e750.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Hardware definitions for the Toshiba eseries PDAs - * - * Copyright (c) 2003 Ian Molton <spyro@f2s.com> - * - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/fb.h> -#include <linux/mfd/tc6393xb.h> - -#include <video/w100fb.h> - -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/pxa25x.h> -#include <mach/eseries-gpio.h> -#include <mach/udc.h> -#include <mach/irda.h> -#include <mach/irqs.h> -#include <mach/audio.h> - -#include "generic.h" -#include "eseries.h" -#include "clock.h" - -/* ---------------------- E750 LCD definitions -------------------- */ - -static struct w100_gen_regs e750_lcd_regs = { - .lcd_format = 0x00008003, - .lcdd_cntl1 = 0x00000000, - .lcdd_cntl2 = 0x0003ffff, - .genlcd_cntl1 = 0x00fff003, - .genlcd_cntl2 = 0x003c0f03, - .genlcd_cntl3 = 0x000143aa, -}; - -static struct w100_mode e750_lcd_mode = { - .xres = 240, - .yres = 320, - .left_margin = 21, - .right_margin = 22, - .upper_margin = 5, - .lower_margin = 4, - .crtc_ss = 0x80150014, - .crtc_ls = 0x8014000d, - .crtc_gs = 0xc1000005, - .crtc_vpos_gs = 0x00020147, - .crtc_rev = 0x0040010a, - .crtc_dclk = 0xa1700030, - .crtc_gclk = 0x80cc0015, - .crtc_goe = 0x80cc0015, - .crtc_ps1_active = 0x61060017, - .pll_freq = 57, - .pixclk_divider = 4, - .pixclk_divider_rotated = 4, - .pixclk_src = CLK_SRC_XTAL, - .sysclk_divider = 1, - .sysclk_src = CLK_SRC_PLL, -}; - -static struct w100_gpio_regs e750_w100_gpio_info = { - .init_data1 = 0x01192f1b, - .gpio_dir1 = 0xd5ffdeff, - .gpio_oe1 = 0x000020bf, - .init_data2 = 0x010f010f, - .gpio_dir2 = 0xffffffff, - .gpio_oe2 = 0x000001cf, -}; - -static struct w100fb_mach_info e750_fb_info = { - .modelist = &e750_lcd_mode, - .num_modes = 1, - .regs = &e750_lcd_regs, - .gpio = &e750_w100_gpio_info, - .xtal_freq = 14318000, - .xtal_dbl = 1, -}; - -static struct resource e750_fb_resources[] = { - [0] = { - .start = 0x0c000000, - .end = 0x0cffffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device e750_fb_device = { - .name = "w100fb", - .id = -1, - .dev = { - .platform_data = &e750_fb_info, - }, - .num_resources = ARRAY_SIZE(e750_fb_resources), - .resource = e750_fb_resources, -}; - -/* -------------------- e750 MFP parameters -------------------- */ - -static unsigned long e750_pin_config[] __initdata = { - /* Chip selects */ - GPIO15_nCS_1, /* CS1 - Flash */ - GPIO79_nCS_3, /* CS3 - IMAGEON */ - GPIO80_nCS_4, /* CS4 - TMIO */ - - /* Clocks */ - GPIO11_3_6MHz, - - /* BTUART */ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - - /* TMIO controller */ - GPIO19_GPIO, /* t7l66xb #PCLR */ - GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ - - /* UDC */ - GPIO13_GPIO, - GPIO3_GPIO, - - /* IrDA */ - GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, - - /* AC97 */ - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, - - /* Audio power control */ - GPIO4_GPIO, /* Headphone amp power */ - GPIO7_GPIO, /* Speaker amp power */ - GPIO37_GPIO, /* Headphone detect */ - - /* PC Card */ - GPIO8_GPIO, /* CD0 */ - GPIO44_GPIO, /* CD1 */ - GPIO11_GPIO, /* IRQ0 */ - GPIO6_GPIO, /* IRQ1 */ - GPIO27_GPIO, /* RST0 */ - GPIO24_GPIO, /* RST1 */ - GPIO20_GPIO, /* PWR0 */ - GPIO23_GPIO, /* PWR1 */ - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO52_nPCE_1, - GPIO53_nPCE_2, - GPIO54_nPSKTSEL, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - - /* wakeup */ - GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, -}; - -/* ----------------- e750 tc6393xb parameters ------------------ */ - -static struct tc6393xb_platform_data e750_tc6393xb_info = { - .irq_base = IRQ_BOARD_START, - .scr_pll2cr = 0x0cc1, - .scr_gper = 0, - .gpio_base = -1, - .suspend = &eseries_tmio_suspend, - .resume = &eseries_tmio_resume, - .enable = &eseries_tmio_enable, - .disable = &eseries_tmio_disable, -}; - -static struct platform_device e750_tc6393xb_device = { - .name = "tc6393xb", - .id = -1, - .dev = { - .platform_data = &e750_tc6393xb_info, - }, - .num_resources = 2, - .resource = eseries_tmio_resources, -}; - -/* ------------------------------------------------------------- */ - -static struct platform_device *devices[] __initdata = { - &e750_fb_device, - &e750_tc6393xb_device, -}; - -static void __init e750_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, - "GPIO11_CLK", NULL), - eseries_get_tmio_gpios(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); - pxa_set_ac97_info(NULL); - pxa_set_ficp_info(&e7xx_ficp_platform_data); -} - -MACHINE_START(E750, "Toshiba e750") - /* Maintainer: Ian Molton (spyro@f2s.com) */ - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa25x_init_irq, - .fixup = eseries_fixup, - .init_machine = e750_init, - .timer = &pxa_timer, -MACHINE_END - diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c deleted file mode 100644 index 8ea97bf53fe..00000000000 --- a/arch/arm/mach-pxa/e800.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Hardware definitions for the Toshiba eseries PDAs - * - * Copyright (c) 2003 Ian Molton <spyro@f2s.com> - * - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/fb.h> -#include <linux/mfd/tc6393xb.h> - -#include <video/w100fb.h> - -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/pxa25x.h> -#include <mach/eseries-gpio.h> -#include <mach/udc.h> -#include <mach/irqs.h> -#include <mach/audio.h> - -#include "generic.h" -#include "eseries.h" -#include "clock.h" - -/* ------------------------ e800 LCD definitions ------------------------- */ - -static unsigned long e800_pin_config[] __initdata = { - /* AC97 */ - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, -}; - -static struct w100_gen_regs e800_lcd_regs = { - .lcd_format = 0x00008003, - .lcdd_cntl1 = 0x02a00000, - .lcdd_cntl2 = 0x0003ffff, - .genlcd_cntl1 = 0x000ff2a3, - .genlcd_cntl2 = 0x000002a3, - .genlcd_cntl3 = 0x000102aa, -}; - -static struct w100_mode e800_lcd_mode[2] = { - [0] = { - .xres = 480, - .yres = 640, - .left_margin = 52, - .right_margin = 148, - .upper_margin = 2, - .lower_margin = 6, - .crtc_ss = 0x80350034, - .crtc_ls = 0x802b0026, - .crtc_gs = 0x80160016, - .crtc_vpos_gs = 0x00020003, - .crtc_rev = 0x0040001d, - .crtc_dclk = 0xe0000000, - .crtc_gclk = 0x82a50049, - .crtc_goe = 0x80ee001c, - .crtc_ps1_active = 0x00000000, - .pll_freq = 128, - .pixclk_divider = 4, - .pixclk_divider_rotated = 6, - .pixclk_src = CLK_SRC_PLL, - .sysclk_divider = 0, - .sysclk_src = CLK_SRC_PLL, - }, - [1] = { - .xres = 240, - .yres = 320, - .left_margin = 15, - .right_margin = 88, - .upper_margin = 0, - .lower_margin = 7, - .crtc_ss = 0xd010000f, - .crtc_ls = 0x80070003, - .crtc_gs = 0x80000000, - .crtc_vpos_gs = 0x01460147, - .crtc_rev = 0x00400003, - .crtc_dclk = 0xa1700030, - .crtc_gclk = 0x814b0008, - .crtc_goe = 0x80cc0015, - .crtc_ps1_active = 0x00000000, - .pll_freq = 100, - .pixclk_divider = 6, /* Wince uses 14 which gives a */ - .pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */ - .pixclk_src = CLK_SRC_PLL, - .sysclk_divider = 0, - .sysclk_src = CLK_SRC_PLL, - } -}; - - -static struct w100_gpio_regs e800_w100_gpio_info = { - .init_data1 = 0xc13fc019, - .gpio_dir1 = 0x3e40df7f, - .gpio_oe1 = 0x003c3000, - .init_data2 = 0x00000000, - .gpio_dir2 = 0x00000000, - .gpio_oe2 = 0x00000000, -}; - -static struct w100_mem_info e800_w100_mem_info = { - .ext_cntl = 0x09640011, - .sdram_mode_reg = 0x00600021, - .ext_timing_cntl = 0x10001545, - .io_cntl = 0x7ddd7333, - .size = 0x1fffff, -}; - -static void e800_tg_change(struct w100fb_par *par) -{ - unsigned long tmp; - - tmp = w100fb_gpio_read(W100_GPIO_PORT_A); - if (par->mode->xres == 480) - tmp |= 0x100; - else - tmp &= ~0x100; - w100fb_gpio_write(W100_GPIO_PORT_A, tmp); -} - -static struct w100_tg_info e800_tg_info = { - .change = e800_tg_change, -}; - -static struct w100fb_mach_info e800_fb_info = { - .modelist = e800_lcd_mode, - .num_modes = 2, - .regs = &e800_lcd_regs, - .gpio = &e800_w100_gpio_info, - .mem = &e800_w100_mem_info, - .tg = &e800_tg_info, - .xtal_freq = 16000000, -}; - -static struct resource e800_fb_resources[] = { - [0] = { - .start = 0x0c000000, - .end = 0x0cffffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device e800_fb_device = { - .name = "w100fb", - .id = -1, - .dev = { - .platform_data = &e800_fb_info, - }, - .num_resources = ARRAY_SIZE(e800_fb_resources), - .resource = e800_fb_resources, -}; - -/* --------------------------- UDC definitions --------------------------- */ - -static struct pxa2xx_udc_mach_info e800_udc_mach_info = { - .gpio_vbus = GPIO_E800_USB_DISC, - .gpio_pullup = GPIO_E800_USB_PULLUP, - .gpio_pullup_inverted = 1 -}; - -/* ----------------- e800 tc6393xb parameters ------------------ */ - -static struct tc6393xb_platform_data e800_tc6393xb_info = { - .irq_base = IRQ_BOARD_START, - .scr_pll2cr = 0x0cc1, - .scr_gper = 0, - .gpio_base = -1, - .suspend = &eseries_tmio_suspend, - .resume = &eseries_tmio_resume, - .enable = &eseries_tmio_enable, - .disable = &eseries_tmio_disable, -}; - -static struct platform_device e800_tc6393xb_device = { - .name = "tc6393xb", - .id = -1, - .dev = { - .platform_data = &e800_tc6393xb_info, - }, - .num_resources = 2, - .resource = eseries_tmio_resources, -}; - -/* ----------------------------------------------------------------------- */ - -static struct platform_device *devices[] __initdata = { - &e800_fb_device, - &e800_tc6393xb_device, -}; - -static void __init e800_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config)); - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, - "GPIO11_CLK", NULL), - eseries_get_tmio_gpios(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_udc_info(&e800_udc_mach_info); - pxa_set_ac97_info(NULL); -} - -MACHINE_START(E800, "Toshiba e800") - /* Maintainer: Ian Molton (spyro@f2s.com) */ - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa25x_init_irq, - .fixup = eseries_fixup, - .init_machine = e800_init, - .timer = &pxa_timer, -MACHINE_END - diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index a0ab3082a00..349212a1cbd 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -15,6 +15,13 @@ #include <linux/gpio.h> #include <linux/delay.h> #include <linux/platform_device.h> +#include <linux/mfd/tc6387xb.h> +#include <linux/mfd/tc6393xb.h> +#include <linux/mfd/t7l66xb.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> + +#include <video/w100fb.h> #include <asm/setup.h> #include <asm/mach/arch.h> @@ -22,9 +29,12 @@ #include <mach/pxa25x.h> #include <mach/eseries-gpio.h> +#include <mach/audio.h> +#include <mach/pxafb.h> #include <mach/udc.h> #include <mach/irda.h> +#include "devices.h" #include "generic.h" #include "clock.h" @@ -130,3 +140,802 @@ void eseries_register_clks(void) clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs)); } +#ifdef CONFIG_MACH_E330 +/* -------------------- e330 tc6387xb parameters -------------------- */ + +static struct tc6387xb_platform_data e330_tc6387xb_info = { + .enable = &eseries_tmio_enable, + .disable = &eseries_tmio_disable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, +}; + +static struct platform_device e330_tc6387xb_device = { + .name = "tc6387xb", + .id = -1, + .dev = { + .platform_data = &e330_tc6387xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* --------------------------------------------------------------- */ + +static struct platform_device *e330_devices[] __initdata = { + &e330_tc6387xb_device, +}; + +static void __init e330_init(void) +{ + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + eseries_register_clks(); + eseries_get_tmio_gpios(); + platform_add_devices(ARRAY_AND_SIZE(e330_devices)); + pxa_set_udc_info(&e7xx_udc_mach_info); +} + +MACHINE_START(E330, "Toshiba e330") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .init_machine = e330_init, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E350 +/* -------------------- e350 t7l66xb parameters -------------------- */ + +static struct t7l66xb_platform_data e350_t7l66xb_info = { + .irq_base = IRQ_BOARD_START, + .enable = &eseries_tmio_enable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, +}; + +static struct platform_device e350_t7l66xb_device = { + .name = "t7l66xb", + .id = -1, + .dev = { + .platform_data = &e350_t7l66xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ---------------------------------------------------------- */ + +static struct platform_device *e350_devices[] __initdata = { + &e350_t7l66xb_device, +}; + +static void __init e350_init(void) +{ + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + eseries_register_clks(); + eseries_get_tmio_gpios(); + platform_add_devices(ARRAY_AND_SIZE(e350_devices)); + pxa_set_udc_info(&e7xx_udc_mach_info); +} + +MACHINE_START(E350, "Toshiba e350") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .init_machine = e350_init, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E400 +/* ------------------------ E400 LCD definitions ------------------------ */ + +static struct pxafb_mode_info e400_pxafb_mode_info = { + .pixclock = 140703, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 4, + .left_margin = 28, + .right_margin = 8, + .vsync_len = 3, + .upper_margin = 5, + .lower_margin = 6, + .sync = 0, +}; + +static struct pxafb_mach_info e400_pxafb_mach_info = { + .modes = &e400_pxafb_mode_info, + .num_modes = 1, + .lcd_conn = LCD_COLOR_TFT_16BPP, + .lccr3 = 0, + .pxafb_backlight_power = NULL, +}; + +/* ------------------------ E400 MFP config ----------------------------- */ + +static unsigned long e400_pin_config[] __initdata = { + /* Chip selects */ + GPIO15_nCS_1, /* CS1 - Flash */ + GPIO80_nCS_4, /* CS4 - TMIO */ + + /* Clocks */ + GPIO12_32KHz, + + /* BTUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + + /* TMIO controller */ + GPIO19_GPIO, /* t7l66xb #PCLR */ + GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ + + /* wakeup */ + GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, +}; + +/* ---------------------------------------------------------------------- */ + +static struct mtd_partition partition_a = { + .name = "Internal NAND flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, +}; + +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr e400_t7l66xb_nand_bbt = { + .options = 0, + .offs = 4, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct tmio_nand_data e400_t7l66xb_nand_config = { + .num_partitions = 1, + .partition = &partition_a, + .badblock_pattern = &e400_t7l66xb_nand_bbt, +}; + +static struct t7l66xb_platform_data e400_t7l66xb_info = { + .irq_base = IRQ_BOARD_START, + .enable = &eseries_tmio_enable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, + + .nand_data = &e400_t7l66xb_nand_config, +}; + +static struct platform_device e400_t7l66xb_device = { + .name = "t7l66xb", + .id = -1, + .dev = { + .platform_data = &e400_t7l66xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ---------------------------------------------------------- */ + +static struct platform_device *e400_devices[] __initdata = { + &e400_t7l66xb_device, +}; + +static void __init e400_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + /* Fixme - e400 may have a switched clock */ + eseries_register_clks(); + eseries_get_tmio_gpios(); + set_pxa_fb_info(&e400_pxafb_mach_info); + platform_add_devices(ARRAY_AND_SIZE(e400_devices)); + pxa_set_udc_info(&e7xx_udc_mach_info); +} + +MACHINE_START(E400, "Toshiba e400") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .init_machine = e400_init, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E740 +/* ------------------------ e740 video support --------------------------- */ + +static struct w100_gen_regs e740_lcd_regs = { + .lcd_format = 0x00008023, + .lcdd_cntl1 = 0x0f000000, + .lcdd_cntl2 = 0x0003ffff, + .genlcd_cntl1 = 0x00ffff03, + .genlcd_cntl2 = 0x003c0f03, + .genlcd_cntl3 = 0x000143aa, +}; + +static struct w100_mode e740_lcd_mode = { + .xres = 240, + .yres = 320, + .left_margin = 20, + .right_margin = 28, + .upper_margin = 9, + .lower_margin = 8, + .crtc_ss = 0x80140013, + .crtc_ls = 0x81150110, + .crtc_gs = 0x80050005, + .crtc_vpos_gs = 0x000a0009, + .crtc_rev = 0x0040010a, + .crtc_dclk = 0xa906000a, + .crtc_gclk = 0x80050108, + .crtc_goe = 0x80050108, + .pll_freq = 57, + .pixclk_divider = 4, + .pixclk_divider_rotated = 4, + .pixclk_src = CLK_SRC_XTAL, + .sysclk_divider = 1, + .sysclk_src = CLK_SRC_PLL, + .crtc_ps1_active = 0x41060010, +}; + +static struct w100_gpio_regs e740_w100_gpio_info = { + .init_data1 = 0x21002103, + .gpio_dir1 = 0xffffdeff, + .gpio_oe1 = 0x03c00643, + .init_data2 = 0x003f003f, + .gpio_dir2 = 0xffffffff, + .gpio_oe2 = 0x000000ff, +}; + +static struct w100fb_mach_info e740_fb_info = { + .modelist = &e740_lcd_mode, + .num_modes = 1, + .regs = &e740_lcd_regs, + .gpio = &e740_w100_gpio_info, + .xtal_freq = 14318000, + .xtal_dbl = 1, +}; + +static struct resource e740_fb_resources[] = { + [0] = { + .start = 0x0c000000, + .end = 0x0cffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device e740_fb_device = { + .name = "w100fb", + .id = -1, + .dev = { + .platform_data = &e740_fb_info, + }, + .num_resources = ARRAY_SIZE(e740_fb_resources), + .resource = e740_fb_resources, +}; + +/* --------------------------- MFP Pin config -------------------------- */ + +static unsigned long e740_pin_config[] __initdata = { + /* Chip selects */ + GPIO15_nCS_1, /* CS1 - Flash */ + GPIO79_nCS_3, /* CS3 - IMAGEON */ + GPIO80_nCS_4, /* CS4 - TMIO */ + + /* Clocks */ + GPIO12_32KHz, + + /* BTUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + + /* TMIO controller */ + GPIO19_GPIO, /* t7l66xb #PCLR */ + GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ + + /* UDC */ + GPIO13_GPIO, + GPIO3_GPIO, + + /* IrDA */ + GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + + /* Audio power control */ + GPIO16_GPIO, /* AC97 codec AVDD2 supply (analogue power) */ + GPIO40_GPIO, /* Mic amp power */ + GPIO41_GPIO, /* Headphone amp power */ + + /* PC Card */ + GPIO8_GPIO, /* CD0 */ + GPIO44_GPIO, /* CD1 */ + GPIO11_GPIO, /* IRQ0 */ + GPIO6_GPIO, /* IRQ1 */ + GPIO27_GPIO, /* RST0 */ + GPIO24_GPIO, /* RST1 */ + GPIO20_GPIO, /* PWR0 */ + GPIO23_GPIO, /* PWR1 */ + GPIO48_nPOE, + GPIO49_nPWE, + GPIO50_nPIOR, + GPIO51_nPIOW, + GPIO52_nPCE_1, + GPIO53_nPCE_2, + GPIO54_nPSKTSEL, + GPIO55_nPREG, + GPIO56_nPWAIT, + GPIO57_nIOIS16, + + /* wakeup */ + GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, +}; + +/* -------------------- e740 t7l66xb parameters -------------------- */ + +static struct t7l66xb_platform_data e740_t7l66xb_info = { + .irq_base = IRQ_BOARD_START, + .enable = &eseries_tmio_enable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, +}; + +static struct platform_device e740_t7l66xb_device = { + .name = "t7l66xb", + .id = -1, + .dev = { + .platform_data = &e740_t7l66xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ----------------------------------------------------------------------- */ + +static struct platform_device *e740_devices[] __initdata = { + &e740_fb_device, + &e740_t7l66xb_device, +}; + +static void __init e740_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + eseries_register_clks(); + clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, + "UDCCLK", &pxa25x_device_udc.dev), + eseries_get_tmio_gpios(); + platform_add_devices(ARRAY_AND_SIZE(e740_devices)); + pxa_set_udc_info(&e7xx_udc_mach_info); + pxa_set_ac97_info(NULL); + pxa_set_ficp_info(&e7xx_ficp_platform_data); +} + +MACHINE_START(E740, "Toshiba e740") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .init_machine = e740_init, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E750 +/* ---------------------- E750 LCD definitions -------------------- */ + +static struct w100_gen_regs e750_lcd_regs = { + .lcd_format = 0x00008003, + .lcdd_cntl1 = 0x00000000, + .lcdd_cntl2 = 0x0003ffff, + .genlcd_cntl1 = 0x00fff003, + .genlcd_cntl2 = 0x003c0f03, + .genlcd_cntl3 = 0x000143aa, +}; + +static struct w100_mode e750_lcd_mode = { + .xres = 240, + .yres = 320, + .left_margin = 21, + .right_margin = 22, + .upper_margin = 5, + .lower_margin = 4, + .crtc_ss = 0x80150014, + .crtc_ls = 0x8014000d, + .crtc_gs = 0xc1000005, + .crtc_vpos_gs = 0x00020147, + .crtc_rev = 0x0040010a, + .crtc_dclk = 0xa1700030, + .crtc_gclk = 0x80cc0015, + .crtc_goe = 0x80cc0015, + .crtc_ps1_active = 0x61060017, + .pll_freq = 57, + .pixclk_divider = 4, + .pixclk_divider_rotated = 4, + .pixclk_src = CLK_SRC_XTAL, + .sysclk_divider = 1, + .sysclk_src = CLK_SRC_PLL, +}; + +static struct w100_gpio_regs e750_w100_gpio_info = { + .init_data1 = 0x01192f1b, + .gpio_dir1 = 0xd5ffdeff, + .gpio_oe1 = 0x000020bf, + .init_data2 = 0x010f010f, + .gpio_dir2 = 0xffffffff, + .gpio_oe2 = 0x000001cf, +}; + +static struct w100fb_mach_info e750_fb_info = { + .modelist = &e750_lcd_mode, + .num_modes = 1, + .regs = &e750_lcd_regs, + .gpio = &e750_w100_gpio_info, + .xtal_freq = 14318000, + .xtal_dbl = 1, +}; + +static struct resource e750_fb_resources[] = { + [0] = { + .start = 0x0c000000, + .end = 0x0cffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device e750_fb_device = { + .name = "w100fb", + .id = -1, + .dev = { + .platform_data = &e750_fb_info, + }, + .num_resources = ARRAY_SIZE(e750_fb_resources), + .resource = e750_fb_resources, +}; + +/* -------------------- e750 MFP parameters -------------------- */ + +static unsigned long e750_pin_config[] __initdata = { + /* Chip selects */ + GPIO15_nCS_1, /* CS1 - Flash */ + GPIO79_nCS_3, /* CS3 - IMAGEON */ + GPIO80_nCS_4, /* CS4 - TMIO */ + + /* Clocks */ + GPIO11_3_6MHz, + + /* BTUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + + /* TMIO controller */ + GPIO19_GPIO, /* t7l66xb #PCLR */ + GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ + + /* UDC */ + GPIO13_GPIO, + GPIO3_GPIO, + + /* IrDA */ + GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + + /* Audio power control */ + GPIO4_GPIO, /* Headphone amp power */ + GPIO7_GPIO, /* Speaker amp power */ + GPIO37_GPIO, /* Headphone detect */ + + /* PC Card */ + GPIO8_GPIO, /* CD0 */ + GPIO44_GPIO, /* CD1 */ + GPIO11_GPIO, /* IRQ0 */ + GPIO6_GPIO, /* IRQ1 */ + GPIO27_GPIO, /* RST0 */ + GPIO24_GPIO, /* RST1 */ + GPIO20_GPIO, /* PWR0 */ + GPIO23_GPIO, /* PWR1 */ + GPIO48_nPOE, + GPIO49_nPWE, + GPIO50_nPIOR, + GPIO51_nPIOW, + GPIO52_nPCE_1, + GPIO53_nPCE_2, + GPIO54_nPSKTSEL, + GPIO55_nPREG, + GPIO56_nPWAIT, + GPIO57_nIOIS16, + + /* wakeup */ + GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, +}; + +/* ----------------- e750 tc6393xb parameters ------------------ */ + +static struct tc6393xb_platform_data e750_tc6393xb_info = { + .irq_base = IRQ_BOARD_START, + .scr_pll2cr = 0x0cc1, + .scr_gper = 0, + .gpio_base = -1, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, + .enable = &eseries_tmio_enable, + .disable = &eseries_tmio_disable, +}; + +static struct platform_device e750_tc6393xb_device = { + .name = "tc6393xb", + .id = -1, + .dev = { + .platform_data = &e750_tc6393xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ------------------------------------------------------------- */ + +static struct platform_device *e750_devices[] __initdata = { + &e750_fb_device, + &e750_tc6393xb_device, +}; + +static void __init e750_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, + "GPIO11_CLK", NULL), + eseries_get_tmio_gpios(); + platform_add_devices(ARRAY_AND_SIZE(e750_devices)); + pxa_set_udc_info(&e7xx_udc_mach_info); + pxa_set_ac97_info(NULL); + pxa_set_ficp_info(&e7xx_ficp_platform_data); +} + +MACHINE_START(E750, "Toshiba e750") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .init_machine = e750_init, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_E800 +/* ------------------------ e800 LCD definitions ------------------------- */ + +static unsigned long e800_pin_config[] __initdata = { + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, +}; + +static struct w100_gen_regs e800_lcd_regs = { + .lcd_format = 0x00008003, + .lcdd_cntl1 = 0x02a00000, + .lcdd_cntl2 = 0x0003ffff, + .genlcd_cntl1 = 0x000ff2a3, + .genlcd_cntl2 = 0x000002a3, + .genlcd_cntl3 = 0x000102aa, +}; + +static struct w100_mode e800_lcd_mode[2] = { + [0] = { + .xres = 480, + .yres = 640, + .left_margin = 52, + .right_margin = 148, + .upper_margin = 2, + .lower_margin = 6, + .crtc_ss = 0x80350034, + .crtc_ls = 0x802b0026, + .crtc_gs = 0x80160016, + .crtc_vpos_gs = 0x00020003, + .crtc_rev = 0x0040001d, + .crtc_dclk = 0xe0000000, + .crtc_gclk = 0x82a50049, + .crtc_goe = 0x80ee001c, + .crtc_ps1_active = 0x00000000, + .pll_freq = 128, + .pixclk_divider = 4, + .pixclk_divider_rotated = 6, + .pixclk_src = CLK_SRC_PLL, + .sysclk_divider = 0, + .sysclk_src = CLK_SRC_PLL, + }, + [1] = { + .xres = 240, + .yres = 320, + .left_margin = 15, + .right_margin = 88, + .upper_margin = 0, + .lower_margin = 7, + .crtc_ss = 0xd010000f, + .crtc_ls = 0x80070003, + .crtc_gs = 0x80000000, + .crtc_vpos_gs = 0x01460147, + .crtc_rev = 0x00400003, + .crtc_dclk = 0xa1700030, + .crtc_gclk = 0x814b0008, + .crtc_goe = 0x80cc0015, + .crtc_ps1_active = 0x00000000, + .pll_freq = 100, + .pixclk_divider = 6, /* Wince uses 14 which gives a */ + .pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */ + .pixclk_src = CLK_SRC_PLL, + .sysclk_divider = 0, + .sysclk_src = CLK_SRC_PLL, + } +}; + + +static struct w100_gpio_regs e800_w100_gpio_info = { + .init_data1 = 0xc13fc019, + .gpio_dir1 = 0x3e40df7f, + .gpio_oe1 = 0x003c3000, + .init_data2 = 0x00000000, + .gpio_dir2 = 0x00000000, + .gpio_oe2 = 0x00000000, +}; + +static struct w100_mem_info e800_w100_mem_info = { + .ext_cntl = 0x09640011, + .sdram_mode_reg = 0x00600021, + .ext_timing_cntl = 0x10001545, + .io_cntl = 0x7ddd7333, + .size = 0x1fffff, +}; + +static void e800_tg_change(struct w100fb_par *par) +{ + unsigned long tmp; + + tmp = w100fb_gpio_read(W100_GPIO_PORT_A); + if (par->mode->xres == 480) + tmp |= 0x100; + else + tmp &= ~0x100; + w100fb_gpio_write(W100_GPIO_PORT_A, tmp); +} + +static struct w100_tg_info e800_tg_info = { + .change = e800_tg_change, +}; + +static struct w100fb_mach_info e800_fb_info = { + .modelist = e800_lcd_mode, + .num_modes = 2, + .regs = &e800_lcd_regs, + .gpio = &e800_w100_gpio_info, + .mem = &e800_w100_mem_info, + .tg = &e800_tg_info, + .xtal_freq = 16000000, +}; + +static struct resource e800_fb_resources[] = { + [0] = { + .start = 0x0c000000, + .end = 0x0cffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device e800_fb_device = { + .name = "w100fb", + .id = -1, + .dev = { + .platform_data = &e800_fb_info, + }, + .num_resources = ARRAY_SIZE(e800_fb_resources), + .resource = e800_fb_resources, +}; + +/* --------------------------- UDC definitions --------------------------- */ + +static struct pxa2xx_udc_mach_info e800_udc_mach_info = { + .gpio_vbus = GPIO_E800_USB_DISC, + .gpio_pullup = GPIO_E800_USB_PULLUP, + .gpio_pullup_inverted = 1 +}; + +/* ----------------- e800 tc6393xb parameters ------------------ */ + +static struct tc6393xb_platform_data e800_tc6393xb_info = { + .irq_base = IRQ_BOARD_START, + .scr_pll2cr = 0x0cc1, + .scr_gper = 0, + .gpio_base = -1, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, + .enable = &eseries_tmio_enable, + .disable = &eseries_tmio_disable, +}; + +static struct platform_device e800_tc6393xb_device = { + .name = "tc6393xb", + .id = -1, + .dev = { + .platform_data = &e800_tc6393xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ----------------------------------------------------------------------- */ + +static struct platform_device *e800_devices[] __initdata = { + &e800_fb_device, + &e800_tc6393xb_device, +}; + +static void __init e800_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, + "GPIO11_CLK", NULL), + eseries_get_tmio_gpios(); + platform_add_devices(ARRAY_AND_SIZE(e800_devices)); + pxa_set_udc_info(&e800_udc_mach_info); + pxa_set_ac97_info(NULL); +} + +MACHINE_START(E800, "Toshiba e800") + /* Maintainer: Ian Molton (spyro@f2s.com) */ + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .fixup = eseries_fixup, + .init_machine = e800_init, + .timer = &pxa_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c deleted file mode 100644 index 5161dca8ccc..00000000000 --- a/arch/arm/mach-pxa/imote2.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - * linux/arch/arm/mach-pxa/imote2.c - * - * Author: Ed C. Epp - * Created: Nov 05, 2002 - * Copyright: Intel Corp. - * - * Modified 2008: Jonathan Cameron - * - * The Imote2 is a wireless sensor node platform sold - * by Crossbow (www.xbow.com). - */ - -#include <linux/init.h> -#include <linux/device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/regulator/machine.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/spi/spi.h> -#include <linux/i2c.h> -#include <linux/mfd/da903x.h> -#include <linux/sht15.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/flash.h> - -#include <mach/pxa27x.h> -#include <plat/i2c.h> -#include <mach/udc.h> -#include <mach/mmc.h> -#include <mach/pxa2xx_spi.h> -#include <mach/pxa27x-udc.h> - -#include "devices.h" -#include "generic.h" - -static unsigned long imote2_pin_config[] __initdata = { - - /* Device Identification for wakeup*/ - GPIO102_GPIO, - - /* Button */ - GPIO91_GPIO, - - /* DA9030 */ - GPIO1_GPIO, - - /* MMC */ - GPIO32_MMC_CLK, - GPIO112_MMC_CMD, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - - /* 802.15.4 radio - driver out of mainline */ - GPIO22_GPIO, /* CC_RSTN */ - GPIO114_GPIO, /* CC_FIFO */ - GPIO116_GPIO, /* CC_CCA */ - GPIO0_GPIO, /* CC_FIFOP */ - GPIO16_GPIO, /* CCSFD */ - GPIO115_GPIO, /* Power enable */ - - /* I2C */ - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, - - /* SSP 3 - 802.15.4 radio */ - GPIO39_GPIO, /* Chip Select */ - GPIO34_SSP3_SCLK, - GPIO35_SSP3_TXD, - GPIO41_SSP3_RXD, - - /* SSP 2 - to daughter boards */ - GPIO37_GPIO, /* Chip Select */ - GPIO36_SSP2_SCLK, - GPIO38_SSP2_TXD, - GPIO11_SSP2_RXD, - - /* SSP 1 - to daughter boards */ - GPIO24_GPIO, /* Chip Select */ - GPIO23_SSP1_SCLK, - GPIO25_SSP1_TXD, - GPIO26_SSP1_RXD, - - /* BTUART Basic Connector*/ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - GPIO45_BTUART_RTS, - - /* STUART Serial console via debug board*/ - GPIO46_STUART_RXD, - GPIO47_STUART_TXD, - - /* Basic sensor board */ - GPIO96_GPIO, /* accelerometer interrupt */ - GPIO99_GPIO, /* ADC interrupt */ - - /* SHT15 */ - GPIO100_GPIO, - GPIO98_GPIO, - - /* Connector pins specified as gpios */ - GPIO94_GPIO, /* large basic connector pin 14 */ - GPIO10_GPIO, /* large basic connector pin 23 */ - - /* LEDS */ - GPIO103_GPIO, /* red led */ - GPIO104_GPIO, /* green led */ - GPIO105_GPIO, /* blue led */ -}; - -static struct sht15_platform_data platform_data_sht15 = { - .gpio_data = 100, - .gpio_sck = 98, -}; - -static struct platform_device sht15 = { - .name = "sht15", - .id = -1, - .dev = { - .platform_data = &platform_data_sht15, - }, -}; - -static struct regulator_consumer_supply imote2_sensor_3_con[] = { - { - .dev = &sht15.dev, - .supply = "vcc", - }, -}; - -static struct gpio_led imote2_led_pins[] = { - { - .name = "imote2:red", - .gpio = 103, - .active_low = 1, - }, { - .name = "imote2:green", - .gpio = 104, - .active_low = 1, - }, { - .name = "imote2:blue", - .gpio = 105, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data imote2_led_data = { - .num_leds = ARRAY_SIZE(imote2_led_pins), - .leds = imote2_led_pins, -}; - -static struct platform_device imote2_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &imote2_led_data, - }, -}; - -/* Reverse engineered partly from Platformx drivers */ -enum imote2_ldos{ - vcc_vref, - vcc_cc2420, - vcc_mica, - vcc_bt, - /* The two voltages available to sensor boards */ - vcc_sensor_1_8, - vcc_sensor_3, - - vcc_sram_ext, /* directly connected to the pxa271 */ - vcc_pxa_pll, - vcc_pxa_usim, /* Reference voltage for certain gpios */ - vcc_pxa_mem, - vcc_pxa_flash, - vcc_pxa_core, /*Dc-Dc buck not yet supported */ - vcc_lcd, - vcc_bb, - vcc_bbio, - vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/ -}; - -/* The values of the various regulator constraints are obviously dependent - * on exactly what is wired to each ldo. Unfortunately this information is - * not generally available. More information has been requested from Xbow - * but as of yet they haven't been forthcoming. - * - * Some of these are clearly Stargate 2 related (no way of plugging - * in an lcd on the IM2 for example!). - */ -static struct regulator_init_data imote2_ldo_init_data[] = { - [vcc_bbio] = { - .constraints = { /* board default 1.8V */ - .name = "vcc_bbio", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_bb] = { - .constraints = { /* board default 2.8V */ - .name = "vcc_bb", - .min_uV = 2700000, - .max_uV = 3000000, - }, - }, - [vcc_pxa_flash] = { - .constraints = {/* default is 1.8V */ - .name = "vcc_pxa_flash", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_cc2420] = { /* also vcc_io */ - .constraints = { - /* board default is 2.8V */ - .name = "vcc_cc2420", - .min_uV = 2700000, - .max_uV = 3300000, - }, - }, - [vcc_vref] = { /* Reference for what? */ - .constraints = { /* default 1.8V */ - .name = "vcc_vref", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_sram_ext] = { - .constraints = { /* default 2.8V */ - .name = "vcc_sram_ext", - .min_uV = 2800000, - .max_uV = 2800000, - }, - }, - [vcc_mica] = { - .constraints = { /* default 2.8V */ - .name = "vcc_mica", - .min_uV = 2800000, - .max_uV = 2800000, - }, - }, - [vcc_bt] = { - .constraints = { /* default 2.8V */ - .name = "vcc_bt", - .min_uV = 2800000, - .max_uV = 2800000, - }, - }, - [vcc_lcd] = { - .constraints = { /* default 2.8V */ - .name = "vcc_lcd", - .min_uV = 2700000, - .max_uV = 3300000, - }, - }, - [vcc_io] = { /* Same or higher than everything - * bar vccbat and vccusb */ - .constraints = { /* default 2.8V */ - .name = "vcc_io", - .min_uV = 2692000, - .max_uV = 3300000, - }, - }, - [vcc_sensor_1_8] = { - .constraints = { /* default 1.8V */ - .name = "vcc_sensor_1_8", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_sensor_3] = { /* curiously default 2.8V */ - .constraints = { - .name = "vcc_sensor_3", - .min_uV = 2800000, - .max_uV = 3000000, - }, - .num_consumer_supplies = ARRAY_SIZE(imote2_sensor_3_con), - .consumer_supplies = imote2_sensor_3_con, - }, - [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/ - .constraints = { - .name = "vcc_pxa_pll", - .min_uV = 1170000, - .max_uV = 1430000, - }, - }, - [vcc_pxa_usim] = { - .constraints = { /* default 1.8V */ - .name = "vcc_pxa_usim", - .min_uV = 1710000, - .max_uV = 2160000, - }, - }, - [vcc_pxa_mem] = { - .constraints = { /* default 1.8V */ - .name = "vcc_pxa_mem", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, -}; - -static struct da903x_subdev_info imote2_da9030_subdevs[] = { - { - .name = "da903x-regulator", - .id = DA9030_ID_LDO2, - .platform_data = &imote2_ldo_init_data[vcc_bbio], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO3, - .platform_data = &imote2_ldo_init_data[vcc_bb], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO4, - .platform_data = &imote2_ldo_init_data[vcc_pxa_flash], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO5, - .platform_data = &imote2_ldo_init_data[vcc_cc2420], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO6, - .platform_data = &imote2_ldo_init_data[vcc_vref], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO7, - .platform_data = &imote2_ldo_init_data[vcc_sram_ext], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO8, - .platform_data = &imote2_ldo_init_data[vcc_mica], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO9, - .platform_data = &imote2_ldo_init_data[vcc_bt], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO10, - .platform_data = &imote2_ldo_init_data[vcc_sensor_1_8], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO11, - .platform_data = &imote2_ldo_init_data[vcc_sensor_3], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO12, - .platform_data = &imote2_ldo_init_data[vcc_lcd], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO15, - .platform_data = &imote2_ldo_init_data[vcc_pxa_pll], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO17, - .platform_data = &imote2_ldo_init_data[vcc_pxa_usim], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO18, - .platform_data = &imote2_ldo_init_data[vcc_io], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO19, - .platform_data = &imote2_ldo_init_data[vcc_pxa_mem], - }, -}; - -static struct da903x_platform_data imote2_da9030_pdata = { - .num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs), - .subdevs = imote2_da9030_subdevs, -}; - -/* As the the imote2 doesn't currently have a conventional SD slot - * there is no option to hotplug cards, making all this rather simple - */ -static int imote2_mci_get_ro(struct device *dev) -{ - return 0; -} - -/* Rather simple case as hotplugging not possible */ -static struct pxamci_platform_data imote2_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */ - .get_ro = imote2_mci_get_ro, - .gpio_card_detect = -1, - .gpio_card_ro = -1, - .gpio_power = -1, -}; - -static struct mtd_partition imote2flash_partitions[] = { - { - .name = "Bootloader", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0x00040000, - .mask_flags = 0, - }, { - .name = "Filesystem", - .size = 0x01DC0000, - .offset = 0x00240000, - .mask_flags = 0, - }, -}; - -static struct resource flash_resources = { - .start = PXA_CS0_PHYS, - .end = PXA_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct flash_platform_data imote2_flash_data = { - .map_name = "cfi_probe", - .parts = imote2flash_partitions, - .nr_parts = ARRAY_SIZE(imote2flash_partitions), - .name = "PXA27xOnChipROM", - .width = 2, -}; - -static struct platform_device imote2_flash_device = { - .name = "pxa2xx-flash", - .id = 0, - .dev = { - .platform_data = &imote2_flash_data, - }, - .resource = &flash_resources, - .num_resources = 1, -}; - -/* Some of the drivers here are out of kernel at the moment (parts of IIO) - * and it may be a while before they are in the mainline. - */ -static struct i2c_board_info __initdata imote2_i2c_board_info[] = { - { /* UCAM sensor board */ - .type = "max1239", - .addr = 0x35, - }, { /* ITS400 Sensor board only */ - .type = "max1363", - .addr = 0x34, - /* Through a nand gate - Also beware, on V2 sensor board the - * pull up resistors are missing. - */ - .irq = IRQ_GPIO(99), - }, { /* ITS400 Sensor board only */ - .type = "tsl2561", - .addr = 0x49, - /* Through a nand gate - Also beware, on V2 sensor board the - * pull up resistors are missing. - */ - .irq = IRQ_GPIO(99), - }, { /* ITS400 Sensor board only */ - .type = "tmp175", - .addr = 0x4A, - .irq = IRQ_GPIO(96), - }, { /* IMB400 Multimedia board */ - .type = "wm8940", - .addr = 0x1A, - }, -}; - -static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { - { - .type = "da9030", - .addr = 0x49, - .platform_data = &imote2_da9030_pdata, - .irq = gpio_to_irq(1), - }, -}; - -static struct pxa2xx_spi_master pxa_ssp_master_0_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_master pxa_ssp_master_1_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_master pxa_ssp_master_2_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_chip staccel_chip_info = { - .tx_threshold = 8, - .rx_threshold = 8, - .dma_burst_size = 8, - .timeout = 235, - .gpio_cs = 24, -}; - -static struct pxa2xx_spi_chip cc2420_info = { - .tx_threshold = 8, - .rx_threshold = 8, - .dma_burst_size = 8, - .timeout = 235, - .gpio_cs = 39, -}; - -static struct spi_board_info spi_board_info[] __initdata = { - { /* Driver in IIO */ - .modalias = "lis3l02dq", - .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */ - .bus_num = 1, - .chip_select = 0, - .controller_data = &staccel_chip_info, - .irq = IRQ_GPIO(96), - }, { /* Driver out of kernel as it needs considerable rewriting */ - .modalias = "cc2420", - .max_speed_hz = 6500000, - .bus_num = 3, - .chip_select = 0, - .controller_data = &cc2420_info, - }, -}; - -static void im2_udc_command(int cmd) -{ - switch (cmd) { - case PXA2XX_UDC_CMD_CONNECT: - UP2OCR |= UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE; - break; - case PXA2XX_UDC_CMD_DISCONNECT: - UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE); - break; - } -} - -static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = { - .udc_command = im2_udc_command, -}; - -static struct platform_device *imote2_devices[] = { - &imote2_flash_device, - &imote2_leds, - &sht15, -}; - -static struct i2c_pxa_platform_data i2c_pwr_pdata = { - .fast_mode = 1, -}; - -static struct i2c_pxa_platform_data i2c_pdata = { - .fast_mode = 1, -}; - -static void __init imote2_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); - - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - - platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices)); - - pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info); - pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info); - pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info); - - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - - i2c_register_board_info(0, imote2_i2c_board_info, - ARRAY_SIZE(imote2_i2c_board_info)); - i2c_register_board_info(1, imote2_pwr_i2c_board_info, - ARRAY_SIZE(imote2_pwr_i2c_board_info)); - - pxa27x_set_i2c_power_info(&i2c_pwr_pdata); - pxa_set_i2c_info(&i2c_pdata); - - pxa_set_mci_info(&imote2_mci_platform_data); - pxa_set_udc_info(&imote2_udc_info); -} - -MACHINE_START(INTELMOTE2, "IMOTE 2") - .phys_io = 0x40000000, - .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .map_io = pxa_map_io, - .init_irq = pxa27x_init_irq, - .timer = &pxa_timer, - .init_machine = imote2_init, - .boot_params = 0xA0000100, -MACHINE_END diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index 1a741065045..eec92e6fd7c 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -26,21 +26,55 @@ enum balloon3_features { #define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ #define BALLOON3_FPGA_LENGTH 0x01000000 -/* FPGA/CPLD registers */ -#define BALLOON3_PCMCIA0_REG (BALLOON3_FPGA_VIRT + 0x00e00008) -/* fixme - same for now */ -#define BALLOON3_PCMCIA1_REG (BALLOON3_FPGA_VIRT + 0x00e00008) -#define BALLOON3_NANDIO_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) +/* FPGA / CPLD registers for CF socket */ +#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) +/* FPGA / CPLD version register */ +#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c) +/* FPGA / CPLD registers for NAND flash */ +#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) +#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) +#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) +#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00010) +#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) + /* fpga/cpld interrupt control register */ #define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C) -#define BALLOON3_NANDIO_CTL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) -#define BALLOON3_NANDIO_CTL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) #define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c) #define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000) #define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004) #define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c) +/* CF Status Register bits (read-only) bits */ +#define BALLOON3_CF_nIRQ (1 << 0) +#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1) + +/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */ +#define BALLOON3_CF_RESET (1 << 0) +#define BALLOON3_CF_ENABLE (1 << 1) +#define BALLOON3_CF_ADD_ENABLE (1 << 2) + +/* CF Interrupt sources */ +#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) +#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) + +/* NAND Control register */ +#define BALLOON3_NAND_CONTROL_FLWP (1 << 7) +#define BALLOON3_NAND_CONTROL_FLSE (1 << 6) +#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5) +#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4) +#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3) +#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2) +#define BALLOON3_NAND_CONTROL_FLALE (1 << 1) +#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0) + +/* NAND Status register */ +#define BALLOON3_NAND_STAT_RNB (1 << 0) + +/* NAND Control2 register */ +#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0) + /* GPIOs for irqs */ #define BALLOON3_GPIO_AUX_NIRQ (94) #define BALLOON3_GPIO_CODEC_IRQ (95) @@ -54,20 +88,24 @@ enum balloon3_features { #define BALLOON3_GPIO_S0_CD (105) +/* NAND */ +#define BALLOON3_GPIO_RUN_NAND (102) + +/* PCF8574A Leds */ +#define BALLOON3_PCF_GPIO_BASE 160 +#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0) +#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1) +#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2) +#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3) +#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4) +#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5) +#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6) +#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7) + /* FPGA Interrupt Mask/Acknowledge Register */ #define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */ #define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */ -/* CF Status Register */ -#define BALLOON3_PCMCIA_nIRQ (1 << 0) /* IRQ / ready signal */ -#define BALLOON3_PCMCIA_nSTSCHG_BVD1 (1 << 1) - /* VDD sense / card status changed */ - -/* CF control register (write) */ -#define BALLOON3_PCMCIA_RESET (1 << 0) /* Card reset signal */ -#define BALLOON3_PCMCIA_ENABLE (1 << 1) -#define BALLOON3_PCMCIA_ADD_ENABLE (1 << 2) - /* CPLD (and FPGA) interface definitions */ #define CPLD_LCD0_DATA_SET 0x00 #define CPLD_LCD0_DATA_CLR 0x10 @@ -132,9 +170,6 @@ enum balloon3_features { /* Balloon3 Interrupts */ #define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) -#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) -#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) - #define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) #define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) #define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index 5f2ba8d9015..58dada11054 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h @@ -5,6 +5,27 @@ #include <mach/mfp.h> /* + * base board glue for PXA270 module + */ + +enum { + COLIBRI_PXA270_EVALBOARD = 0, + COLIBRI_PXA270_INCOME, +}; + +#if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) +extern void colibri_pxa270_evalboard_init(void); +#else +static inline void colibri_pxa270_evalboard_init(void) {} +#endif + +#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) +extern void colibri_pxa270_income_boardinit(void); +#else +static inline void colibri_pxa270_income_boardinit(void) {} +#endif + +/* * common settings for all modules */ @@ -33,13 +54,10 @@ static inline void colibri_pxa3xx_init_nand(void) {} /* physical memory regions */ #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ -/* definitions for Colibri PXA270 */ - -#define COLIBRI_PXA270_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ -#define COLIBRI_PXA270_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet */ -#define COLIBRI_PXA270_ETH_IRQ_GPIO 114 -#define COLIBRI_PXA270_ETH_IRQ \ - gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO)) +/* GPIO definitions for Colibri PXA270 */ +#define GPIO114_COLIBRI_PXA270_ETH_IRQ 114 +#define GPIO0_COLIBRI_PXA270_SD_DETECT 0 +#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 #endif /* _COLIBRI_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h index 585970ef08c..0011055bc3f 100644 --- a/arch/arm/mach-pxa/include/mach/corgi.h +++ b/arch/arm/mach-pxa/include/mach/corgi.h @@ -109,10 +109,5 @@ #define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7) #define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8) -/* - * Shared data structures - */ -extern struct platform_device corgiscoop_device; - #endif /* __ASM_ARCH_CORGI_H */ diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 06abd416060..9b898680b20 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h @@ -14,25 +14,15 @@ /* GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean -interrupt signal for determining cable presence. On the original gumstix, -this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F, +interrupt signal for determining cable presence. On the gumstix F, this moves to GPIO17 and GPIO37. */ /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn has detected a cable insertion; driven low otherwise. */ -#ifdef CONFIG_ARCH_GUMSTIX_ORIG - -#define GPIO_GUMSTIX_USB_GPIOn 81 -#define GPIO_GUMSTIX_USB_GPIOx 83 - -#else - #define GPIO_GUMSTIX_USB_GPIOn 35 #define GPIO_GUMSTIX_USB_GPIOx 41 -#endif - /* usb state change */ #define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index 3d8d8cb0968..7f64d24cd56 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -14,11 +14,6 @@ #define __ASM_ARCH_HARDWARE_H /* - * We requires absolute addresses. - */ -#define PCIO_BASE 0 - -/* * Workarounds for at least 2 errata so far require this. * The mapping is set in mach-pxa/generic.c. */ diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h new file mode 100644 index 00000000000..0a5e5eadebf --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palm27x.h @@ -0,0 +1,81 @@ +/* + * Common functions for Palm LD, T5, TX, Z72 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __INCLUDE_MACH_PALM27X__ +#define __INCLUDE_MACH_PALM27X__ + +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +extern void __init palm27x_mmc_init(int detect, int ro, int power, + int power_inverted); +#else +static inline void palm27x_mmc_init(int detect, int ro, int power, + int power_inverted) +{} +#endif + +#if defined(CONFIG_SUSPEND) +extern void __init palm27x_pm_init(unsigned long str_base); +#else +static inline void palm27x_pm_init(unsigned long str_base) {} +#endif + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +extern struct pxafb_mode_info palm_320x480_lcd_mode; +extern struct pxafb_mode_info palm_320x320_lcd_mode; +extern struct pxafb_mode_info palm_320x320_new_lcd_mode; +extern void __init palm27x_lcd_init(int power, + struct pxafb_mode_info *mode); +#else +static inline void palm27x_lcd_init(int power, struct pxafb_mode_info *mode) {} +#endif + +#if defined(CONFIG_USB_GADGET_PXA27X) || \ + defined(CONFIG_USB_GADGET_PXA27X_MODULE) +extern void __init palm27x_udc_init(int vbus, int pullup, + int vbus_inverted); +#else +static inline void palm27x_udc_init(int vbus, int pullup, int vbus_inverted) {} +#endif + +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) +extern void __init palm27x_irda_init(int pwdn); +#else +static inline void palm27x_irda_init(int pwdn) {} +#endif + +#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \ + defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE) +extern void __init palm27x_ac97_init(int minv, int maxv, int jack, + int reset); +#else +static inline void palm27x_ac97_init(int minv, int maxv, int jack, int reset) {} +#endif + +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +extern void __init palm27x_pwm_init(int bl, int lcd); +#else +static inline void palm27x_pwm_init(int bl, int lcd) {} +#endif + +#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE) +extern void __init palm27x_power_init(int ac, int usb); +#else +static inline void palm27x_power_init(int ac, int usb) {} +#endif + +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +extern void __init palm27x_pmic_init(void); +#else +static inline void palm27x_pmic_init(void) {} +#endif + +#endif /* __INCLUDE_MACH_PALM27X__ */ diff --git a/arch/arm/mach-pxa/include/mach/pata_pxa.h b/arch/arm/mach-pxa/include/mach/pata_pxa.h new file mode 100644 index 00000000000..6cf7df1d583 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pata_pxa.h @@ -0,0 +1,33 @@ +/* + * Generic PXA PATA driver + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MACH_PATA_PXA_H__ +#define __MACH_PATA_PXA_H__ + +struct pata_pxa_pdata { + /* PXA DMA DREQ<0:2> pin */ + uint32_t dma_dreq; + /* Register shift */ + uint32_t reg_shift; + /* IRQ flags */ + uint32_t irq_flags; +}; + +#endif /* __MACH_PATA_PXA_H__ */ diff --git a/arch/arm/mach-pxa/include/mach/sharpsl.h b/arch/arm/mach-pxa/include/mach/sharpsl.h deleted file mode 100644 index 8242e14a44f..00000000000 --- a/arch/arm/mach-pxa/include/mach/sharpsl.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SharpSL SSP Driver - */ - -unsigned long corgi_ssp_ads7846_putget(unsigned long); -unsigned long corgi_ssp_ads7846_get(void); -void corgi_ssp_ads7846_put(unsigned long data); -void corgi_ssp_ads7846_lock(void); -void corgi_ssp_ads7846_unlock(void); -void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data); -void corgi_ssp_blduty_set(int duty); -int corgi_ssp_max1111_get(unsigned long data); - -/* - * SharpSL Touchscreen Driver - */ - -struct corgits_machinfo { - unsigned long (*get_hsync_invperiod)(void); - void (*put_hsync)(void); - void (*wait_hsync)(void); -}; - - -/* - * SharpSL Backlight - */ -extern void corgibl_limit_intensity(int limit); -extern void corgi_lcd_limit_intensity(int limit); - - -/* - * SharpSL Battery/PM Driver - */ -extern void sharpsl_battery_kick(void); diff --git a/arch/arm/mach-pxa/include/mach/sharpsl_pm.h b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h index 1920dc6b05d..905be6755f0 100644 --- a/arch/arm/mach-pxa/include/mach/sharpsl_pm.h +++ b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h @@ -93,6 +93,8 @@ struct sharpsl_pm_status { extern struct sharpsl_pm_status sharpsl_pm; +extern struct battery_thresh sharpsl_battery_levels_acin[]; +extern struct battery_thresh sharpsl_battery_levels_noac[]; #define SHARPSL_LED_ERROR 2 #define SHARPSL_LED_ON 1 @@ -101,4 +103,11 @@ extern struct sharpsl_pm_status sharpsl_pm; void sharpsl_battery_kick(void); void sharpsl_pm_led(int val); +/* MAX1111 Channel Definitions */ +#define MAX1111_BATT_VOLT 4u +#define MAX1111_BATT_TEMP 2u +#define MAX1111_ACIN_VOLT 6u +int sharpsl_pm_pxa_read_max1111(int channel); + +void corgi_lcd_limit_intensity(int limit); #endif diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h index fa1998caa78..685749a51c4 100644 --- a/arch/arm/mach-pxa/include/mach/spitz.h +++ b/arch/arm/mach-pxa/include/mach/spitz.h @@ -185,7 +185,5 @@ /* * Shared data structures */ -extern struct platform_device spitzscoop_device; -extern struct platform_device spitzscoop2_device; extern struct platform_device spitzssp_device; extern struct sharpsl_charger_machinfo spitz_pm_machinfo; diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index fa6a708b409..dc66942ef9a 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -34,7 +34,7 @@ #include <linux/irq.h> #include <linux/pda_power.h> #include <linux/power_supply.h> -#include <linux/wm97xx_batt.h> +#include <linux/wm97xx.h> #include <linux/mtd/physmap.h> #include <linux/usb/gpio_vbus.h> #include <linux/regulator/max1586.h> @@ -636,7 +636,7 @@ static struct platform_device power_dev = { }, }; -static struct wm97xx_batt_info mioa701_battery_data = { +static struct wm97xx_batt_pdata mioa701_battery_data = { .batt_aux = WM97XX_AUX_ID1, .temp_aux = -1, .charge_gpio = -1, @@ -648,6 +648,10 @@ static struct wm97xx_batt_info mioa701_battery_data = { .batt_name = "mioa701_battery", }; +static struct wm97xx_pdata mioa701_wm97xx_pdata = { + .batt_pdata = &mioa701_battery_data, +}; + /* * Voltage regulation */ @@ -716,6 +720,7 @@ struct i2c_pxa_platform_data i2c_pdata = { static pxa2xx_audio_ops_t mioa701_ac97_info = { .reset_gpio = 95, + .codec_pdata = { &mioa701_wm97xx_pdata, }, }; /* @@ -794,7 +799,6 @@ static void __init mioa701_machine_init(void) set_pxa_fb_info(&mioa701_pxafb_info); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); - wm97xx_bat_set_pdata(&mioa701_battery_data); pxa_set_udc_info(&mioa701_udc_info); pxa_set_ac97_info(&mioa701_ac97_info); pm_power_off = mioa701_poweroff; diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c new file mode 100644 index 00000000000..77ad6d34ab5 --- /dev/null +++ b/arch/arm/mach-pxa/palm27x.c @@ -0,0 +1,477 @@ +/* + * Common code for Palm LD, T5, TX, Z72 + * + * Copyright (C) 2010 + * Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/pda_power.h> +#include <linux/pwm_backlight.h> +#include <linux/gpio.h> +#include <linux/wm97xx.h> +#include <linux/power_supply.h> +#include <linux/usb/gpio_vbus.h> +#include <linux/regulator/max1586.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/pxa27x.h> +#include <mach/audio.h> +#include <mach/mmc.h> +#include <mach/pxafb.h> +#include <mach/irda.h> +#include <mach/udc.h> +#include <mach/palmasoc.h> +#include <mach/palm27x.h> + +#include <plat/i2c.h> + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +static struct pxamci_platform_data palm27x_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .detect_delay_ms = 200, +}; + +void __init palm27x_mmc_init(int detect, int ro, int power, + int power_inverted) +{ + palm27x_mci_platform_data.gpio_card_detect = detect; + palm27x_mci_platform_data.gpio_card_ro = ro; + palm27x_mci_platform_data.gpio_power = power; + palm27x_mci_platform_data.gpio_power_invert = power_inverted; + + pxa_set_mci_info(&palm27x_mci_platform_data); +} +#endif + +/****************************************************************************** + * Power management - standby + ******************************************************************************/ +#if defined(CONFIG_SUSPEND) +void __init palm27x_pm_init(unsigned long str_base) +{ + static const unsigned long resume[] = { + 0xe3a00101, /* mov r0, #0x40000000 */ + 0xe380060f, /* orr r0, r0, #0x00f00000 */ + 0xe590f008, /* ldr pc, [r0, #0x08] */ + }; + + /* + * Copy the bootloader. + * NOTE: PalmZ72 uses a different wakeup method! + */ + memcpy(phys_to_virt(str_base), resume, sizeof(resume)); +} +#endif + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +struct pxafb_mode_info palm_320x480_lcd_mode = { + .pixclock = 57692, + .xres = 320, + .yres = 480, + .bpp = 16, + + .left_margin = 32, + .right_margin = 1, + .upper_margin = 7, + .lower_margin = 1, + + .hsync_len = 4, + .vsync_len = 1, +}; + +struct pxafb_mode_info palm_320x320_lcd_mode = { + .pixclock = 115384, + .xres = 320, + .yres = 320, + .bpp = 16, + + .left_margin = 27, + .right_margin = 7, + .upper_margin = 7, + .lower_margin = 8, + + .hsync_len = 6, + .vsync_len = 1, +}; + +struct pxafb_mode_info palm_320x320_new_lcd_mode = { + .pixclock = 86538, + .xres = 320, + .yres = 320, + .bpp = 16, + + .left_margin = 20, + .right_margin = 8, + .upper_margin = 8, + .lower_margin = 5, + + .hsync_len = 4, + .vsync_len = 1, +}; + +static struct pxafb_mach_info palm27x_lcd_screen = { + .num_modes = 1, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +static int palm27x_lcd_power; +static void palm27x_lcd_ctl(int on, struct fb_var_screeninfo *info) +{ + gpio_set_value(palm27x_lcd_power, on); +} + +void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode) +{ + palm27x_lcd_screen.modes = mode; + + if (gpio_is_valid(power)) { + if (!gpio_request(power, "LCD power")) { + pr_err("Palm27x: failed to claim lcd power gpio!\n"); + return; + } + if (!gpio_direction_output(power, 1)) { + pr_err("Palm27x: lcd power configuration failed!\n"); + return; + } + palm27x_lcd_power = power; + palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl; + } + + set_pxa_fb_info(&palm27x_lcd_screen); +} +#endif + +/****************************************************************************** + * USB Gadget + ******************************************************************************/ +#if defined(CONFIG_USB_GADGET_PXA27X) || \ + defined(CONFIG_USB_GADGET_PXA27X_MODULE) +static struct gpio_vbus_mach_info palm27x_udc_info = { + .gpio_vbus_inverted = 1, +}; + +static struct platform_device palm27x_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palm27x_udc_info, + }, +}; + +void __init palm27x_udc_init(int vbus, int pullup, int vbus_inverted) +{ + palm27x_udc_info.gpio_vbus = vbus; + palm27x_udc_info.gpio_pullup = pullup; + + palm27x_udc_info.gpio_vbus_inverted = vbus_inverted; + + if (!gpio_request(pullup, "USB Pullup")) { + gpio_direction_output(pullup, + palm27x_udc_info.gpio_vbus_inverted); + gpio_free(pullup); + } else + return; + + platform_device_register(&palm27x_gpio_vbus); +} +#endif + +/****************************************************************************** + * IrDA + ******************************************************************************/ +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) +static struct pxaficp_platform_data palm27x_ficp_platform_data = { + .transceiver_cap = IR_SIRMODE | IR_OFF, +}; + +void __init palm27x_irda_init(int pwdn) +{ + palm27x_ficp_platform_data.gpio_pwdown = pwdn; + pxa_set_ficp_info(&palm27x_ficp_platform_data); +} +#endif + +/****************************************************************************** + * WM97xx audio, battery + ******************************************************************************/ +#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \ + defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE) +static struct wm97xx_batt_pdata palm27x_batt_pdata = { + .batt_aux = WM97XX_AUX_ID3, + .temp_aux = WM97XX_AUX_ID2, + .charge_gpio = -1, + .batt_mult = 1000, + .batt_div = 414, + .temp_mult = 1, + .temp_div = 1, + .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, + .batt_name = "main-batt", +}; + +static struct wm97xx_pdata palm27x_wm97xx_pdata = { + .batt_pdata = &palm27x_batt_pdata, +}; + +static pxa2xx_audio_ops_t palm27x_ac97_pdata = { + .codec_pdata = { &palm27x_wm97xx_pdata, }, +}; + +static struct palm27x_asoc_info palm27x_asoc_pdata = { + .jack_gpio = -1, +}; + +static struct platform_device palm27x_asoc = { + .name = "palm27x-asoc", + .id = -1, + .dev = { + .platform_data = &palm27x_asoc_pdata, + }, +}; + +void __init palm27x_ac97_init(int minv, int maxv, int jack, int reset) +{ + palm27x_ac97_pdata.reset_gpio = reset; + palm27x_asoc_pdata.jack_gpio = jack; + + if (minv < 0 || maxv < 0) { + palm27x_ac97_pdata.codec_pdata[0] = NULL; + pxa_set_ac97_info(&palm27x_ac97_pdata); + } else { + palm27x_batt_pdata.min_voltage = minv, + palm27x_batt_pdata.max_voltage = maxv, + + pxa_set_ac97_info(&palm27x_ac97_pdata); + platform_device_register(&palm27x_asoc); + } +} +#endif + +/****************************************************************************** + * Backlight + ******************************************************************************/ +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +static int palm_bl_power; +static int palm_lcd_power; + +static int palm27x_backlight_init(struct device *dev) +{ + int ret; + + ret = gpio_request(palm_bl_power, "BL POWER"); + if (ret) + goto err; + ret = gpio_direction_output(palm_bl_power, 0); + if (ret) + goto err2; + + if (gpio_is_valid(palm_lcd_power)) { + ret = gpio_request(palm_lcd_power, "LCD POWER"); + if (ret) + goto err2; + ret = gpio_direction_output(palm_lcd_power, 0); + if (ret) + goto err3; + } + + return 0; +err3: + gpio_free(palm_lcd_power); +err2: + gpio_free(palm_bl_power); +err: + return ret; +} + +static int palm27x_backlight_notify(struct device *dev, int brightness) +{ + gpio_set_value(palm_bl_power, brightness); + if (gpio_is_valid(palm_lcd_power)) + gpio_set_value(palm_lcd_power, brightness); + return brightness; +} + +static void palm27x_backlight_exit(struct device *dev) +{ + gpio_free(palm_bl_power); + if (gpio_is_valid(palm_lcd_power)) + gpio_free(palm_lcd_power); +} + +static struct platform_pwm_backlight_data palm27x_backlight_data = { + .pwm_id = 0, + .max_brightness = 0xfe, + .dft_brightness = 0x7e, + .pwm_period_ns = 3500, + .init = palm27x_backlight_init, + .notify = palm27x_backlight_notify, + .exit = palm27x_backlight_exit, +}; + +static struct platform_device palm27x_backlight = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &palm27x_backlight_data, + }, +}; + +void __init palm27x_pwm_init(int bl, int lcd) +{ + palm_bl_power = bl; + palm_lcd_power = lcd; + platform_device_register(&palm27x_backlight); +} +#endif + +/****************************************************************************** + * Power supply + ******************************************************************************/ +#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE) +static int palm_ac_state; +static int palm_usb_state; + +static int palm27x_power_supply_init(struct device *dev) +{ + int ret; + + ret = gpio_request(palm_ac_state, "AC state"); + if (ret) + goto err1; + ret = gpio_direction_input(palm_ac_state); + if (ret) + goto err2; + + if (gpio_is_valid(palm_usb_state)) { + ret = gpio_request(palm_usb_state, "USB state"); + if (ret) + goto err2; + ret = gpio_direction_input(palm_usb_state); + if (ret) + goto err3; + } + + return 0; +err3: + gpio_free(palm_usb_state); +err2: + gpio_free(palm_ac_state); +err1: + return ret; +} + +static void palm27x_power_supply_exit(struct device *dev) +{ + gpio_free(palm_usb_state); + gpio_free(palm_ac_state); +} + +static int palm27x_is_ac_online(void) +{ + return gpio_get_value(palm_ac_state); +} + +static int palm27x_is_usb_online(void) +{ + return !gpio_get_value(palm_usb_state); +} +static char *palm27x_supplicants[] = { + "main-battery", +}; + +static struct pda_power_pdata palm27x_ps_info = { + .init = palm27x_power_supply_init, + .exit = palm27x_power_supply_exit, + .is_ac_online = palm27x_is_ac_online, + .is_usb_online = palm27x_is_usb_online, + .supplied_to = palm27x_supplicants, + .num_supplicants = ARRAY_SIZE(palm27x_supplicants), +}; + +static struct platform_device palm27x_power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = &palm27x_ps_info, + }, +}; + +void __init palm27x_power_init(int ac, int usb) +{ + palm_ac_state = ac; + palm_usb_state = usb; + platform_device_register(&palm27x_power_supply); +} +#endif + +/****************************************************************************** + * Core power regulator + ******************************************************************************/ +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +static struct regulator_consumer_supply palm27x_max1587a_consumers[] = { + { + .supply = "vcc_core", + } +}; + +static struct regulator_init_data palm27x_max1587a_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 900000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .consumer_supplies = palm27x_max1587a_consumers, + .num_consumer_supplies = ARRAY_SIZE(palm27x_max1587a_consumers), +}; + +static struct max1586_subdev_data palm27x_max1587a_subdevs[] = { + { + .name = "vcc_core", + .id = MAX1586_V3, + .platform_data = &palm27x_max1587a_v3_info, + } +}; + +static struct max1586_platform_data palm27x_max1587a_info = { + .subdevs = palm27x_max1587a_subdevs, + .num_subdevs = ARRAY_SIZE(palm27x_max1587a_subdevs), + .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */ +}; + +static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &palm27x_max1587a_info, + }, +}; + +void __init palm27x_pmic_init(void) +{ + i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info)); + pxa27x_set_i2c_power_info(NULL); +} +#endif diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 1963819dba9..91038eeafe4 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -22,7 +22,7 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> -#include <linux/wm97xx_batt.h> +#include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/sysdev.h> #include <linux/mtd/mtd.h> @@ -41,6 +41,7 @@ #include <mach/irda.h> #include <mach/pxa27x_keypad.h> #include <mach/palmasoc.h> +#include <mach/palm27x.h> #include "generic.h" #include "devices.h" @@ -127,6 +128,7 @@ static unsigned long palmld_pin_config[] __initdata = { /****************************************************************************** * NOR Flash ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition palmld_partitions[] = { { .name = "Flash", @@ -160,20 +162,18 @@ static struct platform_device palmld_flash = { }, }; -/****************************************************************************** - * SD/MMC card controller - ******************************************************************************/ -static struct pxamci_platform_data palmld_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_PALMLD_SD_DETECT_N, - .gpio_card_ro = GPIO_NR_PALMLD_SD_READONLY, - .gpio_power = GPIO_NR_PALMLD_SD_POWER, - .detect_delay_ms = 200, -}; +static void __init palmld_nor_init(void) +{ + platform_device_register(&palmld_flash); +} +#else +static inline void palmld_nor_init(void) {} +#endif /****************************************************************************** * GPIO keyboard ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) static unsigned int palmld_matrix_keys[] = { KEY(0, 1, KEY_F2), KEY(0, 2, KEY_UP), @@ -200,9 +200,18 @@ static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = { .debounce_interval = 30, }; +static void __init palmld_kpc_init(void) +{ + pxa_set_keypad_info(&palmld_keypad_platform_data); +} +#else +static inline void palmld_kpc_init(void) {} +#endif + /****************************************************************************** * GPIO keys ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button palmld_pxa_buttons[] = { {KEY_F8, GPIO_NR_PALMLD_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, {KEY_F9, GPIO_NR_PALMLD_LOCK_SWITCH, 0, "Lock Switch" }, @@ -222,77 +231,18 @@ static struct platform_device palmld_pxa_keys = { }, }; -/****************************************************************************** - * Backlight - ******************************************************************************/ -static int palmld_backlight_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMLD_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_PALMLD_BL_POWER, 0); - if (ret) - goto err2; - ret = gpio_request(GPIO_NR_PALMLD_LCD_POWER, "LCD POWER"); - if (ret) - goto err2; - ret = gpio_direction_output(GPIO_NR_PALMLD_LCD_POWER, 0); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMLD_LCD_POWER); -err2: - gpio_free(GPIO_NR_PALMLD_BL_POWER); -err: - return ret; -} - -static int palmld_backlight_notify(struct device *dev, int brightness) +static void __init palmld_keys_init(void) { - gpio_set_value(GPIO_NR_PALMLD_BL_POWER, brightness); - gpio_set_value(GPIO_NR_PALMLD_LCD_POWER, brightness); - return brightness; + platform_device_register(&palmld_pxa_keys); } - -static void palmld_backlight_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMLD_BL_POWER); - gpio_free(GPIO_NR_PALMLD_LCD_POWER); -} - -static struct platform_pwm_backlight_data palmld_backlight_data = { - .pwm_id = 0, - .max_brightness = PALMLD_MAX_INTENSITY, - .dft_brightness = PALMLD_MAX_INTENSITY, - .pwm_period_ns = PALMLD_PERIOD_NS, - .init = palmld_backlight_init, - .notify = palmld_backlight_notify, - .exit = palmld_backlight_exit, -}; - -static struct platform_device palmld_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &pxa27x_device_pwm0.dev, - .platform_data = &palmld_backlight_data, - }, -}; - -/****************************************************************************** - * IrDA - ******************************************************************************/ -static struct pxaficp_platform_data palmld_ficp_platform_data = { - .gpio_pwdown = GPIO_NR_PALMLD_IR_DISABLE, - .transceiver_cap = IR_SIRMODE | IR_OFF, -}; +#else +static inline void palmld_keys_init(void) {} +#endif /****************************************************************************** * LEDs ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) struct gpio_led gpio_leds[] = { { .name = "palmld:green:led", @@ -318,174 +268,34 @@ static struct platform_device palmld_leds = { } }; -/****************************************************************************** - * Power supply - ******************************************************************************/ -static int power_supply_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMLD_POWER_DETECT, "CABLE_STATE_AC"); - if (ret) - goto err1; - ret = gpio_direction_input(GPIO_NR_PALMLD_POWER_DETECT); - if (ret) - goto err2; - - ret = gpio_request(GPIO_NR_PALMLD_USB_DETECT_N, "CABLE_STATE_USB"); - if (ret) - goto err2; - ret = gpio_direction_input(GPIO_NR_PALMLD_USB_DETECT_N); - if (ret) - goto err3; - - return 0; - -err3: - gpio_free(GPIO_NR_PALMLD_USB_DETECT_N); -err2: - gpio_free(GPIO_NR_PALMLD_POWER_DETECT); -err1: - return ret; -} - -static int palmld_is_ac_online(void) +static void __init palmld_leds_init(void) { - return gpio_get_value(GPIO_NR_PALMLD_POWER_DETECT); + platform_device_register(&palmld_leds); } - -static int palmld_is_usb_online(void) -{ - return !gpio_get_value(GPIO_NR_PALMLD_USB_DETECT_N); -} - -static void power_supply_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMLD_USB_DETECT_N); - gpio_free(GPIO_NR_PALMLD_POWER_DETECT); -} - -static char *palmld_supplicants[] = { - "main-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = palmld_is_ac_online, - .is_usb_online = palmld_is_usb_online, - .exit = power_supply_exit, - .supplied_to = palmld_supplicants, - .num_supplicants = ARRAY_SIZE(palmld_supplicants), -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, -}; - -/****************************************************************************** - * WM97xx battery - ******************************************************************************/ -static struct wm97xx_batt_info wm97xx_batt_pdata = { - .batt_aux = WM97XX_AUX_ID3, - .temp_aux = WM97XX_AUX_ID2, - .charge_gpio = -1, - .max_voltage = PALMLD_BAT_MAX_VOLTAGE, - .min_voltage = PALMLD_BAT_MIN_VOLTAGE, - .batt_mult = 1000, - .batt_div = 414, - .temp_mult = 1, - .temp_div = 1, - .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, - .batt_name = "main-batt", -}; - -/****************************************************************************** - * aSoC audio - ******************************************************************************/ -static struct palm27x_asoc_info palmld_asoc_pdata = { - .jack_gpio = GPIO_NR_PALMLD_EARPHONE_DETECT, -}; - -static pxa2xx_audio_ops_t palmld_ac97_pdata = { - .reset_gpio = 95, -}; - -static struct platform_device palmld_asoc = { - .name = "palm27x-asoc", - .id = -1, - .dev = { - .platform_data = &palmld_asoc_pdata, - }, -}; +#else +static inline void palmld_leds_init(void) {} +#endif /****************************************************************************** * HDD ******************************************************************************/ -static struct platform_device palmld_hdd = { +#if defined(CONFIG_PATA_PALMLD) || defined(CONFIG_PATA_PALMLD_MODULE) +static struct platform_device palmld_ide_device = { .name = "pata_palmld", .id = -1, }; -/****************************************************************************** - * Framebuffer - ******************************************************************************/ -static struct pxafb_mode_info palmld_lcd_modes[] = { -{ - .pixclock = 57692, - .xres = 320, - .yres = 480, - .bpp = 16, - - .left_margin = 32, - .right_margin = 1, - .upper_margin = 7, - .lower_margin = 1, - - .hsync_len = 4, - .vsync_len = 1, -}, -}; - -static struct pxafb_mach_info palmld_lcd_screen = { - .modes = palmld_lcd_modes, - .num_modes = ARRAY_SIZE(palmld_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, -}; - -/****************************************************************************** - * Power management - standby - ******************************************************************************/ -static void __init palmld_pm_init(void) +static void __init palmld_ide_init(void) { - static u32 resume[] = { - 0xe3a00101, /* mov r0, #0x40000000 */ - 0xe380060f, /* orr r0, r0, #0x00f00000 */ - 0xe590f008, /* ldr pc, [r0, #0x08] */ - }; - - /* copy the bootloader */ - memcpy(phys_to_virt(PALMLD_STR_BASE), resume, sizeof(resume)); + platform_device_register(&palmld_ide_device); } +#else +static inline void palmld_ide_init(void) {} +#endif /****************************************************************************** * Machine init ******************************************************************************/ -static struct platform_device *devices[] __initdata = { -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) - &palmld_pxa_keys, -#endif - &palmld_backlight, - &palmld_leds, - &power_supply, - &palmld_asoc, - &palmld_hdd, - &palmld_flash, -}; - static struct map_desc palmld_io_desc[] __initdata = { { .virtual = PALMLD_IDE_VIRT, @@ -510,20 +320,26 @@ static void __init palmld_map_io(void) static void __init palmld_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config)); - pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - palmld_pm_init(); - set_pxa_fb_info(&palmld_lcd_screen); - pxa_set_mci_info(&palmld_mci_platform_data); - pxa_set_ac97_info(&palmld_ac97_pdata); - pxa_set_ficp_info(&palmld_ficp_platform_data); - pxa_set_keypad_info(&palmld_keypad_platform_data); - wm97xx_bat_set_pdata(&wm97xx_batt_pdata); - - platform_add_devices(devices, ARRAY_SIZE(devices)); + palm27x_mmc_init(GPIO_NR_PALMLD_SD_DETECT_N, GPIO_NR_PALMLD_SD_READONLY, + GPIO_NR_PALMLD_SD_POWER, 0); + palm27x_pm_init(PALMLD_STR_BASE); + palm27x_lcd_init(-1, &palm_320x480_lcd_mode); + palm27x_irda_init(GPIO_NR_PALMLD_IR_DISABLE); + palm27x_ac97_init(PALMLD_BAT_MIN_VOLTAGE, PALMLD_BAT_MAX_VOLTAGE, + GPIO_NR_PALMLD_EARPHONE_DETECT, 95); + palm27x_pwm_init(GPIO_NR_PALMLD_BL_POWER, GPIO_NR_PALMLD_LCD_POWER); + palm27x_power_init(GPIO_NR_PALMLD_POWER_DETECT, + GPIO_NR_PALMLD_USB_DETECT_N); + palm27x_pmic_init(); + palmld_kpc_init(); + palmld_keys_init(); + palmld_nor_init(); + palmld_leds_init(); + palmld_ide_init(); } MACHINE_START(PALMLD, "Palm LifeDrive") diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 5e92d84fe50..1c281995f65 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -25,7 +25,7 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> -#include <linux/wm97xx_batt.h> +#include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> @@ -42,6 +42,7 @@ #include <mach/pxa27x_keypad.h> #include <mach/udc.h> #include <mach/palmasoc.h> +#include <mach/palm27x.h> #include "generic.h" #include "devices.h" @@ -104,19 +105,9 @@ static unsigned long palmt5_pin_config[] __initdata = { }; /****************************************************************************** - * SD/MMC card controller - ******************************************************************************/ -static struct pxamci_platform_data palmt5_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_PALMT5_SD_DETECT_N, - .gpio_card_ro = GPIO_NR_PALMT5_SD_READONLY, - .gpio_power = GPIO_NR_PALMT5_SD_POWER, - .detect_delay_ms = 200, -}; - -/****************************************************************************** * GPIO keyboard ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) static unsigned int palmt5_matrix_keys[] = { KEY(0, 0, KEY_POWER), KEY(0, 1, KEY_F1), @@ -142,9 +133,18 @@ static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = { .debounce_interval = 30, }; +static void __init palmt5_kpc_init(void) +{ + pxa_set_keypad_info(&palmt5_keypad_platform_data); +} +#else +static inline void palmt5_kpc_init(void) {} +#endif + /****************************************************************************** * GPIO keys ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button palmt5_pxa_buttons[] = { {KEY_F8, GPIO_NR_PALMT5_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, }; @@ -162,241 +162,17 @@ static struct platform_device palmt5_pxa_keys = { }, }; -/****************************************************************************** - * Backlight - ******************************************************************************/ -static int palmt5_backlight_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMT5_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_PALMT5_BL_POWER, 0); - if (ret) - goto err2; - ret = gpio_request(GPIO_NR_PALMT5_LCD_POWER, "LCD POWER"); - if (ret) - goto err2; - ret = gpio_direction_output(GPIO_NR_PALMT5_LCD_POWER, 0); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMT5_LCD_POWER); -err2: - gpio_free(GPIO_NR_PALMT5_BL_POWER); -err: - return ret; -} - -static int palmt5_backlight_notify(struct device *dev, int brightness) -{ - gpio_set_value(GPIO_NR_PALMT5_BL_POWER, brightness); - gpio_set_value(GPIO_NR_PALMT5_LCD_POWER, brightness); - return brightness; -} - -static void palmt5_backlight_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMT5_BL_POWER); - gpio_free(GPIO_NR_PALMT5_LCD_POWER); -} - -static struct platform_pwm_backlight_data palmt5_backlight_data = { - .pwm_id = 0, - .max_brightness = PALMT5_MAX_INTENSITY, - .dft_brightness = PALMT5_MAX_INTENSITY, - .pwm_period_ns = PALMT5_PERIOD_NS, - .init = palmt5_backlight_init, - .notify = palmt5_backlight_notify, - .exit = palmt5_backlight_exit, -}; - -static struct platform_device palmt5_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &pxa27x_device_pwm0.dev, - .platform_data = &palmt5_backlight_data, - }, -}; - -/****************************************************************************** - * IrDA - ******************************************************************************/ -static struct pxaficp_platform_data palmt5_ficp_platform_data = { - .gpio_pwdown = GPIO_NR_PALMT5_IR_DISABLE, - .transceiver_cap = IR_SIRMODE | IR_OFF, -}; - -/****************************************************************************** - * UDC - ******************************************************************************/ -static struct gpio_vbus_mach_info palmt5_udc_info = { - .gpio_vbus = GPIO_NR_PALMT5_USB_DETECT_N, - .gpio_vbus_inverted = 1, - .gpio_pullup = GPIO_NR_PALMT5_USB_PULLUP, -}; - -static struct platform_device palmt5_gpio_vbus = { - .name = "gpio-vbus", - .id = -1, - .dev = { - .platform_data = &palmt5_udc_info, - }, -}; - -/****************************************************************************** - * Power supply - ******************************************************************************/ -static int power_supply_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMT5_POWER_DETECT, "CABLE_STATE_AC"); - if (ret) - goto err1; - ret = gpio_direction_input(GPIO_NR_PALMT5_POWER_DETECT); - if (ret) - goto err2; - - return 0; -err2: - gpio_free(GPIO_NR_PALMT5_POWER_DETECT); -err1: - return ret; -} - -static int palmt5_is_ac_online(void) -{ - return gpio_get_value(GPIO_NR_PALMT5_POWER_DETECT); -} - -static void power_supply_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMT5_POWER_DETECT); -} - -static char *palmt5_supplicants[] = { - "main-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = palmt5_is_ac_online, - .exit = power_supply_exit, - .supplied_to = palmt5_supplicants, - .num_supplicants = ARRAY_SIZE(palmt5_supplicants), -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, -}; - -/****************************************************************************** - * WM97xx battery - ******************************************************************************/ -static struct wm97xx_batt_info wm97xx_batt_pdata = { - .batt_aux = WM97XX_AUX_ID3, - .temp_aux = WM97XX_AUX_ID2, - .charge_gpio = -1, - .max_voltage = PALMT5_BAT_MAX_VOLTAGE, - .min_voltage = PALMT5_BAT_MIN_VOLTAGE, - .batt_mult = 1000, - .batt_div = 414, - .temp_mult = 1, - .temp_div = 1, - .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, - .batt_name = "main-batt", -}; - -/****************************************************************************** - * aSoC audio - ******************************************************************************/ -static struct palm27x_asoc_info palmt5_asoc_pdata = { - .jack_gpio = GPIO_NR_PALMT5_EARPHONE_DETECT, -}; - -static pxa2xx_audio_ops_t palmt5_ac97_pdata = { - .reset_gpio = 95, -}; - -static struct platform_device palmt5_asoc = { - .name = "palm27x-asoc", - .id = -1, - .dev = { - .platform_data = &palmt5_asoc_pdata, - }, -}; - -/****************************************************************************** - * Framebuffer - ******************************************************************************/ -static struct pxafb_mode_info palmt5_lcd_modes[] = { -{ - .pixclock = 57692, - .xres = 320, - .yres = 480, - .bpp = 16, - - .left_margin = 32, - .right_margin = 1, - .upper_margin = 7, - .lower_margin = 1, - - .hsync_len = 4, - .vsync_len = 1, -}, -}; - -static struct pxafb_mach_info palmt5_lcd_screen = { - .modes = palmt5_lcd_modes, - .num_modes = ARRAY_SIZE(palmt5_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, -}; - -/****************************************************************************** - * Power management - standby - ******************************************************************************/ -static void __init palmt5_pm_init(void) +static void __init palmt5_keys_init(void) { - static u32 resume[] = { - 0xe3a00101, /* mov r0, #0x40000000 */ - 0xe380060f, /* orr r0, r0, #0x00f00000 */ - 0xe590f008, /* ldr pc, [r0, #0x08] */ - }; - - /* copy the bootloader */ - memcpy(phys_to_virt(PALMT5_STR_BASE), resume, sizeof(resume)); + platform_device_register(&palmt5_pxa_keys); } +#else +static inline void palmt5_keys_init(void) {} +#endif /****************************************************************************** * Machine init ******************************************************************************/ -static struct platform_device *devices[] __initdata = { -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) - &palmt5_pxa_keys, -#endif - &palmt5_backlight, - &power_supply, - &palmt5_asoc, - &palmt5_gpio_vbus, -}; - -/* setup udc GPIOs initial state */ -static void __init palmt5_udc_init(void) -{ - if (!gpio_request(GPIO_NR_PALMT5_USB_PULLUP, "UDC Vbus")) { - gpio_direction_output(GPIO_NR_PALMT5_USB_PULLUP, 1); - gpio_free(GPIO_NR_PALMT5_USB_PULLUP); - } -} - static void __init palmt5_reserve(void) { memblock_reserve(0xa0200000, 0x1000); @@ -405,21 +181,24 @@ static void __init palmt5_reserve(void) static void __init palmt5_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); - pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - palmt5_pm_init(); - set_pxa_fb_info(&palmt5_lcd_screen); - pxa_set_mci_info(&palmt5_mci_platform_data); - palmt5_udc_init(); - pxa_set_ac97_info(&palmt5_ac97_pdata); - pxa_set_ficp_info(&palmt5_ficp_platform_data); - pxa_set_keypad_info(&palmt5_keypad_platform_data); - wm97xx_bat_set_pdata(&wm97xx_batt_pdata); - - platform_add_devices(devices, ARRAY_SIZE(devices)); + palm27x_mmc_init(GPIO_NR_PALMT5_SD_DETECT_N, GPIO_NR_PALMT5_SD_READONLY, + GPIO_NR_PALMT5_SD_POWER, 0); + palm27x_pm_init(PALMT5_STR_BASE); + palm27x_lcd_init(-1, &palm_320x480_lcd_mode); + palm27x_udc_init(GPIO_NR_PALMT5_USB_DETECT_N, + GPIO_NR_PALMT5_USB_PULLUP, 1); + palm27x_irda_init(GPIO_NR_PALMT5_IR_DISABLE); + palm27x_ac97_init(PALMT5_BAT_MIN_VOLTAGE, PALMT5_BAT_MAX_VOLTAGE, + GPIO_NR_PALMT5_EARPHONE_DETECT, 95); + palm27x_pwm_init(GPIO_NR_PALMT5_BL_POWER, GPIO_NR_PALMT5_LCD_POWER); + palm27x_power_init(GPIO_NR_PALMT5_POWER_DETECT, -1); + palm27x_pmic_init(); + palmt5_kpc_init(); + palmt5_keys_init(); } MACHINE_START(PALMT5, "Palm Tungsten|T5") diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 3d284ff1a64..93c11a0438d 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -23,7 +23,7 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> -#include <linux/wm97xx_batt.h> +#include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> @@ -271,9 +271,9 @@ static struct platform_device power_supply = { }; /****************************************************************************** - * WM97xx battery + * WM97xx audio, battery ******************************************************************************/ -static struct wm97xx_batt_info wm97xx_batt_pdata = { +static struct wm97xx_batt_pdata palmte2_batt_pdata = { .batt_aux = WM97XX_AUX_ID3, .temp_aux = WM97XX_AUX_ID2, .charge_gpio = -1, @@ -287,9 +287,14 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = { .batt_name = "main-batt", }; -/****************************************************************************** - * aSoC audio - ******************************************************************************/ +static struct wm97xx_pdata palmte2_wm97xx_pdata = { + .batt_pdata = &palmte2_batt_pdata, +}; + +static pxa2xx_audio_ops_t palmte2_ac97_pdata = { + .codec_pdata = { &palmte2_wm97xx_pdata, }, +}; + static struct palm27x_asoc_info palmte2_asoc_pdata = { .jack_gpio = GPIO_NR_PALMTE2_EARPHONE_DETECT, }; @@ -361,9 +366,8 @@ static void __init palmte2_init(void) set_pxa_fb_info(&palmte2_lcd_screen); pxa_set_mci_info(&palmte2_mci_platform_data); palmte2_udc_init(); - pxa_set_ac97_info(NULL); + pxa_set_ac97_info(&palmte2_ac97_pdata); pxa_set_ficp_info(&palmte2_ficp_platform_data); - wm97xx_bat_set_pdata(&wm97xx_batt_pdata); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 3d0c9cc2a40..52defd5e42e 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -24,7 +24,6 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> -#include <linux/wm97xx_batt.h> #include <linux/power_supply.h> #include <linux/sysdev.h> #include <linux/w1-gpio.h> @@ -46,6 +45,7 @@ #include <mach/pxa2xx-regs.h> #include <mach/palmasoc.h> #include <mach/camera.h> +#include <mach/palm27x.h> #include <sound/pxa2xx-lib.h> @@ -160,31 +160,9 @@ static unsigned long centro685_pin_config[] __initdata = { #endif /* CONFIG_MACH_CENTRO */ /****************************************************************************** - * SD/MMC card controller - ******************************************************************************/ -#ifdef CONFIG_MACH_TREO680 -static struct pxamci_platform_data treo680_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_TREO_SD_DETECT_N, - .gpio_card_ro = GPIO_NR_TREO680_SD_READONLY, - .gpio_power = GPIO_NR_TREO680_SD_POWER, -}; -#endif /* CONFIG_MACH_TREO680 */ - -#ifdef CONFIG_MACH_CENTRO -static struct pxamci_platform_data centro_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_TREO_SD_DETECT_N, - .gpio_card_ro = -1, - .gpio_power = GPIO_NR_CENTRO_SD_POWER, - .gpio_power_invert = 1, -}; -#endif /* CONFIG_MACH_CENTRO */ - -/****************************************************************************** * GPIO keyboard ******************************************************************************/ -#ifdef CONFIG_MACH_TREO680 +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) static unsigned int treo680_matrix_keys[] = { KEY(0, 0, KEY_F8), /* Red/Off/Power */ KEY(0, 1, KEY_LEFT), @@ -244,19 +222,6 @@ static unsigned int treo680_matrix_keys[] = { KEY(7, 5, KEY_I), }; -static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { - .matrix_key_rows = 8, - .matrix_key_cols = 7, - .matrix_key_map = treo680_matrix_keys, - .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), - .direct_key_map = { KEY_CONNECT }, - .direct_key_num = 1, - - .debounce_interval = 30, -}; -#endif /* CONFIG_MACH_TREO680 */ - -#ifdef CONFIG_MACH_CENTRO static unsigned int centro_matrix_keys[] = { KEY(0, 0, KEY_F9), /* Home */ KEY(0, 1, KEY_LEFT), @@ -316,157 +281,50 @@ static unsigned int centro_matrix_keys[] = { KEY(7, 5, KEY_I), }; -static struct pxa27x_keypad_platform_data centro_keypad_platform_data = { +static struct pxa27x_keypad_platform_data treo680_keypad_pdata = { .matrix_key_rows = 8, .matrix_key_cols = 7, - .matrix_key_map = centro_matrix_keys, - .matrix_key_map_size = ARRAY_SIZE(centro_matrix_keys), + .matrix_key_map = treo680_matrix_keys, + .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), .direct_key_map = { KEY_CONNECT }, .direct_key_num = 1, .debounce_interval = 30, }; -#endif /* CONFIG_MACH_CENTRO */ -/****************************************************************************** - * aSoC audio - ******************************************************************************/ - -static pxa2xx_audio_ops_t treo_ac97_pdata = { - .reset_gpio = 95, -}; - -/****************************************************************************** - * Backlight - ******************************************************************************/ -static int treo_backlight_init(struct device *dev) +static void __init palmtreo_kpc_init(void) { - int ret; - - ret = gpio_request(GPIO_NR_TREO_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_TREO_BL_POWER, 0); - if (ret) - goto err2; - - return 0; + static struct pxa27x_keypad_platform_data *data = &treo680_keypad_pdata; -err2: - gpio_free(GPIO_NR_TREO_BL_POWER); -err: - return ret; -} - -static int treo_backlight_notify(struct device *dev, int brightness) -{ - gpio_set_value(GPIO_NR_TREO_BL_POWER, brightness); - return TREO_MAX_INTENSITY - brightness; -}; + if (machine_is_centro()) { + data->matrix_key_map = centro_matrix_keys; + data->matrix_key_map_size = ARRAY_SIZE(centro_matrix_keys); + } -static void treo_backlight_exit(struct device *dev) -{ - gpio_free(GPIO_NR_TREO_BL_POWER); + pxa_set_keypad_info(&treo680_keypad_pdata); } - -static struct platform_pwm_backlight_data treo_backlight_data = { - .pwm_id = 0, - .max_brightness = TREO_MAX_INTENSITY, - .dft_brightness = TREO_DEFAULT_INTENSITY, - .pwm_period_ns = TREO_PERIOD_NS, - .init = treo_backlight_init, - .notify = treo_backlight_notify, - .exit = treo_backlight_exit, -}; - -static struct platform_device treo_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &pxa27x_device_pwm0.dev, - .platform_data = &treo_backlight_data, - }, -}; - -/****************************************************************************** - * IrDA - ******************************************************************************/ -static struct pxaficp_platform_data treo_ficp_info = { - .gpio_pwdown = GPIO_NR_TREO_IR_EN, - .transceiver_cap = IR_SIRMODE | IR_OFF, -}; - -/****************************************************************************** - * UDC - ******************************************************************************/ -static struct pxa2xx_udc_mach_info treo_udc_info __initdata = { - .gpio_vbus = GPIO_NR_TREO_USB_DETECT, - .gpio_vbus_inverted = 1, - .gpio_pullup = GPIO_NR_TREO_USB_PULLUP, -}; - +#else +static inline void palmtreo_kpc_init(void) {} +#endif /****************************************************************************** * USB host ******************************************************************************/ -#ifdef CONFIG_MACH_TREO680 +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) static struct pxaohci_platform_data treo680_ohci_info = { .port_mode = PMM_PERPORT_MODE, .flags = ENABLE_PORT1 | ENABLE_PORT3, .power_budget = 0, }; -#endif /* CONFIG_MACH_TREO680 */ -/****************************************************************************** - * Power supply - ******************************************************************************/ -static int power_supply_init(struct device *dev) +static void __init palmtreo_uhc_init(void) { - int ret; - - ret = gpio_request(GPIO_NR_TREO_POWER_DETECT, "CABLE_STATE_AC"); - if (ret) - goto err1; - ret = gpio_direction_input(GPIO_NR_TREO_POWER_DETECT); - if (ret) - goto err2; - - return 0; - -err2: - gpio_free(GPIO_NR_TREO_POWER_DETECT); -err1: - return ret; -} - -static int treo_is_ac_online(void) -{ - return gpio_get_value(GPIO_NR_TREO_POWER_DETECT); + if (machine_is_treo680()) + pxa_set_ohci_info(&treo680_ohci_info); } - -static void power_supply_exit(struct device *dev) -{ - gpio_free(GPIO_NR_TREO_POWER_DETECT); -} - -static char *treo_supplicants[] = { - "main-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = treo_is_ac_online, - .exit = power_supply_exit, - .supplied_to = treo_supplicants, - .num_supplicants = ARRAY_SIZE(treo_supplicants), -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, -}; +#else +static inline void palmtreo_uhc_init(void) {} +#endif /****************************************************************************** * Vibra and LEDs @@ -495,16 +353,6 @@ static struct gpio_led_platform_data treo680_gpio_led_info = { .num_leds = ARRAY_SIZE(treo680_gpio_leds), }; -static struct platform_device treo680_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &treo680_gpio_led_info, - } -}; -#endif /* CONFIG_MACH_TREO680 */ - -#ifdef CONFIG_MACH_CENTRO static struct gpio_led centro_gpio_leds[] = { { .name = "centro:vibra:vibra", @@ -529,145 +377,67 @@ static struct gpio_led_platform_data centro_gpio_led_info = { .num_leds = ARRAY_SIZE(centro_gpio_leds), }; -static struct platform_device centro_leds = { +static struct platform_device palmtreo_leds = { .name = "leds-gpio", .id = -1, .dev = { - .platform_data = ¢ro_gpio_led_info, + .platform_data = &treo680_gpio_led_info, } }; -#endif /* CONFIG_MACH_CENTRO */ - -/****************************************************************************** - * Framebuffer - ******************************************************************************/ -/* TODO: add support for 324x324 */ -static struct pxafb_mode_info treo_lcd_modes[] = { -{ - .pixclock = 86538, - .xres = 320, - .yres = 320, - .bpp = 16, - - .left_margin = 20, - .right_margin = 8, - .upper_margin = 8, - .lower_margin = 5, - - .hsync_len = 4, - .vsync_len = 1, -}, -}; -static void treo_lcd_power(int on, struct fb_var_screeninfo *info) +static void __init palmtreo_leds_init(void) { - gpio_set_value(GPIO_NR_TREO_BL_POWER, on); -} - -static struct pxafb_mach_info treo_lcd_screen = { - .modes = treo_lcd_modes, - .num_modes = ARRAY_SIZE(treo_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, -}; + if (machine_is_centro()) + palmtreo_leds.dev.platform_data = ¢ro_gpio_led_info; -/****************************************************************************** - * Power management - standby - ******************************************************************************/ -static void __init treo_pm_init(void) -{ - static u32 resume[] = { - 0xe3a00101, /* mov r0, #0x40000000 */ - 0xe380060f, /* orr r0, r0, #0x00f00000 */ - 0xe590f008, /* ldr pc, [r0, #0x08] */ - }; - - /* this is where the bootloader jumps */ - memcpy(phys_to_virt(TREO_STR_BASE), resume, sizeof(resume)); + platform_device_register(&palmtreo_leds); } +#else +static inline void palmtreo_leds_init(void) {} +#endif /****************************************************************************** * Machine init ******************************************************************************/ -static struct platform_device *treo_devices[] __initdata = { - &treo_backlight, - &power_supply, -}; - -#ifdef CONFIG_MACH_TREO680 -static struct platform_device *treo680_devices[] __initdata = { - &treo680_leds, -}; -#endif /* CONFIG_MACH_TREO680 */ - -#ifdef CONFIG_MACH_CENTRO -static struct platform_device *centro_devices[] __initdata = { - ¢ro_leds, -}; -#endif /* CONFIG_MACH_CENTRO */ - -/* setup udc GPIOs initial state */ -static void __init treo_udc_init(void) -{ - if (!gpio_request(GPIO_NR_TREO_USB_PULLUP, "UDC Vbus")) { - gpio_direction_output(GPIO_NR_TREO_USB_PULLUP, 1); - gpio_free(GPIO_NR_TREO_USB_PULLUP); - } -} - -static void __init treo_lcd_power_init(void) -{ - int ret; - - ret = gpio_request(GPIO_NR_TREO_LCD_POWER, "LCD POWER"); - if (ret) { - pr_err("Treo680: LCD power GPIO request failed!\n"); - return; - } - - ret = gpio_direction_output(GPIO_NR_TREO_LCD_POWER, 0); - if (ret) { - pr_err("Treo680: setting LCD power GPIO direction failed!\n"); - gpio_free(GPIO_NR_TREO_LCD_POWER); - return; - } - - treo_lcd_screen.pxafb_lcd_power = treo_lcd_power; -} - static void __init treo_reserve(void) { memblock_reserve(0xa0000000, 0x1000); memblock_reserve(0xa2000000, 0x1000); } -static void __init treo_init(void) +static void __init palmphone_common_init(void) { + pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config)); pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - - treo_pm_init(); - pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config)); - treo_lcd_power_init(); - set_pxa_fb_info(&treo_lcd_screen); - treo_udc_init(); - pxa_set_udc_info(&treo_udc_info); - pxa_set_ac97_info(&treo_ac97_pdata); - pxa_set_ficp_info(&treo_ficp_info); - - platform_add_devices(ARRAY_AND_SIZE(treo_devices)); + palm27x_pm_init(TREO_STR_BASE); + palm27x_lcd_init(GPIO_NR_TREO_BL_POWER, &palm_320x320_new_lcd_mode); + palm27x_udc_init(GPIO_NR_TREO_USB_DETECT, GPIO_NR_TREO_USB_PULLUP, 1); + palm27x_irda_init(GPIO_NR_TREO_IR_EN); + palm27x_ac97_init(-1, -1, -1, 95); + palm27x_pwm_init(GPIO_NR_TREO_BL_POWER, -1); + palm27x_power_init(GPIO_NR_TREO_POWER_DETECT, -1); + palm27x_pmic_init(); + palmtreo_kpc_init(); + palmtreo_uhc_init(); + palmtreo_leds_init(); } -#ifdef CONFIG_MACH_TREO680 static void __init treo680_init(void) { - treo_init(); pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); - pxa_set_mci_info(&treo680_mci_platform_data); - pxa_set_keypad_info(&treo680_keypad_platform_data); - pxa_set_ohci_info(&treo680_ohci_info); + palmphone_common_init(); + palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY, + GPIO_NR_TREO680_SD_POWER, 0); +} - platform_add_devices(ARRAY_AND_SIZE(treo680_devices)); +static void __init centro_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config)); + palmphone_common_init(); + palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, -1, + GPIO_NR_CENTRO_SD_POWER, 1); } MACHINE_START(TREO680, "Palm Treo 680") @@ -680,19 +450,6 @@ MACHINE_START(TREO680, "Palm Treo 680") .timer = &pxa_timer, .init_machine = treo680_init, MACHINE_END -#endif /* CONFIG_MACH_TREO680 */ - -#ifdef CONFIG_MACH_CENTRO -static void __init centro_init(void) -{ - treo_init(); - pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config)); - pxa_set_mci_info(¢ro_mci_platform_data); - - pxa_set_keypad_info(¢ro_keypad_platform_data); - - platform_add_devices(ARRAY_AND_SIZE(centro_devices)); -} MACHINE_START(CENTRO, "Palm Centro 685") .phys_io = TREO_PHYS_IO_START, @@ -702,6 +459,5 @@ MACHINE_START(CENTRO, "Palm Centro 685") .reserve = treo_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = centro_init, + .init_machine = centro_init, MACHINE_END -#endif /* CONFIG_MACH_CENTRO */ diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index ecc1a401598..144dc2b6911 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -25,7 +25,7 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> -#include <linux/wm97xx_batt.h> +#include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> #include <linux/mtd/nand.h> @@ -46,6 +46,7 @@ #include <mach/pxa27x_keypad.h> #include <mach/udc.h> #include <mach/palmasoc.h> +#include <mach/palm27x.h> #include "generic.h" #include "devices.h" @@ -129,6 +130,7 @@ static unsigned long palmtx_pin_config[] __initdata = { /****************************************************************************** * NOR Flash ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition palmtx_partitions[] = { { .name = "Flash", @@ -162,20 +164,18 @@ static struct platform_device palmtx_flash = { }, }; -/****************************************************************************** - * SD/MMC card controller - ******************************************************************************/ -static struct pxamci_platform_data palmtx_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_PALMTX_SD_DETECT_N, - .gpio_card_ro = GPIO_NR_PALMTX_SD_READONLY, - .gpio_power = GPIO_NR_PALMTX_SD_POWER, - .detect_delay_ms = 200, -}; +static void __init palmtx_nor_init(void) +{ + platform_device_register(&palmtx_flash); +} +#else +static inline void palmtx_nor_init(void) {} +#endif /****************************************************************************** * GPIO keyboard ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) static unsigned int palmtx_matrix_keys[] = { KEY(0, 0, KEY_POWER), KEY(0, 1, KEY_F1), @@ -201,9 +201,18 @@ static struct pxa27x_keypad_platform_data palmtx_keypad_platform_data = { .debounce_interval = 30, }; +static void __init palmtx_kpc_init(void) +{ + pxa_set_keypad_info(&palmtx_keypad_platform_data); +} +#else +static inline void palmtx_kpc_init(void) {} +#endif + /****************************************************************************** * GPIO keys ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button palmtx_pxa_buttons[] = { {KEY_F8, GPIO_NR_PALMTX_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, }; @@ -221,208 +230,18 @@ static struct platform_device palmtx_pxa_keys = { }, }; -/****************************************************************************** - * Backlight - ******************************************************************************/ -static int palmtx_backlight_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMTX_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_PALMTX_BL_POWER, 0); - if (ret) - goto err2; - ret = gpio_request(GPIO_NR_PALMTX_LCD_POWER, "LCD POWER"); - if (ret) - goto err2; - ret = gpio_direction_output(GPIO_NR_PALMTX_LCD_POWER, 0); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMTX_LCD_POWER); -err2: - gpio_free(GPIO_NR_PALMTX_BL_POWER); -err: - return ret; -} - -static int palmtx_backlight_notify(struct device *dev, int brightness) -{ - gpio_set_value(GPIO_NR_PALMTX_BL_POWER, brightness); - gpio_set_value(GPIO_NR_PALMTX_LCD_POWER, brightness); - return brightness; -} - -static void palmtx_backlight_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMTX_BL_POWER); - gpio_free(GPIO_NR_PALMTX_LCD_POWER); -} - -static struct platform_pwm_backlight_data palmtx_backlight_data = { - .pwm_id = 0, - .max_brightness = PALMTX_MAX_INTENSITY, - .dft_brightness = PALMTX_MAX_INTENSITY, - .pwm_period_ns = PALMTX_PERIOD_NS, - .init = palmtx_backlight_init, - .notify = palmtx_backlight_notify, - .exit = palmtx_backlight_exit, -}; - -static struct platform_device palmtx_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &pxa27x_device_pwm0.dev, - .platform_data = &palmtx_backlight_data, - }, -}; - -/****************************************************************************** - * IrDA - ******************************************************************************/ -static struct pxaficp_platform_data palmtx_ficp_platform_data = { - .gpio_pwdown = GPIO_NR_PALMTX_IR_DISABLE, - .transceiver_cap = IR_SIRMODE | IR_OFF, -}; - -/****************************************************************************** - * UDC - ******************************************************************************/ -static struct gpio_vbus_mach_info palmtx_udc_info = { - .gpio_vbus = GPIO_NR_PALMTX_USB_DETECT_N, - .gpio_vbus_inverted = 1, - .gpio_pullup = GPIO_NR_PALMTX_USB_PULLUP, -}; - -static struct platform_device palmtx_gpio_vbus = { - .name = "gpio-vbus", - .id = -1, - .dev = { - .platform_data = &palmtx_udc_info, - }, -}; - -/****************************************************************************** - * Power supply - ******************************************************************************/ -static int power_supply_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMTX_POWER_DETECT, "CABLE_STATE_AC"); - if (ret) - goto err1; - ret = gpio_direction_input(GPIO_NR_PALMTX_POWER_DETECT); - if (ret) - goto err2; - - return 0; - -err2: - gpio_free(GPIO_NR_PALMTX_POWER_DETECT); -err1: - return ret; -} - -static int palmtx_is_ac_online(void) -{ - return gpio_get_value(GPIO_NR_PALMTX_POWER_DETECT); -} - -static void power_supply_exit(struct device *dev) +static void __init palmtx_keys_init(void) { - gpio_free(GPIO_NR_PALMTX_POWER_DETECT); + platform_device_register(&palmtx_pxa_keys); } - -static char *palmtx_supplicants[] = { - "main-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = palmtx_is_ac_online, - .exit = power_supply_exit, - .supplied_to = palmtx_supplicants, - .num_supplicants = ARRAY_SIZE(palmtx_supplicants), -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, -}; - -/****************************************************************************** - * WM97xx battery - ******************************************************************************/ -static struct wm97xx_batt_info wm97xx_batt_pdata = { - .batt_aux = WM97XX_AUX_ID3, - .temp_aux = WM97XX_AUX_ID2, - .charge_gpio = -1, - .max_voltage = PALMTX_BAT_MAX_VOLTAGE, - .min_voltage = PALMTX_BAT_MIN_VOLTAGE, - .batt_mult = 1000, - .batt_div = 414, - .temp_mult = 1, - .temp_div = 1, - .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, - .batt_name = "main-batt", -}; - -/****************************************************************************** - * aSoC audio - ******************************************************************************/ -static struct palm27x_asoc_info palmtx_asoc_pdata = { - .jack_gpio = GPIO_NR_PALMTX_EARPHONE_DETECT, -}; - -static pxa2xx_audio_ops_t palmtx_ac97_pdata = { - .reset_gpio = 95, -}; - -static struct platform_device palmtx_asoc = { - .name = "palm27x-asoc", - .id = -1, - .dev = { - .platform_data = &palmtx_asoc_pdata, - }, -}; - -/****************************************************************************** - * Framebuffer - ******************************************************************************/ -static struct pxafb_mode_info palmtx_lcd_modes[] = { -{ - .pixclock = 57692, - .xres = 320, - .yres = 480, - .bpp = 16, - - .left_margin = 32, - .right_margin = 1, - .upper_margin = 7, - .lower_margin = 1, - - .hsync_len = 4, - .vsync_len = 1, -}, -}; - -static struct pxafb_mach_info palmtx_lcd_screen = { - .modes = palmtx_lcd_modes, - .num_modes = ARRAY_SIZE(palmtx_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, -}; +#else +static inline void palmtx_keys_init(void) {} +#endif /****************************************************************************** * NAND Flash ******************************************************************************/ +#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE) static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { @@ -482,36 +301,17 @@ static struct platform_device palmtx_nand = { } }; -/****************************************************************************** - * Power management - standby - ******************************************************************************/ -static void __init palmtx_pm_init(void) +static void __init palmtx_nand_init(void) { - static u32 resume[] = { - 0xe3a00101, /* mov r0, #0x40000000 */ - 0xe380060f, /* orr r0, r0, #0x00f00000 */ - 0xe590f008, /* ldr pc, [r0, #0x08] */ - }; - - /* copy the bootloader */ - memcpy(phys_to_virt(PALMTX_STR_BASE), resume, sizeof(resume)); + platform_device_register(&palmtx_nand); } +#else +static inline void palmtx_nand_init(void) {} +#endif /****************************************************************************** * Machine init ******************************************************************************/ -static struct platform_device *devices[] __initdata = { -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) - &palmtx_pxa_keys, -#endif - &palmtx_backlight, - &power_supply, - &palmtx_asoc, - &palmtx_gpio_vbus, - &palmtx_flash, - &palmtx_nand, -}; - static struct map_desc palmtx_io_desc[] __initdata = { { .virtual = PALMTX_PCMCIA_VIRT, @@ -537,34 +337,29 @@ static void __init palmtx_map_io(void) iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc)); } -/* setup udc GPIOs initial state */ -static void __init palmtx_udc_init(void) -{ - if (!gpio_request(GPIO_NR_PALMTX_USB_PULLUP, "UDC Vbus")) { - gpio_direction_output(GPIO_NR_PALMTX_USB_PULLUP, 1); - gpio_free(GPIO_NR_PALMTX_USB_PULLUP); - } -} - - static void __init palmtx_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config)); - pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - palmtx_pm_init(); - set_pxa_fb_info(&palmtx_lcd_screen); - pxa_set_mci_info(&palmtx_mci_platform_data); - palmtx_udc_init(); - pxa_set_ac97_info(&palmtx_ac97_pdata); - pxa_set_ficp_info(&palmtx_ficp_platform_data); - pxa_set_keypad_info(&palmtx_keypad_platform_data); - wm97xx_bat_set_pdata(&wm97xx_batt_pdata); - - platform_add_devices(devices, ARRAY_SIZE(devices)); + palm27x_mmc_init(GPIO_NR_PALMTX_SD_DETECT_N, GPIO_NR_PALMTX_SD_READONLY, + GPIO_NR_PALMTX_SD_POWER, 0); + palm27x_pm_init(PALMTX_STR_BASE); + palm27x_lcd_init(-1, &palm_320x480_lcd_mode); + palm27x_udc_init(GPIO_NR_PALMTX_USB_DETECT_N, + GPIO_NR_PALMTX_USB_PULLUP, 1); + palm27x_irda_init(GPIO_NR_PALMTX_IR_DISABLE); + palm27x_ac97_init(PALMTX_BAT_MIN_VOLTAGE, PALMTX_BAT_MAX_VOLTAGE, + GPIO_NR_PALMTX_EARPHONE_DETECT, 95); + palm27x_pwm_init(GPIO_NR_PALMTX_BL_POWER, GPIO_NR_PALMTX_LCD_POWER); + palm27x_power_init(GPIO_NR_PALMTX_POWER_DETECT, -1); + palm27x_pmic_init(); + palmtx_kpc_init(); + palmtx_keys_init(); + palmtx_nor_init(); + palmtx_nand_init(); } MACHINE_START(PALMTX, "Palm T|X") diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 3a7925ca394..87e4b1044e0 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -27,7 +27,7 @@ #include <linux/pda_power.h> #include <linux/pwm_backlight.h> #include <linux/gpio.h> -#include <linux/wm97xx_batt.h> +#include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> @@ -44,6 +44,7 @@ #include <mach/pxa27x_keypad.h> #include <mach/udc.h> #include <mach/palmasoc.h> +#include <mach/palm27x.h> #include <mach/pm.h> @@ -109,21 +110,9 @@ static unsigned long palmz72_pin_config[] __initdata = { }; /****************************************************************************** - * SD/MMC card controller - ******************************************************************************/ -/* SD_POWER is not actually power, but it is more like chip - * select, i.e. it is inverted */ -static struct pxamci_platform_data palmz72_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_PALMZ72_SD_DETECT_N, - .gpio_card_ro = GPIO_NR_PALMZ72_SD_RO, - .gpio_power = GPIO_NR_PALMZ72_SD_POWER_N, - .gpio_power_invert = 1, -}; - -/****************************************************************************** * GPIO keyboard ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) static unsigned int palmz72_matrix_keys[] = { KEY(0, 0, KEY_POWER), KEY(0, 1, KEY_F1), @@ -149,77 +138,18 @@ static struct pxa27x_keypad_platform_data palmz72_keypad_platform_data = { .debounce_interval = 30, }; -/****************************************************************************** - * Backlight - ******************************************************************************/ -static int palmz72_backlight_init(struct device *dev) +static void __init palmz72_kpc_init(void) { - int ret; - - ret = gpio_request(GPIO_NR_PALMZ72_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_PALMZ72_BL_POWER, 0); - if (ret) - goto err2; - ret = gpio_request(GPIO_NR_PALMZ72_LCD_POWER, "LCD POWER"); - if (ret) - goto err2; - ret = gpio_direction_output(GPIO_NR_PALMZ72_LCD_POWER, 0); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMZ72_LCD_POWER); -err2: - gpio_free(GPIO_NR_PALMZ72_BL_POWER); -err: - return ret; -} - -static int palmz72_backlight_notify(struct device *dev, int brightness) -{ - gpio_set_value(GPIO_NR_PALMZ72_BL_POWER, brightness); - gpio_set_value(GPIO_NR_PALMZ72_LCD_POWER, brightness); - return brightness; -} - -static void palmz72_backlight_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMZ72_BL_POWER); - gpio_free(GPIO_NR_PALMZ72_LCD_POWER); + pxa_set_keypad_info(&palmz72_keypad_platform_data); } - -static struct platform_pwm_backlight_data palmz72_backlight_data = { - .pwm_id = 0, - .max_brightness = PALMZ72_MAX_INTENSITY, - .dft_brightness = PALMZ72_MAX_INTENSITY, - .pwm_period_ns = PALMZ72_PERIOD_NS, - .init = palmz72_backlight_init, - .notify = palmz72_backlight_notify, - .exit = palmz72_backlight_exit, -}; - -static struct platform_device palmz72_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &pxa27x_device_pwm0.dev, - .platform_data = &palmz72_backlight_data, - }, -}; - -/****************************************************************************** - * IrDA - ******************************************************************************/ -static struct pxaficp_platform_data palmz72_ficp_platform_data = { - .gpio_pwdown = GPIO_NR_PALMZ72_IR_DISABLE, - .transceiver_cap = IR_SIRMODE | IR_OFF, -}; +#else +static inline void palmz72_kpc_init(void) {} +#endif /****************************************************************************** * LEDs ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) static struct gpio_led gpio_leds[] = { { .name = "palmz72:green:led", @@ -241,139 +171,13 @@ static struct platform_device palmz72_leds = { } }; -/****************************************************************************** - * UDC - ******************************************************************************/ -static struct gpio_vbus_mach_info palmz72_udc_info = { - .gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N, - .gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP, -}; - -static struct platform_device palmz72_gpio_vbus = { - .name = "gpio-vbus", - .id = -1, - .dev = { - .platform_data = &palmz72_udc_info, - }, -}; - -/****************************************************************************** - * Power supply - ******************************************************************************/ -static int power_supply_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_PALMZ72_POWER_DETECT, "CABLE_STATE_AC"); - if (ret) - goto err1; - ret = gpio_direction_input(GPIO_NR_PALMZ72_POWER_DETECT); - if (ret) - goto err2; - - ret = gpio_request(GPIO_NR_PALMZ72_USB_DETECT_N, "CABLE_STATE_USB"); - if (ret) - goto err2; - ret = gpio_direction_input(GPIO_NR_PALMZ72_USB_DETECT_N); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMZ72_USB_DETECT_N); -err2: - gpio_free(GPIO_NR_PALMZ72_POWER_DETECT); -err1: - return ret; -} - -static int palmz72_is_ac_online(void) -{ - return gpio_get_value(GPIO_NR_PALMZ72_POWER_DETECT); -} - -static int palmz72_is_usb_online(void) +static void __init palmz72_leds_init(void) { - return !gpio_get_value(GPIO_NR_PALMZ72_USB_DETECT_N); + platform_device_register(&palmz72_leds); } - -static void power_supply_exit(struct device *dev) -{ - gpio_free(GPIO_NR_PALMZ72_USB_DETECT_N); - gpio_free(GPIO_NR_PALMZ72_POWER_DETECT); -} - -static char *palmz72_supplicants[] = { - "main-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = palmz72_is_ac_online, - .is_usb_online = palmz72_is_usb_online, - .exit = power_supply_exit, - .supplied_to = palmz72_supplicants, - .num_supplicants = ARRAY_SIZE(palmz72_supplicants), -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, -}; - -/****************************************************************************** - * WM97xx battery - ******************************************************************************/ -static struct wm97xx_batt_info wm97xx_batt_pdata = { - .batt_aux = WM97XX_AUX_ID3, - .temp_aux = WM97XX_AUX_ID2, - .charge_gpio = -1, - .max_voltage = PALMZ72_BAT_MAX_VOLTAGE, - .min_voltage = PALMZ72_BAT_MIN_VOLTAGE, - .batt_mult = 1000, - .batt_div = 414, - .temp_mult = 1, - .temp_div = 1, - .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, - .batt_name = "main-batt", -}; - -/****************************************************************************** - * aSoC audio - ******************************************************************************/ -static struct platform_device palmz72_asoc = { - .name = "palm27x-asoc", - .id = -1, -}; - -/****************************************************************************** - * Framebuffer - ******************************************************************************/ -static struct pxafb_mode_info palmz72_lcd_modes[] = { -{ - .pixclock = 115384, - .xres = 320, - .yres = 320, - .bpp = 16, - - .left_margin = 27, - .right_margin = 7, - .upper_margin = 7, - .lower_margin = 8, - - .hsync_len = 6, - .vsync_len = 1, -}, -}; - -static struct pxafb_mach_info palmz72_lcd_screen = { - .modes = palmz72_lcd_modes, - .num_modes = ARRAY_SIZE(palmz72_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, -}; +#else +static inline void palmz72_leds_init(void) {} +#endif #ifdef CONFIG_PM @@ -452,40 +256,26 @@ device_initcall(palmz72_pm_init); /****************************************************************************** * Machine init ******************************************************************************/ -static struct platform_device *devices[] __initdata = { - &palmz72_backlight, - &palmz72_leds, - &palmz72_asoc, - &power_supply, - &palmz72_gpio_vbus, -}; - -/* setup udc GPIOs initial state */ -static void __init palmz72_udc_init(void) -{ - if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) { - gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0); - gpio_free(GPIO_NR_PALMZ72_USB_PULLUP); - } -} - static void __init palmz72_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); - pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - set_pxa_fb_info(&palmz72_lcd_screen); - pxa_set_mci_info(&palmz72_mci_platform_data); - palmz72_udc_init(); - pxa_set_ac97_info(NULL); - pxa_set_ficp_info(&palmz72_ficp_platform_data); - pxa_set_keypad_info(&palmz72_keypad_platform_data); - wm97xx_bat_set_pdata(&wm97xx_batt_pdata); - - platform_add_devices(devices, ARRAY_SIZE(devices)); + palm27x_mmc_init(GPIO_NR_PALMZ72_SD_DETECT_N, GPIO_NR_PALMZ72_SD_RO, + GPIO_NR_PALMZ72_SD_POWER_N, 1); + palm27x_lcd_init(-1, &palm_320x320_lcd_mode); + palm27x_udc_init(GPIO_NR_PALMZ72_USB_DETECT_N, + GPIO_NR_PALMZ72_USB_PULLUP, 0); + palm27x_irda_init(GPIO_NR_PALMZ72_IR_DISABLE); + palm27x_ac97_init(PALMZ72_BAT_MIN_VOLTAGE, PALMZ72_BAT_MAX_VOLTAGE, + -1, 113); + palm27x_pwm_init(-1, -1); + palm27x_power_init(-1, -1); + palm27x_pmic_init(); + palmz72_kpc_init(); + palmz72_leds_init(); } MACHINE_START(PALMZ72, "Palm Zire72") diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index bc2758b5444..55e8fcde014 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -43,7 +43,6 @@ #include <mach/irda.h> #include <mach/poodle.h> #include <mach/pxafb.h> -#include <mach/sharpsl.h> #include <mach/pxa2xx_spi.h> #include <plat/i2c.h> @@ -53,7 +52,6 @@ #include "generic.h" #include "devices.h" -#include "sharpsl.h" static unsigned long poodle_pin_config[] __initdata = { /* I/O */ diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 0b9ad30bfd5..de53f2e4aa3 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -322,6 +322,7 @@ void __init pxa26x_init_irq(void) static struct platform_device *pxa25x_devices[] __initdata = { &pxa25x_device_udc, + &pxa_device_pmu, &pxa_device_i2s, &sa1100_device_rtc, &pxa25x_device_ssp, diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index c059dac02b6..12e5b9f01e6 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -383,6 +383,7 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, + &pxa_device_pmu, &pxa_device_i2s, &sa1100_device_rtc, &pxa_device_rtc, diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f544e58e153..fa0014847c7 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -52,7 +52,7 @@ static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; /* crystal frequency to HSIO bus frequency multiplier (HSS) */ -static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; +static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; /* * Get the clock frequency as reflected by CCSR and the turbo flag. @@ -552,11 +552,23 @@ static void pxa_unmask_ext_wakeup(unsigned int irq) PECR |= PECR_IE(irq - IRQ_WAKEUP0); } +static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type) +{ + if (flow_type & IRQ_TYPE_EDGE_RISING) + PWER |= 1 << (irq - IRQ_WAKEUP0); + + if (flow_type & IRQ_TYPE_EDGE_FALLING) + PWER |= 1 << (irq - IRQ_WAKEUP0 + 2); + + return 0; +} + static struct irq_chip pxa_ext_wakeup_chip = { .name = "WAKEUP", .ack = pxa_ack_ext_wakeup, .mask = pxa_mask_ext_wakeup, .unmask = pxa_unmask_ext_wakeup, + .set_type = pxa_set_ext_wakeup_type, }; static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) @@ -596,6 +608,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, + &pxa_device_pmu, &pxa_device_i2s, &sa1100_device_rtc, &pxa_device_rtc, diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index d4b61b3f08f..67e04f4e07c 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -745,13 +745,32 @@ static int raumfeld_is_usb_online(void) static char *raumfeld_power_supplicants[] = { "ds2760-battery.0" }; +static void raumfeld_power_signal_charged(void) +{ + struct power_supply *psy = + power_supply_get_by_name(raumfeld_power_supplicants[0]); + + if (psy) + power_supply_set_battery_charged(psy); +} + +static int raumfeld_power_resume(void) +{ + /* check if GPIO_CHARGE_DONE went low while we were sleeping */ + if (!gpio_get_value(GPIO_CHARGE_DONE)) + raumfeld_power_signal_charged(); + + return 0; +} + static struct pda_power_pdata power_supply_info = { .init = power_supply_init, .is_ac_online = raumfeld_is_ac_online, .is_usb_online = raumfeld_is_usb_online, .exit = power_supply_exit, .supplied_to = raumfeld_power_supplicants, - .num_supplicants = ARRAY_SIZE(raumfeld_power_supplicants) + .num_supplicants = ARRAY_SIZE(raumfeld_power_supplicants), + .resume = raumfeld_power_resume, }; static struct resource power_supply_resources[] = { @@ -766,13 +785,7 @@ static struct resource power_supply_resources[] = { static irqreturn_t charge_done_irq(int irq, void *dev_id) { - struct power_supply *psy; - - psy = power_supply_get_by_name("ds2760-battery.0"); - - if (psy) - power_supply_set_battery_charged(psy); - + raumfeld_power_signal_charged(); return IRQ_HANDLED; } diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h deleted file mode 100644 index 0cc1203c5be..00000000000 --- a/arch/arm/mach-pxa/sharpsl.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2004-2005 Richard Purdie - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <mach/sharpsl_pm.h> - -/* - * SharpSL Battery/PM Driver - */ -#define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x)) - -/* MAX1111 Channel Definitions */ -#define MAX1111_BATT_VOLT 4u -#define MAX1111_BATT_TEMP 2u -#define MAX1111_ACIN_VOLT 6u - -extern struct battery_thresh sharpsl_battery_levels_acin[]; -extern struct battery_thresh sharpsl_battery_levels_noac[]; -int sharpsl_pm_pxa_read_max1111(int channel); - - diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index cb4767251f3..8fed027b12d 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -29,11 +29,8 @@ #include <mach/pm.h> #include <mach/pxa2xx-regs.h> #include <mach/regs-rtc.h> -#include <mach/sharpsl.h> #include <mach/sharpsl_pm.h> -#include "sharpsl.h" - /* * Constants */ @@ -180,17 +177,12 @@ int sharpsl_pm_pxa_read_max1111(int channel) if (machine_is_tosa()) return 0; -#ifdef CONFIG_CORGI_SSP_DEPRECATED - return corgi_ssp_max1111_get((channel << MAXCTRL_SEL_SH) | MAXCTRL_PD0 | MAXCTRL_PD1 - | MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR); -#else extern int max1111_read_channel(int); /* max1111 accepts channels from 0-3, however, * it is encoded from 0-7 here in the code. */ return max1111_read_channel(channel >> 1); -#endif } static int get_percentage(int voltage) @@ -277,21 +269,6 @@ static void sharpsl_battery_thread(struct work_struct *private_) dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage, sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies); -#ifdef CONFIG_BACKLIGHT_CORGI - /* If battery is low. limit backlight intensity to save power. */ - if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) - && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) - || (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) { - if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) { - sharpsl_pm.machinfo->backlight_limit(1); - sharpsl_pm.flags |= SHARPSL_BL_LIMIT; - } - } else if (sharpsl_pm.flags & SHARPSL_BL_LIMIT) { - sharpsl_pm.machinfo->backlight_limit(0); - sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT; - } -#endif - /* Suspend if critical battery level */ if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL) diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 2ed95f369cf..52c30b01a67 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -339,10 +339,6 @@ ENTRY(pxa_cpu_resume) mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB -#ifdef CONFIG_XSCALE_CACHE_ERRATA - bic r9, r9, #0x0004 @ see cpu_xscale_proc_init -#endif - mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. mcr p15, 0, r4, c15, c1, 0 @ CP access reg mcr p15, 0, r5, c13, c0, 0 @ PID @@ -368,9 +364,6 @@ sleep_save_sp: .text resume_after_mmu: -#ifdef CONFIG_XSCALE_CACHE_ERRATA - bl cpu_xscale_proc_init -#endif ldmfd sp!, {r2, r3} #ifndef CONFIG_IWMMXT mar acc0, r2, r3 diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 51756c72355..1cd99cb87bb 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -18,14 +18,15 @@ #include <linux/gpio_keys.h> #include <linux/gpio.h> #include <linux/leds.h> -#include <linux/mtd/physmap.h> #include <linux/i2c.h> #include <linux/i2c/pca953x.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/spi/corgi_lcd.h> +#include <linux/mtd/physmap.h> #include <linux/mtd/sharpsl.h> #include <linux/input/matrix_keypad.h> +#include <linux/regulator/machine.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -33,22 +34,25 @@ #include <asm/mach/sharpsl_param.h> #include <asm/hardware/scoop.h> - #include <mach/pxa27x.h> #include <mach/pxa27x-udc.h> #include <mach/reset.h> -#include <plat/i2c.h> #include <mach/irda.h> #include <mach/mmc.h> #include <mach/ohci.h> #include <mach/pxafb.h> #include <mach/pxa2xx_spi.h> #include <mach/spitz.h> +#include <mach/sharpsl_pm.h> + +#include <plat/i2c.h> #include "generic.h" #include "devices.h" -#include "sharpsl.h" +/****************************************************************************** + * Pin configuration + ******************************************************************************/ static unsigned long spitz_pin_config[] __initdata = { /* Chip Selects */ GPIO78_nCS_2, /* SCOOP #2 */ @@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, /* SPITZ_GPIO_RESET */ }; -/* - * Spitz SCOOP Device #1 - */ -static struct resource spitz_scoop_resources[] = { + +/****************************************************************************** + * Scoop GPIO expander + ******************************************************************************/ +#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE) +/* SCOOP Device #1 */ +static struct resource spitz_scoop_1_resources[] = { [0] = { .start = 0x10800000, .end = 0x10800fff, @@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = { }, }; -static struct scoop_config spitz_scoop_setup = { +static struct scoop_config spitz_scoop_1_setup = { .io_dir = SPITZ_SCP_IO_DIR, .io_out = SPITZ_SCP_IO_OUT, .suspend_clr = SPITZ_SCP_SUS_CLR, @@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = { .gpio_base = SPITZ_SCP_GPIO_BASE, }; -struct platform_device spitzscoop_device = { +struct platform_device spitz_scoop_1_device = { .name = "sharp-scoop", .id = 0, .dev = { - .platform_data = &spitz_scoop_setup, + .platform_data = &spitz_scoop_1_setup, }, - .num_resources = ARRAY_SIZE(spitz_scoop_resources), - .resource = spitz_scoop_resources, + .num_resources = ARRAY_SIZE(spitz_scoop_1_resources), + .resource = spitz_scoop_1_resources, }; -/* - * Spitz SCOOP Device #2 - */ -static struct resource spitz_scoop2_resources[] = { +/* SCOOP Device #2 */ +static struct resource spitz_scoop_2_resources[] = { [0] = { .start = 0x08800040, .end = 0x08800fff, @@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = { }, }; -static struct scoop_config spitz_scoop2_setup = { +static struct scoop_config spitz_scoop_2_setup = { .io_dir = SPITZ_SCP2_IO_DIR, .io_out = SPITZ_SCP2_IO_OUT, .suspend_clr = SPITZ_SCP2_SUS_CLR, @@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = { .gpio_base = SPITZ_SCP2_GPIO_BASE, }; -struct platform_device spitzscoop2_device = { +struct platform_device spitz_scoop_2_device = { .name = "sharp-scoop", .id = 1, .dev = { - .platform_data = &spitz_scoop2_setup, + .platform_data = &spitz_scoop_2_setup, }, - .num_resources = ARRAY_SIZE(spitz_scoop2_resources), - .resource = spitz_scoop2_resources, + .num_resources = ARRAY_SIZE(spitz_scoop_2_resources), + .resource = spitz_scoop_2_resources, }; -#define SPITZ_PWR_SD 0x01 -#define SPITZ_PWR_CF 0x02 +static void __init spitz_scoop_init(void) +{ + platform_device_register(&spitz_scoop_1_device); + + /* Akita doesn't have the second SCOOP chip */ + if (!machine_is_akita()) + platform_device_register(&spitz_scoop_2_device); +} /* Power control is shared with between one of the CF slots and SD */ -static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr) +static void spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) { - unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR); + unsigned short cpr; + unsigned long flags; - if (new_cpr & 0x0007) { + if (new_cpr & 0x7) { gpio_set_value(SPITZ_GPIO_CF_POWER, 1); - if (!(cpr & 0x0002) && !(cpr & 0x0004)) - mdelay(5); - if (device == SPITZ_PWR_CF) - cpr |= 0x0002; - if (device == SPITZ_PWR_SD) - cpr |= 0x0004; - write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr); - } else { - if (device == SPITZ_PWR_CF) - cpr &= ~0x0002; - if (device == SPITZ_PWR_SD) - cpr &= ~0x0004; - if (!(cpr & 0x0002) && !(cpr & 0x0004)) { - write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000); - mdelay(1); - gpio_set_value(SPITZ_GPIO_CF_POWER, 0); - } else { - write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr); - } + mdelay(5); + } + + local_irq_save(flags); + + cpr = read_scoop_reg(&spitz_scoop_1_device.dev, SCOOP_CPR); + + if (enable & new_cpr) + cpr |= new_cpr; + else + cpr &= ~enable; + + write_scoop_reg(&spitz_scoop_1_device.dev, SCOOP_CPR, cpr); + + local_irq_restore(flags); + + if (!(cpr & 0x7)) { + mdelay(1); + gpio_set_value(SPITZ_GPIO_CF_POWER, 0); } } -static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr) +#else +static inline void spitz_scoop_init(void) {} +static inline void spitz_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {} +#endif + +/****************************************************************************** + * PCMCIA + ******************************************************************************/ +#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE) +static void spitz_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr) { /* Only need to override behaviour for slot 0 */ if (nr == 0) - spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr); + spitz_card_pwr_ctrl( + cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr); else write_scoop_reg(scoop, SCOOP_CPR, cpr); } static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = { -{ - .dev = &spitzscoop_device.dev, - .irq = SPITZ_IRQ_GPIO_CF_IRQ, - .cd_irq = SPITZ_IRQ_GPIO_CF_CD, - .cd_irq_str = "PCMCIA0 CD", -},{ - .dev = &spitzscoop2_device.dev, - .irq = SPITZ_IRQ_GPIO_CF2_IRQ, - .cd_irq = -1, -}, + { + .dev = &spitz_scoop_1_device.dev, + .irq = SPITZ_IRQ_GPIO_CF_IRQ, + .cd_irq = SPITZ_IRQ_GPIO_CF_CD, + .cd_irq_str = "PCMCIA0 CD", + }, { + .dev = &spitz_scoop_2_device.dev, + .irq = SPITZ_IRQ_GPIO_CF2_IRQ, + .cd_irq = -1, + }, }; static struct scoop_pcmcia_config spitz_pcmcia_config = { - .devs = &spitz_pcmcia_scoop[0], - .num_devs = 2, - .power_ctrl = spitz_pcmcia_pwr, + .devs = &spitz_pcmcia_scoop[0], + .num_devs = 2, + .power_ctrl = spitz_pcmcia_pwr, }; -EXPORT_SYMBOL(spitzscoop_device); -EXPORT_SYMBOL(spitzscoop2_device); +static void __init spitz_pcmcia_init(void) +{ + /* Akita has only one PCMCIA slot used */ + if (machine_is_akita()) + spitz_pcmcia_config.num_devs = 1; + + platform_scoop_config = &spitz_pcmcia_config; +} +#else +static inline void spitz_pcmcia_init(void) {} +#endif + +/****************************************************************************** + * GPIO keyboard + ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE) -/* - * Spitz Keyboard Device - */ #define SPITZ_KEY_CALENDAR KEY_F1 #define SPITZ_KEY_ADDRESS KEY_F2 #define SPITZ_KEY_FN KEY_F3 @@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device); #define SPITZ_KEY_OK KEY_F11 #define SPITZ_KEY_MENU KEY_F12 -static const uint32_t spitzkbd_keymap[] = { +static const uint32_t spitz_keymap[] = { KEY(0, 0, KEY_LEFTCTRL), KEY(0, 1, KEY_1), KEY(0, 2, KEY_3), @@ -330,36 +363,47 @@ static const uint32_t spitzkbd_keymap[] = { KEY(6, 8, KEY_RIGHT), }; -static const struct matrix_keymap_data spitzkbd_keymap_data = { - .keymap = spitzkbd_keymap, - .keymap_size = ARRAY_SIZE(spitzkbd_keymap), +static const struct matrix_keymap_data spitz_keymap_data = { + .keymap = spitz_keymap, + .keymap_size = ARRAY_SIZE(spitz_keymap), }; -static const uint32_t spitzkbd_row_gpios[] = +static const uint32_t spitz_row_gpios[] = { 12, 17, 91, 34, 36, 38, 39 }; -static const uint32_t spitzkbd_col_gpios[] = +static const uint32_t spitz_col_gpios[] = { 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 }; -static struct matrix_keypad_platform_data spitzkbd_pdata = { - .keymap_data = &spitzkbd_keymap_data, - .row_gpios = spitzkbd_row_gpios, - .col_gpios = spitzkbd_col_gpios, - .num_row_gpios = ARRAY_SIZE(spitzkbd_row_gpios), - .num_col_gpios = ARRAY_SIZE(spitzkbd_col_gpios), +static struct matrix_keypad_platform_data spitz_mkp_pdata = { + .keymap_data = &spitz_keymap_data, + .row_gpios = spitz_row_gpios, + .col_gpios = spitz_col_gpios, + .num_row_gpios = ARRAY_SIZE(spitz_row_gpios), + .num_col_gpios = ARRAY_SIZE(spitz_col_gpios), .col_scan_delay_us = 10, .debounce_ms = 10, .wakeup = 1, }; -static struct platform_device spitzkbd_device = { +static struct platform_device spitz_mkp_device = { .name = "matrix-keypad", .id = -1, .dev = { - .platform_data = &spitzkbd_pdata, + .platform_data = &spitz_mkp_pdata, }, }; +static void __init spitz_mkp_init(void) +{ + platform_device_register(&spitz_mkp_device); +} +#else +static inline void spitz_mkp_init(void) {} +#endif +/****************************************************************************** + * GPIO keys + ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button spitz_gpio_keys[] = { { .type = EV_PWR, @@ -396,10 +440,18 @@ static struct platform_device spitz_gpio_keys_device = { }, }; +static void __init spitz_keys_init(void) +{ + platform_device_register(&spitz_gpio_keys_device); +} +#else +static inline void spitz_keys_init(void) {} +#endif -/* - * Spitz LEDs - */ +/****************************************************************************** + * LEDs + ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) static struct gpio_led spitz_gpio_leds[] = { { .name = "spitz:amber:charge", @@ -418,20 +470,27 @@ static struct gpio_led_platform_data spitz_gpio_leds_info = { .num_leds = ARRAY_SIZE(spitz_gpio_leds), }; -static struct platform_device spitzled_device = { +static struct platform_device spitz_led_device = { .name = "leds-gpio", .id = -1, .dev = { - .platform_data = &spitz_gpio_leds_info, + .platform_data = &spitz_gpio_leds_info, }, }; -#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) -static struct pxa2xx_spi_master spitz_spi_info = { - .num_chipselect = 3, -}; +static void __init spitz_leds_init(void) +{ + platform_device_register(&spitz_led_device); +} +#else +static inline void spitz_leds_init(void) {} +#endif -static void spitz_wait_for_hsync(void) +/****************************************************************************** + * SSP Devices + ******************************************************************************/ +#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) +static void spitz_ads7846_wait_for_hsync(void) { while (gpio_get_value(SPITZ_GPIO_HSYNC)) cpu_relax(); @@ -447,7 +506,7 @@ static struct ads7846_platform_data spitz_ads7846_info = { .y_plate_ohms = 486, .pressure_max = 1024, .gpio_pendown = SPITZ_GPIO_TP_INT, - .wait_for_sync = spitz_wait_for_hsync, + .wait_for_sync = spitz_ads7846_wait_for_hsync, }; static struct pxa2xx_spi_chip spitz_ads7846_chip = { @@ -485,72 +544,88 @@ static struct pxa2xx_spi_chip spitz_max1111_chip = { static struct spi_board_info spitz_spi_devices[] = { { - .modalias = "ads7846", - .max_speed_hz = 1200000, - .bus_num = 2, - .chip_select = 0, - .platform_data = &spitz_ads7846_info, - .controller_data= &spitz_ads7846_chip, - .irq = gpio_to_irq(SPITZ_GPIO_TP_INT), + .modalias = "ads7846", + .max_speed_hz = 1200000, + .bus_num = 2, + .chip_select = 0, + .platform_data = &spitz_ads7846_info, + .controller_data = &spitz_ads7846_chip, + .irq = gpio_to_irq(SPITZ_GPIO_TP_INT), }, { - .modalias = "corgi-lcd", - .max_speed_hz = 50000, - .bus_num = 2, - .chip_select = 1, - .platform_data = &spitz_lcdcon_info, - .controller_data= &spitz_lcdcon_chip, + .modalias = "corgi-lcd", + .max_speed_hz = 50000, + .bus_num = 2, + .chip_select = 1, + .platform_data = &spitz_lcdcon_info, + .controller_data = &spitz_lcdcon_chip, }, { - .modalias = "max1111", - .max_speed_hz = 450000, - .bus_num = 2, - .chip_select = 2, - .controller_data= &spitz_max1111_chip, + .modalias = "max1111", + .max_speed_hz = 450000, + .bus_num = 2, + .chip_select = 2, + .controller_data = &spitz_max1111_chip, }, }; -static void __init spitz_init_spi(void) +static struct pxa2xx_spi_master spitz_spi_info = { + .num_chipselect = 3, +}; + +static void __init spitz_spi_init(void) { + struct corgi_lcd_platform_data *lcd_data = &spitz_lcdcon_info; + if (machine_is_akita()) { - spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; - spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; + lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; + lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; } pxa2xx_set_spi_info(2, &spitz_spi_info); spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices)); } #else -static inline void spitz_init_spi(void) {} +static inline void spitz_spi_init(void) {} #endif +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) /* - * MMC/SD Device - * - * The card detect interrupt isn't debounced so we delay it by 250ms - * to give the card a chance to fully insert/eject. + * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to + * give the card a chance to fully insert/eject. */ static void spitz_mci_setpower(struct device *dev, unsigned int vdd) { struct pxamci_platform_data* p_d = dev->platform_data; - if (( 1 << vdd) & p_d->ocr_mask) - spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004); + if ((1 << vdd) & p_d->ocr_mask) + spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V); else - spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000); + spitz_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0); } static struct pxamci_platform_data spitz_mci_platform_data = { .detect_delay_ms = 250, .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, - .setpower = spitz_mci_setpower, + .setpower = spitz_mci_setpower, .gpio_card_detect = SPITZ_GPIO_nSD_DETECT, .gpio_card_ro = SPITZ_GPIO_nSD_WP, .gpio_power = -1, }; +static void __init spitz_mmc_init(void) +{ + pxa_set_mci_info(&spitz_mci_platform_data); +} +#else +static inline void spitz_mmc_init(void) {} +#endif -/* - * USB Host (OHCI) - */ +/****************************************************************************** + * USB Host + ******************************************************************************/ +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) static int spitz_ohci_init(struct device *dev) { int err; @@ -559,9 +634,7 @@ static int spitz_ohci_init(struct device *dev) if (err) return err; - /* Only Port 2 is connected - * Setup USB Port 2 Output Control Register - */ + /* Only Port 2 is connected, setup USB Port 2 Output Control Register */ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1); @@ -580,67 +653,95 @@ static struct pxaohci_platform_data spitz_ohci_platform_data = { .power_budget = 150, }; +static void __init spitz_uhc_init(void) +{ + pxa_set_ohci_info(&spitz_ohci_platform_data); +} +#else +static inline void spitz_uhc_init(void) {} +#endif -/* - * Irda - */ - +/****************************************************************************** + * IrDA + ******************************************************************************/ +#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE) static struct pxaficp_platform_data spitz_ficp_platform_data = { -/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */ .transceiver_cap = IR_SIRMODE | IR_OFF, }; +static void __init spitz_irda_init(void) +{ + if (machine_is_akita()) + spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON; + else + spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON; -/* - * Spitz PXA Framebuffer - */ + pxa_set_ficp_info(&spitz_ficp_platform_data); +} +#else +static inline void spitz_irda_init(void) {} +#endif +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct pxafb_mode_info spitz_pxafb_modes[] = { -{ - .pixclock = 19231, - .xres = 480, - .yres = 640, - .bpp = 16, - .hsync_len = 40, - .left_margin = 46, - .right_margin = 125, - .vsync_len = 3, - .upper_margin = 1, - .lower_margin = 0, - .sync = 0, -},{ - .pixclock = 134617, - .xres = 240, - .yres = 320, - .bpp = 16, - .hsync_len = 20, - .left_margin = 20, - .right_margin = 46, - .vsync_len = 2, - .upper_margin = 1, - .lower_margin = 0, - .sync = 0, -}, + { + .pixclock = 19231, + .xres = 480, + .yres = 640, + .bpp = 16, + .hsync_len = 40, + .left_margin = 46, + .right_margin = 125, + .vsync_len = 3, + .upper_margin = 1, + .lower_margin = 0, + .sync = 0, + }, { + .pixclock = 134617, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 20, + .left_margin = 20, + .right_margin = 46, + .vsync_len = 2, + .upper_margin = 1, + .lower_margin = 0, + .sync = 0, + }, }; static struct pxafb_mach_info spitz_pxafb_info = { - .modes = &spitz_pxafb_modes[0], - .num_modes = 2, + .modes = spitz_pxafb_modes, + .num_modes = ARRAY_SIZE(spitz_pxafb_modes), .fixed_modes = 1, .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING, }; -static struct mtd_partition sharpsl_nand_partitions[] = { +static void __init spitz_lcd_init(void) +{ + set_pxa_fb_info(&spitz_pxafb_info); +} +#else +static inline void spitz_lcd_init(void) {} +#endif + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE) +static struct mtd_partition spitz_nand_partitions[] = { { .name = "System Area", .offset = 0, .size = 7 * 1024 * 1024, - }, - { + }, { .name = "Root Filesystem", .offset = 7 * 1024 * 1024, - }, - { + }, { .name = "Home Filesystem", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL, @@ -649,37 +750,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = { static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; -static struct nand_bbt_descr sharpsl_bbt = { - .options = 0, - .offs = 4, - .len = 2, - .pattern = scan_ff_pattern +static struct nand_bbt_descr spitz_nand_bbt = { + .options = 0, + .offs = 4, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_ecclayout akita_oobinfo = { + .oobfree = { {0x08, 0x09} }, + .eccbytes = 24, + .eccpos = { + 0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11, + 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23, + 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37, + }, }; -static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = { - .badblock_pattern = &sharpsl_bbt, - .partitions = sharpsl_nand_partitions, - .nr_partitions = ARRAY_SIZE(sharpsl_nand_partitions), +static struct sharpsl_nand_platform_data spitz_nand_pdata = { + .badblock_pattern = &spitz_nand_bbt, + .partitions = spitz_nand_partitions, + .nr_partitions = ARRAY_SIZE(spitz_nand_partitions), }; -static struct resource sharpsl_nand_resources[] = { +static struct resource spitz_nand_resources[] = { { - .start = 0x0C000000, - .end = 0x0C000FFF, + .start = PXA_CS3_PHYS, + .end = PXA_CS3_PHYS + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; -static struct platform_device sharpsl_nand_device = { +static struct platform_device spitz_nand_device = { .name = "sharpsl-nand", .id = -1, - .resource = sharpsl_nand_resources, - .num_resources = ARRAY_SIZE(sharpsl_nand_resources), - .dev.platform_data = &sharpsl_nand_platform_data, + .resource = spitz_nand_resources, + .num_resources = ARRAY_SIZE(spitz_nand_resources), + .dev = { + .platform_data = &spitz_nand_pdata, + } }; +static void __init spitz_nand_init(void) +{ + if (machine_is_spitz()) { + spitz_nand_partitions[1].size = 5 * 1024 * 1024; + } else if (machine_is_akita()) { + spitz_nand_partitions[1].size = 58 * 1024 * 1024; + spitz_nand_bbt.len = 1; + spitz_nand_pdata.ecc_layout = &akita_oobinfo; + } else if (machine_is_borzoi()) { + spitz_nand_partitions[1].size = 32 * 1024 * 1024; + spitz_nand_bbt.len = 1; + spitz_nand_pdata.ecc_layout = &akita_oobinfo; + } + + platform_device_register(&spitz_nand_device); +} +#else +static inline void spitz_nand_init(void) {} +#endif -static struct mtd_partition sharpsl_rom_parts[] = { +/****************************************************************************** + * NOR Flash + ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition spitz_rom_parts[] = { { .name ="Boot PROM Filesystem", .offset = 0x00140000, @@ -687,37 +823,105 @@ static struct mtd_partition sharpsl_rom_parts[] = { }, }; -static struct physmap_flash_data sharpsl_rom_data = { +static struct physmap_flash_data spitz_rom_data = { .width = 2, - .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), - .parts = sharpsl_rom_parts, + .nr_parts = ARRAY_SIZE(spitz_rom_parts), + .parts = spitz_rom_parts, }; -static struct resource sharpsl_rom_resources[] = { +static struct resource spitz_rom_resources[] = { { - .start = 0x00000000, - .end = 0x007fffff, + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_8M - 1, .flags = IORESOURCE_MEM, }, }; -static struct platform_device sharpsl_rom_device = { - .name = "physmap-flash", - .id = -1, - .resource = sharpsl_rom_resources, - .num_resources = ARRAY_SIZE(sharpsl_rom_resources), - .dev.platform_data = &sharpsl_rom_data, +static struct platform_device spitz_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = spitz_rom_resources, + .num_resources = ARRAY_SIZE(spitz_rom_resources), + .dev = { + .platform_data = &spitz_rom_data, + }, }; -static struct platform_device *devices[] __initdata = { - &spitzscoop_device, - &spitzkbd_device, - &spitz_gpio_keys_device, - &spitzled_device, - &sharpsl_nand_device, - &sharpsl_rom_device, +static void __init spitz_nor_init(void) +{ + platform_device_register(&spitz_rom_device); +} +#else +static inline void spitz_nor_init(void) {} +#endif + +/****************************************************************************** + * GPIO expander + ******************************************************************************/ +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) +static struct pca953x_platform_data akita_pca953x_pdata = { + .gpio_base = AKITA_IOEXP_GPIO_BASE, }; +static struct i2c_board_info spitz_i2c_devs[] = { + { + .type = "wm8750", + .addr = 0x1b, + }, { + .type = "max7310", + .addr = 0x18, + .platform_data = &akita_pca953x_pdata, + }, +}; + +static struct regulator_consumer_supply isl6271a_consumers[] = { + { + .supply = "vcc_core", + } +}; + +static struct regulator_init_data isl6271a_info[] = { + { + .constraints = { + .name = "vcc_core range", + .min_uV = 850000, + .max_uV = 1600000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .consumer_supplies = isl6271a_consumers, + .num_consumer_supplies = ARRAY_SIZE(isl6271a_consumers), + } +}; + +static struct i2c_board_info spitz_pi2c_devs[] = { + { + .type = "isl6271a", + .addr = 0x0c, + .platform_data = &isl6271a_info, + }, +}; + +static void __init spitz_i2c_init(void) +{ + int size = ARRAY_SIZE(spitz_i2c_devs); + + /* Only Akita has the max7310 chip */ + if (!machine_is_akita()) + size--; + + pxa_set_i2c_info(NULL); + pxa27x_set_i2c_power_info(NULL); + i2c_register_board_info(0, spitz_i2c_devs, size); + i2c_register_board_info(1, ARRAY_AND_SIZE(spitz_pi2c_devs)); +} +#else +static inline void spitz_i2c_init(void) {} +#endif + +/****************************************************************************** + * Machine init + ******************************************************************************/ static void spitz_poweroff(void) { arm_machine_restart('g', NULL); @@ -726,26 +930,18 @@ static void spitz_poweroff(void) static void spitz_restart(char mode, const char *cmd) { /* Bootloader magic for a reboot */ - if((MSC0 & 0xffff0000) == 0x7ff00000) + if ((MSC0 & 0xffff0000) == 0x7ff00000) MSC0 = (MSC0 & 0xffff) | 0x7ee00000; spitz_poweroff(); } -static void __init common_init(void) +static void __init spitz_init(void) { init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0); pm_power_off = spitz_poweroff; arm_pm_restart = spitz_restart; - if (machine_is_spitz()) { - sharpsl_nand_partitions[1].size = 5 * 1024 * 1024; - } else if (machine_is_akita()) { - sharpsl_nand_partitions[1].size = 58 * 1024 * 1024; - } else if (machine_is_borzoi()) { - sharpsl_nand_partitions[1].size = 32 * 1024 * 1024; - } - PMCR = 0x00; /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */ @@ -757,91 +953,22 @@ static void __init common_init(void) pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - spitz_init_spi(); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - pxa_set_mci_info(&spitz_mci_platform_data); - pxa_set_ohci_info(&spitz_ohci_platform_data); - pxa_set_ficp_info(&spitz_ficp_platform_data); - set_pxa_fb_info(&spitz_pxafb_info); - pxa_set_i2c_info(NULL); + spitz_spi_init(); + spitz_scoop_init(); + spitz_mkp_init(); + spitz_keys_init(); + spitz_leds_init(); + spitz_mmc_init(); + spitz_pcmcia_init(); + spitz_irda_init(); + spitz_uhc_init(); + spitz_lcd_init(); + spitz_nor_init(); + spitz_nand_init(); + spitz_i2c_init(); } -#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI) -static struct nand_bbt_descr sharpsl_akita_bbt = { - .options = 0, - .offs = 4, - .len = 1, - .pattern = scan_ff_pattern -}; - -static struct nand_ecclayout akita_oobinfo = { - .eccbytes = 24, - .eccpos = { - 0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11, - 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23, - 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37}, - .oobfree = {{0x08, 0x09}} -}; -#endif - -#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI) -static void __init spitz_init(void) -{ - spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON; - -#ifdef CONFIG_MACH_BORZOI - if (machine_is_borzoi()) { - sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt; - sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo; - } -#endif - - platform_scoop_config = &spitz_pcmcia_config; - - common_init(); - - platform_device_register(&spitzscoop2_device); -} -#endif - -#ifdef CONFIG_MACH_AKITA -/* - * Akita IO Expander - */ -static struct pca953x_platform_data akita_ioexp = { - .gpio_base = AKITA_IOEXP_GPIO_BASE, -}; - -static struct i2c_board_info akita_i2c_board_info[] = { - { - .type = "max7310", - .addr = 0x18, - .platform_data = &akita_ioexp, - }, { - .type = "wm8750", - .addr = 0x1b, - }, -}; - -static void __init akita_init(void) -{ - spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON; - - sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt; - sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo; - - /* We just pretend the second element of the array doesn't exist */ - spitz_pcmcia_config.num_devs = 1; - platform_scoop_config = &spitz_pcmcia_config; - - i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info)); - - common_init(); -} -#endif - -static void __init fixup_spitz(struct machine_desc *desc, +static void __init spitz_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { sharpsl_save_param(); @@ -854,7 +981,7 @@ static void __init fixup_spitz(struct machine_desc *desc, MACHINE_START(SPITZ, "SHARP Spitz") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = fixup_spitz, + .fixup = spitz_fixup, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .init_machine = spitz_init, @@ -866,7 +993,7 @@ MACHINE_END MACHINE_START(BORZOI, "SHARP Borzoi") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = fixup_spitz, + .fixup = spitz_fixup, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .init_machine = spitz_init, @@ -878,10 +1005,10 @@ MACHINE_END MACHINE_START(AKITA, "SHARP Akita") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = fixup_spitz, + .fixup = spitz_fixup, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, - .init_machine = akita_init, + .init_machine = spitz_init, .timer = &pxa_timer, MACHINE_END #endif diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 4209ddf6da6..7fe74067d85 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -22,11 +22,10 @@ #include <asm/mach-types.h> #include <mach/hardware.h> -#include <mach/sharpsl.h> #include <mach/spitz.h> #include <mach/pxa27x.h> +#include <mach/sharpsl_pm.h> -#include "sharpsl.h" #include "generic.h" #define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */ @@ -178,11 +177,11 @@ unsigned long spitzpm_read_devdata(int type) case SHARPSL_STATUS_ACIN: return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0); case SHARPSL_STATUS_LOCK: - return READ_GPIO_BIT(sharpsl_pm.machinfo->gpio_batlock); + return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock); case SHARPSL_STATUS_CHRGFULL: - return READ_GPIO_BIT(sharpsl_pm.machinfo->gpio_batfull); + return gpio_get_value(sharpsl_pm.machinfo->gpio_batfull); case SHARPSL_STATUS_FATAL: - return READ_GPIO_BIT(sharpsl_pm.machinfo->gpio_fatal); + return gpio_get_value(sharpsl_pm.machinfo->gpio_fatal); case SHARPSL_ACIN_VOLT: return sharpsl_pm_pxa_read_max1111(MAX1111_ACIN_VOLT); case SHARPSL_BATT_TEMP: @@ -212,8 +211,6 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { .should_wakeup = spitz_should_wakeup, #if defined(CONFIG_LCD_CORGI) .backlight_limit = corgi_lcd_limit_intensity, -#elif defined(CONFIG_BACKLIGHT_CORGI) - .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index af40d2a12d3..a654d1e6b38 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -29,6 +29,7 @@ #include <linux/i2c/at24.h> #include <linux/smc91x.h> #include <linux/gpio.h> +#include <linux/leds.h> #include <asm/types.h> #include <asm/setup.h> @@ -62,37 +63,12 @@ #define SG2_GPIO_nSD_DETECT 90 #define SG2_SD_POWER_ENABLE 89 -static unsigned long stargate2_pin_config[] __initdata = { - - GPIO15_nCS_1, /* SRAM */ - /* SMC91x */ - GPIO80_nCS_4, - GPIO40_GPIO, /*cable detect?*/ +static unsigned long sg2_im2_unified_pin_config[] __initdata = { /* Device Identification for wakeup*/ GPIO102_GPIO, - - /* Button */ - GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH, - /* DA9030 */ GPIO1_GPIO, - /* Compact Flash */ - GPIO79_PSKTSEL, - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO85_nPCE_1, - GPIO54_nPCE_2, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - GPIO120_GPIO, /* Buff ctrl */ - GPIO108_GPIO, /* Power ctrl */ - GPIO82_GPIO, /* Reset */ - GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */ - /* MMC */ GPIO32_MMC_CLK, GPIO112_MMC_CMD, @@ -100,49 +76,44 @@ static unsigned long stargate2_pin_config[] __initdata = { GPIO109_MMC_DAT_1, GPIO110_MMC_DAT_2, GPIO111_MMC_DAT_3, - GPIO90_GPIO, /* nSD detect */ - GPIO89_GPIO, /* SD_POWER_ENABLE */ - /* Bluetooth */ - GPIO81_GPIO, /* reset */ - - /* cc2420 802.15.4 radio */ - GPIO22_GPIO, /* CC_RSTN (out)*/ - GPIO114_GPIO, /* CC_FIFO (in) */ - GPIO116_GPIO, /* CC_CCA (in) */ - GPIO0_GPIO, /* CC_FIFOP (in) */ - GPIO16_GPIO, /* CCSFD (in) */ - GPIO39_GPIO, /* CSn (out) */ + /* 802.15.4 radio - driver out of mainline */ + GPIO22_GPIO, /* CC_RSTN */ + GPIO114_GPIO, /* CC_FIFO */ + GPIO116_GPIO, /* CC_CCA */ + GPIO0_GPIO, /* CC_FIFOP */ + GPIO16_GPIO, /* CCSFD */ + GPIO115_GPIO, /* Power enable */ /* I2C */ GPIO117_I2C_SCL, GPIO118_I2C_SDA, /* SSP 3 - 802.15.4 radio */ - GPIO39_GPIO, /* chip select */ + GPIO39_GPIO, /* Chip Select */ GPIO34_SSP3_SCLK, GPIO35_SSP3_TXD, GPIO41_SSP3_RXD, - /* SSP 2 */ + /* SSP 2 to daughter boards */ GPIO11_SSP2_RXD, GPIO38_SSP2_TXD, GPIO36_SSP2_SCLK, GPIO37_GPIO, /* chip select */ - /* SSP 1 */ - GPIO26_SSP1_RXD, - GPIO25_SSP1_TXD, + /* SSP 1 - to daughter boards */ + GPIO24_GPIO, /* Chip Select */ GPIO23_SSP1_SCLK, - GPIO24_GPIO, /* chip select */ + GPIO25_SSP1_TXD, + GPIO26_SSP1_RXD, - /* BTUART */ + /* BTUART Basic Connector*/ GPIO42_BTUART_RXD, GPIO43_BTUART_TXD, GPIO44_BTUART_CTS, GPIO45_BTUART_RTS, - /* STUART */ + /* STUART - IM2 via debug board not sure on SG2*/ GPIO46_STUART_RXD, GPIO47_STUART_TXD, @@ -150,47 +121,17 @@ static unsigned long stargate2_pin_config[] __initdata = { GPIO96_GPIO, /* accelerometer interrupt */ GPIO99_GPIO, /* ADC interrupt */ - /* Connector pins specified as gpios */ - GPIO94_GPIO, /* large basic connector pin 14 */ - GPIO10_GPIO, /* large basic connector pin 23 */ - /* SHT15 */ GPIO100_GPIO, GPIO98_GPIO, -}; -/** - * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state - **/ -static int stargate2_reset_bluetooth(void) -{ - int err; - err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET"); - if (err) { - printk(KERN_ERR "Could not get gpio for bluetooth reset \n"); - return err; - } - gpio_direction_output(SG2_BT_RESET, 1); - mdelay(5); - /* now reset it - 5 msec minimum */ - gpio_set_value(SG2_BT_RESET, 0); - mdelay(10); - gpio_set_value(SG2_BT_RESET, 1); - gpio_free(SG2_BT_RESET); - return 0; -} + /* Basic sensor board */ + GPIO96_GPIO, /* accelerometer interrupt */ + GPIO99_GPIO, /* ADC interrupt */ -static struct led_info stargate2_leds[] = { - { - .name = "sg2:red", - .flags = DA9030_LED_RATE_ON, - }, { - .name = "sg2:blue", - .flags = DA9030_LED_RATE_ON, - }, { - .name = "sg2:green", - .flags = DA9030_LED_RATE_ON, - }, + /* Connector pins specified as gpios */ + GPIO94_GPIO, /* large basic connector pin 14 */ + GPIO10_GPIO, /* large basic connector pin 23 */ }; static struct sht15_platform_data platform_data_sht15 = { @@ -352,20 +293,184 @@ static struct regulator_init_data stargate2_ldo_init_data[] = { }, }; -static struct da903x_subdev_info stargate2_da9030_subdevs[] = { +static struct mtd_partition stargate2flash_partitions[] = { { - .name = "da903x-led", - .id = DA9030_ID_LED_2, - .platform_data = &stargate2_leds[0], + .name = "Bootloader", + .size = 0x00040000, + .offset = 0, + .mask_flags = 0, }, { - .name = "da903x-led", - .id = DA9030_ID_LED_3, - .platform_data = &stargate2_leds[2], + .name = "Kernel", + .size = 0x00200000, + .offset = 0x00040000, + .mask_flags = 0 }, { - .name = "da903x-led", - .id = DA9030_ID_LED_4, - .platform_data = &stargate2_leds[1], + .name = "Filesystem", + .size = 0x01DC0000, + .offset = 0x00240000, + .mask_flags = 0 + }, +}; + +static struct resource flash_resources = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct flash_platform_data stargate2_flash_data = { + .map_name = "cfi_probe", + .parts = stargate2flash_partitions, + .nr_parts = ARRAY_SIZE(stargate2flash_partitions), + .name = "PXA27xOnChipROM", + .width = 2, +}; + +static struct platform_device stargate2_flash_device = { + .name = "pxa2xx-flash", + .id = 0, + .dev = { + .platform_data = &stargate2_flash_data, + }, + .resource = &flash_resources, + .num_resources = 1, +}; + +static struct pxa2xx_spi_master pxa_ssp_master_0_info = { + .num_chipselect = 1, +}; + +static struct pxa2xx_spi_master pxa_ssp_master_1_info = { + .num_chipselect = 1, +}; + +static struct pxa2xx_spi_master pxa_ssp_master_2_info = { + .num_chipselect = 1, +}; + +/* An upcoming kernel change will scrap SFRM usage so these + * drivers have been moved to use gpio's via cs_control */ +static struct pxa2xx_spi_chip staccel_chip_info = { + .tx_threshold = 8, + .rx_threshold = 8, + .dma_burst_size = 8, + .timeout = 235, + .gpio_cs = 24, +}; + +static struct pxa2xx_spi_chip cc2420_info = { + .tx_threshold = 8, + .rx_threshold = 8, + .dma_burst_size = 8, + .timeout = 235, + .gpio_cs = 39, +}; + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "lis3l02dq", + .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */ + .bus_num = 1, + .chip_select = 0, + .controller_data = &staccel_chip_info, + .irq = IRQ_GPIO(96), }, { + .modalias = "cc2420", + .max_speed_hz = 6500000, + .bus_num = 3, + .chip_select = 0, + .controller_data = &cc2420_info, + }, +}; + +static void sg2_udc_command(int cmd) +{ + switch (cmd) { + case PXA2XX_UDC_CMD_CONNECT: + UP2OCR |= UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE; + break; + case PXA2XX_UDC_CMD_DISCONNECT: + UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE); + break; + } +} + +static struct i2c_pxa_platform_data i2c_pwr_pdata = { + .fast_mode = 1, +}; + +static struct i2c_pxa_platform_data i2c_pdata = { + .fast_mode = 1, +}; + +static void __init imote2_stargate2_init(void) +{ + + pxa2xx_mfp_config(ARRAY_AND_SIZE(sg2_im2_unified_pin_config)); + + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + + pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info); + pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info); + pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info); + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + + + pxa27x_set_i2c_power_info(&i2c_pwr_pdata); + pxa_set_i2c_info(&i2c_pdata); +} + +#ifdef CONFIG_MACH_INTELMOTE2 +/* As the the imote2 doesn't currently have a conventional SD slot + * there is no option to hotplug cards, making all this rather simple + */ +static int imote2_mci_get_ro(struct device *dev) +{ + return 0; +} + +/* Rather simple case as hotplugging not possible */ +static struct pxamci_platform_data imote2_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */ + .get_ro = imote2_mci_get_ro, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, +}; + +static struct gpio_led imote2_led_pins[] = { + { + .name = "imote2:red", + .gpio = 103, + .active_low = 1, + }, { + .name = "imote2:green", + .gpio = 104, + .active_low = 1, + }, { + .name = "imote2:blue", + .gpio = 105, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data imote2_led_data = { + .num_leds = ARRAY_SIZE(imote2_led_pins), + .leds = imote2_led_pins, +}; + +static struct platform_device imote2_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &imote2_led_data, + }, +}; + +static struct da903x_subdev_info imote2_da9030_subdevs[] = { + { .name = "da903x-regulator", .id = DA9030_ID_LDO2, .platform_data = &stargate2_ldo_init_data[vcc_bbio], @@ -428,9 +533,121 @@ static struct da903x_subdev_info stargate2_da9030_subdevs[] = { }, }; -static struct da903x_platform_data stargate2_da9030_pdata = { - .num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs), - .subdevs = stargate2_da9030_subdevs, +static struct da903x_platform_data imote2_da9030_pdata = { + .num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs), + .subdevs = imote2_da9030_subdevs, +}; + +static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { + { + .type = "da9030", + .addr = 0x49, + .platform_data = &imote2_da9030_pdata, + .irq = gpio_to_irq(1), + }, +}; + +static struct i2c_board_info __initdata imote2_i2c_board_info[] = { + { /* UCAM sensor board */ + .type = "max1239", + .addr = 0x35, + }, { /* ITS400 Sensor board only */ + .type = "max1363", + .addr = 0x34, + /* Through a nand gate - Also beware, on V2 sensor board the + * pull up resistors are missing. + */ + .irq = IRQ_GPIO(99), + }, { /* ITS400 Sensor board only */ + .type = "tsl2561", + .addr = 0x49, + /* Through a nand gate - Also beware, on V2 sensor board the + * pull up resistors are missing. + */ + .irq = IRQ_GPIO(99), + }, { /* ITS400 Sensor board only */ + .type = "tmp175", + .addr = 0x4A, + .irq = IRQ_GPIO(96), + }, { /* IMB400 Multimedia board */ + .type = "wm8940", + .addr = 0x1A, + }, +}; + +static unsigned long imote2_pin_config[] __initdata = { + + /* Button */ + GPIO91_GPIO, + + /* LEDS */ + GPIO103_GPIO, /* red led */ + GPIO104_GPIO, /* green led */ + GPIO105_GPIO, /* blue led */ +}; + +static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = { + .udc_command = sg2_udc_command, +}; + +static struct platform_device *imote2_devices[] = { + &stargate2_flash_device, + &imote2_leds, + &sht15, +}; + +static void __init imote2_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); + + imote2_stargate2_init(); + + platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices)); + + i2c_register_board_info(0, imote2_i2c_board_info, + ARRAY_SIZE(imote2_i2c_board_info)); + i2c_register_board_info(1, imote2_pwr_i2c_board_info, + ARRAY_SIZE(imote2_pwr_i2c_board_info)); + + pxa_set_mci_info(&imote2_mci_platform_data); + pxa_set_udc_info(&imote2_udc_info); +} +#endif + +#ifdef CONFIG_MACH_STARGATE2 + +static unsigned long stargate2_pin_config[] __initdata = { + + GPIO15_nCS_1, /* SRAM */ + /* SMC91x */ + GPIO80_nCS_4, + GPIO40_GPIO, /*cable detect?*/ + + /* Button */ + GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH, + + /* Compact Flash */ + GPIO79_PSKTSEL, + GPIO48_nPOE, + GPIO49_nPWE, + GPIO50_nPIOR, + GPIO51_nPIOW, + GPIO85_nPCE_1, + GPIO54_nPCE_2, + GPIO55_nPREG, + GPIO56_nPWAIT, + GPIO57_nIOIS16, + GPIO120_GPIO, /* Buff ctrl */ + GPIO108_GPIO, /* Power ctrl */ + GPIO82_GPIO, /* Reset */ + GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */ + + /* MMC not shared with imote2 */ + GPIO90_GPIO, /* nSD detect */ + GPIO89_GPIO, /* SD_POWER_ENABLE */ + + /* Bluetooth */ + GPIO81_GPIO, /* reset */ }; static struct resource smc91x_resources[] = { @@ -463,7 +680,6 @@ static struct platform_device smc91x_device = { }; - /* * The card detect interrupt isn't debounced so we delay it by 250ms * to give the card a chance to fully insert / eject. @@ -532,48 +748,6 @@ static struct pxamci_platform_data stargate2_mci_platform_data = { .exit = stargate2_mci_exit, }; -static struct mtd_partition stargate2flash_partitions[] = { - { - .name = "Bootloader", - .size = 0x00040000, - .offset = 0, - .mask_flags = 0, - }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0x00040000, - .mask_flags = 0 - }, { - .name = "Filesystem", - .size = 0x01DC0000, - .offset = 0x00240000, - .mask_flags = 0 - }, -}; - -static struct resource flash_resources = { - .start = PXA_CS0_PHYS, - .end = PXA_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct flash_platform_data stargate2_flash_data = { - .map_name = "cfi_probe", - .parts = stargate2flash_partitions, - .nr_parts = ARRAY_SIZE(stargate2flash_partitions), - .name = "PXA27xOnChipROM", - .width = 2, -}; - -static struct platform_device stargate2_flash_device = { - .name = "pxa2xx-flash", - .id = 0, - .dev = { - .platform_data = &stargate2_flash_data, - }, - .resource = &flash_resources, - .num_resources = 1, -}; /* * SRAM - The Stargate 2 has 32MB of SRAM. @@ -616,6 +790,129 @@ static struct at24_platform_data pca9500_eeprom_pdata = { .page_size = 4, }; +/** + * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state + **/ +static int stargate2_reset_bluetooth(void) +{ + int err; + err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET"); + if (err) { + printk(KERN_ERR "Could not get gpio for bluetooth reset\n"); + return err; + } + gpio_direction_output(SG2_BT_RESET, 1); + mdelay(5); + /* now reset it - 5 msec minimum */ + gpio_set_value(SG2_BT_RESET, 0); + mdelay(10); + gpio_set_value(SG2_BT_RESET, 1); + gpio_free(SG2_BT_RESET); + return 0; +} + +static struct led_info stargate2_leds[] = { + { + .name = "sg2:red", + .flags = DA9030_LED_RATE_ON, + }, { + .name = "sg2:blue", + .flags = DA9030_LED_RATE_ON, + }, { + .name = "sg2:green", + .flags = DA9030_LED_RATE_ON, + }, +}; + +static struct da903x_subdev_info stargate2_da9030_subdevs[] = { + { + .name = "da903x-led", + .id = DA9030_ID_LED_2, + .platform_data = &stargate2_leds[0], + }, { + .name = "da903x-led", + .id = DA9030_ID_LED_3, + .platform_data = &stargate2_leds[2], + }, { + .name = "da903x-led", + .id = DA9030_ID_LED_4, + .platform_data = &stargate2_leds[1], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO2, + .platform_data = &stargate2_ldo_init_data[vcc_bbio], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO3, + .platform_data = &stargate2_ldo_init_data[vcc_bb], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO4, + .platform_data = &stargate2_ldo_init_data[vcc_pxa_flash], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO5, + .platform_data = &stargate2_ldo_init_data[vcc_cc2420], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO6, + .platform_data = &stargate2_ldo_init_data[vcc_vref], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO7, + .platform_data = &stargate2_ldo_init_data[vcc_sram_ext], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO8, + .platform_data = &stargate2_ldo_init_data[vcc_mica], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO9, + .platform_data = &stargate2_ldo_init_data[vcc_bt], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO10, + .platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO11, + .platform_data = &stargate2_ldo_init_data[vcc_sensor_3], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO12, + .platform_data = &stargate2_ldo_init_data[vcc_lcd], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO15, + .platform_data = &stargate2_ldo_init_data[vcc_pxa_pll], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO17, + .platform_data = &stargate2_ldo_init_data[vcc_pxa_usim], + }, { + .name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */ + .id = DA9030_ID_LDO18, + .platform_data = &stargate2_ldo_init_data[vcc_io], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO19, + .platform_data = &stargate2_ldo_init_data[vcc_pxa_mem], + }, +}; + +static struct da903x_platform_data stargate2_da9030_pdata = { + .num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs), + .subdevs = stargate2_da9030_subdevs, +}; + +static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = { + { + .type = "da9030", + .addr = 0x49, + .platform_data = &stargate2_da9030_pdata, + .irq = gpio_to_irq(1), + }, +}; static struct i2c_board_info __initdata stargate2_i2c_board_info[] = { /* Techically this a pca9500 - but it's compatible with the 8574 @@ -653,74 +950,6 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = { }, }; -static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = { - { - .type = "da9030", - .addr = 0x49, - .platform_data = &stargate2_da9030_pdata, - .irq = gpio_to_irq(1), - }, -}; - -static struct pxa2xx_spi_master pxa_ssp_master_0_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_master pxa_ssp_master_1_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_master pxa_ssp_master_2_info = { - .num_chipselect = 1, -}; - -/* An upcoming kernel change will scrap SFRM usage so these - * drivers have been moved to use gpio's via cs_control */ -static struct pxa2xx_spi_chip staccel_chip_info = { - .tx_threshold = 8, - .rx_threshold = 8, - .dma_burst_size = 8, - .timeout = 235, - .gpio_cs = 24, -}; - -static struct pxa2xx_spi_chip cc2420_info = { - .tx_threshold = 8, - .rx_threshold = 8, - .dma_burst_size = 8, - .timeout = 235, - .gpio_cs = 39, -}; - -static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "lis3l02dq", - .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */ - .bus_num = 1, - .chip_select = 0, - .controller_data = &staccel_chip_info, - .irq = IRQ_GPIO(96), - }, { - .modalias = "cc2420", - .max_speed_hz = 6500000, - .bus_num = 3, - .chip_select = 0, - .controller_data = &cc2420_info, - }, -}; - -static void sg2_udc_command(int cmd) -{ - switch (cmd) { - case PXA2XX_UDC_CMD_CONNECT: - UP2OCR |= UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE; - break; - case PXA2XX_UDC_CMD_DISCONNECT: - UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE); - break; - } -} - /* Board doesn't support cable detection - so always lie and say * something is there. */ @@ -741,14 +970,6 @@ static struct platform_device *stargate2_devices[] = { &sht15, }; -static struct i2c_pxa_platform_data i2c_pwr_pdata = { - .fast_mode = 1, -}; - -static struct i2c_pxa_platform_data i2c_pdata = { - .fast_mode = 1, -}; - static void __init stargate2_init(void) { /* This is probably a board specific hack as this must be set @@ -757,22 +978,13 @@ static void __init stargate2_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); + imote2_stargate2_init(); platform_add_devices(ARRAY_AND_SIZE(stargate2_devices)); - pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info); - pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info); - pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info); - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - i2c_register_board_info(0, ARRAY_AND_SIZE(stargate2_i2c_board_info)); - i2c_register_board_info(1, - ARRAY_AND_SIZE(stargate2_pwr_i2c_board_info)); - pxa27x_set_i2c_power_info(&i2c_pwr_pdata); - pxa_set_i2c_info(&i2c_pdata); + i2c_register_board_info(1, stargate2_pwr_i2c_board_info, + ARRAY_SIZE(stargate2_pwr_i2c_board_info)); pxa_set_mci_info(&stargate2_mci_platform_data); @@ -780,7 +992,21 @@ static void __init stargate2_init(void) stargate2_reset_bluetooth(); } +#endif + +#ifdef CONFIG_MACH_INTELMOTE2 +MACHINE_START(INTELMOTE2, "IMOTE 2") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = imote2_init, + .boot_params = 0xA0000100, +MACHINE_END +#endif +#ifdef CONFIG_MACH_STARGATE2 MACHINE_START(STARGATE2, "Stargate 2") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, @@ -790,3 +1016,4 @@ MACHINE_START(STARGATE2, "Stargate 2") .init_machine = stargate2_init, .boot_params = 0xA0000100, MACHINE_END +#endif diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 69689112eae..0acff172ef2 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -530,13 +530,9 @@ static void __init trizeps4_init(void) i2c_register_board_info(0, trizeps4_i2c_devices, ARRAY_SIZE(trizeps4_i2c_devices)); -#ifdef CONFIG_IDE_PXA_CF - /* if boot direct from compact flash dont disable power */ - trizeps_conxs_bcr = 0x0009; -#else /* this is the reset value */ trizeps_conxs_bcr = 0x00A0; -#endif + BCR_writew(trizeps_conxs_bcr); board_backlight_power(1); } diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index 9884fa978f1..c9b747cedea 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -25,6 +25,7 @@ #include <linux/dm9000.h> #include <linux/ucb1400.h> #include <linux/ata_platform.h> +#include <linux/regulator/max1586.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -37,6 +38,7 @@ #include <mach/ohci.h> #include <mach/pxa27x-udc.h> #include <mach/udc.h> +#include <mach/pata_pxa.h> #include <plat/i2c.h> @@ -464,7 +466,6 @@ static struct i2c_board_info __initdata vpac270_i2c_devs[] = { static void __init vpac270_rtc_init(void) { - pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(vpac270_i2c_devs)); } #else @@ -492,7 +493,55 @@ static struct pxafb_mode_info vpac270_lcd_modes[] = { .vsync_len = 2, .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -}, +}, { /* CRT 640x480 */ + .pixclock = 35000, + .xres = 640, + .yres = 480, + .bpp = 16, + .depth = 16, + + .left_margin = 96, + .right_margin = 48, + .upper_margin = 33, + .lower_margin = 10, + + .hsync_len = 48, + .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}, { /* CRT 800x600 H=30kHz V=48HZ */ + .pixclock = 25000, + .xres = 800, + .yres = 600, + .bpp = 16, + .depth = 16, + + .left_margin = 50, + .right_margin = 1, + .upper_margin = 21, + .lower_margin = 12, + + .hsync_len = 8, + .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}, { /* CRT 1024x768 H=40kHz V=50Hz */ + .pixclock = 15000, + .xres = 1024, + .yres = 768, + .bpp = 16, + .depth = 16, + + .left_margin = 220, + .right_margin = 8, + .upper_margin = 33, + .lower_margin = 2, + + .hsync_len = 48, + .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +} }; static struct pxafb_mach_info vpac270_lcd_screen = { @@ -538,9 +587,10 @@ static inline void vpac270_lcd_init(void) {} /****************************************************************************** * PATA IDE ******************************************************************************/ -#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) -static struct pata_platform_info vpac270_pata_pdata = { - .ioport_shift = 1, +#if defined(CONFIG_PATA_PXA) || defined(CONFIG_PATA_PXA_MODULE) +static struct pata_pxa_pdata vpac270_pata_pdata = { + .reg_shift = 1, + .dma_dreq = 1, .irq_flags = IRQF_TRIGGER_RISING, }; @@ -555,7 +605,12 @@ static struct resource vpac270_ide_resources[] = { .end = PXA_CS3_PHYS + 0x15f, .flags = IORESOURCE_MEM }, - [2] = { /* IDE IRQ pin */ + [2] = { /* DMA Base address */ + .start = PXA_CS3_PHYS + 0x20, + .end = PXA_CS3_PHYS + 0x2f, + .flags = IORESOURCE_DMA + }, + [3] = { /* IDE IRQ pin */ .start = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), .end = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), .flags = IORESOURCE_IRQ @@ -563,11 +618,12 @@ static struct resource vpac270_ide_resources[] = { }; static struct platform_device vpac270_ide_device = { - .name = "pata_platform", + .name = "pata_pxa", .num_resources = ARRAY_SIZE(vpac270_ide_resources), .resource = vpac270_ide_resources, .dev = { .platform_data = &vpac270_pata_pdata, + .coherent_dma_mask = 0xffffffff, } }; @@ -580,6 +636,59 @@ static inline void vpac270_ide_init(void) {} #endif /****************************************************************************** + * Core power regulator + ******************************************************************************/ +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +static struct regulator_consumer_supply vpac270_max1587a_consumers[] = { + { + .supply = "vcc_core", + } +}; + +static struct regulator_init_data vpac270_max1587a_v3_info = { + .constraints = { + .name = "vcc_core range", + .min_uV = 900000, + .max_uV = 1705000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .consumer_supplies = vpac270_max1587a_consumers, + .num_consumer_supplies = ARRAY_SIZE(vpac270_max1587a_consumers), +}; + +static struct max1586_subdev_data vpac270_max1587a_subdevs[] = { + { + .name = "vcc_core", + .id = MAX1586_V3, + .platform_data = &vpac270_max1587a_v3_info, + } +}; + +static struct max1586_platform_data vpac270_max1587a_info = { + .subdevs = vpac270_max1587a_subdevs, + .num_subdevs = ARRAY_SIZE(vpac270_max1587a_subdevs), + .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */ +}; + +static struct i2c_board_info __initdata vpac270_pi2c_board_info[] = { + { + I2C_BOARD_INFO("max1586", 0x14), + .platform_data = &vpac270_max1587a_info, + }, +}; + +static void __init vpac270_pmic_init(void) +{ + i2c_register_board_info(1, ARRAY_AND_SIZE(vpac270_pi2c_board_info)); +} +#else +static inline void vpac270_pmic_init(void) {} +#endif + + +/****************************************************************************** * Machine init ******************************************************************************/ static void __init vpac270_init(void) @@ -589,7 +698,10 @@ static void __init vpac270_init(void) pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); + pxa27x_set_i2c_power_info(NULL); + vpac270_pmic_init(); vpac270_lcd_init(); vpac270_mmc_init(); vpac270_nor_init(); diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index d303c6929d3..f0d02288b4c 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -17,6 +17,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/pwm_backlight.h> +#include <linux/z2_battery.h> #include <linux/dma-mapping.h> #include <linux/spi/spi.h> #include <linux/spi/libertas_spi.h> @@ -26,6 +27,7 @@ #include <linux/gpio.h> #include <linux/gpio_keys.h> #include <linux/delay.h> +#include <linux/regulator/machine.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -162,7 +164,7 @@ static struct mtd_partition z2_flash_parts[] = { }, { .name = "U-Boot Environment", .offset = 0x40000, - .size = 0x60000, + .size = 0x20000, }, { .name = "Flash", .offset = 0x60000, @@ -452,6 +454,42 @@ static inline void z2_keys_init(void) {} #endif /****************************************************************************** + * Battery + ******************************************************************************/ +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) +static struct z2_battery_info batt_chip_info = { + .batt_I2C_bus = 0, + .batt_I2C_addr = 0x55, + .batt_I2C_reg = 2, + .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT, + .min_voltage = 2400000, + .max_voltage = 3700000, + .batt_div = 69, + .batt_mult = 1000000, + .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, + .batt_name = "Z2", +}; + +static struct i2c_board_info __initdata z2_i2c_board_info[] = { + { + I2C_BOARD_INFO("aer915", 0x55), + .platform_data = &batt_chip_info, + }, { + I2C_BOARD_INFO("wm8750", 0x1b), + }, + +}; + +static void __init z2_i2c_init(void) +{ + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(z2_i2c_board_info)); +} +#else +static inline void z2_i2c_init(void) {} +#endif + +/****************************************************************************** * SSP Devices - WiFi and LCD control ******************************************************************************/ #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) @@ -573,23 +611,95 @@ static inline void z2_spi_init(void) {} #endif /****************************************************************************** + * Core power regulator + ******************************************************************************/ +#if defined(CONFIG_REGULATOR_TPS65023) || \ + defined(CONFIG_REGULATOR_TPS65023_MODULE) +static struct regulator_consumer_supply z2_tps65021_consumers[] = { + { + .supply = "vcc_core", + } +}; + +static struct regulator_init_data z2_tps65021_info[] = { + { + .constraints = { + .name = "vcc_core range", + .min_uV = 800000, + .max_uV = 1600000, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .consumer_supplies = z2_tps65021_consumers, + .num_consumer_supplies = ARRAY_SIZE(z2_tps65021_consumers), + }, { + .constraints = { + .name = "DCDC2", + .min_uV = 3300000, + .max_uV = 3300000, + .always_on = 1, + }, + }, { + .constraints = { + .name = "DCDC3", + .min_uV = 1800000, + .max_uV = 1800000, + .always_on = 1, + }, + }, { + .constraints = { + .name = "LDO1", + .min_uV = 1000000, + .max_uV = 3150000, + .always_on = 1, + }, + }, { + .constraints = { + .name = "LDO2", + .min_uV = 1050000, + .max_uV = 3300000, + .always_on = 1, + }, + } +}; + +static struct i2c_board_info __initdata z2_pi2c_board_info[] = { + { + I2C_BOARD_INFO("tps65021", 0x48), + .platform_data = &z2_tps65021_info, + }, +}; + +static void __init z2_pmic_init(void) +{ + pxa27x_set_i2c_power_info(NULL); + i2c_register_board_info(1, ARRAY_AND_SIZE(z2_pi2c_board_info)); +} +#else +static inline void z2_pmic_init(void) {} +#endif + +/****************************************************************************** * Machine init ******************************************************************************/ static void __init z2_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(z2_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + z2_lcd_init(); z2_mmc_init(); z2_mkp_init(); - - pxa_set_i2c_info(NULL); - + z2_i2c_init(); z2_spi_init(); z2_nor_init(); z2_pwm_init(); z2_leds_init(); z2_keys_init(); + z2_pmic_init(); } MACHINE_START(ZIPIT2, "Zipit Z2") diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h index 315b0078a34..54297eb0bf5 100644 --- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h +++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h @@ -15,6 +15,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END (0xE0000000) +#define VMALLOC_END 0xE0000000UL #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 35dabccd0ac..bc30245e133 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -55,6 +55,7 @@ #include <plat/cpu.h> #include <plat/iic-core.h> +#include <plat/fb-core.h> static struct map_desc s3c2416_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), @@ -90,7 +91,7 @@ int __init s3c2416_init(void) s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); - s3c_device_fb.name = "s3c2443-fb"; + s3c_fb_setname("s3c2443-fb"); return sysdev_register(&s3c2416_sysdev); } diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index 9e39faa283b..deaabe86741 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -90,24 +90,17 @@ static struct pcf50633 *gta02_pcf; /* - * This gets called every 1ms when we paniced. + * This gets called frequently when we paniced. */ -static long gta02_panic_blink(long count) +static long gta02_panic_blink(int state) { long delay = 0; - static long last_blink; - static char led; + char led; - /* Fast blink: 200ms period. */ - if (count - last_blink < 100) - return 0; - - led ^= 1; + led = (state) ? 1 : 0; gpio_direction_output(GTA02_GPIO_AUX_LED, led); - last_blink = count; - return delay; } @@ -556,7 +549,7 @@ static void gta02_poweroff(void) static void __init gta02_machine_init(void) { - /* Set the panic callback to make AUX LED blink at ~5Hz. */ + /* Set the panic callback to turn AUX LED on or off. */ panic_blink = gta02_panic_blink; s3c_pm_init(); diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index ce2ec329893..839b6b2ced7 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -35,6 +35,7 @@ #include <plat/s3c2443.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/fb-core.h> static struct map_desc s3c2443_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), @@ -62,6 +63,7 @@ int __init s3c2443_init(void) s3c24xx_reset_hook = s3c2443_hard_reset; s3c_device_nand.name = "s3c2412-nand"; + s3c_fb_setname("s3c2443-fb"); /* change WDT IRQ number */ s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT; diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index f5a59727949..1e4d78af7d8 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -57,11 +57,21 @@ config S3C64XX_SETUP_I2C1 help Common setup code for i2c bus 1. +config S3C64XX_SETUP_IDE + bool + help + Common setup code for S3C64XX IDE. + config S3C64XX_SETUP_FB_24BPP bool help Common setup code for S3C64XX with an 24bpp RGB display helper. +config S3C64XX_SETUP_KEYPAD + bool + help + Common setup code for S3C64XX KEYPAD GPIO configurations + config S3C64XX_SETUP_SDHCI_GPIO bool help @@ -88,6 +98,15 @@ config MACH_ANW6410 help Machine support for the A&W6410 +config MACH_REAL6410 + bool "REAL6410" + select CPU_S3C6410 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C64XX_SETUP_SDHCI + help + Machine support for the CoreWind REAL6410 + config MACH_SMDK6410 bool "SMDK6410" select CPU_S3C6410 @@ -95,15 +114,20 @@ config MACH_SMDK6410 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 + select SAMSUNG_DEV_IDE select S3C_DEV_FB + select S3C_DEV_RTC select SAMSUNG_DEV_TS select S3C_DEV_USB_HOST select S3C_DEV_USB_HSOTG select S3C_DEV_WDT + select SAMSUNG_DEV_KEYPAD select HAVE_S3C2410_WATCHDOG select S3C64XX_SETUP_SDHCI select S3C64XX_SETUP_I2C1 + select S3C64XX_SETUP_IDE select S3C64XX_SETUP_FB_24BPP + select S3C64XX_SETUP_KEYPAD help Machine support for the Samsung SMDK6410 diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 9d1006938f5..90221a2e0c5 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -35,6 +35,8 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o +obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o @@ -50,6 +52,7 @@ obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o +obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o obj-$(CONFIG_MACH_NCP) += mach-ncp.o obj-$(CONFIG_MACH_HMT) += mach-hmt.o obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index fbd85a9b7bb..7e03f0ae2fc 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -133,6 +133,12 @@ static struct clk init_clocks_disable[] = { .id = -1, .parent = &clk_h, }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_RTC, + }, { .name = "adc", .id = -1, .parent = &clk_p, @@ -165,6 +171,12 @@ static struct clk init_clocks_disable[] = { .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, }, { #endif + .name = "keypad", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, + }, { .name = "spi", .id = 0, .parent = &clk_p, @@ -295,12 +307,6 @@ static struct clk init_clocks[] = { .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_UART3, }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s3c64xx_pclk_ctrl, - .ctrlbit = S3C_CLKCON_PCLK_RTC, - }, { .name = "watchdog", .id = -1, .parent = &clk_p, @@ -310,6 +316,12 @@ static struct clk init_clocks[] = { .id = -1, .parent = &clk_p, .ctrlbit = S3C_CLKCON_PCLK_AC97, + }, { + .name = "cfcon", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_IHOST, } }; diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c index c3e9e73bd0f..9648fbc36ee 100644 --- a/arch/arm/mach-s3c64xx/dev-audio.c +++ b/arch/arm/mach-s3c64xx/dev-audio.c @@ -12,11 +12,11 @@ #include <linux/string.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/irqs.h> #include <mach/map.h> #include <mach/dma.h> -#include <mach/gpio.h> #include <plat/devs.h> #include <plat/audio.h> diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c index 29c32d08851..a492b982aa0 100644 --- a/arch/arm/mach-s3c64xx/dev-spi.c +++ b/arch/arm/mach-s3c64xx/dev-spi.c @@ -12,10 +12,10 @@ #include <linux/string.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/dma.h> #include <mach/map.h> -#include <mach/gpio.h> #include <mach/gpio-bank-c.h> #include <mach/spi-clocks.h> diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 5567e037b0d..e7d03ab41d8 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -697,7 +697,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, chptr->number = chno; chptr->dmac = dmac; chptr->regs = regptr; - regptr += PL008_Cx_STRIDE; + regptr += PL080_Cx_STRIDE; } /* for the moment, permanently enable the controller */ diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c index 60c929a3cab..300dee4a667 100644 --- a/arch/arm/mach-s3c64xx/gpiolib.c +++ b/arch/arm/mach-s3c64xx/gpiolib.c @@ -15,9 +15,9 @@ #include <linux/kernel.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/gpio.h> #include <mach/map.h> -#include <mach/gpio.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index e1eab3c94ae..a1f13f02c84 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -67,6 +67,7 @@ #define S3C64XX_PA_USB_HSOTG (0x7C000000) #define S3C64XX_PA_WATCHDOG (0x7E004000) #define S3C64XX_PA_RTC (0x7E005000) +#define S3C64XX_PA_KEYPAD (0x7E00A000) #define S3C64XX_PA_ADC (0x7E00B000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_AC97 (0x7F001000) @@ -86,6 +87,9 @@ #define S3C64XX_SZ_GPIO SZ_4K #define S3C64XX_PA_SDRAM (0x50000000) + +#define S3C64XX_PA_CFCON (0x70300000) + #define S3C64XX_PA_VIC0 (0x71200000) #define S3C64XX_PA_VIC1 (0x71300000) @@ -120,5 +124,7 @@ #define S3C_PA_WDT S3C64XX_PA_WATCHDOG #define SAMSUNG_PA_ADC S3C64XX_PA_ADC +#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON +#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h index a3ac84a6548..42cc54e2ee3 100644 --- a/arch/arm/mach-s3c64xx/include/mach/memory.h +++ b/arch/arm/mach-s3c64xx/include/mach/memory.h @@ -15,4 +15,6 @@ #define PHYS_OFFSET UL(0x50000000) +#define CONSISTENT_DMA_SIZE SZ_8M + #endif diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 0114eb0c1fe..05332b998ec 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -34,6 +34,7 @@ #define S3C_SCLK_GATE S3C_CLKREG(0x38) #define S3C_MEM0_GATE S3C_CLKREG(0x3C) #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) +#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) /* CLKDIV0 */ #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) @@ -154,4 +155,8 @@ #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) #define S3C6400_CLKSRC_MFC (1 << 4) +/* MEM_SYS_CFG */ +#define MEM_SYS_CFG_INDEP_CF 0x4000 +#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 + #endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h index f56611526c6..a06ee0af9a4 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h @@ -18,24 +18,4 @@ #include <plat/regs-fb-v4.h> -/* Palette registers */ -#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2)) -#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2)) -#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2)) -#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4)) -#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4)) - -static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) -{ - switch (window) { - case 0: return WIN0_PAL(reg); - case 1: return WIN1_PAL(reg); - case 2: return WIN2_PAL(reg); - case 3: return WIN3_PAL(reg); - case 4: return WIN4_PAL(reg); - } - - BUG(); -} - #endif /* __ASM_ARCH_MACH_REGS_FB_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h index 7411ef3711a..bc0e9138986 100644 --- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h +++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h @@ -15,6 +15,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END (0xE0000000) +#define VMALLOC_END 0xE0000000UL #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index 4a0bb243d14..742dc87bd9c 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -134,7 +134,6 @@ static struct platform_device anw6410_lcd_powerdev = { static struct s3c_fb_pd_win anw6410_fb_win0 = { /* this is to ensure we use win0 */ .win_mode = { - .pixclock = 41094, .left_margin = 8, .right_margin = 13, .upper_margin = 7, diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 187441a78dd..fba90229f0d 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -128,7 +128,6 @@ static struct platform_device hmt_backlight_device = { static struct s3c_fb_pd_win hmt_fb_win0 = { .win_mode = { - .pixclock = 41094, .left_margin = 8, .right_margin = 13, .upper_margin = 7, diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c new file mode 100644 index 00000000000..5c07d013b23 --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -0,0 +1,152 @@ +/* linux/arch/arm/mach-s3c64xx/mach-real6410.c + * + * Copyright 2010 Darius Augulis <augulis.darius@gmail.com> + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/init.h> +#include <linux/dm9000.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/map.h> +#include <mach/s3c6410.h> +#include <mach/regs-srom.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/regs-serial.h> + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = UCON, + .ulcon = ULCON, + .ufcon = UFCON, + }, +}; + +/* DM9000AEP 10/100 ethernet controller */ + +static struct resource real6410_dm9k_resource[] = { + [0] = { + .start = S3C64XX_PA_XM0CSN1, + .end = S3C64XX_PA_XM0CSN1 + 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = S3C64XX_PA_XM0CSN1 + 4, + .end = S3C64XX_PA_XM0CSN1 + 5, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = S3C_EINT(7), + .end = S3C_EINT(7), + .flags = IORESOURCE_IRQ, + } +}; + +static struct dm9000_plat_data real6410_dm9k_pdata = { + .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), +}; + +static struct platform_device real6410_device_eth = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(real6410_dm9k_resource), + .resource = real6410_dm9k_resource, + .dev = { + .platform_data = &real6410_dm9k_pdata, + }, +}; + +static struct platform_device *real6410_devices[] __initdata = { + &real6410_device_eth, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, +}; + +static void __init real6410_map_io(void) +{ + s3c64xx_init_io(NULL, 0); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs)); +} + +static void __init real6410_machine_init(void) +{ + u32 cs1; + + /* configure nCS1 width to 16 bits */ + + cs1 = __raw_readl(S3C64XX_SROM_BW) & + ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | + (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << + S3C64XX_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S3C64XX_SROM_BW); + + /* set timing for nCS1 suitable for ethernet chip */ + + __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | + (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | + (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | + (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | + (13 << S3C64XX_SROM_BCX__TACC__SHIFT) | + (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | + (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); + + platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices)); +} + +MACHINE_START(REAL6410, "REAL6410") + /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C64XX_PA_SDRAM + 0x100, + + .init_irq = s3c6410_init_irq, + .map_io = real6410_map_io, + .init_machine = real6410_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 028d080dcd3..3a9639bc3d9 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -16,6 +16,7 @@ #include <linux/platform_device.h> #include <linux/pwm_backlight.h> #include <linux/serial_core.h> +#include <linux/spi/spi_gpio.h> #include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> @@ -166,7 +167,7 @@ static struct s3c2410_ts_mach_info smartq_touchscreen_pdata __initdata = { static struct s3c_sdhci_platdata smartq_internal_hsmmc_pdata = { .max_width = 4, - /*.broken_card_detection = true,*/ + .cd_type = S3C_SDHCI_CD_PERMANENT, }; static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = { @@ -184,6 +185,33 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = { }, }; +static int __init smartq_lcd_setup_gpio(void) +{ + int ret; + + ret = gpio_request(S3C64XX_GPM(3), "LCD power"); + if (ret < 0) + return ret; + + /* turn power off */ + gpio_direction_output(S3C64XX_GPM(3), 0); + + return 0; +} + +/* GPM0 -> CS */ +static struct spi_gpio_platform_data smartq_lcd_control = { + .sck = S3C64XX_GPM(1), + .mosi = S3C64XX_GPM(2), + .miso = S3C64XX_GPM(2), +}; + +static struct platform_device smartq_lcd_control_device = { + .name = "spi-gpio", + .id = 1, + .dev.platform_data = &smartq_lcd_control, +}; + static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) { gpio_direction_output(S3C64XX_GPM(3), power); @@ -199,6 +227,9 @@ static struct platform_device smartq_lcd_power_device = { .dev.platform_data = &smartq_lcd_power_data, }; +static struct i2c_board_info smartq_i2c_devs[] __initdata = { + { I2C_BOARD_INFO("wm8987", 0x1a), }, +}; static struct platform_device *smartq_devices[] __initdata = { &s3c_device_hsmmc1, /* Init iNAND first, ... */ @@ -213,7 +244,9 @@ static struct platform_device *smartq_devices[] __initdata = { &s3c_device_timer[1], &s3c_device_ts, &s3c_device_usb_hsotg, + &s3c64xx_device_iis0, &smartq_backlight_device, + &smartq_lcd_control_device, &smartq_lcd_power_device, &smartq_usb_otg_vbus_dev, }; @@ -252,7 +285,6 @@ static int __init smartq_power_off_init(void) /* leave power on */ gpio_direction_output(S3C64XX_GPK(15), 0); - pm_power_off = smartq_power_off; return ret; @@ -354,6 +386,10 @@ void __init smartq_machine_init(void) s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata); s3c24xx_ts_set_platdata(&smartq_touchscreen_pdata); + i2c_register_board_info(0, smartq_i2c_devs, + ARRAY_SIZE(smartq_i2c_devs)); + + WARN_ON(smartq_lcd_setup_gpio()); WARN_ON(smartq_power_off_init()); WARN_ON(smartq_usb_host_init()); WARN_ON(smartq_usb_otg_init()); diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c index 1d0326ead90..a4d59b076e3 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c @@ -12,7 +12,6 @@ #include <linux/fb.h> #include <linux/gpio.h> #include <linux/gpio_keys.h> -#include <linux/i2c-gpio.h> #include <linux/init.h> #include <linux/input.h> #include <linux/leds.h> @@ -33,31 +32,6 @@ #include "mach-smartq.h" -static void __init smartq5_lcd_setup_gpio(void) -{ - gpio_request(S3C64XX_GPM(0), "LCD SCEN pin"); - gpio_request(S3C64XX_GPM(1), "LCD SCL pin"); - gpio_request(S3C64XX_GPM(2), "LCD SDA pin"); - gpio_request(S3C64XX_GPM(3), "LCD power"); - - /* turn power off */ - gpio_direction_output(S3C64XX_GPM(0), 1); - gpio_direction_input(S3C64XX_GPM(1)); - gpio_direction_input(S3C64XX_GPM(2)); - gpio_direction_output(S3C64XX_GPM(3), 0); -} - -static struct i2c_gpio_platform_data smartq5_lcd_control = { - .sda_pin = S3C64XX_GPM(2), - .scl_pin = S3C64XX_GPM(1), -}; - -static struct platform_device smartq5_lcd_control_device = { - .name = "i2c-gpio", - .id = 1, - .dev.platform_data = &smartq5_lcd_control, -}; - static struct gpio_led smartq5_leds[] __initdata = { { .name = "smartq5:green", @@ -134,16 +108,15 @@ static struct platform_device smartq5_buttons_device = { static struct s3c_fb_pd_win smartq5_fb_win0 = { .win_mode = { - .pixclock = 1000000000000ULL / - ((40+1+216+800)*(10+1+35+480)*80), - .left_margin = 40, - .right_margin = 216, - .upper_margin = 10, - .lower_margin = 35, + .left_margin = 216, + .right_margin = 40, + .upper_margin = 35, + .lower_margin = 10, .hsync_len = 1, .vsync_len = 1, .xres = 800, .yres = 480, + .refresh = 80, }, .max_bpp = 32, .default_bpp = 16, @@ -160,7 +133,6 @@ static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = { static struct platform_device *smartq5_devices[] __initdata = { &smartq5_leds_device, &smartq5_buttons_device, - &smartq5_lcd_control_device, }; static void __init smartq5_machine_init(void) @@ -168,7 +140,6 @@ static void __init smartq5_machine_init(void) s3c_fb_set_platdata(&smartq5_lcd_pdata); smartq_machine_init(); - smartq5_lcd_setup_gpio(); platform_add_devices(smartq5_devices, ARRAY_SIZE(smartq5_devices)); } diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c index e0bc78ecb15..e50a7d78173 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c @@ -12,7 +12,6 @@ #include <linux/fb.h> #include <linux/gpio.h> #include <linux/gpio_keys.h> -#include <linux/i2c-gpio.h> #include <linux/init.h> #include <linux/input.h> #include <linux/leds.h> @@ -33,31 +32,6 @@ #include "mach-smartq.h" -static void __init smartq7_lcd_setup_gpio(void) -{ - gpio_request(S3C64XX_GPM(0), "LCD CSB pin"); - gpio_request(S3C64XX_GPM(3), "LCD power"); - gpio_request(S3C64XX_GPM(4), "LCD power status"); - - /* turn power off */ - gpio_direction_output(S3C64XX_GPM(0), 1); - gpio_direction_output(S3C64XX_GPM(3), 0); - gpio_direction_input(S3C64XX_GPM(4)); -} - -static struct i2c_gpio_platform_data smartq7_lcd_control = { - .sda_pin = S3C64XX_GPM(2), - .scl_pin = S3C64XX_GPM(1), - .sda_is_open_drain = 1, - .scl_is_open_drain = 1, -}; - -static struct platform_device smartq7_lcd_control_device = { - .name = "i2c-gpio", - .id = 1, - .dev.platform_data = &smartq7_lcd_control, -}; - static struct gpio_led smartq7_leds[] __initdata = { { .name = "smartq7:red", @@ -150,8 +124,6 @@ static struct platform_device smartq7_buttons_device = { static struct s3c_fb_pd_win smartq7_fb_win0 = { .win_mode = { - .pixclock = 1000000000000ULL / - ((3+10+5+800)*(1+3+20+480)*80), .left_margin = 3, .right_margin = 5, .upper_margin = 1, @@ -160,6 +132,7 @@ static struct s3c_fb_pd_win smartq7_fb_win0 = { .vsync_len = 3, .xres = 800, .yres = 480, + .refresh = 80, }, .max_bpp = 32, .default_bpp = 16, @@ -176,7 +149,6 @@ static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = { static struct platform_device *smartq7_devices[] __initdata = { &smartq7_leds_device, &smartq7_buttons_device, - &smartq7_lcd_control_device, }; static void __init smartq7_machine_init(void) @@ -184,7 +156,6 @@ static void __init smartq7_machine_init(void) s3c_fb_set_platdata(&smartq7_lcd_pdata); smartq_machine_init(); - smartq7_lcd_setup_gpio(); platform_add_devices(smartq7_devices, ARRAY_SIZE(smartq7_devices)); } diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d9a03555f88..d498219fff1 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -17,6 +17,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/input.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -56,6 +57,7 @@ #include <mach/regs-gpio.h> #include <mach/regs-sys.h> #include <mach/regs-srom.h> +#include <plat/ata.h> #include <plat/iic.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> @@ -66,6 +68,7 @@ #include <plat/cpu.h> #include <plat/adc.h> #include <plat/ts.h> +#include <plat/keypad.h> #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB @@ -141,7 +144,6 @@ static struct platform_device smdk6410_lcd_powerdev = { static struct s3c_fb_pd_win smdk6410_fb_win0 = { /* this is to ensure we use win0 */ .win_mode = { - .pixclock = 41094, .left_margin = 8, .right_margin = 13, .upper_margin = 7, @@ -153,6 +155,8 @@ static struct s3c_fb_pd_win smdk6410_fb_win0 = { }, .max_bpp = 32, .default_bpp = 16, + .virtual_y = 480 * 2, + .virtual_x = 800, }; /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ @@ -242,6 +246,29 @@ static struct platform_device smdk6410_b_pwr_5v = { }; #endif +static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = { + .setup_gpio = s3c64xx_ide_setup_gpio, +}; + +static uint32_t smdk6410_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), + KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), + KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), + KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) +}; + +static struct matrix_keymap_data smdk6410_keymap_data __initdata = { + .keymap = smdk6410_keymap, + .keymap_size = ARRAY_SIZE(smdk6410_keymap), +}; + +static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = { + .keymap_data = &smdk6410_keymap_data, + .rows = 2, + .cols = 8, +}; + static struct map_desc smdk6410_iodesc[] = {}; static struct platform_device *smdk6410_devices[] __initdata = { @@ -257,6 +284,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_ohci, &s3c_device_usb_hsotg, &s3c64xx_device_iisv4, + &samsung_device_keypad, #ifdef CONFIG_REGULATOR &smdk6410_b_pwr_5v, @@ -265,6 +293,8 @@ static struct platform_device *smdk6410_devices[] __initdata = { &smdk6410_smsc911x, &s3c_device_adc, + &s3c_device_cfcon, + &s3c_device_rtc, &s3c_device_ts, &s3c_device_wdt, }; @@ -636,6 +666,8 @@ static void __init smdk6410_machine_init(void) s3c_i2c1_set_platdata(NULL); s3c_fb_set_platdata(&smdk6410_lcd_pdata); + samsung_keypad_set_platdata(&smdk6410_keypad_data); + s3c24xx_ts_set_platdata(&s3c_ts_platform); /* configure nCS1 width to 16 bits */ @@ -665,6 +697,8 @@ static void __init smdk6410_machine_init(void) i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + s3c_ide_set_platdata(&smdk6410_ide_pdata); + platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); } diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 014401c39f3..312aa6b115e 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -37,8 +37,9 @@ #include <plat/devs.h> #include <plat/clock.h> #include <plat/sdhci.h> +#include <plat/ata-core.h> +#include <plat/adc-core.h> #include <plat/iic-core.h> -#include <plat/adc.h> #include <plat/onenand-core.h> #include <mach/s3c6400.h> #include <mach/s3c6410.h> @@ -54,10 +55,11 @@ void __init s3c6410_map_io(void) s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); - s3c_device_adc.name = "s3c64xx-adc"; + s3c_adc_setname("s3c64xx-adc"); s3c_device_nand.name = "s3c6400-nand"; s3c_onenand_setname("s3c6410-onenand"); s3c64xx_onenand1_setname("s3c6410-onenand"); + s3c_cfcon_setname("s3c64xx-pata"); } void __init s3c6410_init_clocks(int xtal) diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c index 8e28e448dd2..000736877df 100644 --- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c +++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c @@ -15,9 +15,9 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/fb.h> +#include <linux/gpio.h> #include <mach/regs-fb.h> -#include <mach/gpio.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c64xx/setup-i2c0.c index d1b11e6e77e..406192a43c6 100644 --- a/arch/arm/mach-s3c64xx/setup-i2c0.c +++ b/arch/arm/mach-s3c64xx/setup-i2c0.c @@ -14,10 +14,10 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> #include <mach/gpio-bank-b.h> #include <plat/iic.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c64xx/setup-i2c1.c index 2dce57d8c6f..1ee62c97cd7 100644 --- a/arch/arm/mach-s3c64xx/setup-i2c1.c +++ b/arch/arm/mach-s3c64xx/setup-i2c1.c @@ -14,10 +14,10 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> #include <mach/gpio-bank-b.h> #include <plat/iic.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c new file mode 100644 index 00000000000..c12c315f33b --- /dev/null +++ b/arch/arm/mach-s3c64xx/setup-ide.c @@ -0,0 +1,46 @@ +/* linux/arch/arm/mach-s3c64xx/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S3C64XX setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <plat/gpio-cfg.h> + +void s3c64xx_ide_setup_gpio(void) +{ + u32 reg; + u32 gpio = 0; + + reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); + + /* Independent CF interface, CF chip select configuration */ + writel(reg | MEM_SYS_CFG_INDEP_CF | + MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG); + + s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4)); + + /* Set XhiDATA[15:0] pins as CF Data[15:0] */ + for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5)); + + /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */ + for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6)); + + /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ + s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1)); + for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6)); +} diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c new file mode 100644 index 00000000000..abc34e4e1a9 --- /dev/null +++ b/arch/arm/mach-s3c64xx/setup-keypad.c @@ -0,0 +1,34 @@ +/* linux/arch/arm/mach-s3c64xx/setup-keypad.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * GPIO configuration for S3C64XX KeyPad device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> + +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) +{ + unsigned int gpio; + unsigned int end; + + /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */ + end = S3C64XX_GPK(8 + rows); + for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */ + end = S3C64XX_GPL(0 + cols); + for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c index a58c0cc7ba5..32235959137 100644 --- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c @@ -16,12 +16,14 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio.h> -#include <mach/gpio.h> #include <plat/gpio-cfg.h> +#include <plat/sdhci.h> void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; unsigned int end; @@ -33,12 +35,15 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); + } } void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; unsigned int end; @@ -50,8 +55,10 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } - s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); + } } void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig index f066fae07c5..6a4af7f5758 100644 --- a/arch/arm/mach-s5p6440/Kconfig +++ b/arch/arm/mach-s5p6440/Kconfig @@ -13,13 +13,20 @@ config CPU_S5P6440 help Enable S5P6440 CPU support +config S5P6440_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + config MACH_SMDK6440 bool "SMDK6440" select CPU_S5P6440 - select SAMSUNG_DEV_TS - select SAMSUNG_DEV_ADC + select S3C_DEV_I2C1 + select S3C_DEV_RTC select S3C_DEV_WDT - select HAVE_S3C2410_WATCHDOG + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_TS + select S5P6440_SETUP_I2C1 help Machine support for the Samsung SMDK6440 diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index be3c53aab23..c3fe4d3662a 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o # device support obj-y += dev-audio.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o +obj-$(CONFIG_S5P6440_SETUP_I2C1) += setup-i2c1.o diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c index b2fe6a58155..526f33adb31 100644 --- a/arch/arm/mach-s5p6440/cpu.c +++ b/arch/arm/mach-s5p6440/cpu.c @@ -37,6 +37,7 @@ #include <plat/devs.h> #include <plat/clock.h> #include <plat/s5p6440.h> +#include <plat/adc-core.h> static void s5p6440_idle(void) { @@ -61,7 +62,7 @@ static void s5p6440_idle(void) void __init s5p6440_map_io(void) { /* initialize any device information early */ - s3c_device_adc.name = "s3c64xx-adc"; + s3c_adc_setname("s3c64xx-adc"); } void __init s5p6440_init_clocks(int xtal) diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c index 0c536796283..3ca0d2b8275 100644 --- a/arch/arm/mach-s5p6440/dev-audio.c +++ b/arch/arm/mach-s5p6440/dev-audio.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <plat/gpio-cfg.h> #include <plat/audio.h> -#include <mach/gpio.h> #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c index 0a30280019c..510af44d180 100644 --- a/arch/arm/mach-s5p6440/dev-spi.c +++ b/arch/arm/mach-s5p6440/dev-spi.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/dma.h> #include <mach/map.h> #include <mach/irqs.h> -#include <mach/gpio.h> #include <mach/spi-clocks.h> #include <plat/s3c64xx-spi.h> diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c index 92efc05b1ba..8bf6e0ce51c 100644 --- a/arch/arm/mach-s5p6440/gpio.c +++ b/arch/arm/mach-s5p6440/gpio.c @@ -13,9 +13,11 @@ #include <linux/kernel.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/gpio.h> + #include <mach/map.h> -#include <mach/gpio.h> #include <mach/regs-gpio.h> + #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h index 911854d9ad4..16a761270de 100644 --- a/arch/arm/mach-s5p6440/include/mach/irqs.h +++ b/arch/arm/mach-s5p6440/include/mach/irqs.h @@ -51,7 +51,7 @@ #define IRQ_DISPCON3 S5P_IRQ_VIC1(19) #define IRQ_FIMGVG S5P_IRQ_VIC1(20) #define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) -#define IRQ_PMUIRQ S5P_IRQ_VIC1(23) +#define IRQ_PMU S5P_IRQ_VIC1(23) #define IRQ_HSMMC0 S5P_IRQ_VIC1(24) #define IRQ_HSMMC1 S5P_IRQ_VIC1(25) #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index 44011b91fbd..6cc5cbc88ff 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -38,7 +38,6 @@ #define S5P_PA_TIMER S5P6440_PA_TIMER #define S5P6440_PA_RTC (0xEA100000) -#define S5P_PA_RTC S5P6440_PA_RTC #define S5P6440_PA_WDT (0xEA200000) #define S5P_PA_WDT S5P6440_PA_WDT @@ -53,6 +52,7 @@ #define S5P_SZ_UART SZ_256 #define S5P6440_PA_IIC0 (0xEC104000) +#define S5P6440_PA_IIC1 (0xEC20F000) #define S5P6440_PA_SPI0 0xEC400000 #define S5P6440_PA_SPI1 0xEC500000 @@ -77,6 +77,8 @@ /* compatibiltiy defines. */ #define S3C_PA_UART S5P6440_PA_UART #define S3C_PA_IIC S5P6440_PA_IIC0 +#define S3C_PA_RTC S5P6440_PA_RTC +#define S3C_PA_IIC1 S5P6440_PA_IIC1 #define S3C_PA_WDT S5P6440_PA_WDT #define SAMSUNG_PA_ADC S5P6440_PA_ADC diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h index d2dd817da66..a359ee3fa51 100644 --- a/arch/arm/mach-s5p6440/include/mach/system.h +++ b/arch/arm/mach-s5p6440/include/mach/system.h @@ -13,12 +13,9 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ -static void arch_idle(void) -{ - /* nothing here yet */ -} +#include <plat/system-reset.h> -static void arch_reset(char mode, const char *cmd) +static void arch_idle(void) { /* nothing here yet */ } diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p6440/include/mach/vmalloc.h index 16df257b1dc..e3f0eebf520 100644 --- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h +++ b/arch/arm/mach-s5p6440/include/mach/vmalloc.h @@ -12,6 +12,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END (0xE0000000) +#define VMALLOC_END 0xE0000000UL #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c index 8291fecc701..9202aaac3b5 100644 --- a/arch/arm/mach-s5p6440/mach-smdk6440.c +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c @@ -15,6 +15,7 @@ #include <linux/timer.h> #include <linux/delay.h> #include <linux/init.h> +#include <linux/i2c.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -37,20 +38,21 @@ #include <mach/regs-clock.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/iic.h> #include <plat/pll.h> #include <plat/adc.h> #include <plat/ts.h> -#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S3C2440_UFCON_TXTRIG16 | \ S3C2410_UFCON_RXTRIG8) @@ -58,40 +60,51 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5P6440_UCON_DEFAULT, - .ulcon = S5P6440_ULCON_DEFAULT, - .ufcon = S5P6440_UFCON_DEFAULT, + .ucon = SMDK6440_UCON_DEFAULT, + .ulcon = SMDK6440_ULCON_DEFAULT, + .ufcon = SMDK6440_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5P6440_UCON_DEFAULT, - .ulcon = S5P6440_ULCON_DEFAULT, - .ufcon = S5P6440_UFCON_DEFAULT, + .ucon = SMDK6440_UCON_DEFAULT, + .ulcon = SMDK6440_ULCON_DEFAULT, + .ufcon = SMDK6440_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5P6440_UCON_DEFAULT, - .ulcon = S5P6440_ULCON_DEFAULT, - .ufcon = S5P6440_UFCON_DEFAULT, + .ucon = SMDK6440_UCON_DEFAULT, + .ulcon = SMDK6440_ULCON_DEFAULT, + .ufcon = SMDK6440_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5P6440_UCON_DEFAULT, - .ulcon = S5P6440_ULCON_DEFAULT, - .ufcon = S5P6440_UFCON_DEFAULT, + .ucon = SMDK6440_UCON_DEFAULT, + .ulcon = SMDK6440_ULCON_DEFAULT, + .ufcon = SMDK6440_UFCON_DEFAULT, }, }; static struct platform_device *smdk6440_devices[] __initdata = { &s5p6440_device_iis, &s3c_device_adc, + &s3c_device_rtc, + &s3c_device_i2c0, + &s3c_device_i2c1, &s3c_device_ts, &s3c_device_wdt, }; +static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, +}; + +static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = { + /* To be populated */ +}; + static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { .delay = 10000, .presc = 49, @@ -109,6 +122,14 @@ static void __init smdk6440_machine_init(void) { s3c24xx_ts_set_platdata(&s3c_ts_platform); + /* I2C */ + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(0, smdk6440_i2c_devs0, + ARRAY_SIZE(smdk6440_i2c_devs0)); + i2c_register_board_info(1, smdk6440_i2c_devs1, + ARRAY_SIZE(smdk6440_i2c_devs1)); + platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); } diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p6440/setup-i2c0.c index 69e8a664aed..2c99d14f7ac 100644 --- a/arch/arm/mach-s5p6440/setup-i2c0.c +++ b/arch/arm/mach-s5p6440/setup-i2c0.c @@ -17,9 +17,14 @@ struct platform_device; /* don't need the contents */ +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> #include <plat/iic.h> void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - /* Will be populated later */ + s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5p6440/setup-i2c1.c b/arch/arm/mach-s5p6440/setup-i2c1.c new file mode 100644 index 00000000000..9a1537f786e --- /dev/null +++ b/arch/arm/mach-s5p6440/setup-i2c1.c @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-s5p6440/setup-i2c1.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C1 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/gpio.h> + +struct platform_device; /* don't need the contents */ + +#include <plat/gpio-cfg.h> +#include <plat/iic.h> + +void s3c_i2c1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6)); + s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6)); + s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig index 0fd41b44791..0fda0a5df96 100644 --- a/arch/arm/mach-s5p6442/Kconfig +++ b/arch/arm/mach-s5p6442/Kconfig @@ -19,6 +19,7 @@ config CPU_S5P6442 config MACH_SMDK6442 bool "SMDK6442" select CPU_S5P6442 + select S3C_DEV_WDT help Machine support for Samsung SMDK6442 diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c index 087e57f20ad..dcd20f17212 100644 --- a/arch/arm/mach-s5p6442/clock.c +++ b/arch/arm/mach-s5p6442/clock.c @@ -361,6 +361,12 @@ static struct clk init_clocks[] = { .enable = s5p6442_clk_ip3_ctrl, .ctrlbit = (1<<19), }, { + .name = "watchdog", + .id = -1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1 << 22), + }, { .name = "timers", .id = -1, .parent = &clk_pclkd1, diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c index cb801e1f5e2..7a4e34720b7 100644 --- a/arch/arm/mach-s5p6442/dev-audio.c +++ b/arch/arm/mach-s5p6442/dev-audio.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <plat/gpio-cfg.h> #include <plat/audio.h> -#include <mach/gpio.h> #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c index 30199525dac..e894651a88b 100644 --- a/arch/arm/mach-s5p6442/dev-spi.c +++ b/arch/arm/mach-s5p6442/dev-spi.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/dma.h> #include <mach/map.h> #include <mach/irqs.h> -#include <mach/gpio.h> #include <mach/spi-clocks.h> #include <plat/s3c64xx-spi.h> diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h index 02c23749c02..3fbc6c3ad2d 100644 --- a/arch/arm/mach-s5p6442/include/mach/irqs.h +++ b/arch/arm/mach-s5p6442/include/mach/irqs.h @@ -32,7 +32,7 @@ #define IRQ_GPIOINT S5P_IRQ_VIC0(30) /* VIC1 */ -#define IRQ_nPMUIRQ S5P_IRQ_VIC1(0) +#define IRQ_PMU S5P_IRQ_VIC1(0) #define IRQ_ONENAND S5P_IRQ_VIC1(7) #define IRQ_UART0 S5P_IRQ_VIC1(10) #define IRQ_UART1 S5P_IRQ_VIC1(11) diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 32ca424ef7f..281d256faaf 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -42,6 +42,8 @@ #define S5P6442_PA_SYSTIMER (0xEA100000) +#define S5P6442_PA_WATCHDOG (0xEA200000) + #define S5P6442_PA_UART (0xEC000000) #define S5P_PA_UART0 (S5P6442_PA_UART + 0x0) @@ -65,6 +67,7 @@ #define S5P6442_PA_PCM1 0xF2500000 /* compatibiltiy defines. */ +#define S3C_PA_WDT S5P6442_PA_WATCHDOG #define S3C_PA_UART S5P6442_PA_UART #define S3C_PA_IIC S5P6442_PA_IIC0 diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h index 8bcd8ed0c3c..c30c1cc1b97 100644 --- a/arch/arm/mach-s5p6442/include/mach/system.h +++ b/arch/arm/mach-s5p6442/include/mach/system.h @@ -13,12 +13,9 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ -static void arch_idle(void) -{ - /* nothing here yet */ -} +#include <plat/system-reset.h> -static void arch_reset(char mode, const char *cmd) +static void arch_idle(void) { /* nothing here yet */ } diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h index be3333688c2..f5c83f02c18 100644 --- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h +++ b/arch/arm/mach-s5p6442/include/mach/vmalloc.h @@ -12,6 +12,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END (0xE0000000) +#define VMALLOC_END 0xE0000000UL #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c index ebcf9977725..8d8d04272f8 100644 --- a/arch/arm/mach-s5p6442/mach-smdk6442.c +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c @@ -27,16 +27,16 @@ #include <plat/cpu.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) @@ -44,28 +44,29 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5P6442_UCON_DEFAULT, - .ulcon = S5P6442_ULCON_DEFAULT, - .ufcon = S5P6442_UFCON_DEFAULT, + .ucon = SMDK6442_UCON_DEFAULT, + .ulcon = SMDK6442_ULCON_DEFAULT, + .ufcon = SMDK6442_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5P6442_UCON_DEFAULT, - .ulcon = S5P6442_ULCON_DEFAULT, - .ufcon = S5P6442_UFCON_DEFAULT, + .ucon = SMDK6442_UCON_DEFAULT, + .ulcon = SMDK6442_ULCON_DEFAULT, + .ufcon = SMDK6442_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5P6442_UCON_DEFAULT, - .ulcon = S5P6442_ULCON_DEFAULT, - .ufcon = S5P6442_UFCON_DEFAULT, + .ucon = SMDK6442_UCON_DEFAULT, + .ulcon = SMDK6442_ULCON_DEFAULT, + .ufcon = SMDK6442_UFCON_DEFAULT, }, }; static struct platform_device *smdk6442_devices[] __initdata = { &s5p6442_device_iis0, + &s3c_device_wdt, }; static void __init smdk6442_map_io(void) diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index b2a11dfa339..77ae4bfb74b 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -25,6 +25,16 @@ config S5PC100_SETUP_I2C1 help Common setup code for i2c bus 1. +config S5PC100_SETUP_IDE + bool + help + Common setup code for S5PC100 IDE GPIO configurations + +config S5PC100_SETUP_KEYPAD + bool + help + Common setup code for KEYPAD GPIO configurations. + config S5PC100_SETUP_SDHCI bool select S5PC100_SETUP_SDHCI_GPIO @@ -40,13 +50,24 @@ config MACH_SMDKC100 bool "SMDKC100" select CPU_S5PC100 select S3C_DEV_FB - select S3C_DEV_I2C1 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_RTC + select S3C_DEV_WDT + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_IDE + select SAMSUNG_DEV_KEYPAD + select SAMSUNG_DEV_TS select S5PC100_SETUP_FB_24BPP select S5PC100_SETUP_I2C1 + select S5PC100_SETUP_IDE + select S5PC100_SETUP_KEYPAD select S5PC100_SETUP_SDHCI + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 help Machine support for the Samsung SMDKC100 diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 543f3de5131..a021ed1fb4b 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -19,6 +19,8 @@ obj-$(CONFIG_CPU_S5PC100) += dma.o obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o +obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index e3fed4cfe7a..084abd13b0a 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -737,7 +737,7 @@ static struct clk init_clocks_disable[] = { .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 7), }, { - .name = "keyif", + .name = "keypad", .id = -1, .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_5_ctrl, @@ -1078,7 +1078,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 0, .ctrlbit = (1 << 12), .enable = s5pc100_sclk1_ctrl, @@ -1089,7 +1089,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 1, .ctrlbit = (1 << 13), .enable = s5pc100_sclk1_ctrl, @@ -1100,7 +1100,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 2, .ctrlbit = (1 << 14), .enable = s5pc100_sclk1_ctrl, diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index 7b5bdbc9a5d..251c92ac5b2 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -38,9 +38,12 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/clock.h> +#include <plat/ata-core.h> #include <plat/iic-core.h> #include <plat/sdhci.h> +#include <plat/adc-core.h> #include <plat/onenand-core.h> +#include <plat/fb-core.h> #include <plat/s5pc100.h> @@ -87,11 +90,15 @@ void __init s5pc100_map_io(void) s5pc100_default_sdhci1(); s5pc100_default_sdhci2(); + s3c_adc_setname("s3c64xx-adc"); + /* the i2c devices are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); s3c_onenand_setname("s5pc100-onenand"); + s3c_fb_setname("s5pc100-fb"); + s3c_cfcon_setname("s5pc100-pata"); } void __init s5pc100_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c index 18cfe9ae193..a699ed6acc2 100644 --- a/arch/arm/mach-s5pc100/dev-audio.c +++ b/arch/arm/mach-s5pc100/dev-audio.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <plat/gpio-cfg.h> #include <plat/audio.h> -#include <mach/gpio.h> #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c index 14618c34605..a0ef7c302c1 100644 --- a/arch/arm/mach-s5pc100/dev-spi.c +++ b/arch/arm/mach-s5pc100/dev-spi.c @@ -10,10 +10,10 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/dma.h> #include <mach/map.h> -#include <mach/gpio.h> #include <mach/spi-clocks.h> #include <plat/s3c64xx-spi.h> diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 28aa551dc3a..06513e64724 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -29,7 +29,7 @@ #define IRQ_GPIOINT S5P_IRQ_VIC0(30) /* VIC1: ARM, power, memory, connectivity */ -#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) +#define IRQ_PMU S5P_IRQ_VIC1(0) #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) @@ -38,7 +38,7 @@ #define IRQ_IEMIEC S5P_IRQ_VIC1(6) #define IRQ_ONENAND S5P_IRQ_VIC1(7) #define IRQ_NFC S5P_IRQ_VIC1(8) -#define IRQ_CFC S5P_IRQ_VIC1(9) +#define IRQ_CFCON S5P_IRQ_VIC1(9) #define IRQ_UART0 S5P_IRQ_VIC1(10) #define IRQ_UART1 S5P_IRQ_VIC1(11) #define IRQ_UART2 S5P_IRQ_VIC1(12) diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index cadae430568..01b9134feff 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -61,6 +61,8 @@ #define S5PC100_PA_ONENAND (0xE7100000) +#define S5PC100_PA_CFCON (0xE7800000) + /* DMA */ #define S5PC100_PA_MDMA (0xE8100000) #define S5PC100_PA_PDMA0 (0xE9000000) @@ -72,6 +74,9 @@ #define S5PC100_PA_SYSTIMER (0xEA100000) +#define S5PC100_PA_WATCHDOG (0xEA200000) +#define S5PC100_PA_RTC (0xEA300000) + #define S5PC100_PA_UART (0xEC000000) #define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) @@ -94,6 +99,10 @@ #define S5PC100_PA_FB (0xEE000000) +#define S5PC100_PA_FIMC0 (0xEE200000) +#define S5PC100_PA_FIMC1 (0xEE300000) +#define S5PC100_PA_FIMC2 (0xEE400000) + #define S5PC100_PA_I2S0 (0xF2000000) #define S5PC100_PA_I2S1 (0xF2100000) #define S5PC100_PA_I2S2 (0xF2200000) @@ -104,6 +113,8 @@ #define S5PC100_PA_PCM0 0xF2400000 #define S5PC100_PA_PCM1 0xF2500000 +#define S5PC100_PA_TSADC (0xF3000000) + /* KEYPAD */ #define S5PC100_PA_KEYPAD (0xF3100000) @@ -130,9 +141,19 @@ #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD +#define S3C_PA_WDT S5PC100_PA_WATCHDOG #define S3C_PA_TSADC S5PC100_PA_TSADC #define S3C_PA_ONENAND S5PC100_PA_ONENAND #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF #define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF +#define S3C_PA_RTC S5PC100_PA_RTC + +#define SAMSUNG_PA_ADC S5PC100_PA_TSADC +#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON +#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD + +#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 +#define S5P_PA_FIMC1 S5PC100_PA_FIMC1 +#define S5P_PA_FIMC2 S5PC100_PA_FIMC2 #endif /* __ASM_ARCH_C100_MAP_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h index 5d27d286d50..bc92da2e0ba 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h @@ -71,7 +71,10 @@ #define S5P_CLKDIV1_PCLKD1_SHIFT (16) #define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) +#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200) #define S5PC100_SWRESET_RESETVAL 0xc100 +#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 + #endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h index 1732cd28c76..4be4cc9abf7 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h @@ -100,40 +100,6 @@ #define BLENDCON (0x260) #define BLENDCON_8BIT_ALPHA (1 << 0) -/* Per-window palette base addresses (start of palette memory). - * Each window palette area consists of 256 32-bit entries. - * START is the first address (entry 0th), END is the address of 255th entry. - */ -#define WIN0_PAL_BASE (0x2400) -#define WIN0_PAL_END (0x27fc) -#define WIN1_PAL_BASE (0x2800) -#define WIN1_PAL_END (0x2bfc) -#define WIN2_PAL_BASE (0x2c00) -#define WIN2_PAL_END (0x2ffc) -#define WIN3_PAL_BASE (0x3000) -#define WIN3_PAL_END (0x33fc) -#define WIN4_PAL_BASE (0x3400) -#define WIN4_PAL_END (0x37fc) - -#define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4)) -#define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4)) -#define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4)) -#define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4)) -#define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4)) - -static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) -{ - switch (window) { - case 0: return WIN0_PAL(reg); - case 1: return WIN1_PAL(reg); - case 2: return WIN2_PAL(reg); - case 3: return WIN3_PAL(reg); - case 4: return WIN4_PAL(reg); - } - - BUG(); -} - #endif /* __ASM_ARCH_REGS_FB_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h index 681f626a9ae..a9ea57c0660 100644 --- a/arch/arm/mach-s5pc100/include/mach/system.h +++ b/arch/arm/mach-s5pc100/include/mach/system.h @@ -11,18 +11,11 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ -#include <linux/io.h> -#include <mach/map.h> -#include <mach/regs-clock.h> +#include <plat/system-reset.h> static void arch_idle(void) { /* nothing here yet */ } -static void arch_reset(char mode, const char *cmd) -{ - __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET); - return; -} #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index af22f8202a0..020c3f98f81 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -22,6 +22,7 @@ #include <linux/i2c.h> #include <linux/fb.h> #include <linux/delay.h> +#include <linux/input.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -42,18 +43,22 @@ #include <plat/s5pc100.h> #include <plat/fb.h> #include <plat/iic.h> +#include <plat/ata.h> +#include <plat/adc.h> +#include <plat/keypad.h> +#include <plat/ts.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S3C2440_UFCON_RXTRIG8 | \ S3C2440_UFCON_TXTRIG16) @@ -61,30 +66,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, }; @@ -128,7 +133,6 @@ static struct platform_device smdkc100_lcd_powerdev = { static struct s3c_fb_pd_win smdkc100_fb_win0 = { /* this is to ensure we use win0 */ .win_mode = { - .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80), .left_margin = 8, .right_margin = 13, .upper_margin = 7, @@ -137,6 +141,7 @@ static struct s3c_fb_pd_win smdkc100_fb_win0 = { .vsync_len = 1, .xres = 800, .yres = 480, + .refresh = 80, }, .max_bpp = 32, .default_bpp = 16, @@ -149,16 +154,54 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { .setup_gpio = s5pc100_fb_gpio_setup_24bpp, }; +static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = { + .setup_gpio = s5pc100_ide_setup_gpio, +}; + +static uint32_t smdkc100_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), + KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), + KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), + KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) +}; + +static struct matrix_keymap_data smdkc100_keymap_data __initdata = { + .keymap = smdkc100_keymap, + .keymap_size = ARRAY_SIZE(smdkc100_keymap), +}; + +static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = { + .keymap_data = &smdkc100_keymap_data, + .rows = 2, + .cols = 8, +}; + static struct platform_device *smdkc100_devices[] __initdata = { + &s3c_device_adc, + &s3c_device_cfcon, &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_fb, &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, + &s3c_device_ts, + &s3c_device_wdt, &smdkc100_lcd_powerdev, &s5pc100_device_iis0, + &samsung_device_keypad, &s5pc100_device_ac97, + &s3c_device_rtc, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, +}; + +static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, }; static void __init smdkc100_map_io(void) @@ -170,6 +213,8 @@ static void __init smdkc100_map_io(void) static void __init smdkc100_machine_init(void) { + s3c24xx_ts_set_platdata(&s3c_ts_platform); + /* I2C */ s3c_i2c0_set_platdata(NULL); s3c_i2c1_set_platdata(NULL); @@ -177,6 +222,9 @@ static void __init smdkc100_machine_init(void) i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); s3c_fb_set_platdata(&smdkc100_lcd_pdata); + s3c_ide_set_platdata(&smdkc100_ide_pdata); + + samsung_keypad_set_platdata(&smdkc100_keypad_data); /* LCD init */ gpio_request(S5PC100_GPD(0), "GPD"); diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c new file mode 100644 index 00000000000..83575671fb5 --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-ide.c @@ -0,0 +1,70 @@ +/* linux/arch/arm/mach-s5pc100/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PC100 setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/regs-clock.h> +#include <plat/gpio-cfg.h> + +void s5pc100_ide_setup_gpio(void) +{ + u32 reg; + u32 gpio = 0; + + /* Independent CF interface, CF chip select configuration */ + reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); + writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); + + /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ + for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + /*CF_Data[0 - 7] */ + for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + /* CF_Data[8 - 15] */ + for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ + for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + /* EBI_OE, EBI_WE */ + for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); + + /* CF_OE, CF_WE */ + for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* CF_CD */ + s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE); +} diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c new file mode 100644 index 00000000000..d0837a72a58 --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-keypad.c @@ -0,0 +1,34 @@ +/* linux/arch/arm/mach-s5pc100/setup-keypad.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * GPIO configuration for S5PC100 KeyPad device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> + +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) +{ + unsigned int gpio; + unsigned int end; + + /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ + end = S5PC100_GPH3(rows); + for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ + end = S5PC100_GPH2(cols); + for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c index 7769c760c9e..dc7208c639e 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c @@ -20,9 +20,11 @@ #include <plat/gpio-cfg.h> #include <plat/regs-sdhci.h> +#include <plat/sdhci.h> void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; unsigned int end; unsigned int num; @@ -47,12 +49,15 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) } } - s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); + } } void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; unsigned int end; @@ -64,12 +69,15 @@ void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } - s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); + } } void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; unsigned int end; @@ -81,6 +89,8 @@ void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } - s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); + } } diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c index ea7ff19adb9..f16946e456e 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ b/arch/arm/mach-s5pc100/setup-sdhci.c @@ -26,10 +26,10 @@ /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ char *s5pc100_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - /* [2] = "mmc_bus", not yet successfully used yet */ - /* [3] = "48m", - note not successfully used yet */ + [0] = "hsmmc", /* HCLK */ + /* [1] = "hsmmc", - duplicate HCLK entry */ + [2] = "sclk_mmc", /* mmc_bus */ + /* [3] = "48m", - note not successfully used yet */ }; diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 0761eac9aae..d3a38955c74 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -27,11 +27,21 @@ config S5PV210_SETUP_I2C2 help Common setup code for i2c bus 2. +config S5PV210_SETUP_IDE + bool + help + Common setup code for S5PV210 IDE GPIO configurations + config S5PV210_SETUP_FB_24BPP bool help Common setup code for S5PV210 with an 24bpp RGB display helper. +config S5PV210_SETUP_KEYPAD + bool + help + Common setup code for keypad. + config S5PV210_SETUP_SDHCI bool select S5PV210_SETUP_SDHCI_GPIO @@ -43,14 +53,27 @@ config S5PV210_SETUP_SDHCI_GPIO help Common setup code for SDHCI gpio. -# machine support +config S5PC110_DEV_ONENAND + bool + help + Compile in platform device definition for OneNAND1 controller + +menu "S5PC110 Machines" config MACH_AQUILA - bool "Samsung Aquila" + bool "Aquila" select CPU_S5PV210 select ARCH_SPARSEMEM_ENABLE - select S5PV210_SETUP_FB_24BPP select S3C_DEV_FB + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S5PC110_DEV_ONENAND + select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_SDHCI help Machine support for the Samsung Aquila target based on S5PC110 SoC @@ -58,34 +81,64 @@ config MACH_GONI bool "GONI" select CPU_S5PV210 select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_FB + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S5PC110_DEV_ONENAND + select S5PV210_SETUP_FB_24BPP + select S5PV210_SETUP_SDHCI help Machine support for Samsung GONI board S5PC110(MCP) is one of package option of S5PV210 -config S5PC110_DEV_ONENAND - bool +config MACH_SMDKC110 + bool "SMDKC110" + select CPU_S5PV210 + select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_RTC + select S3C_DEV_WDT + select SAMSUNG_DEV_IDE + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_IDE help - Compile in platform device definition for OneNAND1 controller + Machine support for Samsung SMDKC110 + S5PC110(MCP) is one of package option of S5PV210 + +endmenu + +menu "S5PV210 Machines" config MACH_SMDKV210 bool "SMDKV210" select CPU_S5PV210 select ARCH_SPARSEMEM_ENABLE + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S3C_DEV_RTC + select S3C_DEV_WDT select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_IDE + select SAMSUNG_DEV_KEYPAD select SAMSUNG_DEV_TS - select S3C_DEV_WDT - select HAVE_S3C2410_WATCHDOG + select S5PV210_SETUP_I2C1 + select S5PV210_SETUP_I2C2 + select S5PV210_SETUP_IDE + select S5PV210_SETUP_KEYPAD + select S5PV210_SETUP_SDHCI help Machine support for Samsung SMDKV210 -config MACH_SMDKC110 - bool "SMDKC110" - select CPU_S5PV210 - select ARCH_SPARSEMEM_ENABLE - select S3C_DEV_WDT - select HAVE_S3C2410_WATCHDOG - help - Machine support for Samsung SMDKC110 - S5PC110(MCP) is one of package option of S5PV210 +endmenu endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 30be9a6a462..05048c5aa4c 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -31,5 +31,7 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o +obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o +obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 411a4a9cbfc..b9f4d677cf5 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -31,9 +31,15 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/clock.h> +#include <plat/fb-core.h> #include <plat/s5pv210.h> +#include <plat/adc-core.h> +#include <plat/ata-core.h> +#include <plat/fimc-core.h> #include <plat/iic-core.h> +#include <plat/keypad-core.h> #include <plat/sdhci.h> +#include <plat/reset.h> /* Initial IO mappings */ @@ -69,6 +75,11 @@ static void s5pv210_idle(void) local_irq_enable(); } +static void s5pv210_sw_reset(void) +{ + __raw_writel(0x1, S5P_SWRESET); +} + /* s5pv210_map_io * * register the standard cpu IO areas @@ -76,21 +87,31 @@ static void s5pv210_idle(void) void __init s5pv210_map_io(void) { -#ifdef CONFIG_S3C_DEV_ADC - s3c_device_adc.name = "s3c64xx-adc"; -#endif - iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); /* initialise device information early */ s5pv210_default_sdhci0(); s5pv210_default_sdhci1(); s5pv210_default_sdhci2(); + s5pv210_default_sdhci3(); + + s3c_adc_setname("s3c64xx-adc"); + + s3c_cfcon_setname("s5pv210-pata"); + + s3c_fimc_setname(0, "s5pv210-fimc"); + s3c_fimc_setname(1, "s5pv210-fimc"); + s3c_fimc_setname(2, "s5pv210-fimc"); /* the i2c devices are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c2_setname("s3c2440-i2c"); + + s3c_fb_setname("s5pv210-fb"); + + /* Use s5pv210-keypad instead of samsung-keypad */ + samsung_keypad_setname("s5pv210-keypad"); } void __init s5pv210_init_clocks(int xtal) @@ -138,5 +159,8 @@ int __init s5pv210_init(void) /* set idle function */ pm_idle = s5pv210_idle; + /* set sw_reset function */ + s5p_reset_hook = s5pv210_sw_reset; + return sysdev_register(&s5pv210_sysdev); } diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 6e215330a1b..21dc6cf955c 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <plat/gpio-cfg.h> #include <plat/audio.h> -#include <mach/gpio.h> #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/mach-s5pv210/dev-onenand.c index 34997b752f9..f8ede33ee82 100644 --- a/arch/arm/mach-s5pv210/dev-onenand.c +++ b/arch/arm/mach-s5pv210/dev-onenand.c @@ -27,9 +27,14 @@ static struct resource s5pc110_onenand_resources[] = { }, [1] = { .start = S5PC110_PA_ONENAND_DMA, - .end = S5PC110_PA_ONENAND_DMA + SZ_2K - 1, + .end = S5PC110_PA_ONENAND_DMA + SZ_8K - 1, .flags = IORESOURCE_MEM, }, + [2] = { + .start = IRQ_ONENAND_AUDI, + .end = IRQ_ONENAND_AUDI, + .flags = IORESOURCE_IRQ, + }, }; struct platform_device s5pc110_device_onenand = { diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c index 337a62b57a0..826cdbc43e2 100644 --- a/arch/arm/mach-s5pv210/dev-spi.c +++ b/arch/arm/mach-s5pv210/dev-spi.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/dma.h> #include <mach/map.h> #include <mach/irqs.h> -#include <mach/gpio.h> #include <mach/spi-clocks.h> #include <plat/s3c64xx-spi.h> diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c index 9ea8972e023..0d459112d03 100644 --- a/arch/arm/mach-s5pv210/gpiolib.c +++ b/arch/arm/mach-s5pv210/gpiolib.c @@ -207,6 +207,20 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { .label = "MP03", }, }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP04(0), + .ngpio = S5PV210_GPIO_MP04_NR, + .label = "MP04", + }, + }, { + .config = &gpio_cfg_noint, + .chip = { + .base = S5PV210_MP05(0), + .ngpio = S5PV210_GPIO_MP05_NR, + .label = "MP05", + }, + }, { .base = (S5P_VA_GPIO + 0xC00), .config = &gpio_cfg_noint, .chip = { diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index d6461ba2b71..1f4b595534c 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -52,6 +52,8 @@ #define S5PV210_GPIO_MP01_NR (8) #define S5PV210_GPIO_MP02_NR (4) #define S5PV210_GPIO_MP03_NR (8) +#define S5PV210_GPIO_MP04_NR (8) +#define S5PV210_GPIO_MP05_NR (8) /* GPIO bank numbers */ @@ -94,6 +96,8 @@ enum s5p_gpio_number { S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4), S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01), S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), + S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03), + S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04), }; /* S5PV210 GPIO number definitions */ @@ -127,13 +131,15 @@ enum s5p_gpio_number { #define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr)) #define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr)) #define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) +#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr)) +#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr)) /* the end of the S5PV210 specific gpios */ -#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1) +#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) #define S3C_GPIO_END S5PV210_GPIO_END -/* define the number of gpios we need to the one after the MP03() range */ -#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \ +/* define the number of gpios we need to the one after the MP05() range */ +#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \ CONFIG_SAMSUNG_GPIO_EXTRA + 1) #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 96895378ea2..e1c020e5a49 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -36,7 +36,7 @@ /* VIC1: ARM, Power, Memory, Connectivity, Storage */ -#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) +#define IRQ_PMU S5P_IRQ_VIC1(0) #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) @@ -45,7 +45,7 @@ #define IRQ_IEMIEC S5P_IRQ_VIC1(6) #define IRQ_ONENAND S5P_IRQ_VIC1(7) #define IRQ_NFC S5P_IRQ_VIC1(8) -#define IRQ_CFC S5P_IRQ_VIC1(9) +#define IRQ_CFCON S5P_IRQ_VIC1(9) #define IRQ_UART0 S5P_IRQ_VIC1(10) #define IRQ_UART1 S5P_IRQ_VIC1(11) #define IRQ_UART2 S5P_IRQ_VIC1(12) diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 34eb168ec95..dd4fb6bf14b 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -32,6 +32,8 @@ #define S5PV210_PA_SPI0 0xE1300000 #define S5PV210_PA_SPI1 0xE1400000 +#define S5PV210_PA_KEYPAD (0xE1600000) + #define S5PV210_PA_IIC0 (0xE1800000) #define S5PV210_PA_IIC1 (0xFAB00000) #define S5PV210_PA_IIC2 (0xE1A00000) @@ -43,6 +45,7 @@ #define S5PV210_PA_WATCHDOG (0xE2700000) +#define S5PV210_PA_RTC (0xE2800000) #define S5PV210_PA_UART (0xE2900000) #define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) @@ -54,12 +57,18 @@ #define S5PV210_PA_SROMC (0xE8000000) +#define S5PV210_PA_CFCON (0xE8200000) + #define S5PV210_PA_MDMA 0xFA200000 #define S5PV210_PA_PDMA0 0xE0900000 #define S5PV210_PA_PDMA1 0xE0A00000 #define S5PV210_PA_FB (0xF8000000) +#define S5PV210_PA_FIMC0 (0xFB200000) +#define S5PV210_PA_FIMC1 (0xFB300000) +#define S5PV210_PA_FIMC2 (0xFB400000) + #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) #define S5PV210_PA_VIC0 (0xF2000000) @@ -97,12 +106,19 @@ #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) #define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) #define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) +#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3) #define S3C_PA_IIC S5PV210_PA_IIC0 #define S3C_PA_IIC1 S5PV210_PA_IIC1 #define S3C_PA_IIC2 S5PV210_PA_IIC2 #define S3C_PA_FB S5PV210_PA_FB +#define S3C_PA_RTC S5PV210_PA_RTC #define S3C_PA_WDT S5PV210_PA_WATCHDOG +#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 +#define S5P_PA_FIMC1 S5PV210_PA_FIMC1 +#define S5P_PA_FIMC2 S5PV210_PA_FIMC2 #define SAMSUNG_PA_ADC S5PV210_PA_ADC +#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON +#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index 379117e2760..d503e0c4ce4 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -16,8 +16,13 @@ #define PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) -/* Maximum of 256MiB in one bank */ -#define MAX_PHYSMEM_BITS 32 +/* + * Sparsemem support + * Physical memory can be located from 0x20000000 to 0x7fffffff, + * so MAX_PHYSMEM_BITS is 31. + */ + +#define MAX_PHYSMEM_BITS 31 #define SECTION_SIZE_BITS 28 #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 2a25ab40c86..499aef73747 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -90,6 +90,8 @@ #define S5P_CLKDIV0_PCLK66_SHIFT (28) #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) +#define S5P_SWRESET S5P_CLKREG(0x2000) + /* Registers related to power management */ #define S5P_PWR_CFG S5P_CLKREG(0xC000) #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h index 1ca04d5025b..af8a200b213 100644 --- a/arch/arm/mach-s5pv210/include/mach/system.h +++ b/arch/arm/mach-s5pv210/include/mach/system.h @@ -13,12 +13,9 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ -static void arch_idle(void) -{ - /* nothing here yet */ -} +#include <plat/system-reset.h> -static void arch_reset(char mode, const char *cmd) +static void arch_idle(void) { /* nothing here yet */ } diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h index 58f515e0747..df9a2880832 100644 --- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h +++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h @@ -17,6 +17,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H __FILE__ -#define VMALLOC_END (0xE0000000) +#define VMALLOC_END (0xE0000000UL) #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 10bc76ec402..0dda8012d6b 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -13,6 +13,12 @@ #include <linux/init.h> #include <linux/serial_core.h> #include <linux/fb.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/mfd/max8998.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -23,61 +29,69 @@ #include <mach/regs-clock.h> #include <mach/regs-fb.h> +#include <plat/gpio-cfg.h> #include <plat/regs-serial.h> #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/fb.h> +#include <plat/fimc-core.h> +#include <plat/sdhci.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) +#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE -static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { +static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + /* + * Actually UART0 can support 256 bytes fifo, but aquila board + * supports 128 bytes fifo because of initial chip bug + */ + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = AQUILA_UCON_DEFAULT, + .ulcon = AQUILA_ULCON_DEFAULT, + .ufcon = AQUILA_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, }; /* Frame Buffer */ static struct s3c_fb_pd_win aquila_fb_win0 = { .win_mode = { - .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), .left_margin = 16, .right_margin = 16, .upper_margin = 3, @@ -93,7 +107,6 @@ static struct s3c_fb_pd_win aquila_fb_win0 = { static struct s3c_fb_pd_win aquila_fb_win1 = { .win_mode = { - .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), .left_margin = 16, .right_margin = 16, .upper_margin = 3, @@ -116,19 +129,383 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = { .setup_gpio = s5pv210_fb_gpio_setup_24bpp, }; +/* MAX8998 regulators */ +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + +static struct regulator_init_data aquila_ldo2_data = { + .constraints = { + .name = "VALIVE_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data aquila_ldo3_data = { + .constraints = { + .name = "VUSB/MIPI_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo4_data = { + .constraints = { + .name = "VDAC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data aquila_ldo5_data = { + .constraints = { + .name = "VTF_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data aquila_ldo6_data = { + .constraints = { + .name = "VCC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data aquila_ldo7_data = { + .constraints = { + .name = "VCC_3.0V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo8_data = { + .constraints = { + .name = "VUSB/VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo9_data = { + .constraints = { + .name = "VCC/VCAM_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo10_data = { + .constraints = { + .name = "VPLL_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo11_data = { + .constraints = { + .name = "CAM_IO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo12_data = { + .constraints = { + .name = "CAM_ISP_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo13_data = { + .constraints = { + .name = "CAM_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo14_data = { + .constraints = { + .name = "CAM_CIF_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo15_data = { + .constraints = { + .name = "CAM_AF_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo16_data = { + .constraints = { + .name = "VMIPI_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data aquila_ldo17_data = { + .constraints = { + .name = "CAM_8M_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +/* BUCK */ +static struct regulator_consumer_supply buck1_consumer[] = { + { .supply = "vddarm", }, +}; + +static struct regulator_consumer_supply buck2_consumer[] = { + { .supply = "vddint", }, +}; + +static struct regulator_init_data aquila_buck1_data = { + .constraints = { + .name = "VARM_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + +static struct regulator_init_data aquila_buck2_data = { + .constraints = { + .name = "VINT_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data aquila_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data aquila_buck4_data = { + .constraints = { + .name = "CAM_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct max8998_regulator_data aquila_regulators[] = { + { MAX8998_LDO2, &aquila_ldo2_data }, + { MAX8998_LDO3, &aquila_ldo3_data }, + { MAX8998_LDO4, &aquila_ldo4_data }, + { MAX8998_LDO5, &aquila_ldo5_data }, + { MAX8998_LDO6, &aquila_ldo6_data }, + { MAX8998_LDO7, &aquila_ldo7_data }, + { MAX8998_LDO8, &aquila_ldo8_data }, + { MAX8998_LDO9, &aquila_ldo9_data }, + { MAX8998_LDO10, &aquila_ldo10_data }, + { MAX8998_LDO11, &aquila_ldo11_data }, + { MAX8998_LDO12, &aquila_ldo12_data }, + { MAX8998_LDO13, &aquila_ldo13_data }, + { MAX8998_LDO14, &aquila_ldo14_data }, + { MAX8998_LDO15, &aquila_ldo15_data }, + { MAX8998_LDO16, &aquila_ldo16_data }, + { MAX8998_LDO17, &aquila_ldo17_data }, + { MAX8998_BUCK1, &aquila_buck1_data }, + { MAX8998_BUCK2, &aquila_buck2_data }, + { MAX8998_BUCK3, &aquila_buck3_data }, + { MAX8998_BUCK4, &aquila_buck4_data }, +}; + +static struct max8998_platform_data aquila_max8998_pdata = { + .num_regulators = ARRAY_SIZE(aquila_regulators), + .regulators = aquila_regulators, +}; +#endif + +/* GPIO I2C PMIC */ +#define AP_I2C_GPIO_PMIC_BUS_4 4 +static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = { + .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */ + .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */ +}; + +static struct platform_device aquila_i2c_gpio_pmic = { + .name = "i2c-gpio", + .id = AP_I2C_GPIO_PMIC_BUS_4, + .dev = { + .platform_data = &aquila_i2c_gpio_pmic_data, + }, +}; + +static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = { +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + { + /* 0xCC when SRAD = 0 */ + I2C_BOARD_INFO("max8998", 0xCC >> 1), + .platform_data = &aquila_max8998_pdata, + }, +#endif +}; + +/* PMIC Power button */ +static struct gpio_keys_button aquila_gpio_keys_table[] = { + { + .code = KEY_POWER, + .gpio = S5PV210_GPH2(6), + .desc = "gpio-keys: KEY_POWER", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data aquila_gpio_keys_data = { + .buttons = aquila_gpio_keys_table, + .nbuttons = ARRAY_SIZE(aquila_gpio_keys_table), +}; + +static struct platform_device aquila_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &aquila_gpio_keys_data, + }, +}; + +static void __init aquila_pmic_init(void) +{ + /* AP_PMIC_IRQ: EINT7 */ + s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP); + + /* nPower: EINT22 */ + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); +} + +/* MoviNAND */ +static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_PERMANENT, +}; + +/* Wireless LAN */ +static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_EXTERNAL, + /* ext_cd_{init,cleanup} callbacks will be added later */ +}; + +/* External Flash */ +#define AQUILA_EXT_FLASH_EN S5PV210_MP05(4) +#define AQUILA_EXT_FLASH_CD S5PV210_GPH3(4) +static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = AQUILA_EXT_FLASH_CD, + .ext_cd_gpio_invert = 1, +}; + +static void aquila_setup_sdhci(void) +{ + gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN"); + gpio_direction_output(AQUILA_EXT_FLASH_EN, 1); + + s3c_sdhci0_set_platdata(&aquila_hsmmc0_data); + s3c_sdhci1_set_platdata(&aquila_hsmmc1_data); + s3c_sdhci2_set_platdata(&aquila_hsmmc2_data); +}; + static struct platform_device *aquila_devices[] __initdata = { + &aquila_i2c_gpio_pmic, + &aquila_device_gpiokeys, &s3c_device_fb, + &s5pc110_device_onenand, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, }; static void __init aquila_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); s3c24xx_init_clocks(24000000); - s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); + s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs)); } static void __init aquila_machine_init(void) { + /* PMIC */ + aquila_pmic_init(); + i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs, + ARRAY_SIZE(i2c_gpio_pmic_devs)); + /* SDHCI */ + aquila_setup_sdhci(); + + s3c_fimc_setname(0, "s5p-fimc"); + s3c_fimc_setname(1, "s5p-fimc"); + s3c_fimc_setname(2, "s5p-fimc"); + /* FB */ s3c_fb_set_platdata(&aquila_lcd_pdata); diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 4863b13824e..53754d7d364 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -12,6 +12,13 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/fb.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/mfd/max8998.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -20,58 +27,444 @@ #include <mach/map.h> #include <mach/regs-clock.h> +#include <mach/regs-fb.h> +#include <plat/gpio-cfg.h> #include <plat/regs-serial.h> #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/sdhci.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) +#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = GONI_UCON_DEFAULT, + .ulcon = GONI_ULCON_DEFAULT, + .ufcon = GONI_UFCON_DEFAULT | + S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, }, }; +/* Frame Buffer */ +static struct s3c_fb_pd_win goni_fb_win0 = { + .win_mode = { + .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*55), + .left_margin = 16, + .right_margin = 16, + .upper_margin = 3, + .lower_margin = 28, + .hsync_len = 2, + .vsync_len = 2, + .xres = 480, + .yres = 800, + .refresh = 55, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +static struct s3c_fb_platdata goni_lcd_pdata __initdata = { + .win[0] = &goni_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | + VIDCON0_CLKSEL_LCD, + .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN + | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = s5pv210_fb_gpio_setup_24bpp, +}; + +/* MAX8998 regulators */ +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + +static struct regulator_init_data goni_ldo2_data = { + .constraints = { + .name = "VALIVE_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data goni_ldo3_data = { + .constraints = { + .name = "VUSB/MIPI_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo4_data = { + .constraints = { + .name = "VDAC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo5_data = { + .constraints = { + .name = "VTF_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo6_data = { + .constraints = { + .name = "VCC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data goni_ldo7_data = { + .constraints = { + .name = "VLCD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo8_data = { + .constraints = { + .name = "VUSB/VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo9_data = { + .constraints = { + .name = "VCC/VCAM_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo10_data = { + .constraints = { + .name = "VPLL_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo11_data = { + .constraints = { + .name = "CAM_IO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo12_data = { + .constraints = { + .name = "CAM_ISP_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo13_data = { + .constraints = { + .name = "CAM_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo14_data = { + .constraints = { + .name = "CAM_CIF_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo15_data = { + .constraints = { + .name = "CAM_AF_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo16_data = { + .constraints = { + .name = "VMIPI_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data goni_ldo17_data = { + .constraints = { + .name = "VCC_3.0V_LCD", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +/* BUCK */ +static struct regulator_consumer_supply buck1_consumer[] = { + { .supply = "vddarm", }, +}; + +static struct regulator_consumer_supply buck2_consumer[] = { + { .supply = "vddint", }, +}; + +static struct regulator_init_data goni_buck1_data = { + .constraints = { + .name = "VARM_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + +static struct regulator_init_data goni_buck2_data = { + .constraints = { + .name = "VINT_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data goni_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data goni_buck4_data = { + .constraints = { + .name = "CAM_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct max8998_regulator_data goni_regulators[] = { + { MAX8998_LDO2, &goni_ldo2_data }, + { MAX8998_LDO3, &goni_ldo3_data }, + { MAX8998_LDO4, &goni_ldo4_data }, + { MAX8998_LDO5, &goni_ldo5_data }, + { MAX8998_LDO6, &goni_ldo6_data }, + { MAX8998_LDO7, &goni_ldo7_data }, + { MAX8998_LDO8, &goni_ldo8_data }, + { MAX8998_LDO9, &goni_ldo9_data }, + { MAX8998_LDO10, &goni_ldo10_data }, + { MAX8998_LDO11, &goni_ldo11_data }, + { MAX8998_LDO12, &goni_ldo12_data }, + { MAX8998_LDO13, &goni_ldo13_data }, + { MAX8998_LDO14, &goni_ldo14_data }, + { MAX8998_LDO15, &goni_ldo15_data }, + { MAX8998_LDO16, &goni_ldo16_data }, + { MAX8998_LDO17, &goni_ldo17_data }, + { MAX8998_BUCK1, &goni_buck1_data }, + { MAX8998_BUCK2, &goni_buck2_data }, + { MAX8998_BUCK3, &goni_buck3_data }, + { MAX8998_BUCK4, &goni_buck4_data }, +}; + +static struct max8998_platform_data goni_max8998_pdata = { + .num_regulators = ARRAY_SIZE(goni_regulators), + .regulators = goni_regulators, +}; +#endif + +/* GPIO I2C PMIC */ +#define AP_I2C_GPIO_PMIC_BUS_4 4 +static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = { + .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */ + .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */ +}; + +static struct platform_device goni_i2c_gpio_pmic = { + .name = "i2c-gpio", + .id = AP_I2C_GPIO_PMIC_BUS_4, + .dev = { + .platform_data = &goni_i2c_gpio_pmic_data, + }, +}; + +static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = { +#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) + { + /* 0xCC when SRAD = 0 */ + I2C_BOARD_INFO("max8998", 0xCC >> 1), + .platform_data = &goni_max8998_pdata, + }, +#endif +}; + +/* PMIC Power button */ +static struct gpio_keys_button goni_gpio_keys_table[] = { + { + .code = KEY_POWER, + .gpio = S5PV210_GPH2(6), + .desc = "gpio-keys: KEY_POWER", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data goni_gpio_keys_data = { + .buttons = goni_gpio_keys_table, + .nbuttons = ARRAY_SIZE(goni_gpio_keys_table), +}; + +static struct platform_device goni_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &goni_gpio_keys_data, + }, +}; + +static void __init goni_pmic_init(void) +{ + /* AP_PMIC_IRQ: EINT7 */ + s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP); + + /* nPower: EINT22 */ + s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP); +} + +/* MoviNAND */ +static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_PERMANENT, +}; + +/* Wireless LAN */ +static struct s3c_sdhci_platdata goni_hsmmc1_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_EXTERNAL, + /* ext_cd_{init,cleanup} callbacks will be added later */ +}; + +/* External Flash */ +#define GONI_EXT_FLASH_EN S5PV210_MP05(4) +#define GONI_EXT_FLASH_CD S5PV210_GPH3(4) +static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = { + .max_width = 4, + .cd_type = S3C_SDHCI_CD_GPIO, + .ext_cd_gpio = GONI_EXT_FLASH_CD, + .ext_cd_gpio_invert = 1, +}; + +static void goni_setup_sdhci(void) +{ + gpio_request(GONI_EXT_FLASH_EN, "FLASH_EN"); + gpio_direction_output(GONI_EXT_FLASH_EN, 1); + + s3c_sdhci0_set_platdata(&goni_hsmmc0_data); + s3c_sdhci1_set_platdata(&goni_hsmmc1_data); + s3c_sdhci2_set_platdata(&goni_hsmmc2_data); +}; + static struct platform_device *goni_devices[] __initdata = { + &s3c_device_fb, + &s5pc110_device_onenand, + &goni_i2c_gpio_pmic, + &goni_device_gpiokeys, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, }; static void __init goni_map_io(void) @@ -83,6 +476,16 @@ static void __init goni_map_io(void) static void __init goni_machine_init(void) { + /* PMIC */ + goni_pmic_init(); + i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs, + ARRAY_SIZE(i2c_gpio_pmic_devs)); + /* SDHCI */ + goni_setup_sdhci(); + + /* FB */ + s3c_fb_set_platdata(&goni_lcd_pdata); + platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices)); } diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 4c8903c6d10..8211bb87c54 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -12,6 +12,7 @@ #include <linux/types.h> #include <linux/init.h> #include <linux/serial_core.h> +#include <linux/i2c.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -25,18 +26,20 @@ #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/ata.h> +#include <plat/iic.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) @@ -44,39 +47,60 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKC110_UCON_DEFAULT, + .ulcon = SMDKC110_ULCON_DEFAULT, + .ufcon = SMDKC110_UFCON_DEFAULT, }, }; +static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = { + .setup_gpio = s5pv210_ide_setup_gpio, +}; + static struct platform_device *smdkc110_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_ac97, + &s3c_device_cfcon, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c2, + &s3c_device_rtc, &s3c_device_wdt, }; +static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ +}; + +static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = { + /* To Be Updated */ +}; + +static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = { + /* To Be Updated */ +}; + static void __init smdkc110_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -86,6 +110,18 @@ static void __init smdkc110_map_io(void) static void __init smdkc110_machine_init(void) { + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + i2c_register_board_info(0, smdkc110_i2c_devs0, + ARRAY_SIZE(smdkc110_i2c_devs0)); + i2c_register_board_info(1, smdkc110_i2c_devs1, + ARRAY_SIZE(smdkc110_i2c_devs1)); + i2c_register_board_info(2, smdkc110_i2c_devs2, + ARRAY_SIZE(smdkc110_i2c_devs2)); + + s3c_ide_set_platdata(&smdkc110_ide_pdata); + platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices)); } diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 0d462794804..fbbc0a3c373 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/i2c.h> #include <linux/init.h> #include <linux/serial_core.h> @@ -27,18 +28,21 @@ #include <plat/cpu.h> #include <plat/adc.h> #include <plat/ts.h> +#include <plat/ata.h> +#include <plat/iic.h> +#include <plat/keypad.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) @@ -46,41 +50,86 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PV210_UCON_DEFAULT, - .ulcon = S5PV210_ULCON_DEFAULT, - .ufcon = S5PV210_UFCON_DEFAULT, + .ucon = SMDKV210_UCON_DEFAULT, + .ulcon = SMDKV210_ULCON_DEFAULT, + .ufcon = SMDKV210_UFCON_DEFAULT, }, }; +static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = { + .setup_gpio = s5pv210_ide_setup_gpio, +}; + +static uint32_t smdkv210_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), + KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), + KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), + KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) +}; + +static struct matrix_keymap_data smdkv210_keymap_data __initdata = { + .keymap = smdkv210_keymap, + .keymap_size = ARRAY_SIZE(smdkv210_keymap), +}; + +static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = { + .keymap_data = &smdkv210_keymap_data, + .rows = 8, + .cols = 8, +}; + static struct platform_device *smdkv210_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_ac97, &s3c_device_adc, + &s3c_device_cfcon, + &s3c_device_hsmmc0, + &s3c_device_hsmmc1, + &s3c_device_hsmmc2, + &s3c_device_hsmmc3, + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c2, + &samsung_device_keypad, + &s3c_device_rtc, &s3c_device_ts, &s3c_device_wdt, }; +static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ +}; + +static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = { + /* To Be Updated */ +}; + +static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = { + /* To Be Updated */ +}; + static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { .delay = 10000, .presc = 49, @@ -96,7 +145,21 @@ static void __init smdkv210_map_io(void) static void __init smdkv210_machine_init(void) { + samsung_keypad_set_platdata(&smdkv210_keypad_data); s3c24xx_ts_set_platdata(&s3c_ts_platform); + + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + i2c_register_board_info(0, smdkv210_i2c_devs0, + ARRAY_SIZE(smdkv210_i2c_devs0)); + i2c_register_board_info(1, smdkv210_i2c_devs1, + ARRAY_SIZE(smdkv210_i2c_devs1)); + i2c_register_board_info(2, smdkv210_i2c_devs2, + ARRAY_SIZE(smdkv210_i2c_devs2)); + + s3c_ide_set_platdata(&smdkv210_ide_pdata); + platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); } diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c index a50cbac8720..928cf1f125f 100644 --- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c @@ -13,9 +13,9 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/fb.h> +#include <linux/gpio.h> #include <mach/regs-fb.h> -#include <mach/gpio.h> #include <mach/map.h> #include <plat/fb.h> #include <mach/regs-clock.h> diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index c718253c70b..d38f7cb7e66 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c @@ -14,10 +14,10 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> #include <plat/iic.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c index 45e0e6ed2ed..148bb7857d8 100644 --- a/arch/arm/mach-s5pv210/setup-i2c1.c +++ b/arch/arm/mach-s5pv210/setup-i2c1.c @@ -14,10 +14,10 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> #include <plat/iic.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c index b11b4bff69a..2396cb8c373 100644 --- a/arch/arm/mach-s5pv210/setup-i2c2.c +++ b/arch/arm/mach-s5pv210/setup-i2c2.c @@ -14,10 +14,10 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> struct platform_device; /* don't need the contents */ -#include <mach/gpio.h> #include <plat/iic.h> #include <plat/gpio-cfg.h> diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c new file mode 100644 index 00000000000..b558b1cc8d6 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-ide.c @@ -0,0 +1,50 @@ +/* linux/arch/arm/mach-s5pv210/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV210 setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> + +#include <plat/gpio-cfg.h> + +void s5pv210_ide_setup_gpio(void) +{ + unsigned int gpio = 0; + + for (gpio = S5PV210_GPJ0(0); gpio <= S5PV210_GPJ0(7); gpio++) { + /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, + CF_DMACK */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV210_GPJ2(0); gpio <= S5PV210_GPJ2(7); gpio++) { + /*CF_Data[0 - 7] */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV210_GPJ3(0); gpio <= S5PV210_GPJ3(7); gpio++) { + /* CF_Data[8 - 15] */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } + + for (gpio = S5PV210_GPJ4(0); gpio <= S5PV210_GPJ4(3); gpio++) { + /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); + } +} diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c new file mode 100644 index 00000000000..37b2790aafc --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-keypad.c @@ -0,0 +1,34 @@ +/* + * linux/arch/arm/mach-s5pv210/setup-keypad.c + * + * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> + +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) +{ + unsigned int gpio, end; + + /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ + end = S5PV210_GPH3(rows); + for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ + end = S5PV210_GPH2(cols); + for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index fe7d86dad14..b18587b1ec5 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -15,15 +15,17 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/mmc/host.h> #include <linux/mmc/card.h> -#include <mach/gpio.h> #include <plat/gpio-cfg.h> #include <plat/regs-sdhci.h> +#include <plat/sdhci.h> void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; /* Set all the necessary GPG0/GPG1 pins to special-function 2 */ @@ -48,12 +50,15 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) break; } - s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); + } } void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; /* Set all the necessary GPG1[0:1] pins to special-function 2 */ @@ -68,12 +73,15 @@ void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } - s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); + } } void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int gpio; /* Set all the necessary GPG2[0:1] pins to special-function 2 */ @@ -99,6 +107,31 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) break; } - s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); + } +} + +void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) +{ + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; + unsigned int gpio; + + /* Set all the necessary GPG3[0:2] pins to special-function 2 */ + for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + /* Data pin GPG3[3:6] to special-function 2 */ + for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2)); + } } diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index 51815ec60c2..c32e202731c 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -26,9 +26,9 @@ char *s5pv210_hsmmc_clksrcs[4] = { [0] = "hsmmc", /* HCLK */ - [1] = "hsmmc", /* HCLK */ + /* [1] = "hsmmc", - duplicate HCLK entry */ [2] = "sclk_mmc", /* mmc_bus */ - /*[4] = reserved */ + /* [3] = NULL, - reserved */ }; void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig new file mode 100644 index 00000000000..331b5bd97ab --- /dev/null +++ b/arch/arm/mach-s5pv310/Kconfig @@ -0,0 +1,45 @@ +# arch/arm/mach-s5pv310/Kconfig +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +# Configuration options for the S5PV310 + +if ARCH_S5PV310 + +config CPU_S5PV310 + bool + select PLAT_S5P + help + Enable S5PV310 CPU support + +config S5PV310_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + +config S5PV310_SETUP_I2C2 + bool + help + Common setup code for i2c bus 2. + +# machine support + +config MACH_SMDKV310 + bool "SMDKV310" + select CPU_S5PV310 + select ARCH_SPARSEMEM_ENABLE + help + Machine support for Samsung SMDKV310 + +config MACH_UNIVERSAL_C210 + bool "Mobile UNIVERSAL_C210 Board" + select CPU_S5PV310 + select ARCH_SPARSEMEM_ENABLE + help + Machine support for Samsung Mobile Universal S5PC210 Reference + Board. S5PC210(MCP) is one of package option of S5PV310 + +endif diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile new file mode 100644 index 00000000000..d5b51c72340 --- /dev/null +++ b/arch/arm/mach-s5pv310/Makefile @@ -0,0 +1,30 @@ +# arch/arm/mach-s5pv310/Makefile +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S5PV310 system + +obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o +obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o + +obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +# machine support + +obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o +obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o + +# device support + +obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o diff --git a/arch/arm/mach-s5pv310/Makefile.boot b/arch/arm/mach-s5pv310/Makefile.boot new file mode 100644 index 00000000000..d65956ffb43 --- /dev/null +++ b/arch/arm/mach-s5pv310/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c new file mode 100644 index 00000000000..26a0f03df8e --- /dev/null +++ b/arch/arm/mach-s5pv310/clock.c @@ -0,0 +1,588 @@ +/* linux/arch/arm/mach-s5pv310/clock.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/cpu-freq.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/pll.h> +#include <plat/s5p-clock.h> +#include <plat/clock-clksrc.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> + +static struct clk clk_sclk_hdmi27m = { + .name = "sclk_hdmi27m", + .id = -1, + .rate = 27000000, +}; + +static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); +} + +static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); +} + +/* Core list of CMU_CPU side */ + +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_sclk_apll = { + .clk = { + .name = "sclk_apll", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, +}; + +static struct clk *clkset_moutcore_list[] = { + [0] = &clk_sclk_apll.clk, + [1] = &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clkset_moutcore = { + .sources = clkset_moutcore_list, + .nr_sources = ARRAY_SIZE(clkset_moutcore_list), +}; + +static struct clksrc_clk clk_moutcore = { + .clk = { + .name = "moutcore", + .id = -1, + }, + .sources = &clkset_moutcore, + .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk clk_coreclk = { + .clk = { + .name = "core_clk", + .id = -1, + .parent = &clk_moutcore.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk clk_armclk = { + .clk = { + .name = "armclk", + .id = -1, + .parent = &clk_coreclk.clk, + }, +}; + +static struct clksrc_clk clk_aclk_corem0 = { + .clk = { + .name = "aclk_corem0", + .id = -1, + .parent = &clk_coreclk.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk clk_aclk_cores = { + .clk = { + .name = "aclk_cores", + .id = -1, + .parent = &clk_coreclk.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk clk_aclk_corem1 = { + .clk = { + .name = "aclk_corem1", + .id = -1, + .parent = &clk_coreclk.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk clk_periphclk = { + .clk = { + .name = "periphclk", + .id = -1, + .parent = &clk_coreclk.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk clk_atclk = { + .clk = { + .name = "atclk", + .id = -1, + .parent = &clk_moutcore.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk clk_pclk_dbg = { + .clk = { + .name = "pclk_dbg", + .id = -1, + .parent = &clk_atclk.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 }, +}; + +/* Core list of CMU_CORE side */ + +static struct clk *clkset_corebus_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_sclk_apll.clk, +}; + +static struct clksrc_sources clkset_mout_corebus = { + .sources = clkset_corebus_list, + .nr_sources = ARRAY_SIZE(clkset_corebus_list), +}; + +static struct clksrc_clk clk_mout_corebus = { + .clk = { + .name = "mout_corebus", + .id = -1, + }, + .sources = &clkset_mout_corebus, + .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk clk_sclk_dmc = { + .clk = { + .name = "sclk_dmc", + .id = -1, + .parent = &clk_mout_corebus.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk clk_aclk_cored = { + .clk = { + .name = "aclk_cored", + .id = -1, + .parent = &clk_sclk_dmc.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk clk_aclk_corep = { + .clk = { + .name = "aclk_corep", + .id = -1, + .parent = &clk_aclk_cored.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, +}; + +static struct clksrc_clk clk_aclk_acp = { + .clk = { + .name = "aclk_acp", + .id = -1, + .parent = &clk_mout_corebus.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk clk_pclk_acp = { + .clk = { + .name = "pclk_acp", + .id = -1, + .parent = &clk_aclk_acp.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, +}; + +/* Core list of CMU_TOP side */ + +static struct clk *clkset_aclk_top_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_sclk_apll.clk, +}; + +static struct clksrc_sources clkset_aclk_200 = { + .sources = clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), +}; + +static struct clksrc_clk clk_aclk_200 = { + .clk = { + .name = "aclk_200", + .id = -1, + }, + .sources = &clkset_aclk_200, + .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, +}; + +static struct clksrc_sources clkset_aclk_100 = { + .sources = clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), +}; + +static struct clksrc_clk clk_aclk_100 = { + .clk = { + .name = "aclk_100", + .id = -1, + }, + .sources = &clkset_aclk_100, + .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, +}; + +static struct clksrc_sources clkset_aclk_160 = { + .sources = clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), +}; + +static struct clksrc_clk clk_aclk_160 = { + .clk = { + .name = "aclk_160", + .id = -1, + }, + .sources = &clkset_aclk_160, + .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, +}; + +static struct clksrc_sources clkset_aclk_133 = { + .sources = clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), +}; + +static struct clksrc_clk clk_aclk_133 = { + .clk = { + .name = "aclk_133", + .id = -1, + }, + .sources = &clkset_aclk_133, + .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, +}; + +static struct clk *clkset_vpllsrc_list[] = { + [0] = &clk_fin_vpll, + [1] = &clk_sclk_hdmi27m, +}; + +static struct clksrc_sources clkset_vpllsrc = { + .sources = clkset_vpllsrc_list, + .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), +}; + +static struct clksrc_clk clk_vpllsrc = { + .clk = { + .name = "vpll_src", + .id = -1, + }, + .sources = &clkset_vpllsrc, + .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, +}; + +static struct clk *clkset_sclk_vpll_list[] = { + [0] = &clk_vpllsrc.clk, + [1] = &clk_fout_vpll, +}; + +static struct clksrc_sources clkset_sclk_vpll = { + .sources = clkset_sclk_vpll_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), +}; + +static struct clksrc_clk clk_sclk_vpll = { + .clk = { + .name = "sclk_vpll", + .id = -1, + }, + .sources = &clkset_sclk_vpll, + .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, +}; + +static struct clk init_clocks_disable[] = { + { + .name = "timers", + .id = -1, + .parent = &clk_aclk_100.clk, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1<<24), + } +}; + +static struct clk init_clocks[] = { + { + .name = "uart", + .id = 0, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "uart", + .id = 1, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .id = 2, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "uart", + .id = 3, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "uart", + .id = 4, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "uart", + .id = 5, + .enable = s5pv310_clk_ip_peril_ctrl, + .ctrlbit = (1 << 5), + } +}; + +static struct clk *clkset_group_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_xusbxti, + [2] = &clk_sclk_hdmi27m, + [6] = &clk_mout_mpll.clk, + [7] = &clk_mout_epll.clk, + [8] = &clk_sclk_vpll.clk, +}; + +static struct clksrc_sources clkset_group = { + .sources = clkset_group_list, + .nr_sources = ARRAY_SIZE(clkset_group_list), +}; + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "uclk1", + .id = 0, + .enable = s5pv310_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 1, + .enable = s5pv310_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 2, + .enable = s5pv310_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = 3, + .enable = s5pv310_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_pwm", + .id = -1, + .enable = s5pv310_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, + }, +}; + +/* Clock initialization code */ +static struct clksrc_clk *sysclks[] = { + &clk_mout_apll, + &clk_sclk_apll, + &clk_mout_epll, + &clk_mout_mpll, + &clk_moutcore, + &clk_coreclk, + &clk_armclk, + &clk_aclk_corem0, + &clk_aclk_cores, + &clk_aclk_corem1, + &clk_periphclk, + &clk_atclk, + &clk_pclk_dbg, + &clk_mout_corebus, + &clk_sclk_dmc, + &clk_aclk_cored, + &clk_aclk_corep, + &clk_aclk_acp, + &clk_pclk_acp, + &clk_vpllsrc, + &clk_sclk_vpll, + &clk_aclk_200, + &clk_aclk_100, + &clk_aclk_160, + &clk_aclk_133, +}; + +void __init_or_cpufreq s5pv310_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long apll; + unsigned long mpll; + unsigned long epll; + unsigned long vpll; + unsigned long vpllsrc; + unsigned long xtal; + unsigned long armclk; + unsigned long aclk_corem0; + unsigned long aclk_cores; + unsigned long aclk_corem1; + unsigned long periphclk; + unsigned long sclk_dmc; + unsigned long aclk_cored; + unsigned long aclk_corep; + unsigned long aclk_acp; + unsigned long pclk_acp; + unsigned int ptr; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); + epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), + __raw_readl(S5P_EPLL_CON1), pll_4600); + + vpllsrc = clk_get_rate(&clk_vpllsrc.clk); + vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), + __raw_readl(S5P_VPLL_CON1), pll_4650); + + clk_fout_apll.rate = apll; + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_vpll.rate = vpll; + + printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", + apll, mpll, epll, vpll); + + armclk = clk_get_rate(&clk_armclk.clk); + aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk); + aclk_cores = clk_get_rate(&clk_aclk_cores.clk); + aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk); + periphclk = clk_get_rate(&clk_periphclk.clk); + sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); + aclk_cored = clk_get_rate(&clk_aclk_cored.clk); + aclk_corep = clk_get_rate(&clk_aclk_corep.clk); + aclk_acp = clk_get_rate(&clk_aclk_acp.clk); + pclk_acp = clk_get_rate(&clk_pclk_acp.clk); + + printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n" + "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n" + "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld", + armclk, aclk_corem0, aclk_cores, aclk_corem1, + periphclk, sclk_dmc, aclk_cored, aclk_corep, + aclk_acp, pclk_acp); + + clk_f.rate = armclk; + clk_h.rate = sclk_dmc; + clk_p.rate = periphclk; + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); +} + +static struct clk *clks[] __initdata = { + /* Nothing here yet */ +}; + +void __init s5pv310_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + + ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + if (ret > 0) + printk(KERN_ERR "Failed to register %u clocks\n", ret); + + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + (clkp->enable)(clkp, 0); + } + + s3c_pwmclk_init(); +} diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c new file mode 100644 index 00000000000..e5b261a99ab --- /dev/null +++ b/arch/arm/mach-s5pv310/cpu.c @@ -0,0 +1,132 @@ +/* linux/arch/arm/mach-s5pv310/cpu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/sched.h> +#include <linux/sysdev.h> + +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/proc-fns.h> + +#include <plat/cpu.h> +#include <plat/clock.h> +#include <plat/s5pv310.h> + +#include <mach/regs-irq.h> + +void __iomem *gic_cpu_base_addr; + +extern int combiner_init(unsigned int combiner_nr, void __iomem *base, + unsigned int irq_start); +extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); + +/* Initial IO mappings */ +static struct map_desc s5pv310_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_COREPERI_BASE, + .pfn = __phys_to_pfn(S5PV310_PA_COREPERI), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_COMBINER_BASE, + .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_L2CC, + .pfn = __phys_to_pfn(S5PV310_PA_L2CC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_CMU, + .pfn = __phys_to_pfn(S5PV310_PA_CMU), + .length = SZ_128K, + .type = MT_DEVICE, + }, +}; + +static void s5pv310_idle(void) +{ + if (!need_resched()) + cpu_do_idle(); + + local_irq_enable(); +} + +/* s5pv310_map_io + * + * register the standard cpu IO areas +*/ +void __init s5pv310_map_io(void) +{ + iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); +} + +void __init s5pv310_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5pv310_register_clocks(); + s5pv310_setup_clocks(); +} + +void __init s5pv310_init_irq(void) +{ + int irq; + + gic_cpu_base_addr = S5P_VA_GIC_CPU; + gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER); + gic_cpu_init(0, S5P_VA_GIC_CPU); + + for (irq = 0; irq < MAX_COMBINER_NR; irq++) { + combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), + COMBINER_IRQ(irq, 0)); + combiner_cascade_irq(irq, IRQ_SPI(irq)); + } + + /* The parameters of s5p_init_irq() are for VIC init. + * Theses parameters should be NULL and 0 because S5PV310 + * uses GIC instead of VIC. + */ + s5p_init_irq(NULL, 0); +} + +struct sysdev_class s5pv310_sysclass = { + .name = "s5pv310-core", +}; + +static struct sys_device s5pv310_sysdev = { + .cls = &s5pv310_sysclass, +}; + +static int __init s5pv310_core_init(void) +{ + return sysdev_class_register(&s5pv310_sysclass); +} + +core_initcall(s5pv310_core_init); + +int __init s5pv310_init(void) +{ + printk(KERN_INFO "S5PV310: Initializing architecture\n"); + + /* set idle function */ + pm_idle = s5pv310_idle; + + return sysdev_register(&s5pv310_sysdev); +} diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-s5pv310/headsmp.S new file mode 100644 index 00000000000..164b7b04571 --- /dev/null +++ b/arch/arm/mach-s5pv310/headsmp.S @@ -0,0 +1,41 @@ +/* + * linux/arch/arm/mach-s5pv310/headsmp.S + * + * Cloned from linux/arch/arm/mach-realview/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * s5pv310 specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(s5pv310_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + +1: .long . + .long pen_release diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-s5pv310/include/mach/debug-macro.S new file mode 100644 index 00000000000..6fb3893486b --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S3C_PA_UART + ldrne \rx, = S3C_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(0x10000 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +#define fifo_full fifo_full_s5pv210 +#define fifo_level fifo_level_s5pv210 + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-s5pv310/include/mach/entry-macro.S new file mode 100644 index 00000000000..e600e1d522d --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/entry-macro.S @@ -0,0 +1,84 @@ +/* arch/arm/mach-s5pv310/include/mach/entry-macro.S + * + * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for S5PV310 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include <mach/hardware.h> +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt if it's + * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number of the highest + * priority enabled interrupt. We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + addne \irqnr, \irqnr, #32 + + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h new file mode 100644 index 00000000000..20cb80c2346 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/gpio.h @@ -0,0 +1,135 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* Practically, GPIO banks upto GPZ are the configurable gpio banks */ + +/* GPIO bank sizes */ +#define S5PV310_GPIO_A0_NR (8) +#define S5PV310_GPIO_A1_NR (6) +#define S5PV310_GPIO_B_NR (8) +#define S5PV310_GPIO_C0_NR (5) +#define S5PV310_GPIO_C1_NR (5) +#define S5PV310_GPIO_D0_NR (4) +#define S5PV310_GPIO_D1_NR (4) +#define S5PV310_GPIO_E0_NR (5) +#define S5PV310_GPIO_E1_NR (8) +#define S5PV310_GPIO_E2_NR (6) +#define S5PV310_GPIO_E3_NR (8) +#define S5PV310_GPIO_E4_NR (8) +#define S5PV310_GPIO_F0_NR (8) +#define S5PV310_GPIO_F1_NR (8) +#define S5PV310_GPIO_F2_NR (8) +#define S5PV310_GPIO_F3_NR (6) +#define S5PV310_GPIO_J0_NR (8) +#define S5PV310_GPIO_J1_NR (5) +#define S5PV310_GPIO_K0_NR (7) +#define S5PV310_GPIO_K1_NR (7) +#define S5PV310_GPIO_K2_NR (7) +#define S5PV310_GPIO_K3_NR (7) +#define S5PV310_GPIO_L0_NR (8) +#define S5PV310_GPIO_L1_NR (3) +#define S5PV310_GPIO_L2_NR (8) +#define S5PV310_GPIO_X0_NR (8) +#define S5PV310_GPIO_X1_NR (8) +#define S5PV310_GPIO_X2_NR (8) +#define S5PV310_GPIO_X3_NR (8) +#define S5PV310_GPIO_Z_NR (7) + +/* GPIO bank numbers */ + +#define S5PV310_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s5p_gpio_number { + S5PV310_GPIO_A0_START = 0, + S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0), + S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1), + S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B), + S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0), + S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1), + S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0), + S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1), + S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0), + S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1), + S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2), + S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3), + S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4), + S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0), + S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1), + S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2), + S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3), + S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0), + S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1), + S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0), + S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1), + S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2), + S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3), + S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0), + S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1), + S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2), + S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0), + S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1), + S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2), + S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3), +}; + +/* S5PV310 GPIO number definitions */ +#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr)) +#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr)) +#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr)) +#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr)) +#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr)) +#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr)) +#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr)) +#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr)) +#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr)) +#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr)) +#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr)) +#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr)) +#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr)) +#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr)) +#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr)) +#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr)) +#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr)) +#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr)) +#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr)) +#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr)) +#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr)) +#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr)) +#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr)) +#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr)) +#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr)) +#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr)) +#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr)) +#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr)) +#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr)) +#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr)) + +/* the end of the S5PV310 specific gpios */ +#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1) +#define S3C_GPIO_END S5PV310_GPIO_END + +/* define the number of gpios we need to the one after the GPZ() range */ +#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \ + CONFIG_SAMSUNG_GPIO_EXTRA + 1) + +#include <asm-generic/gpio.h> + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-s5pv310/include/mach/hardware.h new file mode 100644 index 00000000000..28ff9881f1a --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Hardware support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-s5pv310/include/mach/io.h new file mode 100644 index 00000000000..8a7f9128391 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/io.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/io.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> + * + * Based on arch/arm/mach-s5p6442/include/mach/io.h + * + * Default IO routines for S5PV310 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H __FILE__ + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif /* __ASM_ARM_ARCH_IO_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h new file mode 100644 index 00000000000..4cdedda6e65 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -0,0 +1,77 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - IRQ definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +#include <plat/irqs.h> + +/* PPI: Private Peripheral Interrupt */ + +#define IRQ_PPI(x) S5P_IRQ(x+16) + +#define IRQ_LOCALTIMER IRQ_PPI(13) + +/* SPI: Shared Peripheral Interrupt */ + +#define IRQ_SPI(x) S5P_IRQ(x+32) + +#define IRQ_EINT0 IRQ_SPI(40) +#define IRQ_EINT1 IRQ_SPI(41) +#define IRQ_EINT2 IRQ_SPI(42) +#define IRQ_EINT3 IRQ_SPI(43) +#define IRQ_USB_HSOTG IRQ_SPI(44) +#define IRQ_USB_HOST IRQ_SPI(45) +#define IRQ_MODEM_IF IRQ_SPI(46) +#define IRQ_ROTATOR IRQ_SPI(47) +#define IRQ_JPEG IRQ_SPI(48) +#define IRQ_2D IRQ_SPI(49) +#define IRQ_PCIE IRQ_SPI(50) +#define IRQ_SYSTEM_TIMER IRQ_SPI(51) +#define IRQ_MFC IRQ_SPI(52) +#define IRQ_WDT IRQ_SPI(53) +#define IRQ_AUDIO_SS IRQ_SPI(54) +#define IRQ_AC97 IRQ_SPI(55) +#define IRQ_SPDIF IRQ_SPI(56) +#define IRQ_KEYPAD IRQ_SPI(57) +#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58) +#define IRQ_SLIMBUS IRQ_SPI(59) +#define IRQ_PMU IRQ_SPI(60) +#define IRQ_TSI IRQ_SPI(61) +#define IRQ_SATA IRQ_SPI(62) +#define IRQ_GPS IRQ_SPI(63) + +#define MAX_IRQ_IN_COMBINER 8 +#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) +#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) + +#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0) +#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1) +#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2) +#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3) +#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4) + +#define IRQ_UART0 COMBINER_IRQ(26, 0) +#define IRQ_UART1 COMBINER_IRQ(26, 1) +#define IRQ_UART2 COMBINER_IRQ(26, 2) +#define IRQ_UART3 COMBINER_IRQ(26, 3) +#define IRQ_UART4 COMBINER_IRQ(26, 4) + +#define IRQ_IIC COMBINER_IRQ(27, 0) + +/* Set the default NR_IRQS */ + +#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) + +#define MAX_COMBINER_NR 39 + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h new file mode 100644 index 00000000000..213e1101a3b --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -0,0 +1,81 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/map.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include <plat/map-base.h> + +/* + * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400. + * So need to define it, and here is to avoid redefinition warning. + */ +#define S3C_UART_OFFSET (0x10000) + +#include <plat/map-s5p.h> + +#define S5PV310_PA_SYSRAM (0x02025000) + +#define S5PV310_PA_CHIPID (0x10000000) +#define S5P_PA_CHIPID S5PV310_PA_CHIPID + +#define S5PV310_PA_SYSCON (0x10020000) +#define S5P_PA_SYSCON S5PV310_PA_SYSCON + +#define S5PV310_PA_CMU (0x10030000) + +#define S5PV310_PA_WATCHDOG (0x10060000) + +#define S5PV310_PA_COMBINER (0x10448000) + +#define S5PV310_PA_COREPERI (0x10500000) +#define S5PV310_PA_GIC_CPU (0x10500100) +#define S5PV310_PA_TWD (0x10500600) +#define S5PV310_PA_GIC_DIST (0x10501000) +#define S5PV310_PA_L2CC (0x10502000) + +#define S5PV310_PA_GPIO1 (0x11400000) +#define S5PV310_PA_GPIO2 (0x11000000) +#define S5PV310_PA_GPIO3 (0x03860000) +#define S5P_PA_GPIO S5PV310_PA_GPIO1 + +#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) + +#define S5PV310_PA_UART (0x13800000) + +#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) +#define S5P_PA_UART0 S5P_PA_UART(0) +#define S5P_PA_UART1 S5P_PA_UART(1) +#define S5P_PA_UART2 S5P_PA_UART(2) +#define S5P_PA_UART3 S5P_PA_UART(3) +#define S5P_PA_UART4 S5P_PA_UART(4) + +#define S5P_SZ_UART SZ_256 + +#define S5PV310_PA_IIC0 (0x13860000) + +#define S5PV310_PA_TIMER (0x139D0000) +#define S5P_PA_TIMER S5PV310_PA_TIMER + +#define S5PV310_PA_SDRAM (0x40000000) +#define S5P_PA_SDRAM S5PV310_PA_SDRAM + +/* compatibiltiy defines. */ +#define S3C_PA_UART S5PV310_PA_UART +#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) +#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) +#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) +#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3) +#define S3C_PA_IIC S5PV310_PA_IIC0 +#define S3C_PA_WDT S5PV310_PA_WATCHDOG + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h new file mode 100644 index 00000000000..1dffb482324 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/memory.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/memory.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Memory definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H __FILE__ + +#define PHYS_OFFSET UL(0x40000000) + +/* Maximum of 256MiB in one bank */ +#define MAX_PHYSMEM_BITS 32 +#define SECTION_SIZE_BITS 28 + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h b/arch/arm/mach-s5pv310/include/mach/pwm-clock.h new file mode 100644 index 00000000000..7e6da270108 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/pwm-clock.h @@ -0,0 +1,70 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h + * + * S5PV310 - pwm clock and timer support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_PWMCLK_H +#define __ASM_ARCH_PWMCLK_H __FILE__ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @tcfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg == S3C64XX_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << tcfg1; +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 1; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div); +} + +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK + +#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h new file mode 100644 index 00000000000..4013553cd9b --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h @@ -0,0 +1,63 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - Clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#include <mach/map.h> + +#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) + +#define S5P_INFORM0 S5P_CLKREG(0x800) + +#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) +#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) +#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) +#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) + +#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) +#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) + +#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) + +#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) + +#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) +#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) +#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) +#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) +#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) +#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) + +#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) + +#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) + +#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) +#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) + +#define S5P_APLL_LOCK S5P_CLKREG(0x14000) +#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) +#define S5P_APLL_CON0 S5P_CLKREG(0x14100) +#define S5P_APLL_CON1 S5P_CLKREG(0x14104) +#define S5P_MPLL_CON0 S5P_CLKREG(0x14108) +#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) + +#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) +#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) + +#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) +#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) + +#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-irq.h b/arch/arm/mach-s5pv310/include/mach/regs-irq.h new file mode 100644 index 00000000000..c6e09c7f916 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/regs-irq.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include <asm/hardware/gic.h> +#include <mach/map.h> + +#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h new file mode 100644 index 00000000000..990f3ba88a1 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/smp.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/smp.h + * + * Cloned from arch/arm/mach-realview/include/mach/smp.h +*/ + +#ifndef ASM_ARCH_SMP_H +#define ASM_ARCH_SMP_H __FILE__ + +#include <asm/hardware/gic.h> + +extern void __iomem *gic_cpu_base_addr; + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x03; \ + }) + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} + +#endif diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-s5pv310/include/mach/system.h new file mode 100644 index 00000000000..d10c009cf0f --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/system.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/system.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - system support header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +#include <plat/system-reset.h> + +static void arch_idle(void) +{ + /* nothing here yet */ +} +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-s5pv310/include/mach/timex.h new file mode 100644 index 00000000000..bd2359b952b --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/timex.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/timex.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright (c) 2003-2010 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Based on arch/arm/mach-s5p6442/include/mach/timex.h + * + * S5PV310 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H __FILE__ + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-s5pv310/include/mach/uncompress.h new file mode 100644 index 00000000000..59593c1e241 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/uncompress.h @@ -0,0 +1,30 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV310 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H __FILE__ + +#include <mach/map.h> +#include <plat/uncompress.h> + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ + + /* + * For preventing FIFO overrun or infinite loop of UART console, + * fifo_max should be the minimum fifo size of all of the UART channels + */ + fifo_mask = S5PV210_UFSTAT_TXMASK; + fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT; +} +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h new file mode 100644 index 00000000000..256f221edf3 --- /dev/null +++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2010 Ben Dooks <ben-linux@fluff.org> + * + * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S5PV310 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H __FILE__ + +#define VMALLOC_END (0xF0000000UL) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-s5pv310/init.c new file mode 100644 index 00000000000..182dcf42cfb --- /dev/null +++ b/arch/arm/mach-s5pv310/init.c @@ -0,0 +1,41 @@ +/* linux/arch/arm/mach-s5pv310/init.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/serial_core.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/regs-serial.h> + +static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = { + [0] = { + .name = "uclk1", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, +}; + +/* uart registration process */ +void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + struct s3c2410_uartcfg *tcfg = cfg; + u32 ucnt; + + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { + if (!tcfg->clocks) { + tcfg->has_fracval = 1; + tcfg->clocks = s5pv310_serial_clocks; + tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks); + } + } + + s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); +} diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c new file mode 100644 index 00000000000..0f7052164f2 --- /dev/null +++ b/arch/arm/mach-s5pv310/irq-combiner.c @@ -0,0 +1,125 @@ +/* linux/arch/arm/mach-s5pv310/irq-combiner.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/common/gic.c + * + * IRQ COMBINER support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/io.h> + +#include <asm/mach/irq.h> + +#define COMBINER_ENABLE_SET 0x0 +#define COMBINER_ENABLE_CLEAR 0x4 +#define COMBINER_INT_STATUS 0xC + +static DEFINE_SPINLOCK(irq_controller_lock); + +struct combiner_chip_data { + unsigned int irq_offset; + void __iomem *base; +}; + +static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; + +static inline void __iomem *combiner_base(unsigned int irq) +{ + struct combiner_chip_data *combiner_data = get_irq_chip_data(irq); + return combiner_data->base; +} + +static void combiner_mask_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + + __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR); +} + +static void combiner_unmask_irq(unsigned int irq) +{ + u32 mask = 1 << (irq % 32); + + __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET); +} + +static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) +{ + struct combiner_chip_data *chip_data = get_irq_data(irq); + struct irq_chip *chip = get_irq_chip(irq); + unsigned int cascade_irq, combiner_irq; + unsigned long status; + + /* primary controller ack'ing */ + chip->ack(irq); + + spin_lock(&irq_controller_lock); + status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); + spin_unlock(&irq_controller_lock); + + if (status == 0) + goto out; + + for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) { + if (status & 0x1) + break; + status >>= 1; + } + + cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); + if (unlikely(cascade_irq >= NR_IRQS)) + do_bad_IRQ(cascade_irq, desc); + else + generic_handle_irq(cascade_irq); + + out: + /* primary controller unmasking */ + chip->unmask(irq); +} + +static struct irq_chip combiner_chip = { + .name = "COMBINER", + .mask = combiner_mask_irq, + .unmask = combiner_unmask_irq, +}; + +void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) +{ + if (combiner_nr >= MAX_COMBINER_NR) + BUG(); + if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) + BUG(); + set_irq_chained_handler(irq, combiner_handle_cascade_irq); +} + +void __init combiner_init(unsigned int combiner_nr, void __iomem *base, + unsigned int irq_start) +{ + unsigned int i; + + if (combiner_nr >= MAX_COMBINER_NR) + BUG(); + + combiner_data[combiner_nr].base = base; + combiner_data[combiner_nr].irq_offset = irq_start; + + /* Disable all interrupts */ + + __raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR); + + /* Setup the Linux IRQ subsystem */ + + for (i = irq_start; i < combiner_data[combiner_nr].irq_offset + + MAX_IRQ_IN_COMBINER; i++) { + set_irq_chip(i, &combiner_chip); + set_irq_chip_data(i, &combiner_data[combiner_nr]); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } +} diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-s5pv310/localtimer.c new file mode 100644 index 00000000000..2784036cd8b --- /dev/null +++ b/arch/arm/mach-s5pv310/localtimer.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/mach-s5pv310/localtimer.c + * + * Cloned from linux/arch/arm/mach-realview/localtimer.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clockchips.h> + +#include <asm/irq.h> +#include <asm/localtimer.h> + +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + evt->irq = IRQ_LOCALTIMER; + twd_timer_setup(evt); +} diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c new file mode 100644 index 00000000000..0d6ab77709d --- /dev/null +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -0,0 +1,92 @@ +/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <asm/hardware/cache-l2x0.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv310.h> +#include <plat/cpu.h> + +#include <mach/map.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDKV310_UCON_DEFAULT, + .ulcon = SMDKV310_ULCON_DEFAULT, + .ufcon = SMDKV310_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDKV310_UCON_DEFAULT, + .ulcon = SMDKV310_ULCON_DEFAULT, + .ufcon = SMDKV310_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDKV310_UCON_DEFAULT, + .ulcon = SMDKV310_ULCON_DEFAULT, + .ufcon = SMDKV310_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDKV310_UCON_DEFAULT, + .ulcon = SMDKV310_ULCON_DEFAULT, + .ufcon = SMDKV310_UFCON_DEFAULT, + }, +}; + +static void __init smdkv310_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); +} + +static void __init smdkv310_machine_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); +#endif +} + +MACHINE_START(SMDKV310, "SMDKV310") + /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ + /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv310_init_irq, + .map_io = smdkv310_map_io, + .init_machine = smdkv310_machine_init, + .timer = &s5pv310_timer, +MACHINE_END diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c new file mode 100644 index 00000000000..2388cb94793 --- /dev/null +++ b/arch/arm/mach-s5pv310/mach-universal_c210.c @@ -0,0 +1,86 @@ +/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <asm/hardware/cache-l2x0.h> + +#include <plat/regs-serial.h> +#include <plat/s5pv310.h> +#include <plat/cpu.h> + +#include <mach/map.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG256 | \ + S5PV210_UFCON_RXTRIG256) + +static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .ucon = UNIVERSAL_UCON_DEFAULT, + .ulcon = UNIVERSAL_ULCON_DEFAULT, + .ufcon = UNIVERSAL_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .ucon = UNIVERSAL_UCON_DEFAULT, + .ulcon = UNIVERSAL_ULCON_DEFAULT, + .ufcon = UNIVERSAL_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .ucon = UNIVERSAL_UCON_DEFAULT, + .ulcon = UNIVERSAL_ULCON_DEFAULT, + .ufcon = UNIVERSAL_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .ucon = UNIVERSAL_UCON_DEFAULT, + .ulcon = UNIVERSAL_ULCON_DEFAULT, + .ufcon = UNIVERSAL_UFCON_DEFAULT, + }, +}; + +static void __init universal_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); +} + +static void __init universal_machine_init(void) +{ +#ifdef CONFIG_CACHE_L2X0 + l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); +#endif +} + +MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") + /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5pv310_init_irq, + .map_io = universal_map_io, + .init_machine = universal_machine_init, + .timer = &s5pv310_timer, +MACHINE_END diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c new file mode 100644 index 00000000000..d357c198ede --- /dev/null +++ b/arch/arm/mach-s5pv310/platsmp.c @@ -0,0 +1,192 @@ +/* linux/arch/arm/mach-s5pv310/platsmp.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Cloned from linux/arch/arm/mach-vexpress/platsmp.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> +#include <asm/localtimer.h> +#include <asm/smp_scu.h> +#include <asm/unified.h> + +#include <mach/hardware.h> +#include <mach/regs-clock.h> + +extern void s5pv310_secondary_startup(void); + +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ + +volatile int __cpuinitdata pen_release = -1; + +static void __iomem *scu_base_addr(void) +{ + return (void __iomem *)(S5P_VA_SCU); +} + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_cpu_init(0, gic_cpu_base_addr); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + pen_release = cpu; + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + smp_cross_call(cpumask_of(cpu)); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ + +void __init smp_init_cpus(void) +{ + void __iomem *scu_base = scu_base_addr(); + unsigned int i, ncores; + + ncores = scu_base ? scu_get_core_count(scu_base) : 1; + + /* sanity check */ + if (ncores == 0) { + printk(KERN_ERR + "S5PV310: strange CM count of 0? Default to 1\n"); + + ncores = 1; + } + + if (ncores > NR_CPUS) { + printk(KERN_WARNING + "S5PV310: no. of cores (%d) greater than configured " + "maximum of %d - clipping\n", + ncores, NR_CPUS); + ncores = NR_CPUS; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); +} + +void __init smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned int ncores = num_possible_cpus(); + unsigned int cpu = smp_processor_id(); + int i; + + smp_store_cpu_info(cpu); + + /* are we trying to boot more cores than exist? */ + if (max_cpus > ncores) + max_cpus = ncores; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + /* + * Initialise the SCU if there are more than one CPU and let + * them know where to start. + */ + if (max_cpus > 1) { + /* + * Enable the local timer or broadcast device for the + * boot CPU, but only if we have more than one CPU. + */ + percpu_timer_setup(); + + scu_enable(scu_base_addr()); + + /* + * Write the address of secondary startup into the + * system-wide flags register. The boot monitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. + */ + __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); + } +} diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c new file mode 100644 index 00000000000..43671280738 --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c0.c @@ -0,0 +1,28 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c0.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include <linux/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV310_GPD1(0), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPD1(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV310_GPD1(1), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPD1(1), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c new file mode 100644 index 00000000000..1ecd5bc35b5 --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c1.c @@ -0,0 +1,25 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c1.c + * + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * I2C1 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include <linux/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV310_GPD1(2), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPD1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV310_GPD1(3), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV310_GPD1(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c new file mode 100644 index 00000000000..4c0d8def660 --- /dev/null +++ b/arch/arm/mach-s5pv310/setup-i2c2.c @@ -0,0 +1,25 @@ +/* + * linux/arch/arm/mach-s5pv310/setup-i2c2.c + * + * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. + * + * I2C2 GPIO configuration. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct platform_device; /* don't need the contents */ + +#include <linux/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c2_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S5PV310_GPA0(6), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PV310_GPA0(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PV310_GPA0(7), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(S5PV310_GPA0(7), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-s5pv310/time.c new file mode 100644 index 00000000000..01b012ad1bf --- /dev/null +++ b/arch/arm/mach-s5pv310/time.c @@ -0,0 +1,287 @@ +/* linux/arch/arm/mach-s5pv310/time.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV310 (and compatible) HRT support + * PWM 2/4 is used for this feature + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/clockchips.h> +#include <linux/platform_device.h> + +#include <asm/smp_twd.h> + +#include <mach/map.h> +#include <plat/regs-timer.h> +#include <asm/mach/time.h> + +static unsigned long clock_count_per_tick; + +static struct clk *tin2; +static struct clk *tin4; +static struct clk *tdiv2; +static struct clk *tdiv4; +static struct clk *timerclk; + +static void s5pv310_pwm_stop(unsigned int pwm_id) +{ + unsigned long tcon; + + tcon = __raw_readl(S3C2410_TCON); + + switch (pwm_id) { + case 2: + tcon &= ~S3C2410_TCON_T2START; + break; + case 4: + tcon &= ~S3C2410_TCON_T4START; + break; + default: + break; + } + __raw_writel(tcon, S3C2410_TCON); +} + +static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt) +{ + unsigned long tcon; + + tcon = __raw_readl(S3C2410_TCON); + + /* timers reload after counting zero, so reduce the count by 1 */ + tcnt--; + + /* ensure timer is stopped... */ + switch (pwm_id) { + case 2: + tcon &= ~(0xf<<12); + tcon |= S3C2410_TCON_T2MANUALUPD; + + __raw_writel(tcnt, S3C2410_TCNTB(2)); + __raw_writel(tcnt, S3C2410_TCMPB(2)); + __raw_writel(tcon, S3C2410_TCON); + + break; + case 4: + tcon &= ~(7<<20); + tcon |= S3C2410_TCON_T4MANUALUPD; + + __raw_writel(tcnt, S3C2410_TCNTB(4)); + __raw_writel(tcnt, S3C2410_TCMPB(4)); + __raw_writel(tcon, S3C2410_TCON); + + break; + default: + break; + } +} + +static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic) +{ + unsigned long tcon; + + tcon = __raw_readl(S3C2410_TCON); + + switch (pwm_id) { + case 2: + tcon |= S3C2410_TCON_T2START; + tcon &= ~S3C2410_TCON_T2MANUALUPD; + + if (periodic) + tcon |= S3C2410_TCON_T2RELOAD; + else + tcon &= ~S3C2410_TCON_T2RELOAD; + break; + case 4: + tcon |= S3C2410_TCON_T4START; + tcon &= ~S3C2410_TCON_T4MANUALUPD; + + if (periodic) + tcon |= S3C2410_TCON_T4RELOAD; + else + tcon &= ~S3C2410_TCON_T4RELOAD; + break; + default: + break; + } + __raw_writel(tcon, S3C2410_TCON); +} + +static int s5pv310_pwm_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + s5pv310_pwm_init(2, cycles); + s5pv310_pwm_start(2, 0); + return 0; +} + +static void s5pv310_pwm_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + s5pv310_pwm_stop(2); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + s5pv310_pwm_init(2, clock_count_per_tick); + s5pv310_pwm_start(2, 1); + break; + case CLOCK_EVT_MODE_ONESHOT: + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device pwm_event_device = { + .name = "pwm_timer2", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .shift = 32, + .set_next_event = s5pv310_pwm_set_next_event, + .set_mode = s5pv310_pwm_set_mode, +}; + +irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id) +{ + struct clock_event_device *evt = &pwm_event_device; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction s5pv310_clock_event_irq = { + .name = "pwm_timer2_irq", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = s5pv310_clock_event_isr, +}; + +static void __init s5pv310_clockevent_init(void) +{ + unsigned long pclk; + unsigned long clock_rate; + struct clk *tscaler; + + pclk = clk_get_rate(timerclk); + + /* configure clock tick */ + + tscaler = clk_get_parent(tdiv2); + + clk_set_rate(tscaler, pclk / 2); + clk_set_rate(tdiv2, pclk / 2); + clk_set_parent(tin2, tdiv2); + + clock_rate = clk_get_rate(tin2); + + clock_count_per_tick = clock_rate / HZ; + + pwm_event_device.mult = + div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift); + pwm_event_device.max_delta_ns = + clockevent_delta2ns(-1, &pwm_event_device); + pwm_event_device.min_delta_ns = + clockevent_delta2ns(1, &pwm_event_device); + + pwm_event_device.cpumask = cpumask_of(0); + clockevents_register_device(&pwm_event_device); + + setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq); +} + +static cycle_t s5pv310_pwm4_read(struct clocksource *cs) +{ + return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40)); +} + +struct clocksource pwm_clocksource = { + .name = "pwm_timer4", + .rating = 250, + .read = s5pv310_pwm4_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS , +}; + +static void __init s5pv310_clocksource_init(void) +{ + unsigned long pclk; + unsigned long clock_rate; + + pclk = clk_get_rate(timerclk); + + clk_set_rate(tdiv4, pclk / 2); + clk_set_parent(tin4, tdiv4); + + clock_rate = clk_get_rate(tin4); + + s5pv310_pwm_init(4, ~0); + s5pv310_pwm_start(4, 1); + + pwm_clocksource.mult = + clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift); + + if (clocksource_register(&pwm_clocksource)) + panic("%s: can't register clocksource\n", pwm_clocksource.name); +} + +static void __init s5pv310_timer_resources(void) +{ + struct platform_device tmpdev; + + tmpdev.dev.bus = &platform_bus_type; + + timerclk = clk_get(NULL, "timers"); + if (IS_ERR(timerclk)) + panic("failed to get timers clock for system timer"); + + clk_enable(timerclk); + + tmpdev.id = 2; + tin2 = clk_get(&tmpdev.dev, "pwm-tin"); + if (IS_ERR(tin2)) + panic("failed to get pwm-tin2 clock for system timer"); + + tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv"); + if (IS_ERR(tdiv2)) + panic("failed to get pwm-tdiv2 clock for system timer"); + clk_enable(tin2); + + tmpdev.id = 4; + tin4 = clk_get(&tmpdev.dev, "pwm-tin"); + if (IS_ERR(tin4)) + panic("failed to get pwm-tin4 clock for system timer"); + + tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv"); + if (IS_ERR(tdiv4)) + panic("failed to get pwm-tdiv4 clock for system timer"); + + clk_enable(tin4); +} + +static void __init s5pv310_timer_init(void) +{ +#ifdef CONFIG_LOCAL_TIMERS + twd_base = S5P_VA_TWD; +#endif + + s5pv310_timer_resources(); + s5pv310_clockevent_init(); + s5pv310_clocksource_init(); +} + +struct sys_timer s5pv310_timer = { + .init = s5pv310_timer_init, +}; diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index 8c8845b5ae5..d18f21abef8 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h @@ -77,7 +77,7 @@ */ #ifdef CONFIG_SA1111 #define NR_IRQS (IRQ_BOARD_END + 55) -#elif defined(CONFIG_SHARPSL_LOCOMO) +#elif defined(CONFIG_SHARP_LOCOMO) #define NR_IRQS (IRQ_BOARD_START + 4) #else #define NR_IRQS (IRQ_BOARD_START) diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 4c704b4e8b3..54b479c35ee 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -7,6 +7,7 @@ config ARCH_SH7367 select CPU_V6 select HAVE_CLK select COMMON_CLKDEV + select SH_CLK_CPG select GENERIC_CLOCKEVENTS config ARCH_SH7377 @@ -14,6 +15,7 @@ config ARCH_SH7377 select CPU_V7 select HAVE_CLK select COMMON_CLKDEV + select SH_CLK_CPG select GENERIC_CLOCKEVENTS config ARCH_SH7372 @@ -21,6 +23,7 @@ config ARCH_SH7372 select CPU_V7 select HAVE_CLK select COMMON_CLKDEV + select SH_CLK_CPG select GENERIC_CLOCKEVENTS comment "SH-Mobile Board Type" @@ -39,6 +42,20 @@ config MACH_AP4EVB bool "AP4EVB board" depends on ARCH_SH7372 select ARCH_REQUIRE_GPIOLIB + select SH_LCD_MIPI_DSI + +choice + prompt "AP4EVB LCD panel selection" + default AP4EVB_QHD + depends on MACH_AP4EVB + +config AP4EVB_QHD + bool "MIPI-DSI QHD (960x540)" + +config AP4EVB_WVGA + bool "Parallel WVGA (800x480)" + +endchoice comment "SH-Mobile System Configuration" @@ -88,6 +105,15 @@ config SH_TIMER_CMT help This enables build of the CMT timer driver. +config SH_TIMER_TMU + bool "TMU timer driver" + default y + help + This enables build of the TMU timer driver. + endmenu +config SH_CLK_CPG + bool + endif diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 6d385d371c3..5e16b4c6922 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -3,12 +3,12 @@ # # Common objects -obj-y := timer.o console.o +obj-y := timer.o console.o clock.o # CPU objects obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o -obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o -obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o +obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o +obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o # Pinmux setup pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 1c2ec96ce26..23d472f9525 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -17,25 +17,45 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/clk.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mmc/host.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> +#include <linux/mmc/host.h> +#include <linux/mmc/sh_mmcif.h> +#include <linux/i2c.h> +#include <linux/i2c/tsc2007.h> #include <linux/io.h> #include <linux/smsc911x.h> +#include <linux/sh_intc.h> +#include <linux/sh_clk.h> #include <linux/gpio.h> #include <linux/input.h> #include <linux/input/sh_keysc.h> +#include <linux/usb/r8a66597.h> + +#include <sound/sh_fsi.h> + +#include <video/sh_mobile_hdmi.h> +#include <video/sh_mobile_lcdc.h> +#include <video/sh_mipi_dsi.h> + #include <mach/common.h> +#include <mach/irqs.h> #include <mach/sh7372.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/time.h> /* * Address Interface BusWidth note @@ -80,12 +100,56 @@ */ /* - * KEYSC + * LCD / IRQ / KEYSC / IrDA + * + * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen) + * LCD = 2nd LCDC (WVGA) * - * SW43 KEYSC - * ------------------------- - * ON enable - * OFF disable + * | SW43 | + * SW3 | ON | OFF | + * -------------+-----------------------+---------------+ + * ON | KEY / IrDA | LCD | + * OFF | KEY / IrDA / IRQ | IRQ | + * + * + * QHD / WVGA display + * + * You can choice display type on menuconfig. + * Then, check above dip-switch. + */ + +/* + * USB + * + * J7 : 1-2 MAX3355E VBUS + * 2-3 DC 5.0V + * + * S39: bit2: off + */ + +/* + * FSI/FSMI + * + * SW41 : ON : SH-Mobile AP4 Audio Mode + * : OFF : Bluetooth Audio Mode + */ + +/* + * MMC0/SDHI1 (CN7) + * + * J22 : select card voltage + * 1-2 pin : 1.8v + * 2-3 pin : 3.3v + * + * SW1 | SW33 + * | bit1 | bit2 | bit3 | bit4 + * ------------+------+------+------+------- + * MMC0 OFF | OFF | ON | ON | X + * SDHI1 OFF | ON | X | OFF | ON + * + * voltage lebel + * CN7 : 1.8v + * CN12: 3.3v */ /* MTD */ @@ -148,7 +212,7 @@ static struct resource smc911x_resources[] = { .end = 0x16000000 - 1, .flags = IORESOURCE_MEM, }, { - .start = 6, + .start = evt2irq(0x02c0) /* IRQ6A */, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, }, }; @@ -169,6 +233,180 @@ static struct platform_device smc911x_device = { }, }; +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .name = "SH_MMCIF", + .start = 0xE6BD0000, + .end = 0xE6BD00FF, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* MMC ERR */ + .start = evt2irq(0x1ac0), + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* MMC NOR */ + .start = evt2irq(0x1ae0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0, + .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NEEDS_POLL, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + +/* SDHI0 */ +static struct sh_mobile_sdhi_info sdhi0_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, +}; + +static struct resource sdhi0_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0xe6850000, + .end = 0xe68501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0e00) /* SDHI0 */, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi0_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi0_resources), + .resource = sdhi0_resources, + .id = 0, + .dev = { + .platform_data = &sdhi0_info, + }, +}; + +/* SDHI1 */ +static struct sh_mobile_sdhi_info sdhi1_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, + .tmio_ocr_mask = MMC_VDD_165_195, +}; + +static struct resource sdhi1_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0xe6860000, + .end = 0xe68601ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0e80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi1_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi1_resources), + .resource = sdhi1_resources, + .id = 1, + .dev = { + .platform_data = &sdhi1_info, + }, +}; + +/* USB1 */ +static void usb1_host_port_power(int port, int power) +{ + if (!power) /* only power-on supported for now */ + return; + + /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ + __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); +} + +static struct r8a66597_platdata usb1_host_data = { + .on_chip = 1, + .port_power = usb1_host_port_power, +}; + +static struct resource usb1_host_resources[] = { + [0] = { + .name = "USBHS", + .start = 0xE68B0000, + .end = 0xE68B00E6 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb1_host_device = { + .name = "r8a66597_hcd", + .id = 1, + .dev = { + .dma_mask = NULL, /* not use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &usb1_host_data, + }, + .num_resources = ARRAY_SIZE(usb1_host_resources), + .resource = usb1_host_resources, +}; + +static struct sh_mobile_lcdc_info lcdc_info = { + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe943fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x580), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + .coherent_dma_mask = ~0, + }, +}; + +/* + * QHD display + */ +#ifdef CONFIG_AP4EVB_QHD + /* KEYSC (Needs SW43 set to ON) */ static struct sh_keysc_info keysc_info = { .mode = SH_KEYSC_MODE_1, @@ -191,7 +429,7 @@ static struct resource keysc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 79, + .start = evt2irq(0x0be0), /* KEYSC_KEY */ .flags = IORESOURCE_IRQ, }, }; @@ -206,32 +444,362 @@ static struct platform_device keysc_device = { }, }; -/* SDHI0 */ -static struct resource sdhi0_resources[] = { +/* MIPI-DSI */ +static struct resource mipidsi0_resources[] = { [0] = { - .name = "SDHI0", - .start = 0xe6850000, - .end = 0xe68501ff, + .start = 0xffc60000, + .end = 0xffc68fff, .flags = IORESOURCE_MEM, }, +}; + +static struct sh_mipi_dsi_info mipidsi0_info = { + .data_format = MIPI_RGB888, + .lcd_chan = &lcdc_info.ch[0], +}; + +static struct platform_device mipidsi0_device = { + .name = "sh-mipi-dsi", + .num_resources = ARRAY_SIZE(mipidsi0_resources), + .resource = mipidsi0_resources, + .id = 0, + .dev = { + .platform_data = &mipidsi0_info, + }, +}; + +/* This function will disappear when we switch to (runtime) PM */ +static int __init ap4evb_init_display_clk(void) +{ + struct clk *lcdc_clk; + struct clk *dsitx_clk; + int ret; + + lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0"); + if (IS_ERR(lcdc_clk)) + return PTR_ERR(lcdc_clk); + + dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0"); + if (IS_ERR(dsitx_clk)) { + ret = PTR_ERR(dsitx_clk); + goto eclkdsitxget; + } + + ret = clk_enable(lcdc_clk); + if (ret < 0) + goto eclklcdcon; + + ret = clk_enable(dsitx_clk); + if (ret < 0) + goto eclkdsitxon; + + return 0; + +eclkdsitxon: + clk_disable(lcdc_clk); +eclklcdcon: + clk_put(dsitx_clk); +eclkdsitxget: + clk_put(lcdc_clk); + + return ret; +} +device_initcall(ap4evb_init_display_clk); + +static struct platform_device *qhd_devices[] __initdata = { + &mipidsi0_device, + &keysc_device, +}; +#endif /* CONFIG_AP4EVB_QHD */ + +/* FSI */ +#define IRQ_FSI evt2irq(0x1840) +#define FSIACKCR 0xE6150018 +static void fsiackcr_init(struct clk *clk) +{ + u32 status = __raw_readl(clk->enable_reg); + + /* use external clock */ + status &= ~0x000000ff; + status |= 0x00000080; + __raw_writel(status, clk->enable_reg); +} + +static struct clk_ops fsiackcr_clk_ops = { + .init = fsiackcr_init, +}; + +static struct clk fsiackcr_clk = { + .ops = &fsiackcr_clk_ops, + .enable_reg = (void __iomem *)FSIACKCR, + .rate = 0, /* unknown */ +}; + +static struct sh_fsi_platform_info fsi_info = { + .porta_flags = SH_FSI_BRS_INV | + SH_FSI_OUT_SLAVE_MODE | + SH_FSI_IN_SLAVE_MODE | + SH_FSI_OFMT(PCM) | + SH_FSI_IFMT(PCM), +}; + +static struct resource fsi_resources[] = { + [0] = { + .name = "FSI", + .start = 0xFE3C0000, + .end = 0xFE3C0400 - 1, + .flags = IORESOURCE_MEM, + }, [1] = { - .start = 96, + .start = IRQ_FSI, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device sdhi0_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi0_resources), - .resource = sdhi0_resources, - .id = 0, +static struct platform_device fsi_device = { + .name = "sh_fsi2", + .id = 0, + .num_resources = ARRAY_SIZE(fsi_resources), + .resource = fsi_resources, + .dev = { + .platform_data = &fsi_info, + }, +}; + +static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { + .clock_source = LCDC_CLK_EXTERNAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = RGB24, + .clock_divider = 1, + .flags = LCDC_FLAGS_DWPOL, + .lcd_cfg = { + .name = "HDMI", + /* So far only 720p is supported */ + .xres = 1280, + .yres = 720, + /* + * If left and right margins are not multiples of 8, + * LDHAJR will be adjusted accordingly by the LCDC + * driver. Until we start using EDID, these values + * might have to be adjusted for different monitors. + */ + .left_margin = 200, + .right_margin = 88, + .hsync_len = 48, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .pixclock = 13468, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, + }, + } +}; + +static struct resource lcdc1_resources[] = { + [0] = { + .name = "LCDC1", + .start = 0xfe944000, + .end = 0xfe947fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0x17a0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lcdc1_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc1_resources), + .resource = lcdc1_resources, + .id = 1, + .dev = { + .platform_data = &sh_mobile_lcdc1_info, + .coherent_dma_mask = ~0, + }, +}; + +static struct sh_mobile_hdmi_info hdmi_info = { + .lcd_chan = &sh_mobile_lcdc1_info.ch[0], + .lcd_dev = &lcdc1_device.dev, +}; + +static struct resource hdmi_resources[] = { + [0] = { + .name = "HDMI", + .start = 0xe6be0000, + .end = 0xe6be00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ + .start = evt2irq(0x17e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device hdmi_device = { + .name = "sh-mobile-hdmi", + .num_resources = ARRAY_SIZE(hdmi_resources), + .resource = hdmi_resources, + .id = -1, + .dev = { + .platform_data = &hdmi_info, + }, }; static struct platform_device *ap4evb_devices[] __initdata = { &nor_flash_device, &smc911x_device, - &keysc_device, &sdhi0_device, + &sdhi1_device, + &usb1_host_device, + &fsi_device, + &sh_mmcif_device, + &lcdc1_device, + &lcdc_device, + &hdmi_device, +}; + +static int __init hdmi_init_pm_clock(void) +{ + struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); + int ret; + long rate; + + if (IS_ERR(hdmi_ick)) { + ret = PTR_ERR(hdmi_ick); + pr_err("Cannot get HDMI ICK: %d\n", ret); + goto out; + } + + ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk); + if (ret < 0) { + pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount); + goto out; + } + + pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk)); + + rate = clk_round_rate(&pllc2_clk, 594000000); + if (rate < 0) { + pr_err("Cannot get suitable rate: %ld\n", rate); + ret = rate; + goto out; + } + + ret = clk_set_rate(&pllc2_clk, rate); + if (ret < 0) { + pr_err("Cannot set rate %ld: %d\n", rate, ret); + goto out; + } + + pr_debug("PLLC2 set frequency %lu\n", rate); + + ret = clk_set_parent(hdmi_ick, &pllc2_clk); + if (ret < 0) { + pr_err("Cannot set HDMI parent: %d\n", ret); + goto out; + } + +out: + if (!IS_ERR(hdmi_ick)) + clk_put(hdmi_ick); + return ret; +} + +device_initcall(hdmi_init_pm_clock); + +/* + * FIXME !! + * + * gpio_no_direction + * gpio_pull_up + * are quick_hack. + * + * current gpio frame work doesn't have + * the method to control only pull up/down/free. + * this function should be replaced by correct gpio function + */ +static void __init gpio_no_direction(u32 addr) +{ + __raw_writeb(0x00, addr); +} + +static void __init gpio_pull_up(u32 addr) +{ + u8 data = __raw_readb(addr); + + data &= 0x0F; + data |= 0xC0; + __raw_writeb(data, addr); +} + +/* TouchScreen */ +#define IRQ28 evt2irq(0x3380) /* IRQ28A */ +#define IRQ7 evt2irq(0x02e0) /* IRQ7A */ +static int ts_get_pendown_state(void) +{ + int val1, val2; + + gpio_free(GPIO_FN_IRQ28_123); + gpio_free(GPIO_FN_IRQ7_40); + + gpio_request(GPIO_PORT123, NULL); + gpio_request(GPIO_PORT40, NULL); + + gpio_direction_input(GPIO_PORT123); + gpio_direction_input(GPIO_PORT40); + + val1 = gpio_get_value(GPIO_PORT123); + val2 = gpio_get_value(GPIO_PORT40); + + gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */ + gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */ + + return val1 ^ val2; +} + +#define PORT40CR 0xE6051028 +#define PORT123CR 0xE605007B +static int ts_init(void) +{ + gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */ + gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */ + + gpio_pull_up(PORT40CR); + gpio_pull_up(PORT123CR); + + return 0; +} + +static struct tsc2007_platform_data tsc2007_info = { + .model = 2007, + .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, +}; + +static struct i2c_board_info tsc_device = { + I2C_BOARD_INFO("tsc2007", 0x48), + .type = "tsc2007", + .platform_data = &tsc2007_info, + /*.irq is selected on ap4evb_init */ +}; + +/* I2C */ +static struct i2c_board_info i2c0_devices[] = { + { + I2C_BOARD_INFO("ak4643", 0x13), + }, +}; + +static struct i2c_board_info i2c1_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, }; static struct map_desc ap4evb_io_desc[] __initdata = { @@ -250,14 +818,18 @@ static void __init ap4evb_map_io(void) { iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); - /* setup early devices, clocks and console here as well */ + /* setup early devices and console here as well */ sh7372_add_early_devices(); - sh7367_clock_init(); /* use g3 clocks for now */ shmobile_setup_console(); } +#define GPIO_PORT9CR 0xE6051009 +#define GPIO_PORT10CR 0xE605100A static void __init ap4evb_init(void) { + u32 srcr4; + struct clk *clk; + sh7372_pinmux_init(); /* enable SCIFA0 */ @@ -296,6 +868,93 @@ static void __init ap4evb_init(void) gpio_export(GPIO_PORT34, 0); gpio_export(GPIO_PORT35, 0); + /* SDHI0 */ + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + + /* SDHI1 */ + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_FN_MMCCLK0, NULL); + + /* USB enable */ + gpio_request(GPIO_FN_VBUS0_1, NULL); + gpio_request(GPIO_FN_IDIN_1_18, NULL); + gpio_request(GPIO_FN_PWEN_1_115, NULL); + gpio_request(GPIO_FN_OVCN_1_114, NULL); + gpio_request(GPIO_FN_EXTLP_1, NULL); + gpio_request(GPIO_FN_OVCN2_1, NULL); + + /* setup USB phy */ + __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */ + + /* enable FSI2 */ + gpio_request(GPIO_FN_FSIAIBT, NULL); + gpio_request(GPIO_FN_FSIAILR, NULL); + gpio_request(GPIO_FN_FSIAISLD, NULL); + gpio_request(GPIO_FN_FSIAOSLD, NULL); + gpio_request(GPIO_PORT161, NULL); + gpio_direction_output(GPIO_PORT161, 0); /* slave */ + + gpio_request(GPIO_PORT9, NULL); + gpio_request(GPIO_PORT10, NULL); + gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */ + gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */ + + /* set SPU2 clock to 119.6 MHz */ + clk = clk_get(NULL, "spu_clk"); + if (!IS_ERR(clk)) { + clk_set_rate(clk, clk_round_rate(clk, 119600000)); + clk_put(clk); + } + + /* change parent of FSI A */ + clk = clk_get(NULL, "fsia_clk"); + if (!IS_ERR(clk)) { + clk_register(&fsiackcr_clk); + clk_set_parent(clk, &fsiackcr_clk); + clk_put(clk); + } + + /* + * set irq priority, to avoid sound chopping + * when NFS rootfs is used + * FSI(3) > SMSC911X(2) + */ + intc_set_priority(IRQ_FSI, 3); + + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); + + i2c_register_board_info(1, i2c1_devices, + ARRAY_SIZE(i2c1_devices)); + +#ifdef CONFIG_AP4EVB_QHD + /* + * QHD + */ + /* enable KEYSC */ gpio_request(GPIO_FN_KEYOUT0, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); @@ -308,26 +967,122 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_KEYIN3_133, NULL); gpio_request(GPIO_FN_KEYIN4, NULL); - /* SDHI0 */ - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); + /* enable TouchScreen */ + set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); + + tsc_device.irq = IRQ28; + i2c_register_board_info(1, &tsc_device, 1); + + /* LCDC0 */ + lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; + lcdc_info.ch[0].interface_type = RGB24; + lcdc_info.ch[0].clock_divider = 1; + lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; + lcdc_info.ch[0].lcd_cfg.name = "R63302(QHD)"; + lcdc_info.ch[0].lcd_cfg.xres = 544; + lcdc_info.ch[0].lcd_cfg.yres = 961; + lcdc_info.ch[0].lcd_cfg.left_margin = 72; + lcdc_info.ch[0].lcd_cfg.right_margin = 600; + lcdc_info.ch[0].lcd_cfg.hsync_len = 16; + lcdc_info.ch[0].lcd_cfg.upper_margin = 8; + lcdc_info.ch[0].lcd_cfg.lower_margin = 8; + lcdc_info.ch[0].lcd_cfg.vsync_len = 2; + lcdc_info.ch[0].lcd_cfg.sync = FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_HOR_HIGH_ACT; + lcdc_info.ch[0].lcd_size_cfg.width = 44; + lcdc_info.ch[0].lcd_size_cfg.height = 79; + + platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices)); + +#else + /* + * WVGA + */ + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + + gpio_request(GPIO_PORT189, NULL); /* backlight */ + gpio_direction_output(GPIO_PORT189, 1); + + gpio_request(GPIO_PORT151, NULL); /* LCDDON */ + gpio_direction_output(GPIO_PORT151, 1); + + lcdc_info.clock_source = LCDC_CLK_BUS; + lcdc_info.ch[0].interface_type = RGB18; + lcdc_info.ch[0].clock_divider = 2; + lcdc_info.ch[0].flags = 0; + lcdc_info.ch[0].lcd_cfg.name = "WVGA Panel"; + lcdc_info.ch[0].lcd_cfg.xres = 800; + lcdc_info.ch[0].lcd_cfg.yres = 480; + lcdc_info.ch[0].lcd_cfg.left_margin = 220; + lcdc_info.ch[0].lcd_cfg.right_margin = 110; + lcdc_info.ch[0].lcd_cfg.hsync_len = 70; + lcdc_info.ch[0].lcd_cfg.upper_margin = 20; + lcdc_info.ch[0].lcd_cfg.lower_margin = 5; + lcdc_info.ch[0].lcd_cfg.vsync_len = 5; + lcdc_info.ch[0].lcd_cfg.sync = 0; + lcdc_info.ch[0].lcd_size_cfg.width = 152; + lcdc_info.ch[0].lcd_size_cfg.height = 91; + + /* enable TouchScreen */ + set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + + tsc_device.irq = IRQ7; + i2c_register_board_info(0, &tsc_device, 1); +#endif /* CONFIG_AP4EVB_QHD */ sh7372_add_standard_devices(); + /* HDMI */ + gpio_request(GPIO_FN_HDMI_HPD, NULL); + gpio_request(GPIO_FN_HDMI_CEC, NULL); + + /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ +#define SRCR4 0xe61580bc + srcr4 = __raw_readl(SRCR4); + __raw_writel(srcr4 | (1 << 13), SRCR4); + udelay(50); + __raw_writel(srcr4 & ~(1 << 13), SRCR4); + platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); } +static void __init ap4evb_timer_init(void) +{ + sh7372_clock_init(); + shmobile_timer.init(); + + /* External clock source */ + clk_set_rate(&dv_clki_clk, 27000000); +} + +static struct sys_timer ap4evb_timer = { + .init = ap4evb_timer_init, +}; + MACHINE_START(AP4EVB, "ap4evb") .phys_io = 0xe6000000, .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, .map_io = ap4evb_map_io, .init_irq = sh7372_init_irq, .init_machine = ap4evb_init, - .timer = &shmobile_timer, + .timer = &ap4evb_timer, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index 9247503296c..a5525901e91 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c @@ -37,6 +37,15 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/time.h> + +/* + * IrDA + * + * S67: 5bit : ON power + * : 6bit : ON remote control + * OFF IrDA + */ static struct mtd_partition nor_flash_partitions[] = { { @@ -91,7 +100,7 @@ static struct platform_device nor_flash_device = { }; /* USBHS */ -void usb_host_port_power(int port, int power) +static void usb_host_port_power(int port, int power) { if (!power) /* only power-on supported for now */ return; @@ -113,7 +122,7 @@ static struct resource usb_host_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, + .start = evt2irq(0xa20), /* USBHS_USHI0 */ .flags = IORESOURCE_IRQ, }, }; @@ -153,7 +162,7 @@ static struct resource keysc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 79, + .start = evt2irq(0xbe0), /* KEYSC_KEY */ .flags = IORESOURCE_IRQ, }, }; @@ -209,11 +218,31 @@ static struct platform_device nand_flash_device = { }, }; +static struct resource irda_resources[] = { + [0] = { + .start = 0xE6D00000, + .end = 0xE6D01FD4 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), /* IRDA */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device irda_device = { + .name = "sh_irda", + .id = -1, + .resource = irda_resources, + .num_resources = ARRAY_SIZE(irda_resources), +}; + static struct platform_device *g3evm_devices[] __initdata = { &nor_flash_device, &usb_host_device, &keysc_device, &nand_flash_device, + &irda_device, }; static struct map_desc g3evm_io_desc[] __initdata = { @@ -232,9 +261,8 @@ static void __init g3evm_map_io(void) { iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); - /* setup early devices, clocks and console here as well */ + /* setup early devices and console here as well */ sh7367_add_early_devices(); - sh7367_clock_init(); shmobile_setup_console(); } @@ -271,9 +299,6 @@ static void __init g3evm_init(void) gpio_request(GPIO_FN_EXTLP, NULL); gpio_request(GPIO_FN_IDIN, NULL); - /* enable clock in SYMSTPCR2 */ - __raw_writel(__raw_readl(0xe6158048) & ~(1 << 22), 0xe6158048); - /* setup USB phy */ __raw_writew(0x0300, 0xe605810a); /* USBCR1 */ __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ @@ -318,16 +343,32 @@ static void __init g3evm_init(void) /* FOE, FCDE, FSC on dedicated pins */ __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048); + /* IrDA */ + gpio_request(GPIO_FN_IRDA_OUT, NULL); + gpio_request(GPIO_FN_IRDA_IN, NULL); + gpio_request(GPIO_FN_IRDA_FIRSEL, NULL); + set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW); + sh7367_add_standard_devices(); platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices)); } +static void __init g3evm_timer_init(void) +{ + sh7367_clock_init(); + shmobile_timer.init(); +} + +static struct sys_timer g3evm_timer = { + .init = g3evm_timer_init, +}; + MACHINE_START(G3EVM, "g3evm") .phys_io = 0xe6000000, .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, .map_io = g3evm_map_io, .init_irq = sh7367_init_irq, .init_machine = g3evm_init, - .timer = &shmobile_timer, + .timer = &g3evm_timer, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 10673a90be5..2c3ff6f7f34 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -30,12 +30,39 @@ #include <linux/io.h> #include <linux/input.h> #include <linux/input/sh_keysc.h> +#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/gpio.h> #include <mach/sh7377.h> #include <mach/common.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/time.h> + +/* + * SDHI + * + * SDHI0 : card detection is possible + * SDHI1 : card detection is impossible + * + * [G4-MAIN-BOARD] + * JP74 : short # DBG_2V8A for SDHI0 + * JP75 : NC # DBG_3V3A for SDHI0 + * JP76 : NC # DBG_3V3A_SD for SDHI0 + * JP77 : NC # 3V3A_SDIO for SDHI1 + * JP78 : short # DBG_2V8A for SDHI1 + * JP79 : NC # DBG_3V3A for SDHI1 + * JP80 : NC # DBG_3V3A_SD for SDHI1 + * + * [G4-CORE-BOARD] + * S32 : all off # to dissever from G3-CORE_DBG board + * S33 : all off # to dissever from G3-CORE_DBG board + * + * [G3-CORE_DBG-BOARD] + * S1 : all off # to dissever from G3-CORE_DBG board + * S3 : all off # to dissever from G3-CORE_DBG board + * S4 : all off # to dissever from G3-CORE_DBG board + */ static struct mtd_partition nor_flash_partitions[] = { { @@ -90,7 +117,7 @@ static struct platform_device nor_flash_device = { }; /* USBHS */ -void usb_host_port_power(int port, int power) +static void usb_host_port_power(int port, int power) { if (!power) /* only power-on supported for now */ return; @@ -112,8 +139,7 @@ static struct resource usb_host_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 65, - .end = 65, + .start = evt2irq(0x0a20), /* USBHS_USHI0 */ .flags = IORESOURCE_IRQ, }, }; @@ -154,7 +180,7 @@ static struct resource keysc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 79, + .start = evt2irq(0x0be0), /* KEYSC_KEY */ .flags = IORESOURCE_IRQ, }, }; @@ -169,10 +195,53 @@ static struct platform_device keysc_device = { }, }; +/* SDHI */ +static struct resource sdhi0_resources[] = { + [0] = { + .name = "SDHI0", + .start = 0xe6d50000, + .end = 0xe6d501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0e00), /* SDHI0 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi0_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi0_resources), + .resource = sdhi0_resources, + .id = 0, +}; + +static struct resource sdhi1_resources[] = { + [0] = { + .name = "SDHI1", + .start = 0xe6d60000, + .end = 0xe6d601ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x0e80), /* SDHI1 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi1_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi1_resources), + .resource = sdhi1_resources, + .id = 1, +}; + static struct platform_device *g4evm_devices[] __initdata = { &nor_flash_device, &usb_host_device, &keysc_device, + &sdhi0_device, + &sdhi1_device, }; static struct map_desc g4evm_io_desc[] __initdata = { @@ -191,12 +260,41 @@ static void __init g4evm_map_io(void) { iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); - /* setup early devices, clocks and console here as well */ + /* setup early devices and console here as well */ sh7377_add_early_devices(); - sh7367_clock_init(); /* use g3 clocks for now */ shmobile_setup_console(); } +#define GPIO_SDHID0_D0 0xe60520fc +#define GPIO_SDHID0_D1 0xe60520fd +#define GPIO_SDHID0_D2 0xe60520fe +#define GPIO_SDHID0_D3 0xe60520ff +#define GPIO_SDHICMD0 0xe6052100 + +#define GPIO_SDHID1_D0 0xe6052103 +#define GPIO_SDHID1_D1 0xe6052104 +#define GPIO_SDHID1_D2 0xe6052105 +#define GPIO_SDHID1_D3 0xe6052106 +#define GPIO_SDHICMD1 0xe6052107 + +/* + * FIXME !! + * + * gpio_pull_up is quick_hack. + * + * current gpio frame work doesn't have + * the method to control only pull up/down/free. + * this function should be replaced by correct gpio function + */ +static void __init gpio_pull_up(u32 addr) +{ + u8 data = __raw_readb(addr); + + data &= 0x0F; + data |= 0xC0; + __raw_writeb(data, addr); +} + static void __init g4evm_init(void) { sh7377_pinmux_init(); @@ -229,9 +327,6 @@ static void __init g4evm_init(void) gpio_request(GPIO_FN_EXTLP, NULL); gpio_request(GPIO_FN_IDIN, NULL); - /* enable clock in SMSTPCR3 */ - __raw_writel(__raw_readl(0xe615013c) & ~(1 << 22), 0xe615013c); - /* setup USB phy */ __raw_writew(0x0200, 0xe605810a); /* USBCR1 */ __raw_writew(0x00e0, 0xe60581c0); /* CPFCH */ @@ -253,16 +348,54 @@ static void __init g4evm_init(void) gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL); gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL); + /* SDHI0 */ + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_pull_up(GPIO_SDHID0_D0); + gpio_pull_up(GPIO_SDHID0_D1); + gpio_pull_up(GPIO_SDHID0_D2); + gpio_pull_up(GPIO_SDHID0_D3); + gpio_pull_up(GPIO_SDHICMD0); + + /* SDHI1 */ + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_pull_up(GPIO_SDHID1_D0); + gpio_pull_up(GPIO_SDHID1_D1); + gpio_pull_up(GPIO_SDHID1_D2); + gpio_pull_up(GPIO_SDHID1_D3); + gpio_pull_up(GPIO_SDHICMD1); + sh7377_add_standard_devices(); platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices)); } +static void __init g4evm_timer_init(void) +{ + sh7377_clock_init(); + shmobile_timer.init(); +} + +static struct sys_timer g4evm_timer = { + .init = g4evm_timer_init, +}; + MACHINE_START(G4EVM, "g4evm") .phys_io = 0xe6000000, .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc, .map_io = g4evm_map_io, .init_irq = sh7377_init_irq, .init_machine = g4evm_init, - .timer = &shmobile_timer, + .timer = &g4evm_timer, MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index bb940c6e4e6..b6454c9f2ab 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -1,5 +1,5 @@ /* - * Preliminary clock framework support for sh7367 + * SH7367 clock framework support * * Copyright (C) 2010 Magnus Damm * @@ -17,87 +17,342 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <linux/init.h> -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk.h> +#include <linux/io.h> +#include <linux/sh_clk.h> +#include <mach/common.h> +#include <asm/clkdev.h> + +/* SH7367 registers */ +#define RTFRQCR 0xe6150000 +#define SYFRQCR 0xe6150004 +#define CMFRQCR 0xe61500E0 +#define VCLKCR1 0xe6150008 +#define VCLKCR2 0xe615000C +#define VCLKCR3 0xe615001C +#define SCLKACR 0xe6150010 +#define SCLKBCR 0xe6150014 +#define SUBUSBCKCR 0xe6158080 +#define SPUCKCR 0xe6150084 +#define MSUCKCR 0xe6150088 +#define MVI3CKCR 0xe6150090 +#define VOUCKCR 0xe6150094 +#define MFCK1CR 0xe6150098 +#define MFCK2CR 0xe615009C +#define PLLC1CR 0xe6150028 +#define PLLC2CR 0xe615002C +#define RTMSTPCR0 0xe6158030 +#define RTMSTPCR2 0xe6158038 +#define SYMSTPCR0 0xe6158040 +#define SYMSTPCR2 0xe6158048 +#define CMMSTPCR0 0xe615804c -struct clk { - const char *name; - unsigned long rate; +/* Fixed 32 KHz root clock from EXTALR pin */ +static struct clk r_clk = { + .rate = 32768, }; -#include <asm/clkdev.h> +/* + * 26MHz default rate for the EXTALB1 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh7367_extalb1_clk = { + .rate = 26666666, +}; -int __clk_get(struct clk *clk) -{ - return 1; -} -EXPORT_SYMBOL(__clk_get); +/* + * 48MHz default rate for the EXTAL2 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh7367_extal2_clk = { + .rate = 48000000, +}; -void __clk_put(struct clk *clk) +/* A fixed divide-by-2 block */ +static unsigned long div2_recalc(struct clk *clk) { + return clk->parent->rate / 2; } -EXPORT_SYMBOL(__clk_put); +static struct clk_ops div2_clk_ops = { + .recalc = div2_recalc, +}; + +/* Divide extalb1 by two */ +static struct clk extalb1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7367_extalb1_clk, +}; + +/* Divide extal2 by two */ +static struct clk extal2_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7367_extal2_clk, +}; -int clk_enable(struct clk *clk) +/* PLLC1 */ +static unsigned long pllc1_recalc(struct clk *clk) { - return 0; + unsigned long mult = 1; + + if (__raw_readl(PLLC1CR) & (1 << 14)) + mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2; + + return clk->parent->rate * mult; } -EXPORT_SYMBOL(clk_enable); -void clk_disable(struct clk *clk) +static struct clk_ops pllc1_clk_ops = { + .recalc = pllc1_recalc, +}; + +static struct clk pllc1_clk = { + .ops = &pllc1_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extalb1_div2_clk, +}; + +/* Divide PLLC1 by two */ +static struct clk pllc1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &pllc1_clk, +}; + +/* PLLC2 */ +static unsigned long pllc2_recalc(struct clk *clk) { + unsigned long mult = 1; + + if (__raw_readl(PLLC2CR) & (1 << 31)) + mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; + + return clk->parent->rate * mult; } -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) +static struct clk_ops pllc2_clk_ops = { + .recalc = pllc2_recalc, +}; + +static struct clk pllc2_clk = { + .ops = &pllc2_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extalb1_div2_clk, +}; + +static struct clk *main_clks[] = { + &r_clk, + &sh7367_extalb1_clk, + &sh7367_extal2_clk, + &extalb1_div2_clk, + &extal2_div2_clk, + &pllc1_clk, + &pllc1_div2_clk, + &pllc2_clk, +}; + +static void div4_kick(struct clk *clk) { - return clk ? clk->rate : 0; + unsigned long value; + + /* set KICK bit in SYFRQCR to update hardware setting */ + value = __raw_readl(SYFRQCR); + value |= (1 << 31); + __raw_writel(value, SYFRQCR); } -EXPORT_SYMBOL(clk_get_rate); -/* a static peripheral clock for now - enough to get sh-sci working */ -static struct clk peripheral_clk = { - .name = "peripheral_clk", - .rate = 48000000, +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48, 0, 72, 0, 0 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), }; -/* a static rclk for now - enough to get sh_cmt working */ -static struct clk r_clk = { - .name = "r_clk", - .rate = 32768, +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B, + DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP, + DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags) + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0), + [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0), + [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0), + [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0), + [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0), + [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0), + [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0), + [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0), + [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0), }; -/* a static usb0 for now - enough to get r8a66597 working */ -static struct clk usb0_clk = { - .name = "usb0", +enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU, + DIV6_MVI3, DIV6_MF1, DIV6_MF2, + DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU, + DIV6_NR }; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0), + [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0), + [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0), + [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0), + [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), + [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0), + [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0), + [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0), + [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0), + [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0), + [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), + [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0), }; -/* a static keysc0 clk for now - enough to get sh_keysc working */ -static struct clk keysc0_clk = { - .name = "keysc0", +enum { RTMSTP001, + RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226, + RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201, + SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004, + SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000, + SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222, + SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211, + CMMSTP003, + MSTP_NR }; + +#define MSTP(_parent, _reg, _bit, _flags) \ + SH_CLK_MSTP32(_parent, _reg, _bit, _flags) + +static struct clk mstp_clks[MSTP_NR] = { + [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */ + [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */ + [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */ + [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */ + [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */ + [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */ + [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */ + [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */ + [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */ + [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */ + [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */ + [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */ + [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */ + [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */ + [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */ + [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */ + [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */ + [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */ + [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */ + [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */ + [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */ + [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */ + [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */ + [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */ + [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */ + [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */ + [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */ + [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */ }; +#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } +#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } + static struct clk_lookup lookups[] = { - { - .clk = &peripheral_clk, - }, { - .clk = &r_clk, - }, { - .clk = &usb0_clk, - }, { - .clk = &keysc0_clk, - } + /* main clocks */ + CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk), + CLKDEV_CON_ID("extal2", &sh7367_extal2_clk), + CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk), + CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), + CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), + CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), + CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]), + CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), + CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), + CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]), + CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]), + CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), + CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]), + CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), + CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]), + CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), + CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]), + CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]), + CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]), + CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), + CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]), + CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]), + CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]), + CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), + CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */ + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */ + CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */ + CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */ + CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */ + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */ + CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */ + CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */ + CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */ + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */ + CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */ + CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */ + CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */ + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */ }; void __init sh7367_clock_init(void) { - int i; + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - for (i = 0; i < ARRAY_SIZE(lookups); i++) { - lookups[i].con_id = lookups[i].clk->name; - clkdev_add(&lookups[i]); - } + if (!ret) + clk_init(); + else + panic("failed to setup sh7367 clocks\n"); } diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c new file mode 100644 index 00000000000..fb4e9b1d788 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -0,0 +1,560 @@ +/* + * SH7372 clock framework support + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/sh_clk.h> +#include <mach/common.h> +#include <asm/clkdev.h> + +/* SH7372 registers */ +#define FRQCRA 0xe6150000 +#define FRQCRB 0xe6150004 +#define FRQCRC 0xe61500e0 +#define FRQCRD 0xe61500e4 +#define VCLKCR1 0xe6150008 +#define VCLKCR2 0xe615000c +#define VCLKCR3 0xe615001c +#define FMSICKCR 0xe6150010 +#define FMSOCKCR 0xe6150014 +#define FSIACKCR 0xe6150018 +#define FSIBCKCR 0xe6150090 +#define SUBCKCR 0xe6150080 +#define SPUCKCR 0xe6150084 +#define VOUCKCR 0xe6150088 +#define HDMICKCR 0xe6150094 +#define DSITCKCR 0xe6150060 +#define DSI0PCKCR 0xe6150064 +#define DSI1PCKCR 0xe6150098 +#define PLLC01CR 0xe6150028 +#define PLLC2CR 0xe615002c +#define SMSTPCR0 0xe6150130 +#define SMSTPCR1 0xe6150134 +#define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c +#define SMSTPCR4 0xe6150140 + +/* Platforms must set frequency on their DV_CLKI pin */ +struct clk dv_clki_clk = { +}; + +/* Fixed 32 KHz root clock from EXTALR pin */ +static struct clk r_clk = { + .rate = 32768, +}; + +/* + * 26MHz default rate for the EXTAL1 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh7372_extal1_clk = { + .rate = 26000000, +}; + +/* + * 48MHz default rate for the EXTAL2 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh7372_extal2_clk = { + .rate = 48000000, +}; + +/* A fixed divide-by-2 block */ +static unsigned long div2_recalc(struct clk *clk) +{ + return clk->parent->rate / 2; +} + +static struct clk_ops div2_clk_ops = { + .recalc = div2_recalc, +}; + +/* Divide dv_clki by two */ +struct clk dv_clki_div2_clk = { + .ops = &div2_clk_ops, + .parent = &dv_clki_clk, +}; + +/* Divide extal1 by two */ +static struct clk extal1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7372_extal1_clk, +}; + +/* Divide extal2 by two */ +static struct clk extal2_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7372_extal2_clk, +}; + +/* Divide extal2 by four */ +static struct clk extal2_div4_clk = { + .ops = &div2_clk_ops, + .parent = &extal2_div2_clk, +}; + +/* PLLC0 and PLLC1 */ +static unsigned long pllc01_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (__raw_readl(PLLC01CR) & (1 << 14)) + mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2; + + return clk->parent->rate * mult; +} + +static struct clk_ops pllc01_clk_ops = { + .recalc = pllc01_recalc, +}; + +static struct clk pllc0_clk = { + .ops = &pllc01_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extal1_div2_clk, + .enable_reg = (void __iomem *)FRQCRC, +}; + +static struct clk pllc1_clk = { + .ops = &pllc01_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extal1_div2_clk, + .enable_reg = (void __iomem *)FRQCRA, +}; + +/* Divide PLLC1 by two */ +static struct clk pllc1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &pllc1_clk, +}; + +/* PLLC2 */ + +/* Indices are important - they are the actual src selecting values */ +static struct clk *pllc2_parent[] = { + [0] = &extal1_div2_clk, + [1] = &extal2_div2_clk, + [2] = &dv_clki_div2_clk, +}; + +/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ +static struct cpufreq_frequency_table pllc2_freq_table[29]; + +static void pllc2_table_rebuild(struct clk *clk) +{ + int i; + + /* Initialise PLLC2 frequency table */ + for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) { + pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2; + pllc2_freq_table[i].index = i; + } + + /* This is a special entry - switching PLL off makes it a repeater */ + pllc2_freq_table[i].frequency = clk->parent->rate; + pllc2_freq_table[i].index = i; + + pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END; + pllc2_freq_table[i].index = i; +} + +static unsigned long pllc2_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + pllc2_table_rebuild(clk); + + /* + * If the PLL is off, mult == 1, clk->rate will be updated in + * pllc2_enable(). + */ + if (__raw_readl(PLLC2CR) & (1 << 31)) + mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; + + return clk->parent->rate * mult; +} + +static long pllc2_round_rate(struct clk *clk, unsigned long rate) +{ + return clk_rate_table_round(clk, clk->freq_table, rate); +} + +static int pllc2_enable(struct clk *clk) +{ + int i; + + __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR); + + for (i = 0; i < 100; i++) + if (__raw_readl(PLLC2CR) & 0x80000000) { + clk->rate = pllc2_recalc(clk); + return 0; + } + + pr_err("%s(): timeout!\n", __func__); + + return -ETIMEDOUT; +} + +static void pllc2_disable(struct clk *clk) +{ + __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR); +} + +static int pllc2_set_rate(struct clk *clk, + unsigned long rate, int algo_id) +{ + unsigned long value; + int idx; + + idx = clk_rate_table_find(clk, clk->freq_table, rate); + if (idx < 0) + return idx; + + if (rate == clk->parent->rate) { + pllc2_disable(clk); + return 0; + } + + value = __raw_readl(PLLC2CR) & ~(0x3f << 24); + + if (value & 0x80000000) + pllc2_disable(clk); + + __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR); + + if (value & 0x80000000) + return pllc2_enable(clk); + + return 0; +} + +static int pllc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 value; + int ret, i; + + if (!clk->parent_table || !clk->parent_num) + return -EINVAL; + + /* Search the parent */ + for (i = 0; i < clk->parent_num; i++) + if (clk->parent_table[i] == parent) + break; + + if (i == clk->parent_num) + return -ENODEV; + + ret = clk_reparent(clk, parent); + if (ret < 0) + return ret; + + value = __raw_readl(PLLC2CR) & ~(3 << 6); + + __raw_writel(value | (i << 6), PLLC2CR); + + /* Rebiuld the frequency table */ + pllc2_table_rebuild(clk); + + return 0; +} + +static struct clk_ops pllc2_clk_ops = { + .recalc = pllc2_recalc, + .round_rate = pllc2_round_rate, + .set_rate = pllc2_set_rate, + .enable = pllc2_enable, + .disable = pllc2_disable, + .set_parent = pllc2_set_parent, +}; + +struct clk pllc2_clk = { + .ops = &pllc2_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extal1_div2_clk, + .freq_table = pllc2_freq_table, + .parent_table = pllc2_parent, + .parent_num = ARRAY_SIZE(pllc2_parent), +}; + +static struct clk *main_clks[] = { + &dv_clki_clk, + &r_clk, + &sh7372_extal1_clk, + &sh7372_extal2_clk, + &dv_clki_div2_clk, + &extal1_div2_clk, + &extal2_div2_clk, + &extal2_div4_clk, + &pllc0_clk, + &pllc1_clk, + &pllc1_div2_clk, + &pllc2_clk, +}; + +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = __raw_readl(FRQCRB); + value |= (1 << 31); + __raw_writel(value, FRQCRB); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48, 0, 72, 96, 0 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, + DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, + DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, + DIV4_DDRP, DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags) + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), + [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), + [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), + [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), + [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), + [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), + [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0), + [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0), + [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0), + [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0), + [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0), +}; + +enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, + DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU, + DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, + DIV6_NR }; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0), + [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0), + [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), + [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), + [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), + [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0), + [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0), + [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0), + [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), + [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0), + [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0), + [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0), + [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0), +}; + +enum { DIV6_HDMI, DIV6_REPARENT_NR }; + +/* Indices are important - they are the actual src selecting values */ +static struct clk *hdmi_parent[] = { + [0] = &pllc1_div2_clk, + [1] = &pllc2_clk, + [2] = &dv_clki_clk, + [3] = NULL, /* pllc2_div4 not implemented yet */ +}; + +static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { + [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0, + hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), +}; + +enum { MSTP001, + MSTP131, MSTP130, + MSTP129, MSTP128, + MSTP118, MSTP117, MSTP116, + MSTP106, MSTP101, MSTP100, + MSTP223, + MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312, + MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403, + MSTP_NR }; + +#define MSTP(_parent, _reg, _bit, _flags) \ + SH_CLK_MSTP32(_parent, _reg, _bit, _flags) + +static struct clk mstp_clks[MSTP_NR] = { + [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */ + [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ + [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ + [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ + [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ + [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ + [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ + [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ + [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ + [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */ + [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ + [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */ + [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ + [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ + [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ + [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ + [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ + [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ + [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, CLK_ENABLE_ON_INIT), /* FSIA */ + [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ + [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ + [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ + [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ + [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */ + [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */ + [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */ + [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */ + [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ +}; + +#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } +#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk), + CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), + CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), + CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk), + CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), + CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), + CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), + CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), + CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), + CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), + CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), + CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), + CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), + CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), + CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), + CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), + CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]), + CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), + CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]), + CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), + CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), + CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]), + CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]), + CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]), + CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]), + CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), + CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), + CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), + CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), + CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]), + CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]), + CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ + CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ + CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */ + CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ + CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */ + CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */ + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ + CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */ + CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */ + CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */ + CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */ + CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */ + CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */ + CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */ + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ + {.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]}, +}; + +void __init sh7372_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) + ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + clk_init(); + else + panic("failed to setup sh7372 clocks\n"); + +} diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c new file mode 100644 index 00000000000..e007c28cf0a --- /dev/null +++ b/arch/arm/mach-shmobile/clock-sh7377.c @@ -0,0 +1,369 @@ +/* + * SH7377 clock framework support + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/sh_clk.h> +#include <mach/common.h> +#include <asm/clkdev.h> + +/* SH7377 registers */ +#define RTFRQCR 0xe6150000 +#define SYFRQCR 0xe6150004 +#define CMFRQCR 0xe61500E0 +#define VCLKCR1 0xe6150008 +#define VCLKCR2 0xe615000C +#define VCLKCR3 0xe615001C +#define FMSICKCR 0xe6150010 +#define FMSOCKCR 0xe6150014 +#define FSICKCR 0xe6150018 +#define PLLC1CR 0xe6150028 +#define PLLC2CR 0xe615002C +#define SUBUSBCKCR 0xe6150080 +#define SPUCKCR 0xe6150084 +#define MSUCKCR 0xe6150088 +#define MVI3CKCR 0xe6150090 +#define HDMICKCR 0xe6150094 +#define MFCK1CR 0xe6150098 +#define MFCK2CR 0xe615009C +#define DSITCKCR 0xe6150060 +#define DSIPCKCR 0xe6150064 +#define SMSTPCR0 0xe6150130 +#define SMSTPCR1 0xe6150134 +#define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013C +#define SMSTPCR4 0xe6150140 + +/* Fixed 32 KHz root clock from EXTALR pin */ +static struct clk r_clk = { + .rate = 32768, +}; + +/* + * 26MHz default rate for the EXTALC1 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh7377_extalc1_clk = { + .rate = 26666666, +}; + +/* + * 48MHz default rate for the EXTAL2 root input clock. + * If needed, reset this with clk_set_rate() from the platform code. + */ +struct clk sh7377_extal2_clk = { + .rate = 48000000, +}; + +/* A fixed divide-by-2 block */ +static unsigned long div2_recalc(struct clk *clk) +{ + return clk->parent->rate / 2; +} + +static struct clk_ops div2_clk_ops = { + .recalc = div2_recalc, +}; + +/* Divide extalc1 by two */ +static struct clk extalc1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7377_extalc1_clk, +}; + +/* Divide extal2 by two */ +static struct clk extal2_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7377_extal2_clk, +}; + +/* Divide extal2 by four */ +static struct clk extal2_div4_clk = { + .ops = &div2_clk_ops, + .parent = &extal2_div2_clk, +}; + +/* PLLC1 */ +static unsigned long pllc1_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (__raw_readl(PLLC1CR) & (1 << 14)) + mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2; + + return clk->parent->rate * mult; +} + +static struct clk_ops pllc1_clk_ops = { + .recalc = pllc1_recalc, +}; + +static struct clk pllc1_clk = { + .ops = &pllc1_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extalc1_div2_clk, +}; + +/* Divide PLLC1 by two */ +static struct clk pllc1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &pllc1_clk, +}; + +/* PLLC2 */ +static unsigned long pllc2_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (__raw_readl(PLLC2CR) & (1 << 31)) + mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; + + return clk->parent->rate * mult; +} + +static struct clk_ops pllc2_clk_ops = { + .recalc = pllc2_recalc, +}; + +static struct clk pllc2_clk = { + .ops = &pllc2_clk_ops, + .flags = CLK_ENABLE_ON_INIT, + .parent = &extalc1_div2_clk, +}; + +static struct clk *main_clks[] = { + &r_clk, + &sh7377_extalc1_clk, + &sh7377_extal2_clk, + &extalc1_div2_clk, + &extal2_div2_clk, + &extal2_div4_clk, + &pllc1_clk, + &pllc1_div2_clk, + &pllc2_clk, +}; + +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in SYFRQCR to update hardware setting */ + value = __raw_readl(SYFRQCR); + value |= (1 << 31); + __raw_writel(value, SYFRQCR); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48, 0, 72, 96, 0 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, + DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP, + DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; + +#define DIV4(_reg, _bit, _mask, _flags) \ + SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags) + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0), + [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0), + [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0), + [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0), + [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0), + [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0), + [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0), + [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0), + [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0), +}; + +enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, + DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI, + DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP, + DIV6_NR }; + +static struct clk div6_clks[] = { + [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0), + [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0), + [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), + [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), + [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), + [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0), + [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0), + [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), + [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0), + [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0), + [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0), + [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0), + [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0), + [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0), + [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0), +}; + +enum { MSTP001, + MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101, + MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, + MSTP331, MSTP329, MSTP325, MSTP323, MSTP322, + MSTP315, MSTP314, MSTP313, + MSTP403, + MSTP_NR }; + +#define MSTP(_parent, _reg, _bit, _flags) \ + SH_CLK_MSTP32(_parent, _reg, _bit, _flags) + +static struct clk mstp_clks[] = { + [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */ + [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ + [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ + [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ + [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ + [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ + [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ + [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */ + [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */ + [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ + [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ + [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ + [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ + [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ + [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ + [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ + [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */ + [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ + [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ + [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */ + [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ +}; + +#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } +#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } + +static struct clk_lookup lookups[] = { + /* main clocks */ + CLKDEV_CON_ID("r_clk", &r_clk), + CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk), + CLKDEV_CON_ID("extal2", &sh7377_extal2_clk), + CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk), + CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), + CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), + CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), + CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), + CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), + CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), + CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), + CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), + CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), + CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]), + CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), + CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]), + CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), + CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]), + CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), + + /* DIV6 clocks */ + CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), + CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]), + CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]), + CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]), + CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), + CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), + CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]), + CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]), + CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]), + CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]), + CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]), + CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]), + CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]), + + /* MSTP32 clocks */ + CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ + CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ + CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */ + CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */ + CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */ + CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ + CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */ + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ + CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ + CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ + CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ + CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ + CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ + CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */ + CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */ + CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ + CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */ + CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */ + CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ +}; + +void __init sh7377_clock_init(void) +{ + int k, ret = 0; + + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) + ret = clk_register(main_clks[k]); + + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + if (!ret) + clk_init(); + else + panic("failed to setup sh7377 clocks\n"); +} diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c new file mode 100644 index 00000000000..b7c705a213a --- /dev/null +++ b/arch/arm/mach-shmobile/clock.c @@ -0,0 +1,44 @@ +/* + * SH-Mobile Timer + * + * Copyright (C) 2010 Magnus Damm + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/sh_clk.h> + +int __init clk_init(void) +{ + /* Kick the child clocks.. */ + recalculate_root_clocks(); + + /* Enable the necessary init clocks */ + clk_enable_init_clocks(); + + return 0; +} + +int __clk_get(struct clk *clk) +{ + return 1; +} +EXPORT_SYMBOL(__clk_get); + +void __clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(__clk_put); diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 57903605cc5..efeef778a87 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -3,21 +3,31 @@ extern struct sys_timer shmobile_timer; extern void shmobile_setup_console(void); +struct clk; +extern int clk_init(void); extern void sh7367_init_irq(void); extern void sh7367_add_early_devices(void); extern void sh7367_add_standard_devices(void); extern void sh7367_clock_init(void); extern void sh7367_pinmux_init(void); +extern struct clk sh7367_extalb1_clk; +extern struct clk sh7367_extal2_clk; extern void sh7377_init_irq(void); extern void sh7377_add_early_devices(void); extern void sh7377_add_standard_devices(void); +extern void sh7377_clock_init(void); extern void sh7377_pinmux_init(void); +extern struct clk sh7377_extalc1_clk; +extern struct clk sh7377_extal2_clk; extern void sh7372_init_irq(void); extern void sh7372_add_early_devices(void); extern void sh7372_add_standard_devices(void); +extern void sh7372_clock_init(void); extern void sh7372_pinmux_init(void); +extern struct clk sh7372_extal1_clk; +extern struct clk sh7372_extal2_clk; #endif /* __ARCH_MACH_COMMON_H */ diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 132256bb8c8..fa15b5f8a00 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -3,7 +3,13 @@ #define NR_IRQS 512 +/* INTCA */ #define evt2irq(evt) (((evt) >> 5) - 16) #define irq2evt(irq) (((irq) + 16) << 5) +/* INTCS */ +#define INTCS_VECT_BASE 0x2200 +#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) +#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) + #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h index e188183f4dc..377584e57e0 100644 --- a/arch/arm/mach-shmobile/include/mach/memory.h +++ b/arch/arm/mach-shmobile/include/mach/memory.h @@ -4,4 +4,7 @@ #define PHYS_OFFSET UL(CONFIG_MEMORY_START) #define MEM_SIZE UL(CONFIG_MEMORY_SIZE) +/* DMA memory at 0xf6000000 - 0xffdfffff */ +#define CONSISTENT_DMA_SIZE (158 << 20) + #endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index dc34f00c56b..33e9700ded7 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -11,6 +11,8 @@ #ifndef __ASM_SH7372_H__ #define __ASM_SH7372_H__ +#include <linux/sh_clk.h> + /* * Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function @@ -431,4 +433,32 @@ enum { GPIO_FN_SDENC_DV_CLKI, }; +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_SDHI2_TX, +}; + +extern struct clk dv_clki_clk; +extern struct clk dv_clki_div2_clk; +extern struct clk pllc2_clk; + #endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h index fb3c4f1ab25..4aecf6e3a85 100644 --- a/arch/arm/mach-shmobile/include/mach/vmalloc.h +++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h @@ -1,6 +1,7 @@ #ifndef __ASM_MACH_VMALLOC_H #define __ASM_MACH_VMALLOC_H -#define VMALLOC_END (PAGE_OFFSET + 0x24000000) +/* Vmalloc at ... - 0xe5ffffff */ +#define VMALLOC_END 0xe6000000 #endif /* __ASM_MACH_VMALLOC_H */ diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 5ff70cadfc3..1a20c489b20 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -75,7 +75,7 @@ enum { ETM11, ARM11, USBHS, FLCTL, IIC1 }; -static struct intc_vect intca_vectors[] = { +static struct intc_vect intca_vectors[] __initdata = { INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), @@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = { INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), }; -static struct intc_mask_reg intca_mask_registers[] = { +static struct intc_mask_reg intca_mask_registers[] __initdata = { { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ @@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = { MISTY, CMT3, RWDT1, RWDT0 } }, }; -static struct intc_prio_reg intca_prio_registers[] = { +static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6900010, 0, 32, 4, /* INTPRI00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900014, 0, 32, 4, /* INTPRI10A */ @@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = { intca_sense_registers, intca_ack_registers), }; +enum { + UNUSED_INTCS = 0, + + INTCS, + + /* interrupt sources INTCS */ + VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3, + VIO3_VOU, + RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, + VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2, + VPU, + SGX530, + _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3, + IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, + IPMMU_IPMMUB, IPMMU_IPMMUS, + RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, + MSIOF, + IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, + TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, + CMT, + TSIF, + IPMMUI, + MVI3, + ICB, + PEP, + ASA, + BEM, + VE2HO, + HQE, + JPEG, + LCDC, + + /* interrupt groups INTCS */ + _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, +}; + +static struct intc_vect intcs_vectors[] = { + INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720), + INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760), + INTCS_VECT(VIO3_VOU, 0x780), + INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), + INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), + INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0), + INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0), + INTCS_VECT(VPU, 0x980), + INTCS_VECT(SGX530, 0x9e0), + INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20), + INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60), + INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), + INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), + INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60), + INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), + INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), + INTCS_VECT(MSIOF, 0xd20), + INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), + INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), + INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), + INTCS_VECT(TMU_TUNI2, 0xec0), + INTCS_VECT(CMT, 0xf00), + INTCS_VECT(TSIF, 0xf20), + INTCS_VECT(IPMMUI, 0xf60), + INTCS_VECT(MVI3, 0x420), + INTCS_VECT(ICB, 0x480), + INTCS_VECT(PEP, 0x4a0), + INTCS_VECT(ASA, 0x4c0), + INTCS_VECT(BEM, 0x4e0), + INTCS_VECT(VE2HO, 0x520), + INTCS_VECT(HQE, 0x540), + INTCS_VECT(JPEG, 0x560), + INTCS_VECT(LCDC, 0x580), + + INTC_VECT(INTCS, 0xf80), +}; + +static struct intc_group intcs_groups[] __initdata = { + INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1, + _2DDMAC_2DDM2, _2DDMAC_2DDM3), + INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1, + RTDMAC_1_DEI2, RTDMAC_1_DEI3), + INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR), + INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3), + INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2), + INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), + INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB), + INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), +}; + +static struct intc_mask_reg intcs_mask_registers[] = { + { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ + { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU, + VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } }, + { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ + { VIO3_VOU, 0, VE2HO, VPU, + 0, 0, 0, 0 } }, + { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ + { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0, + BEM, ASA, PEP, ICB } }, + { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ + { 0, 0, MVI3, 0, + JPEG, HQE, 0, LCDC } }, + { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ + { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4, + RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, + { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ + { 0, 0, MSIOF, 0, + SGX530, 0, 0, 0 } }, + { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ + { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, + 0, 0, 0, 0 } }, + { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ + { 0, 0, 0, CMT, + IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, + { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */ + { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0, + 0, 0, 0, 0 } }, + { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ + { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, + 0, 0, IPMMUI, TSIF } }, + { 0xffd20104, 0, 16, /* INTAMASK */ + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, INTCS } }, +}; + +/* Priority is needed for INTCA to receive the INTCS interrupt */ +static struct intc_prio_reg intcs_prio_registers[] = { + { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } }, + { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } }, + { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, + { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } }, + { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } }, + { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1, + TMU_TUNI2, 0 } }, + { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } }, + { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } }, + { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } }, + { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } }, + { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } }, + { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, +}; + +static struct resource intcs_resources[] __initdata = { + [0] = { + .start = 0xffd20000, + .end = 0xffd2ffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct intc_desc intcs_desc __initdata = { + .name = "sh7367-intcs", + .resource = intcs_resources, + .num_resources = ARRAY_SIZE(intcs_resources), + .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, + intcs_prio_registers, NULL, NULL), +}; + +static void intcs_demux(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *reg = (void *)get_irq_data(irq); + unsigned int evtcodeas = ioread32(reg); + + generic_handle_irq(intcs_evt2irq(evtcodeas)); +} + void __init sh7367_init_irq(void) { - /* INTCA */ + void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + register_intc_controller(&intca_desc); + register_intc_controller(&intcs_desc); + + /* demux using INTEVTSA */ + set_irq_data(evt2irq(0xf80), (void *)intevtsa); + set_irq_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 3ce9d9bd589..e3551b56cd0 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, CMT14, CMT15 } }, - { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, + { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } }, - { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, + { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4 } }, - { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, + { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, - { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, + { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, 0/*TXI*/, 0/*TEI*/} }, - { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, + { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, - { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, + { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, }; static struct intc_sense_reg intca_sense_registers[] __initdata = { @@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = { intca_sense_registers, intca_ack_registers), }; +enum { + UNUSED_INTCS = 0, + + INTCS, + + /* interrupt sources INTCS */ + VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, + RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, + CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2, + VPU, + TSIF1, + _3DG_SGX530, + _2DDMAC, + IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, + IPMMU_IPMMUR, IPMMU_IPMMUR2, + RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, + MSIOF, + IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, + TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, + CMT0, + TSIF0, + LMB, + CTI, + ICB, + JPU_JPEG, + LCDC, + LCRC, + RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, + RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, + ISP, + LCDC1, + CSIRX, + DSITX_DSITX0, + DSITX_DSITX1, + TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, + CMT4, + DSITX1_DSITX1_0, + DSITX1_DSITX1_1, + CPORTS2R, + JPU6E, + + /* interrupt groups INTCS */ + RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, + RTDMAC2_1, RTDMAC2_2, TMU1, DSITX, +}; + +static struct intc_vect intcs_vectors[] = { + INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720), + INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760), + INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), + INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), + INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0), + INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0), + INTCS_VECT(VPU, 0x980), + INTCS_VECT(TSIF1, 0x9a0), + INTCS_VECT(_3DG_SGX530, 0x9e0), + INTCS_VECT(_2DDMAC, 0xa00), + INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), + INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), + INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20), + INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), + INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), + INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), + INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), + INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), + INTCS_VECT(TMU_TUNI2, 0xec0), + INTCS_VECT(CMT0, 0xf00), + INTCS_VECT(TSIF0, 0xf20), + INTCS_VECT(LMB, 0xf60), + INTCS_VECT(CTI, 0x400), + INTCS_VECT(ICB, 0x480), + INTCS_VECT(JPU_JPEG, 0x560), + INTCS_VECT(LCDC, 0x580), + INTCS_VECT(LCRC, 0x5a0), + INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320), + INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360), + INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0), + INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0), + INTCS_VECT(ISP, 0x1720), + INTCS_VECT(LCDC1, 0x1780), + INTCS_VECT(CSIRX, 0x17a0), + INTCS_VECT(DSITX_DSITX0, 0x17c0), + INTCS_VECT(DSITX_DSITX1, 0x17e0), + INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920), + INTCS_VECT(TMU1_TUNI2, 0x1940), + INTCS_VECT(CMT4, 0x1980), + INTCS_VECT(DSITX1_DSITX1_0, 0x19a0), + INTCS_VECT(DSITX1_DSITX1_1, 0x19c0), + INTCS_VECT(CPORTS2R, 0x1a20), + INTCS_VECT(JPU6E, 0x1a80), + + INTC_VECT(INTCS, 0xf80), +}; + +static struct intc_group intcs_groups[] __initdata = { + INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1, + RTDMAC_1_DEI2, RTDMAC_1_DEI3), + INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR), + INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3), + INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2), + INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), + INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2), + INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), + INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, + RTDMAC2_1_DEI2, RTDMAC2_1_DEI3), + INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, + RTDMAC2_2_DEI5, RTDMAC2_2_DADERR), + INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0), + INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1), +}; + +static struct intc_mask_reg intcs_mask_registers[] = { + { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ + { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU, + VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } }, + { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ + { 0, 0, 0, VPU, + 0, 0, 0, 0 } }, + { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ + { 0, 0, 0, _2DDMAC, + 0, 0, 0, ICB } }, + { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ + { 0, 0, 0, CTI, + JPU_JPEG, 0, LCRC, LCDC } }, + { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ + { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4, + RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, + { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ + { 0, 0, MSIOF, 0, + _3DG_SGX530, 0, 0, 0 } }, + { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ + { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, + 0, 0, 0, 0 } }, + { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ + { 0, 0, 0, CMT0, + IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, + { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */ + { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR, + 0, 0, 0, 0 } }, + { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ + { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, + 0, TSIF1, LMB, TSIF0 } }, + { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ + { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4, + RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } }, + { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ + { 0, ISP, 0, 0, + LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } }, + { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ + { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, + CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } }, + { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ + { 0, CPORTS2R, 0, 0, + JPU6E, 0, 0, 0 } }, + { 0xffd20104, 0, 16, /* INTAMASK */ + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, INTCS } }, +}; + +/* Priority is needed for INTCA to receive the INTCS interrupt */ +static struct intc_prio_reg intcs_prio_registers[] = { + { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } }, + { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, + { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } }, + { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } }, + { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1, + TMU_TUNI2, TSIF1 } }, + { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } }, + { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } }, + { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } }, + { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } }, + { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } }, + { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, + { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } }, + { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } }, + { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } }, + { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } }, + { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, + { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0, + DSITX1_DSITX1_1, 0 } }, + { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } }, + { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } }, +}; + +static struct resource intcs_resources[] __initdata = { + [0] = { + .start = 0xffd20000, + .end = 0xffd201ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0xffd50000, + .end = 0xffd501ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct intc_desc intcs_desc __initdata = { + .name = "sh7372-intcs", + .resource = intcs_resources, + .num_resources = ARRAY_SIZE(intcs_resources), + .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, + intcs_prio_registers, NULL, NULL), +}; + +static void intcs_demux(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *reg = (void *)get_irq_data(irq); + unsigned int evtcodeas = ioread32(reg); + + generic_handle_irq(intcs_evt2irq(evtcodeas)); +} + void __init sh7372_init_irq(void) { + void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + register_intc_controller(&intca_desc); + register_intc_controller(&intcs_desc); + + /* demux using INTEVTSA */ + set_irq_data(evt2irq(0xf80), (void *)intevtsa); + set_irq_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index 5c781e2d189..2cdeb8ccd82 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -90,7 +90,7 @@ enum { ICUSB, ICUDMC }; -static struct intc_vect intca_vectors[] = { +static struct intc_vect intca_vectors[] __initdata = { INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), @@ -202,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = { INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), }; -static struct intc_mask_reg intca_mask_registers[] = { +static struct intc_mask_reg intca_mask_registers[] __initdata = { { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ @@ -272,7 +272,7 @@ static struct intc_mask_reg intca_mask_registers[] = { SCIFA6, 0, 0, 0 } }, }; -static struct intc_prio_reg intca_prio_registers[] = { +static struct intc_prio_reg intca_prio_registers[] __initdata = { { 0xe6900010, 0, 32, 4, /* INTPRI00A */ { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, { 0xe6900014, 0, 32, 4, /* INTPRI10A */ @@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = { intca_sense_registers, intca_ack_registers), }; +/* this macro ignore entry which is also in INTCA */ +#define __IGNORE(a...) +#define __IGNORE0(a...) 0 + +enum { + UNUSED_INTCS = 0, + + INTCS, + + /* interrupt sources INTCS */ + VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, + RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3, + CEU, + BEU_BEU0, BEU_BEU1, BEU_BEU2, + __IGNORE(MFI) + __IGNORE(BBIF2) + VPU, + TSIF1, + __IGNORE(SGX540) + _2DDMAC, + IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, + IPMMU_IPMMUR, IPMMU_IPMMUR2, + RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR, + __IGNORE(KEYSC) + __IGNORE(TTI20) + __IGNORE(MSIOF) + IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, + TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, + CMT0, + TSIF0, + __IGNORE(CMT2) + LMB, + __IGNORE(MSUG) + __IGNORE(MSU_MSU, MSU_MSU2) + __IGNORE(CTI) + MVI3, + __IGNORE(RWDT0) + __IGNORE(RWDT1) + ICB, + PEP, + ASA, + __IGNORE(_2DG) + HQE, + JPU, + LCDC0, + __IGNORE(LCRC) + RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, + RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, + FRC, + LCDC1, + CSIRX, + DSITX_DSITX0, DSITX_DSITX1, + __IGNORE(SPU2_SPU0, SPU2_SPU1) + __IGNORE(FSI) + __IGNORE(FMSI) + __IGNORE(SCUV) + TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, + TSIF2, + CMT4, + __IGNORE(MFIS2) + CPORTS2R, + + /* interrupt groups INTCS */ + RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU, + IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1, +}; + +#define INTCS_INTVECT 0x0F80 +static struct intc_vect intcs_vectors[] __initdata = { + INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720), + INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760), + INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820), + INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860), + INTCS_VECT(CEU, 0x0880), + INTCS_VECT(BEU_BEU0, 0x08A0), + INTCS_VECT(BEU_BEU1, 0x08C0), + INTCS_VECT(BEU_BEU2, 0x08E0), + __IGNORE(INTCS_VECT(MFI, 0x0900)) + __IGNORE(INTCS_VECT(BBIF2, 0x0960)) + INTCS_VECT(VPU, 0x0980), + INTCS_VECT(TSIF1, 0x09A0), + __IGNORE(INTCS_VECT(SGX540, 0x09E0)) + INTCS_VECT(_2DDMAC, 0x0A00), + INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0), + INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0), + INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20), + INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80), + INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0), + INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0), + __IGNORE(INTCS_VECT(KEYSC 0x0BE0)) + __IGNORE(INTCS_VECT(TTI20, 0x0C80)) + __IGNORE(INTCS_VECT(MSIOF, 0x0D20)) + INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20), + INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60), + INTCS_VECT(TMU_TUNI0, 0x0E80), + INTCS_VECT(TMU_TUNI1, 0x0EA0), + INTCS_VECT(TMU_TUNI2, 0x0EC0), + INTCS_VECT(CMT0, 0x0F00), + INTCS_VECT(TSIF0, 0x0F20), + __IGNORE(INTCS_VECT(CMT2, 0x0F40)) + INTCS_VECT(LMB, 0x0F60), + __IGNORE(INTCS_VECT(MSUG, 0x0F80)) + __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0)) + __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0)) + __IGNORE(INTCS_VECT(CTI, 0x0400)) + INTCS_VECT(MVI3, 0x0420), + __IGNORE(INTCS_VECT(RWDT0, 0x0440)) + __IGNORE(INTCS_VECT(RWDT1, 0x0460)) + INTCS_VECT(ICB, 0x0480), + INTCS_VECT(PEP, 0x04A0), + INTCS_VECT(ASA, 0x04C0), + __IGNORE(INTCS_VECT(_2DG, 0x04E0)) + INTCS_VECT(HQE, 0x0540), + INTCS_VECT(JPU, 0x0560), + INTCS_VECT(LCDC0, 0x0580), + __IGNORE(INTCS_VECT(LCRC, 0x05A0)) + INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320), + INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360), + INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0), + INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0), + INTCS_VECT(FRC, 0x1700), + INTCS_VECT(LCDC1, 0x1780), + INTCS_VECT(CSIRX, 0x17A0), + INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0), + __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800)) + __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820)) + __IGNORE(INTCS_VECT(FSI, 0x1840)) + __IGNORE(INTCS_VECT(FMSI, 0x1860)) + __IGNORE(INTCS_VECT(SCUV, 0x1880)) + INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), + INTCS_VECT(TMU1_TUNI12, 0x1940), + INTCS_VECT(TSIF2, 0x1960), + INTCS_VECT(CMT4, 0x1980), + __IGNORE(INTCS_VECT(MFIS2, 0x1A00)) + INTCS_VECT(CPORTS2R, 0x1A20), + + INTC_VECT(INTCS, INTCS_INTVECT), +}; + +static struct intc_group intcs_groups[] __initdata = { + INTC_GROUP(RTDMAC1_1, + RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, + RTDMAC1_1_DEI2, RTDMAC1_1_DEI3), + INTC_GROUP(RTDMAC1_2, + RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR), + INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3), + INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2), + INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), + __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2)) + INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2), + INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), + INTC_GROUP(RTDMAC2_1, + RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, + RTDMAC2_1_DEI2, RTDMAC2_1_DEI3), + INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR), + INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1), + __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1)) + INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12), +}; + +static struct intc_mask_reg intcs_mask_registers[] __initdata = { + { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */ + { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU, + VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } }, + { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */ + { 0, 0, 0, VPU, + __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } }, + { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */ + { 0, 0, 0, _2DDMAC, + __IGNORE0(_2DG), ASA, PEP, ICB } }, + { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */ + { 0, 0, MVI3, __IGNORE0(CTI), + JPU, HQE, __IGNORE0(LCRC), LCDC0 } }, + { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */ + { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4, + RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } }, + __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */ + { 0, 0, MSIOF, 0, + SGX540, 0, TTI20, 0 } }) + { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */ + { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, + 0, 0, 0, 0 } }, + __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */ + { 0, 0, 0, 0, + 0, MSU_MSU, MSU_MSU2, MSUG } }) + { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */ + { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0, + IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, + { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */ + { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2, + 0, 0, 0, 0 } }, + { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */ + { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, + 0, TSIF1, LMB, TSIF0 } }, + { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */ + { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, + RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } }, + { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */ + { FRC, 0, 0, 0, + LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } }, + __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */ + {SPU2_SPU0, SPU2_SPU1, FSI, FMSI, + SCUV, 0, 0, 0 } }) + { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */ + { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2, + CMT4, 0, 0, 0 } }, + { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */ + { __IGNORE0(MFIS2), CPORTS2R, 0, 0, + 0, 0, 0, 0 } }, + { 0xFFD20104, 0, 16, /* INTAMASK */ + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, INTCS } } +}; + +static struct intc_prio_reg intcs_prio_registers[] __initdata = { + /* IPRAS */ + { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } }, + /* IPRBS */ + { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } }, + /* IPRCS */ + __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } }) + /* IPRES */ + { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } }, + /* IPRFS */ + { 0xFFD20014, 0, 16, 4, + { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } }, + /* IPRGS */ + { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } }, + /* IPRHS */ + { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } }, + /* IPRIS */ + { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } }, + /* IPRJS */ + __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } }) + /* IPRKS */ + { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } }, + /* IPRLS */ + { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } }, + /* IPRMS */ + { 0xFFD20030, 0, 16, 4, + { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } }, + /* IPRAS3 */ + { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } }, + /* IPRBS3 */ + { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } }, + /* IPRIS3 */ + { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } }, + /* IPRJS3 */ + { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } }, + /* IPRKS3 */ + __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } }) + /* IPRLS3 */ + __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } }) + /* IPRMS3 */ + { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } }, + /* IPRNS3 */ + { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } }, + /* IPROS3 */ + { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } }, +}; + +static struct resource intcs_resources[] __initdata = { + [0] = { + .start = 0xffd20000, + .end = 0xffd500ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct intc_desc intcs_desc __initdata = { + .name = "sh7377-intcs", + .resource = intcs_resources, + .num_resources = ARRAY_SIZE(intcs_resources), + .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, + intcs_mask_registers, intcs_prio_registers, + NULL, NULL), +}; + +static void intcs_demux(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *reg = (void *)get_irq_data(irq); + unsigned int evtcodeas = ioread32(reg); + + generic_handle_irq(intcs_evt2irq(evtcodeas)); +} + +#define INTEVTSA 0xFFD20100 void __init sh7377_init_irq(void) { + void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); + register_intc_controller(&intca_desc); + register_intc_controller(&intcs_desc); + + /* demux using INTEVTSA */ + set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); + set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); } diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c index 9557d0964d7..ec420353f8e 100644 --- a/arch/arm/mach-shmobile/pfc-sh7372.c +++ b/arch/arm/mach-shmobile/pfc-sh7372.c @@ -1160,6 +1160,9 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(LCDD18), GPIO_FN(LCDD19), GPIO_FN(LCDD20), GPIO_FN(LCDD21), GPIO_FN(LCDD22), GPIO_FN(LCDD23), + GPIO_FN(LCDC0_SELECT), + GPIO_FN(LCDC1_SELECT), + /* IRDA */ GPIO_FN(IRDA_OUT), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL), GPIO_FN(IROUT_139), GPIO_FN(IROUT_140), diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c index eca90716140..3148c11a550 100644 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -31,11 +31,13 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +/* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = { evt2irq(0xc00), evt2irq(0xc00), + evt2irq(0xc00), evt2irq(0xc00) }, }; static struct platform_device scif0_device = { @@ -46,11 +48,13 @@ static struct platform_device scif0_device = { }, }; +/* SCIFA1 */ static struct plat_sci_port scif1_platform_data = { .mapbase = 0xe6c50000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = { evt2irq(0xc20), evt2irq(0xc20), + evt2irq(0xc20), evt2irq(0xc20) }, }; static struct platform_device scif1_device = { @@ -61,11 +65,13 @@ static struct platform_device scif1_device = { }, }; +/* SCIFA2 */ static struct plat_sci_port scif2_platform_data = { .mapbase = 0xe6c60000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = { evt2irq(0xc40), evt2irq(0xc40), + evt2irq(0xc40), evt2irq(0xc40) }, }; static struct platform_device scif2_device = { @@ -76,11 +82,13 @@ static struct platform_device scif2_device = { }, }; +/* SCIFA3 */ static struct plat_sci_port scif3_platform_data = { .mapbase = 0xe6c70000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 83, 83, 83, 83 }, + .irqs = { evt2irq(0xc60), evt2irq(0xc60), + evt2irq(0xc60), evt2irq(0xc60) }, }; static struct platform_device scif3_device = { @@ -91,11 +99,13 @@ static struct platform_device scif3_device = { }, }; +/* SCIFA4 */ static struct plat_sci_port scif4_platform_data = { .mapbase = 0xe6c80000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 89, 89, 89, 89 }, + .irqs = { evt2irq(0xd20), evt2irq(0xd20), + evt2irq(0xd20), evt2irq(0xd20) }, }; static struct platform_device scif4_device = { @@ -106,11 +116,13 @@ static struct platform_device scif4_device = { }, }; +/* SCIFA5 */ static struct plat_sci_port scif5_platform_data = { .mapbase = 0xe6cb0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 90, 90, 90, 90 }, + .irqs = { evt2irq(0xd40), evt2irq(0xd40), + evt2irq(0xd40), evt2irq(0xd40) }, }; static struct platform_device scif5_device = { @@ -121,11 +133,13 @@ static struct platform_device scif5_device = { }, }; +/* SCIFB */ static struct plat_sci_port scif6_platform_data = { .mapbase = 0xe6c30000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 91, 91, 91, 91 }, + .irqs = { evt2irq(0xd60), evt2irq(0xd60), + evt2irq(0xd60), evt2irq(0xd60) }, }; static struct platform_device scif6_device = { @@ -153,7 +167,7 @@ static struct resource cmt10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 72, + .start = evt2irq(0xb00), /* CMT1_CMT10 */ .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 1d1153290f5..e26686c9d0b 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -26,17 +26,21 @@ #include <linux/input.h> #include <linux/io.h> #include <linux/serial_sci.h> +#include <linux/sh_dma.h> #include <linux/sh_intc.h> #include <linux/sh_timer.h> #include <mach/hardware.h> +#include <mach/sh7372.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +/* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .type = PORT_SCIFA, + .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), + evt2irq(0x0c00), evt2irq(0x0c00) }, }; static struct platform_device scif0_device = { @@ -47,11 +51,13 @@ static struct platform_device scif0_device = { }, }; +/* SCIFA1 */ static struct plat_sci_port scif1_platform_data = { .mapbase = 0xe6c50000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .type = PORT_SCIFA, + .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), + evt2irq(0x0c20), evt2irq(0x0c20) }, }; static struct platform_device scif1_device = { @@ -62,11 +68,13 @@ static struct platform_device scif1_device = { }, }; +/* SCIFA2 */ static struct plat_sci_port scif2_platform_data = { .mapbase = 0xe6c60000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .type = PORT_SCIFA, + .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), + evt2irq(0x0c40), evt2irq(0x0c40) }, }; static struct platform_device scif2_device = { @@ -77,11 +85,13 @@ static struct platform_device scif2_device = { }, }; +/* SCIFA3 */ static struct plat_sci_port scif3_platform_data = { .mapbase = 0xe6c70000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 83, 83, 83, 83 }, + .type = PORT_SCIFA, + .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), + evt2irq(0x0c60), evt2irq(0x0c60) }, }; static struct platform_device scif3_device = { @@ -92,11 +102,13 @@ static struct platform_device scif3_device = { }, }; +/* SCIFA4 */ static struct plat_sci_port scif4_platform_data = { .mapbase = 0xe6c80000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 89, 89, 89, 89 }, + .type = PORT_SCIFA, + .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), + evt2irq(0x0d20), evt2irq(0x0d20) }, }; static struct platform_device scif4_device = { @@ -107,11 +119,13 @@ static struct platform_device scif4_device = { }, }; +/* SCIFA5 */ static struct plat_sci_port scif5_platform_data = { .mapbase = 0xe6cb0000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 90, 90, 90, 90 }, + .type = PORT_SCIFA, + .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), + evt2irq(0x0d40), evt2irq(0x0d40) }, }; static struct platform_device scif5_device = { @@ -122,11 +136,13 @@ static struct platform_device scif5_device = { }, }; +/* SCIFB */ static struct plat_sci_port scif6_platform_data = { .mapbase = 0xe6c30000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCIF, - .irqs = { 91, 91, 91, 91 }, + .type = PORT_SCIFB, + .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), + evt2irq(0x0d60), evt2irq(0x0d60) }, }; static struct platform_device scif6_device = { @@ -137,11 +153,12 @@ static struct platform_device scif6_device = { }, }; +/* CMT */ static struct sh_timer_config cmt10_platform_data = { .name = "CMT10", .channel_offset = 0x10, .timer_bit = 0, - .clk = "r_clk", + .clk = "cmt1", .clockevent_rating = 125, .clocksource_rating = 125, }; @@ -154,7 +171,7 @@ static struct resource cmt10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 72, + .start = evt2irq(0x0b00), /* CMT1_CMT10 */ .flags = IORESOURCE_IRQ, }, }; @@ -169,6 +186,337 @@ static struct platform_device cmt10_device = { .num_resources = ARRAY_SIZE(cmt10_resources), }; +/* I2C */ +static struct resource iic0_resources[] = { + [0] = { + .name = "IIC0", + .start = 0xFFF20000, + .end = 0xFFF20425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */ + .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device iic0_device = { + .name = "i2c-sh_mobile", + .id = 0, /* "i2c0" clock */ + .num_resources = ARRAY_SIZE(iic0_resources), + .resource = iic0_resources, +}; + +static struct resource iic1_resources[] = { + [0] = { + .name = "IIC1", + .start = 0xE6C20000, + .end = 0xE6C20425 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x780), /* IIC1_ALI1 */ + .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device iic1_device = { + .name = "i2c-sh_mobile", + .id = 1, /* "i2c1" clock */ + .num_resources = ARRAY_SIZE(iic1_resources), + .resource = iic1_resources, +}; + +/* DMA */ +/* Transmit sizes and respective CHCR register values */ +enum { + XMIT_SZ_8BIT = 0, + XMIT_SZ_16BIT = 1, + XMIT_SZ_32BIT = 2, + XMIT_SZ_64BIT = 7, + XMIT_SZ_128BIT = 3, + XMIT_SZ_256BIT = 4, + XMIT_SZ_512BIT = 5, +}; + +/* log2(size / 8) - used to calculate number of transfers */ +#define TS_SHIFT { \ + [XMIT_SZ_8BIT] = 0, \ + [XMIT_SZ_16BIT] = 1, \ + [XMIT_SZ_32BIT] = 2, \ + [XMIT_SZ_64BIT] = 3, \ + [XMIT_SZ_128BIT] = 4, \ + [XMIT_SZ_256BIT] = 5, \ + [XMIT_SZ_512BIT] = 6, \ +} + +#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \ + (((i) & 0xc) << (20 - 2))) + +static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SCIF0_TX, + .addr = 0xe6c40020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x21, + }, { + .slave_id = SHDMA_SLAVE_SCIF0_RX, + .addr = 0xe6c40024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x22, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_TX, + .addr = 0xe6c50020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x25, + }, { + .slave_id = SHDMA_SLAVE_SCIF1_RX, + .addr = 0xe6c50024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x26, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_TX, + .addr = 0xe6c60020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x29, + }, { + .slave_id = SHDMA_SLAVE_SCIF2_RX, + .addr = 0xe6c60024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2a, + }, { + .slave_id = SHDMA_SLAVE_SCIF3_TX, + .addr = 0xe6c70020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2d, + }, { + .slave_id = SHDMA_SLAVE_SCIF3_RX, + .addr = 0xe6c70024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x2e, + }, { + .slave_id = SHDMA_SLAVE_SCIF4_TX, + .addr = 0xe6c80020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x39, + }, { + .slave_id = SHDMA_SLAVE_SCIF4_RX, + .addr = 0xe6c80024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x3a, + }, { + .slave_id = SHDMA_SLAVE_SCIF5_TX, + .addr = 0xe6cb0020, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x35, + }, { + .slave_id = SHDMA_SLAVE_SCIF5_RX, + .addr = 0xe6cb0024, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x36, + }, { + .slave_id = SHDMA_SLAVE_SCIF6_TX, + .addr = 0xe6c30040, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x3d, + }, { + .slave_id = SHDMA_SLAVE_SCIF6_RX, + .addr = 0xe6c30060, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), + .mid_rid = 0x3e, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_TX, + .addr = 0xe6850030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_RX, + .addr = 0xe6850030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc2, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_TX, + .addr = 0xe6860030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xc9, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_RX, + .addr = 0xe6860030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xca, + }, { + .slave_id = SHDMA_SLAVE_SDHI2_TX, + .addr = 0xe6870030, + .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xcd, + }, { + .slave_id = SHDMA_SLAVE_SDHI2_RX, + .addr = 0xe6870030, + .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), + .mid_rid = 0xce, + }, +}; + +static const struct sh_dmae_channel sh7372_dmae_channels[] = { + { + .offset = 0, + .dmars = 0, + .dmars_bit = 0, + }, { + .offset = 0x10, + .dmars = 0, + .dmars_bit = 8, + }, { + .offset = 0x20, + .dmars = 4, + .dmars_bit = 0, + }, { + .offset = 0x30, + .dmars = 4, + .dmars_bit = 8, + }, { + .offset = 0x50, + .dmars = 8, + .dmars_bit = 0, + }, { + .offset = 0x60, + .dmars = 8, + .dmars_bit = 8, + } +}; + +static const unsigned int ts_shift[] = TS_SHIFT; + +static struct sh_dmae_pdata dma_platform_data = { + .slave = sh7372_dmae_slaves, + .slave_num = ARRAY_SIZE(sh7372_dmae_slaves), + .channel = sh7372_dmae_channels, + .channel_num = ARRAY_SIZE(sh7372_dmae_channels), + .ts_low_shift = 3, + .ts_low_mask = 0x18, + .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ + .ts_high_mask = 0x00300000, + .ts_shift = ts_shift, + .ts_shift_num = ARRAY_SIZE(ts_shift), + .dmaor_init = DMAOR_DME, +}; + +/* Resource order important! */ +static struct resource sh7372_dmae0_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfe008020, + .end = 0xfe00808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfe009000, + .end = 0xfe00900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error IRQ */ + .start = 246, + .end = 246, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-5 */ + .start = 240, + .end = 245, + .flags = IORESOURCE_IRQ, + }, +}; + +/* Resource order important! */ +static struct resource sh7372_dmae1_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfe018020, + .end = 0xfe01808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfe019000, + .end = 0xfe01900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error IRQ */ + .start = 254, + .end = 254, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-5 */ + .start = 248, + .end = 253, + .flags = IORESOURCE_IRQ, + }, +}; + +/* Resource order important! */ +static struct resource sh7372_dmae2_resources[] = { + { + /* Channel registers and DMAOR */ + .start = 0xfe028020, + .end = 0xfe02808f, + .flags = IORESOURCE_MEM, + }, + { + /* DMARSx */ + .start = 0xfe029000, + .end = 0xfe02900b, + .flags = IORESOURCE_MEM, + }, + { + /* DMA error IRQ */ + .start = 262, + .end = 262, + .flags = IORESOURCE_IRQ, + }, + { + /* IRQ for channels 0-5 */ + .start = 256, + .end = 261, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dma0_device = { + .name = "sh-dma-engine", + .id = 0, + .resource = sh7372_dmae0_resources, + .num_resources = ARRAY_SIZE(sh7372_dmae0_resources), + .dev = { + .platform_data = &dma_platform_data, + }, +}; + +static struct platform_device dma1_device = { + .name = "sh-dma-engine", + .id = 1, + .resource = sh7372_dmae1_resources, + .num_resources = ARRAY_SIZE(sh7372_dmae1_resources), + .dev = { + .platform_data = &dma_platform_data, + }, +}; + +static struct platform_device dma2_device = { + .name = "sh-dma-engine", + .id = 2, + .resource = sh7372_dmae2_resources, + .num_resources = ARRAY_SIZE(sh7372_dmae2_resources), + .dev = { + .platform_data = &dma_platform_data, + }, +}; + static struct platform_device *sh7372_early_devices[] __initdata = { &scif0_device, &scif1_device, @@ -178,6 +526,11 @@ static struct platform_device *sh7372_early_devices[] __initdata = { &scif5_device, &scif6_device, &cmt10_device, + &iic0_device, + &iic1_device, + &dma0_device, + &dma1_device, + &dma2_device, }; void __init sh7372_add_standard_devices(void) @@ -186,14 +539,8 @@ void __init sh7372_add_standard_devices(void) ARRAY_SIZE(sh7372_early_devices)); } -#define SMSTPCR3 0xe615013c -#define SMSTPCR3_CMT1 (1 << 29) - void __init sh7372_add_early_devices(void) { - /* enable clock to CMT1 */ - __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); - early_platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); } diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c index 60e37774c35..bb4adf17dbf 100644 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -32,11 +32,13 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> +/* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 80, 80, 80, 80 }, + .irqs = { evt2irq(0xc00), evt2irq(0xc00), + evt2irq(0xc00), evt2irq(0xc00) }, }; static struct platform_device scif0_device = { @@ -47,11 +49,13 @@ static struct platform_device scif0_device = { }, }; +/* SCIFA1 */ static struct plat_sci_port scif1_platform_data = { .mapbase = 0xe6c50000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 81, 81, 81, 81 }, + .irqs = { evt2irq(0xc20), evt2irq(0xc20), + evt2irq(0xc20), evt2irq(0xc20) }, }; static struct platform_device scif1_device = { @@ -62,11 +66,13 @@ static struct platform_device scif1_device = { }, }; +/* SCIFA2 */ static struct plat_sci_port scif2_platform_data = { .mapbase = 0xe6c60000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 82, 82, 82, 82 }, + .irqs = { evt2irq(0xc40), evt2irq(0xc40), + evt2irq(0xc40), evt2irq(0xc40) }, }; static struct platform_device scif2_device = { @@ -77,11 +83,13 @@ static struct platform_device scif2_device = { }, }; +/* SCIFA3 */ static struct plat_sci_port scif3_platform_data = { .mapbase = 0xe6c70000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 83, 83, 83, 83 }, + .irqs = { evt2irq(0xc60), evt2irq(0xc60), + evt2irq(0xc60), evt2irq(0xc60) }, }; static struct platform_device scif3_device = { @@ -92,11 +100,13 @@ static struct platform_device scif3_device = { }, }; +/* SCIFA4 */ static struct plat_sci_port scif4_platform_data = { .mapbase = 0xe6c80000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 89, 89, 89, 89 }, + .irqs = { evt2irq(0xd20), evt2irq(0xd20), + evt2irq(0xd20), evt2irq(0xd20) }, }; static struct platform_device scif4_device = { @@ -107,11 +117,13 @@ static struct platform_device scif4_device = { }, }; +/* SCIFA5 */ static struct plat_sci_port scif5_platform_data = { .mapbase = 0xe6cb0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 90, 90, 90, 90 }, + .irqs = { evt2irq(0xd40), evt2irq(0xd40), + evt2irq(0xd40), evt2irq(0xd40) }, }; static struct platform_device scif5_device = { @@ -122,11 +134,13 @@ static struct platform_device scif5_device = { }, }; +/* SCIFA6 */ static struct plat_sci_port scif6_platform_data = { .mapbase = 0xe6cc0000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 196, 196, 196, 196 }, + .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), + intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, }; static struct platform_device scif6_device = { @@ -137,11 +151,13 @@ static struct platform_device scif6_device = { }, }; +/* SCIFB */ static struct plat_sci_port scif7_platform_data = { .mapbase = 0xe6c30000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 91, 91, 91, 91 }, + .irqs = { evt2irq(0xd60), evt2irq(0xd60), + evt2irq(0xd60), evt2irq(0xd60) }, }; static struct platform_device scif7_device = { @@ -169,7 +185,7 @@ static struct resource cmt10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = 72, + .start = evt2irq(0xb00), /* CMT1_CMT10 */ .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig new file mode 100644 index 00000000000..a57713c1954 --- /dev/null +++ b/arch/arm/mach-tegra/Kconfig @@ -0,0 +1,50 @@ +if ARCH_TEGRA + +comment "NVIDIA Tegra options" + +choice + prompt "Select Tegra processor family for target system" + +config ARCH_TEGRA_2x_SOC + bool "Tegra 2 family" + select CPU_V7 + select ARM_GIC + select ARCH_REQUIRE_GPIOLIB + help + Support for NVIDIA Tegra AP20 and T20 processors, based on the + ARM CortexA9MP CPU and the ARM PL310 L2 cache controller + +endchoice + +comment "Tegra board type" + +config MACH_HARMONY + bool "Harmony board" + help + Support for nVidia Harmony development platform + +choice + prompt "Low-level debug console UART" + default TEGRA_DEBUG_UART_NONE + +config TEGRA_DEBUG_UART_NONE + bool "None" + +config TEGRA_DEBUG_UARTA + bool "UART-A" + +config TEGRA_DEBUG_UARTB + bool "UART-B" + +config TEGRA_DEBUG_UARTC + bool "UART-C" + +config TEGRA_DEBUG_UARTD + bool "UART-D" + +config TEGRA_DEBUG_UARTE + bool "UART-E" + +endchoice + +endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile new file mode 100644 index 00000000000..51e9370eed9 --- /dev/null +++ b/arch/arm/mach-tegra/Makefile @@ -0,0 +1,14 @@ +obj-y += common.o +obj-y += io.o +obj-y += irq.o +obj-y += clock.o +obj-y += timer.o +obj-y += gpio.o +obj-y += pinmux.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o +obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +obj-${CONFIG_MACH_HARMONY} += board-harmony.o +obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot new file mode 100644 index 00000000000..db52d61a738 --- /dev/null +++ b/arch/arm/mach-tegra/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00008000 +params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 +initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c new file mode 100644 index 00000000000..50b15d500ca --- /dev/null +++ b/arch/arm/mach-tegra/board-harmony-pinmux.c @@ -0,0 +1,144 @@ +/* + * arch/arm/mach-tegra/board-harmony-pinmux.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <mach/pinmux.h> + +#include "board-harmony.h" + +static struct tegra_pingroup_config harmony_pinmux[] = { + {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +void harmony_pinmux_init(void) +{ + tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux)); +} diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c new file mode 100644 index 00000000000..9e305de56be --- /dev/null +++ b/arch/arm/mach-tegra/board-harmony.c @@ -0,0 +1,125 @@ +/* + * arch/arm/mach-tegra/board-harmony.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/pda_power.h> +#include <linux/io.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/setup.h> + +#include <mach/iomap.h> +#include <mach/irqs.h> + +#include "board.h" +#include "board-harmony.h" +#include "clock.h" + +/* NVidia bootloader tags */ +#define ATAG_NVIDIA 0x41000801 + +#define ATAG_NVIDIA_RM 0x1 +#define ATAG_NVIDIA_DISPLAY 0x2 +#define ATAG_NVIDIA_FRAMEBUFFER 0x3 +#define ATAG_NVIDIA_CHIPSHMOO 0x4 +#define ATAG_NVIDIA_CHIPSHMOOPHYS 0x5 +#define ATAG_NVIDIA_PRESERVED_MEM_0 0x10000 +#define ATAG_NVIDIA_PRESERVED_MEM_N 2 +#define ATAG_NVIDIA_FORCE_32 0x7fffffff + +struct tag_tegra { + __u32 bootarg_key; + __u32 bootarg_len; + char bootarg[1]; +}; + +static int __init parse_tag_nvidia(const struct tag *tag) +{ + + return 0; +} +__tagtable(ATAG_NVIDIA, parse_tag_nvidia); + +static struct plat_serial8250_port debug_uart_platform_data[] = { + { + .membase = IO_ADDRESS(TEGRA_UARTD_BASE), + .mapbase = TEGRA_UARTD_BASE, + .irq = INT_UARTD, + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, { + .flags = 0 + } +}; + +static struct platform_device debug_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = debug_uart_platform_data, + }, +}; + +static struct platform_device *harmony_devices[] __initdata = { + &debug_uart, +}; + +static void __init tegra_harmony_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 2; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].size = 448 * SZ_1M; + mi->bank[1].start = SZ_512M; + mi->bank[1].size = SZ_512M; +} + +static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = { + /* name parent rate enabled */ + { "uartd", "pll_p", 216000000, true }, + { NULL, NULL, 0, 0}, +}; + +static void __init tegra_harmony_init(void) +{ + tegra_common_init(); + + tegra_clk_init_from_table(harmony_clk_init_table); + + harmony_pinmux_init(); + + platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices)); +} + +MACHINE_START(HARMONY, "harmony") + .boot_params = 0x00000100, + .phys_io = IO_APB_PHYS, + .io_pg_offst = ((IO_APB_VIRT) >> 18) & 0xfffc, + .fixup = tegra_harmony_fixup, + .init_irq = tegra_init_irq, + .init_machine = tegra_harmony_init, + .map_io = tegra_map_common_io, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h new file mode 100644 index 00000000000..09ca7755dd5 --- /dev/null +++ b/arch/arm/mach-tegra/board-harmony.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-tegra/board-harmony.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_HARMONY_H +#define _MACH_TEGRA_BOARD_HARMONY_H + +void harmony_pinmux_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h new file mode 100644 index 00000000000..3d06354136f --- /dev/null +++ b/arch/arm/mach-tegra/board.h @@ -0,0 +1,32 @@ +/* + * arch/arm/mach-tegra/board.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_BOARD_H +#define __MACH_TEGRA_BOARD_H + +#include <linux/types.h> + +void __init tegra_common_init(void); +void __init tegra_map_common_io(void); +void __init tegra_init_irq(void); +void __init tegra_init_clock(void); + +extern struct sys_timer tegra_timer; +#endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c new file mode 100644 index 00000000000..03ad578349b --- /dev/null +++ b/arch/arm/mach-tegra/clock.c @@ -0,0 +1,488 @@ +/* + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/list.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/debugfs.h> +#include <linux/slab.h> +#include <linux/seq_file.h> +#include <asm/clkdev.h> + +#include "clock.h" + +static LIST_HEAD(clocks); + +static DEFINE_SPINLOCK(clock_lock); + +struct clk *tegra_get_clock_by_name(const char *name) +{ + struct clk *c; + struct clk *ret = NULL; + unsigned long flags; + spin_lock_irqsave(&clock_lock, flags); + list_for_each_entry(c, &clocks, node) { + if (strcmp(c->name, name) == 0) { + ret = c; + break; + } + } + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} + +int clk_reparent(struct clk *c, struct clk *parent) +{ + pr_debug("%s: %s\n", __func__, c->name); + if (c->refcnt && c->parent) + clk_disable_locked(c->parent); + c->parent = parent; + if (c->refcnt && c->parent) + clk_enable_locked(c->parent); + list_del(&c->sibling); + list_add_tail(&c->sibling, &parent->children); + return 0; +} + +static void propagate_rate(struct clk *c) +{ + struct clk *clkp; + pr_debug("%s: %s\n", __func__, c->name); + list_for_each_entry(clkp, &c->children, sibling) { + pr_debug(" %s\n", clkp->name); + if (clkp->ops->recalculate_rate) + clkp->ops->recalculate_rate(clkp); + propagate_rate(clkp); + } +} + +void clk_init(struct clk *c) +{ + unsigned long flags; + + spin_lock_irqsave(&clock_lock, flags); + + INIT_LIST_HEAD(&c->children); + INIT_LIST_HEAD(&c->sibling); + + if (c->ops && c->ops->init) + c->ops->init(c); + + list_add(&c->node, &clocks); + + if (c->parent) + list_add_tail(&c->sibling, &c->parent->children); + + spin_unlock_irqrestore(&clock_lock, flags); +} + +int clk_enable_locked(struct clk *c) +{ + int ret; + pr_debug("%s: %s\n", __func__, c->name); + if (c->refcnt == 0) { + if (c->parent) { + ret = clk_enable_locked(c->parent); + if (ret) + return ret; + } + + if (c->ops && c->ops->enable) { + ret = c->ops->enable(c); + if (ret) { + if (c->parent) + clk_disable_locked(c->parent); + return ret; + } + c->state = ON; +#ifdef CONFIG_DEBUG_FS + c->set = 1; +#endif + } + } + c->refcnt++; + + return 0; +} + +int clk_enable(struct clk *c) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(&clock_lock, flags); + ret = clk_enable_locked(c); + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable_locked(struct clk *c) +{ + pr_debug("%s: %s\n", __func__, c->name); + if (c->refcnt == 0) { + WARN(1, "Attempting to disable clock %s with refcnt 0", c->name); + return; + } + if (c->refcnt == 1) { + if (c->ops && c->ops->disable) + c->ops->disable(c); + + if (c->parent) + clk_disable_locked(c->parent); + + c->state = OFF; + } + c->refcnt--; +} + +void clk_disable(struct clk *c) +{ + unsigned long flags; + spin_lock_irqsave(&clock_lock, flags); + clk_disable_locked(c); + spin_unlock_irqrestore(&clock_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +int clk_set_parent_locked(struct clk *c, struct clk *parent) +{ + int ret; + + pr_debug("%s: %s\n", __func__, c->name); + + if (!c->ops || !c->ops->set_parent) + return -ENOSYS; + + ret = c->ops->set_parent(c, parent); + + if (ret) + return ret; + + propagate_rate(c); + + return 0; +} + +int clk_set_parent(struct clk *c, struct clk *parent) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(&clock_lock, flags); + ret = clk_set_parent_locked(c, parent); + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *c) +{ + return c->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&clock_lock, flags); + + pr_debug("%s: %s\n", __func__, c->name); + + if (c->ops && c->ops->set_rate) + ret = c->ops->set_rate(c, rate); + else + ret = -ENOSYS; + + propagate_rate(c); + + spin_unlock_irqrestore(&clock_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +unsigned long clk_get_rate(struct clk *c) +{ + unsigned long flags; + unsigned long ret; + + spin_lock_irqsave(&clock_lock, flags); + + pr_debug("%s: %s\n", __func__, c->name); + + ret = c->rate; + + spin_unlock_irqrestore(&clock_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_get_rate); + +static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table) +{ + struct clk *c; + struct clk *p; + + int ret = 0; + + c = tegra_get_clock_by_name(table->name); + + if (!c) { + pr_warning("Unable to initialize clock %s\n", + table->name); + return -ENODEV; + } + + if (table->parent) { + p = tegra_get_clock_by_name(table->parent); + if (!p) { + pr_warning("Unable to find parent %s of clock %s\n", + table->parent, table->name); + return -ENODEV; + } + + if (c->parent != p) { + ret = clk_set_parent(c, p); + if (ret) { + pr_warning("Unable to set parent %s of clock %s: %d\n", + table->parent, table->name, ret); + return -EINVAL; + } + } + } + + if (table->rate && table->rate != clk_get_rate(c)) { + ret = clk_set_rate(c, table->rate); + if (ret) { + pr_warning("Unable to set clock %s to rate %lu: %d\n", + table->name, table->rate, ret); + return -EINVAL; + } + } + + if (table->enabled) { + ret = clk_enable(c); + if (ret) { + pr_warning("Unable to enable clock %s: %d\n", + table->name, ret); + return -EINVAL; + } + } + + return 0; +} + +void tegra_clk_init_from_table(struct tegra_clk_init_table *table) +{ + for (; table->name; table++) + tegra_clk_init_one_from_table(table); +} +EXPORT_SYMBOL(tegra_clk_init_from_table); + +void tegra_periph_reset_deassert(struct clk *c) +{ + tegra2_periph_reset_deassert(c); +} +EXPORT_SYMBOL(tegra_periph_reset_deassert); + +void tegra_periph_reset_assert(struct clk *c) +{ + tegra2_periph_reset_assert(c); +} +EXPORT_SYMBOL(tegra_periph_reset_assert); + +int __init tegra_init_clock(void) +{ + tegra2_init_clocks(); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static struct dentry *clk_debugfs_root; + + +static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level) +{ + struct clk *child; + struct clk *safe; + const char *state = "uninit"; + char div[5] = {0}; + + if (c->state == ON) + state = "on"; + else if (c->state == OFF) + state = "off"; + + if (c->mul != 0 && c->div != 0) { + BUG_ON(c->mul > 2); + if (c->mul > c->div) + snprintf(div, sizeof(div), "x%d", c->mul / c->div); + else + snprintf(div, sizeof(div), "%d%s", c->div / c->mul, + (c->div % c->mul) ? ".5" : ""); + } + + seq_printf(s, "%*s%-*s %-6s %-3d %-5s %-10lu\n", + level * 3 + 1, c->set ? "" : "*", + 30 - level * 3, c->name, + state, c->refcnt, div, c->rate); + list_for_each_entry_safe(child, safe, &c->children, sibling) { + clock_tree_show_one(s, child, level + 1); + } +} + +static int clock_tree_show(struct seq_file *s, void *data) +{ + struct clk *c; + unsigned long flags; + seq_printf(s, " clock state ref div rate \n"); + seq_printf(s, "-----------------------------------------------------------\n"); + spin_lock_irqsave(&clock_lock, flags); + list_for_each_entry(c, &clocks, node) + if (c->parent == NULL) + clock_tree_show_one(s, c, 0); + spin_unlock_irqrestore(&clock_lock, flags); + return 0; +} + +static int clock_tree_open(struct inode *inode, struct file *file) +{ + return single_open(file, clock_tree_show, inode->i_private); +} + +static const struct file_operations clock_tree_fops = { + .open = clock_tree_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int possible_parents_show(struct seq_file *s, void *data) +{ + struct clk *c = s->private; + int i; + + for (i = 0; c->inputs[i].input; i++) { + char *first = (i == 0) ? "" : " "; + seq_printf(s, "%s%s", first, c->inputs[i].input->name); + } + seq_printf(s, "\n"); + return 0; +} + +static int possible_parents_open(struct inode *inode, struct file *file) +{ + return single_open(file, possible_parents_show, inode->i_private); +} + +static const struct file_operations possible_parents_fops = { + .open = possible_parents_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int clk_debugfs_register_one(struct clk *c) +{ + struct dentry *d, *child, *child_tmp; + + d = debugfs_create_dir(c->name, clk_debugfs_root); + if (!d) + return -ENOMEM; + c->dent = d; + + d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt); + if (!d) + goto err_out; + + d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); + if (!d) + goto err_out; + + d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); + if (!d) + goto err_out; + + if (c->inputs) { + d = debugfs_create_file("possible_parents", S_IRUGO, c->dent, + c, &possible_parents_fops); + if (!d) + goto err_out; + } + + return 0; + +err_out: + d = c->dent; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(c->dent); + return -ENOMEM; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->parent; + + if (pa && !pa->dent) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (!c->dent) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err = -ENOMEM; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL, + &clock_tree_fops); + if (!d) + goto err_out; + + list_for_each_entry(c, &clocks, node) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} + +late_initcall(clk_debugfs_init); +#endif diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h new file mode 100644 index 00000000000..af7c70e2a3b --- /dev/null +++ b/arch/arm/mach-tegra/clock.h @@ -0,0 +1,147 @@ +/* + * arch/arm/mach-tegra/include/mach/clock.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_CLOCK_H +#define __MACH_TEGRA_CLOCK_H + +#include <linux/list.h> +#include <asm/clkdev.h> + +#define DIV_BUS (1 << 0) +#define DIV_U71 (1 << 1) +#define DIV_U71_FIXED (1 << 2) +#define DIV_2 (1 << 3) +#define PLL_FIXED (1 << 4) +#define PLL_HAS_CPCON (1 << 5) +#define MUX (1 << 6) +#define PLLD (1 << 7) +#define PERIPH_NO_RESET (1 << 8) +#define PERIPH_NO_ENB (1 << 9) +#define PERIPH_EMC_ENB (1 << 10) +#define PERIPH_MANUAL_RESET (1 << 11) +#define PLL_ALT_MISC_REG (1 << 12) +#define ENABLE_ON_INIT (1 << 28) + +struct clk; + +struct clk_mux_sel { + struct clk *input; + u32 value; +}; + +struct clk_pll_table { + unsigned long input_rate; + unsigned long output_rate; + u16 n; + u16 m; + u8 p; + u8 cpcon; +}; + +struct clk_ops { + void (*init)(struct clk *); + int (*enable)(struct clk *); + void (*disable)(struct clk *); + void (*recalc)(struct clk *); + int (*set_parent)(struct clk *, struct clk *); + int (*set_rate)(struct clk *, unsigned long); + unsigned long (*get_rate)(struct clk *); + long (*round_rate)(struct clk *, unsigned long); + unsigned long (*recalculate_rate)(struct clk *); +}; + +enum clk_state { + UNINITIALIZED = 0, + ON, + OFF, +}; + +struct clk { + /* node for master clocks list */ + struct list_head node; + struct list_head children; /* list of children */ + struct list_head sibling; /* node for children */ +#ifdef CONFIG_DEBUG_FS + struct dentry *dent; + struct dentry *parent_dent; +#endif + struct clk_ops *ops; + struct clk *parent; + struct clk_lookup lookup; + unsigned long rate; + u32 flags; + u32 refcnt; + const char *name; + u32 reg; + u32 reg_shift; + unsigned int clk_num; + enum clk_state state; +#ifdef CONFIG_DEBUG_FS + bool set; +#endif + + /* PLL */ + unsigned long input_min; + unsigned long input_max; + unsigned long cf_min; + unsigned long cf_max; + unsigned long vco_min; + unsigned long vco_max; + u32 m; + u32 n; + u32 p; + u32 cpcon; + const struct clk_pll_table *pll_table; + + /* DIV */ + u32 div; + u32 mul; + + /* MUX */ + const struct clk_mux_sel *inputs; + u32 sel; + u32 reg_mask; +}; + + +struct clk_duplicate { + const char *name; + struct clk_lookup lookup; +}; + +struct tegra_clk_init_table { + const char *name; + const char *parent; + unsigned long rate; + bool enabled; +}; + +void tegra2_init_clocks(void); +void tegra2_periph_reset_deassert(struct clk *c); +void tegra2_periph_reset_assert(struct clk *c); +void clk_init(struct clk *clk); +struct clk *tegra_get_clock_by_name(const char *name); +unsigned long clk_measure_input_freq(void); +void clk_disable_locked(struct clk *c); +int clk_enable_locked(struct clk *c); +int clk_set_parent_locked(struct clk *c, struct clk *parent); +int clk_reparent(struct clk *c, struct clk *parent); +void tegra_clk_init_from_table(struct tegra_clk_init_table *table); + +#endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c new file mode 100644 index 00000000000..039a514b61e --- /dev/null +++ b/arch/arm/mach-tegra/common.c @@ -0,0 +1,61 @@ +/* + * arch/arm/mach-tegra/board-harmony.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/hardware/cache-l2x0.h> + +#include <mach/iomap.h> + +#include "board.h" +#include "clock.h" + +static __initdata struct tegra_clk_init_table common_clk_init_table[] = { + /* name parent rate enabled */ + { "clk_m", NULL, 0, true }, + { "pll_p", "clk_m", 216000000, true }, + { "pll_p_out1", "pll_p", 28800000, true }, + { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out3", "pll_p", 72000000, true }, + { "pll_p_out4", "pll_p", 108000000, true }, + { "sys", "pll_p_out4", 108000000, true }, + { "hclk", "sys", 108000000, true }, + { "pclk", "hclk", 54000000, true }, + { NULL, NULL, 0, 0}, +}; + +void __init tegra_init_cache(void) +{ +#ifdef CONFIG_CACHE_L2X0 + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + + writel(0x331, p + L2X0_TAG_LATENCY_CTRL); + writel(0x441, p + L2X0_DATA_LATENCY_CTRL); + + l2x0_init(p, 0x6C080001, 0x8200c3fe); +#endif +} + +void __init tegra_common_init(void) +{ + tegra_init_clock(); + tegra_clk_init_from_table(common_clk_init_table); + tegra_init_cache(); +} diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h new file mode 100644 index 00000000000..f28220a641b --- /dev/null +++ b/arch/arm/mach-tegra/gpio-names.h @@ -0,0 +1,247 @@ +/* + * arch/arm/mach-tegra/include/mach/gpio-names.h + * + * Copyright (c) 2010 Google, Inc + * + * Author: + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TEGRA_GPIO_NAMES_H +#define __MACH_TEGRA_GPIO_NAMES_H + +#define TEGRA_GPIO_PA0 0 +#define TEGRA_GPIO_PA1 1 +#define TEGRA_GPIO_PA2 2 +#define TEGRA_GPIO_PA3 3 +#define TEGRA_GPIO_PA4 4 +#define TEGRA_GPIO_PA5 5 +#define TEGRA_GPIO_PA6 6 +#define TEGRA_GPIO_PA7 7 +#define TEGRA_GPIO_PB0 8 +#define TEGRA_GPIO_PB1 9 +#define TEGRA_GPIO_PB2 10 +#define TEGRA_GPIO_PB3 11 +#define TEGRA_GPIO_PB4 12 +#define TEGRA_GPIO_PB5 13 +#define TEGRA_GPIO_PB6 14 +#define TEGRA_GPIO_PB7 15 +#define TEGRA_GPIO_PC0 16 +#define TEGRA_GPIO_PC1 17 +#define TEGRA_GPIO_PC2 18 +#define TEGRA_GPIO_PC3 19 +#define TEGRA_GPIO_PC4 20 +#define TEGRA_GPIO_PC5 21 +#define TEGRA_GPIO_PC6 22 +#define TEGRA_GPIO_PC7 23 +#define TEGRA_GPIO_PD0 24 +#define TEGRA_GPIO_PD1 25 +#define TEGRA_GPIO_PD2 26 +#define TEGRA_GPIO_PD3 27 +#define TEGRA_GPIO_PD4 28 +#define TEGRA_GPIO_PD5 29 +#define TEGRA_GPIO_PD6 30 +#define TEGRA_GPIO_PD7 31 +#define TEGRA_GPIO_PE0 32 +#define TEGRA_GPIO_PE1 33 +#define TEGRA_GPIO_PE2 34 +#define TEGRA_GPIO_PE3 35 +#define TEGRA_GPIO_PE4 36 +#define TEGRA_GPIO_PE5 37 +#define TEGRA_GPIO_PE6 38 +#define TEGRA_GPIO_PE7 39 +#define TEGRA_GPIO_PF0 40 +#define TEGRA_GPIO_PF1 41 +#define TEGRA_GPIO_PF2 42 +#define TEGRA_GPIO_PF3 43 +#define TEGRA_GPIO_PF4 44 +#define TEGRA_GPIO_PF5 45 +#define TEGRA_GPIO_PF6 46 +#define TEGRA_GPIO_PF7 47 +#define TEGRA_GPIO_PG0 48 +#define TEGRA_GPIO_PG1 49 +#define TEGRA_GPIO_PG2 50 +#define TEGRA_GPIO_PG3 51 +#define TEGRA_GPIO_PG4 52 +#define TEGRA_GPIO_PG5 53 +#define TEGRA_GPIO_PG6 54 +#define TEGRA_GPIO_PG7 55 +#define TEGRA_GPIO_PH0 56 +#define TEGRA_GPIO_PH1 57 +#define TEGRA_GPIO_PH2 58 +#define TEGRA_GPIO_PH3 59 +#define TEGRA_GPIO_PH4 60 +#define TEGRA_GPIO_PH5 61 +#define TEGRA_GPIO_PH6 62 +#define TEGRA_GPIO_PH7 63 +#define TEGRA_GPIO_PI0 64 +#define TEGRA_GPIO_PI1 65 +#define TEGRA_GPIO_PI2 66 +#define TEGRA_GPIO_PI3 67 +#define TEGRA_GPIO_PI4 68 +#define TEGRA_GPIO_PI5 69 +#define TEGRA_GPIO_PI6 70 +#define TEGRA_GPIO_PI7 71 +#define TEGRA_GPIO_PJ0 72 +#define TEGRA_GPIO_PJ1 73 +#define TEGRA_GPIO_PJ2 74 +#define TEGRA_GPIO_PJ3 75 +#define TEGRA_GPIO_PJ4 76 +#define TEGRA_GPIO_PJ5 77 +#define TEGRA_GPIO_PJ6 78 +#define TEGRA_GPIO_PJ7 79 +#define TEGRA_GPIO_PK0 80 +#define TEGRA_GPIO_PK1 81 +#define TEGRA_GPIO_PK2 82 +#define TEGRA_GPIO_PK3 83 +#define TEGRA_GPIO_PK4 84 +#define TEGRA_GPIO_PK5 85 +#define TEGRA_GPIO_PK6 86 +#define TEGRA_GPIO_PK7 87 +#define TEGRA_GPIO_PL0 88 +#define TEGRA_GPIO_PL1 89 +#define TEGRA_GPIO_PL2 90 +#define TEGRA_GPIO_PL3 91 +#define TEGRA_GPIO_PL4 92 +#define TEGRA_GPIO_PL5 93 +#define TEGRA_GPIO_PL6 94 +#define TEGRA_GPIO_PL7 95 +#define TEGRA_GPIO_PM0 96 +#define TEGRA_GPIO_PM1 97 +#define TEGRA_GPIO_PM2 98 +#define TEGRA_GPIO_PM3 99 +#define TEGRA_GPIO_PM4 100 +#define TEGRA_GPIO_PM5 101 +#define TEGRA_GPIO_PM6 102 +#define TEGRA_GPIO_PM7 103 +#define TEGRA_GPIO_PN0 104 +#define TEGRA_GPIO_PN1 105 +#define TEGRA_GPIO_PN2 106 +#define TEGRA_GPIO_PN3 107 +#define TEGRA_GPIO_PN4 108 +#define TEGRA_GPIO_PN5 109 +#define TEGRA_GPIO_PN6 110 +#define TEGRA_GPIO_PN7 111 +#define TEGRA_GPIO_PO0 112 +#define TEGRA_GPIO_PO1 113 +#define TEGRA_GPIO_PO2 114 +#define TEGRA_GPIO_PO3 115 +#define TEGRA_GPIO_PO4 116 +#define TEGRA_GPIO_PO5 117 +#define TEGRA_GPIO_PO6 118 +#define TEGRA_GPIO_PO7 119 +#define TEGRA_GPIO_PP0 120 +#define TEGRA_GPIO_PP1 121 +#define TEGRA_GPIO_PP2 122 +#define TEGRA_GPIO_PP3 123 +#define TEGRA_GPIO_PP4 124 +#define TEGRA_GPIO_PP5 125 +#define TEGRA_GPIO_PP6 126 +#define TEGRA_GPIO_PP7 127 +#define TEGRA_GPIO_PQ0 128 +#define TEGRA_GPIO_PQ1 129 +#define TEGRA_GPIO_PQ2 130 +#define TEGRA_GPIO_PQ3 131 +#define TEGRA_GPIO_PQ4 132 +#define TEGRA_GPIO_PQ5 133 +#define TEGRA_GPIO_PQ6 134 +#define TEGRA_GPIO_PQ7 135 +#define TEGRA_GPIO_PR0 136 +#define TEGRA_GPIO_PR1 137 +#define TEGRA_GPIO_PR2 138 +#define TEGRA_GPIO_PR3 139 +#define TEGRA_GPIO_PR4 140 +#define TEGRA_GPIO_PR5 141 +#define TEGRA_GPIO_PR6 142 +#define TEGRA_GPIO_PR7 143 +#define TEGRA_GPIO_PS0 144 +#define TEGRA_GPIO_PS1 145 +#define TEGRA_GPIO_PS2 146 +#define TEGRA_GPIO_PS3 147 +#define TEGRA_GPIO_PS4 148 +#define TEGRA_GPIO_PS5 149 +#define TEGRA_GPIO_PS6 150 +#define TEGRA_GPIO_PS7 151 +#define TEGRA_GPIO_PT0 152 +#define TEGRA_GPIO_PT1 153 +#define TEGRA_GPIO_PT2 154 +#define TEGRA_GPIO_PT3 155 +#define TEGRA_GPIO_PT4 156 +#define TEGRA_GPIO_PT5 157 +#define TEGRA_GPIO_PT6 158 +#define TEGRA_GPIO_PT7 159 +#define TEGRA_GPIO_PU0 160 +#define TEGRA_GPIO_PU1 161 +#define TEGRA_GPIO_PU2 162 +#define TEGRA_GPIO_PU3 163 +#define TEGRA_GPIO_PU4 164 +#define TEGRA_GPIO_PU5 165 +#define TEGRA_GPIO_PU6 166 +#define TEGRA_GPIO_PU7 167 +#define TEGRA_GPIO_PV0 168 +#define TEGRA_GPIO_PV1 169 +#define TEGRA_GPIO_PV2 170 +#define TEGRA_GPIO_PV3 171 +#define TEGRA_GPIO_PV4 172 +#define TEGRA_GPIO_PV5 173 +#define TEGRA_GPIO_PV6 174 +#define TEGRA_GPIO_PV7 175 +#define TEGRA_GPIO_PW0 176 +#define TEGRA_GPIO_PW1 177 +#define TEGRA_GPIO_PW2 178 +#define TEGRA_GPIO_PW3 179 +#define TEGRA_GPIO_PW4 180 +#define TEGRA_GPIO_PW5 181 +#define TEGRA_GPIO_PW6 182 +#define TEGRA_GPIO_PW7 183 +#define TEGRA_GPIO_PX0 184 +#define TEGRA_GPIO_PX1 185 +#define TEGRA_GPIO_PX2 186 +#define TEGRA_GPIO_PX3 187 +#define TEGRA_GPIO_PX4 188 +#define TEGRA_GPIO_PX5 189 +#define TEGRA_GPIO_PX6 190 +#define TEGRA_GPIO_PX7 191 +#define TEGRA_GPIO_PY0 192 +#define TEGRA_GPIO_PY1 193 +#define TEGRA_GPIO_PY2 194 +#define TEGRA_GPIO_PY3 195 +#define TEGRA_GPIO_PY4 196 +#define TEGRA_GPIO_PY5 197 +#define TEGRA_GPIO_PY6 198 +#define TEGRA_GPIO_PY7 199 +#define TEGRA_GPIO_PZ0 200 +#define TEGRA_GPIO_PZ1 201 +#define TEGRA_GPIO_PZ2 202 +#define TEGRA_GPIO_PZ3 203 +#define TEGRA_GPIO_PZ4 204 +#define TEGRA_GPIO_PZ5 205 +#define TEGRA_GPIO_PZ6 206 +#define TEGRA_GPIO_PZ7 207 +#define TEGRA_GPIO_PAA0 208 +#define TEGRA_GPIO_PAA1 209 +#define TEGRA_GPIO_PAA2 210 +#define TEGRA_GPIO_PAA3 211 +#define TEGRA_GPIO_PAA4 212 +#define TEGRA_GPIO_PAA5 213 +#define TEGRA_GPIO_PAA6 214 +#define TEGRA_GPIO_PAA7 215 +#define TEGRA_GPIO_PBB0 216 +#define TEGRA_GPIO_PBB1 217 +#define TEGRA_GPIO_PBB2 218 +#define TEGRA_GPIO_PBB3 219 +#define TEGRA_GPIO_PBB4 220 +#define TEGRA_GPIO_PBB5 221 +#define TEGRA_GPIO_PBB6 222 +#define TEGRA_GPIO_PBB7 223 + +#endif diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c new file mode 100644 index 00000000000..fe78fba25f3 --- /dev/null +++ b/arch/arm/mach-tegra/gpio.c @@ -0,0 +1,348 @@ +/* + * arch/arm/mach-tegra/gpio.c + * + * Copyright (c) 2010 Google, Inc + * + * Author: + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/irq.h> + +#include <linux/io.h> +#include <linux/gpio.h> + +#include <mach/iomap.h> + +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_BIT(x) ((x) & 0x7) + +#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \ + GPIO_BANK(x) * 0x80 + \ + GPIO_PORT(x) * 4) + +#define GPIO_CNF(x) (GPIO_REG(x) + 0x00) +#define GPIO_OE(x) (GPIO_REG(x) + 0x10) +#define GPIO_OUT(x) (GPIO_REG(x) + 0X20) +#define GPIO_IN(x) (GPIO_REG(x) + 0x30) +#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) +#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) +#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) +#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) + +#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) +#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) +#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) +#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) +#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) +#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) + +#define GPIO_INT_LVL_MASK 0x010101 +#define GPIO_INT_LVL_EDGE_RISING 0x000101 +#define GPIO_INT_LVL_EDGE_FALLING 0x000100 +#define GPIO_INT_LVL_EDGE_BOTH 0x010100 +#define GPIO_INT_LVL_LEVEL_HIGH 0x000001 +#define GPIO_INT_LVL_LEVEL_LOW 0x000000 + +struct tegra_gpio_bank { + int bank; + int irq; + spinlock_t lvl_lock[4]; +}; + + +static struct tegra_gpio_bank tegra_gpio_banks[] = { + {.bank = 0, .irq = INT_GPIO1}, + {.bank = 1, .irq = INT_GPIO2}, + {.bank = 2, .irq = INT_GPIO3}, + {.bank = 3, .irq = INT_GPIO4}, + {.bank = 4, .irq = INT_GPIO5}, + {.bank = 5, .irq = INT_GPIO6}, + {.bank = 6, .irq = INT_GPIO7}, +}; + +static int tegra_gpio_compose(int bank, int port, int bit) +{ + return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); +} + +static void tegra_gpio_mask_write(u32 reg, int gpio, int value) +{ + u32 val; + + val = 0x100 << GPIO_BIT(gpio); + if (value) + val |= 1 << GPIO_BIT(gpio); + __raw_writel(val, reg); +} + +void tegra_gpio_enable(int gpio) +{ + tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); +} + +void tegra_gpio_disable(int gpio) +{ + tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); +} + +static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); +} + +static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; +} + +static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); + return 0; +} + +static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + tegra_gpio_set(chip, offset, value); + tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); + return 0; +} + + + +static struct gpio_chip tegra_gpio_chip = { + .label = "tegra-gpio", + .direction_input = tegra_gpio_direction_input, + .get = tegra_gpio_get, + .direction_output = tegra_gpio_direction_output, + .set = tegra_gpio_set, + .base = 0, + .ngpio = ARCH_NR_GPIOS, +}; + +static void tegra_gpio_irq_ack(unsigned int irq) +{ + int gpio = irq - INT_GPIO_BASE; + + __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); +} + +static void tegra_gpio_irq_mask(unsigned int irq) +{ + int gpio = irq - INT_GPIO_BASE; + + tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); +} + +static void tegra_gpio_irq_unmask(unsigned int irq) +{ + int gpio = irq - INT_GPIO_BASE; + + tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); +} + +static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type) +{ + int gpio = irq - INT_GPIO_BASE; + struct tegra_gpio_bank *bank = get_irq_chip_data(irq); + int port = GPIO_PORT(gpio); + int lvl_type; + int val; + unsigned long flags; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + lvl_type = GPIO_INT_LVL_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + lvl_type = GPIO_INT_LVL_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_BOTH: + lvl_type = GPIO_INT_LVL_EDGE_BOTH; + break; + + case IRQ_TYPE_LEVEL_HIGH: + lvl_type = GPIO_INT_LVL_LEVEL_HIGH; + break; + + case IRQ_TYPE_LEVEL_LOW: + lvl_type = GPIO_INT_LVL_LEVEL_LOW; + break; + + default: + return -EINVAL; + } + + spin_lock_irqsave(&bank->lvl_lock[port], flags); + + val = __raw_readl(GPIO_INT_LVL(gpio)); + val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); + val |= lvl_type << GPIO_BIT(gpio); + __raw_writel(val, GPIO_INT_LVL(gpio)); + + spin_unlock_irqrestore(&bank->lvl_lock[port], flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __set_irq_handler_unlocked(irq, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + __set_irq_handler_unlocked(irq, handle_edge_irq); + + return 0; +} + +static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct tegra_gpio_bank *bank; + int port; + int pin; + int unmasked = 0; + + desc->chip->ack(irq); + + bank = get_irq_data(irq); + + for (port = 0; port < 4; port++) { + int gpio = tegra_gpio_compose(bank->bank, port, 0); + unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) & + __raw_readl(GPIO_INT_ENB(gpio)); + u32 lvl = __raw_readl(GPIO_INT_LVL(gpio)); + + for_each_set_bit(pin, &sta, 8) { + __raw_writel(1 << pin, GPIO_INT_CLR(gpio)); + + /* if gpio is edge triggered, clear condition + * before executing the hander so that we don't + * miss edges + */ + if (lvl & (0x100 << pin)) { + unmasked = 1; + desc->chip->unmask(irq); + } + + generic_handle_irq(gpio_to_irq(gpio + pin)); + } + } + + if (!unmasked) + desc->chip->unmask(irq); + +} + + +static struct irq_chip tegra_gpio_irq_chip = { + .name = "GPIO", + .ack = tegra_gpio_irq_ack, + .mask = tegra_gpio_irq_mask, + .unmask = tegra_gpio_irq_unmask, + .set_type = tegra_gpio_irq_set_type, +}; + + +/* This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + +static int __init tegra_gpio_init(void) +{ + struct tegra_gpio_bank *bank; + int i; + int j; + + for (i = 0; i < 7; i++) { + for (j = 0; j < 4; j++) { + int gpio = tegra_gpio_compose(i, j, 0); + __raw_writel(0x00, GPIO_INT_ENB(gpio)); + } + } + + gpiochip_add(&tegra_gpio_chip); + + for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) { + bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; + + lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); + set_irq_chip_data(i, bank); + set_irq_chip(i, &tegra_gpio_irq_chip); + set_irq_handler(i, handle_simple_irq); + set_irq_flags(i, IRQF_VALID); + } + + for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { + bank = &tegra_gpio_banks[i]; + + set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); + set_irq_data(bank->irq, bank); + + for (j = 0; j < 4; j++) + spin_lock_init(&bank->lvl_lock[j]); + } + + return 0; +} + +postcore_initcall(tegra_gpio_init); + +#ifdef CONFIG_DEBUG_FS + +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +static int dbg_gpio_show(struct seq_file *s, void *unused) +{ + int i; + int j; + + for (i = 0; i < 7; i++) { + for (j = 0; j < 4; j++) { + int gpio = tegra_gpio_compose(i, j, 0); + seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", + i, j, + __raw_readl(GPIO_CNF(gpio)), + __raw_readl(GPIO_OE(gpio)), + __raw_readl(GPIO_OUT(gpio)), + __raw_readl(GPIO_IN(gpio)), + __raw_readl(GPIO_INT_STA(gpio)), + __raw_readl(GPIO_INT_ENB(gpio)), + __raw_readl(GPIO_INT_LVL(gpio))); + } + } + return 0; +} + +static int dbg_gpio_open(struct inode *inode, struct file *file) +{ + return single_open(file, dbg_gpio_show, &inode->i_private); +} + +static const struct file_operations debug_fops = { + .open = dbg_gpio_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init tegra_gpio_debuginit(void) +{ + (void) debugfs_create_file("tegra_gpio", S_IRUGO, + NULL, NULL, &debug_fops); + return 0; +} +late_initcall(tegra_gpio_debuginit); +#endif diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S new file mode 100644 index 00000000000..b5349b2f13d --- /dev/null +++ b/arch/arm/mach-tegra/headsmp.S @@ -0,0 +1,61 @@ +#include <linux/linkage.h> +#include <linux/init.h> + + .section ".text.head", "ax" + __CPUINIT + +/* + * Tegra specific entry point for secondary CPUs. + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +ENTRY(tegra_secondary_startup) + msr cpsr_fsxc, #0xd3 + bl v7_invalidate_l1 + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + ldr r1, =0x6000f100 + str r0, [r1] +1: ldr r2, [r1] + cmp r0, r2 + beq 1b + b secondary_startup +ENDPROC(tegra_secondary_startup) diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c new file mode 100644 index 00000000000..8e7f115aa21 --- /dev/null +++ b/arch/arm/mach-tegra/hotplug.c @@ -0,0 +1,140 @@ +/* + * linux/arch/arm/mach-realview/hotplug.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <linux/completion.h> + +#include <asm/cacheflush.h> + +static DECLARE_COMPLETION(cpu_killed); + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0) + : "cc"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + + /*if (pen_release == cpu) {*/ + /* + * OK, proper wakeup, we're done + */ + break; + /*}*/ + + /* + * getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * The trouble is, letting people know about this is not really + * possible, since we are currently running incoherently, and + * therefore cannot safely call printk() or anything else + */ +#ifdef DEBUG + printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu); +#endif + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ +#ifdef DEBUG + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } +#endif + + printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h new file mode 100644 index 00000000000..cc115174899 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/barriers.h @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-realview/include/mach/barriers.h + * + * Copyright (C) 2010 ARM Ltd. + * Written by Catalin Marinas <catalin.marinas@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MACH_BARRIERS_H +#define __MACH_BARRIERS_H + +#include <asm/outercache.h> + +#define rmb() dmb() +#define wmb() do { dsb(); outer_sync(); } while (0) +#define mb() wmb() + +#endif /* __MACH_BARRIERS_H */ diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h new file mode 100644 index 00000000000..2896f25ebfb --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/clk.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-tegra/include/mach/clk.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLK_H +#define __MACH_CLK_H + +void tegra_periph_reset_deassert(struct clk *c); +void tegra_periph_reset_assert(struct clk *c); + +#endif diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h new file mode 100644 index 00000000000..412f5c63e65 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/clkdev.h @@ -0,0 +1,32 @@ +/* + * arch/arm/mach-tegra/include/mach/clkdev.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S new file mode 100644 index 00000000000..55a39564b43 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/debug-macro.S @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-tegra/include/mach/debug-macro.S + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <mach/io.h> + + .macro addruart,rx, tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =IO_APB_PHYS @ physical + ldrne \rx, =IO_APB_VIRT @ virtual +#if defined(CONFIG_TEGRA_DEBUG_UART_NONE) +#error "A debug UART must be selected in the kernel config to use DEBUG_LL" +#elif defined(CONFIG_TEGRA_DEBUG_UARTA) + orr \rx, \rx, #0x6000 +#elif defined(CONFIG_TEGRA_DEBUG_UARTB) + ldr \tmp, =0x6040 + orr \rx, \rx, \tmp +#elif defined(CONFIG_TEGRA_DEBUG_UARTC) + orr \rx, \rx, #0x6200 +#elif defined(CONFIG_TEGRA_DEBUG_UARTD) + orr \rx, \rx, #0x6300 +#elif defined(CONFIG_TEGRA_DEBUG_UARTE) + orr \rx, \rx, #0x6400 +#endif + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> + diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S new file mode 100644 index 00000000000..2ba9e5c9d2f --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/entry-macro.S @@ -0,0 +1,118 @@ +/* arch/arm/mach-tegra/include/mach/entry-macro.S + * + * Copyright (C) 2009 Palm, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <mach/iomap.h> +#include <mach/io.h> + +#if defined(CONFIG_ARM_GIC) + +#include <asm/hardware/gic.h> + + /* Uses the GIC interrupt controller built into the cpu */ +#define ICTRL_BASE (IO_CPU_VIRT + 0x100) + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + movw \base, #(ICTRL_BASE & 0x0000ffff) + movt \base, #((ICTRL_BASE & 0xffff0000) >> 16) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an interrupt + * if it's between 30 and 1020. The test_for_ipi routine below will + * pick up on IPIs. + * + * A simple read from the controller will tell us the number of the + * highest priority enabled interrupt. We then just need to check + * whether it is in the valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + /* bits 12-10 = src CPU, 9-0 = int # */ + ldr \irqstat, [\base, #GIC_CPU_INTACK] + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm + +#else + /* legacy interrupt controller for AP16 */ + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + @ enable imprecise aborts + cpsie a + @ EVP base at 0xf010f000 + mov \base, #0xf0000000 + orr \base, #0x00100000 + orr \base, #0x0000f000 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS + cmp \irqnr, #0x80 + .endm +#endif diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h new file mode 100644 index 00000000000..540e822e50f --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/gpio.h @@ -0,0 +1,53 @@ +/* + * arch/arm/mach-tegra/include/mach/gpio.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_GPIO_H +#define __MACH_TEGRA_GPIO_H + +#include <mach/irqs.h> + +#define ARCH_NR_GPIOS INT_GPIO_NR + +#include <asm-generic/gpio.h> + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep + +#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio)) +#define TEGRA_IRQ_TO_GPIO(irq) ((gpio) - INT_GPIO_BASE) + +static inline int gpio_to_irq(unsigned int gpio) +{ + if (gpio < ARCH_NR_GPIOS) + return INT_GPIO_BASE + gpio; + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned int irq) +{ + if ((irq >= INT_GPIO_BASE) && (irq < INT_GPIO_BASE + INT_GPIO_NR)) + return irq - INT_GPIO_BASE; + return -EINVAL; +} + +void tegra_gpio_enable(int gpio); +void tegra_gpio_disable(int gpio); + +#endif diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h new file mode 100644 index 00000000000..6014edf60d9 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/hardware.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-tegra/include/mach/hardware.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_HARDWARE_H +#define __MACH_TEGRA_HARDWARE_H + +#endif diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h new file mode 100644 index 00000000000..35edfc32ffc --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/io.h @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-tegra/include/mach/io.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_IO_H +#define __MACH_TEGRA_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* On TEGRA, many peripherals are very closely packed in + * two 256MB io windows (that actually only use about 64KB + * at the start of each). + * + * We will just map the first 1MB of each window (to minimize + * pt entries needed) and provide a macro to transform physical + * io addresses to an appropriate void __iomem *. + * + */ + +#define IO_CPU_PHYS 0x50040000 +#define IO_CPU_VIRT 0xFE000000 +#define IO_CPU_SIZE SZ_16K + +#define IO_PPSB_PHYS 0x60000000 +#define IO_PPSB_VIRT 0xFE200000 +#define IO_PPSB_SIZE SZ_1M + +#define IO_APB_PHYS 0x70000000 +#define IO_APB_VIRT 0xFE300000 +#define IO_APB_SIZE SZ_1M + +#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) +#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) + +#define IO_TO_VIRT(n) ( \ + IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \ + IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \ + IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \ + IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \ + IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \ + IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \ + 0) + +#ifndef __ASSEMBLER__ + +#define __arch_ioremap(p, s, t) tegra_ioremap(p, s, t) +#define __arch_iounmap(v) tegra_iounmap(v) + +void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type); +void tegra_iounmap(volatile void __iomem *addr); + +#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n)) + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} +#define __io(a) __io(a) +#define __mem_pci(a) (a) + +#endif + +#endif diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h new file mode 100644 index 00000000000..1741f7dd7a9 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -0,0 +1,203 @@ +/* + * arch/arm/mach-tegra/include/mach/iomap.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_IOMAP_H +#define __MACH_TEGRA_IOMAP_H + +#include <asm/sizes.h> + +#define TEGRA_ARM_PERIF_BASE 0x50040000 +#define TEGRA_ARM_PERIF_SIZE SZ_8K + +#define TEGRA_ARM_INT_DIST_BASE 0x50041000 +#define TEGRA_ARM_INT_DIST_SIZE SZ_4K + +#define TEGRA_DISPLAY_BASE 0x54200000 +#define TEGRA_DISPLAY_SIZE SZ_256K + +#define TEGRA_DISPLAY2_BASE 0x54240000 +#define TEGRA_DISPLAY2_SIZE SZ_256K + +#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 +#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 + +#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 +#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64 + +#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 +#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64 + +#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 +#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 + +#define TEGRA_TMR1_BASE 0x60005000 +#define TEGRA_TMR1_SIZE SZ_8 + +#define TEGRA_TMR2_BASE 0x60005008 +#define TEGRA_TMR2_SIZE SZ_8 + +#define TEGRA_TMRUS_BASE 0x60005010 +#define TEGRA_TMRUS_SIZE SZ_64 + +#define TEGRA_TMR3_BASE 0x60005050 +#define TEGRA_TMR3_SIZE SZ_8 + +#define TEGRA_TMR4_BASE 0x60005058 +#define TEGRA_TMR4_SIZE SZ_8 + +#define TEGRA_CLK_RESET_BASE 0x60006000 +#define TEGRA_CLK_RESET_SIZE SZ_4K + +#define TEGRA_FLOW_CTRL_BASE 0x60007000 +#define TEGRA_FLOW_CTRL_SIZE 20 + +#define TEGRA_STATMON_BASE 0x6000C4000 +#define TEGRA_STATMON_SIZE SZ_1K + +#define TEGRA_GPIO_BASE 0x6000D000 +#define TEGRA_GPIO_SIZE SZ_4K + +#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 +#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K + +#define TEGRA_APB_MISC_BASE 0x70000000 +#define TEGRA_APB_MISC_SIZE SZ_4K + +#define TEGRA_AC97_BASE 0x70002000 +#define TEGRA_AC97_SIZE SZ_512 + +#define TEGRA_SPDIF_BASE 0x70002400 +#define TEGRA_SPDIF_SIZE SZ_512 + +#define TEGRA_I2S1_BASE 0x70002800 +#define TEGRA_I2S1_SIZE SZ_256 + +#define TEGRA_I2S2_BASE 0x70002A00 +#define TEGRA_I2S2_SIZE SZ_256 + +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTA_SIZE SZ_64 + +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTB_SIZE SZ_64 + +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTC_SIZE SZ_256 + +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTD_SIZE SZ_256 + +#define TEGRA_UARTE_BASE 0x70006400 +#define TEGRA_UARTE_SIZE SZ_256 + +#define TEGRA_NAND_BASE 0x70008000 +#define TEGRA_NAND_SIZE SZ_256 + +#define TEGRA_HSMMC_BASE 0x70008500 +#define TEGRA_HSMMC_SIZE SZ_256 + +#define TEGRA_SNOR_BASE 0x70009000 +#define TEGRA_SNOR_SIZE SZ_4K + +#define TEGRA_PWFM_BASE 0x7000A000 +#define TEGRA_PWFM_SIZE SZ_256 + +#define TEGRA_MIPI_BASE 0x7000B000 +#define TEGRA_MIPI_SIZE SZ_256 + +#define TEGRA_I2C_BASE 0x7000C000 +#define TEGRA_I2C_SIZE SZ_256 + +#define TEGRA_TWC_BASE 0x7000C100 +#define TEGRA_TWC_SIZE SZ_256 + +#define TEGRA_SPI_BASE 0x7000C380 +#define TEGRA_SPI_SIZE 48 + +#define TEGRA_I2C2_BASE 0x7000C400 +#define TEGRA_I2C2_SIZE SZ_256 + +#define TEGRA_I2C3_BASE 0x7000C500 +#define TEGRA_I2C3_SIZE SZ_256 + +#define TEGRA_OWR_BASE 0x7000D000 +#define TEGRA_OWR_SIZE 80 + +#define TEGRA_DVC_BASE 0x7000D000 +#define TEGRA_DVC_SIZE SZ_512 + +#define TEGRA_SPI1_BASE 0x7000D400 +#define TEGRA_SPI1_SIZE SZ_512 + +#define TEGRA_SPI2_BASE 0x7000D600 +#define TEGRA_SPI2_SIZE SZ_512 + +#define TEGRA_SPI3_BASE 0x7000D800 +#define TEGRA_SPI3_SIZE SZ_512 + +#define TEGRA_SPI4_BASE 0x7000DA00 +#define TEGRA_SPI4_SIZE SZ_512 + +#define TEGRA_RTC_BASE 0x7000E000 +#define TEGRA_RTC_SIZE SZ_256 + +#define TEGRA_KBC_BASE 0x7000E200 +#define TEGRA_KBC_SIZE SZ_256 + +#define TEGRA_PMC_BASE 0x7000E400 +#define TEGRA_PMC_SIZE SZ_256 + +#define TEGRA_MC_BASE 0x7000F000 +#define TEGRA_MC_SIZE SZ_1K + +#define TEGRA_EMC_BASE 0x7000F400 +#define TEGRA_EMC_SIZE SZ_1K + +#define TEGRA_FUSE_BASE 0x7000F800 +#define TEGRA_FUSE_SIZE SZ_1K + +#define TEGRA_KFUSE_BASE 0x7000FC00 +#define TEGRA_KFUSE_SIZE SZ_1K + +#define TEGRA_CSITE_BASE 0x70040000 +#define TEGRA_CSITE_SIZE SZ_256K + +#define TEGRA_USB_BASE 0xC5000000 +#define TEGRA_USB_SIZE SZ_16K + +#define TEGRA_USB1_BASE 0xC5004000 +#define TEGRA_USB1_SIZE SZ_16K + +#define TEGRA_USB2_BASE 0xC5008000 +#define TEGRA_USB2_SIZE SZ_16K + +#define TEGRA_SDMMC1_BASE 0xC8000000 +#define TEGRA_SDMMC1_SIZE SZ_512 + +#define TEGRA_SDMMC2_BASE 0xC8000200 +#define TEGRA_SDMMC2_SIZE SZ_512 + +#define TEGRA_SDMMC3_BASE 0xC8000400 +#define TEGRA_SDMMC3_SIZE SZ_512 + +#define TEGRA_SDMMC4_BASE 0xC8000600 +#define TEGRA_SDMMC4_SIZE SZ_512 + +#endif diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h new file mode 100644 index 00000000000..20f640edaa0 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/irqs.h @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-tegra/include/mach/irqs.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_IRQS_H +#define __MACH_TEGRA_IRQS_H + +#define INT_GIC_BASE 0 + +#define IRQ_LOCALTIMER 29 + +/* Primary Interrupt Controller */ +#define INT_PRI_BASE (INT_GIC_BASE + 32) +#define INT_TMR1 (INT_PRI_BASE + 0) +#define INT_TMR2 (INT_PRI_BASE + 1) +#define INT_RTC (INT_PRI_BASE + 2) +#define INT_I2S2 (INT_PRI_BASE + 3) +#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4) +#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5) +#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6) +#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7) +#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8) +#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9) +#define INT_VDE_BSE_V (INT_PRI_BASE + 10) +#define INT_VDE_BSE_A (INT_PRI_BASE + 11) +#define INT_VDE_SXE (INT_PRI_BASE + 12) +#define INT_I2S1 (INT_PRI_BASE + 13) +#define INT_SDMMC1 (INT_PRI_BASE + 14) +#define INT_SDMMC2 (INT_PRI_BASE + 15) +#define INT_XIO (INT_PRI_BASE + 16) +#define INT_VDE (INT_PRI_BASE + 17) +#define INT_AVP_UCQ (INT_PRI_BASE + 18) +#define INT_SDMMC3 (INT_PRI_BASE + 19) +#define INT_USB (INT_PRI_BASE + 20) +#define INT_USB2 (INT_PRI_BASE + 21) +#define INT_PRI_RES_22 (INT_PRI_BASE + 22) +#define INT_EIDE (INT_PRI_BASE + 23) +#define INT_NANDFLASH (INT_PRI_BASE + 24) +#define INT_VCP (INT_PRI_BASE + 25) +#define INT_APB_DMA (INT_PRI_BASE + 26) +#define INT_AHB_DMA (INT_PRI_BASE + 27) +#define INT_GNT_0 (INT_PRI_BASE + 28) +#define INT_GNT_1 (INT_PRI_BASE + 29) +#define INT_OWR (INT_PRI_BASE + 30) +#define INT_SDMMC4 (INT_PRI_BASE + 31) + +/* Secondary Interrupt Controller */ +#define INT_SEC_BASE (INT_PRI_BASE + 32) +#define INT_GPIO1 (INT_SEC_BASE + 0) +#define INT_GPIO2 (INT_SEC_BASE + 1) +#define INT_GPIO3 (INT_SEC_BASE + 2) +#define INT_GPIO4 (INT_SEC_BASE + 3) +#define INT_UARTA (INT_SEC_BASE + 4) +#define INT_UARTB (INT_SEC_BASE + 5) +#define INT_I2C (INT_SEC_BASE + 6) +#define INT_SPI (INT_SEC_BASE + 7) +#define INT_TWC (INT_SEC_BASE + 8) +#define INT_TMR3 (INT_SEC_BASE + 9) +#define INT_TMR4 (INT_SEC_BASE + 10) +#define INT_FLOW_RSM0 (INT_SEC_BASE + 11) +#define INT_FLOW_RSM1 (INT_SEC_BASE + 12) +#define INT_SPDIF (INT_SEC_BASE + 13) +#define INT_UARTC (INT_SEC_BASE + 14) +#define INT_MIPI (INT_SEC_BASE + 15) +#define INT_EVENTA (INT_SEC_BASE + 16) +#define INT_EVENTB (INT_SEC_BASE + 17) +#define INT_EVENTC (INT_SEC_BASE + 18) +#define INT_EVENTD (INT_SEC_BASE + 19) +#define INT_VFIR (INT_SEC_BASE + 20) +#define INT_DVC (INT_SEC_BASE + 21) +#define INT_SYS_STATS_MON (INT_SEC_BASE + 22) +#define INT_GPIO5 (INT_SEC_BASE + 23) +#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24) +#define INT_CPU2_PMU_INTR (INT_SEC_BASE + 25) +#define INT_SEC_RES_26 (INT_SEC_BASE + 26) +#define INT_S_LINK1 (INT_SEC_BASE + 27) +#define INT_APB_DMA_COP (INT_SEC_BASE + 28) +#define INT_AHB_DMA_COP (INT_SEC_BASE + 29) +#define INT_DMA_TX (INT_SEC_BASE + 30) +#define INT_DMA_RX (INT_SEC_BASE + 31) + +/* Tertiary Interrupt Controller */ +#define INT_TRI_BASE (INT_SEC_BASE + 32) +#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0) +#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1) +#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2) +#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3) +#define INT_MPE_GENERAL (INT_TRI_BASE + 4) +#define INT_VI_GENERAL (INT_TRI_BASE + 5) +#define INT_EPP_GENERAL (INT_TRI_BASE + 6) +#define INT_ISP_GENERAL (INT_TRI_BASE + 7) +#define INT_2D_GENERAL (INT_TRI_BASE + 8) +#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9) +#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10) +#define INT_HDMI (INT_TRI_BASE + 11) +#define INT_TVO_GENERAL (INT_TRI_BASE + 12) +#define INT_MC_GENERAL (INT_TRI_BASE + 13) +#define INT_EMC_GENERAL (INT_TRI_BASE + 14) +#define INT_TRI_RES_15 (INT_TRI_BASE + 15) +#define INT_TRI_RES_16 (INT_TRI_BASE + 16) +#define INT_AC97 (INT_TRI_BASE + 17) +#define INT_SPI_2 (INT_TRI_BASE + 18) +#define INT_SPI_3 (INT_TRI_BASE + 19) +#define INT_I2C2 (INT_TRI_BASE + 20) +#define INT_KBC (INT_TRI_BASE + 21) +#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22) +#define INT_GPIO6 (INT_TRI_BASE + 23) +#define INT_TVDAC (INT_TRI_BASE + 24) +#define INT_GPIO7 (INT_TRI_BASE + 25) +#define INT_UARTD (INT_TRI_BASE + 26) +#define INT_UARTE (INT_TRI_BASE + 27) +#define INT_I2C3 (INT_TRI_BASE + 28) +#define INT_SPI_4 (INT_TRI_BASE + 29) +#define INT_TRI_RES_30 (INT_TRI_BASE + 30) +#define INT_SW_RESERVED (INT_TRI_BASE + 31) + +/* Quaternary Interrupt Controller */ +#define INT_QUAD_BASE (INT_TRI_BASE + 32) +#define INT_SNOR (INT_QUAD_BASE + 0) +#define INT_USB3 (INT_QUAD_BASE + 1) +#define INT_PCIE_INTR (INT_QUAD_BASE + 2) +#define INT_PCIE_MSI (INT_QUAD_BASE + 3) +#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4) +#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5) +#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6) +#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7) +#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8) +#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9) +#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10) +#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11) +#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12) +#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13) +#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14) +#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15) +#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16) +#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17) +#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18) +#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19) +#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20) +#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21) +#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22) +#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23) +#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24) +#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25) +#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26) +#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27) +#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28) +#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29) +#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30) +#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31) + +#define INT_GPIO_BASE (INT_QUAD_BASE + 32) +#define INT_GPIO_NR (28 * 8) + +#define NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR) + +#endif diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h new file mode 100644 index 00000000000..6151bab62af --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/memory.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-tegra/include/mach/memory.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_MEMORY_H +#define __MACH_TEGRA_MEMORY_H + +/* physical offset of RAM */ +#define PHYS_OFFSET UL(0) + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h new file mode 100644 index 00000000000..41c8ce5b7c2 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -0,0 +1,348 @@ +/* + * linux/arch/arm/mach-tegra/include/mach/pinmux.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_PINMUX_H +#define __MACH_TEGRA_PINMUX_H + +enum tegra_pingroup { + TEGRA_PINGROUP_ATA = 0, + TEGRA_PINGROUP_ATB, + TEGRA_PINGROUP_ATC, + TEGRA_PINGROUP_ATD, + TEGRA_PINGROUP_ATE, + TEGRA_PINGROUP_CDEV1, + TEGRA_PINGROUP_CDEV2, + TEGRA_PINGROUP_CRTP, + TEGRA_PINGROUP_CSUS, + TEGRA_PINGROUP_DAP1, + TEGRA_PINGROUP_DAP2, + TEGRA_PINGROUP_DAP3, + TEGRA_PINGROUP_DAP4, + TEGRA_PINGROUP_DDC, + TEGRA_PINGROUP_DTA, + TEGRA_PINGROUP_DTB, + TEGRA_PINGROUP_DTC, + TEGRA_PINGROUP_DTD, + TEGRA_PINGROUP_DTE, + TEGRA_PINGROUP_DTF, + TEGRA_PINGROUP_GMA, + TEGRA_PINGROUP_GMB, + TEGRA_PINGROUP_GMC, + TEGRA_PINGROUP_GMD, + TEGRA_PINGROUP_GME, + TEGRA_PINGROUP_GPU, + TEGRA_PINGROUP_GPU7, + TEGRA_PINGROUP_GPV, + TEGRA_PINGROUP_HDINT, + TEGRA_PINGROUP_I2CP, + TEGRA_PINGROUP_IRRX, + TEGRA_PINGROUP_IRTX, + TEGRA_PINGROUP_KBCA, + TEGRA_PINGROUP_KBCB, + TEGRA_PINGROUP_KBCC, + TEGRA_PINGROUP_KBCD, + TEGRA_PINGROUP_KBCE, + TEGRA_PINGROUP_KBCF, + TEGRA_PINGROUP_LCSN, + TEGRA_PINGROUP_LD0, + TEGRA_PINGROUP_LD1, + TEGRA_PINGROUP_LD10, + TEGRA_PINGROUP_LD11, + TEGRA_PINGROUP_LD12, + TEGRA_PINGROUP_LD13, + TEGRA_PINGROUP_LD14, + TEGRA_PINGROUP_LD15, + TEGRA_PINGROUP_LD16, + TEGRA_PINGROUP_LD17, + TEGRA_PINGROUP_LD2, + TEGRA_PINGROUP_LD3, + TEGRA_PINGROUP_LD4, + TEGRA_PINGROUP_LD5, + TEGRA_PINGROUP_LD6, + TEGRA_PINGROUP_LD7, + TEGRA_PINGROUP_LD8, + TEGRA_PINGROUP_LD9, + TEGRA_PINGROUP_LDC, + TEGRA_PINGROUP_LDI, + TEGRA_PINGROUP_LHP0, + TEGRA_PINGROUP_LHP1, + TEGRA_PINGROUP_LHP2, + TEGRA_PINGROUP_LHS, + TEGRA_PINGROUP_LM0, + TEGRA_PINGROUP_LM1, + TEGRA_PINGROUP_LPP, + TEGRA_PINGROUP_LPW0, + TEGRA_PINGROUP_LPW1, + TEGRA_PINGROUP_LPW2, + TEGRA_PINGROUP_LSC0, + TEGRA_PINGROUP_LSC1, + TEGRA_PINGROUP_LSCK, + TEGRA_PINGROUP_LSDA, + TEGRA_PINGROUP_LSDI, + TEGRA_PINGROUP_LSPI, + TEGRA_PINGROUP_LVP0, + TEGRA_PINGROUP_LVP1, + TEGRA_PINGROUP_LVS, + TEGRA_PINGROUP_OWC, + TEGRA_PINGROUP_PMC, + TEGRA_PINGROUP_PTA, + TEGRA_PINGROUP_RM, + TEGRA_PINGROUP_SDB, + TEGRA_PINGROUP_SDC, + TEGRA_PINGROUP_SDD, + TEGRA_PINGROUP_SDIO1, + TEGRA_PINGROUP_SLXA, + TEGRA_PINGROUP_SLXC, + TEGRA_PINGROUP_SLXD, + TEGRA_PINGROUP_SLXK, + TEGRA_PINGROUP_SPDI, + TEGRA_PINGROUP_SPDO, + TEGRA_PINGROUP_SPIA, + TEGRA_PINGROUP_SPIB, + TEGRA_PINGROUP_SPIC, + TEGRA_PINGROUP_SPID, + TEGRA_PINGROUP_SPIE, + TEGRA_PINGROUP_SPIF, + TEGRA_PINGROUP_SPIG, + TEGRA_PINGROUP_SPIH, + TEGRA_PINGROUP_UAA, + TEGRA_PINGROUP_UAB, + TEGRA_PINGROUP_UAC, + TEGRA_PINGROUP_UAD, + TEGRA_PINGROUP_UCA, + TEGRA_PINGROUP_UCB, + TEGRA_PINGROUP_UDA, + /* these pin groups only have pullup and pull down control */ + TEGRA_PINGROUP_CK32, + TEGRA_PINGROUP_DDRC, + TEGRA_PINGROUP_PMCA, + TEGRA_PINGROUP_PMCB, + TEGRA_PINGROUP_PMCC, + TEGRA_PINGROUP_PMCD, + TEGRA_PINGROUP_PMCE, + TEGRA_PINGROUP_XM2C, + TEGRA_PINGROUP_XM2D, + TEGRA_MAX_PINGROUP, +}; + +enum tegra_mux_func { + TEGRA_MUX_RSVD = 0x8000, + TEGRA_MUX_RSVD1 = 0x8000, + TEGRA_MUX_RSVD2 = 0x8001, + TEGRA_MUX_RSVD3 = 0x8002, + TEGRA_MUX_RSVD4 = 0x8003, + TEGRA_MUX_NONE = -1, + TEGRA_MUX_AHB_CLK, + TEGRA_MUX_APB_CLK, + TEGRA_MUX_AUDIO_SYNC, + TEGRA_MUX_CRT, + TEGRA_MUX_DAP1, + TEGRA_MUX_DAP2, + TEGRA_MUX_DAP3, + TEGRA_MUX_DAP4, + TEGRA_MUX_DAP5, + TEGRA_MUX_DISPLAYA, + TEGRA_MUX_DISPLAYB, + TEGRA_MUX_EMC_TEST0_DLL, + TEGRA_MUX_EMC_TEST1_DLL, + TEGRA_MUX_GMI, + TEGRA_MUX_GMI_INT, + TEGRA_MUX_HDMI, + TEGRA_MUX_I2C, + TEGRA_MUX_I2C2, + TEGRA_MUX_I2C3, + TEGRA_MUX_IDE, + TEGRA_MUX_IRDA, + TEGRA_MUX_KBC, + TEGRA_MUX_MIO, + TEGRA_MUX_MIPI_HS, + TEGRA_MUX_NAND, + TEGRA_MUX_OSC, + TEGRA_MUX_OWR, + TEGRA_MUX_PCIE, + TEGRA_MUX_PLLA_OUT, + TEGRA_MUX_PLLC_OUT1, + TEGRA_MUX_PLLM_OUT1, + TEGRA_MUX_PLLP_OUT2, + TEGRA_MUX_PLLP_OUT3, + TEGRA_MUX_PLLP_OUT4, + TEGRA_MUX_PWM, + TEGRA_MUX_PWR_INTR, + TEGRA_MUX_PWR_ON, + TEGRA_MUX_RTCK, + TEGRA_MUX_SDIO1, + TEGRA_MUX_SDIO2, + TEGRA_MUX_SDIO3, + TEGRA_MUX_SDIO4, + TEGRA_MUX_SFLASH, + TEGRA_MUX_SPDIF, + TEGRA_MUX_SPI1, + TEGRA_MUX_SPI2, + TEGRA_MUX_SPI2_ALT, + TEGRA_MUX_SPI3, + TEGRA_MUX_SPI4, + TEGRA_MUX_TRACE, + TEGRA_MUX_TWC, + TEGRA_MUX_UARTA, + TEGRA_MUX_UARTB, + TEGRA_MUX_UARTC, + TEGRA_MUX_UARTD, + TEGRA_MUX_UARTE, + TEGRA_MUX_ULPI, + TEGRA_MUX_VI, + TEGRA_MUX_VI_SENSOR_CLK, + TEGRA_MUX_XIO, + TEGRA_MAX_MUX, +}; + +enum tegra_pullupdown { + TEGRA_PUPD_NORMAL = 0, + TEGRA_PUPD_PULL_DOWN, + TEGRA_PUPD_PULL_UP, +}; + +enum tegra_tristate { + TEGRA_TRI_NORMAL = 0, + TEGRA_TRI_TRISTATE = 1, +}; + +struct tegra_pingroup_config { + enum tegra_pingroup pingroup; + enum tegra_mux_func func; + enum tegra_pullupdown pupd; + enum tegra_tristate tristate; +}; + +enum tegra_slew { + TEGRA_SLEW_FASTEST = 0, + TEGRA_SLEW_FAST, + TEGRA_SLEW_SLOW, + TEGRA_SLEW_SLOWEST, + TEGRA_MAX_SLEW, +}; + +enum tegra_pull_strength { + TEGRA_PULL_0 = 0, + TEGRA_PULL_1, + TEGRA_PULL_2, + TEGRA_PULL_3, + TEGRA_PULL_4, + TEGRA_PULL_5, + TEGRA_PULL_6, + TEGRA_PULL_7, + TEGRA_PULL_8, + TEGRA_PULL_9, + TEGRA_PULL_10, + TEGRA_PULL_11, + TEGRA_PULL_12, + TEGRA_PULL_13, + TEGRA_PULL_14, + TEGRA_PULL_15, + TEGRA_PULL_16, + TEGRA_PULL_17, + TEGRA_PULL_18, + TEGRA_PULL_19, + TEGRA_PULL_20, + TEGRA_PULL_21, + TEGRA_PULL_22, + TEGRA_PULL_23, + TEGRA_PULL_24, + TEGRA_PULL_25, + TEGRA_PULL_26, + TEGRA_PULL_27, + TEGRA_PULL_28, + TEGRA_PULL_29, + TEGRA_PULL_30, + TEGRA_PULL_31, + TEGRA_MAX_PULL, +}; + +enum tegra_drive_pingroup { + TEGRA_DRIVE_PINGROUP_AO1 = 0, + TEGRA_DRIVE_PINGROUP_AO2, + TEGRA_DRIVE_PINGROUP_AT1, + TEGRA_DRIVE_PINGROUP_AT2, + TEGRA_DRIVE_PINGROUP_CDEV1, + TEGRA_DRIVE_PINGROUP_CDEV2, + TEGRA_DRIVE_PINGROUP_CSUS, + TEGRA_DRIVE_PINGROUP_DAP1, + TEGRA_DRIVE_PINGROUP_DAP2, + TEGRA_DRIVE_PINGROUP_DAP3, + TEGRA_DRIVE_PINGROUP_DAP4, + TEGRA_DRIVE_PINGROUP_DBG, + TEGRA_DRIVE_PINGROUP_LCD1, + TEGRA_DRIVE_PINGROUP_LCD2, + TEGRA_DRIVE_PINGROUP_SDMMC2, + TEGRA_DRIVE_PINGROUP_SDMMC3, + TEGRA_DRIVE_PINGROUP_SPI, + TEGRA_DRIVE_PINGROUP_UAA, + TEGRA_DRIVE_PINGROUP_UAB, + TEGRA_DRIVE_PINGROUP_UART2, + TEGRA_DRIVE_PINGROUP_UART3, + TEGRA_DRIVE_PINGROUP_VI1, + TEGRA_DRIVE_PINGROUP_VI2, + TEGRA_DRIVE_PINGROUP_XM2A, + TEGRA_DRIVE_PINGROUP_XM2C, + TEGRA_DRIVE_PINGROUP_XM2D, + TEGRA_DRIVE_PINGROUP_XM2CLK, + TEGRA_DRIVE_PINGROUP_MEMCOMP, + TEGRA_MAX_DRIVE_PINGROUP, +}; + +enum tegra_drive { + TEGRA_DRIVE_DIV_8 = 0, + TEGRA_DRIVE_DIV_4, + TEGRA_DRIVE_DIV_2, + TEGRA_DRIVE_DIV_1, + TEGRA_MAX_DRIVE, +}; + +enum tegra_hsm { + TEGRA_HSM_DISABLE = 0, + TEGRA_HSM_ENABLE, +}; + +enum tegra_schmitt { + TEGRA_SCHMITT_DISABLE = 0, + TEGRA_SCHMITT_ENABLE, +}; + +struct tegra_drive_pingroup_config { + enum tegra_drive_pingroup pingroup; + enum tegra_hsm hsm; + enum tegra_schmitt schmitt; + enum tegra_drive drive; + enum tegra_pull_strength pull_down; + enum tegra_pull_strength pull_up; + enum tegra_slew slew_rising; + enum tegra_slew slew_falling; +}; + +int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func); +int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate); +int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd); + +void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, + enum tegra_mux_func func, enum tegra_pullupdown pupd, + enum tegra_tristate tristate); + +void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len); + +void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, + int len); + +#endif + diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h new file mode 100644 index 00000000000..8b42dab79a7 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/smp.h @@ -0,0 +1,30 @@ +#ifndef ASMARM_ARCH_SMP_H +#define ASMARM_ARCH_SMP_H + + +#include <asm/hardware/gic.h> + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} + +/* + * Do nothing on MPcore. + */ +static inline void smp_cross_call_done(cpumask_t callmap) +{ +} + +#endif diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h new file mode 100644 index 00000000000..84d5d46113f --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/system.h @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-tegra/include/mach/system.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_SYSTEM_H +#define __MACH_TEGRA_SYSTEM_H + +#include <mach/hardware.h> +#include <mach/iomap.h> + +static inline void arch_idle(void) +{ +} + +static inline void arch_reset(char mode, const char *cmd) +{ + void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); + u32 reg = readl(reset); + reg |= 0x04; + writel(reg, reset); +} + +#endif diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h new file mode 100644 index 00000000000..a44ccbdb7db --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/timex.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-tegra/include/mach/timex.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_TIMEX_H +#define __MACH_TEGRA_TIMEX_H + +#define CLOCK_TICK_RATE 1000000 + +#endif diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h new file mode 100644 index 00000000000..6c4dd815abd --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/uncompress.h @@ -0,0 +1,78 @@ +/* + * arch/arm/mach-tegra/include/mach/uncompress.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_UNCOMPRESS_H +#define __MACH_TEGRA_UNCOMPRESS_H + +#include <linux/types.h> +#include <linux/serial_reg.h> + +#include <mach/iomap.h> + +#if defined(CONFIG_TEGRA_DEBUG_UARTA) +#define DEBUG_UART_BASE TEGRA_UARTA_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTB) +#define DEBUG_UART_BASE TEGRA_UARTB_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTC) +#define DEBUG_UART_BASE TEGRA_UARTC_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTD) +#define DEBUG_UART_BASE TEGRA_UARTD_BASE +#elif defined(CONFIG_TEGRA_DEBUG_UARTE) +#define DEBUG_UART_BASE TEGRA_UARTE_BASE +#else +#define DEBUG_UART_BASE NULL +#endif + +static void putc(int c) +{ + volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE; + int shift = 2; + + if (uart == NULL) + return; + + while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) + barrier(); + uart[UART_TX << shift] = c; +} + +static inline void flush(void) +{ +} + +static inline void arch_decomp_setup(void) +{ + volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE; + int shift = 2; + + if (uart == NULL) + return; + + uart[UART_LCR << shift] |= UART_LCR_DLAB; + uart[UART_DLL << shift] = 0x75; + uart[UART_DLM << shift] = 0x0; + uart[UART_LCR << shift] = 3; +} + +static inline void arch_decomp_wdog(void) +{ +} + +#endif diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h new file mode 100644 index 00000000000..fd6aa65b2dc --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/vmalloc.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-tegra/include/mach/vmalloc.h + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_TEGRA_VMALLOC_H +#define __MACH_TEGRA_VMALLOC_H + +#include <asm/sizes.h> + +#define VMALLOC_END 0xFE000000UL + +#endif diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c new file mode 100644 index 00000000000..9fe2c5c683d --- /dev/null +++ b/arch/arm/mach-tegra/io.c @@ -0,0 +1,78 @@ +/* + * arch/arm/mach-tegra/io.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * Erik Gilling <konkers@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <asm/page.h> +#include <asm/mach/map.h> + +#include "board.h" + +static struct map_desc tegra_io_desc[] __initdata = { + { + .virtual = IO_PPSB_VIRT, + .pfn = __phys_to_pfn(IO_PPSB_PHYS), + .length = IO_PPSB_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = IO_APB_VIRT, + .pfn = __phys_to_pfn(IO_APB_PHYS), + .length = IO_APB_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = IO_CPU_VIRT, + .pfn = __phys_to_pfn(IO_CPU_PHYS), + .length = IO_CPU_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init tegra_map_common_io(void) +{ + iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc)); +} + +/* + * Intercept ioremap() requests for addresses in our fixed mapping regions. + */ +void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type) +{ + void __iomem *v = IO_ADDRESS(p); + if (v == NULL) + v = __arm_ioremap(p, size, type); + return v; +} +EXPORT_SYMBOL(tegra_ioremap); + +void tegra_iounmap(volatile void __iomem *addr) +{ + unsigned long virt = (unsigned long)addr; + + if (virt >= VMALLOC_START && virt < VMALLOC_END) + __iounmap(addr); +} +EXPORT_SYMBOL(tegra_iounmap); diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c new file mode 100644 index 00000000000..1fdbe708d43 --- /dev/null +++ b/arch/arm/mach-tegra/irq.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/hardware/gic.h> + +#include <mach/iomap.h> + +#include "board.h" + +void __init tegra_init_irq(void) +{ + gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29); + gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); +} diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c new file mode 100644 index 00000000000..f81ca7cbbc1 --- /dev/null +++ b/arch/arm/mach-tegra/localtimer.c @@ -0,0 +1,25 @@ +/* + * arch/arm/mach-tegra/localtimer.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/clockchips.h> +#include <asm/irq.h> +#include <asm/smp_twd.h> +#include <asm/localtimer.h> + +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + evt->irq = IRQ_LOCALTIMER; + twd_timer_setup(evt); +} diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c new file mode 100644 index 00000000000..13ae10237e8 --- /dev/null +++ b/arch/arm/mach-tegra/pinmux.c @@ -0,0 +1,945 @@ +/* + * linux/arch/arm/mach-tegra/pinmux.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/spinlock.h> +#include <linux/io.h> + +#include <mach/iomap.h> +#include <mach/pinmux.h> + + +#define TEGRA_TRI_STATE(x) (0x14 + (4 * (x))) +#define TEGRA_PP_MUX_CTL(x) (0x80 + (4 * (x))) +#define TEGRA_PP_PU_PD(x) (0xa0 + (4 * (x))) + +#define REG_A 0 +#define REG_B 1 +#define REG_C 2 +#define REG_D 3 +#define REG_E 4 +#define REG_F 5 +#define REG_G 6 + +#define REG_N -1 + +#define HSM_EN(reg) (((reg) >> 2) & 0x1) +#define SCHMT_EN(reg) (((reg) >> 3) & 0x1) +#define LPMD(reg) (((reg) >> 4) & 0x3) +#define DRVDN(reg) (((reg) >> 12) & 0x1f) +#define DRVUP(reg) (((reg) >> 20) & 0x1f) +#define SLWR(reg) (((reg) >> 28) & 0x3) +#define SLWF(reg) (((reg) >> 30) & 0x3) + +struct tegra_pingroup_desc { + const char *name; + int funcs[4]; + s8 tri_reg; /* offset into the TRISTATE_REG_* register bank */ + s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ + s8 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ + s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ + s8 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ + s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ +}; + +#define PINGROUP(pg_name, f0, f1, f2, f3, \ + tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \ + [TEGRA_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .funcs = { \ + TEGRA_MUX_ ## f0, \ + TEGRA_MUX_ ## f1, \ + TEGRA_MUX_ ## f2, \ + TEGRA_MUX_ ## f3, \ + }, \ + .tri_reg = REG_ ## tri_r, \ + .tri_bit = tri_b, \ + .mux_reg = REG_ ## mux_r, \ + .mux_bit = mux_b, \ + .pupd_reg = REG_ ## pupd_r, \ + .pupd_bit = pupd_b, \ + } + +static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = { + PINGROUP(ATA, IDE, NAND, GMI, RSVD, A, 0, A, 24, A, 0), + PINGROUP(ATB, IDE, NAND, GMI, SDIO4, A, 1, A, 16, A, 2), + PINGROUP(ATC, IDE, NAND, GMI, SDIO4, A, 2, A, 22, A, 4), + PINGROUP(ATD, IDE, NAND, GMI, SDIO4, A, 3, A, 20, A, 6), + PINGROUP(ATE, IDE, NAND, GMI, RSVD, B, 25, A, 12, A, 8), + PINGROUP(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, A, 4, C, 2, C, 0), + PINGROUP(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, A, 5, C, 4, C, 2), + PINGROUP(CRTP, CRT, RSVD, RSVD, RSVD, D, 14, G, 20, B, 24), + PINGROUP(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6, C, 6, D, 24), + PINGROUP(DAP1, DAP1, RSVD, GMI, SDIO2, A, 7, C, 20, A, 10), + PINGROUP(DAP2, DAP2, TWC, RSVD, GMI, A, 8, C, 22, A, 12), + PINGROUP(DAP3, DAP3, RSVD, RSVD, RSVD, A, 9, C, 24, A, 14), + PINGROUP(DAP4, DAP4, RSVD, GMI, RSVD, A, 10, C, 26, A, 16), + PINGROUP(DDC, I2C2, RSVD, RSVD, RSVD, B, 31, C, 0, E, 28), + PINGROUP(DTA, RSVD, SDIO2, VI, RSVD, A, 11, B, 20, A, 18), + PINGROUP(DTB, RSVD, RSVD, VI, SPI1, A, 12, B, 22, A, 20), + PINGROUP(DTC, RSVD, RSVD, VI, RSVD, A, 13, B, 26, A, 22), + PINGROUP(DTD, RSVD, SDIO2, VI, RSVD, A, 14, B, 28, A, 24), + PINGROUP(DTE, RSVD, RSVD, VI, SPI1, A, 15, B, 30, A, 26), + PINGROUP(DTF, I2C3, RSVD, VI, RSVD, D, 12, G, 30, A, 28), + PINGROUP(GMA, UARTE, SPI3, GMI, SDIO4, A, 28, B, 0, E, 20), + PINGROUP(GMB, IDE, NAND, GMI, GMI_INT, B, 29, C, 28, E, 22), + PINGROUP(GMC, UARTD, SPI4, GMI, SFLASH, A, 29, B, 2, E, 24), + PINGROUP(GMD, RSVD, NAND, GMI, SFLASH, B, 30, C, 30, E, 26), + PINGROUP(GME, RSVD, DAP5, GMI, SDIO4, B, 0, D, 0, C, 24), + PINGROUP(GPU, PWM, UARTA, GMI, RSVD, A, 16, D, 4, B, 20), + PINGROUP(GPU7, RTCK, RSVD, RSVD, RSVD, D, 11, G, 28, B, 6), + PINGROUP(GPV, PCIE, RSVD, RSVD, RSVD, A, 17, D, 2, A, 30), + PINGROUP(HDINT, HDMI, RSVD, RSVD, RSVD, C, 23, B, 4, D, 22), + PINGROUP(I2CP, I2C, RSVD, RSVD, RSVD, A, 18, C, 8, B, 2), + PINGROUP(IRRX, UARTA, UARTB, GMI, SPI4, A, 20, C, 18, C, 22), + PINGROUP(IRTX, UARTA, UARTB, GMI, SPI4, A, 19, C, 16, C, 20), + PINGROUP(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL, A, 22, C, 10, B, 8), + PINGROUP(KBCB, KBC, NAND, SDIO2, MIO, A, 21, C, 12, B, 10), + PINGROUP(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL, B, 26, C, 14, B, 12), + PINGROUP(KBCD, KBC, NAND, SDIO2, MIO, D, 10, G, 26, B, 14), + PINGROUP(KBCE, KBC, NAND, OWR, RSVD, A, 26, A, 28, E, 2), + PINGROUP(KBCF, KBC, NAND, TRACE, MIO, A, 27, A, 26, E, 0), + PINGROUP(LCSN, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 31, E, 12, D, 20), + PINGROUP(LD0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 0, F, 0, D, 12), + PINGROUP(LD1, DISPLAYA, DISPLAYB, XIO, RSVD, C, 1, F, 2, D, 12), + PINGROUP(LD10, DISPLAYA, DISPLAYB, XIO, RSVD, C, 10, F, 20, D, 12), + PINGROUP(LD11, DISPLAYA, DISPLAYB, XIO, RSVD, C, 11, F, 22, D, 12), + PINGROUP(LD12, DISPLAYA, DISPLAYB, XIO, RSVD, C, 12, F, 24, D, 12), + PINGROUP(LD13, DISPLAYA, DISPLAYB, XIO, RSVD, C, 13, F, 26, D, 12), + PINGROUP(LD14, DISPLAYA, DISPLAYB, XIO, RSVD, C, 14, F, 28, D, 12), + PINGROUP(LD15, DISPLAYA, DISPLAYB, XIO, RSVD, C, 15, F, 30, D, 12), + PINGROUP(LD16, DISPLAYA, DISPLAYB, XIO, RSVD, C, 16, G, 0, D, 12), + PINGROUP(LD17, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 17, G, 2, D, 12), + PINGROUP(LD2, DISPLAYA, DISPLAYB, XIO, RSVD, C, 2, F, 4, D, 12), + PINGROUP(LD3, DISPLAYA, DISPLAYB, XIO, RSVD, C, 3, F, 6, D, 12), + PINGROUP(LD4, DISPLAYA, DISPLAYB, XIO, RSVD, C, 4, F, 8, D, 12), + PINGROUP(LD5, DISPLAYA, DISPLAYB, XIO, RSVD, C, 5, F, 10, D, 12), + PINGROUP(LD6, DISPLAYA, DISPLAYB, XIO, RSVD, C, 6, F, 12, D, 12), + PINGROUP(LD7, DISPLAYA, DISPLAYB, XIO, RSVD, C, 7, F, 14, D, 12), + PINGROUP(LD8, DISPLAYA, DISPLAYB, XIO, RSVD, C, 8, F, 16, D, 12), + PINGROUP(LD9, DISPLAYA, DISPLAYB, XIO, RSVD, C, 9, F, 18, D, 12), + PINGROUP(LDC, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 30, E, 14, D, 20), + PINGROUP(LDI, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 6, G, 16, D, 18), + PINGROUP(LHP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 18, G, 10, D, 16), + PINGROUP(LHP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 19, G, 4, D, 14), + PINGROUP(LHP2, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 20, G, 6, D, 14), + PINGROUP(LHS, DISPLAYA, DISPLAYB, XIO, RSVD, D, 7, E, 22, D, 22), + PINGROUP(LM0, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 24, E, 26, D, 22), + PINGROUP(LM1, DISPLAYA, DISPLAYB, RSVD, CRT, C, 25, E, 28, D, 22), + PINGROUP(LPP, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 8, G, 14, D, 18), + PINGROUP(LPW0, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 3, E, 0, D, 20), + PINGROUP(LPW1, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 4, E, 2, D, 20), + PINGROUP(LPW2, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 5, E, 4, D, 20), + PINGROUP(LSC0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 27, E, 18, D, 22), + PINGROUP(LSC1, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 28, E, 20, D, 20), + PINGROUP(LSCK, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 29, E, 16, D, 20), + PINGROUP(LSDA, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 1, E, 8, D, 20), + PINGROUP(LSDI, DISPLAYA, DISPLAYB, SPI3, RSVD, D, 2, E, 6, D, 20), + PINGROUP(LSPI, DISPLAYA, DISPLAYB, XIO, HDMI, D, 0, E, 10, D, 22), + PINGROUP(LVP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 21, E, 30, D, 22), + PINGROUP(LVP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 22, G, 8, D, 16), + PINGROUP(LVS, DISPLAYA, DISPLAYB, XIO, RSVD, C, 26, E, 24, D, 22), + PINGROUP(OWC, OWR, RSVD, RSVD, RSVD, A, 31, B, 8, E, 30), + PINGROUP(PMC, PWR_ON, PWR_INTR, RSVD, RSVD, A, 23, G, 18, N, -1), + PINGROUP(PTA, I2C2, HDMI, GMI, RSVD, A, 24, G, 22, B, 4), + PINGROUP(RM, I2C, RSVD, RSVD, RSVD, A, 25, A, 14, B, 0), + PINGROUP(SDB, UARTA, PWM, SDIO3, SPI2, D, 15, D, 10, N, -1), + PINGROUP(SDC, PWM, TWC, SDIO3, SPI3, B, 1, D, 12, D, 28), + PINGROUP(SDD, UARTA, PWM, SDIO3, SPI3, B, 2, D, 14, D, 30), + PINGROUP(SDIO1, SDIO1, RSVD, UARTE, UARTA, A, 30, A, 30, E, 18), + PINGROUP(SLXA, PCIE, SPI4, SDIO3, SPI2, B, 3, B, 6, B, 22), + PINGROUP(SLXC, SPDIF, SPI4, SDIO3, SPI2, B, 5, B, 10, B, 26), + PINGROUP(SLXD, SPDIF, SPI4, SDIO3, SPI2, B, 6, B, 12, B, 28), + PINGROUP(SLXK, PCIE, SPI4, SDIO3, SPI2, B, 7, B, 14, B, 30), + PINGROUP(SPDI, SPDIF, RSVD, I2C, SDIO2, B, 8, D, 8, B, 16), + PINGROUP(SPDO, SPDIF, RSVD, I2C, SDIO2, B, 9, D, 6, B, 18), + PINGROUP(SPIA, SPI1, SPI2, SPI3, GMI, B, 10, D, 30, C, 4), + PINGROUP(SPIB, SPI1, SPI2, SPI3, GMI, B, 11, D, 28, C, 6), + PINGROUP(SPIC, SPI1, SPI2, SPI3, GMI, B, 12, D, 26, C, 8), + PINGROUP(SPID, SPI2, SPI1, SPI2_ALT, GMI, B, 13, D, 24, C, 10), + PINGROUP(SPIE, SPI2, SPI1, SPI2_ALT, GMI, B, 14, D, 22, C, 12), + PINGROUP(SPIF, SPI3, SPI1, SPI2, RSVD, B, 15, D, 20, C, 14), + PINGROUP(SPIG, SPI3, SPI2, SPI2_ALT, I2C, B, 16, D, 18, C, 16), + PINGROUP(SPIH, SPI3, SPI2, SPI2_ALT, I2C, B, 17, D, 16, C, 18), + PINGROUP(UAA, SPI3, MIPI_HS, UARTA, ULPI, B, 18, A, 0, D, 0), + PINGROUP(UAB, SPI2, MIPI_HS, UARTA, ULPI, B, 19, A, 2, D, 2), + PINGROUP(UAC, OWR, RSVD, RSVD, RSVD, B, 20, A, 4, D, 4), + PINGROUP(UAD, IRDA, SPDIF, UARTA, SPI4, B, 21, A, 6, D, 6), + PINGROUP(UCA, UARTC, RSVD, GMI, RSVD, B, 22, B, 16, D, 8), + PINGROUP(UCB, UARTC, PWM, GMI, RSVD, B, 23, B, 18, D, 10), + PINGROUP(UDA, SPI1, RSVD, UARTD, ULPI, D, 13, A, 8, E, 16), + /* these pin groups only have pullup and pull down control */ + PINGROUP(CK32, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 14), + PINGROUP(DDRC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, D, 26), + PINGROUP(PMCA, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 4), + PINGROUP(PMCB, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 6), + PINGROUP(PMCC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 8), + PINGROUP(PMCD, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 10), + PINGROUP(PMCE, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 12), + PINGROUP(XM2C, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 30), + PINGROUP(XM2D, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 28), +}; + +static char *tegra_mux_names[TEGRA_MAX_MUX] = { + [TEGRA_MUX_AHB_CLK] = "AHB_CLK", + [TEGRA_MUX_APB_CLK] = "APB_CLK", + [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC", + [TEGRA_MUX_CRT] = "CRT", + [TEGRA_MUX_DAP1] = "DAP1", + [TEGRA_MUX_DAP2] = "DAP2", + [TEGRA_MUX_DAP3] = "DAP3", + [TEGRA_MUX_DAP4] = "DAP4", + [TEGRA_MUX_DAP5] = "DAP5", + [TEGRA_MUX_DISPLAYA] = "DISPLAYA", + [TEGRA_MUX_DISPLAYB] = "DISPLAYB", + [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL", + [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL", + [TEGRA_MUX_GMI] = "GMI", + [TEGRA_MUX_GMI_INT] = "GMI_INT", + [TEGRA_MUX_HDMI] = "HDMI", + [TEGRA_MUX_I2C] = "I2C", + [TEGRA_MUX_I2C2] = "I2C2", + [TEGRA_MUX_I2C3] = "I2C3", + [TEGRA_MUX_IDE] = "IDE", + [TEGRA_MUX_IRDA] = "IRDA", + [TEGRA_MUX_KBC] = "KBC", + [TEGRA_MUX_MIO] = "MIO", + [TEGRA_MUX_MIPI_HS] = "MIPI_HS", + [TEGRA_MUX_NAND] = "NAND", + [TEGRA_MUX_OSC] = "OSC", + [TEGRA_MUX_OWR] = "OWR", + [TEGRA_MUX_PCIE] = "PCIE", + [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT", + [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1", + [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1", + [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2", + [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3", + [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4", + [TEGRA_MUX_PWM] = "PWM", + [TEGRA_MUX_PWR_INTR] = "PWR_INTR", + [TEGRA_MUX_PWR_ON] = "PWR_ON", + [TEGRA_MUX_RTCK] = "RTCK", + [TEGRA_MUX_SDIO1] = "SDIO1", + [TEGRA_MUX_SDIO2] = "SDIO2", + [TEGRA_MUX_SDIO3] = "SDIO3", + [TEGRA_MUX_SDIO4] = "SDIO4", + [TEGRA_MUX_SFLASH] = "SFLASH", + [TEGRA_MUX_SPDIF] = "SPDIF", + [TEGRA_MUX_SPI1] = "SPI1", + [TEGRA_MUX_SPI2] = "SPI2", + [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT", + [TEGRA_MUX_SPI3] = "SPI3", + [TEGRA_MUX_SPI4] = "SPI4", + [TEGRA_MUX_TRACE] = "TRACE", + [TEGRA_MUX_TWC] = "TWC", + [TEGRA_MUX_UARTA] = "UARTA", + [TEGRA_MUX_UARTB] = "UARTB", + [TEGRA_MUX_UARTC] = "UARTC", + [TEGRA_MUX_UARTD] = "UARTD", + [TEGRA_MUX_UARTE] = "UARTE", + [TEGRA_MUX_ULPI] = "ULPI", + [TEGRA_MUX_VI] = "VI", + [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", + [TEGRA_MUX_XIO] = "XIO", +}; + +struct tegra_drive_pingroup_desc { + const char *name; + s16 reg; +}; + +#define DRIVE_PINGROUP(pg_name, r) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg = r \ + } + +static const struct tegra_drive_pingroup_desc drive_pingroups[TEGRA_MAX_PINGROUP] = { + DRIVE_PINGROUP(AO1, 0x868), + DRIVE_PINGROUP(AO2, 0x86c), + DRIVE_PINGROUP(AT1, 0x870), + DRIVE_PINGROUP(AT2, 0x874), + DRIVE_PINGROUP(CDEV1, 0x878), + DRIVE_PINGROUP(CDEV2, 0x87c), + DRIVE_PINGROUP(CSUS, 0x880), + DRIVE_PINGROUP(DAP1, 0x884), + DRIVE_PINGROUP(DAP2, 0x888), + DRIVE_PINGROUP(DAP3, 0x88c), + DRIVE_PINGROUP(DAP4, 0x890), + DRIVE_PINGROUP(DBG, 0x894), + DRIVE_PINGROUP(LCD1, 0x898), + DRIVE_PINGROUP(LCD2, 0x89c), + DRIVE_PINGROUP(SDMMC2, 0x8a0), + DRIVE_PINGROUP(SDMMC3, 0x8a4), + DRIVE_PINGROUP(SPI, 0x8a8), + DRIVE_PINGROUP(UAA, 0x8ac), + DRIVE_PINGROUP(UAB, 0x8b0), + DRIVE_PINGROUP(UART2, 0x8b4), + DRIVE_PINGROUP(UART3, 0x8b8), + DRIVE_PINGROUP(VI1, 0x8bc), + DRIVE_PINGROUP(VI2, 0x8c0), + DRIVE_PINGROUP(XM2A, 0x8c4), + DRIVE_PINGROUP(XM2C, 0x8c8), + DRIVE_PINGROUP(XM2D, 0x8cc), + DRIVE_PINGROUP(XM2CLK, 0x8d0), + DRIVE_PINGROUP(MEMCOMP, 0x8d4), +}; + +static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = { + [TEGRA_DRIVE_DIV_8] = "DIV_8", + [TEGRA_DRIVE_DIV_4] = "DIV_4", + [TEGRA_DRIVE_DIV_2] = "DIV_2", + [TEGRA_DRIVE_DIV_1] = "DIV_1", +}; + +static const char *tegra_slew_names[TEGRA_MAX_SLEW] = { + [TEGRA_SLEW_FASTEST] = "FASTEST", + [TEGRA_SLEW_FAST] = "FAST", + [TEGRA_SLEW_SLOW] = "SLOW", + [TEGRA_SLEW_SLOWEST] = "SLOWEST", +}; + +static DEFINE_SPINLOCK(mux_lock); + +static const char *pingroup_name(enum tegra_pingroup pg) +{ + if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + return "<UNKNOWN>"; + + return pingroups[pg].name; +} + +static const char *func_name(enum tegra_mux_func func) +{ + if (func == TEGRA_MUX_RSVD1) + return "RSVD1"; + + if (func == TEGRA_MUX_RSVD2) + return "RSVD2"; + + if (func == TEGRA_MUX_RSVD3) + return "RSVD3"; + + if (func == TEGRA_MUX_RSVD4) + return "RSVD4"; + + if (func == TEGRA_MUX_NONE) + return "NONE"; + + if (func < 0 || func >= TEGRA_MAX_MUX) + return "<UNKNOWN>"; + + return tegra_mux_names[func]; +} + + +static const char *tri_name(unsigned long val) +{ + return val ? "TRISTATE" : "NORMAL"; +} + +static const char *pupd_name(unsigned long val) +{ + switch (val) { + case 0: + return "NORMAL"; + + case 1: + return "PULL_DOWN"; + + case 2: + return "PULL_UP"; + + default: + return "RSVD"; + } +} + + +static inline unsigned long pg_readl(unsigned long offset) +{ + return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); +} + +static inline void pg_writel(unsigned long value, unsigned long offset) +{ + writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); +} + +int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func) +{ + int mux = -1; + int i; + unsigned long reg; + unsigned long flags; + + if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + return -ERANGE; + + if (pingroups[pg].mux_reg == REG_N) + return -EINVAL; + + if (func < 0) + return -ERANGE; + + if (func & TEGRA_MUX_RSVD) { + mux = func & 0x3; + } else { + for (i = 0; i < 4; i++) { + if (pingroups[pg].funcs[i] == func) { + mux = i; + break; + } + } + } + + if (mux < 0) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); + reg &= ~(0x3 << pingroups[pg].mux_bit); + reg |= mux << pingroups[pg].mux_bit; + pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +int tegra_pinmux_set_tristate(enum tegra_pingroup pg, + enum tegra_tristate tristate) +{ + unsigned long reg; + unsigned long flags; + + if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + return -ERANGE; + + if (pingroups[pg].tri_reg == REG_N) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg)); + reg &= ~(0x1 << pingroups[pg].tri_bit); + if (tristate) + reg |= 1 << pingroups[pg].tri_bit; + pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg)); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, + enum tegra_pullupdown pupd) +{ + unsigned long reg; + unsigned long flags; + + if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) + return -ERANGE; + + if (pingroups[pg].pupd_reg == REG_N) + return -EINVAL; + + if (pupd != TEGRA_PUPD_NORMAL && + pupd != TEGRA_PUPD_PULL_DOWN && + pupd != TEGRA_PUPD_PULL_UP) + return -EINVAL; + + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); + reg &= ~(0x3 << pingroups[pg].pupd_bit); + reg |= pupd << pingroups[pg].pupd_bit; + pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, + enum tegra_mux_func func, + enum tegra_pullupdown pupd, + enum tegra_tristate tristate) +{ + int err; + + if (pingroups[pingroup].mux_reg != REG_N) { + err = tegra_pinmux_set_func(pingroup, func); + if (err < 0) + pr_err("pinmux: can't set pingroup %s func to %s: %d\n", + pingroup_name(pingroup), func_name(func), err); + } + + if (pingroups[pingroup].pupd_reg != REG_N) { + err = tegra_pinmux_set_pullupdown(pingroup, pupd); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n", + pingroup_name(pingroup), pupd_name(pupd), err); + } + + if (pingroups[pingroup].tri_reg != REG_N) { + err = tegra_pinmux_set_tristate(pingroup, tristate); + if (err < 0) + pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n", + pingroup_name(pingroup), tri_name(func), err); + } +} + + + +void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + tegra_pinmux_config_pingroup(config[i].pingroup, + config[i].func, + config[i].pupd, + config[i].tristate); +} + +static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) +{ + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return "<UNKNOWN>"; + + return drive_pingroups[pg].name; +} + +static const char *enable_name(unsigned long val) +{ + return val ? "ENABLE" : "DISABLE"; +} + +static const char *drive_name(unsigned long val) +{ + if (val >= TEGRA_MAX_DRIVE) + return "<UNKNOWN>"; + + return tegra_drive_names[val]; +} + +static const char *slew_name(unsigned long val) +{ + if (val >= TEGRA_MAX_SLEW) + return "<UNKNOWN>"; + + return tegra_slew_names[val]; +} + +static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, + enum tegra_hsm hsm) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + if (hsm == TEGRA_HSM_ENABLE) + reg |= (1 << 2); + else + reg &= ~(1 << 2); + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, + enum tegra_schmitt schmitt) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + if (schmitt == TEGRA_SCHMITT_ENABLE) + reg |= (1 << 3); + else + reg &= ~(1 << 3); + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, + enum tegra_drive drive) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (drive < 0 || drive >= TEGRA_MAX_DRIVE) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + reg &= ~(0x3 << 4); + reg |= drive << 4; + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, + enum tegra_pull_strength pull_down) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + reg &= ~(0x1f << 12); + reg |= pull_down << 12; + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, + enum tegra_pull_strength pull_up) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + reg &= ~(0x1f << 12); + reg |= pull_up << 12; + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, + enum tegra_slew slew_rising) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + reg &= ~(0x3 << 28); + reg |= slew_rising << 28; + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, + enum tegra_slew slew_falling) +{ + unsigned long flags; + u32 reg; + if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) + return -ERANGE; + + if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW) + return -EINVAL; + + spin_lock_irqsave(&mux_lock, flags); + + reg = pg_readl(drive_pingroups[pg].reg); + reg &= ~(0x3 << 30); + reg |= slew_falling << 30; + pg_writel(reg, drive_pingroups[pg].reg); + + spin_unlock_irqrestore(&mux_lock, flags); + + return 0; +} + +static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup, + enum tegra_hsm hsm, + enum tegra_schmitt schmitt, + enum tegra_drive drive, + enum tegra_pull_strength pull_down, + enum tegra_pull_strength pull_up, + enum tegra_slew slew_rising, + enum tegra_slew slew_falling) +{ + int err; + + err = tegra_drive_pinmux_set_hsm(pingroup, hsm); + if (err < 0) + pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n", + drive_pinmux_name(pingroup), + enable_name(hsm), err); + + err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt); + if (err < 0) + pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n", + drive_pinmux_name(pingroup), + enable_name(schmitt), err); + + err = tegra_drive_pinmux_set_drive(pingroup, drive); + if (err < 0) + pr_err("pinmux: can't set pingroup %s drive to %s: %d\n", + drive_pinmux_name(pingroup), + drive_name(drive), err); + + err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n", + drive_pinmux_name(pingroup), + pull_down, err); + + err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up); + if (err < 0) + pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n", + drive_pinmux_name(pingroup), + pull_up, err); + + err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising); + if (err < 0) + pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n", + drive_pinmux_name(pingroup), + slew_name(slew_rising), err); + + err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling); + if (err < 0) + pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n", + drive_pinmux_name(pingroup), + slew_name(slew_falling), err); +} + +void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, + int len) +{ + int i; + + for (i = 0; i < len; i++) + tegra_drive_pinmux_config_pingroup(config[i].pingroup, + config[i].hsm, + config[i].schmitt, + config[i].drive, + config[i].pull_down, + config[i].pull_up, + config[i].slew_rising, + config[i].slew_falling); +} + + +#ifdef CONFIG_DEBUG_FS + +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +static void dbg_pad_field(struct seq_file *s, int len) +{ + seq_putc(s, ','); + + while (len-- > -1) + seq_putc(s, ' '); +} + +static int dbg_pinmux_show(struct seq_file *s, void *unused) +{ + int i; + int len; + + for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { + unsigned long tri; + unsigned long mux; + unsigned long pupd; + + seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name); + len = strlen(pingroups[i].name); + dbg_pad_field(s, 5 - len); + + if (pingroups[i].mux_reg == REG_N) { + seq_printf(s, "TEGRA_MUX_NONE"); + len = strlen("NONE"); + } else { + mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >> + pingroups[i].mux_bit) & 0x3; + if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { + seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); + len = 5; + } else { + seq_printf(s, "TEGRA_MUX_%s", + tegra_mux_names[pingroups[i].funcs[mux]]); + len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]); + } + } + dbg_pad_field(s, 13-len); + + if (pingroups[i].mux_reg == REG_N) { + seq_printf(s, "TEGRA_PUPD_NORMAL"); + len = strlen("NORMAL"); + } else { + pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >> + pingroups[i].pupd_bit) & 0x3; + seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); + len = strlen(pupd_name(pupd)); + } + dbg_pad_field(s, 9 - len); + + if (pingroups[i].tri_reg == REG_N) { + seq_printf(s, "TEGRA_TRI_NORMAL"); + } else { + tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >> + pingroups[i].tri_bit) & 0x1; + + seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); + } + seq_printf(s, "},\n"); + } + return 0; +} + +static int dbg_pinmux_open(struct inode *inode, struct file *file) +{ + return single_open(file, dbg_pinmux_show, &inode->i_private); +} + +static const struct file_operations debug_fops = { + .open = dbg_pinmux_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) +{ + int i; + int len; + + for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { + u32 reg; + + seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s", + drive_pingroups[i].name); + len = strlen(drive_pingroups[i].name); + dbg_pad_field(s, 7 - len); + + + reg = pg_readl(drive_pingroups[i].reg); + if (HSM_EN(reg)) { + seq_printf(s, "TEGRA_HSM_ENABLE"); + len = 16; + } else { + seq_printf(s, "TEGRA_HSM_DISABLE"); + len = 17; + } + dbg_pad_field(s, 17 - len); + + if (SCHMT_EN(reg)) { + seq_printf(s, "TEGRA_SCHMITT_ENABLE"); + len = 21; + } else { + seq_printf(s, "TEGRA_SCHMITT_DISABLE"); + len = 22; + } + dbg_pad_field(s, 22 - len); + + seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg))); + len = strlen(drive_name(LPMD(reg))); + dbg_pad_field(s, 5 - len); + + seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg)); + len = DRVDN(reg) < 10 ? 1 : 2; + dbg_pad_field(s, 2 - len); + + seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg)); + len = DRVUP(reg) < 10 ? 1 : 2; + dbg_pad_field(s, 2 - len); + + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg))); + len = strlen(slew_name(SLWR(reg))); + dbg_pad_field(s, 7 - len); + + seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg))); + + seq_printf(s, "},\n"); + } + return 0; +} + +static int dbg_drive_pinmux_open(struct inode *inode, struct file *file) +{ + return single_open(file, dbg_drive_pinmux_show, &inode->i_private); +} + +static const struct file_operations debug_drive_fops = { + .open = dbg_drive_pinmux_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init tegra_pinmux_debuginit(void) +{ + (void) debugfs_create_file("tegra_pinmux", S_IRUGO, + NULL, NULL, &debug_fops); + (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO, + NULL, NULL, &debug_drive_fops); + return 0; +} +late_initcall(tegra_pinmux_debuginit); +#endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c new file mode 100644 index 00000000000..1c0fd92cab3 --- /dev/null +++ b/arch/arm/mach-tegra/platsmp.c @@ -0,0 +1,156 @@ +/* + * linux/arch/arm/mach-tegra/platsmp.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * Copyright (C) 2009 Palm + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/localtimer.h> +#include <asm/smp_scu.h> + +#include <mach/iomap.h> + +extern void tegra_secondary_startup(void); + +static DEFINE_SPINLOCK(boot_lock); +static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); + +#define EVP_CPU_RESET_VECTOR \ + (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) +#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ + (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) +#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ + (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long old_boot_vector; + unsigned long boot_vector; + unsigned long timeout; + u32 reg; + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + + /* set the reset vector to point to the secondary_startup routine */ + + boot_vector = virt_to_phys(tegra_secondary_startup); + old_boot_vector = readl(EVP_CPU_RESET_VECTOR); + writel(boot_vector, EVP_CPU_RESET_VECTOR); + + /* enable cpu clock on cpu1 */ + reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + + reg = (1<<13) | (1<<9) | (1<<5) | (1<<1); + writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); + + smp_wmb(); + flush_cache_all(); + + /* unhalt the cpu */ + writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + if (readl(EVP_CPU_RESET_VECTOR) != boot_vector) + break; + udelay(10); + } + + /* put the old boot vector back */ + writel(old_boot_vector, EVP_CPU_RESET_VECTOR); + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + unsigned int i, ncores = scu_get_core_count(scu_base); + + for (i = 0; i < ncores; i++) + cpu_set(i, cpu_possible_map); +} + +void __init smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned int ncores = scu_get_core_count(scu_base); + unsigned int cpu = smp_processor_id(); + int i; + + smp_store_cpu_info(cpu); + + /* + * are we trying to boot more cores than exist? + */ + if (max_cpus > ncores) + max_cpus = ncores; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + set_cpu_present(i, true); + + /* + * Initialise the SCU if there are more than one CPU and let + * them know where to start. Note that, on modern versions of + * MILO, the "poke" doesn't actually do anything until each + * individual core is sent a soft interrupt to get it out of + * WFI + */ + if (max_cpus > 1) { + percpu_timer_setup(); + scu_enable(scu_base); + } +} diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c new file mode 100644 index 00000000000..426163231ff --- /dev/null +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -0,0 +1,1359 @@ +/* + * arch/arm/mach-tegra/tegra2_clocks.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/list.h> +#include <linux/spinlock.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/hrtimer.h> + +#include <asm/clkdev.h> + +#include <mach/iomap.h> + +#include "clock.h" + +#define RST_DEVICES 0x004 +#define RST_DEVICES_SET 0x300 +#define RST_DEVICES_CLR 0x304 + +#define CLK_OUT_ENB 0x010 +#define CLK_OUT_ENB_SET 0x320 +#define CLK_OUT_ENB_CLR 0x324 + +#define OSC_CTRL 0x50 +#define OSC_CTRL_OSC_FREQ_MASK (3<<30) +#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) +#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) +#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) +#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) + +#define OSC_FREQ_DET 0x58 +#define OSC_FREQ_DET_TRIG (1<<31) + +#define OSC_FREQ_DET_STATUS 0x5C +#define OSC_FREQ_DET_BUSY (1<<31) +#define OSC_FREQ_DET_CNT_MASK 0xFFFF + +#define PERIPH_CLK_SOURCE_MASK (3<<30) +#define PERIPH_CLK_SOURCE_SHIFT 30 +#define PERIPH_CLK_SOURCE_ENABLE (1<<28) +#define PERIPH_CLK_SOURCE_DIV_MASK 0xFF +#define PERIPH_CLK_SOURCE_DIV_SHIFT 0 + +#define PLL_BASE 0x0 +#define PLL_BASE_BYPASS (1<<31) +#define PLL_BASE_ENABLE (1<<30) +#define PLL_BASE_REF_ENABLE (1<<29) +#define PLL_BASE_OVERRIDE (1<<28) +#define PLL_BASE_LOCK (1<<27) +#define PLL_BASE_DIVP_MASK (0x7<<20) +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVN_MASK (0x3FF<<8) +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVM_MASK (0x1F) +#define PLL_BASE_DIVM_SHIFT 0 + +#define PLL_OUT_RATIO_MASK (0xFF<<8) +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_OVERRIDE (1<<2) +#define PLL_OUT_CLKEN (1<<1) +#define PLL_OUT_RESET_DISABLE (1<<0) + +#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) +#define PLL_MISC_DCCON_SHIFT 20 +#define PLL_MISC_LOCK_ENABLE (1<<18) +#define PLL_MISC_CPCON_SHIFT 8 +#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) +#define PLL_MISC_LFCON_SHIFT 4 +#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) +#define PLL_MISC_VCOCON_SHIFT 0 +#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) + +#define PLLD_MISC_CLKENABLE (1<<30) +#define PLLD_MISC_DIV_RST (1<<23) +#define PLLD_MISC_DCCON_SHIFT 12 + +#define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) +#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) +#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) + +#define SUPER_CLK_MUX 0x00 +#define SUPER_STATE_SHIFT 28 +#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) +#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) +#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) +#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) +#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) +#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) +#define SUPER_SOURCE_MASK 0xF +#define SUPER_FIQ_SOURCE_SHIFT 12 +#define SUPER_IRQ_SOURCE_SHIFT 8 +#define SUPER_RUN_SOURCE_SHIFT 4 +#define SUPER_IDLE_SOURCE_SHIFT 0 + +#define SUPER_CLK_DIVIDER 0x04 + +#define BUS_CLK_DISABLE (1<<3) +#define BUS_CLK_DIV_MASK 0x3 + +static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); + +#define clk_writel(value, reg) \ + __raw_writel(value, (u32)reg_clk_base + (reg)) +#define clk_readl(reg) \ + __raw_readl((u32)reg_clk_base + (reg)) + +unsigned long clk_measure_input_freq(void) +{ + u32 clock_autodetect; + clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); + do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); + clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); + if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { + return 12000000; + } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { + return 13000000; + } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { + return 19200000; + } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { + return 26000000; + } else { + pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect); + BUG(); + return 0; + } +} + +static int clk_div71_get_divider(struct clk *c, unsigned long rate) +{ + unsigned long divider_u71; + + divider_u71 = DIV_ROUND_UP(c->rate * 2, rate); + + if (divider_u71 - 2 > 255 || divider_u71 - 2 < 0) + return -EINVAL; + + return divider_u71 - 2; +} + +static unsigned long tegra2_clk_recalculate_rate(struct clk *c) +{ + unsigned long rate; + rate = c->parent->rate; + + if (c->mul != 0 && c->div != 0) + c->rate = rate * c->mul / c->div; + else + c->rate = rate; + return c->rate; +} + + +/* clk_m functions */ +static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) +{ + u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK; + + c->rate = clk_measure_input_freq(); + switch (c->rate) { + case 12000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; + break; + case 13000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; + break; + case 19200000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; + break; + case 26000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; + break; + default: + pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); + BUG(); + } + clk_writel(auto_clock_control, OSC_CTRL); + return c->rate; +} + +static void tegra2_clk_m_init(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + tegra2_clk_m_autodetect_rate(c); +} + +static int tegra2_clk_m_enable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + return 0; +} + +static void tegra2_clk_m_disable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + BUG(); +} + +static struct clk_ops tegra_clk_m_ops = { + .init = tegra2_clk_m_init, + .enable = tegra2_clk_m_enable, + .disable = tegra2_clk_m_disable, +}; + +/* super clock functions */ +/* "super clocks" on tegra have two-stage muxes and a clock skipping + * super divider. We will ignore the clock skipping divider, since we + * can't lower the voltage when using the clock skip, but we can if we + * lower the PLL frequency. + */ +static void tegra2_super_clk_init(struct clk *c) +{ + u32 val; + int source; + int shift; + const struct clk_mux_sel *sel; + val = clk_readl(c->reg + SUPER_CLK_MUX); + c->state = ON; + BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && + ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); + shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? + SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; + source = (val >> shift) & SUPER_SOURCE_MASK; + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->value == source) + break; + } + BUG_ON(sel->input == NULL); + c->parent = sel->input; + tegra2_clk_recalculate_rate(c); +} + +static int tegra2_super_clk_enable(struct clk *c) +{ + clk_writel(0, c->reg + SUPER_CLK_DIVIDER); + return 0; +} + +static void tegra2_super_clk_disable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + + /* oops - don't disable the CPU clock! */ + BUG(); +} + +static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + const struct clk_mux_sel *sel; + int shift; + val = clk_readl(c->reg + SUPER_CLK_MUX);; + BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && + ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); + shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? + SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + clk_reparent(c, p); + val &= ~(SUPER_SOURCE_MASK << shift); + val |= sel->value << shift; + clk_writel(val, c->reg); + c->rate = c->parent->rate; + return 0; + } + } + return -EINVAL; +} + +static struct clk_ops tegra_super_ops = { + .init = tegra2_super_clk_init, + .enable = tegra2_super_clk_enable, + .disable = tegra2_super_clk_disable, + .set_parent = tegra2_super_clk_set_parent, + .recalculate_rate = tegra2_clk_recalculate_rate, +}; + +/* bus clock functions */ +static void tegra2_bus_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; + c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; + c->mul = 1; + tegra2_clk_recalculate_rate(c); +} + +static int tegra2_bus_clk_enable(struct clk *c) +{ + u32 val = clk_readl(c->reg); + val &= ~(BUS_CLK_DISABLE << c->reg_shift); + clk_writel(val, c->reg); + return 0; +} + +static void tegra2_bus_clk_disable(struct clk *c) +{ + u32 val = clk_readl(c->reg); + val |= BUS_CLK_DISABLE << c->reg_shift; + clk_writel(val, c->reg); +} + +static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val = clk_readl(c->reg); + unsigned long parent_rate = c->parent->rate; + int i; + for (i = 1; i <= 4; i++) { + if (rate == parent_rate / i) { + val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); + val |= (i - 1) << c->reg_shift; + clk_writel(val, c->reg); + c->div = i; + c->mul = 1; + return 0; + } + } + return -EINVAL; +} + +static struct clk_ops tegra_bus_ops = { + .init = tegra2_bus_clk_init, + .enable = tegra2_bus_clk_enable, + .disable = tegra2_bus_clk_disable, + .set_rate = tegra2_bus_clk_set_rate, + .recalculate_rate = tegra2_clk_recalculate_rate, +}; + +/* PLL Functions */ +static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c) +{ + u64 rate; + rate = c->parent->rate; + rate *= c->n; + do_div(rate, c->m); + if (c->p == 2) + rate >>= 1; + c->rate = rate; + return c->rate; +} + +static int tegra2_pll_clk_wait_for_lock(struct clk *c) +{ + ktime_t before; + + before = ktime_get(); + while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) { + if (ktime_us_delta(ktime_get(), before) > 5000) { + pr_err("Timed out waiting for lock bit on pll %s", + c->name); + return -1; + } + } + + return 0; +} + +static void tegra2_pll_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg + PLL_BASE); + + c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; + + if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { + pr_warning("Clock %s has unknown fixed frequency\n", c->name); + c->n = 1; + c->m = 0; + c->p = 1; + } else if (val & PLL_BASE_BYPASS) { + c->n = 1; + c->m = 1; + c->p = 1; + } else { + c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; + c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; + c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1; + } + + val = clk_readl(c->reg + PLL_MISC(c)); + if (c->flags & PLL_HAS_CPCON) + c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT; + + tegra2_pll_clk_recalculate_rate(c); +} + +static int tegra2_pll_clk_enable(struct clk *c) +{ + u32 val; + pr_debug("%s on clock %s\n", __func__, c->name); + + val = clk_readl(c->reg + PLL_BASE); + val &= ~PLL_BASE_BYPASS; + val |= PLL_BASE_ENABLE; + clk_writel(val, c->reg + PLL_BASE); + + val = clk_readl(c->reg + PLL_MISC(c)); + val |= PLL_MISC_LOCK_ENABLE; + clk_writel(val, c->reg + PLL_MISC(c)); + + tegra2_pll_clk_wait_for_lock(c); + + return 0; +} + +static void tegra2_pll_clk_disable(struct clk *c) +{ + u32 val; + pr_debug("%s on clock %s\n", __func__, c->name); + + val = clk_readl(c->reg); + val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); + clk_writel(val, c->reg); +} + +static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val; + unsigned long input_rate; + const struct clk_pll_table *sel; + + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + BUG_ON(c->refcnt != 0); + + input_rate = c->parent->rate; + for (sel = c->pll_table; sel->input_rate != 0; sel++) { + if (sel->input_rate == input_rate && sel->output_rate == rate) { + c->n = sel->n; + c->m = sel->m; + c->p = sel->p; + c->cpcon = sel->cpcon; + + val = clk_readl(c->reg + PLL_BASE); + if (c->flags & PLL_FIXED) + val |= PLL_BASE_OVERRIDE; + val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | + PLL_BASE_DIVM_MASK); + val |= (c->m << PLL_BASE_DIVM_SHIFT) | + (c->n << PLL_BASE_DIVN_SHIFT); + BUG_ON(c->p > 2); + if (c->p == 2) + val |= 1 << PLL_BASE_DIVP_SHIFT; + clk_writel(val, c->reg + PLL_BASE); + + if (c->flags & PLL_HAS_CPCON) { + val = c->cpcon << PLL_MISC_CPCON_SHIFT; + val |= PLL_MISC_LOCK_ENABLE; + clk_writel(val, c->reg + PLL_MISC(c)); + } + + if (c->state == ON) + tegra2_pll_clk_enable(c); + + c->rate = rate; + return 0; + } + } + return -EINVAL; +} + +static struct clk_ops tegra_pll_ops = { + .init = tegra2_pll_clk_init, + .enable = tegra2_pll_clk_enable, + .disable = tegra2_pll_clk_disable, + .set_rate = tegra2_pll_clk_set_rate, + .recalculate_rate = tegra2_pll_clk_recalculate_rate, +}; + +/* Clock divider ops */ +static void tegra2_pll_div_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + u32 divu71; + val >>= c->reg_shift; + c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; + if (!(val & PLL_OUT_RESET_DISABLE)) + c->state = OFF; + + if (c->flags & DIV_U71) { + divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; + c->div = (divu71 + 2); + c->mul = 2; + } else if (c->flags & DIV_2) { + c->div = 2; + c->mul = 1; + } else { + c->div = 1; + c->mul = 1; + } + + tegra2_clk_recalculate_rate(c); +} + +static int tegra2_pll_div_clk_enable(struct clk *c) +{ + u32 val; + u32 new_val; + + pr_debug("%s: %s\n", __func__, c->name); + if (c->flags & DIV_U71) { + val = clk_readl(c->reg); + new_val = val >> c->reg_shift; + new_val &= 0xFFFF; + + new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; + + val &= ~(0xFFFF << c->reg_shift); + val |= new_val << c->reg_shift; + clk_writel(val, c->reg); + return 0; + } else if (c->flags & DIV_2) { + BUG_ON(!(c->flags & PLLD)); + val = clk_readl(c->reg); + val &= ~PLLD_MISC_DIV_RST; + clk_writel(val, c->reg); + return 0; + } + return -EINVAL; +} + +static void tegra2_pll_div_clk_disable(struct clk *c) +{ + u32 val; + u32 new_val; + + pr_debug("%s: %s\n", __func__, c->name); + if (c->flags & DIV_U71) { + val = clk_readl(c->reg); + new_val = val >> c->reg_shift; + new_val &= 0xFFFF; + + new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); + + val &= ~(0xFFFF << c->reg_shift); + val |= new_val << c->reg_shift; + clk_writel(val, c->reg); + } else if (c->flags & DIV_2) { + BUG_ON(!(c->flags & PLLD)); + val = clk_readl(c->reg); + val |= PLLD_MISC_DIV_RST; + clk_writel(val, c->reg); + } +} + +static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val; + u32 new_val; + int divider_u71; + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + if (c->flags & DIV_U71) { + divider_u71 = clk_div71_get_divider(c->parent, rate); + if (divider_u71 >= 0) { + val = clk_readl(c->reg); + new_val = val >> c->reg_shift; + new_val &= 0xFFFF; + if (c->flags & DIV_U71_FIXED) + new_val |= PLL_OUT_OVERRIDE; + new_val &= ~PLL_OUT_RATIO_MASK; + new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; + + val &= ~(0xFFFF << c->reg_shift); + val |= new_val << c->reg_shift; + clk_writel(val, c->reg); + c->div = divider_u71 + 2; + c->mul = 2; + tegra2_clk_recalculate_rate(c); + return 0; + } + } else if (c->flags & DIV_2) { + if (c->parent->rate == rate * 2) { + c->rate = rate; + return 0; + } + } + return -EINVAL; +} + + +static struct clk_ops tegra_pll_div_ops = { + .init = tegra2_pll_div_clk_init, + .enable = tegra2_pll_div_clk_enable, + .disable = tegra2_pll_div_clk_disable, + .set_rate = tegra2_pll_div_clk_set_rate, + .recalculate_rate = tegra2_clk_recalculate_rate, +}; + +/* Periph clk ops */ + +static void tegra2_periph_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + const struct clk_mux_sel *mux = 0; + const struct clk_mux_sel *sel; + if (c->flags & MUX) { + for (sel = c->inputs; sel->input != NULL; sel++) { + if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value) + mux = sel; + } + BUG_ON(!mux); + + c->parent = mux->input; + } else { + c->parent = c->inputs[0].input; + } + + if (c->flags & DIV_U71) { + u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK; + c->div = divu71 + 2; + c->mul = 2; + } else { + c->div = 1; + c->mul = 1; + } + + c->state = ON; + if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & + PERIPH_CLK_TO_ENB_BIT(c))) + c->state = OFF; + if (!(c->flags & PERIPH_NO_RESET)) + if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & + PERIPH_CLK_TO_ENB_BIT(c)) + c->state = OFF; + tegra2_clk_recalculate_rate(c); +} + +static int tegra2_periph_clk_enable(struct clk *c) +{ + u32 val; + pr_debug("%s on clock %s\n", __func__, c->name); + + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); + if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); + if (c->flags & PERIPH_EMC_ENB) { + /* The EMC peripheral clock has 2 extra enable bits */ + /* FIXME: Do they need to be disabled? */ + val = clk_readl(c->reg); + val |= 0x3 << 24; + clk_writel(val, c->reg); + } + return 0; +} + +static void tegra2_periph_clk_disable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); +} + +void tegra2_periph_reset_deassert(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + if (!(c->flags & PERIPH_NO_RESET)) + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); +} + +void tegra2_periph_reset_assert(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + if (!(c->flags & PERIPH_NO_RESET)) + clk_writel(PERIPH_CLK_TO_ENB_BIT(c), + RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); +} + + +static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + const struct clk_mux_sel *sel; + pr_debug("%s: %s %s\n", __func__, c->name, p->name); + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + clk_reparent(c, p); + val = clk_readl(c->reg); + val &= ~PERIPH_CLK_SOURCE_MASK; + val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; + clk_writel(val, c->reg); + c->rate = c->parent->rate; + return 0; + } + } + + return -EINVAL; +} + +static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val; + int divider_u71; + pr_debug("%s: %lu\n", __func__, rate); + if (c->flags & DIV_U71) { + divider_u71 = clk_div71_get_divider(c->parent, rate); + if (divider_u71 >= 0) { + val = clk_readl(c->reg); + val &= ~PERIPH_CLK_SOURCE_DIV_MASK; + val |= divider_u71; + clk_writel(val, c->reg); + c->div = divider_u71 + 2; + c->mul = 2; + tegra2_clk_recalculate_rate(c); + return 0; + } + } + return -EINVAL; +} + +static struct clk_ops tegra_periph_clk_ops = { + .init = &tegra2_periph_clk_init, + .enable = &tegra2_periph_clk_enable, + .disable = &tegra2_periph_clk_disable, + .set_parent = &tegra2_periph_clk_set_parent, + .set_rate = &tegra2_periph_clk_set_rate, + .recalculate_rate = &tegra2_clk_recalculate_rate, +}; + +/* Clock doubler ops */ +static void tegra2_clk_double_init(struct clk *c) +{ + c->mul = 2; + c->div = 1; + c->state = ON; + if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & + PERIPH_CLK_TO_ENB_BIT(c))) + c->state = OFF; + tegra2_clk_recalculate_rate(c); +}; + +static struct clk_ops tegra_clk_double_ops = { + .init = &tegra2_clk_double_init, + .enable = &tegra2_periph_clk_enable, + .disable = &tegra2_periph_clk_disable, + .recalculate_rate = &tegra2_clk_recalculate_rate, +}; + +/* Clock definitions */ +static struct clk tegra_clk_32k = { + .name = "clk_32k", + .rate = 32678, + .ops = NULL, +}; + +static struct clk_pll_table tegra_pll_s_table[] = { + {32768, 12000000, 366, 1, 1, 0}, + {32768, 13000000, 397, 1, 1, 0}, + {32768, 19200000, 586, 1, 1, 0}, + {32768, 26000000, 793, 1, 1, 0}, + {0, 0, 0, 0, 0, 0}, +}; + +static struct clk tegra_pll_s = { + .name = "pll_s", + .flags = PLL_ALT_MISC_REG, + .ops = &tegra_pll_ops, + .reg = 0xf0, + .input_min = 32768, + .input_max = 32768, + .parent = &tegra_clk_32k, + .cf_min = 0, /* FIXME */ + .cf_max = 0, /* FIXME */ + .vco_min = 12000000, + .vco_max = 26000000, + .pll_table = tegra_pll_s_table, +}; + +static struct clk_mux_sel tegra_clk_m_sel[] = { + { .input = &tegra_clk_32k, .value = 0}, + { .input = &tegra_pll_s, .value = 1}, + { 0, 0}, +}; +static struct clk tegra_clk_m = { + .name = "clk_m", + .flags = ENABLE_ON_INIT, + .ops = &tegra_clk_m_ops, + .inputs = tegra_clk_m_sel, + .reg = 0x1fc, + .reg_mask = (1<<28), + .reg_shift = 28, +}; + +static struct clk_pll_table tegra_pll_c_table[] = { + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_c = { + .name = "pll_c", + .flags = PLL_HAS_CPCON, + .ops = &tegra_pll_ops, + .reg = 0x80, + .input_min = 2000000, + .input_max = 31000000, + .parent = &tegra_clk_m, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .pll_table = tegra_pll_c_table, +}; + +static struct clk tegra_pll_c_out1 = { + .name = "pll_c_out1", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71, + .parent = &tegra_pll_c, + .reg = 0x84, + .reg_shift = 0, +}; + +static struct clk_pll_table tegra_pll_m_table[] = { + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_m = { + .name = "pll_m", + .flags = PLL_HAS_CPCON, + .ops = &tegra_pll_ops, + .reg = 0x90, + .input_min = 2000000, + .input_max = 31000000, + .parent = &tegra_clk_m, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1200000000, + .pll_table = tegra_pll_m_table, +}; + +static struct clk tegra_pll_m_out1 = { + .name = "pll_m_out1", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71, + .parent = &tegra_pll_m, + .reg = 0x94, + .reg_shift = 0, +}; + +static struct clk_pll_table tegra_pll_p_table[] = { + { 12000000, 216000000, 432, 12, 2, 8}, + { 13000000, 216000000, 432, 13, 2, 8}, + { 19200000, 216000000, 90, 4, 2, 1}, + { 26000000, 216000000, 432, 26, 2, 8}, + { 12000000, 432000000, 432, 12, 1, 8}, + { 13000000, 432000000, 432, 13, 1, 8}, + { 19200000, 432000000, 90, 4, 1, 1}, + { 26000000, 432000000, 432, 26, 1, 8}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_p = { + .name = "pll_p", + .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, + .ops = &tegra_pll_ops, + .reg = 0xa0, + .input_min = 2000000, + .input_max = 31000000, + .parent = &tegra_clk_m, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .pll_table = tegra_pll_p_table, +}; + +static struct clk tegra_pll_p_out1 = { + .name = "pll_p_out1", + .ops = &tegra_pll_div_ops, + .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa4, + .reg_shift = 0, +}; + +static struct clk tegra_pll_p_out2 = { + .name = "pll_p_out2", + .ops = &tegra_pll_div_ops, + .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa4, + .reg_shift = 16, +}; + +static struct clk tegra_pll_p_out3 = { + .name = "pll_p_out3", + .ops = &tegra_pll_div_ops, + .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa8, + .reg_shift = 0, +}; + +static struct clk tegra_pll_p_out4 = { + .name = "pll_p_out4", + .ops = &tegra_pll_div_ops, + .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa8, + .reg_shift = 16, +}; + +static struct clk_pll_table tegra_pll_a_table[] = { + { 28800000, 56448000, 49, 25, 1, 1}, + { 28800000, 73728000, 64, 25, 1, 1}, + { 28800000, 11289600, 49, 25, 1, 1}, + { 28800000, 12288000, 64, 25, 1, 1}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_a = { + .name = "pll_a", + .flags = PLL_HAS_CPCON, + .ops = &tegra_pll_ops, + .reg = 0xb0, + .input_min = 2000000, + .input_max = 31000000, + .parent = &tegra_pll_p_out1, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .pll_table = tegra_pll_a_table, +}; + +static struct clk tegra_pll_a_out0 = { + .name = "pll_a_out0", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71, + .parent = &tegra_pll_a, + .reg = 0xb4, + .reg_shift = 0, +}; + +static struct clk_pll_table tegra_pll_d_table[] = { + { 12000000, 1000000000, 1000, 12, 1, 12}, + { 13000000, 1000000000, 1000, 13, 1, 12}, + { 19200000, 1000000000, 625, 12, 1, 8}, + { 26000000, 1000000000, 1000, 26, 1, 12}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_d = { + .name = "pll_d", + .flags = PLL_HAS_CPCON | PLLD, + .ops = &tegra_pll_ops, + .reg = 0xd0, + .input_min = 2000000, + .input_max = 40000000, + .parent = &tegra_clk_m, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 40000000, + .vco_max = 1000000000, + .pll_table = tegra_pll_d_table, +}; + +static struct clk tegra_pll_d_out0 = { + .name = "pll_d_out0", + .ops = &tegra_pll_div_ops, + .flags = DIV_2 | PLLD, + .parent = &tegra_pll_d, +}; + +static struct clk_pll_table tegra_pll_u_table[] = { + { 12000000, 480000000, 960, 12, 1, 0}, + { 13000000, 480000000, 960, 13, 1, 0}, + { 19200000, 480000000, 200, 4, 1, 0}, + { 26000000, 480000000, 960, 26, 1, 0}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_u = { + .name = "pll_u", + .flags = 0, + .ops = &tegra_pll_ops, + .reg = 0xc0, + .input_min = 2000000, + .input_max = 40000000, + .parent = &tegra_clk_m, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 480000000, + .vco_max = 960000000, + .pll_table = tegra_pll_u_table, +}; + +static struct clk_pll_table tegra_pll_x_table[] = { + { 12000000, 1000000000, 1000, 12, 1, 12}, + { 13000000, 1000000000, 1000, 13, 1, 12}, + { 19200000, 1000000000, 625, 12, 1, 8}, + { 26000000, 1000000000, 1000, 26, 1, 12}, + { 12000000, 750000000, 750, 12, 1, 12}, + { 13000000, 750000000, 750, 13, 1, 12}, + { 19200000, 750000000, 625, 16, 1, 8}, + { 26000000, 750000000, 750, 26, 1, 12}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_x = { + .name = "pll_x", + .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, + .ops = &tegra_pll_ops, + .reg = 0xe0, + .input_min = 2000000, + .input_max = 31000000, + .parent = &tegra_clk_m, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1200000000, + .pll_table = tegra_pll_x_table, +}; + +static struct clk tegra_clk_d = { + .name = "clk_d", + .flags = PERIPH_NO_RESET, + .ops = &tegra_clk_double_ops, + .clk_num = 90, + .reg = 0x34, + .reg_shift = 12, + .parent = &tegra_clk_m, +}; + +/* FIXME: need tegra_audio +static struct clk tegra_clk_audio_2x = { + .name = "clk_d", + .flags = PERIPH_NO_RESET, + .ops = &tegra_clk_double_ops, + .clk_num = 89, + .reg = 0x34, + .reg_shift = 8, + .parent = &tegra_audio, +} +*/ + +static struct clk_mux_sel mux_cclk[] = { + { .input = &tegra_clk_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_clk_32k, .value = 2}, + { .input = &tegra_pll_m, .value = 3}, + { .input = &tegra_pll_p, .value = 4}, + { .input = &tegra_pll_p_out4, .value = 5}, + { .input = &tegra_pll_p_out3, .value = 6}, + { .input = &tegra_clk_d, .value = 7}, + { .input = &tegra_pll_x, .value = 8}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_sclk[] = { + { .input = &tegra_clk_m, .value = 0}, + { .input = &tegra_pll_c_out1, .value = 1}, + { .input = &tegra_pll_p_out4, .value = 2}, + { .input = &tegra_pll_p_out3, .value = 3}, + { .input = &tegra_pll_p_out2, .value = 4}, + { .input = &tegra_clk_d, .value = 5}, + { .input = &tegra_clk_32k, .value = 6}, + { .input = &tegra_pll_m_out1, .value = 7}, + { 0, 0}, +}; + +static struct clk tegra_clk_cpu = { + .name = "cpu", + .inputs = mux_cclk, + .reg = 0x20, + .ops = &tegra_super_ops, +}; + +static struct clk tegra_clk_sys = { + .name = "sys", + .inputs = mux_sclk, + .reg = 0x28, + .ops = &tegra_super_ops, +}; + +static struct clk tegra_clk_hclk = { + .name = "hclk", + .flags = DIV_BUS, + .parent = &tegra_clk_sys, + .reg = 0x30, + .reg_shift = 4, + .ops = &tegra_bus_ops, +}; + +static struct clk tegra_clk_pclk = { + .name = "pclk", + .flags = DIV_BUS, + .parent = &tegra_clk_hclk, + .reg = 0x30, + .reg_shift = 0, + .ops = &tegra_bus_ops, +}; + +static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { + { .input = &tegra_pll_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_pll_p, .value = 2}, + { .input = &tegra_pll_a_out0, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { + { .input = &tegra_pll_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_pll_p, .value = 2}, + { .input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { + { .input = &tegra_pll_p, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_pll_m, .value = 2}, + { .input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = { + {.input = &tegra_pll_a, .value = 0}, + /* FIXME: no mux defined for tegra_audio + {.input = &tegra_audio, .value = 1},*/ + {.input = &tegra_pll_p, .value = 2}, + {.input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_d_out0, .value = 1}, + {.input = &tegra_pll_c, .value = 2}, + {.input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_c, .value = 1}, + /* FIXME: no mux defined for tegra_audio + {.input = &tegra_audio, .value = 2},*/ + {.input = &tegra_clk_m, .value = 3}, + {.input = &tegra_clk_32k, .value = 4}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_pllm[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_c, .value = 1}, + {.input = &tegra_pll_m, .value = 2}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_clk_m[] = { + { .input = &tegra_clk_m, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_out3[] = { + { .input = &tegra_pll_p_out3, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_plld[] = { + { .input = &tegra_pll_d, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_clk_32k[] = { + { .input = &tegra_clk_32k, .value = 0}, + { 0, 0}, +}; + +#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + .ops = &tegra_periph_clk_ops, \ + .clk_num = _clk_num, \ + .reg = _reg, \ + .inputs = _inputs, \ + .flags = _flags, \ + } + +struct clk tegra_periph_clks[] = { + PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, mux_clk_32k, PERIPH_NO_RESET), + PERIPH_CLK("timer", "timer", NULL, 5, 0, mux_clk_m, 0), + PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, mux_plla_audio_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, mux_plla_audio_pllp_clkm, MUX | DIV_U71), + /* FIXME: spdif has 2 clocks but 1 enable */ + PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, mux_plla_audio_pllp_clkm, MUX | DIV_U71), + PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, mux_pllp_pllc_pllm, MUX | DIV_U71), + PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), + PERIPH_CLK("spi", "spi", NULL, 43, 0x114, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("xio", "xio", NULL, 45, 0x120, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("ide", "ide", NULL, 25, 0x144, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + /* FIXME: vfir shares an enable with uartb */ + PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + /* FIXME: what is la? */ + PERIPH_CLK("la", "la", NULL, 76, 0x1f8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("owr", "owr", NULL, 71, 0x1cc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, mux_pllp_out3, 0), + PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, mux_pllp_out3, 0), + PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, mux_pllp_out3, 0), + PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, mux_pllp_out3, 0), + PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), + PERIPH_CLK("3d", "3d", NULL, 24, 0x158, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), + PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + /* FIXME: vi and vi_sensor share an enable */ + PERIPH_CLK("vi", "vi", NULL, 20, 0x148, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), + /* FIXME: cve and tvo share an enable */ + PERIPH_CLK("cve", "cve", NULL, 49, 0x140, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), + PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), + PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), + PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), + PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), + PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), + PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, mux_clk_m, 0), + PERIPH_CLK("usb2", "usb.1", NULL, 58, 0, mux_clk_m, 0), + PERIPH_CLK("usb3", "usb.2", NULL, 59, 0, mux_clk_m, 0), + PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB), + PERIPH_CLK("dsi", "dsi", NULL, 48, 0, mux_plld, 0), +}; + +#define CLK_DUPLICATE(_name, _dev, _con) \ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + } + +/* Some clocks may be used by different drivers depending on the board + * configuration. List those here to register them twice in the clock lookup + * table under two names. + */ +struct clk_duplicate tegra_clk_duplicates[] = { + CLK_DUPLICATE("uarta", "tegra_uart.0", NULL), + CLK_DUPLICATE("uartb", "tegra_uart.1", NULL), + CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), + CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), + CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), +}; + +#define CLK(dev, con, ck) \ + { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + } + +struct clk_lookup tegra_clk_lookups[] = { + /* external root sources */ + CLK(NULL, "32k_clk", &tegra_clk_32k), + CLK(NULL, "pll_s", &tegra_pll_s), + CLK(NULL, "clk_m", &tegra_clk_m), + CLK(NULL, "pll_m", &tegra_pll_m), + CLK(NULL, "pll_m_out1", &tegra_pll_m_out1), + CLK(NULL, "pll_c", &tegra_pll_c), + CLK(NULL, "pll_c_out1", &tegra_pll_c_out1), + CLK(NULL, "pll_p", &tegra_pll_p), + CLK(NULL, "pll_p_out1", &tegra_pll_p_out1), + CLK(NULL, "pll_p_out2", &tegra_pll_p_out2), + CLK(NULL, "pll_p_out3", &tegra_pll_p_out3), + CLK(NULL, "pll_p_out4", &tegra_pll_p_out4), + CLK(NULL, "pll_a", &tegra_pll_a), + CLK(NULL, "pll_a_out0", &tegra_pll_a_out0), + CLK(NULL, "pll_d", &tegra_pll_d), + CLK(NULL, "pll_d_out0", &tegra_pll_d_out0), + CLK(NULL, "pll_u", &tegra_pll_u), + CLK(NULL, "pll_x", &tegra_pll_x), + CLK(NULL, "cpu", &tegra_clk_cpu), + CLK(NULL, "sys", &tegra_clk_sys), + CLK(NULL, "hclk", &tegra_clk_hclk), + CLK(NULL, "pclk", &tegra_clk_pclk), + CLK(NULL, "clk_d", &tegra_clk_d), +}; + +void __init tegra2_init_clocks(void) +{ + int i; + struct clk_lookup *cl; + struct clk *c; + struct clk_duplicate *cd; + + for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) { + cl = &tegra_clk_lookups[i]; + clk_init(cl->clk); + clkdev_add(cl); + } + + for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) { + c = &tegra_periph_clks[i]; + cl = &c->lookup; + cl->clk = c; + + clk_init(cl->clk); + clkdev_add(cl); + } + + for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { + cd = &tegra_clk_duplicates[i]; + c = tegra_get_clock_by_name(cd->name); + if (c) { + cl = &cd->lookup; + cl->clk = c; + clkdev_add(cl); + } else { + pr_err("%s: Unknown duplicate clock %s\n", __func__, + cd->name); + } + } +} diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c new file mode 100644 index 00000000000..2f420210d40 --- /dev/null +++ b/arch/arm/mach-tegra/timer.c @@ -0,0 +1,187 @@ +/* + * arch/arch/mach-tegra/timer.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross <ccross@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/time.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/cnt32_to_63.h> + +#include <asm/mach/time.h> +#include <asm/mach/time.h> +#include <asm/localtimer.h> + +#include <mach/iomap.h> +#include <mach/irqs.h> + +#include "board.h" +#include "clock.h" + +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c + +#define TIMER1_BASE 0x0 +#define TIMER2_BASE 0x8 +#define TIMER3_BASE 0x50 +#define TIMER4_BASE 0x58 + +#define TIMER_PTV 0x0 +#define TIMER_PCR 0x4 + +struct tegra_timer; + +static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); + +#define timer_writel(value, reg) \ + __raw_writel(value, (u32)timer_reg_base + (reg)) +#define timer_readl(reg) \ + __raw_readl((u32)timer_reg_base + (reg)) + +static int tegra_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + u32 reg; + + reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); + timer_writel(reg, TIMER3_BASE + TIMER_PTV); + + return 0; +} + +static void tegra_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + u32 reg; + + timer_writel(0, TIMER3_BASE + TIMER_PTV); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + reg = 0xC0000000 | ((1000000/HZ)-1); + timer_writel(reg, TIMER3_BASE + TIMER_PTV); + break; + case CLOCK_EVT_MODE_ONESHOT: + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static cycle_t tegra_clocksource_read(struct clocksource *cs) +{ + return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US)); +} + +static struct clock_event_device tegra_clockevent = { + .name = "timer0", + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .set_next_event = tegra_timer_set_next_event, + .set_mode = tegra_timer_set_mode, +}; + +static struct clocksource tegra_clocksource = { + .name = "timer_us", + .rating = 300, + .read = tegra_clocksource_read, + .mask = 0x7FFFFFFFFFFFFFFFULL, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +unsigned long long sched_clock(void) +{ + return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource), + tegra_clocksource.mult, tegra_clocksource.shift); +} + +static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static struct irqaction tegra_timer_irq = { + .name = "timer0", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, + .handler = tegra_timer_interrupt, + .dev_id = &tegra_clockevent, + .irq = INT_TMR3, +}; + +static void __init tegra_init_timer(void) +{ + unsigned long rate = clk_measure_input_freq(); + int ret; + +#ifdef CONFIG_HAVE_ARM_TWD + twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); +#endif + + switch (rate) { + case 12000000: + timer_writel(0x000b, TIMERUS_USEC_CFG); + break; + case 13000000: + timer_writel(0x000c, TIMERUS_USEC_CFG); + break; + case 19200000: + timer_writel(0x045f, TIMERUS_USEC_CFG); + break; + case 26000000: + timer_writel(0x0019, TIMERUS_USEC_CFG); + break; + default: + WARN(1, "Unknown clock rate"); + } + + if (clocksource_register_hz(&tegra_clocksource, 1000000)) { + printk(KERN_ERR "Failed to register clocksource\n"); + BUG(); + } + + ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); + if (ret) { + printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret); + BUG(); + } + + clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); + tegra_clockevent.max_delta_ns = + clockevent_delta2ns(0x1fffffff, &tegra_clockevent); + tegra_clockevent.min_delta_ns = + clockevent_delta2ns(0x1, &tegra_clockevent); + tegra_clockevent.cpumask = cpu_all_mask; + tegra_clockevent.irq = tegra_timer_irq.irq; + clockevents_register_device(&tegra_clockevent); + + return; +} + +struct sys_timer tegra_timer = { + .init = tegra_init_timer, +}; diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index 5d12d547789..60acf9e708a 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c @@ -947,6 +947,10 @@ static struct clk fast_clk = { .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock), }; +/* + * The MMCI apb_pclk is hardwired to the same terminal as the + * external MCI clock. Thus this will be referenced twice. + */ static struct clk mmcsd_clk = { .name = "MCLK", .parent = &fast_clk, @@ -1024,6 +1028,10 @@ static struct clk i2c1_clk = { .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock), }; +/* + * The SPI apb_pclk is hardwired to the same terminal as the + * external SPI clock. Thus this will be referenced twice. + */ static struct clk spi_clk = { .name = "SPI", .parent = &fast_clk, @@ -1040,10 +1048,9 @@ static struct clk spi_clk = { }; #ifdef CONFIG_MACH_U300_BS335 -static struct clk uart1_clk = { - .name = "UART1", +static struct clk uart1_pclk = { + .name = "UART1_PCLK", .parent = &fast_clk, - .rate = 13000000, .hw_ctrld = false, .reset = true, .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, @@ -1051,6 +1058,14 @@ static struct clk uart1_clk = { .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, .enable = syscon_clk_enable, .disable = syscon_clk_disable, + .lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock), +}; + +/* This one is hardwired to PLL13 */ +static struct clk uart1_clk = { + .name = "UART1_CLK", + .rate = 13000000, + .hw_ctrld = true, .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock), }; #endif @@ -1085,11 +1100,9 @@ static struct clk wdog_clk = { .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock), }; -/* This one is hardwired to PLL13 */ -static struct clk uart_clk = { - .name = "UARTCLK", +static struct clk uart0_pclk = { + .name = "UART0_PCLK", .parent = &slow_clk, - .rate = 13000000, .hw_ctrld = false, .reset = true, .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, @@ -1097,7 +1110,16 @@ static struct clk uart_clk = { .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, .enable = syscon_clk_enable, .disable = syscon_clk_disable, - .lock = __SPIN_LOCK_UNLOCKED(uart_clk.lock), + .lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock), +}; + +/* This one is hardwired to PLL13 */ +static struct clk uart0_clk = { + .name = "UART0_CLK", + .parent = &slow_clk, + .rate = 13000000, + .hw_ctrld = true, + .lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock), }; static struct clk keypad_clk = { @@ -1182,10 +1204,14 @@ static struct clk timer_clk = { .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock), }; +/* + * There is a binary divider in the hardware that divides + * the 13MHz PLL by 13 down to 1 MHz. + */ static struct clk app_timer_clk = { .name = "TIMER_APP", .parent = &slow_clk, - .rate = 13000000, + .rate = 1000000, .hw_ctrld = true, .reset = true, .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, @@ -1212,23 +1238,24 @@ static struct clk ppm_clk = { }; #endif -static struct clk dummy_apb_pclk; - #define DEF_LOOKUP(devid, clkref) \ { \ .dev_id = devid, \ .clk = clkref, \ } +#define DEF_LOOKUP_CON(devid, conid, clkref) \ + { \ + .dev_id = devid, \ + .con_id = conid, \ + .clk = clkref, \ + } + /* * Here we only define clocks that are meaningful to * look up through clockdevice. */ static struct clk_lookup lookups[] = { - { - .con_id = "apb_pclk", - .clk = &dummy_apb_pclk, - }, /* Connected directly to the AMBA bus */ DEF_LOOKUP("amba", &amba_clk), DEF_LOOKUP("cpu", &cpu_clk), @@ -1247,11 +1274,14 @@ static struct clk_lookup lookups[] = { /* AHB bridge clocks */ DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk), DEF_LOOKUP("intcon", &intcon_clk), + DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk), DEF_LOOKUP("mspro", &mspro_clk), DEF_LOOKUP("pl172", &emif_clk), + DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk), /* FAST bridge clocks */ DEF_LOOKUP("fast", &fast_clk), DEF_LOOKUP("mmci", &mmcsd_clk), + DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk), /* * The .0 and .1 identifiers on these comes from the platform device * .id field and are assigned when the platform devices are registered. @@ -1261,13 +1291,16 @@ static struct clk_lookup lookups[] = { DEF_LOOKUP("stu300.0", &i2c0_clk), DEF_LOOKUP("stu300.1", &i2c1_clk), DEF_LOOKUP("pl022", &spi_clk), + DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk), #ifdef CONFIG_MACH_U300_BS335 DEF_LOOKUP("uart1", &uart1_clk), + DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk), #endif /* SLOW bridge clocks */ DEF_LOOKUP("slow", &slow_clk), DEF_LOOKUP("coh901327_wdog", &wdog_clk), - DEF_LOOKUP("uart0", &uart_clk), + DEF_LOOKUP("uart0", &uart0_clk), + DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk), DEF_LOOKUP("apptimer", &app_timer_clk), DEF_LOOKUP("coh901461-keypad", &keypad_clk), DEF_LOOKUP("u300-gpio", &gpio_clk), @@ -1286,64 +1319,6 @@ static void __init clk_register(void) clkdev_add_table(lookups, ARRAY_SIZE(lookups)); } -/* - * These are the clocks for cells registered as primecell drivers - * on the AMBA bus. These must be on during AMBA device registration - * since the bus probe will attempt to read magic configuration - * registers for these devices. If they are deactivated these probes - * will fail. - * - * - * Please note that on emif, both RAM and NAND is connected in dual - * RAM phones. On single RAM phones, ram is on semi and NAND on emif. - * - */ -void u300_clock_primecells(void) -{ - clk_enable(&intcon_clk); - clk_enable(&uart_clk); -#ifdef CONFIG_MACH_U300_BS335 - clk_enable(&uart1_clk); -#endif - clk_enable(&spi_clk); - - clk_enable(&mmcsd_clk); - -} -EXPORT_SYMBOL(u300_clock_primecells); - -void u300_unclock_primecells(void) -{ - - clk_disable(&intcon_clk); - clk_disable(&uart_clk); -#ifdef CONFIG_MACH_U300_BS335 - clk_disable(&uart1_clk); -#endif - clk_disable(&spi_clk); - clk_disable(&mmcsd_clk); - -} -EXPORT_SYMBOL(u300_unclock_primecells); - -/* - * The interrupt controller is enabled before the clock API is registered. - */ -void u300_enable_intcon_clock(void) -{ - clk_enable(&intcon_clk); -} -EXPORT_SYMBOL(u300_enable_intcon_clock); - -/* - * The timer is enabled before the clock API is registered. - */ -void u300_enable_timer_clock(void) -{ - clk_enable(&app_timer_clk); -} -EXPORT_SYMBOL(u300_enable_timer_clock); - #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) /* * The following makes it possible to view the status (especially @@ -1385,11 +1360,13 @@ static struct clk *clks[] = { &spi_clk, #ifdef CONFIG_MACH_U300_BS335 &uart1_clk, + &uart1_pclk, #endif /* SLOW bridge clocks */ &slow_clk, &wdog_clk, - &uart_clk, + &uart0_clk, + &uart0_pclk, &app_timer_clk, &keypad_clk, &gpio_clk, @@ -1430,7 +1407,7 @@ static int u300_clocks_show(struct seq_file *s, void *data) chars++; } cdp[32] = '\0'; - if (clk->get_rate) + if (clk->get_rate || clk->rate != 0) seq_printf(s, "%s%s\t%s\t%d\t%s\t%lu Hz\n", &cdp[0], @@ -1439,7 +1416,7 @@ static int u300_clocks_show(struct seq_file *s, void *data) clk->usecount ? "ON" : "OFF", clk->usecount, clk->hw_ctrld ? "YES" : "NO ", - clk->get_rate(clk)); + clk_get_rate(clk)); else seq_printf(s, "%s%s\t%s\t%d\t%s\t" \ @@ -1483,7 +1460,7 @@ static int __init init_clk_read_debugfs(void) module_init(init_clk_read_debugfs); #endif -static int __init u300_clock_init(void) +int __init u300_clock_init(void) { u16 val; @@ -1520,10 +1497,8 @@ static int __init u300_clock_init(void) */ syscon_block_reset_disable(&semi_clk); syscon_block_reset_disable(&emif_clk); - semi_clk.enable(&semi_clk); - emif_clk.enable(&emif_clk); + clk_enable(&semi_clk); + clk_enable(&emif_clk); return 0; } -/* initialize clocking early to be available later in the boot */ -core_initcall(u300_clock_init); diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h index fc6d9ccfe7e..c34f3ea3017 100644 --- a/arch/arm/mach-u300/clock.h +++ b/arch/arm/mach-u300/clock.h @@ -45,9 +45,6 @@ struct clk { void (*disable) (struct clk *); }; -void u300_clock_primecells(void); -void u300_unclock_primecells(void); -void u300_enable_intcon_clock(void); -void u300_enable_timer_clock(void); +int u300_clock_init(void); #endif diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 653b3e0ab7b..ea41c236be0 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -19,6 +19,8 @@ #include <linux/amba/bus.h> #include <linux/platform_device.h> #include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/coh901318.h> #include <asm/types.h> @@ -1477,11 +1479,19 @@ static struct platform_device *platform_devs[] __initdata = { void __init u300_init_irq(void) { u32 mask[2] = {0, 0}; + struct clk *clk; int i; + /* initialize clocking early, we want to clock the INTCON */ + u300_clock_init(); + + /* Clock the interrupt controller */ + clk = clk_get_sys("intcon", NULL); + BUG_ON(IS_ERR(clk)); + clk_enable(clk); + for (i = 0; i < NR_IRQS; i++) set_bit(i, (unsigned long *) &mask[0]); - u300_enable_intcon_clock(); vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); } @@ -1635,12 +1645,10 @@ void __init u300_init_devices(void) u300_spi_init(&pl022_device); /* Register the AMBA devices in the AMBA bus abstraction layer */ - u300_clock_primecells(); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); } - u300_unclock_primecells(); u300_assign_physmem(); diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index 88506d03059..de1ac9ad221 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c @@ -74,16 +74,16 @@ static void _mmci_callback(struct work_struct *ws) mdelay(20); - mmci_card->mmc_inserted = !!gpio_get_value(U300_GPIO_PIN_MMC_CD); + mmci_card->mmc_inserted = !gpio_get_value(U300_GPIO_PIN_MMC_CD); input_report_switch(mmci_card->mmc_input, KEY_INSERT, - !mmci_card->mmc_inserted); + mmci_card->mmc_inserted); input_sync(mmci_card->mmc_input); pr_debug("MMC/SD card was %s\n", - mmci_card->mmc_inserted ? "removed" : "inserted"); + mmci_card->mmc_inserted ? "inserted" : "removed"); - enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, !mmci_card->mmc_inserted); + enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, mmci_card->mmc_inserted); } int __devinit mmc_init(struct amba_device *adev) diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 26d26f5100f..3fc4472719b 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -15,6 +15,8 @@ #include <linux/clocksource.h> #include <linux/types.h> #include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/hardware.h> @@ -23,7 +25,8 @@ #include <asm/mach/time.h> #include <asm/mach/irq.h> -#include "clock.h" +/* Be able to sleep for atleast 4 seconds (usually more) */ +#define APPTIMER_MIN_RANGE 4 /* * APP side special timer registers @@ -307,8 +310,6 @@ static struct clock_event_device clockevent_u300_1mhz = { .name = "GPT1", .rating = 300, /* Reasonably fast and accurate clock event */ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - /* 22 calculated using the algorithm in arch/mips/kernel/time.c */ - .shift = 22, .set_next_event = u300_set_next_event, .set_mode = u300_set_mode, }; @@ -341,8 +342,6 @@ static struct clocksource clocksource_u300_1mhz = { .rating = 300, /* Reasonably fast and accurate clock source */ .read = u300_get_cycles, .mask = CLOCKSOURCE_MASK(32), /* 32 bits */ - /* 22 calculated using the algorithm in arch/mips/kernel/time.c */ - .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -367,7 +366,15 @@ unsigned long long notrace sched_clock(void) */ static void __init u300_timer_init(void) { - u300_enable_timer_clock(); + struct clk *clk; + unsigned long rate; + + /* Clock the interrupt controller */ + clk = clk_get_sys("apptimer", NULL); + BUG_ON(IS_ERR(clk)); + clk_enable(clk); + rate = clk_get_rate(clk); + /* * Disable the "OS" and "DD" timers - these are designed for Symbian! * Example usage in cnh1601578 cpu subsystem pd_timer_app.c @@ -405,15 +412,14 @@ static void __init u300_timer_init(void) writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); - /* This is a pure microsecond clock source */ - clocksource_u300_1mhz.mult = - clocksource_khz2mult(1000, clocksource_u300_1mhz.shift); + clocksource_calc_mult_shift(&clocksource_u300_1mhz, + rate, APPTIMER_MIN_RANGE); if (clocksource_register(&clocksource_u300_1mhz)) printk(KERN_ERR "timer: failed to initialize clock " "source %s\n", clocksource_u300_1mhz.name); - clockevent_u300_1mhz.mult = - div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift); + clockevents_calc_mult_shift(&clockevent_u300_1mhz, + rate, APPTIMER_MIN_RANGE); /* 32bit counter, so 32bits delta is max */ clockevent_u300_1mhz.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz); diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 654fca944e6..9280d256111 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -113,26 +113,21 @@ struct platform_device u8500_i2c4_device = { static struct resource dma40_resources[] = { [0] = { .start = U8500_DMA_BASE, - .end = U8500_DMA_BASE + SZ_4K - 1, + .end = U8500_DMA_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, - .name = "base", + .name = "base", }, [1] = { .start = U8500_DMA_LCPA_BASE, - .end = U8500_DMA_LCPA_BASE + SZ_4K - 1, + .end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1, .flags = IORESOURCE_MEM, - .name = "lcpa", + .name = "lcpa", }, [2] = { - .start = U8500_DMA_LCLA_BASE, - .end = U8500_DMA_LCLA_BASE + 16 * 1024 - 1, - .flags = IORESOURCE_MEM, - .name = "lcla", - }, - [3] = { .start = IRQ_DB8500_DMA, .end = IRQ_DB8500_DMA, - .flags = IORESOURCE_IRQ} + .flags = IORESOURCE_IRQ, + } }; /* Default configuration for physcial memcpy */ @@ -145,11 +140,12 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = { .src_info.endianess = STEDMA40_LITTLE_ENDIAN, .src_info.data_width = STEDMA40_BYTE_WIDTH, .src_info.psize = STEDMA40_PSIZE_PHY_1, + .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, .dst_info.data_width = STEDMA40_BYTE_WIDTH, .dst_info.psize = STEDMA40_PSIZE_PHY_1, - + .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, }; /* Default configuration for logical memcpy */ struct stedma40_chan_cfg dma40_memcpy_conf_log = { @@ -162,11 +158,12 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = { .src_info.endianess = STEDMA40_LITTLE_ENDIAN, .src_info.data_width = STEDMA40_BYTE_WIDTH, .src_info.psize = STEDMA40_PSIZE_LOG_1, + .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, .dst_info.data_width = STEDMA40_BYTE_WIDTH, .dst_info.psize = STEDMA40_PSIZE_LOG_1, - + .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, }; /* @@ -180,10 +177,12 @@ static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV]; /* Reserved event lines for memcpy only */ static int dma40_memcpy_event[] = { + STEDMA40_MEMCPY_TX_0, STEDMA40_MEMCPY_TX_1, STEDMA40_MEMCPY_TX_2, STEDMA40_MEMCPY_TX_3, STEDMA40_MEMCPY_TX_4, + STEDMA40_MEMCPY_TX_5, }; static struct stedma40_platform_data dma40_plat_data = { @@ -195,6 +194,7 @@ static struct stedma40_platform_data dma40_plat_data = { .memcpy_conf_phy = &dma40_memcpy_conf_phy, .memcpy_conf_log = &dma40_memcpy_conf_log, .llis_per_log = 8, + .disabled_channels = {-1}, }; struct platform_device u8500_dma40_device = { @@ -213,4 +213,6 @@ void dma40_u8500ed_fixup(void) dma40_plat_data.memcpy_len = 0; dma40_resources[0].start = U8500_DMA_BASE_ED; dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; + dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED; + dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1; } diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 85fc6a80b38..f000218210c 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -15,9 +15,9 @@ #define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) #define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) #define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) -/* Use bank 4 for DMA LCLA and LCPA */ -#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 -#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK4 + 0x4000) +/* Use bank 4 for DMA LCPA */ +#define U8500_DMA_LCPA_BASE U8500_ESRAM_BANK4 +#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) #define U8500_PER3_BASE 0x80000000 #define U8500_STM_BASE 0x80100000 diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h index e7016278dfa..9d9d3797b3b 100644 --- a/arch/arm/mach-ux500/ste-dma40-db8500.h +++ b/arch/arm/mach-ux500/ste-dma40-db8500.h @@ -136,7 +136,7 @@ enum dma_dest_dev_type { STEDMA40_DEV_CAC1_TX = 48, STEDMA40_DEV_CAC1_TX_HAC1_TX = 49, STEDMA40_DEV_HAC1_TX = 50, - STEDMA40_MEMXCPY_TX_0 = 51, + STEDMA40_MEMCPY_TX_0 = 51, STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52, STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53, STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54, diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h index 4f8f99aac93..b5e75bb4496 100644 --- a/arch/arm/mach-versatile/include/mach/hardware.h +++ b/arch/arm/mach-versatile/include/mach/hardware.h @@ -30,15 +30,6 @@ #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul -#if 0 -#define VERSATILE_PCI_VIRT_MEM_BASE0 0xf4000000 -#define VERSATILE_PCI_VIRT_MEM_BASE1 0xf5000000 -#define VERSATILE_PCI_VIRT_MEM_BASE2 0xf6000000 - -#define PCIO_BASE VERSATILE_PCI_VIRT_MEM_BASE0 -#define PCIMEM_BASE VERSATILE_PCI_VIRT_MEM_BASE1 -#endif - /* CIK guesswork */ #define PCIBIOS_MIN_IO 0x44000000 #define PCIBIOS_MIN_MEM 0x50000000 diff --git a/arch/arm/mach-w90x900/include/mach/i2c.h b/arch/arm/mach-w90x900/include/mach/i2c.h new file mode 100644 index 00000000000..9ffb12d06e9 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/i2c.h @@ -0,0 +1,9 @@ +#ifndef __ASM_ARCH_NUC900_I2C_H +#define __ASM_ARCH_NUC900_I2C_H + +struct nuc900_platform_i2c { + int bus_num; + unsigned long bus_freq; +}; + +#endif /* __ASM_ARCH_NUC900_I2C_H */ diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 87ec141fcaa..33c3f570aaa 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -771,7 +771,8 @@ config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ - ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 + ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ + ARCH_U8500 || ARCH_VEXPRESS_CA9X4 default y select OUTER_CACHE select OUTER_CACHE_SYNC diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index 6ab244062b4..1fbdb55bfd1 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -82,7 +82,7 @@ void *kmap_atomic(struct page *page, enum km_type type) } EXPORT_SYMBOL(kmap_atomic); -void kunmap_atomic(void *kvaddr, enum km_type type) +void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type) { unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; unsigned int idx = type + KM_TYPE_NR * smp_processor_id(); @@ -103,7 +103,7 @@ void kunmap_atomic(void *kvaddr, enum km_type type) } pagefault_enable(); } -EXPORT_SYMBOL(kunmap_atomic); +EXPORT_SYMBOL(kunmap_atomic_notypecheck); void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) { diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 661fbc60575..af33b74f569 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -19,6 +19,7 @@ #ifndef __ASM_ARCH_MXC_GPIO_H__ #define __ASM_ARCH_MXC_GPIO_H__ +#include <linux/spinlock.h> #include <mach/hardware.h> #include <asm-generic/gpio.h> diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h index c34ded523f1..63f3c280423 100644 --- a/arch/arm/plat-mxc/include/mach/ssi.h +++ b/arch/arm/plat-mxc/include/mach/ssi.h @@ -10,6 +10,9 @@ struct imx_ssi_platform_data { unsigned int flags; #define IMX_SSI_DMA (1 << 0) #define IMX_SSI_USE_AC97 (1 << 1) +#define IMX_SSI_NET (1 << 2) +#define IMX_SSI_SYN (1 << 3) +#define IMX_SSI_USE_I2S_SLAVE (1 << 4) void (*ac97_reset) (struct snd_ac97 *ac97); void (*ac97_warm_reset)(struct snd_ac97 *ac97); }; diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 4d12ea4ca36..5fbde4b8dc1 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -148,7 +148,8 @@ struct stedma40_chan_cfg { * @memcpy_conf_phy: default configuration of physical channel memcpy * @memcpy_conf_log: default configuration of logical channel memcpy * @llis_per_log: number of max linked list items per logical channel - * + * @disabled_channels: A vector, ending with -1, that marks physical channels + * that are for different reasons not available for the driver. */ struct stedma40_platform_data { u32 dev_len; @@ -159,6 +160,7 @@ struct stedma40_platform_data { struct stedma40_chan_cfg *memcpy_conf_phy; struct stedma40_chan_cfg *memcpy_conf_log; unsigned int llis_per_log; + int disabled_channels[8]; }; /** diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 78b49a626d0..e39a417a368 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -1,6 +1,6 @@ if ARCH_OMAP -menu "TI OMAP Implementations" +menu "TI OMAP Common Features" config ARCH_OMAP_OTG bool @@ -21,24 +21,6 @@ config ARCH_OMAP2PLUS help "Systems based on omap24xx, omap34xx or omap44xx" -config ARCH_OMAP2 - bool "TI OMAP2" - depends on ARCH_OMAP2PLUS - select CPU_V6 - -config ARCH_OMAP3 - bool "TI OMAP3" - depends on ARCH_OMAP2PLUS - select CPU_V7 - select USB_ARCH_HAS_EHCI - select ARM_L1_CACHE_SHIFT_6 - -config ARCH_OMAP4 - bool "TI OMAP4" - depends on ARCH_OMAP2PLUS - select CPU_V7 - select ARM_GIC - endchoice comment "OMAP Feature Selections" @@ -51,7 +33,7 @@ config OMAP_DEBUG_DEVICES config OMAP_DEBUG_LEDS bool depends on OMAP_DEBUG_DEVICES - default y if LEDS || LEDS_OMAP_DEBUG + default y if LEDS config OMAP_RESET_CLOCKS bool "Reset unused clocks during boot" @@ -106,6 +88,15 @@ config OMAP_MBOX_FWK Say Y here if you want to use OMAP Mailbox framework support for DSP, IVA1.0 and IVA2 in OMAP1/2/3. +config OMAP_MBOX_KFIFO_SIZE + int "Mailbox kfifo default buffer size (bytes)" + depends on OMAP_MBOX_FWK + default 256 + help + Specify the default size of mailbox's kfifo buffers (bytes). + This can also be changed at runtime (via the mbox_kfifo_size + module parameter). + config OMAP_IOMMU tristate @@ -120,7 +111,7 @@ config OMAP_IOMMU_DEBUG choice prompt "System timer" - default OMAP_MPU_TIMER + default OMAP_32K_TIMER if !ARCH_OMAP15XX config OMAP_MPU_TIMER bool "Use mpu timer" diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 98f01910c2c..9405831b746 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o # omap_device support (OMAP2+ only at the moment) obj-$(CONFIG_ARCH_OMAP2) += omap_device.o obj-$(CONFIG_ARCH_OMAP3) += omap_device.o +obj-$(CONFIG_ARCH_OMAP4) += omap_device.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index ebed82699eb..3008e710448 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -317,18 +317,18 @@ static struct omap_globals omap3_globals = { .uart1_phys = OMAP3_UART1_BASE, .uart2_phys = OMAP3_UART2_BASE, .uart3_phys = OMAP3_UART3_BASE, + .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ }; -void __init omap2_set_globals_343x(void) +void __init omap2_set_globals_3xxx(void) { __omap2_set_globals(&omap3_globals); } -void __init omap2_set_globals_36xx(void) +void __init omap3_map_io(void) { - omap3_globals.uart4_phys = OMAP3_UART4_BASE; - - __omap2_set_globals(&omap3_globals); + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); } #endif diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 53fcef7c520..fc05b102260 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c @@ -39,7 +39,7 @@ static struct h2p2_dbg_fpga __iomem *fpga; static u16 led_state, hw_led_state; -#ifdef CONFIG_LEDS_OMAP_DEBUG +#ifdef CONFIG_OMAP_DEBUG_LEDS #define new_led_api() 1 #else #define new_led_api() 0 diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 95677d17cd1..d1920be7833 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -24,135 +24,13 @@ #include <plat/control.h> #include <plat/board.h> #include <plat/mmc.h> -#include <plat/mux.h> #include <mach/gpio.h> #include <plat/menelaus.h> #include <plat/mcbsp.h> -#include <plat/dsp_common.h> #include <plat/omap44xx.h> -#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) - -static struct dsp_platform_data dsp_pdata = { - .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list), -}; - -static struct resource omap_dsp_resources[] = { - { - .name = "dsp_mmu", - .start = -1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device omap_dsp_device = { - .name = "dsp", - .id = -1, - .num_resources = ARRAY_SIZE(omap_dsp_resources), - .resource = omap_dsp_resources, - .dev = { - .platform_data = &dsp_pdata, - }, -}; - -static inline void omap_init_dsp(void) -{ - struct resource *res; - int irq; - - if (cpu_is_omap15xx()) - irq = INT_1510_DSP_MMU; - else if (cpu_is_omap16xx()) - irq = INT_1610_DSP_MMU; - else if (cpu_is_omap24xx()) - irq = INT_24XX_DSP_MMU; - - res = platform_get_resource_byname(&omap_dsp_device, - IORESOURCE_IRQ, "dsp_mmu"); - res->start = irq; - - platform_device_register(&omap_dsp_device); -} - -int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev) -{ - static DEFINE_MUTEX(dsp_pdata_lock); - - spin_lock_init(&kdev->lock); - - mutex_lock(&dsp_pdata_lock); - list_add_tail(&kdev->entry, &dsp_pdata.kdev_list); - mutex_unlock(&dsp_pdata_lock); - - return 0; -} -EXPORT_SYMBOL(dsp_kfunc_device_register); - -#else -static inline void omap_init_dsp(void) { } -#endif /* CONFIG_OMAP_DSP */ - /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) - -static void omap_init_kp(void) -{ - /* 2430 and 34xx keypad is on TWL4030 */ - if (cpu_is_omap2430() || cpu_is_omap34xx()) - return; - if (machine_is_omap_h2() || machine_is_omap_h3()) { - omap_cfg_reg(F18_1610_KBC0); - omap_cfg_reg(D20_1610_KBC1); - omap_cfg_reg(D19_1610_KBC2); - omap_cfg_reg(E18_1610_KBC3); - omap_cfg_reg(C21_1610_KBC4); - - omap_cfg_reg(G18_1610_KBR0); - omap_cfg_reg(F19_1610_KBR1); - omap_cfg_reg(H14_1610_KBR2); - omap_cfg_reg(E20_1610_KBR3); - omap_cfg_reg(E19_1610_KBR4); - omap_cfg_reg(N19_1610_KBR5); - } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { - omap_cfg_reg(E2_7XX_KBR0); - omap_cfg_reg(J7_7XX_KBR1); - omap_cfg_reg(E1_7XX_KBR2); - omap_cfg_reg(F3_7XX_KBR3); - omap_cfg_reg(D2_7XX_KBR4); - - omap_cfg_reg(C2_7XX_KBC0); - omap_cfg_reg(D3_7XX_KBC1); - omap_cfg_reg(E4_7XX_KBC2); - omap_cfg_reg(F4_7XX_KBC3); - omap_cfg_reg(E3_7XX_KBC4); - } else if (machine_is_omap_h4()) { - omap_cfg_reg(T19_24XX_KBR0); - omap_cfg_reg(R19_24XX_KBR1); - omap_cfg_reg(V18_24XX_KBR2); - omap_cfg_reg(M21_24XX_KBR3); - omap_cfg_reg(E5__24XX_KBR4); - if (omap_has_menelaus()) { - omap_cfg_reg(B3__24XX_KBR5); - omap_cfg_reg(AA4_24XX_KBC2); - omap_cfg_reg(B13_24XX_KBC6); - } else { - omap_cfg_reg(M18_24XX_KBR5); - omap_cfg_reg(H19_24XX_KBC2); - omap_cfg_reg(N19_24XX_KBC6); - } - omap_cfg_reg(R20_24XX_KBC0); - omap_cfg_reg(M14_24XX_KBC1); - omap_cfg_reg(V17_24XX_KBC3); - omap_cfg_reg(P21_24XX_KBC4); - omap_cfg_reg(L14_24XX_KBC5); - } -} -#else -static inline void omap_init_kp(void) {} -#endif - -/*-------------------------------------------------------------------------*/ #if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE) static struct platform_device **omap_mcbsp_devices; @@ -419,8 +297,6 @@ static int __init omap_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_init_dsp(); - omap_init_kp(); omap_init_rng(); omap_init_mcpdm(); omap_init_uwire(); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index f7f571e7987..ec7eddf9e52 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -290,7 +290,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, val = dma_read(CCR(lch)); /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ - val &= ~((3 << 19) | 0x1f); + val &= ~((1 << 23) | (3 << 19) | 0x1f); val |= (dma_trigger & ~0x1f) << 14; val |= dma_trigger & 0x1f; @@ -304,11 +304,14 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, else val &= ~(1 << 18); - if (src_or_dst_synch) + if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { + val &= ~(1 << 24); /* dest synch */ + val |= (1 << 23); /* Prefetch */ + } else if (src_or_dst_synch) { val |= 1 << 24; /* source synch */ - else + } else { val &= ~(1 << 24); /* dest synch */ - + } dma_write(val, CCR(lch)); } diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 9b7e3545f32..7951eefe1a0 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -390,7 +390,9 @@ static inline int gpio_valid(int gpio) return 0; if (cpu_is_omap7xx() && gpio < 192) return 0; - if (cpu_is_omap24xx() && gpio < 128) + if (cpu_is_omap2420() && gpio < 128) + return 0; + if (cpu_is_omap2430() && gpio < 160) return 0; if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) return 0; diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index eec2b4993c6..a5ce4f0aad3 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -138,6 +138,16 @@ static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) return platform_device_register(pdev); } +/* + * XXX This function is a temporary compatibility wrapper - only + * needed until the I2C driver can be converted to call + * omap_pm_set_max_dev_wakeup_lat() and handle a return code. + */ +static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) +{ + omap_pm_set_max_mpu_wakeup_lat(dev, t); +} + static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) { struct resource *res; @@ -168,7 +178,7 @@ static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) struct omap_i2c_bus_platform_data *pd; pd = pdev->dev.platform_data; - pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat; + pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; } return platform_device_register(pdev); diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index 5cd622039da..3cf4fa25ab3 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h @@ -85,6 +85,14 @@ struct omap_usb_config { * 6 == 6 wire unidirectional (or TLL) */ u8 pins[3]; + + struct platform_device *udc_device; + struct platform_device *ohci_device; + struct platform_device *otg_device; + + u32 (*usb0_init)(unsigned nwires, unsigned is_device); + u32 (*usb1_init)(unsigned nwires); + u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); }; struct omap_lcd_config { diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index dfc472ca0cc..fef4696dcf6 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -19,6 +19,22 @@ struct module; struct clk; struct clockdomain; +/** + * struct clkops - some clock function pointers + * @enable: fn ptr that enables the current clock in hardware + * @disable: fn ptr that enables the current clock in hardware + * @find_idlest: function returning the IDLEST register for the clock's IP blk + * @find_companion: function returning the "companion" clk reg for the clock + * + * A "companion" clk is an accompanying clock to the one being queried + * that must be enabled for the IP module connected to the clock to + * become accessible by the hardware. Neither @find_idlest nor + * @find_companion should be needed; that information is IP + * block-specific; the hwmod code has been created to handle this, but + * until hwmod data is ready and drivers have been converted to use PM + * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and + * @find_companion must, unfortunately, remain. + */ struct clkops { int (*enable)(struct clk *); void (*disable)(struct clk *); @@ -30,12 +46,45 @@ struct clkops { #ifdef CONFIG_ARCH_OMAP2PLUS +/* struct clksel_rate.flags possibilities */ +#define RATE_IN_242X (1 << 0) +#define RATE_IN_243X (1 << 1) +#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ +#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ +#define RATE_IN_36XX (1 << 4) +#define RATE_IN_4430 (1 << 5) + +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) +#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) + +/** + * struct clksel_rate - register bitfield values corresponding to clk divisors + * @val: register bitfield value (shifted to bit 0) + * @div: clock divisor corresponding to @val + * @flags: (see "struct clksel_rate.flags possibilities" above) + * + * @val should match the value of a read from struct clk.clksel_reg + * AND'ed with struct clk.clksel_mask, shifted right to bit 0. + * + * @div is the divisor that should be applied to the parent clock's rate + * to produce the current clock's rate. + * + * XXX @flags probably should be replaced with an struct omap_chip. + */ struct clksel_rate { u32 val; u8 div; u8 flags; }; +/** + * struct clksel - available parent clocks, and a pointer to their divisors + * @parent: struct clk * to a possible parent clock + * @rates: available divisors for this parent clock + * + * A struct clksel is always associated with one or more struct clks + * and one or more struct clksel_rates. + */ struct clksel { struct clk *parent; const struct clksel_rate *rates; @@ -116,6 +165,60 @@ struct dpll_data { #endif +/* struct clk.flags possibilities */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ + +/** + * struct clk - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @ops: struct clkops * for this clock + * @name: the name of the clock in the hardware (used in hwmod data and debug) + * @parent: pointer to this clock's parent struct clk + * @children: list_head connecting to the child clks' @sibling list_heads + * @sibling: list_head connecting this clk to its parent clk's @children + * @rate: current clock rate + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @recalc: fn ptr that returns the clock's current rate + * @set_rate: fn ptr that can change the clock's current rate + * @round_rate: fn ptr that can round the clock's current rate + * @init: fn ptr to do clock-specific initialization + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @usecount: number of users that have requested this clock to be enabled + * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div + * @flags: see "struct clk.flags possibilities" above + * @clksel_reg: for clksel clks, register va containing src/divisor select + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector + * @clksel: for clksel clks, pointer to struct clksel for this clock + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock + * @clkdm_name: clockdomain name that this clock is contained in + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) + * @src_offset: bitshift for source selection bitfield (OMAP1 only) + * + * XXX @rate_offset, @src_offset should probably be removed and OMAP1 + * clock code converted to use clksel. + * + * XXX @usecount is poorly named. It should be "enable_count" or + * something similar. "users" in the description refers to kernel + * code (core code or drivers) that have called clk_enable() and not + * yet called clk_disable(); the usecount of parent clocks is also + * incremented by the clock code when clk_enable() is called on child + * clocks and decremented by the clock code when clk_disable() is + * called on child clocks. + * + * XXX @clkdm, @usecount, @children, @sibling should be marked for + * internal use only. + * + * @children and @sibling are used to optimize parent-to-child clock + * tree traversals. (child-to-parent traversals use @parent.) + * + * XXX The notion of the clock's current rate probably needs to be + * separated from the clock's target rate. + */ struct clk { struct list_head node; const struct clkops *ops; @@ -129,8 +232,8 @@ struct clk { int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); void (*init)(struct clk *); - __u8 enable_bit; - __s8 usecount; + u8 enable_bit; + s8 usecount; u8 fixed_div; u8 flags; #ifdef CONFIG_ARCH_OMAP2PLUS @@ -141,8 +244,8 @@ struct clk { const char *clkdm_name; struct clockdomain *clkdm; #else - __u8 rate_offset; - __u8 src_offset; + u8 rate_offset; + u8 src_offset; #endif #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) struct dentry *dent; /* For visible tree hierarchy */ @@ -188,23 +291,4 @@ extern const struct clkops clkops_null; extern struct clk dummy_ck; -/* Clock flags */ -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 1) -#define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ - -/* Clksel_rate flags */ -#define RATE_IN_242X (1 << 0) -#define RATE_IN_243X (1 << 1) -#define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ -#define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ -#define RATE_IN_36XX (1 << 4) -#define RATE_IN_4430 (1 << 5) - -#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) - -#define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) - #endif diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 5e4afbee0fd..9776b41ad76 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -58,8 +58,7 @@ struct omap_globals { void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); -void omap2_set_globals_343x(void); -void omap2_set_globals_36xx(void); +void omap2_set_globals_3xxx(void); void omap2_set_globals_443x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ @@ -69,6 +68,8 @@ void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); void omap2_set_globals_uart(struct omap_globals *); +void omap3_map_io(void); + /** * omap_test_timeout - busy-loop, testing a condition * @cond: condition to test until it evaluates to true @@ -89,4 +90,8 @@ void omap2_set_globals_uart(struct omap_globals *); } \ }) +extern struct device *omap2_get_mpuss_device(void); +extern struct device *omap2_get_dsp_device(void); +extern struct device *omap2_get_l3_device(void); + #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 75141742300..2e2ae530fce 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -66,6 +66,8 @@ unsigned int omap_rev(void); * family. This difference can be handled separately. */ #define OMAP_REVBITS_00 0x00 +#define OMAP_REVBITS_01 0x01 +#define OMAP_REVBITS_02 0x02 #define OMAP_REVBITS_10 0x10 #define OMAP_REVBITS_20 0x20 #define OMAP_REVBITS_30 0x30 @@ -376,6 +378,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3430_REV_ES3_1_2 0x34305034 #define OMAP3630_REV_ES1_0 0x36300034 +#define OMAP3630_REV_ES1_1 0x36300134 +#define OMAP3630_REV_ES1_2 0x36300234 #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -411,6 +415,8 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3430ES3_1 (1 << 6) #define CHIP_IS_OMAP3630ES1 (1 << 7) #define CHIP_IS_OMAP4430ES1 (1 << 8) +#define CHIP_IS_OMAP3630ES1_1 (1 << 9) +#define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -424,11 +430,12 @@ IS_OMAP_TYPE(3517, 0x3517) */ #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ CHIP_IS_OMAP3430ES3_0 | \ - CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) + CHIP_GE_OMAP3430ES3_1) #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \ - CHIP_IS_OMAP3630ES1) - + CHIP_IS_OMAP3630ES1 | \ + CHIP_GE_OMAP3630ES1_1) +#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \ + CHIP_IS_OMAP3630ES1_2) int omap_chip_is(struct omap_chip_id oci); void omap2_check_revision(void); @@ -444,6 +451,7 @@ extern u32 omap3_features; #define OMAP3_HAS_NEON BIT(3) #define OMAP3_HAS_ISP BIT(4) #define OMAP3_HAS_192MHZ_CLK BIT(5) +#define OMAP3_HAS_IO_WAKEUP BIT(6) #define OMAP3_HAS_FEATURE(feat,flag) \ static inline unsigned int omap3_has_ ##feat(void) \ @@ -457,5 +465,6 @@ OMAP3_HAS_FEATURE(iva, IVA) OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) +OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) #endif diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 1c529ce9dc1..8bd15bdb413 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -238,7 +238,7 @@ int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param); int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len); int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen); int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data); -int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data); +int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2); int dsi_vc_set_max_rx_packet_size(int channel, u16 len); int dsi_vc_send_null(int channel); int dsi_vc_send_bta_sync(int channel); @@ -277,8 +277,8 @@ struct omap_video_timings { * identify the mode, and does not actually use the configs * itself. However, the configs should be something that * a normal monitor can also show */ -const extern struct omap_video_timings omap_dss_pal_timings; -const extern struct omap_video_timings omap_dss_ntsc_timings; +extern const struct omap_video_timings omap_dss_pal_timings; +extern const struct omap_video_timings omap_dss_ntsc_timings; #endif struct omap_overlay_info { @@ -560,7 +560,8 @@ void omapdss_dsi_vc_enable_hs(int channel, bool enable); int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); int omap_dsi_prepare_update(struct omap_dss_device *dssdev, - u16 *x, u16 *y, u16 *w, u16 *h); + u16 *x, u16 *y, u16 *w, u16 *h, + bool enlarge_update_area); int omap_dsi_update(struct omap_dss_device *dssdev, int channel, u16 x, u16 y, u16 w, u16 h, diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 02232ca2c37..af3a03941ad 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -345,6 +345,7 @@ #define OMAP_DMA_SYNC_BLOCK 0x02 #define OMAP_DMA_SYNC_PACKET 0x03 +#define OMAP_DMA_DST_SYNC_PREFETCH 0x02 #define OMAP_DMA_SRC_SYNC 0x01 #define OMAP_DMA_DST_SYNC 0x00 diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h deleted file mode 100644 index da97736f3ef..00000000000 --- a/arch/arm/plat-omap/include/plat/dsp_common.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1) - * - * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved. - * - * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef ASM_ARCH_DSP_COMMON_H -#define ASM_ARCH_DSP_COMMON_H - -#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK) -extern void omap_dsp_request_mpui(void); -extern void omap_dsp_release_mpui(void); -extern int omap_dsp_request_mem(void); -extern int omap_dsp_release_mem(void); -#else -static inline int omap_dsp_request_mem(void) -{ - return 0; -} -#define omap_dsp_release_mem() do {} while (0) -#endif - -#endif /* ASM_ARCH_DSP_COMMON_H */ diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 145838a81ef..9fd99b9e40a 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -25,10 +25,26 @@ #define GPMC_CS_NAND_ADDRESS 0x20 #define GPMC_CS_NAND_DATA 0x24 -#define GPMC_CONFIG 0x50 -#define GPMC_STATUS 0x54 -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 +/* Control Commands */ +#define GPMC_CONFIG_RDY_BSY 0x00000001 +#define GPMC_CONFIG_DEV_SIZE 0x00000002 +#define GPMC_CONFIG_DEV_TYPE 0x00000003 +#define GPMC_SET_IRQ_STATUS 0x00000004 +#define GPMC_CONFIG_WP 0x00000005 + +#define GPMC_GET_IRQ_STATUS 0x00000006 +#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */ +#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/ +#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */ + +#define GPMC_NAND_COMMAND 0x0000000a +#define GPMC_NAND_ADDRESS 0x0000000b +#define GPMC_NAND_DATA 0x0000000c + +/* ECC commands */ +#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ +#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ +#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) @@ -47,7 +63,6 @@ #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) -#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2) #define GPMC_CONFIG1_MUXADDDATA (1 << 9) #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) @@ -56,6 +71,14 @@ #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) #define GPMC_CONFIG7_CSVALID (1 << 6) +#define GPMC_DEVICETYPE_NOR 0 +#define GPMC_DEVICETYPE_NAND 2 +#define GPMC_CONFIG_WRITEPROTECT 0x00000010 +#define GPMC_STATUS_BUFF_EMPTY 0x00000001 +#define WR_RD_PIN_MONITORING 0x00600000 +#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) +#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) + /* * Note that all values in this struct are in nanoseconds, while * the register values are in gpmc_fck cycles. @@ -108,10 +131,15 @@ extern int gpmc_cs_set_reserved(int cs, int reserved); extern int gpmc_cs_reserved(int cs); extern int gpmc_prefetch_enable(int cs, int dma_mode, unsigned int u32_count, int is_write); -extern void gpmc_prefetch_reset(void); -extern int gpmc_prefetch_status(void); +extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); extern void gpmc_init(void); +extern int gpmc_read_status(int cmd); +extern int gpmc_cs_configure(int cs, int cmd, int wval); +extern int gpmc_nand_read(int cs, int cmd); +extern int gpmc_nand_write(int cs, int cmd, int wval); +int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size); +int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code); #endif diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 0752af9d099..33c7d41cb6a 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -80,6 +80,7 @@ struct iommu_functions { int (*enable)(struct iommu *obj); void (*disable)(struct iommu *obj); + void (*set_twl)(struct iommu *obj, bool on); u32 (*fault_isr)(struct iommu *obj, u32 *ra); void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); @@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); extern u32 iotlb_cr_to_virt(struct cr_regs *cr); extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); +extern void iommu_set_twl(struct iommu *obj, bool on); extern void flush_iotlb_page(struct iommu *obj, u32 da); extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); extern void flush_iotlb_all(struct iommu *obj); diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index 729166b76a7..99765655210 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h @@ -3,10 +3,11 @@ #ifndef MAILBOX_H #define MAILBOX_H -#include <linux/wait.h> +#include <linux/spinlock.h> #include <linux/workqueue.h> -#include <linux/blkdev.h> #include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/kfifo.h> typedef u32 mbox_msg_t; struct omap_mbox; @@ -42,7 +43,7 @@ struct omap_mbox_ops { struct omap_mbox_queue { spinlock_t lock; - struct request_queue *queue; + struct kfifo fifo; struct work_struct work; struct tasklet_struct tasklet; int (*callback)(void *); @@ -52,19 +53,10 @@ struct omap_mbox_queue { struct omap_mbox { char *name; unsigned int irq; - struct omap_mbox_queue *txq, *rxq; - struct omap_mbox_ops *ops; - - mbox_msg_t seq_snd, seq_rcv; - struct device *dev; - - struct omap_mbox *next; void *priv; - - void (*err_notify)(void); }; int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); @@ -73,8 +65,8 @@ void omap_mbox_init_seq(struct omap_mbox *); struct omap_mbox *omap_mbox_get(const char *); void omap_mbox_put(struct omap_mbox *); -int omap_mbox_register(struct device *parent, struct omap_mbox *); -int omap_mbox_unregister(struct omap_mbox *); +int omap_mbox_register(struct device *parent, struct omap_mbox **); +int omap_mbox_unregister(void); static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) { diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 975744f10a5..b4ff6a11a8f 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -473,6 +473,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); u16 omap_mcbsp_get_max_rx_threshold(unsigned int id); +u16 omap_mcbsp_get_fifo_size(unsigned int id); u16 omap_mcbsp_get_tx_delay(unsigned int id); u16 omap_mcbsp_get_rx_delay(unsigned int id); int omap_mcbsp_get_dma_op_mode(unsigned int id); @@ -483,6 +484,7 @@ static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { } static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; } static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; } +static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; } static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; } static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; } static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; } diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index c835f1e994c..9b89ec601ee 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -122,6 +122,8 @@ struct omap_mmc_platform_data { /* Call back after enabling / disabling regulators */ void (*after_set_reg)(struct device *dev, int slot, int power_on, int vdd); + /* if we have special card, init it using this callback */ + void (*init_card)(struct mmc_card *card); /* return MMC cover switch state, can be NULL if not supported. * diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index c7472a28ce2..aeba71796ad 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h @@ -114,28 +114,11 @@ PU_PD_REG(NA, 0) \ }, -#define MUX_CFG_24XX(desc, reg_offset, mode, \ - pull_en, pull_mode, dbg) \ -{ \ - .name = desc, \ - .debug = dbg, \ - .mux_reg = reg_offset, \ - .mask = mode, \ - .pull_val = pull_en, \ - .pu_pd_val = pull_mode, \ -}, - -/* 24xx/34xx mux bit defines */ -#define OMAP2_PULL_ENA (1 << 3) -#define OMAP2_PULL_UP (1 << 4) -#define OMAP2_ALTELECTRICALSEL (1 << 5) - struct pin_config { char *name; const unsigned int mux_reg; unsigned char debug; -#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) const unsigned char mask_offset; const unsigned char mask; @@ -147,7 +130,6 @@ struct pin_config { const char *pu_pd_name; const unsigned int pu_pd_reg; const unsigned char pu_pd_val; -#endif #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) const char *mux_reg_name; @@ -191,6 +173,10 @@ enum omap7xx_index { SPI_7XX_4, SPI_7XX_5, SPI_7XX_6, + + /* UART */ + UART_7XX_1, + UART_7XX_2, }; enum omap1xxx_index { @@ -446,208 +432,6 @@ enum omap1xxx_index { }; -enum omap24xx_index { - /* 24xx I2C */ - M19_24XX_I2C1_SCL, - L15_24XX_I2C1_SDA, - J15_24XX_I2C2_SCL, - H19_24XX_I2C2_SDA, - - /* 24xx Menelaus interrupt */ - W19_24XX_SYS_NIRQ, - - /* 24xx clock */ - W14_24XX_SYS_CLKOUT, - - /* 24xx GPMC chipselects, wait pin monitoring */ - E2_GPMC_NCS2, - L2_GPMC_NCS7, - L3_GPMC_WAIT0, - N7_GPMC_WAIT1, - M1_GPMC_WAIT2, - P1_GPMC_WAIT3, - - /* 242X McBSP */ - Y15_24XX_MCBSP2_CLKX, - R14_24XX_MCBSP2_FSX, - W15_24XX_MCBSP2_DR, - V15_24XX_MCBSP2_DX, - - /* 24xx GPIO */ - M21_242X_GPIO11, - P21_242X_GPIO12, - AA10_242X_GPIO13, - AA6_242X_GPIO14, - AA4_242X_GPIO15, - Y11_242X_GPIO16, - AA12_242X_GPIO17, - AA8_242X_GPIO58, - Y20_24XX_GPIO60, - W4__24XX_GPIO74, - N15_24XX_GPIO85, - M15_24XX_GPIO92, - P20_24XX_GPIO93, - P18_24XX_GPIO95, - M18_24XX_GPIO96, - L14_24XX_GPIO97, - J15_24XX_GPIO99, - V14_24XX_GPIO117, - P14_24XX_GPIO125, - - /* 242x DBG GPIO */ - V4_242X_GPIO49, - W2_242X_GPIO50, - U4_242X_GPIO51, - V3_242X_GPIO52, - V2_242X_GPIO53, - V6_242X_GPIO53, - T4_242X_GPIO54, - Y4_242X_GPIO54, - T3_242X_GPIO55, - U2_242X_GPIO56, - - /* 24xx external DMA requests */ - AA10_242X_DMAREQ0, - AA6_242X_DMAREQ1, - E4_242X_DMAREQ2, - G4_242X_DMAREQ3, - D3_242X_DMAREQ4, - E3_242X_DMAREQ5, - - /* UART3 */ - K15_24XX_UART3_TX, - K14_24XX_UART3_RX, - - /* MMC/SDIO */ - G19_24XX_MMC_CLKO, - H18_24XX_MMC_CMD, - F20_24XX_MMC_DAT0, - H14_24XX_MMC_DAT1, - E19_24XX_MMC_DAT2, - D19_24XX_MMC_DAT3, - F19_24XX_MMC_DAT_DIR0, - E20_24XX_MMC_DAT_DIR1, - F18_24XX_MMC_DAT_DIR2, - E18_24XX_MMC_DAT_DIR3, - G18_24XX_MMC_CMD_DIR, - H15_24XX_MMC_CLKI, - - /* Full speed USB */ - J20_24XX_USB0_PUEN, - J19_24XX_USB0_VP, - K20_24XX_USB0_VM, - J18_24XX_USB0_RCV, - K19_24XX_USB0_TXEN, - J14_24XX_USB0_SE0, - K18_24XX_USB0_DAT, - - N14_24XX_USB1_SE0, - W12_24XX_USB1_SE0, - P15_24XX_USB1_DAT, - R13_24XX_USB1_DAT, - W20_24XX_USB1_TXEN, - P13_24XX_USB1_TXEN, - V19_24XX_USB1_RCV, - V12_24XX_USB1_RCV, - - AA10_24XX_USB2_SE0, - Y11_24XX_USB2_DAT, - AA12_24XX_USB2_TXEN, - AA6_24XX_USB2_RCV, - AA4_24XX_USB2_TLLSE0, - - /* Keypad GPIO*/ - T19_24XX_KBR0, - R19_24XX_KBR1, - V18_24XX_KBR2, - M21_24XX_KBR3, - E5__24XX_KBR4, - M18_24XX_KBR5, - R20_24XX_KBC0, - M14_24XX_KBC1, - H19_24XX_KBC2, - V17_24XX_KBC3, - P21_24XX_KBC4, - L14_24XX_KBC5, - N19_24XX_KBC6, - - /* 24xx Menelaus Keypad GPIO */ - B3__24XX_KBR5, - AA4_24XX_KBC2, - B13_24XX_KBC6, - - /* 2430 USB */ - AD9_2430_USB0_PUEN, - Y11_2430_USB0_VP, - AD7_2430_USB0_VM, - AE7_2430_USB0_RCV, - AD4_2430_USB0_TXEN, - AF9_2430_USB0_SE0, - AE6_2430_USB0_DAT, - AD24_2430_USB1_SE0, - AB24_2430_USB1_RCV, - Y25_2430_USB1_TXEN, - AA26_2430_USB1_DAT, - - /* 2430 HS-USB */ - AD9_2430_USB0HS_DATA3, - Y11_2430_USB0HS_DATA4, - AD7_2430_USB0HS_DATA5, - AE7_2430_USB0HS_DATA6, - AD4_2430_USB0HS_DATA2, - AF9_2430_USB0HS_DATA0, - AE6_2430_USB0HS_DATA1, - AE8_2430_USB0HS_CLK, - AD8_2430_USB0HS_DIR, - AE5_2430_USB0HS_STP, - AE9_2430_USB0HS_NXT, - AC7_2430_USB0HS_DATA7, - - /* 2430 McBSP */ - AD6_2430_MCBSP_CLKS, - - AB2_2430_MCBSP1_CLKR, - AD5_2430_MCBSP1_FSR, - AA1_2430_MCBSP1_DX, - AF3_2430_MCBSP1_DR, - AB3_2430_MCBSP1_FSX, - Y9_2430_MCBSP1_CLKX, - - AC10_2430_MCBSP2_FSX, - AD16_2430_MCBSP2_CLX, - AE13_2430_MCBSP2_DX, - AD13_2430_MCBSP2_DR, - AC10_2430_MCBSP2_FSX_OFF, - AD16_2430_MCBSP2_CLX_OFF, - AE13_2430_MCBSP2_DX_OFF, - AD13_2430_MCBSP2_DR_OFF, - - AC9_2430_MCBSP3_CLKX, - AE4_2430_MCBSP3_FSX, - AE2_2430_MCBSP3_DR, - AF4_2430_MCBSP3_DX, - - N3_2430_MCBSP4_CLKX, - AD23_2430_MCBSP4_DR, - AB25_2430_MCBSP4_DX, - AC25_2430_MCBSP4_FSX, - - AE16_2430_MCBSP5_CLKX, - AF12_2430_MCBSP5_FSX, - K7_2430_MCBSP5_DX, - M1_2430_MCBSP5_DR, - - /* 2430 McSPI*/ - Y18_2430_MCSPI1_CLK, - AD15_2430_MCSPI1_SIMO, - AE17_2430_MCSPI1_SOMI, - U1_2430_MCSPI1_CS0, - - /* Touchscreen GPIO */ - AF19_2430_GPIO_85, - -}; - struct omap_mux_cfg { struct pin_config *pins; unsigned long size; diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index f8efd5466b1..6562cd082bb 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -21,13 +21,11 @@ struct omap_nand_platform_data { int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; unsigned long phys_base; - void __iomem *gpmc_cs_baseaddr; - void __iomem *gpmc_baseaddr; int devsize; }; -/* size (4 KiB) for IO mapping */ -#define NAND_IO_SIZE SZ_4K +/* minimum size for IO mapping */ +#define NAND_IO_SIZE 4 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) extern int gpmc_nand_init(struct omap_nand_platform_data *d); diff --git a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h new file mode 100644 index 00000000000..01ab6572ccb --- /dev/null +++ b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h @@ -0,0 +1,31 @@ +#ifndef __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H +#define __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H + +#include "display.h" + +/** + * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration + * @name: panel name + * @use_ext_te: use external TE + * @ext_te_gpio: external TE GPIO + * @use_esd_check: perform ESD checks + * @max_backlight_level: maximum backlight level + * @set_backlight: pointer to backlight set function + * @get_backlight: pointer to backlight get function + */ +struct nokia_dsi_panel_data { + const char *name; + + int reset_gpio; + + bool use_ext_te; + int ext_te_gpio; + + bool use_esd_check; + + int max_backlight_level; + int (*set_backlight)(struct omap_dss_device *dssdev, int level); + int (*get_backlight)(struct omap_dss_device *dssdev); +}; + +#endif /* __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H */ diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 3ee41d71149..728fbb9dd54 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -1,8 +1,8 @@ /* * omap-pm.h - OMAP power management interface * - * Copyright (C) 2008-2009 Texas Instruments, Inc. - * Copyright (C) 2008-2009 Nokia Corporation + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation * Paul Walmsley * * Interface developed by (in alphabetical order): Karthik Dasu, Jouni @@ -16,6 +16,7 @@ #include <linux/device.h> #include <linux/cpufreq.h> +#include <linux/clk.h> #include "powerdomain.h" @@ -89,7 +90,7 @@ void omap_pm_if_exit(void); * @t: maximum MPU wakeup latency in microseconds * * Request that the maximum interrupt latency for the MPU to be no - * greater than 't' microseconds. "Interrupt latency" in this case is + * greater than @t microseconds. "Interrupt latency" in this case is * defined as the elapsed time from the occurrence of a hardware or * timer interrupt to the time when the device driver's interrupt * service routine has been entered by the MPU. @@ -105,15 +106,19 @@ void omap_pm_if_exit(void); * elapsed from when a device driver enables a hardware device with * clk_enable(), to when the device is ready for register access or * other use. To control this device wakeup latency, use - * set_max_dev_wakeup_lat() + * omap_pm_set_max_dev_wakeup_lat() * - * Multiple calls to set_max_mpu_wakeup_lat() will replace the + * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the * previous t value. To remove the latency target for the MPU, call * with t = -1. * - * No return value. + * XXX This constraint will be deprecated soon in favor of the more + * general omap_pm_set_max_dev_wakeup_lat() + * + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); +int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); /** @@ -123,8 +128,8 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); * @r: minimum throughput (in KiB/s) * * Request that the minimum data throughput on the OCP interconnect - * attached to device 'dev' interconnect agent 'tbus_id' be no less - * than 'r' KiB/s. + * attached to device @dev interconnect agent @tbus_id be no less + * than @r KiB/s. * * It is expected that the OMAP PM or bus code will use this * information to set the interconnect clock to run at the lowest @@ -138,40 +143,44 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t); * code will also need to add an minimum L3 interconnect speed * constraint, * - * Multiple calls to set_min_bus_tput() will replace the previous rate - * value for this device. To remove the interconnect throughput - * restriction for this device, call with r = 0. + * Multiple calls to omap_pm_set_min_bus_tput() will replace the + * previous rate value for this device. To remove the interconnect + * throughput restriction for this device, call with r = 0. * - * No return value. + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); +int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); /** * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency - * @dev: struct device * + * @req_dev: struct device * requesting the constraint, or NULL if none + * @dev: struct device * to set the constraint one * @t: maximum device wakeup latency in microseconds * - * Request that the maximum amount of time necessary for a device to - * become accessible after its clocks are enabled should be no greater - * than 't' microseconds. Specifically, this represents the time from - * when a device driver enables device clocks with clk_enable(), to - * when the register reads and writes on the device will succeed. - * This function should be called before clk_disable() is called, - * since the power state transition decision may be made during - * clk_disable(). + * Request that the maximum amount of time necessary for a device @dev + * to become accessible after its clocks are enabled should be no + * greater than @t microseconds. Specifically, this represents the + * time from when a device driver enables device clocks with + * clk_enable(), to when the register reads and writes on the device + * will succeed. This function should be called before clk_disable() + * is called, since the power state transition decision may be made + * during clk_disable(). * * It is intended that underlying PM code will use this information to * determine what power state to put the powerdomain enclosing this * device into. * - * Multiple calls to set_max_dev_wakeup_lat() will replace the - * previous wakeup latency values for this device. To remove the wakeup - * latency restriction for this device, call with t = -1. + * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the + * previous wakeup latency values for this device. To remove the + * wakeup latency restriction for this device, call with t = -1. * - * No return value. + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); +int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, + long t); /** @@ -198,10 +207,71 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t); * value for this device. To remove the maximum DMA latency for this * device, call with t = -1. * - * No return value. + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. */ -void omap_pm_set_max_sdma_lat(struct device *dev, long t); +int omap_pm_set_max_sdma_lat(struct device *dev, long t); + +/** + * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev + * @dev: struct device * requesting the constraint + * @clk: struct clk * to set the minimum rate constraint on + * @r: minimum rate in Hz + * + * Request that the minimum clock rate on the device @dev's clk @clk + * be no less than @r Hz. + * + * It is expected that the OMAP PM code will use this information to + * find an OPP or clock setting that will satisfy this clock rate + * constraint, along with any other applicable system constraints on + * the clock rate or corresponding voltage, etc. + * + * omap_pm_set_min_clk_rate() differs from the clock code's + * clk_set_rate() in that it considers other constraints before taking + * any hardware action, and may change a system OPP rather than just a + * clock rate. clk_set_rate() is intended to be a low-level + * interface. + * + * omap_pm_set_min_clk_rate() is easily open to abuse. A better API + * would be something like "omap_pm_set_min_dev_performance()"; + * however, there is no easily-generalizable concept of performance + * that applies to all devices. Only a device (and possibly the + * device subsystem) has both the subsystem-specific knowledge, and + * the hardware IP block-specific knowledge, to translate a constraint + * on "touchscreen sampling accuracy" or "number of pixels or polygons + * rendered per second" to a clock rate. This translation can be + * dependent on the hardware IP block's revision, or firmware version, + * and the driver is the only code on the system that has this + * information and can know how to translate that into a clock rate. + * + * The intended use-case for this function is for userspace or other + * kernel code to communicate a particular performance requirement to + * a subsystem; then for the subsystem to communicate that requirement + * to something that is meaningful to the device driver; then for the + * device driver to convert that requirement to a clock rate, and to + * then call omap_pm_set_min_clk_rate(). + * + * Users of this function (such as device drivers) should not simply + * call this function with some high clock rate to ensure "high + * performance." Rather, the device driver should take a performance + * constraint from its subsystem, such as "render at least X polygons + * per second," and use some formula or table to convert that into a + * clock rate constraint given the hardware type and hardware + * revision. Device drivers or subsystems should not assume that they + * know how to make a power/performance tradeoff - some device use + * cases may tolerate a lower-fidelity device function for lower power + * consumption; others may demand a higher-fidelity device function, + * no matter what the power consumption. + * + * Multiple calls to omap_pm_set_min_clk_rate() will replace the + * previous rate value for the device @dev. To remove the minimum clock + * rate constraint for the device, call with r = 0. + * + * Returns -EINVAL for an invalid argument, -ERANGE if the constraint + * is not satisfiable, or 0 upon success. + */ +int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r); /* * DSP Bridge-specific constraints diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 3694b622c4a..25cd9ac3b09 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -101,6 +101,8 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, int omap_device_register(struct omap_device *od); int omap_early_device_register(struct omap_device *od); +void __iomem *omap_device_get_rt_va(struct omap_device *od); + /* OMAP PM interface */ int omap_device_align_pm_lat(struct platform_device *pdev, u32 new_wakeup_lat_limit); diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 0eccc09ac4a..a4e508dfaba 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -1,7 +1,7 @@ /* * omap_hwmod macros, structures * - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Nokia Corporation * Paul Walmsley * * Created in collaboration with (alphabetical order): Benoît Cousson, @@ -419,7 +419,7 @@ struct omap_hwmod_class { * @slaves: ptr to array of OCP ifs that this hwmod can respond on * @dev_attr: arbitrary device attributes that can be passed to the driver * @_sysc_cache: internal-use hwmod flags - * @_rt_va: cached register target start address (internal use) + * @_mpu_rt_va: cached register target start address (internal use) * @_mpu_port_index: cached MPU register target slave ID (internal use) * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift @@ -460,7 +460,7 @@ struct omap_hwmod { struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ void *dev_attr; u32 _sysc_cache; - void __iomem *_rt_va; + void __iomem *_mpu_rt_va; struct list_head node; u16 flags; u8 _mpu_port_index; @@ -482,11 +482,14 @@ int omap_hwmod_init(struct omap_hwmod **ohs); int omap_hwmod_register(struct omap_hwmod *oh); int omap_hwmod_unregister(struct omap_hwmod *oh); struct omap_hwmod *omap_hwmod_lookup(const char *name); -int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)); -int omap_hwmod_late_init(void); +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), + void *data); +int omap_hwmod_late_init(u8 skip_setup_idle); int omap_hwmod_enable(struct omap_hwmod *oh); +int _omap_hwmod_enable(struct omap_hwmod *oh); int omap_hwmod_idle(struct omap_hwmod *oh); +int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); int omap_hwmod_enable_clocks(struct omap_hwmod *oh); @@ -504,6 +507,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); +void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh); diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index 8983d54c4fd..5177a9c5a25 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h @@ -19,17 +19,11 @@ #include <asm/hardware/gic.h> -/* - * set_event() is used to wake up secondary core from wfe using sev. ROM - * code puts the second core into wfe(standby). - * - */ -#define set_event() __asm__ __volatile__ ("sev" : : : "memory") - /* Needed for secondary core boot */ extern void omap_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); +extern u32 omap_read_auxcoreboot0(void); /* * We use Soft IRQ1 as the IPI diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index bbedd71943f..ddf723be48d 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -25,6 +25,8 @@ #include <plat/serial.h> +#define MDR1_MODE_MASK 0x07 + static volatile u8 *uart_base; static int uart_shift; @@ -42,6 +44,10 @@ static void putc(int c) if (!uart_base) return; + /* Check for UART 16x mode */ + if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) + return; + while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) barrier(); uart_base[UART_TX << uart_shift] = c; diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 98eef5360e6..2a9427c8cc4 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -81,7 +81,34 @@ extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); #endif -void omap_usb_init(struct omap_usb_config *pdata); + +/* + * FIXME correct answer depends on hmc_mode, + * as does (on omap1) any nonzero value for config->otg port number + */ +#ifdef CONFIG_USB_GADGET_OMAP +#define is_usb0_device(config) 1 +#else +#define is_usb0_device(config) 0 +#endif + +void omap_otg_init(struct omap_usb_config *config); + +#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) +void omap1_usb_init(struct omap_usb_config *pdata); +#else +static inline void omap1_usb_init(struct omap_usb_config *pdata) +{ +} +#endif + +#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) +void omap2_usbfs_init(struct omap_usb_config *pdata); +#else +static inline omap2_usbfs_init(struct omap_usb_config *pdata) +{ +} +#endif /*-------------------------------------------------------------------------*/ @@ -192,4 +219,24 @@ void omap_usb_init(struct omap_usb_config *pdata); # define USB0PUENACTLOI (1 << 16) # define USBSTANDBYCTRL (1 << 15) +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) +u32 omap1_usb0_init(unsigned nwires, unsigned is_device); +u32 omap1_usb1_init(unsigned nwires); +u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup); +#else +static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device) +{ + return 0; +} +static inline u32 omap1_usb1_init(unsigned nwires) +{ + return 0; + +} +static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) +{ + return 0; +} +#endif + #endif /* __ASM_ARCH_OMAP_USB_H */ diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index bc094dbacee..a202a2ce6e3 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj) } EXPORT_SYMBOL_GPL(flush_iotlb_all); +/** + * iommu_set_twl - enable/disable table walking logic + * @obj: target iommu + * @on: enable/disable + * + * Function used to enable/disable TWL. If one wants to work + * exclusively with locked TLB entries and receive notifications + * for TLB miss then call this function to disable TWL. + */ +void iommu_set_twl(struct iommu *obj, bool on) +{ + clk_enable(obj->clk); + arch_iommu->set_twl(obj, on); + clk_disable(obj->clk); +} +EXPORT_SYMBOL_GPL(iommu_set_twl); + #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) @@ -653,7 +670,7 @@ void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) if (!*iopgd) goto out; - if (*iopgd & IOPGD_TABLE) + if (iopgd_is_table(*iopgd)) iopte = iopte_offset(iopgd, da); out: *ppgd = iopgd; @@ -670,7 +687,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) if (!*iopgd) return 0; - if (*iopgd & IOPGD_TABLE) { + if (iopgd_is_table(*iopgd)) { int i; u32 *iopte = iopte_offset(iopgd, da); @@ -745,7 +762,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj) if (!*iopgd) continue; - if (*iopgd & IOPGD_TABLE) + if (iopgd_is_table(*iopgd)) iopte_free(iopte_offset(iopgd, 0)); *iopgd = 0; @@ -783,9 +800,11 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) if (!stat) return IRQ_HANDLED; + iommu_disable(obj); + iopgd = iopgd_offset(obj, da); - if (!(*iopgd & IOPGD_TABLE)) { + if (!iopgd_is_table(*iopgd)) { dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, da, iopgd, *iopgd); return IRQ_NONE; diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h index ab23b6a140f..c3e93bb0911 100644 --- a/arch/arm/plat-omap/iopgtable.h +++ b/arch/arm/plat-omap/iopgtable.h @@ -63,6 +63,8 @@ #define IOPGD_SECTION (2 << 0) #define IOPGD_SUPER (1 << 18 | 2 << 0) +#define iopgd_is_table(x) (((x) & 3) == IOPGD_TABLE) + #define IOPTE_SMALL (2 << 0) #define IOPTE_LARGE (1 << 0) @@ -70,12 +72,12 @@ #define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) #define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) -#define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) -#define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) +#define iopgd_page_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) +#define iopgd_page_vaddr(iopgd) ((u32 *)phys_to_virt(iopgd_page_paddr(iopgd))) /* to find an entry in the second-level page table. */ #define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) -#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) +#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da)) static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, u32 flags) diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index 08a2df76628..d2fafb892f7 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c @@ -21,19 +21,26 @@ * */ -#include <linux/module.h> #include <linux/interrupt.h> -#include <linux/device.h> +#include <linux/spinlock.h> +#include <linux/mutex.h> #include <linux/delay.h> #include <linux/slab.h> +#include <linux/kfifo.h> +#include <linux/err.h> #include <plat/mailbox.h> static struct workqueue_struct *mboxd; -static struct omap_mbox *mboxes; -static DEFINE_RWLOCK(mboxes_lock); +static struct omap_mbox **mboxes; +static bool rq_full; static int mbox_configured; +static DEFINE_MUTEX(mbox_configured_lock); + +static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; +module_param(mbox_kfifo_size, uint, S_IRUGO); +MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); /* Mailbox FIFO handle functions */ static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) @@ -67,7 +74,7 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) /* * message sender */ -static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) +static int __mbox_poll_for_space(struct omap_mbox *mbox) { int ret = 0, i = 1000; @@ -78,49 +85,50 @@ static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) return -1; udelay(1); } - mbox_fifo_write(mbox, msg); return ret; } - int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) { + struct omap_mbox_queue *mq = mbox->txq; + int ret = 0, len; - struct request *rq; - struct request_queue *q = mbox->txq->queue; + spin_lock(&mq->lock); - rq = blk_get_request(q, WRITE, GFP_ATOMIC); - if (unlikely(!rq)) - return -ENOMEM; + if (kfifo_avail(&mq->fifo) < sizeof(msg)) { + ret = -ENOMEM; + goto out; + } + + len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + WARN_ON(len != sizeof(msg)); - blk_insert_request(q, rq, 0, (void *) msg); tasklet_schedule(&mbox->txq->tasklet); - return 0; +out: + spin_unlock(&mq->lock); + return ret; } EXPORT_SYMBOL(omap_mbox_msg_send); static void mbox_tx_tasklet(unsigned long tx_data) { - int ret; - struct request *rq; struct omap_mbox *mbox = (struct omap_mbox *)tx_data; - struct request_queue *q = mbox->txq->queue; - - while (1) { - - rq = blk_fetch_request(q); - - if (!rq) - break; + struct omap_mbox_queue *mq = mbox->txq; + mbox_msg_t msg; + int ret; - ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special); - if (ret) { + while (kfifo_len(&mq->fifo)) { + if (__mbox_poll_for_space(mbox)) { omap_mbox_enable_irq(mbox, IRQ_TX); - blk_requeue_request(q, rq); - return; + break; } - blk_end_request_all(rq, 0); + + ret = kfifo_out(&mq->fifo, (unsigned char *)&msg, + sizeof(msg)); + WARN_ON(ret != sizeof(msg)); + + mbox_fifo_write(mbox, msg); } } @@ -131,36 +139,21 @@ static void mbox_rx_work(struct work_struct *work) { struct omap_mbox_queue *mq = container_of(work, struct omap_mbox_queue, work); - struct omap_mbox *mbox = mq->queue->queuedata; - struct request_queue *q = mbox->rxq->queue; - struct request *rq; mbox_msg_t msg; - unsigned long flags; + int len; - while (1) { - spin_lock_irqsave(q->queue_lock, flags); - rq = blk_fetch_request(q); - spin_unlock_irqrestore(q->queue_lock, flags); - if (!rq) - break; + while (kfifo_len(&mq->fifo) >= sizeof(msg)) { + len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + WARN_ON(len != sizeof(msg)); - msg = (mbox_msg_t)rq->special; - blk_end_request_all(rq, 0); - mbox->rxq->callback((void *)msg); + if (mq->callback) + mq->callback((void *)msg); } } /* * Mailbox interrupt handler */ -static void mbox_txq_fn(struct request_queue *q) -{ -} - -static void mbox_rxq_fn(struct request_queue *q) -{ -} - static void __mbox_tx_interrupt(struct omap_mbox *mbox) { omap_mbox_disable_irq(mbox, IRQ_TX); @@ -170,19 +163,22 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox) static void __mbox_rx_interrupt(struct omap_mbox *mbox) { - struct request *rq; + struct omap_mbox_queue *mq = mbox->rxq; mbox_msg_t msg; - struct request_queue *q = mbox->rxq->queue; + int len; while (!mbox_fifo_empty(mbox)) { - rq = blk_get_request(q, WRITE, GFP_ATOMIC); - if (unlikely(!rq)) + if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { + omap_mbox_disable_irq(mbox, IRQ_RX); + rq_full = true; goto nomem; + } msg = mbox_fifo_read(mbox); + len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); + WARN_ON(len != sizeof(msg)); - blk_insert_request(q, rq, 0, (void *)msg); if (mbox->ops->type == OMAP_MBOX_TYPE1) break; } @@ -207,11 +203,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p) } static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, - request_fn_proc *proc, void (*work) (struct work_struct *), void (*tasklet)(unsigned long)) { - struct request_queue *q; struct omap_mbox_queue *mq; mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL); @@ -220,11 +214,8 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, spin_lock_init(&mq->lock); - q = blk_init_queue(proc, &mq->lock); - if (!q) + if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) goto error; - q->queuedata = mbox; - mq->queue = q; if (work) INIT_WORK(&mq->work, work); @@ -239,7 +230,7 @@ error: static void mbox_queue_free(struct omap_mbox_queue *q) { - blk_cleanup_queue(q->queue); + kfifo_free(&q->fifo); kfree(q); } @@ -248,35 +239,35 @@ static int omap_mbox_startup(struct omap_mbox *mbox) int ret = 0; struct omap_mbox_queue *mq; - if (likely(mbox->ops->startup)) { - write_lock(&mboxes_lock); + if (mbox->ops->startup) { + mutex_lock(&mbox_configured_lock); if (!mbox_configured) ret = mbox->ops->startup(mbox); - if (unlikely(ret)) { - write_unlock(&mboxes_lock); + if (ret) { + mutex_unlock(&mbox_configured_lock); return ret; } mbox_configured++; - write_unlock(&mboxes_lock); + mutex_unlock(&mbox_configured_lock); } ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, mbox->name, mbox); - if (unlikely(ret)) { + if (ret) { printk(KERN_ERR "failed to register mailbox interrupt:%d\n", ret); goto fail_request_irq; } - mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet); + mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); if (!mq) { ret = -ENOMEM; goto fail_alloc_txq; } mbox->txq = mq; - mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL); + mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); if (!mq) { ret = -ENOMEM; goto fail_alloc_rxq; @@ -290,7 +281,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox) fail_alloc_txq: free_irq(mbox->irq, mbox); fail_request_irq: - if (unlikely(mbox->ops->shutdown)) + if (mbox->ops->shutdown) mbox->ops->shutdown(mbox); return ret; @@ -298,31 +289,20 @@ static int omap_mbox_startup(struct omap_mbox *mbox) static void omap_mbox_fini(struct omap_mbox *mbox) { + free_irq(mbox->irq, mbox); + tasklet_kill(&mbox->txq->tasklet); + flush_work(&mbox->rxq->work); mbox_queue_free(mbox->txq); mbox_queue_free(mbox->rxq); - free_irq(mbox->irq, mbox); - - if (unlikely(mbox->ops->shutdown)) { - write_lock(&mboxes_lock); + if (mbox->ops->shutdown) { + mutex_lock(&mbox_configured_lock); if (mbox_configured > 0) mbox_configured--; if (!mbox_configured) mbox->ops->shutdown(mbox); - write_unlock(&mboxes_lock); - } -} - -static struct omap_mbox **find_mboxes(const char *name) -{ - struct omap_mbox **p; - - for (p = &mboxes; *p; p = &(*p)->next) { - if (strcmp((*p)->name, name) == 0) - break; + mutex_unlock(&mbox_configured_lock); } - - return p; } struct omap_mbox *omap_mbox_get(const char *name) @@ -330,14 +310,15 @@ struct omap_mbox *omap_mbox_get(const char *name) struct omap_mbox *mbox; int ret; - read_lock(&mboxes_lock); - mbox = *(find_mboxes(name)); - if (mbox == NULL) { - read_unlock(&mboxes_lock); - return ERR_PTR(-ENOENT); - } + if (!mboxes) + return ERR_PTR(-EINVAL); - read_unlock(&mboxes_lock); + for (mbox = *mboxes; mbox; mbox++) + if (!strcmp(mbox->name, name)) + break; + + if (!mbox) + return ERR_PTR(-ENOENT); ret = omap_mbox_startup(mbox); if (ret) @@ -353,70 +334,77 @@ void omap_mbox_put(struct omap_mbox *mbox) } EXPORT_SYMBOL(omap_mbox_put); -int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) +static struct class omap_mbox_class = { .name = "mbox", }; + +int omap_mbox_register(struct device *parent, struct omap_mbox **list) { - int ret = 0; - struct omap_mbox **tmp; + int ret; + int i; - if (!mbox) + mboxes = list; + if (!mboxes) return -EINVAL; - if (mbox->next) - return -EBUSY; - - write_lock(&mboxes_lock); - tmp = find_mboxes(mbox->name); - if (*tmp) { - ret = -EBUSY; - write_unlock(&mboxes_lock); - goto err_find; - } - *tmp = mbox; - write_unlock(&mboxes_lock); + for (i = 0; mboxes[i]; i++) { + struct omap_mbox *mbox = mboxes[i]; + mbox->dev = device_create(&omap_mbox_class, + parent, 0, mbox, "%s", mbox->name); + if (IS_ERR(mbox->dev)) { + ret = PTR_ERR(mbox->dev); + goto err_out; + } + } return 0; -err_find: +err_out: + while (i--) + device_unregister(mboxes[i]->dev); return ret; } EXPORT_SYMBOL(omap_mbox_register); -int omap_mbox_unregister(struct omap_mbox *mbox) +int omap_mbox_unregister(void) { - struct omap_mbox **tmp; - - write_lock(&mboxes_lock); - tmp = &mboxes; - while (*tmp) { - if (mbox == *tmp) { - *tmp = mbox->next; - mbox->next = NULL; - write_unlock(&mboxes_lock); - return 0; - } - tmp = &(*tmp)->next; - } - write_unlock(&mboxes_lock); + int i; + + if (!mboxes) + return -EINVAL; - return -EINVAL; + for (i = 0; mboxes[i]; i++) + device_unregister(mboxes[i]->dev); + mboxes = NULL; + return 0; } EXPORT_SYMBOL(omap_mbox_unregister); static int __init omap_mbox_init(void) { + int err; + + err = class_register(&omap_mbox_class); + if (err) + return err; + mboxd = create_workqueue("mboxd"); if (!mboxd) return -ENOMEM; + /* kfifo size sanity check: alignment and minimal size */ + mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); + mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t)); + return 0; } -module_init(omap_mbox_init); +subsys_initcall(omap_mbox_init); static void __exit omap_mbox_exit(void) { destroy_workqueue(mboxd); + class_unregister(&omap_mbox_class); } module_exit(omap_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); -MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU"); +MODULE_AUTHOR("Toshihiro Kobayashi"); +MODULE_AUTHOR("Hiroshi DOYU"); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 7e669c9744d..e31496e35b0 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -481,9 +481,9 @@ int omap_st_is_enabled(unsigned int id) EXPORT_SYMBOL(omap_st_is_enabled); /* - * omap_mcbsp_set_tx_threshold configures how to deal - * with transmit threshold. the threshold value and handler can be - * configure in here. + * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. + * The threshold parameter is 1 based, and it is converted (threshold - 1) + * for the THRSH2 register. */ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) { @@ -498,14 +498,15 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) } mcbsp = id_to_mcbsp_ptr(id); - MCBSP_WRITE(mcbsp, THRSH2, threshold); + if (threshold && threshold <= mcbsp->max_tx_thres) + MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); } EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); /* - * omap_mcbsp_set_rx_threshold configures how to deal - * with receive threshold. the threshold value and handler can be - * configure in here. + * omap_mcbsp_set_rx_threshold configures the receive threshold in words. + * The threshold parameter is 1 based, and it is converted (threshold - 1) + * for the THRSH1 register. */ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) { @@ -520,7 +521,8 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) } mcbsp = id_to_mcbsp_ptr(id); - MCBSP_WRITE(mcbsp, THRSH1, threshold); + if (threshold && threshold <= mcbsp->max_rx_thres) + MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); } EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); @@ -560,8 +562,20 @@ u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) } EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold); -#define MCBSP2_FIFO_SIZE 0x500 /* 1024 + 256 locations */ -#define MCBSP1345_FIFO_SIZE 0x80 /* 128 locations */ +u16 omap_mcbsp_get_fifo_size(unsigned int id) +{ + struct omap_mcbsp *mcbsp; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + return mcbsp->pdata->buffer_size; +} +EXPORT_SYMBOL(omap_mcbsp_get_fifo_size); + /* * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO */ @@ -580,10 +594,7 @@ u16 omap_mcbsp_get_tx_delay(unsigned int id) buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); /* Number of slots are different in McBSP ports */ - if (mcbsp->id == 2) - return MCBSP2_FIFO_SIZE - buffstat; - else - return MCBSP1345_FIFO_SIZE - buffstat; + return mcbsp->pdata->buffer_size - buffstat; } EXPORT_SYMBOL(omap_mcbsp_get_tx_delay); @@ -1683,8 +1694,16 @@ static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) { mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; if (cpu_is_omap34xx()) { - mcbsp->max_tx_thres = max_thres(mcbsp); - mcbsp->max_rx_thres = max_thres(mcbsp); + /* + * Initially configure the maximum thresholds to a safe value. + * The McBSP FIFO usage with these values should not go under + * 16 locations. + * If the whole FIFO without safety buffer is used, than there + * is a possibility that the DMA will be not able to push the + * new data on time, causing channel shifts in runtime. + */ + mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; + mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; /* * REVISIT: Set dmap_op_mode to THRESHOLD as default * for mcbsp2 instances. diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 06703635ace..0d4aa0d5876 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c @@ -54,7 +54,7 @@ int __init_or_module omap_cfg_reg(const unsigned long index) { struct pin_config *reg; - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + if (!cpu_class_is_omap1()) { printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", index); WARN_ON(1); diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index 186bca82cfa..e129ce80c53 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -34,11 +34,11 @@ struct omap_opp *l3_opps; * Device-driver-originated constraints (via board-*.c files) */ -void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) +int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) { if (!dev || t < -1) { - WARN_ON(1); - return; + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; }; if (t == -1) @@ -58,14 +58,16 @@ void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t) * * TI CDP code can call constraint_set here. */ + + return 0; } -void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) +int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) { if (!dev || (agent_id != OCP_INITIATOR_AGENT && agent_id != OCP_TARGET_AGENT)) { - WARN_ON(1); - return; + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; }; if (r == 0) @@ -83,13 +85,16 @@ void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r) * * TI CDP code can call constraint_set here on the VDD2 OPP. */ + + return 0; } -void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) +int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev, + long t) { - if (!dev || t < -1) { - WARN_ON(1); - return; + if (!req_dev || !dev || t < -1) { + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; }; if (t == -1) @@ -111,13 +116,15 @@ void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t) * * TI CDP code can call constraint_set here. */ + + return 0; } -void omap_pm_set_max_sdma_lat(struct device *dev, long t) +int omap_pm_set_max_sdma_lat(struct device *dev, long t) { if (!dev || t < -1) { - WARN_ON(1); - return; + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; }; if (t == -1) @@ -139,8 +146,36 @@ void omap_pm_set_max_sdma_lat(struct device *dev, long t) * TI CDP code can call constraint_set here. */ + return 0; } +int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r) +{ + if (!dev || !c || r < 0) { + WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__); + return -EINVAL; + } + + if (r == 0) + pr_debug("OMAP PM: remove min clk rate constraint: " + "dev %s\n", dev_name(dev)); + else + pr_debug("OMAP PM: add min clk rate constraint: " + "dev %s, rate = %ld Hz\n", dev_name(dev), r); + + /* + * Code in a real implementation should keep track of these + * constraints on the clock, and determine the highest minimum + * clock rate. It should iterate over each OPP and determine + * whether the OPP will result in a clock rate that would + * satisfy this constraint (and any other PM constraint in effect + * at that time). Once it finds the lowest-voltage OPP that + * meets those conditions, it should switch to it, or return + * an error if the code is not capable of doing so. + */ + + return 0; +} /* * DSP Bridge-specific constraints diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index f899603051a..d2b160942cc 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -1,7 +1,7 @@ /* * omap_device implementation * - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Nokia Corporation * Paul Walmsley, Kevin Hilman * * Developed in collaboration with (alphabetical order): Benoit @@ -90,8 +90,11 @@ #define USE_WAKEUP_LAT 0 #define IGNORE_WAKEUP_LAT 1 - -#define OMAP_DEVICE_MAGIC 0xf00dcafe +/* + * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device + * obtained via container_of() is in fact a struct omap_device + */ +#define OMAP_DEVICE_MAGIC 0xf00dcafe /* Private functions */ @@ -359,7 +362,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, struct omap_device *od; char *pdev_name2; struct resource *res = NULL; - int res_count; + int i, res_count; struct omap_hwmod **hwmods; if (!ohs || oh_cnt == 0 || !pdev_name) @@ -404,7 +407,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, od->pdev.num_resources = res_count; od->pdev.resource = res; - platform_device_add_data(&od->pdev, pdata, pdata_len); + ret = platform_device_add_data(&od->pdev, pdata, pdata_len); + if (ret) + goto odbs_exit4; od->pm_lats = pm_lats; od->pm_lats_cnt = pm_lats_cnt; @@ -416,6 +421,9 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, else ret = omap_device_register(od); + for (i = 0; i < oh_cnt; i++) + hwmods[i]->od = od; + if (ret) goto odbs_exit4; @@ -652,6 +660,25 @@ struct powerdomain *omap_device_get_pwrdm(struct omap_device *od) return omap_hwmod_get_pwrdm(od->hwmods[0]); } +/** + * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base + * @od: struct omap_device * + * + * Return the MPU's virtual address for the base of the hwmod, from + * the ioremap() that the hwmod code does. Only valid if there is one + * hwmod associated with this device. Returns NULL if there are zero + * or more than one hwmods associated with this omap_device; + * otherwise, passes along the return value from + * omap_hwmod_get_mpu_rt_va(). + */ +void __iomem *omap_device_get_rt_va(struct omap_device *od) +{ + if (od->hwmods_cnt != 1) + return NULL; + + return omap_hwmod_get_mpu_rt_va(od->hwmods[0]); +} + /* * Public functions intended for use in omap_device_pm_latency * .activate_func and .deactivate_func function pointers diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index d3bf17cd36f..f3570884883 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -22,524 +22,13 @@ #include <linux/module.h> #include <linux/kernel.h> -#include <linux/types.h> -#include <linux/errno.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/usb/otg.h> #include <linux/io.h> -#include <asm/irq.h> -#include <asm/system.h> -#include <mach/hardware.h> - -#include <plat/control.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> -#ifdef CONFIG_ARCH_OMAP1 - -#define INT_USB_IRQ_GEN IH2_BASE + 20 -#define INT_USB_IRQ_NISO IH2_BASE + 30 -#define INT_USB_IRQ_ISO IH2_BASE + 29 -#define INT_USB_IRQ_HGEN INT_USB_HHC_1 -#define INT_USB_IRQ_OTG IH2_BASE + 8 - -#else - -#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN -#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO -#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO -#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN -#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG - -#endif - - -/* These routines should handle the standard chip-specific modes - * for usb0/1/2 ports, covering basic mux and transceiver setup. - * - * Some board-*.c files will need to set up additional mux options, - * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. - */ - -/* TESTED ON: - * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables - * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables - * - 5912 OSK UDC, with *nonstandard* A-to-A cable - * - 1510 Innovator UDC with bundled usb0 cable - * - 1510 Innovator OHCI with bundled usb1/usb2 cable - * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS - * - 1710 custom development board using alternate pin group - * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables - */ - -/*-------------------------------------------------------------------------*/ - -#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) - -static void omap2_usb_devconf_clear(u8 port, u32 mask) -{ - u32 r; - - r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - r &= ~USBTXWRMODEI(port, mask); - omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); -} - -static void omap2_usb_devconf_set(u8 port, u32 mask) -{ - u32 r; - - r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - r |= USBTXWRMODEI(port, mask); - omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); -} - -static void omap2_usb2_disable_5pinbitll(void) -{ - u32 r; - - r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); - omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); -} - -static void omap2_usb2_enable_5pinunitll(void) -{ - u32 r; - - r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; - omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); -} - -static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) -{ - u32 syscon1 = 0; - - if (cpu_is_omap24xx()) - omap2_usb_devconf_clear(0, USB_BIDIR_TLL); - - if (nwires == 0) { - if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { - u32 l; - - /* pulldown D+/D- */ - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~(3 << 1); - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - return 0; - } - - if (is_device) { - if (cpu_is_omap24xx()) - omap_cfg_reg(J20_24XX_USB0_PUEN); - else if (cpu_is_omap7xx()) { - omap_cfg_reg(AA17_7XX_USB_DM); - omap_cfg_reg(W16_7XX_USB_PU_EN); - omap_cfg_reg(W17_7XX_USB_VBUSI); - omap_cfg_reg(W18_7XX_USB_DMCK_OUT); - omap_cfg_reg(W19_7XX_USB_DCRST); - } else - omap_cfg_reg(W4_USB_PUEN); - } - - /* internal transceiver (unavailable on 17xx, 24xx) */ - if (!cpu_class_is_omap2() && nwires == 2) { - u32 l; - - // omap_cfg_reg(P9_USB_DP); - // omap_cfg_reg(R8_USB_DM); - - if (cpu_is_omap15xx()) { - /* This works on 1510-Innovator */ - return 0; - } - - /* NOTES: - * - peripheral should configure VBUS detection! - * - only peripherals may use the internal D+/D- pulldowns - * - OTG support on this port not yet written - */ - - /* Don't do this for omap7xx -- it causes USB to not work correctly */ - if (!cpu_is_omap7xx()) { - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~(7 << 4); - if (!is_device) - l |= (3 << 1); - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - - return 3 << 16; - } - - /* alternate pin config, external transceiver */ - if (cpu_is_omap15xx()) { - printk(KERN_ERR "no usb0 alt pin config on 15xx\n"); - return 0; - } - - if (cpu_is_omap24xx()) { - omap_cfg_reg(K18_24XX_USB0_DAT); - omap_cfg_reg(K19_24XX_USB0_TXEN); - omap_cfg_reg(J14_24XX_USB0_SE0); - if (nwires != 3) - omap_cfg_reg(J18_24XX_USB0_RCV); - } else { - omap_cfg_reg(V6_USB0_TXD); - omap_cfg_reg(W9_USB0_TXEN); - omap_cfg_reg(W5_USB0_SE0); - if (nwires != 3) - omap_cfg_reg(Y5_USB0_RCV); - } - - /* NOTE: SPEED and SUSP aren't configured here. OTG hosts - * may be able to use I2C requests to set those bits along - * with VBUS switching and overcurrent detection. - */ - - if (cpu_class_is_omap1() && nwires != 6) { - u32 l; - - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~CONF_USB2_UNI_R; - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - - switch (nwires) { - case 3: - syscon1 = 2; - if (cpu_is_omap24xx()) - omap2_usb_devconf_set(0, USB_BIDIR); - break; - case 4: - syscon1 = 1; - if (cpu_is_omap24xx()) - omap2_usb_devconf_set(0, USB_BIDIR); - break; - case 6: - syscon1 = 3; - if (cpu_is_omap24xx()) { - omap_cfg_reg(J19_24XX_USB0_VP); - omap_cfg_reg(K20_24XX_USB0_VM); - omap2_usb_devconf_set(0, USB_UNIDIR); - } else { - u32 l; - - omap_cfg_reg(AA9_USB0_VP); - omap_cfg_reg(R9_USB0_VM); - l = omap_readl(USB_TRANSCEIVER_CTRL); - l |= CONF_USB2_UNI_R; - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - break; - default: - printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", - 0, nwires); - } - return syscon1 << 16; -} - -static u32 __init omap_usb1_init(unsigned nwires) -{ - u32 syscon1 = 0; - - if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { - u32 l; - - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~CONF_USB1_UNI_R; - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - if (cpu_is_omap24xx()) - omap2_usb_devconf_clear(1, USB_BIDIR_TLL); - - if (nwires == 0) - return 0; - - /* external transceiver */ - if (cpu_class_is_omap1()) { - omap_cfg_reg(USB1_TXD); - omap_cfg_reg(USB1_TXEN); - if (nwires != 3) - omap_cfg_reg(USB1_RCV); - } - - if (cpu_is_omap15xx()) { - omap_cfg_reg(USB1_SEO); - omap_cfg_reg(USB1_SPEED); - // SUSP - } else if (cpu_is_omap1610() || cpu_is_omap5912()) { - omap_cfg_reg(W13_1610_USB1_SE0); - omap_cfg_reg(R13_1610_USB1_SPEED); - // SUSP - } else if (cpu_is_omap1710()) { - omap_cfg_reg(R13_1710_USB1_SE0); - // SUSP - } else if (cpu_is_omap24xx()) { - /* NOTE: board-specific code must set up pin muxing for usb1, - * since each signal could come out on either of two balls. - */ - } else { - pr_debug("usb%d cpu unrecognized\n", 1); - return 0; - } - - switch (nwires) { - case 2: - if (!cpu_is_omap24xx()) - goto bad; - /* NOTE: board-specific code must override this setting if - * this TLL link is not using DP/DM - */ - syscon1 = 1; - omap2_usb_devconf_set(1, USB_BIDIR_TLL); - break; - case 3: - syscon1 = 2; - if (cpu_is_omap24xx()) - omap2_usb_devconf_set(1, USB_BIDIR); - break; - case 4: - syscon1 = 1; - if (cpu_is_omap24xx()) - omap2_usb_devconf_set(1, USB_BIDIR); - break; - case 6: - if (cpu_is_omap24xx()) - goto bad; - syscon1 = 3; - omap_cfg_reg(USB1_VP); - omap_cfg_reg(USB1_VM); - if (!cpu_is_omap15xx()) { - u32 l; - - l = omap_readl(USB_TRANSCEIVER_CTRL); - l |= CONF_USB1_UNI_R; - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - break; - default: -bad: - printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", - 1, nwires); - } - return syscon1 << 20; -} - -static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) -{ - u32 syscon1 = 0; - - if (cpu_is_omap24xx()) { - omap2_usb2_disable_5pinbitll(); - alt_pingroup = 0; - } - - /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ - if (alt_pingroup || nwires == 0) - return 0; - - if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { - u32 l; - - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~CONF_USB2_UNI_R; - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - - /* external transceiver */ - if (cpu_is_omap15xx()) { - omap_cfg_reg(USB2_TXD); - omap_cfg_reg(USB2_TXEN); - omap_cfg_reg(USB2_SEO); - if (nwires != 3) - omap_cfg_reg(USB2_RCV); - /* there is no USB2_SPEED */ - } else if (cpu_is_omap16xx()) { - omap_cfg_reg(V6_USB2_TXD); - omap_cfg_reg(W9_USB2_TXEN); - omap_cfg_reg(W5_USB2_SE0); - if (nwires != 3) - omap_cfg_reg(Y5_USB2_RCV); - // FIXME omap_cfg_reg(USB2_SPEED); - } else if (cpu_is_omap24xx()) { - omap_cfg_reg(Y11_24XX_USB2_DAT); - omap_cfg_reg(AA10_24XX_USB2_SE0); - if (nwires > 2) - omap_cfg_reg(AA12_24XX_USB2_TXEN); - if (nwires > 3) - omap_cfg_reg(AA6_24XX_USB2_RCV); - } else { - pr_debug("usb%d cpu unrecognized\n", 1); - return 0; - } - // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP); - - switch (nwires) { - case 2: - if (!cpu_is_omap24xx()) - goto bad; - /* NOTE: board-specific code must override this setting if - * this TLL link is not using DP/DM - */ - syscon1 = 1; - omap2_usb_devconf_set(2, USB_BIDIR_TLL); - break; - case 3: - syscon1 = 2; - if (cpu_is_omap24xx()) - omap2_usb_devconf_set(2, USB_BIDIR); - break; - case 4: - syscon1 = 1; - if (cpu_is_omap24xx()) - omap2_usb_devconf_set(2, USB_BIDIR); - break; - case 5: - if (!cpu_is_omap24xx()) - goto bad; - omap_cfg_reg(AA4_24XX_USB2_TLLSE0); - /* NOTE: board-specific code must override this setting if - * this TLL link is not using DP/DM. Something must also - * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} - */ - syscon1 = 3; - omap2_usb2_enable_5pinunitll(); - break; - case 6: - if (cpu_is_omap24xx()) - goto bad; - syscon1 = 3; - if (cpu_is_omap15xx()) { - omap_cfg_reg(USB2_VP); - omap_cfg_reg(USB2_VM); - } else { - u32 l; - - omap_cfg_reg(AA9_USB2_VP); - omap_cfg_reg(R9_USB2_VM); - l = omap_readl(USB_TRANSCEIVER_CTRL); - l |= CONF_USB2_UNI_R; - omap_writel(l, USB_TRANSCEIVER_CTRL); - } - break; - default: -bad: - printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", - 2, nwires); - } - return syscon1 << 24; -} - -#endif - -/*-------------------------------------------------------------------------*/ - -#ifdef CONFIG_USB_GADGET_OMAP - -static struct resource udc_resources[] = { - /* order is significant! */ - { /* registers */ - .start = UDC_BASE, - .end = UDC_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { /* general IRQ */ - .start = INT_USB_IRQ_GEN, - .flags = IORESOURCE_IRQ, - }, { /* PIO IRQ */ - .start = INT_USB_IRQ_NISO, - .flags = IORESOURCE_IRQ, - }, { /* SOF IRQ */ - .start = INT_USB_IRQ_ISO, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 udc_dmamask = ~(u32)0; - -static struct platform_device udc_device = { - .name = "omap_udc", - .id = -1, - .dev = { - .dma_mask = &udc_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(udc_resources), - .resource = udc_resources, -}; - -#endif - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - -/* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = ~(u32)0; - -static struct resource ohci_resources[] = { - { - .start = OMAP_OHCI_BASE, - .end = OMAP_OHCI_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_USB_IRQ_HGEN, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci_device = { - .name = "ohci", - .id = -1, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(ohci_resources), - .resource = ohci_resources, -}; - -#endif - -#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) - -static struct resource otg_resources[] = { - /* order is significant! */ - { - .start = OTG_BASE, - .end = OTG_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = INT_USB_IRQ_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device otg_device = { - .name = "omap_otg", - .id = -1, - .num_resources = ARRAY_SIZE(otg_resources), - .resource = otg_resources, -}; - -#endif - -/*-------------------------------------------------------------------------*/ - -// FIXME correct answer depends on hmc_mode, -// as does (on omap1) any nonzero value for config->otg port number -#ifdef CONFIG_USB_GADGET_OMAP -#define is_usb0_device(config) 1 -#else -#define is_usb0_device(config) 0 -#endif - -/*-------------------------------------------------------------------------*/ - #ifdef CONFIG_ARCH_OMAP_OTG void __init @@ -560,9 +49,9 @@ omap_otg_init(struct omap_usb_config *config) /* pin muxing and transceiver pinouts */ if (config->pins[0] > 2) /* alt pingroup 2 */ alt_pingroup = 1; - syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); - syscon |= omap_usb1_init(config->pins[1]); - syscon |= omap_usb2_init(config->pins[2], alt_pingroup); + syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); + syscon |= config->usb1_init(config->pins[1]); + syscon |= config->usb2_init(config->pins[2], alt_pingroup); pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); @@ -610,15 +99,11 @@ omap_otg_init(struct omap_usb_config *config) #ifdef CONFIG_USB_GADGET_OMAP if (config->otg || config->register_dev) { + struct platform_device *udc_device = config->udc_device; + syscon &= ~DEV_IDLE_EN; - udc_device.dev.platform_data = config; - /* IRQ numbers for omap7xx */ - if(cpu_is_omap7xx()) { - udc_resources[1].start = INT_7XX_USB_GENI; - udc_resources[2].start = INT_7XX_USB_NON_ISO; - udc_resources[3].start = INT_7XX_USB_ISO; - } - status = platform_device_register(&udc_device); + udc_device->dev.platform_data = config; + status = platform_device_register(udc_device); if (status) pr_debug("can't register UDC device, %d\n", status); } @@ -626,11 +111,11 @@ omap_otg_init(struct omap_usb_config *config) #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) if (config->otg || config->register_host) { + struct platform_device *ohci_device = config->ohci_device; + syscon &= ~HST_IDLE_EN; - ohci_device.dev.platform_data = config; - if (cpu_is_omap7xx()) - ohci_resources[1].start = INT_7XX_USB_HHC_1; - status = platform_device_register(&ohci_device); + ohci_device->dev.platform_data = config; + status = platform_device_register(ohci_device); if (status) pr_debug("can't register OHCI device, %d\n", status); } @@ -638,11 +123,11 @@ omap_otg_init(struct omap_usb_config *config) #ifdef CONFIG_USB_OTG if (config->otg) { + struct platform_device *otg_device = config->otg_device; + syscon &= ~OTG_IDLE_EN; - otg_device.dev.platform_data = config; - if (cpu_is_omap7xx()) - otg_resources[1].start = INT_7XX_USB_OTG; - status = platform_device_register(&otg_device); + otg_device->dev.platform_data = config; + status = platform_device_register(otg_device); if (status) pr_debug("can't register OTG device, %d\n", status); } @@ -654,102 +139,5 @@ omap_otg_init(struct omap_usb_config *config) } #else -static inline void omap_otg_init(struct omap_usb_config *config) {} -#endif - -/*-------------------------------------------------------------------------*/ - -#ifdef CONFIG_ARCH_OMAP15XX - -/* ULPD_DPLL_CTRL */ -#define DPLL_IOB (1 << 13) -#define DPLL_PLL_ENABLE (1 << 4) -#define DPLL_LOCK (1 << 0) - -/* ULPD_APLL_CTRL */ -#define APLL_NDPLL_SWITCH (1 << 0) - - -static void __init omap_1510_usb_init(struct omap_usb_config *config) -{ - unsigned int val; - u16 w; - - omap_usb0_init(config->pins[0], is_usb0_device(config)); - omap_usb1_init(config->pins[1]); - omap_usb2_init(config->pins[2], 0); - - val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1); - val |= (config->hmc_mode << 1); - omap_writel(val, MOD_CONF_CTRL_0); - - printk("USB: hmc %d", config->hmc_mode); - if (config->pins[0]) - printk(", usb0 %d wires%s", config->pins[0], - is_usb0_device(config) ? " (dev)" : ""); - if (config->pins[1]) - printk(", usb1 %d wires", config->pins[1]); - if (config->pins[2]) - printk(", usb2 %d wires", config->pins[2]); - printk("\n"); - - /* use DPLL for 48 MHz function clock */ - pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), - omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ)); - - w = omap_readw(ULPD_APLL_CTRL); - w &= ~APLL_NDPLL_SWITCH; - omap_writew(w, ULPD_APLL_CTRL); - - w = omap_readw(ULPD_DPLL_CTRL); - w |= DPLL_IOB | DPLL_PLL_ENABLE; - omap_writew(w, ULPD_DPLL_CTRL); - - w = omap_readw(ULPD_SOFT_REQ); - w |= SOFT_UDC_REQ | SOFT_DPLL_REQ; - omap_writew(w, ULPD_SOFT_REQ); - - while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) - cpu_relax(); - -#ifdef CONFIG_USB_GADGET_OMAP - if (config->register_dev) { - int status; - - udc_device.dev.platform_data = config; - status = platform_device_register(&udc_device); - if (status) - pr_debug("can't register UDC device, %d\n", status); - /* udc driver gates 48MHz by D+ pullup */ - } -#endif - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - if (config->register_host) { - int status; - - ohci_device.dev.platform_data = config; - status = platform_device_register(&ohci_device); - if (status) - pr_debug("can't register OHCI device, %d\n", status); - /* hcd explicitly gates 48MHz */ - } -#endif -} - -#else -static inline void omap_1510_usb_init(struct omap_usb_config *config) {} +void omap_otg_init(struct omap_usb_config *config) {} #endif - -/*-------------------------------------------------------------------------*/ - -void __init omap_usb_init(struct omap_usb_config *pdata) -{ - if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) - omap_otg_init(pdata); - else if (cpu_is_omap15xx()) - omap_1510_usb_init(pdata); - else - printk(KERN_ERR "USB: No init for your chip yet\n"); -} - diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h new file mode 100644 index 00000000000..9cf1f781329 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/audio.h @@ -0,0 +1,11 @@ +#ifndef __PLAT_AUDIO_H +#define __PLAT_AUDIO_H + +#include <linux/mbus.h> + +struct kirkwood_asoc_platform_data { + u32 tclk; + struct mbus_dram_target_info *dram; + int burst; +}; +#endif diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index a17cc0c6a6b..4aacdd12c9c 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile @@ -4,7 +4,6 @@ obj-y := dma.o -obj-$(CONFIG_ARCH_PXA) += pmu.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o diff --git a/arch/arm/plat-pxa/pmu.c b/arch/arm/plat-pxa/pmu.c deleted file mode 100644 index 267ceb6feb2..00000000000 --- a/arch/arm/plat-pxa/pmu.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * PMU IRQ registration for the PXA xscale PMU families. - * Copyright (C) 2010 Will Deacon, ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/platform_device.h> -#include <asm/pmu.h> -#include <mach/irqs.h> - -static struct resource pmu_resource = { - .start = IRQ_PMU, - .end = IRQ_PMU, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device pmu_device = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .resource = &pmu_resource, - .num_resources = 1, -}; - -static int __init pxa_pmu_init(void) -{ - platform_device_register(&pmu_device); - return 0; -} -arch_initcall(pxa_pmu_init); diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 11d6a1bbd90..c6a855db2fb 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -7,9 +7,10 @@ config PLAT_S5P bool - depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210) + depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310) default y - select ARM_VIC + select ARM_VIC if !ARCH_S5PV310 + select ARM_GIC if ARCH_S5PV310 select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_GPIO_TRACK @@ -30,3 +31,18 @@ config S5P_EXT_INT help Use the external interrupts (other than GPIO interrupts.) Note: Do not choose this for S5P6440. + +config S5P_DEV_FIMC0 + bool + help + Compile in platform device definitions for FIMC controller 0 + +config S5P_DEV_FIMC1 + bool + help + Compile in platform device definitions for FIMC controller 1 + +config S5P_DEV_FIMC2 + bool + help + Compile in platform device definitions for FIMC controller 2 diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 39c242bb9d5..b2e02967395 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -12,9 +12,15 @@ obj- := # Core files +obj-y += dev-pmu.o obj-y += dev-uart.o obj-y += cpu.o obj-y += clock.o obj-y += irq.o obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o +# devices + +obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o +obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o +obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 75cb8c37ca2..b07a078fd28 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -21,6 +21,7 @@ #include <plat/s5p6442.h> #include <plat/s5pc100.h> #include <plat/s5pv210.h> +#include <plat/s5pv310.h> /* table of supported CPUs */ @@ -28,6 +29,7 @@ static const char name_s5p6440[] = "S5P6440"; static const char name_s5p6442[] = "S5P6442"; static const char name_s5pc100[] = "S5PC100"; static const char name_s5pv210[] = "S5PV210/S5PC110"; +static const char name_s5pv310[] = "S5PV310"; static struct cpu_table cpu_ids[] __initdata = { { @@ -62,6 +64,14 @@ static struct cpu_table cpu_ids[] __initdata = { .init_uarts = s5pv210_init_uarts, .init = s5pv210_init, .name = name_s5pv210, + }, { + .idcode = 0x43200000, + .idmask = 0xfffff000, + .map_io = s5pv310_map_io, + .init_clocks = s5pv310_init_clocks, + .init_uarts = s5pv310_init_uarts, + .init = s5pv310_init, + .name = name_s5pv310, }, }; @@ -81,8 +91,9 @@ static struct map_desc s5p_iodesc[] __initdata = { }, { .virtual = (unsigned long)S3C_VA_UART, .pfn = __phys_to_pfn(S3C_PA_UART), - .length = SZ_4K, + .length = SZ_512K, .type = MT_DEVICE, +#ifdef CONFIG_ARM_VIC }, { .virtual = (unsigned long)VA_VIC0, .pfn = __phys_to_pfn(S5P_PA_VIC0), @@ -93,6 +104,7 @@ static struct map_desc s5p_iodesc[] __initdata = { .pfn = __phys_to_pfn(S5P_PA_VIC1), .length = SZ_16K, .type = MT_DEVICE, +#endif }, { .virtual = (unsigned long)S3C_VA_TIMER, .pfn = __phys_to_pfn(S5P_PA_TIMER), @@ -103,6 +115,11 @@ static struct map_desc s5p_iodesc[] __initdata = { .pfn = __phys_to_pfn(S5P_PA_GPIO), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(S3C_PA_WDT), + .length = SZ_4K, + .type = MT_DEVICE, }, }; diff --git a/arch/arm/plat-s5p/dev-fimc0.c b/arch/arm/plat-s5p/dev-fimc0.c new file mode 100644 index 00000000000..d3f1a9b5d2b --- /dev/null +++ b/arch/arm/plat-s5p/dev-fimc0.c @@ -0,0 +1,36 @@ +/* linux/arch/arm/plat-s5p/dev-fimc0.c + * + * Copyright (c) 2010 Samsung Electronics + * + * Base S5P FIMC0 resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <mach/map.h> + +static struct resource s5p_fimc0_resource[] = { + [0] = { + .start = S5P_PA_FIMC0, + .end = S5P_PA_FIMC0 + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC0, + .end = IRQ_FIMC0, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_fimc0 = { + .name = "s5p-fimc", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_fimc0_resource), + .resource = s5p_fimc0_resource, +}; diff --git a/arch/arm/plat-s5p/dev-fimc1.c b/arch/arm/plat-s5p/dev-fimc1.c new file mode 100644 index 00000000000..41bd6986d0a --- /dev/null +++ b/arch/arm/plat-s5p/dev-fimc1.c @@ -0,0 +1,36 @@ +/* linux/arch/arm/plat-s5p/dev-fimc1.c + * + * Copyright (c) 2010 Samsung Electronics + * + * Base S5P FIMC1 resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <mach/map.h> + +static struct resource s5p_fimc1_resource[] = { + [0] = { + .start = S5P_PA_FIMC1, + .end = S5P_PA_FIMC1 + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC1, + .end = IRQ_FIMC1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_fimc1 = { + .name = "s5p-fimc", + .id = 1, + .num_resources = ARRAY_SIZE(s5p_fimc1_resource), + .resource = s5p_fimc1_resource, +}; diff --git a/arch/arm/plat-s5p/dev-fimc2.c b/arch/arm/plat-s5p/dev-fimc2.c new file mode 100644 index 00000000000..dfddeda6d4a --- /dev/null +++ b/arch/arm/plat-s5p/dev-fimc2.c @@ -0,0 +1,36 @@ +/* linux/arch/arm/plat-s5p/dev-fimc2.c + * + * Copyright (c) 2010 Samsung Electronics + * + * Base S5P FIMC2 resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <mach/map.h> + +static struct resource s5p_fimc2_resource[] = { + [0] = { + .start = S5P_PA_FIMC2, + .end = S5P_PA_FIMC2 + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_FIMC2, + .end = IRQ_FIMC2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_fimc2 = { + .name = "s5p-fimc", + .id = 2, + .num_resources = ARRAY_SIZE(s5p_fimc2_resource), + .resource = s5p_fimc2_resource, +}; diff --git a/arch/arm/plat-s5p/dev-pmu.c b/arch/arm/plat-s5p/dev-pmu.c new file mode 100644 index 00000000000..a08576da72b --- /dev/null +++ b/arch/arm/plat-s5p/dev-pmu.c @@ -0,0 +1,36 @@ +/* + * linux/arch/arm/plat-s5p/dev-pmu.c + * + * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/platform_device.h> +#include <asm/pmu.h> +#include <mach/irqs.h> + +static struct resource s5p_pmu_resource = { + .start = IRQ_PMU, + .end = IRQ_PMU, + .flags = IORESOURCE_IRQ, +}; + +struct platform_device s5p_device_pmu = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = 1, + .resource = &s5p_pmu_resource, +}; + +static int __init s5p_pmu_init(void) +{ + platform_device_register(&s5p_device_pmu); + return 0; +} +arch_initcall(s5p_pmu_init); diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index 14828521f70..c4ff88bf647 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -17,13 +17,30 @@ #define S5P_VA_GPIO S3C_ADDR(0x00500000) #define S5P_VA_SYSTIMER S3C_ADDR(0x01200000) #define S5P_VA_SROMC S3C_ADDR(0x01100000) +#define S5P_VA_SYSRAM S3C_ADDR(0x01180000) -#define S5P_VA_UART0 (S3C_VA_UART + 0x0) -#define S5P_VA_UART1 (S3C_VA_UART + 0x400) -#define S5P_VA_UART2 (S3C_VA_UART + 0x800) -#define S5P_VA_UART3 (S3C_VA_UART + 0xC00) +#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000) +#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10) +#define S5P_VA_COREPERI_BASE S3C_ADDR(0x00800000) +#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x)) +#define S5P_VA_SCU S5P_VA_COREPERI(0x0) +#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100) +#define S5P_VA_TWD S5P_VA_COREPERI(0x600) +#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) + +#define S5P_VA_L2CC S3C_ADDR(0x00900000) +#define S5P_VA_CMU S3C_ADDR(0x00920000) + +#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) +#define S5P_VA_UART0 S5P_VA_UART(0) +#define S5P_VA_UART1 S5P_VA_UART(1) +#define S5P_VA_UART2 S5P_VA_UART(2) +#define S5P_VA_UART3 S5P_VA_UART(3) + +#ifndef S3C_UART_OFFSET #define S3C_UART_OFFSET (0x400) +#endif #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index 7db322726bc..4e8fe08cb70 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -46,6 +46,47 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, return (unsigned long)fvco; } +#define PLL46XX_KDIV_MASK (0xFFFF) +#define PLL46XX_MDIV_MASK (0x1FF) +#define PLL46XX_PDIV_MASK (0x3F) +#define PLL46XX_SDIV_MASK (0x7) +#define PLL46XX_MDIV_SHIFT (16) +#define PLL46XX_PDIV_SHIFT (8) +#define PLL46XX_SDIV_SHIFT (0) + +enum pll46xx_type_t { + pll_4600, + pll_4650, +}; + +static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, + u32 pll_con0, u32 pll_con1, + enum pll46xx_type_t pll_type) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; + kdiv = pll_con1 & PLL46XX_KDIV_MASK; + + tmp = baseclk; + + if (pll_type == pll_4600) { + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + } else { + tmp *= (mdiv << 10) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 10; + } + + return result; +} + #define PLL90XX_MDIV_MASK (0xFF) #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7) diff --git a/arch/arm/plat-s5p/include/plat/reset.h b/arch/arm/plat-s5p/include/plat/reset.h new file mode 100644 index 00000000000..335e97812ee --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/reset.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/plat-s5p/include/plat/reset.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_RESET_H +#define __ASM_PLAT_S5P_RESET_H __FILE__ + +extern void (*s5p_reset_hook)(void); + +#endif /* __ASM_PLAT_S5P_RESET_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5pv310.h b/arch/arm/plat-s5p/include/plat/s5pv310.h new file mode 100644 index 00000000000..769c991ceb3 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5pv310.h @@ -0,0 +1,34 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5pv310 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S5PV310 related SoCs */ + +extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5pv310_register_clocks(void); +extern void s5pv310_setup_clocks(void); + +#ifdef CONFIG_CPU_S5PV310 + +extern int s5pv310_init(void); +extern void s5pv310_init_irq(void); +extern void s5pv310_map_io(void); +extern void s5pv310_init_clocks(int xtal); +extern struct sys_timer s5pv310_timer; + +#define s5pv310_init_uarts s5pv310_common_init_uarts + +#else +#define s5pv310_init_clocks NULL +#define s5pv310_init_uarts NULL +#define s5pv310_map_io NULL +#define s5pv310_init NULL +#endif diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h new file mode 100644 index 00000000000..f307f34e642 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/system-reset.h @@ -0,0 +1,31 @@ +/* linux/arch/arm/plat-s5p/include/plat/system-reset.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h + * + * S5P - System define for arch_reset() + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <plat/watchdog-reset.h> + +void (*s5p_reset_hook)(void); + +static void arch_reset(char mode, const char *cmd) +{ + /* SWRESET support in s5p_reset_hook() */ + + if (s5p_reset_hook) + s5p_reset_hook(); + + /* Perform reset using Watchdog reset + * if there is no s5p_reset_hook() + */ + + arch_wdt_reset(); +} diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index 25e1eb6de59..5560b12035d 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -56,11 +56,13 @@ static struct s3c_uart_irq uart_irqs[] = { void __init s5p_init_irq(u32 *vic, u32 num_vic) { +#ifdef CONFIG_ARM_VIC int irq; /* initialize the VICs */ for (irq = 0; irq < num_vic; irq++) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); +#endif s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 2753fb3e4f7..7c0bde78116 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -6,7 +6,7 @@ config PLAT_SAMSUNG bool - depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX + depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P select NO_IOPORT default y help @@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2 help Compile in platform device definitions for HSMMC channel 2 +config S3C_DEV_HSMMC3 + bool + help + Compile in platform device definitions for HSMMC channel 3 + config S3C_DEV_HWMON bool help @@ -216,6 +221,11 @@ config SAMSUNG_DEV_ADC help Compile in platform device definition for ADC controller +config SAMSUNG_DEV_IDE + bool + help + Compile in platform device definitions for IDE + config S3C64XX_DEV_SPI bool help @@ -227,6 +237,11 @@ config SAMSUNG_DEV_TS help Common in platform device definitions for touchscreen device +config SAMSUNG_DEV_KEYPAD + bool + help + Compile in platform device definitions for keypad + # DMA config S3C_DMA diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index b1d82cc5e71..4d8ff923207 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -12,7 +12,7 @@ obj- := # Objects we always build independent of SoC choice obj-y += init.o -obj-y += time.o +obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o obj-y += clock.o obj-y += pwm-clock.o obj-y += gpio.o @@ -30,9 +30,12 @@ obj-$(CONFIG_S3C_ADC) += adc.o # devices +obj-y += platformdata.o + obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o +obj-$(CONFIG_S3C_DEV_HSMMC3) += dev-hsmmc3.o obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o obj-y += dev-i2c0.o obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o @@ -47,7 +50,9 @@ obj-$(CONFIG_S3C_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o +obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o +obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o # DMA support diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c index 4c05b39810e..9d2be094141 100644 --- a/arch/arm/plat-samsung/dev-hsmmc.c +++ b/arch/arm/plat-samsung/dev-hsmmc.c @@ -60,9 +60,16 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; set->max_width = pd->max_width; + set->cd_type = pd->cd_type; + set->ext_cd_init = pd->ext_cd_init; + set->ext_cd_cleanup = pd->ext_cd_cleanup; + set->ext_cd_gpio = pd->ext_cd_gpio; + set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; if (pd->cfg_gpio) set->cfg_gpio = pd->cfg_gpio; if (pd->cfg_card) set->cfg_card = pd->cfg_card; + if (pd->host_caps) + set->host_caps = pd->host_caps; } diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c index e49bc4cd0ee..a6c8295840a 100644 --- a/arch/arm/plat-samsung/dev-hsmmc1.c +++ b/arch/arm/plat-samsung/dev-hsmmc1.c @@ -60,9 +60,16 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; set->max_width = pd->max_width; + set->cd_type = pd->cd_type; + set->ext_cd_init = pd->ext_cd_init; + set->ext_cd_cleanup = pd->ext_cd_cleanup; + set->ext_cd_gpio = pd->ext_cd_gpio; + set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; if (pd->cfg_gpio) set->cfg_gpio = pd->cfg_gpio; if (pd->cfg_card) set->cfg_card = pd->cfg_card; + if (pd->host_caps) + set->host_caps = pd->host_caps; } diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c index 824580bc0e0..cb0d7143381 100644 --- a/arch/arm/plat-samsung/dev-hsmmc2.c +++ b/arch/arm/plat-samsung/dev-hsmmc2.c @@ -61,9 +61,16 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata; set->max_width = pd->max_width; + set->cd_type = pd->cd_type; + set->ext_cd_init = pd->ext_cd_init; + set->ext_cd_cleanup = pd->ext_cd_cleanup; + set->ext_cd_gpio = pd->ext_cd_gpio; + set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; if (pd->cfg_gpio) set->cfg_gpio = pd->cfg_gpio; if (pd->cfg_card) set->cfg_card = pd->cfg_card; + if (pd->host_caps) + set->host_caps = pd->host_caps; } diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c new file mode 100644 index 00000000000..85aaf0f2842 --- /dev/null +++ b/arch/arm/plat-samsung/dev-hsmmc3.c @@ -0,0 +1,77 @@ +/* linux/arch/arm/plat-samsung/dev-hsmmc3.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Based on arch/arm/plat-samsung/dev-hsmmc1.c + * + * Samsung device definition for hsmmc device 3 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> + +#include <mach/map.h> +#include <plat/sdhci.h> +#include <plat/devs.h> + +#define S3C_SZ_HSMMC (0x1000) + +static struct resource s3c_hsmmc3_resource[] = { + [0] = { + .start = S3C_PA_HSMMC3, + .end = S3C_PA_HSMMC3 + S3C_SZ_HSMMC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MMC3, + .end = IRQ_MMC3, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_hsmmc3_dmamask = 0xffffffffUL; + +struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), +}; + +struct platform_device s3c_device_hsmmc3 = { + .name = "s3c-sdhci", + .id = 3, + .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource), + .resource = s3c_hsmmc3_resource, + .dev = { + .dma_mask = &s3c_device_hsmmc3_dmamask, + .coherent_dma_mask = 0xffffffffUL, + .platform_data = &s3c_hsmmc3_def_platdata, + }, +}; + +void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) +{ + struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata; + + set->max_width = pd->max_width; + set->cd_type = pd->cd_type; + set->ext_cd_init = pd->ext_cd_init; + set->ext_cd_cleanup = pd->ext_cd_cleanup; + set->ext_cd_gpio = pd->ext_cd_gpio; + set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert; + + if (pd->cfg_gpio) + set->cfg_gpio = pd->cfg_gpio; + if (pd->cfg_card) + set->cfg_card = pd->cfg_card; +} diff --git a/arch/arm/plat-samsung/dev-ide.c b/arch/arm/plat-samsung/dev-ide.c new file mode 100644 index 00000000000..b497982795a --- /dev/null +++ b/arch/arm/plat-samsung/dev-ide.c @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-samsung/dev-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung CF-ATA device definition. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> + +#include <mach/map.h> +#include <plat/ata.h> +#include <plat/devs.h> + +static struct resource s3c_cfcon_resource[] = { + [0] = { + .start = SAMSUNG_PA_CFCON, + .end = SAMSUNG_PA_CFCON + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CFCON, + .end = IRQ_CFCON, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_cfcon = { + .id = 0, + .num_resources = ARRAY_SIZE(s3c_cfcon_resource), + .resource = s3c_cfcon_resource, +}; + +void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata) +{ + s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata), + &s3c_device_cfcon); +} diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c new file mode 100644 index 00000000000..677c2d731b6 --- /dev/null +++ b/arch/arm/plat-samsung/dev-keypad.c @@ -0,0 +1,50 @@ +/* + * linux/arch/arm/plat-samsung/dev-keypad.c + * + * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/platform_device.h> +#include <mach/irqs.h> +#include <mach/map.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/keypad.h> + +static struct resource samsung_keypad_resources[] = { + [0] = { + .start = SAMSUNG_PA_KEYPAD, + .end = SAMSUNG_PA_KEYPAD + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_KEYPAD, + .end = IRQ_KEYPAD, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device samsung_device_keypad = { + .name = "samsung-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(samsung_keypad_resources), + .resource = samsung_keypad_resources, +}; + +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd) +{ + struct samsung_keypad_platdata *npd; + + npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata), + &samsung_device_keypad); + + if (!npd->cfg_gpio) + npd->cfg_gpio = samsung_keypad_cfg_gpio; +} diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c index 5efca87cddb..019b5b8cf14 100644 --- a/arch/arm/plat-samsung/dev-wdt.c +++ b/arch/arm/plat-samsung/dev-wdt.c @@ -21,7 +21,7 @@ static struct resource s3c_wdt_resource[] = { [0] = { .start = S3C_PA_WDT, - .end = S3C_PA_WDT + SZ_1M - 1, + .end = S3C_PA_WDT + SZ_1K, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c index 8a8ba8bc1d9..c354089254f 100644 --- a/arch/arm/plat-samsung/gpiolib.c +++ b/arch/arm/plat-samsung/gpiolib.c @@ -18,7 +18,7 @@ #include <linux/kernel.h> #include <linux/irq.h> #include <linux/io.h> -#include <mach/gpio.h> +#include <linux/gpio.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/plat-samsung/include/plat/adc-core.h new file mode 100644 index 00000000000..a281568d585 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/adc-core.h @@ -0,0 +1,28 @@ +/* linux/arch/arm/plat-samsung/include/plat/adc-core.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Samsung ADC Controller core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ADC_CORE_H +#define __ASM_PLAT_ADC_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c_adc_setname(char *name) +{ +#ifdef CONFIG_SAMSUNG_DEV_ADC + s3c_device_adc.name = name; +#endif +} + +#endif /* __ASM_PLAT_ADC_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/ata-core.h b/arch/arm/plat-samsung/include/plat/ata-core.h new file mode 100644 index 00000000000..f5a4ec7141b --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/ata-core.h @@ -0,0 +1,28 @@ +/* linux/arch/arm/plat-samsung/include/plat/ata-core.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung CF-ATA Controller core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ATA_CORE_H +#define __ASM_PLAT_ATA_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code +*/ + +/* re-define device name depending on support. */ +static inline void s3c_cfcon_setname(char *name) +{ +#ifdef CONFIG_SAMSUNG_DEV_IDE + s3c_device_cfcon.name = name; +#endif +} + +#endif /* __ASM_PLAT_ATA_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/ata.h b/arch/arm/plat-samsung/include/plat/ata.h new file mode 100644 index 00000000000..2a3855a8372 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/ata.h @@ -0,0 +1,36 @@ +/* linux/arch/arm/plat-samsung/include/plat/ata.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung CF-ATA platform_device info + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ATA_H +#define __ASM_PLAT_ATA_H __FILE__ + +/** + * struct s3c_ide_platdata - S3C IDE driver platform data. + * @setup_gpio: Setup the external GPIO pins to the right state for data + * transfer in true-ide mode. + */ +struct s3c_ide_platdata { + void (*setup_gpio)(void); +}; + +/* + * s3c_ide_set_platdata() - Setup the platform specifc data for IDE driver. + * @pdata: Platform data for IDE driver. + */ +extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata); + +/* architecture-specific IDE configuration */ +extern void s3c64xx_ide_setup_gpio(void); +extern void s5pc100_ide_setup_gpio(void); +extern void s5pv210_ide_setup_gpio(void); + +#endif /*__ASM_PLAT_ATA_H */ diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index e6144e4b911..85f6f23a510 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -54,6 +54,8 @@ extern struct platform_device s3c_device_hwmon; extern struct platform_device s3c_device_hsmmc0; extern struct platform_device s3c_device_hsmmc1; extern struct platform_device s3c_device_hsmmc2; +extern struct platform_device s3c_device_hsmmc3; +extern struct platform_device s3c_device_cfcon; extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; @@ -100,6 +102,12 @@ extern struct platform_device s5pc100_device_iis0; extern struct platform_device s5pc100_device_iis1; extern struct platform_device s5pc100_device_iis2; +extern struct platform_device samsung_device_keypad; + +extern struct platform_device s5p_device_fimc0; +extern struct platform_device s5p_device_fimc1; +extern struct platform_device s5p_device_fimc2; + /* s3c2440 specific devices */ #ifdef CONFIG_CPU_S3C2440 @@ -108,3 +116,15 @@ extern struct platform_device s3c_device_camif; extern struct platform_device s3c_device_ac97; #endif + +/** + * s3c_set_platdata() - helper for setting platform data + * @pd: The default platform data for this device. + * @pdsize: The size of the platform data. + * @pdev: Pointer to the device to fill in. + * + * This helper replaces a number of calls that copy and then set the + * platform data of the device. + */ +extern void *s3c_set_platdata(void *pd, size_t pdsize, + struct platform_device *pdev); diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h new file mode 100644 index 00000000000..bca383efcf6 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/fb-core.h @@ -0,0 +1,29 @@ +/* + * arch/arm/plat-samsung/include/plat/fb-core.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * Pawel Osciak <p.osciak@samsung.com> + * + * Samsung framebuffer driver core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PLAT_FB_CORE_H +#define __ASM_PLAT_FB_CORE_H __FILE__ + +/* + * These functions are only for use with the core support code, such as + * the CPU-specific initialization code. + */ + +/* Re-define device name depending on support. */ +static inline void s3c_fb_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_FB + s3c_device_fb.name = name; +#endif +} + +#endif /* __ASM_PLAT_FB_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 27d3b497b55..cb3ca3adc68 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -42,6 +42,7 @@ struct s3c_fb_pd_win { * @setup_gpio: Setup the external GPIO pins to the right state to transfer * the data from the display system to the connected display * device. + * @default_win: default window layer number to be used for UI layer. * @vidcon0: The base vidcon0 values to control the panel data format. * @vidcon1: The base vidcon1 values to control the panel data output. * @win: The setup data for each hardware window, or NULL for unused. @@ -58,6 +59,8 @@ struct s3c_fb_platdata { struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; + u32 default_win; + u32 vidcon0; u32 vidcon1; }; diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h new file mode 100644 index 00000000000..81a3bfeecca --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/fimc-core.h @@ -0,0 +1,44 @@ +/* + * arch/arm/plat-samsung/include/plat/fimc-core.h + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * Sylwester Nawrocki <s.nawrocki@samsung.com> + * + * Samsung camera interface driver core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_PLAT_FIMC_CORE_H +#define __ASM_PLAT_FIMC_CORE_H __FILE__ + +/* + * These functions are only for use with the core support code, such as + * the CPU-specific initialization code. + */ + +/* Re-define device name to differentiate the subsystem in various SoCs. */ +static inline void s3c_fimc_setname(int id, char *name) +{ + switch (id) { +#ifdef CONFIG_S5P_DEV_FIMC0 + case 0: + s5p_device_fimc0.name = name; + break; +#endif +#ifdef CONFIG_S5P_DEV_FIMC1 + case 1: + s5p_device_fimc1.name = name; + break; +#endif +#ifdef CONFIG_S5P_DEV_FIMC2 + case 2: + s5p_device_fimc2.name = name; + break; +#endif + } +} + +#endif /* __ASM_PLAT_FIMC_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/keypad-core.h b/arch/arm/plat-samsung/include/plat/keypad-core.h new file mode 100644 index 00000000000..d513e1b3a31 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/keypad-core.h @@ -0,0 +1,31 @@ +/* + * linux/arch/arm/plat-samsung/include/plat/keypad-core.h + * + * Copyright (C) 2010 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * Samsung keypad controller core function + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __ASM_ARCH_KEYPAD_CORE_H +#define __ASM_ARCH_KEYPAD_CORE_H + +/* These function are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void samsung_keypad_setname(char *name) +{ +#ifdef CONFIG_SAMSUNG_DEV_KEYPAD + samsung_device_keypad.name = name; +#endif +} + +#endif /* __ASM_ARCH_KEYPAD_CORE_H */ diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h index 3a70c125fe5..b59a6483cd8 100644 --- a/arch/arm/plat-samsung/include/plat/keypad.h +++ b/arch/arm/plat-samsung/include/plat/keypad.h @@ -40,4 +40,17 @@ struct samsung_keypad_platdata { void (*cfg_gpio)(unsigned int rows, unsigned int cols); }; +/** + * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device. + * @pd: Platform data to register to device. + * + * Register the given platform data for use with Samsung Keypad device. + * The call will copy the platform data, so the board definitions can + * make the structure itself __initdata. + */ +extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd); + +/* defined by architecture to configure gpio. */ +extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols); + #endif /* __PLAT_SAMSUNG_KEYPAD_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-ata.h b/arch/arm/plat-samsung/include/plat/regs-ata.h new file mode 100644 index 00000000000..f5df92fdae2 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-ata.h @@ -0,0 +1,56 @@ +/* linux/arch/arm/plat-samsung/include/plat/regs-ata.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung CF-ATA register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_REGS_ATA_H +#define __ASM_PLAT_REGS_ATA_H __FILE__ + +#define S3C_CFATA_REG(x) (x) + +#define S3C_CFATA_MUX S3C_CFATA_REG(0x0) + +#define S3C_ATA_CTRL S3C_CFATA_REG(0x0) +#define S3C_ATA_STATUS S3C_CFATA_REG(0x4) +#define S3C_ATA_CMD S3C_CFATA_REG(0x8) +#define S3C_ATA_SWRST S3C_CFATA_REG(0xc) +#define S3C_ATA_IRQ S3C_CFATA_REG(0x10) +#define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14) +#define S3C_ATA_CFG S3C_CFATA_REG(0x18) + +#define S3C_ATA_MDMA_TIME S3C_CFATA_REG(0x28) +#define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c) +#define S3C_ATA_UDMA_TIME S3C_CFATA_REG(0x30) +#define S3C_ATA_XFR_NUM S3C_CFATA_REG(0x34) +#define S3C_ATA_XFR_CNT S3C_CFATA_REG(0x38) +#define S3C_ATA_TBUF_START S3C_CFATA_REG(0x3c) +#define S3C_ATA_TBUF_SIZE S3C_CFATA_REG(0x40) +#define S3C_ATA_SBUF_START S3C_CFATA_REG(0x44) +#define S3C_ATA_SBUF_SIZE S3C_CFATA_REG(0x48) +#define S3C_ATA_CADR_TBUF S3C_CFATA_REG(0x4c) +#define S3C_ATA_CADR_SBUF S3C_CFATA_REG(0x50) +#define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54) +#define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58) +#define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c) +#define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60) +#define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64) +#define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68) +#define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c) +#define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70) +#define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74) +#define S3C_ATA_PIO_READY S3C_CFATA_REG(0x78) +#define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c) + +#define S3C_CFATA_MUX_TRUEIDE 0x01 + +#define S3C_ATA_CFG_SWAP 0x40 +#define S3C_ATA_CFG_IORDYEN 0x02 + +#endif /* __ASM_PLAT_REGS_ATA_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h index 0f43599248a..4c3647f8005 100644 --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h @@ -40,16 +40,10 @@ /* OSD1 and OSD4 do not have register D */ -#define VIDOSD_A(_win) (0x40 + ((_win) * 16)) -#define VIDOSD_B(_win) (0x44 + ((_win) * 16)) -#define VIDOSD_C(_win) (0x48 + ((_win) * 16)) -#define VIDOSD_D(_win) (0x4C + ((_win) * 16)) - +#define VIDOSD_BASE (0x40) #define VIDINTCON0 (0x130) -#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) - /* WINCONx */ #define WINCONx_CSCWIDTH_MASK (0x3 << 26) @@ -143,76 +137,6 @@ #define WPALCON_W2PAL_16BPP_A555 (1 << 6) -/* system specific implementation code for palette sizes, and other - * information that changes depending on which architecture is being - * compiled. -*/ - -/* return true if window _win has OSD register D */ -#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) - -static inline unsigned int s3c_fb_win_pal_size(unsigned int win) -{ - if (win < 2) - return 256; - if (win < 4) - return 16; - if (win == 4) - return 4; - - BUG(); /* shouldn't get here */ -} - -static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) -{ - /* all windows can do 1/2 bpp */ - - if ((bpp == 25 || bpp == 19) && win == 0) - return 0; /* win 0 does not have 19 or 25bpp modes */ - - if (bpp == 4 && win == 4) - return 0; - - if (bpp == 8 && (win >= 3)) - return 0; /* win 3/4 cannot do 8bpp in any mode */ - - return 1; -} - -static inline int s3c_fb_pal_is16(unsigned int window) -{ - return window > 1; -} - -struct s3c_fb_palette { - struct fb_bitfield r; - struct fb_bitfield g; - struct fb_bitfield b; - struct fb_bitfield a; -}; - -static inline void s3c_fb_init_palette(unsigned int window, - struct s3c_fb_palette *palette) -{ - if (window < 2) { - /* Windows 0/1 are 8/8/8 or A/8/8/8 */ - palette->r.offset = 16; - palette->r.length = 8; - palette->g.offset = 8; - palette->g.length = 8; - palette->b.offset = 0; - palette->b.length = 8; - } else { - /* currently we assume RGB 5/6/5 */ - palette->r.offset = 11; - palette->r.length = 5; - palette->g.offset = 5; - palette->g.length = 6; - palette->b.offset = 0; - palette->b.length = 5; - } -} - /* Notes on per-window bpp settings * * Value Win0 Win1 Win2 Win3 Win 4 diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h index 0ef806e5034..8f39aa5b26e 100644 --- a/arch/arm/plat-samsung/include/plat/regs-fb.h +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h @@ -112,6 +112,13 @@ #define VIDCON2_ORGYCbCr (1 << 8) #define VIDCON2_YUVORDCrCb (1 << 7) +/* PRTCON (S3C6410, S5PC100) + * Might not be present in the S3C6410 documentation, + * but tests prove it's there almost for sure; shouldn't hurt in any case. + */ +#define PRTCON (0x0c) +#define PRTCON_PROTECT (1 << 11) + /* VIDTCON0 */ #define VIDTCON0_VBPDE_MASK (0xff << 24) @@ -173,6 +180,7 @@ #define WINCONx_BITSWP (1 << 18) #define WINCONx_BYTSWP (1 << 17) #define WINCONx_HAWSWP (1 << 16) +#define WINCONx_WSWP (1 << 15) #define WINCONx_BURSTLEN_MASK (0x3 << 9) #define WINCONx_BURSTLEN_SHIFT (9) #define WINCONx_BURSTLEN_16WORD (0x0 << 9) @@ -212,6 +220,13 @@ #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) +/* S5PV210 */ +#define SHADOWCON (0x34) +#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) +/* DMA channels (all windows) */ +#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win)) +/* Local input channels (windows 0-2) */ +#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) #define VIDOSDxA_TOPLEFT_X_SHIFT (11) @@ -291,11 +306,12 @@ #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) -#define VIDINTCON0_FRAMESEL1 (1 << 14) -#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14) -#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14) -#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14) -#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14) +#define VIDINTCON0_FRAMESEL1 (1 << 13) +#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13) +#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13) +#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13) +#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13) +#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13) #define VIDINTCON0_INT_FRAME (1 << 12) #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) @@ -321,6 +337,10 @@ #define VIDINTCON1_INT_FIFO (1 << 0) /* Window colour-key control registers */ +#define WKEYCON (0x140) /* 6410,V210 */ + +#define WKEYCON0 (0x00) +#define WKEYCON1 (0x04) #define WxKEYCON0_KEYBL_EN (1 << 26) #define WxKEYCON0_KEYEN_F (1 << 25) diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h index 65c190d142d..30b7cc14cef 100644 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h @@ -14,6 +14,9 @@ #define __ASM_ARCH_REGS_RTC_H __FILE__ #define S3C2410_RTCREG(x) (x) +#define S3C2410_INTP S3C2410_RTCREG(0x30) +#define S3C2410_INTP_ALM (1 << 1) +#define S3C2410_INTP_TIC (1 << 0) #define S3C2410_RTCCON S3C2410_RTCREG(0x40) #define S3C2410_RTCCON_RTCEN (1<<0) diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index a6eba8496b2..788837e99cb 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -259,6 +259,8 @@ struct s3c2410_uartcfg { unsigned short flags; upf_t uart_flags; /* default uart flags */ + unsigned int has_fracval; + unsigned long ucon; /* value of ucon for port */ unsigned long ulcon; /* value of ulcon for port */ unsigned long ufcon; /* value of ufcon for port */ diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h index 8d18d9d4d14..dc90f5ede88 100644 --- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h @@ -226,6 +226,7 @@ #define S3C_DIEPMSK S3C_HSOTG_REG(0x810) +#define S3C_DIEPMSK_TxFIFOEmpty (1 << 7) #define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) #define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) #define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) @@ -371,6 +372,7 @@ #define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) #define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) +#define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20)) #define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 016674fa20d..30844c263d0 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -20,10 +20,31 @@ struct mmc_host; struct mmc_card; struct mmc_ios; +enum cd_types { + S3C_SDHCI_CD_INTERNAL, /* use mmc internal CD line */ + S3C_SDHCI_CD_EXTERNAL, /* use external callback */ + S3C_SDHCI_CD_GPIO, /* use external gpio pin for CD line */ + S3C_SDHCI_CD_NONE, /* no CD line, use polling to detect card */ + S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */ +}; + /** * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI * @max_width: The maximum number of data bits supported. * @host_caps: Standard MMC host capabilities bit field. + * @cd_type: Type of Card Detection method (see cd_types enum above) + * @ext_cd_init: Initialize external card detect subsystem. Called on + * sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL. + * notify_func argument is a callback to the sdhci-s3c driver + * that triggers the card detection event. Callback arguments: + * dev is pointer to platform device of the host controller, + * state is new state of the card (0 - removed, 1 - inserted). + * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on + * sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL. + * notify_func argument is the same callback as for ext_cd_init. + * @ext_cd_gpio: gpio pin used for external CD line, valid only if + * cd_type == S3C_SDHCI_CD_GPIO + * @ext_cd_gpio_invert: invert values for external CD gpio line * @cfg_gpio: Configure the GPIO for a specific card bit-width * @cfg_card: Configure the interface for a specific card and speed. This * is necessary the controllers and/or GPIO blocks require the @@ -37,9 +58,17 @@ struct mmc_ios; struct s3c_sdhci_platdata { unsigned int max_width; unsigned int host_caps; + enum cd_types cd_type; char **clocks; /* set of clock sources */ + int ext_cd_gpio; + bool ext_cd_gpio_invert; + int (*ext_cd_init)(void (*notify_func)(struct platform_device *, + int state)); + int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, + int state)); + void (*cfg_gpio)(struct platform_device *dev, int width); void (*cfg_card)(struct platform_device *dev, void __iomem *regbase, @@ -58,6 +87,7 @@ struct s3c_sdhci_platdata { extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); +extern void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd); /* Default platform data, exported so that per-cpu initialisation can * set the correct one when there are more than one cpu type selected. @@ -66,6 +96,7 @@ extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; +extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; /* Helper function availablity */ @@ -78,13 +109,13 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); +extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w); -/* S3C6400 SDHCI setup */ +/* S3C64XX SDHCI setup */ #ifdef CONFIG_S3C64XX_SETUP_SDHCI extern char *s3c64xx_hsmmc_clksrcs[4]; -#ifdef CONFIG_S3C_DEV_HSMMC extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, @@ -92,76 +123,62 @@ extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, static inline void s3c6400_default_sdhci0(void) { +#ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; +#endif } -#else -static inline void s3c6400_default_sdhci0(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC */ - -#ifdef CONFIG_S3C_DEV_HSMMC1 static inline void s3c6400_default_sdhci1(void) { +#ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; +#endif } -#else -static inline void s3c6400_default_sdhci1(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ -#ifdef CONFIG_S3C_DEV_HSMMC2 static inline void s3c6400_default_sdhci2(void) { +#ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; +#endif } -#else -static inline void s3c6400_default_sdhci2(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC2 */ - -/* S3C6410 SDHCI setup */ extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, struct mmc_ios *ios, struct mmc_card *card); -#ifdef CONFIG_S3C_DEV_HSMMC static inline void s3c6410_default_sdhci0(void) { +#ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; +#endif } -#else -static inline void s3c6410_default_sdhci0(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC */ -#ifdef CONFIG_S3C_DEV_HSMMC1 static inline void s3c6410_default_sdhci1(void) { +#ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; +#endif } -#else -static inline void s3c6410_default_sdhci1(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ -#ifdef CONFIG_S3C_DEV_HSMMC2 static inline void s3c6410_default_sdhci2(void) { +#ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; +#endif } -#else -static inline void s3c6410_default_sdhci2(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC2 */ #else static inline void s3c6410_default_sdhci0(void) { } @@ -183,48 +200,42 @@ extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, struct mmc_ios *ios, struct mmc_card *card); -#ifdef CONFIG_S3C_DEV_HSMMC static inline void s5pc100_default_sdhci0(void) { +#ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; +#endif } -#else -static inline void s5pc100_default_sdhci0(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC */ -#ifdef CONFIG_S3C_DEV_HSMMC1 static inline void s5pc100_default_sdhci1(void) { +#ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; +#endif } -#else -static inline void s5pc100_default_sdhci1(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ -#ifdef CONFIG_S3C_DEV_HSMMC2 static inline void s5pc100_default_sdhci2(void) { +#ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; +#endif } -#else -static inline void s5pc100_default_sdhci2(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ - #else static inline void s5pc100_default_sdhci0(void) { } static inline void s5pc100_default_sdhci1(void) { } static inline void s5pc100_default_sdhci2(void) { } + #endif /* CONFIG_S5PC100_SETUP_SDHCI */ +/* S5PV210 SDHCI setup */ -/* S5PC110 SDHCI setup */ #ifdef CONFIG_S5PV210_SETUP_SDHCI extern char *s5pv210_hsmmc_clksrcs[4]; @@ -233,46 +244,48 @@ extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, struct mmc_ios *ios, struct mmc_card *card); -#ifdef CONFIG_S3C_DEV_HSMMC static inline void s5pv210_default_sdhci0(void) { +#ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +#endif } -#else -static inline void s5pv210_default_sdhci0(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC */ -#ifdef CONFIG_S3C_DEV_HSMMC1 static inline void s5pv210_default_sdhci1(void) { +#ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +#endif } -#else -static inline void s5pv210_default_sdhci1(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC1 */ -#ifdef CONFIG_S3C_DEV_HSMMC2 static inline void s5pv210_default_sdhci2(void) { +#ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +#endif +} + +static inline void s5pv210_default_sdhci3(void) +{ +#ifdef CONFIG_S3C_DEV_HSMMC3 + s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; + s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; + s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; +#endif } -#else -static inline void s5pv210_default_sdhci2(void) { } -#endif /* CONFIG_S3C_DEV_HSMMC2 */ #else static inline void s5pv210_default_sdhci0(void) { } static inline void s5pv210_default_sdhci1(void) { } static inline void s5pv210_default_sdhci2(void) { } -#endif /* CONFIG_S5PC100_SETUP_SDHCI */ - - +static inline void s5pv210_default_sdhci3(void) { } +#endif /* CONFIG_S5PV210_SETUP_SDHCI */ #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c new file mode 100644 index 00000000000..7cf2e1e3b20 --- /dev/null +++ b/arch/arm/plat-samsung/platformdata.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-samsung/platformdata.c + * + * Copyright 2010 Ben Dooks <ben-linux <at> fluff.org> + * + * Helper for platform data setting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <plat/devs.h> + +void __init *s3c_set_platdata(void *pd, size_t pdsize, + struct platform_device *pdev) +{ + void *npd; + + if (!pd) { + /* too early to use dev_name(), may not be registered */ + printk(KERN_ERR "%s: no platform data supplied\n", pdev->name); + return NULL; + } + + npd = kmemdup(pd, pdsize, GFP_KERNEL); + if (!npd) { + printk(KERN_ERR "%s: cannot clone platform data\n", pdev->name); + return NULL; + } + + pdev->dev.platform_data = npd; + return npd; +} |