diff options
Diffstat (limited to 'arch/arm')
900 files changed, 9702 insertions, 25013 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 93d595a7477..7275009686e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HAVE_C_RECORDMCOUNT select HAVE_GENERIC_HARDIRQS select HAVE_SPARSE_IRQ + select GENERIC_IRQ_SHOW help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and @@ -196,15 +197,21 @@ config ARM_PATCH_PHYS_VIRT depends on !XIP_KERNEL && MMU depends on !ARCH_REALVIEW || !SPARSEMEM help - Patch phys-to-virt translation functions at runtime according to - the position of the kernel in system memory. + Patch phys-to-virt and virt-to-phys translation functions at + boot and module load time according to the position of the + kernel in system memory. - This can only be used with non-XIP with MMU kernels where - the base of physical memory is at a 16MB boundary. + This can only be used with non-XIP MMU kernels where the base + of physical memory is at a 16MB boundary, or theoretically 64K + for the MSM machine class. config ARM_PATCH_PHYS_VIRT_16BIT def_bool y depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM + help + This option extends the physical to virtual translation patching + to allow physical memory down to a theoretical minimum of 64K + boundaries. source "init/Kconfig" @@ -296,6 +303,7 @@ config ARCH_BCMRING depends on MMU select CPU_V6 select ARM_AMBA + select ARM_TIMER_SP804 select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB @@ -365,6 +373,8 @@ config ARCH_MXC select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO + select HAVE_SCHED_CLOCK help Support for Freescale MXC/iMX-based family of processors @@ -373,21 +383,13 @@ config ARCH_MXS select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO help Support for Freescale MXS-based family of processors -config ARCH_STMP3XXX - bool "Freescale STMP3xxx" - select CPU_ARM926T - select CLKDEV_LOOKUP - select ARCH_REQUIRE_GPIOLIB - select GENERIC_CLOCKEVENTS - select USB_ARCH_HAS_EHCI - help - Support for systems based on the Freescale 3xxx CPUs. - config ARCH_NETX bool "Hilscher NetX based" + select CLKSRC_MMIO select CPU_ARM926T select ARM_VIC select GENERIC_CLOCKEVENTS @@ -455,6 +457,7 @@ config ARCH_IXP2000 config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select CLKSRC_MMIO select CPU_XSCALE select GENERIC_GPIO select GENERIC_CLOCKEVENTS @@ -466,7 +469,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" - select CPU_V6K + select CPU_V7 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS @@ -495,6 +498,7 @@ config ARCH_LOKI config ARCH_LPC32XX bool "NXP LPC32XX" + select CLKSRC_MMIO select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB select HAVE_IDE @@ -552,23 +556,12 @@ config ARCH_KS8695 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. -config ARCH_NS9XXX - bool "NetSilicon NS9xxx" - select CPU_ARM926T - select GENERIC_GPIO - select GENERIC_CLOCKEVENTS - select HAVE_CLK - help - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx - System. - - <http://www.digi.com/products/microprocessors/index.jsp> - config ARCH_W90X900 bool "Nuvoton W90X900 CPU" select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO select GENERIC_CLOCKEVENTS help Support for Nuvoton (Winbond logic dept.) ARM9 processor, @@ -590,6 +583,7 @@ config ARCH_NUC93X config ARCH_TEGRA bool "NVIDIA Tegra" select CLKDEV_LOOKUP + select CLKSRC_MMIO select GENERIC_TIME select GENERIC_CLOCKEVENTS select GENERIC_GPIO @@ -615,6 +609,7 @@ config ARCH_PXA select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ select CLKDEV_LOOKUP + select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select HAVE_SCHED_CLOCK @@ -665,6 +660,7 @@ config ARCH_RPC config ARCH_SA1100 bool "SA1100-based" + select CLKSRC_MMIO select CPU_SA1100 select ISA select ARCH_SPARSEMEM_ENABLE @@ -692,7 +688,7 @@ config ARCH_S3C2410 the Samsung SMDK2410 development board (and derivatives). Note, the S3C2416 and the S3C2450 are so close that they even share - the same SoC ID code. This means that there is no seperate machine + the same SoC ID code. This means that there is no separate machine directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. config ARCH_S3C64XX @@ -801,6 +797,7 @@ config ARCH_SHARK config ARCH_TCC_926 bool "Telechips TCC ARM926-based systems" + select CLKSRC_MMIO select CPU_ARM926T select HAVE_CLK select CLKDEV_LOOKUP @@ -811,6 +808,7 @@ config ARCH_TCC_926 config ARCH_U300 bool "ST-Ericsson U300 Series" depends on MMU + select CLKSRC_MMIO select CPU_ARM926T select HAVE_SCHED_CLOCK select HAVE_TCM @@ -852,6 +850,7 @@ config ARCH_DAVINCI select HAVE_IDE select CLKDEV_LOOKUP select GENERIC_ALLOCATOR + select GENERIC_IRQ_CHIP select ARCH_HAS_HOLES_MEMORYMODEL help Support for TI's DaVinci platform. @@ -872,6 +871,7 @@ config PLAT_SPEAR select ARM_AMBA select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select HAVE_CLK help @@ -949,8 +949,6 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/plat-nomadik/Kconfig" -source "arch/arm/mach-ns9xxx/Kconfig" - source "arch/arm/mach-nuc93x/Kconfig" source "arch/arm/plat-omap/Kconfig" @@ -1003,8 +1001,6 @@ source "arch/arm/mach-exynos4/Kconfig" source "arch/arm/mach-shmobile/Kconfig" -source "arch/arm/plat-stmp3xxx/Kconfig" - source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" @@ -1031,6 +1027,8 @@ config PLAT_IOP config PLAT_ORION bool + select CLKSRC_MMIO + select GENERIC_IRQ_CHIP select HAVE_SCHED_CLOCK config PLAT_PXA @@ -1041,6 +1039,7 @@ config PLAT_VERSATILE config ARM_TIMER_SP804 bool + select CLKSRC_MMIO source arch/arm/mm/Kconfig @@ -1316,8 +1315,7 @@ menu "Kernel Features" source "kernel/time/Kconfig" config SMP - bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL + bool "Symmetric Multi-Processing" depends on CPU_V6K || CPU_V7 depends on GENERIC_CLOCKEVENTS depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ @@ -1519,8 +1517,8 @@ config ARCH_SELECT_MEMORY_MODEL def_bool ARCH_SPARSEMEM_ENABLE config HIGHMEM - bool "High Memory Support (EXPERIMENTAL)" - depends on MMU && EXPERIMENTAL + bool "High Memory Support" + depends on MMU help The address space of ARM processors is only 4 Gigabytes large and it has to accommodate user address space, kernel address @@ -1538,7 +1536,6 @@ config HIGHMEM config HIGHPTE bool "Allocate 2nd-level pagetables from highmem" depends on HIGHMEM - depends on !OUTER_CACHE config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" @@ -1741,16 +1738,31 @@ config CMDLINE time by entering them here. As a minimum, you should specify the memory size and the root device (e.g., mem=64M root=/dev/nfs). +choice + prompt "Kernel command line type" if CMDLINE != "" + default CMDLINE_FROM_BOOTLOADER + +config CMDLINE_FROM_BOOTLOADER + bool "Use bootloader kernel arguments if available" + help + Uses the command-line options passed by the boot loader. If + the boot loader doesn't provide any, the default kernel command + string provided in CMDLINE will be used. + +config CMDLINE_EXTEND + bool "Extend bootloader kernel arguments" + help + The command-line arguments provided by the boot loader will be + appended to the default kernel command string. + config CMDLINE_FORCE bool "Always use the default kernel command string" - depends on CMDLINE != "" help Always use the default kernel command string, even if the boot loader passes other arguments to the kernel. This is useful if you cannot or don't want to change the command-line options your boot loader passes to the kernel. - - If unsure, say N. +endchoice config XIP_KERNEL bool "Kernel Execute-In-Place from ROM" @@ -2009,6 +2021,9 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE + depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100 + depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ + CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y endmenu diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index 901e6dff843..2cef8e13f9f 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -34,7 +34,7 @@ config PROCESSOR_ID used instead of the auto-probing which utilizes the register. config REMAP_VECTORS_TO_RAM - bool 'Install vectors to the begining of RAM' if DRAM_BASE + bool 'Install vectors to the beginning of RAM' if DRAM_BASE depends on DRAM_BASE help The kernel needs to change the hardware exception vectors. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 494224a9b45..03d01d783e3 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -63,17 +63,6 @@ config DEBUG_USER 8 - SIGSEGV faults 16 - SIGBUS faults -config DEBUG_ERRORS - bool "Verbose kernel error messages" - depends on DEBUG_KERNEL - help - This option controls verbose debugging information which can be - printed when the kernel detects an internal error. This debugging - information is useful to kernel hackers when tracking down problems, - but mostly meaningless to other people. It's safe to say Y unless - you are concerned with the code size or don't want to see these - messages. - config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" depends on DEBUG_KERNEL diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c7d321a3d95..25750bcb339 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -158,13 +158,11 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MX1) := imx machine-$(CONFIG_ARCH_MX2) := imx machine-$(CONFIG_ARCH_MX25) := imx -machine-$(CONFIG_ARCH_MX3) := mx3 +machine-$(CONFIG_ARCH_MX3) := imx machine-$(CONFIG_ARCH_MX5) := mx5 -machine-$(CONFIG_ARCH_MXC91231) := mxc91231 machine-$(CONFIG_ARCH_MXS) := mxs machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik -machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP2) := omap2 machine-$(CONFIG_ARCH_OMAP3) := omap2 @@ -185,8 +183,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile -machine-$(CONFIG_ARCH_STMP378X) := stmp378x -machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 @@ -207,7 +203,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung -plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx plat-$(CONFIG_ARCH_TCC_926) := tcc plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 8ebbb511c78..23aad072230 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -74,7 +74,7 @@ ZTEXTADDR := $(CONFIG_ZBOOT_ROM_TEXT) ZBSSADDR := $(CONFIG_ZBOOT_ROM_BSS) else ZTEXTADDR := 0 -ZBSSADDR := ALIGN(4) +ZBSSADDR := ALIGN(8) endif SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ @@ -98,8 +98,6 @@ endif ccflags-y := -fpic -fno-builtin asflags-y := -Wa,-march=all -# Provide size of uncompressed kernel to the decompressor via a linker symbol. -LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) @@ -122,10 +120,23 @@ lib1funcs = $(obj)/lib1funcs.o $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE $(call cmd,shipped) +# We need to prevent any GOTOFF relocs being used with references +# to symbols in the .bss section since we cannot relocate them +# independently from the rest at run time. This can be achieved by +# ensuring that no private .bss symbols exist, as global symbols +# always have a GOT entry which is what we need. +# The .data section is already discarded by the linker script so no need +# to bother about it here. +check_for_bad_syms = \ +bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \ +[ -z "$$bad_syms" ] || \ + ( echo "following symbols must have non local/private scope:" >&2; \ + echo "$$bad_syms" >&2; rm -f $@; false ) + $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \ $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE $(call if_changed,ld) - @: + @$(check_for_bad_syms) $(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE $(call if_changed,$(suffix_y)) diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index 4c72a97bc3e..07be5a2f830 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -44,7 +44,7 @@ extern void error(char *); #include "../../../../lib/decompress_unlzma.c" #endif -void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) +int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)) { - decompress(input, len, NULL, NULL, output, NULL, error); + return decompress(input, len, NULL, NULL, output, NULL, error); } diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 84ac4d65631..f9da41921c5 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -21,20 +21,12 @@ #if defined(CONFIG_DEBUG_ICEDCC) -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) .macro loadsp, rb, tmp .endm .macro writeb, ch, rb mcr p14, 0, \ch, c0, c5, 0 .endm -#elif defined(CONFIG_CPU_V7) - .macro loadsp, rb, tmp - .endm - .macro writeb, ch, rb -wait: mrc p14, 0, pc, c0, c1, 0 - bcs wait - mcr p14, 0, \ch, c0, c5, 0 - .endm #elif defined(CONFIG_CPU_XSCALE) .macro loadsp, rb, tmp .endm @@ -187,16 +179,29 @@ not_angel: bl cache_on restart: adr r0, LC0 - ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12} - ldr sp, [r0, #32] + ldmia r0, {r1, r2, r3, r6, r10, r11, r12} + ldr sp, [r0, #28] /* * We might be running at a different address. We need * to fix up various pointers. */ sub r0, r0, r1 @ calculate the delta offset - add r5, r5, r0 @ _start add r6, r6, r0 @ _edata + add r10, r10, r0 @ inflated kernel size location + + /* + * The kernel build system appends the size of the + * decompressed kernel at the end of the compressed data + * in little-endian form. + */ + ldrb r9, [r10, #0] + ldrb lr, [r10, #1] + orr r9, r9, lr, lsl #8 + ldrb lr, [r10, #2] + ldrb r10, [r10, #3] + orr r9, r9, lr, lsl #16 + orr r9, r9, r10, lsl #24 #ifndef CONFIG_ZBOOT_ROM /* malloc space is above the relocated stack (64k max) */ @@ -214,31 +219,40 @@ restart: adr r0, LC0 /* * Check to see if we will overwrite ourselves. * r4 = final kernel address - * r5 = start of this image * r9 = size of decompressed image * r10 = end of this image, including bss/stack/malloc space if non XIP * We basically want: - * r4 >= r10 -> OK - * r4 + image length <= r5 -> OK + * r4 - 16k page directory >= r10 -> OK + * r4 + image length <= current position (pc) -> OK */ + add r10, r10, #16384 cmp r4, r10 bhs wont_overwrite add r10, r4, r9 - cmp r10, r5 + ARM( cmp r10, pc ) + THUMB( mov lr, pc ) + THUMB( cmp r10, lr ) bls wont_overwrite /* * Relocate ourselves past the end of the decompressed kernel. - * r5 = start of this image * r6 = _edata * r10 = end of the decompressed kernel * Because we always copy ahead, we need to do it from the end and go * backward in case the source and destination overlap. */ - /* Round up to next 256-byte boundary. */ - add r10, r10, #256 + /* + * Bump to the next 256-byte boundary with the size of + * the relocation code added. This avoids overwriting + * ourself when the offset is small. + */ + add r10, r10, #((reloc_code_end - restart + 256) & ~255) bic r10, r10, #255 + /* Get start of code we want to copy and align it down. */ + adr r5, restart + bic r5, r5, #31 + sub r9, r6, r5 @ size to copy add r9, r9, #31 @ rounded up to a multiple bic r9, r9, #31 @ ... of 32 bytes @@ -253,6 +267,11 @@ restart: adr r0, LC0 /* Preserve offset to relocated code. */ sub r6, r9, r6 +#ifndef CONFIG_ZBOOT_ROM + /* cache_clean_flush may use the stack, so relocate it */ + add sp, sp, r6 +#endif + bl cache_clean_flush adr r0, BSYM(restart) @@ -341,12 +360,11 @@ not_relocated: mov r0, #0 LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 - .word _start @ r5 .word _edata @ r6 - .word _image_size @ r9 + .word input_data_end - 4 @ r10 (inflated size location) .word _got_start @ r11 .word _got_end @ ip - .word user_stack_end @ sp + .word .L_user_stack_end @ sp .size LC0, . - LC0 #ifdef CONFIG_ARCH_RPC @@ -455,7 +473,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size orr r1, r1, #3 << 10 add r2, r3, #16384 1: cmp r1, r9 @ if virt > start of RAM +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + orrhs r1, r1, #0x08 @ set cacheable +#else orrhs r1, r1, #0x0c @ set cacheable, bufferable +#endif cmp r1, r10 @ if virt > end of RAM bichs r1, r1, #0x0c @ clear cacheable, bufferable str r1, [r0], #4 @ 1:1 mapping @@ -480,6 +502,12 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov pc, lr ENDPROC(__setup_mmu) +__arm926ejs_mmu_cache_on: +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mov r0, #4 @ put dcache in WT mode + mcr p15, 7, r0, c15, c0, 0 +#endif + __armv4_mmu_cache_on: mov r12, lr #ifdef CONFIG_MMU @@ -661,6 +689,12 @@ proc_types: W(b) __armv4_mpu_cache_off W(b) __armv4_mpu_cache_flush + .word 0x41069260 @ ARM926EJ-S (v5TEJ) + .word 0xff0ffff0 + b __arm926ejs_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush + .word 0x00007000 @ ARM7 IDs .word 0x0000f000 mov pc, lr @@ -743,12 +777,6 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush - .word 0x560f5810 @ Marvell PJ4 ARMv6 - .word 0xff0ffff0 - W(b) __armv4_mmu_cache_on - W(b) __armv4_mmu_cache_off - W(b) __armv6_mmu_cache_flush - .word 0x000f0000 @ new CPU Id .word 0x000f0000 W(b) __armv7_mmu_cache_on @@ -1070,8 +1098,9 @@ memdump: mov r12, r0 #endif .ltorg +reloc_code_end: .align .section ".stack", "aw", %nobits -user_stack: .space 4096 -user_stack_end: +.L_user_stack: .space 4096 +.L_user_stack_end: diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 4657e877bf8..832d37236c5 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -26,8 +26,6 @@ unsigned int __machine_arch_type; #include <linux/linkage.h> #include <asm/string.h> -#include <asm/unaligned.h> - static void putstr(const char *ptr); extern void error(char *x); @@ -36,7 +34,7 @@ extern void error(char *x); #ifdef CONFIG_DEBUG_ICEDCC -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) static void icedcc_putc(int ch) { @@ -52,16 +50,6 @@ static void icedcc_putc(int ch) asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); } -#elif defined(CONFIG_CPU_V7) - -static void icedcc_putc(int ch) -{ - asm( - "wait: mrc p14, 0, pc, c0, c1, 0 \n\ - bcs wait \n\ - mcr p14, 0, %0, c0, c5, 0 " - : : "r" (ch)); -} #elif defined(CONFIG_CPU_XSCALE) @@ -149,13 +137,12 @@ void *memcpy(void *__dest, __const void *__src, size_t __n) } /* - * gzip delarations + * gzip declarations */ extern char input_data[]; extern char input_data_end[]; unsigned char *output_data; -unsigned long output_ptr; unsigned long free_mem_ptr; unsigned long free_mem_end_ptr; @@ -180,15 +167,15 @@ asmlinkage void __div0(void) error("Attempting division by 0!"); } -extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); +extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); -unsigned long +void decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, unsigned long free_mem_ptr_end_p, int arch_id) { - unsigned char *tmp; + int ret; output_data = (unsigned char *)output_start; free_mem_ptr = free_mem_ptr_p; @@ -197,12 +184,11 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, arch_decomp_setup(); - tmp = (unsigned char *) (((unsigned long)input_data_end) - 4); - output_ptr = get_unaligned_le32(tmp); - putstr("Uncompressing Linux..."); - do_decompress(input_data, input_data_end - input_data, - output_data, error); - putstr(" done, booting the kernel.\n"); - return output_ptr; + ret = do_decompress(input_data, input_data_end - input_data, + output_data, error); + if (ret) + error("decompressor returned an error"); + else + putstr(" done, booting the kernel.\n"); } diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 5309909d728..ea80abe7884 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in @@ -54,6 +54,7 @@ SECTIONS .bss : { *(.bss) } _end = .; + . = ALIGN(8); /* the stack must be 64-bit aligned */ .stack : { *(.stack) } .stab 0 : { *(.stab) } diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e7521bca2c3..6ea9b6f3607 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -16,5 +16,4 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o obj-$(CONFIG_ARCH_IXP2000) += uengine.o obj-$(CONFIG_ARCH_IXP23XX) += uengine.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o -obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index cb6b041c39d..4ddd0a6ac7f 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -49,7 +49,7 @@ struct gic_chip_data { * Default make them NULL. */ struct irq_chip gic_arch_extn = { - .irq_ack = NULL, + .irq_eoi = NULL, .irq_mask = NULL, .irq_unmask = NULL, .irq_retrigger = NULL, @@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d) /* * Routines to acknowledge, disable and enable interrupts */ -static void gic_ack_irq(struct irq_data *d) -{ - spin_lock(&irq_controller_lock); - if (gic_arch_extn.irq_ack) - gic_arch_extn.irq_ack(d); - writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); - spin_unlock(&irq_controller_lock); -} - static void gic_mask_irq(struct irq_data *d) { u32 mask = 1 << (d->irq % 32); spin_lock(&irq_controller_lock); - writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); + writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); if (gic_arch_extn.irq_mask) gic_arch_extn.irq_mask(d); spin_unlock(&irq_controller_lock); @@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d) spin_lock(&irq_controller_lock); if (gic_arch_extn.irq_unmask) gic_arch_extn.irq_unmask(d); - writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); + writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); spin_unlock(&irq_controller_lock); } +static void gic_eoi_irq(struct irq_data *d) +{ + if (gic_arch_extn.irq_eoi) { + spin_lock(&irq_controller_lock); + gic_arch_extn.irq_eoi(d); + spin_unlock(&irq_controller_lock); + } + + writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); +} + static int gic_set_type(struct irq_data *d, unsigned int type) { void __iomem *base = gic_dist_base(d); @@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) if (gic_arch_extn.irq_set_type) gic_arch_extn.irq_set_type(d, type); - val = readl(base + GIC_DIST_CONFIG + confoff); + val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); if (type == IRQ_TYPE_LEVEL_HIGH) val &= ~confmask; else if (type == IRQ_TYPE_EDGE_RISING) @@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type) * As recommended by the spec, disable the interrupt before changing * the configuration */ - if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { - writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); + if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { + writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); enabled = true; } - writel(val, base + GIC_DIST_CONFIG + confoff); + writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); if (enabled) - writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); + writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); spin_unlock(&irq_controller_lock); @@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, spin_lock(&irq_controller_lock); d->node = cpu; - val = readl(reg) & ~mask; - writel(val | bit, reg); + val = readl_relaxed(reg) & ~mask; + writel_relaxed(val | bit, reg); spin_unlock(&irq_controller_lock); return 0; @@ -213,16 +215,15 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { - struct gic_chip_data *chip_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + struct gic_chip_data *chip_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); unsigned int cascade_irq, gic_irq; unsigned long status; - /* primary controller ack'ing */ - chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); - status = readl(chip_data->cpu_base + GIC_CPU_INTACK); + status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); gic_irq = (status & 0x3ff); @@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) generic_handle_irq(cascade_irq); out: - /* primary controller unmasking */ - chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } static struct irq_chip gic_chip = { .name = "GIC", - .irq_ack = gic_ack_irq, .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, + .irq_eoi = gic_eoi_irq, .irq_set_type = gic_set_type, .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP @@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) { if (gic_nr >= MAX_GIC_NR) BUG(); - if (set_irq_data(irq, &gic_data[gic_nr]) != 0) + if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) BUG(); - set_irq_chained_handler(irq, gic_handle_cascade_irq); + irq_set_chained_handler(irq, gic_handle_cascade_irq); } static void __init gic_dist_init(struct gic_chip_data *gic, @@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic, cpumask |= cpumask << 8; cpumask |= cpumask << 16; - writel(0, base + GIC_DIST_CTRL); + writel_relaxed(0, base + GIC_DIST_CTRL); /* * Find out how many interrupts are supported. * The GIC only supports up to 1020 interrupt sources. */ - gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f; + gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f; gic_irqs = (gic_irqs + 1) * 32; if (gic_irqs > 1020) gic_irqs = 1020; @@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic, * Set all global interrupts to be level triggered, active low. */ for (i = 32; i < gic_irqs; i += 16) - writel(0, base + GIC_DIST_CONFIG + i * 4 / 16); + writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); /* * Set all global interrupts to this CPU only. */ for (i = 32; i < gic_irqs; i += 4) - writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); + writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); /* * Set priority on all global interrupts. */ for (i = 32; i < gic_irqs; i += 4) - writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); + writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); /* * Disable all interrupts. Leave the PPI and SGIs alone * as these enables are banked registers. */ for (i = 32; i < gic_irqs; i += 32) - writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); + writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); /* * Limit number of interrupts registered to the platform maximum @@ -319,13 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic, * Setup the Linux IRQ subsystem. */ for (i = irq_start; i < irq_limit; i++) { - set_irq_chip(i, &gic_chip); - set_irq_chip_data(i, gic); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); + irq_set_chip_data(i, gic); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } - writel(1, base + GIC_DIST_CTRL); + writel_relaxed(1, base + GIC_DIST_CTRL); } static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) @@ -338,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) * Deal with the banked PPI and SGI interrupts - disable all * PPI interrupts, ensure all SGI interrupts are enabled. */ - writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); - writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); + writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); + writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); /* * Set priority on PPI and SGI interrupts */ for (i = 0; i < 32; i += 4) - writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); + writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); - writel(0xf0, base + GIC_CPU_PRIMASK); - writel(1, base + GIC_CPU_CTRL); + writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); + writel_relaxed(1, base + GIC_CPU_CTRL); } void __init gic_init(unsigned int gic_nr, unsigned int irq_start, @@ -382,7 +381,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq) unsigned long flags; local_irq_save(flags); - irq_to_desc(irq)->status |= IRQ_NOPROBE; + irq_set_status_flags(irq, IRQ_NOPROBE); gic_unmask_irq(irq_get_irq_data(irq)); local_irq_restore(flags); } @@ -392,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { unsigned long map = *cpus_addr(*mask); + /* + * Ensure that stores to Normal memory are visible to the + * other CPUs before issuing the IPI. + */ + dsb(); + /* this always happens on GIC0 */ - writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); + writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); } #endif diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index fcddd48fe9d..7a21927c52e 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -88,8 +88,8 @@ void it8152_init_irq(void) __raw_writel((0), IT8152_INTC_LDCNIRR); for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { - set_irq_chip(irq, &it8152_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &it8152_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index a026a6bf489..b55c3625d7e 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = { static void locomo_handler(unsigned int irq, struct irq_desc *desc) { - struct locomo *lchip = get_irq_chip_data(irq); + struct locomo *lchip = irq_get_chip_data(irq); int req, i; /* Acknowledge the parent IRQ */ @@ -197,15 +197,14 @@ static void locomo_setup_irq(struct locomo *lchip) /* * Install handler for IRQ_LOCOMO_HW. */ - set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); - set_irq_chip_data(lchip->irq, lchip); - set_irq_chained_handler(lchip->irq, locomo_handler); + irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); + irq_set_chip_data(lchip->irq, lchip); + irq_set_chained_handler(lchip->irq, locomo_handler); /* Install handlers for IRQ_LOCOMO_* */ for ( ; irq <= lchip->irq_base + 3; irq++) { - set_irq_chip(irq, &locomo_chip); - set_irq_chip_data(irq, lchip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq); + irq_set_chip_data(irq, lchip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } @@ -476,8 +475,8 @@ static void __locomo_remove(struct locomo *lchip) device_for_each_child(lchip->dev, NULL, locomo_remove_child); if (lchip->irq != NO_IRQ) { - set_irq_chained_handler(lchip->irq, NULL); - set_irq_data(lchip->irq, NULL); + irq_set_chained_handler(lchip->irq, NULL); + irq_set_handler_data(lchip->irq, NULL); } iounmap(lchip->base); diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c index 8f0f86db360..97912fa4878 100644 --- a/arch/arm/common/pl330.c +++ b/arch/arm/common/pl330.c @@ -1045,7 +1045,7 @@ static inline int _loop(unsigned dry_run, u8 buf[], unsigned lcnt0, lcnt1, ljmp0, ljmp1; struct _arg_LPEND lpend; - /* Max iterations possibile in DMALP is 256 */ + /* Max iterations possible in DMALP is 256 */ if (*bursts >= 256*256) { lcnt1 = 256; lcnt0 = 256; @@ -1446,7 +1446,7 @@ int pl330_update(const struct pl330_info *pi) } for (ev = 0; ev < pi->pcfg.num_events; ev++) { - if (val & (1 << ev)) { /* Event occured */ + if (val & (1 << ev)) { /* Event occurred */ struct pl330_thread *thrd; u32 inten = readl(regs + INTEN); int active; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index eb9796b0dab..9c49a46a2b7 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = { }, }; -void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes) -{ - unsigned int sz = SZ_1M >> PAGE_SHIFT; - - size[1] = size[0] - sz; - size[0] = sz; -} - /* * SA1111 interrupt support. Since clearing an IRQ while there are * active IRQs causes the interrupt output to pulse, the upper levels @@ -202,7 +194,7 @@ static void sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int stat0, stat1, i; - struct sa1111 *sachip = get_irq_data(irq); + struct sa1111 *sachip = irq_get_handler_data(irq); void __iomem *mapbase = sachip->base + SA1111_INTC; stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); @@ -472,25 +464,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip) sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { - set_irq_chip(irq, &sa1111_low_chip); - set_irq_chip_data(irq, sachip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1111_low_chip, + handle_edge_irq); + irq_set_chip_data(irq, sachip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { - set_irq_chip(irq, &sa1111_high_chip); - set_irq_chip_data(irq, sachip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1111_high_chip, + handle_edge_irq); + irq_set_chip_data(irq, sachip); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Register SA1111 interrupt */ - set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); - set_irq_data(sachip->irq, sachip); - set_irq_chained_handler(sachip->irq, sa1111_irq_handler); + irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); + irq_set_handler_data(sachip->irq, sachip); + irq_set_chained_handler(sachip->irq, sa1111_irq_handler); } /* @@ -815,8 +807,8 @@ static void __sa1111_remove(struct sa1111 *sachip) clk_disable(sachip->clk); if (sachip->irq != NO_IRQ) { - set_irq_chained_handler(sachip->irq, NULL); - set_irq_data(sachip->irq, NULL); + irq_set_chained_handler(sachip->irq, NULL); + irq_set_handler_data(sachip->irq, NULL); release_mem_region(sachip->phys + SA1111_INTC, 512); } diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index 6ef3342153b..41df4787512 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c @@ -18,53 +18,67 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <linux/clk.h> #include <linux/clocksource.h> #include <linux/clockchips.h> +#include <linux/err.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> #include <asm/hardware/arm_timer.h> -/* - * These timers are currently always setup to be clocked at 1MHz. - */ -#define TIMER_FREQ_KHZ (1000) -#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) +static long __init sp804_get_clock_rate(const char *name) +{ + struct clk *clk; + long rate; + int err; + + clk = clk_get_sys("sp804", name); + if (IS_ERR(clk)) { + pr_err("sp804: %s clock not found: %d\n", name, + (int)PTR_ERR(clk)); + return PTR_ERR(clk); + } -static void __iomem *clksrc_base; + err = clk_enable(clk); + if (err) { + pr_err("sp804: %s clock failed to enable: %d\n", name, err); + clk_put(clk); + return err; + } -static cycle_t sp804_read(struct clocksource *cs) -{ - return ~readl(clksrc_base + TIMER_VALUE); -} + rate = clk_get_rate(clk); + if (rate < 0) { + pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); + clk_disable(clk); + clk_put(clk); + } -static struct clocksource clocksource_sp804 = { - .name = "timer3", - .rating = 200, - .read = sp804_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; + return rate; +} -void __init sp804_clocksource_init(void __iomem *base) +void __init sp804_clocksource_init(void __iomem *base, const char *name) { - struct clocksource *cs = &clocksource_sp804; + long rate = sp804_get_clock_rate(name); - clksrc_base = base; + if (rate < 0) + return; /* setup timer 0 as free-running clocksource */ - writel(0, clksrc_base + TIMER_CTRL); - writel(0xffffffff, clksrc_base + TIMER_LOAD); - writel(0xffffffff, clksrc_base + TIMER_VALUE); + writel(0, base + TIMER_CTRL); + writel(0xffffffff, base + TIMER_LOAD); + writel(0xffffffff, base + TIMER_VALUE); writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - clksrc_base + TIMER_CTRL); + base + TIMER_CTRL); - clocksource_register_khz(cs, TIMER_FREQ_KHZ); + clocksource_mmio_init(base + TIMER_VALUE, name, + rate, 200, 32, clocksource_mmio_readl_down); } static void __iomem *clkevt_base; +static unsigned long clkevt_reload; /* * IRQ handler for the timer @@ -90,7 +104,7 @@ static void sp804_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); + writel(clkevt_reload, clkevt_base + TIMER_LOAD); ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; break; @@ -120,7 +134,6 @@ static int sp804_set_next_event(unsigned long next, } static struct clock_event_device sp804_clockevent = { - .name = "timer0", .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = sp804_set_mode, @@ -136,17 +149,24 @@ static struct irqaction sp804_timer_irq = { .dev_id = &sp804_clockevent, }; -void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) +void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, + const char *name) { struct clock_event_device *evt = &sp804_clockevent; + long rate = sp804_get_clock_rate(name); + + if (rate < 0) + return; clkevt_base = base; + clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); - evt->irq = timer_irq; - evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); + evt->name = name; + evt->irq = irq; + evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift); evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); evt->min_delta_ns = clockevent_delta2ns(0xf, evt); - setup_irq(timer_irq, &sp804_timer_irq); + setup_irq(irq, &sp804_timer_irq); clockevents_register_device(evt); } diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index ae5fe7292e0..7aa4262ada7 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -22,17 +22,16 @@ #include <linux/init.h> #include <linux/list.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/device.h> #include <linux/amba/bus.h> #include <asm/mach/irq.h> #include <asm/hardware/vic.h> -#if defined(CONFIG_PM) +#ifdef CONFIG_PM /** * struct vic_device - VIC PM device - * @sysdev: The system device which is registered. * @irq: The IRQ number for the base of the VIC. * @base: The register base for the VIC. * @resume_sources: A bitmask of interrupts for resume. @@ -43,8 +42,6 @@ * @protect: Save for VIC_PROTECT. */ struct vic_device { - struct sys_device sysdev; - void __iomem *base; int irq; u32 resume_sources; @@ -59,11 +56,6 @@ struct vic_device { static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; static int vic_id; - -static inline struct vic_device *to_vic(struct sys_device *sys) -{ - return container_of(sys, struct vic_device, sysdev); -} #endif /* CONFIG_PM */ /** @@ -85,10 +77,9 @@ static void vic_init2(void __iomem *base) writel(32, base + VIC_PL190_DEF_VECT_ADDR); } -#if defined(CONFIG_PM) -static int vic_class_resume(struct sys_device *dev) +#ifdef CONFIG_PM +static void resume_one_vic(struct vic_device *vic) { - struct vic_device *vic = to_vic(dev); void __iomem *base = vic->base; printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); @@ -107,13 +98,18 @@ static int vic_class_resume(struct sys_device *dev) writel(vic->soft_int, base + VIC_INT_SOFT); writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); +} - return 0; +static void vic_resume(void) +{ + int id; + + for (id = vic_id - 1; id >= 0; id--) + resume_one_vic(vic_devices + id); } -static int vic_class_suspend(struct sys_device *dev, pm_message_t state) +static void suspend_one_vic(struct vic_device *vic) { - struct vic_device *vic = to_vic(dev); void __iomem *base = vic->base; printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); @@ -128,14 +124,21 @@ static int vic_class_suspend(struct sys_device *dev, pm_message_t state) writel(vic->resume_irqs, base + VIC_INT_ENABLE); writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); +} + +static int vic_suspend(void) +{ + int id; + + for (id = 0; id < vic_id; id++) + suspend_one_vic(vic_devices + id); return 0; } -struct sysdev_class vic_class = { - .name = "vic", - .suspend = vic_class_suspend, - .resume = vic_class_resume, +struct syscore_ops vic_syscore_ops = { + .suspend = vic_suspend, + .resume = vic_resume, }; /** @@ -147,30 +150,8 @@ struct sysdev_class vic_class = { */ static int __init vic_pm_init(void) { - struct vic_device *dev = vic_devices; - int err; - int id; - - if (vic_id == 0) - return 0; - - err = sysdev_class_register(&vic_class); - if (err) { - printk(KERN_ERR "%s: cannot register class\n", __func__); - return err; - } - - for (id = 0; id < vic_id; id++, dev++) { - dev->sysdev.id = id; - dev->sysdev.cls = &vic_class; - - err = sysdev_register(&dev->sysdev); - if (err) { - printk(KERN_ERR "%s: failed to register device\n", - __func__); - return err; - } - } + if (vic_id > 0) + register_syscore_ops(&vic_syscore_ops); return 0; } @@ -305,9 +286,9 @@ static void __init vic_set_irq_sources(void __iomem *base, if (vic_sources & (1 << i)) { unsigned int irq = irq_start + i; - set_irq_chip(irq, &vic_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &vic_chip, + handle_level_irq); + irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig new file mode 100644 index 00000000000..c55e9212fcb --- /dev/null +++ b/arch/arm/configs/at91x40_defconfig @@ -0,0 +1,48 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_EMBEDDED=y +# CONFIG_HOTPLUG is not set +# CONFIG_ELF_CORE is not set +# CONFIG_FUTEX is not set +# CONFIG_TIMERFD is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MMU is not set +CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91X40=y +CONFIG_MACH_AT91EB01=y +CONFIG_AT91_EARLY_USART0=y +CONFIG_CPU_ARM7TDMI=y +CONFIG_SET_MEM_PARAM=y +CONFIG_DRAM_BASE=0x01000000 +CONFIG_DRAM_SIZE=0x00400000 +CONFIG_FLASH_MEM_BASE=0x01400000 +CONFIG_PROCESSOR_ID=0x14000040 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_BINFMT_FLAT=y +# CONFIG_SUSPEND is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_ROMFS_FS=y +# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 54bf5eec801..40db34cf277 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_DOVE=y CONFIG_MACH_DOVE_DB=y -CONFIG_CPU_V6=y -CONFIG_CPU_32v6K=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_AEABI=y @@ -44,7 +42,6 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 -# CONFIG_MISC_DEVICES is not set # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set @@ -59,12 +56,12 @@ CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set # CONFIG_MOUSE_PS2 is not set # CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_DEVKMEM is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -72,12 +69,10 @@ CONFIG_I2C_MV64XXX=y CONFIG_SPI=y CONFIG_SPI_ORION=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set CONFIG_USB=y CONFIG_USB_DEVICEFS=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_STORAGE=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MV=y @@ -86,7 +81,6 @@ CONFIG_MV_XOR=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_UDF_FS=m @@ -110,23 +104,19 @@ CONFIG_DEBUG_KERNEL=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_DEFLATE=y diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig index b39b5ced8a1..c9436d0bf59 100644 --- a/arch/arm/configs/mx1_defconfig +++ b/arch/arm/configs/mx1_defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_MXC=y CONFIG_ARCH_MX1=y CONFIG_ARCH_MX1ADS=y CONFIG_MACH_SCB9328=y +CONFIG_MACH_APF9328=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index e3c903281f7..0ace16cba9b 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig @@ -13,7 +13,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_MXC=y -CONFIG_ARCH_MX5=y +CONFIG_ARCH_MX51=y CONFIG_MACH_MX51_BABBAGE=y CONFIG_MACH_MX51_3DS=y CONFIG_MACH_EUKREA_CPUIMX51=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig new file mode 100644 index 00000000000..2bf224310fb --- /dev/null +++ b/arch/arm/configs/mxs_defconfig @@ -0,0 +1,129 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MXS=y +CONFIG_MACH_STMP378X_DEVB=y +CONFIG_MACH_TX28=y +# CONFIG_ARM_THUMB is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_AUTO_ZRELADDR=y +CONFIG_FPE_NWFPE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_DEV=m +CONFIG_CAN_FLEXCAN=m +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_ENC28J60=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=m +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MXS=m +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_DISPLAY_SUPPORT=m +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_MXS=y +CONFIG_RTC_CLASS=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_DMADEVICES=y +CONFIG_MXS_DMA=y +CONFIG_EXT3_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PRINTK_TIME=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_TIMER_STATS=y +CONFIG_PROVE_LOCKING=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig deleted file mode 100644 index 1f528a00298..00000000000 --- a/arch/arm/configs/ns9xxx_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_NS9XXX=y -CONFIG_MACH_CC9P9360DEV=y -CONFIG_MACH_CC9P9360JS=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=m -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_SYN_COOKIES=y -CONFIG_MTD=m -CONFIG_MTD_CONCAT=m -CONFIG_MTD_CHAR=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_CFI=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_PHYSMAP=m -CONFIG_BLK_DEV_LOOP=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_GPIO=m -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_RTC_CLASS=m -CONFIG_EXT2_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig index 5ca7a61f7c0..abe61bf379d 100644 --- a/arch/arm/configs/realview-smp_defconfig +++ b/arch/arm/configs/realview-smp_defconfig @@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_PHYSMAP=y CONFIG_ARM_CHARLCD=y CONFIG_NETDEVICES=y CONFIG_SMSC_PHY=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index fcaa6032805..7079cbe898a 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_PHYSMAP=y CONFIG_ARM_CHARLCD=y CONFIG_NETDEVICES=y CONFIG_SMSC_PHY=y diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig deleted file mode 100644 index 824e44418b1..00000000000 --- a/arch/arm/configs/spear310_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_PLAT_SPEAR=y -CONFIG_MACH_SPEAR310=y -CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PL061=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_AUTOFS4_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -CONFIG_TMPFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig deleted file mode 100644 index 842f7f3c512..00000000000 --- a/arch/arm/configs/spear320_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_PLAT_SPEAR=y -CONFIG_MACH_SPEAR320=y -CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PL061=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_AUTOFS4_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -CONFIG_TMPFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear3xx_defconfig index cf29f3e5692..fea7e1f026a 100644 --- a/arch/arm/configs/spear300_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -7,6 +7,9 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PLAT_SPEAR=y +CONFIG_BOARD_SPEAR300_EVB=y +CONFIG_BOARD_SPEAR310_EVB=y +CONFIG_BOARD_SPEAR320_EVB=y CONFIG_BINFMT_MISC=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y @@ -24,7 +27,6 @@ CONFIG_MAX_RAW_DEVS=8192 CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear6xx_defconfig index 6777c11f63e..cef2e836afd 100644 --- a/arch/arm/configs/spear600_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y +CONFIG_BOARD_SPEAR600_EVB=y CONFIG_BINFMT_MISC=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y @@ -22,7 +23,6 @@ CONFIG_MAX_RAW_DEVS=8192 CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig deleted file mode 100644 index 1079c2b6eb3..00000000000 --- a/arch/arm/configs/stmp378x_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-default" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_STMP3XXX=y -CONFIG_ARCH_STMP378X=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NET_SCHED=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_MTD=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_GLUEBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=6144 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_SELFTEST=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_SLAB=y -CONFIG_DEBUG_SLAB_LEAK=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_PROVE_LOCKING=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_KOBJECT=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOT_TRACER=y -CONFIG_STACK_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig deleted file mode 100644 index 564a5cc4408..00000000000 --- a/arch/arm/configs/stmp37xx_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-default" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_STMP3XXX=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NET_SCHED=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=6144 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOT_TRACER=y -CONFIG_STACK_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_DEBUG_LL=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 0ce710f4750..cdd4d2bd396 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_EEPROM_LEGACY=m CONFIG_NETDEVICES=y diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index ed5bc9e05a4..cd4458f6417 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -2,6 +2,7 @@ #define __ASM_ARM_CPUTYPE_H #include <linux/stringify.h> +#include <linux/kernel.h> #define CPUID_ID 0 #define CPUID_CACHETYPE 1 diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index ca51143f97f..42005542932 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -6,8 +6,10 @@ /* * This is the maximum virtual address which can be DMA'd from. */ -#ifndef MAX_DMA_ADDRESS +#ifndef ARM_DMA_ZONE_SIZE #define MAX_DMA_ADDRESS 0xffffffff +#else +#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE) #endif #ifdef CONFIG_ISA_DMA_API diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index c3cd8755e64..0e9ce8d9686 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -108,6 +108,7 @@ struct task_struct; int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define ELF_CORE_COPY_TASK_REGS dump_task_regs +#define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h index ee5e03efc1b..3ad4c10d0d8 100644 --- a/arch/arm/include/asm/fpstate.h +++ b/arch/arm/include/asm/fpstate.h @@ -18,7 +18,7 @@ * VFP storage area has: * - FPEXC, FPSCR, FPINST and FPINST2. * - 16 or 32 double precision data registers - * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6) + * - an implementation-dependent word of state for FLDMX/FSTMX (pre-ARMv6) * * FPEXC will always be non-zero once the VFP has been used in this process. */ diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h index 199a6b6de7f..8c73900da9e 100644 --- a/arch/arm/include/asm/futex.h +++ b/arch/arm/include/asm/futex.h @@ -3,16 +3,74 @@ #ifdef __KERNEL__ +#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP) +/* ARM doesn't provide unprivileged exclusive memory accessors */ +#include <asm-generic/futex.h> +#else + +#include <linux/futex.h> +#include <linux/uaccess.h> +#include <asm/errno.h> + +#define __futex_atomic_ex_table(err_reg) \ + "3:\n" \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4f, 2b, 4f\n" \ + " .popsection\n" \ + " .pushsection .fixup,\"ax\"\n" \ + "4: mov %0, " err_reg "\n" \ + " b 3b\n" \ + " .popsection" + #ifdef CONFIG_SMP -#include <asm-generic/futex.h> +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ + smp_mb(); \ + __asm__ __volatile__( \ + "1: ldrex %1, [%2]\n" \ + " " insn "\n" \ + "2: strex %1, %0, [%2]\n" \ + " teq %1, #0\n" \ + " bne 1b\n" \ + " mov %0, #0\n" \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ + : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ + : "cc", "memory") + +static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + int ret; + u32 val; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + smp_mb(); + __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" + "1: ldrex %1, [%4]\n" + " teq %1, %2\n" + " ite eq @ explicit IT needed for the 2b label\n" + "2: strexeq %0, %3, [%4]\n" + " movne %0, #0\n" + " teq %0, #0\n" + " bne 1b\n" + __futex_atomic_ex_table("%5") + : "=&r" (ret), "=&r" (val) + : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) + : "cc", "memory"); + smp_mb(); + + *uval = val; + return ret; +} #else /* !SMP, we can work around lack of atomic ops by disabling preemption */ -#include <linux/futex.h> #include <linux/preempt.h> -#include <linux/uaccess.h> -#include <asm/errno.h> #include <asm/domain.h> #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ @@ -21,20 +79,38 @@ " " insn "\n" \ "2: " T(str) " %0, [%2]\n" \ " mov %0, #0\n" \ - "3:\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4f, 2b, 4f\n" \ - " .popsection\n" \ - " .pushsection .fixup,\"ax\"\n" \ - "4: mov %0, %4\n" \ - " b 3b\n" \ - " .popsection" \ + __futex_atomic_ex_table("%4") \ : "=&r" (ret), "=&r" (oldval) \ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ : "cc", "memory") static inline int +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + int ret = 0; + u32 val; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + return -EFAULT; + + __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" + "1: " T(ldr) " %1, [%4]\n" + " teq %1, %2\n" + " it eq @ explicit IT needed for the 2b label\n" + "2: " T(streq) " %3, [%4]\n" + __futex_atomic_ex_table("%5") + : "+r" (ret), "=&r" (val) + : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) + : "cc", "memory"); + + *uval = val; + return ret; +} + +#endif /* !SMP */ + +static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) { int op = (encoded_op >> 28) & 7; @@ -87,39 +163,6 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) return ret; } -static inline int -futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, - u32 oldval, u32 newval) -{ - int ret = 0; - u32 val; - - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) - return -EFAULT; - - __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" - "1: " T(ldr) " %1, [%4]\n" - " teq %1, %2\n" - " it eq @ explicit IT needed for the 2b label\n" - "2: " T(streq) " %3, [%4]\n" - "3:\n" - " .pushsection __ex_table,\"a\"\n" - " .align 3\n" - " .long 1b, 4f, 2b, 4f\n" - " .popsection\n" - " .pushsection .fixup,\"ax\"\n" - "4: mov %0, %5\n" - " b 3b\n" - " .popsection" - : "+r" (ret), "=&r" (val) - : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) - : "cc", "memory"); - - *uval = val; - return ret; -} - -#endif /* !SMP */ - +#endif /* !(CPU_USE_DOMAINS && SMP) */ #endif /* __KERNEL__ */ #endif /* _ASM_ARM_FUTEX_H */ diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index c7afbc552c7..7e30874377e 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -126,7 +126,7 @@ #endif #if !defined(_CACHE) && !defined(MULTI_CACHE) -#error Unknown cache maintainence model +#error Unknown cache maintenance model #endif #ifndef MULTI_CACHE diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h index 0ec35d1698a..fbf71d75ec8 100644 --- a/arch/arm/include/asm/glue.h +++ b/arch/arm/include/asm/glue.h @@ -10,8 +10,8 @@ * * This file provides the glue to stick the processor-specific bits * into the kernel in an efficient manner. The idea is to use branches - * when we're only targetting one class of TLB, or indirect calls - * when we're targetting multiple classes of TLBs. + * when we're only targeting one class of TLB, or indirect calls + * when we're targeting multiple classes of TLBs. */ #ifdef __KERNEL__ diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h index f35b86e68dd..e4a04e4e562 100644 --- a/arch/arm/include/asm/hardware/pl080.h +++ b/arch/arm/include/asm/hardware/pl080.h @@ -16,7 +16,7 @@ * make it not entierly compatible with the PL080 specification from * ARM. When in doubt, check the Samsung documentation first. * - * The Samsung defines are PL080S, and add an extra controll register, + * The Samsung defines are PL080S, and add an extra control register, * the ability to move more than 2^11 counts of data and some extra * OneNAND features. */ diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h index 21e75e30d49..4384d81eee7 100644 --- a/arch/arm/include/asm/hardware/timer-sp.h +++ b/arch/arm/include/asm/hardware/timer-sp.h @@ -1,2 +1,2 @@ -void sp804_clocksource_init(void __iomem *); -void sp804_clockevents_init(void __iomem *, unsigned int); +void sp804_clocksource_init(void __iomem *, const char *); +void sp804_clockevents_init(void __iomem *, unsigned int, const char *); diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h index 5586b7c8ef6..a71b417b185 100644 --- a/arch/arm/include/asm/hw_irq.h +++ b/arch/arm/include/asm/hw_irq.h @@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq) irq_err_count++; } -/* - * Obsolete inline function for calling irq descriptor handlers. - */ -static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) -{ - desc->handle_irq(irq, desc); -} - void set_irq_flags(unsigned int irq, unsigned int flags); #define IRQF_VALID (1 << 0) diff --git a/arch/arm/include/asm/i8253.h b/arch/arm/include/asm/i8253.h new file mode 100644 index 00000000000..70656b69d5c --- /dev/null +++ b/arch/arm/include/asm/i8253.h @@ -0,0 +1,15 @@ +#ifndef __ASMARM_I8253_H +#define __ASMARM_I8253_H + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 + +#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) + +extern raw_spinlock_t i8253_lock; + +#define outb_pit outb_p +#define inb_pit inb_p + +#endif diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h index bb8a19bd582..e46bdd0097e 100644 --- a/arch/arm/include/asm/kprobes.h +++ b/arch/arm/include/asm/kprobes.h @@ -39,10 +39,13 @@ typedef u32 kprobe_opcode_t; struct kprobe; typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *); +typedef unsigned long (kprobe_check_cc)(unsigned long); + /* Architecture specific copy of original instruction. */ struct arch_specific_insn { kprobe_opcode_t *insn; kprobe_insn_handler_t *insn_handler; + kprobe_check_cc *insn_check_cc; }; struct prev_kprobe { diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index 883f6be5117..d5adaae5ee2 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -34,7 +34,6 @@ * timer interrupt which may be pending. */ struct sys_timer { - struct sys_device dev; void (*init)(void); void (*suspend)(void); void (*resume)(void); diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h index 833306ee9e7..ea297ac70bc 100644 --- a/arch/arm/include/asm/mach/udc_pxa2xx.h +++ b/arch/arm/include/asm/mach/udc_pxa2xx.h @@ -20,8 +20,6 @@ struct pxa2xx_udc_mach_info { * VBUS IRQ and omit the methods above. Store the GPIO number * here. Note that sometimes the signals go through inverters... */ - bool gpio_vbus_inverted; - int gpio_vbus; /* high == vbus present */ bool gpio_pullup_inverted; int gpio_pullup; /* high == pullup activated */ }; diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 431077c5a86..af44a8fb348 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x) * allocations. This must be the smallest DMA mask in the system, * so a successful GFP_DMA allocation will always satisfy this. */ -#ifndef ISA_DMA_THRESHOLD +#ifndef ARM_DMA_ZONE_SIZE #define ISA_DMA_THRESHOLD (0xffffffffULL) -#endif - -#ifndef arch_adjust_zones -#define arch_adjust_zones(size,holes) do { } while (0) -#elif !defined(CONFIG_ZONE_DMA) -#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA" +#else +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1) #endif /* diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index a8ff22b2a39..312d10877bd 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -128,6 +128,12 @@ struct pt_regs { #define ARM_r0 uregs[0] #define ARM_ORIG_r0 uregs[17] +/* + * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS + * and core dumps. + */ +#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ ) + #ifdef __KERNEL__ #define user_mode(regs) \ diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index 316bb2b2be3..154b89b81d3 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h @@ -16,44 +16,6 @@ /* Size definitions * Copyright (C) ARM Limited 1998. All rights reserved. */ +#include <asm-generic/sizes.h> -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_48M 0x03000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ +#define SZ_48M (SZ_32M + SZ_16M) diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 96ed521f240..a87664f54f9 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -14,8 +14,6 @@ #include <linux/cpumask.h> #include <linux/thread_info.h> -#include <mach/smp.h> - #ifndef CONFIG_SMP # error "<asm/smp.h> included in non-SMP build" #endif @@ -47,9 +45,9 @@ extern void smp_init_cpus(void); /* - * Raise an IPI cross call on CPUs in callmap. + * Provide a function to raise an IPI cross call on CPUs in callmap. */ -extern void smp_cross_call(const struct cpumask *mask, int ipi); +extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); /* * Boot a secondary CPU, and assign it the specified idle task. diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index fdd3820edff..65fa3c88095 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -5,6 +5,8 @@ #error SMP not supported on pre-ARMv6 CPUs #endif +#include <asm/processor.h> + /* * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K * extensions, so when running on UP, we have to patch these instructions away. diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9a87823642d..832888d0c20 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -159,7 +159,7 @@ extern unsigned int user_debug; #include <mach/barriers.h> #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) #define mb() do { dsb(); outer_sync(); } while (0) -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() #else #include <asm/memory.h> @@ -249,7 +249,7 @@ do { \ * cache totally. This means that the cache becomes inconsistent, and, * since we use normal loads/stores as well, this is really bad. * Typically, this causes oopsen in filp_close, but could have other, - * more disasterous effects. There are two work-arounds: + * more disastrous effects. There are two work-arounds: * 1. Disable interrupts and emulate the atomic swap * 2. Clean the cache, perform atomic swap, flush the cache * diff --git a/arch/arm/include/asm/thread_notify.h b/arch/arm/include/asm/thread_notify.h index c4391ba2035..1dc98067589 100644 --- a/arch/arm/include/asm/thread_notify.h +++ b/arch/arm/include/asm/thread_notify.h @@ -43,6 +43,7 @@ static inline void thread_notify(unsigned long rc, struct thread_info *thread) #define THREAD_NOTIFY_FLUSH 0 #define THREAD_NOTIFY_EXIT 1 #define THREAD_NOTIFY_SWITCH 2 +#define THREAD_NOTIFY_COPY 3 #endif #endif diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h index 47f023aa849..14749aec94b 100644 --- a/arch/arm/include/asm/ucontext.h +++ b/arch/arm/include/asm/ucontext.h @@ -47,7 +47,7 @@ struct crunch_sigframe { #endif #ifdef CONFIG_IWMMXT -/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */ +/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */ #define IWMMXT_MAGIC 0x12ef842a #define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8) diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index c891eb76c0e..87dbe3e2197 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -396,6 +396,10 @@ #define __NR_fanotify_init (__NR_SYSCALL_BASE+367) #define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) #define __NR_prlimit64 (__NR_SYSCALL_BASE+369) +#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) +#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) +#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) +#define __NR_syncfs (__NR_SYSCALL_BASE+373) /* * The following SWIs are ARM private. diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 74554f1742d..8d95446150a 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o -obj-$(CONFIG_PM) += sleep.o +obj-$(CONFIG_PM_SLEEP) += sleep.o obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o obj-$(CONFIG_SMP) += smp.o smp_tlb.o obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index d86fcd44b22..e4ee050aad7 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -159,31 +159,6 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); /* - * Same as above. The PrPMC800 carrier board for the PrPMC1100 - * card maps the host-bridge @ 00:01:00 for some reason and it - * ends up getting scanned. Note that we only want to do this - * fixup when we find the IXP4xx on a PrPMC system, which is why - * we check the machine type. We could be running on a board - * with an IXP4xx target device and we don't want to kill the - * resources in that case. - */ -static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev) -{ - int i; - - if (machine_is_prpmc1100()) { - dev->class &= 0xff; - dev->class |= PCI_CLASS_BRIDGE_HOST << 8; - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100); - -/* * PCI IDE controllers use non-standard I/O port decoding, respect it. */ static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 5c26eccef99..7fbf28c35bb 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -379,6 +379,10 @@ CALL(sys_fanotify_init) CALL(sys_fanotify_mark) CALL(sys_prlimit64) +/* 370 */ CALL(sys_name_to_handle_at) + CALL(sys_open_by_handle_at) + CALL(sys_clock_adjtime) + CALL(sys_syncfs) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index d2d983be096..bcd66e00bdb 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -25,7 +25,7 @@ .macro addruart, rp, rv .endm -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) .macro senduart, rd, rx mcr p14, 0, \rd, c0, c5, 0 @@ -49,23 +49,6 @@ 1002: .endm -#elif defined(CONFIG_CPU_V7) - - .macro senduart, rd, rx - mcr p14, 0, \rd, c0, c5, 0 - .endm - - .macro busyuart, rd, rx -busy: mrc p14, 0, pc, c0, c1, 0 - bcs busy - .endm - - .macro waituart, rd, rx -wait: mrc p14, 0, pc, c0, c1, 0 - bcs wait - - .endm - #elif defined(CONFIG_CPU_XSCALE) .macro senduart, rd, rx diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 2ad62df3773..d16500110ee 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type) */ if (slot < 8) { ec->irq = 32 + slot; - set_irq_chip(ec->irq, &ecard_chip); - set_irq_handler(ec->irq, handle_level_irq); + irq_set_chip_and_handler(ec->irq, &ecard_chip, + handle_level_irq); set_irq_flags(ec->irq, IRQF_VALID); } @@ -1103,7 +1103,7 @@ static int __init ecard_init(void) irqhw = ecard_probeirqhw(); - set_irq_chained_handler(IRQ_EXPANSIONCARD, + irq_set_chained_handler(IRQ_EXPANSIONCARD, irqhw ? ecard_irqexp_handler : ecard_irq_handler); ecard_proc_init(); diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c index d4a0da1e48f..9b05c6a0dce 100644 --- a/arch/arm/kernel/elf.c +++ b/arch/arm/kernel/elf.c @@ -40,15 +40,22 @@ EXPORT_SYMBOL(elf_check_arch); void elf_set_personality(const struct elf32_hdr *x) { unsigned int eflags = x->e_flags; - unsigned int personality = PER_LINUX_32BIT; + unsigned int personality = current->personality & ~PER_MASK; + + /* + * We only support Linux ELF executables, so always set the + * personality to LINUX. + */ + personality |= PER_LINUX; /* * APCS-26 is only valid for OABI executables */ - if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) { - if (eflags & EF_ARM_APCS_26) - personality = PER_LINUX; - } + if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN && + (eflags & EF_ARM_APCS_26)) + personality &= ~ADDR_LIMIT_32BIT; + else + personality |= ADDR_LIMIT_32BIT; set_personality(personality); diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 052b509e2d5..1bec8b5f22f 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -338,7 +338,7 @@ static struct miscdevice etb_miscdev = { .fops = &etb_fops, }; -static int __init etb_probe(struct amba_device *dev, const struct amba_id *id) +static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id) { struct tracectx *t = &tracer; int ret = 0; @@ -530,7 +530,7 @@ static ssize_t trace_mode_store(struct kobject *kobj, static struct kobj_attribute trace_mode_attr = __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store); -static int __init etm_probe(struct amba_device *dev, const struct amba_id *id) +static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id) { struct tracectx *t = &tracer; int ret = 0; diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 8dbc126f715..87acc25d7a3 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -868,6 +868,13 @@ static void reset_ctrl_regs(void *info) */ asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); isb(); + + /* + * Clear any configured vector-catch events before + * enabling monitor mode. + */ + asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); + isb(); } if (enable_monitor_mode()) diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 3535d3793e6..83bbad03fcc 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -51,63 +51,18 @@ unsigned long irq_err_count; -int show_interrupts(struct seq_file *p, void *v) +int arch_show_interrupts(struct seq_file *p, int prec) { - int i = *(loff_t *) v, cpu; - struct irq_desc *desc; - struct irqaction * action; - unsigned long flags; - int prec, n; - - for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++) - n *= 10; - -#ifdef CONFIG_SMP - if (prec < 4) - prec = 4; -#endif - - if (i == 0) { - char cpuname[12]; - - seq_printf(p, "%*s ", prec, ""); - for_each_present_cpu(cpu) { - sprintf(cpuname, "CPU%d", cpu); - seq_printf(p, " %10s", cpuname); - } - seq_putc(p, '\n'); - } - - if (i < nr_irqs) { - desc = irq_to_desc(i); - raw_spin_lock_irqsave(&desc->lock, flags); - action = desc->action; - if (!action) - goto unlock; - - seq_printf(p, "%*d: ", prec, i); - for_each_present_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); - seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); - seq_printf(p, " %s", action->name); - for (action = action->next; action; action = action->next) - seq_printf(p, ", %s", action->name); - - seq_putc(p, '\n'); -unlock: - raw_spin_unlock_irqrestore(&desc->lock, flags); - } else if (i == nr_irqs) { #ifdef CONFIG_FIQ - show_fiq_list(p, prec); + show_fiq_list(p, prec); #endif #ifdef CONFIG_SMP - show_ipi_list(p, prec); + show_ipi_list(p, prec); #endif #ifdef CONFIG_LOCAL_TIMERS - show_local_irqs(p, prec); + show_local_irqs(p, prec); #endif - seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); - } + seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); return 0; } @@ -144,24 +99,21 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs) void set_irq_flags(unsigned int irq, unsigned int iflags) { - struct irq_desc *desc; - unsigned long flags; + unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (irq >= nr_irqs) { printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); return; } - desc = irq_to_desc(irq); - raw_spin_lock_irqsave(&desc->lock, flags); - desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; if (iflags & IRQF_VALID) - desc->status &= ~IRQ_NOREQUEST; + clr |= IRQ_NOREQUEST; if (iflags & IRQF_PROBE) - desc->status &= ~IRQ_NOPROBE; + clr |= IRQ_NOPROBE; if (!(iflags & IRQF_NOAUTOEN)) - desc->status &= ~IRQ_NOAUTOEN; - raw_spin_unlock_irqrestore(&desc->lock, flags); + clr |= IRQ_NOAUTOEN; + /* Order is clear bits in "clr" then set bits in "set" */ + irq_modify_status(irq, clr, set & ~clr); } void __init init_IRQ(void) diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index 8f6ed43861f..15eeff6aea0 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c @@ -34,9 +34,6 @@ * * *) If the PC is written to by the instruction, the * instruction must be fully simulated in software. - * If it is a conditional instruction, the handler - * will use insn[0] to copy its condition code to - * set r0 to 1 and insn[1] to "mov pc, lr" to return. * * *) Otherwise, a modified form of the instruction is * directly executed. Its handler calls the @@ -68,13 +65,17 @@ #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25) +#define is_r15(insn, bitpos) (((insn) & (0xf << bitpos)) == (0xf << bitpos)) + +/* + * Test if load/store instructions writeback the address register. + * if P (bit 24) == 0 or W (bit 21) == 1 + */ +#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000) + #define PSR_fs (PSR_f|PSR_s) #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */ -#define SET_R0_TRUE_INSTRUCTION 0xe3a00001 /* mov r0, #1 */ - -#define truecc_insn(insn) (((insn) & 0xf0000000) | \ - (SET_R0_TRUE_INSTRUCTION & 0x0fffffff)) typedef long (insn_0arg_fn_t)(void); typedef long (insn_1arg_fn_t)(long); @@ -419,14 +420,10 @@ insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr, static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; long iaddr = (long)p->addr; int disp = branch_displacement(insn); - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - if (insn & (1 << 24)) regs->ARM_lr = iaddr + 4; @@ -446,14 +443,10 @@ static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs) static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; int rm = insn & 0xf; long rmv = regs->uregs[rm]; - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - if (insn & (1 << 5)) regs->ARM_lr = (long)p->addr + 4; @@ -463,9 +456,16 @@ static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs) regs->ARM_cpsr |= PSR_T_BIT; } +static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs) +{ + kprobe_opcode_t insn = p->opcode; + int rd = (insn >> 12) & 0xf; + unsigned long mask = 0xf8ff03df; /* Mask out execution state */ + regs->uregs[rd] = regs->ARM_cpsr & mask; +} + static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; int rn = (insn >> 16) & 0xf; int lbit = insn & (1 << 20); @@ -476,9 +476,6 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) int reg_bit_vector; int reg_count; - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - reg_count = 0; reg_bit_vector = insn & 0xffff; while (reg_bit_vector) { @@ -510,11 +507,6 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs) static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; - - if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn)) - return; - regs->ARM_pc = (long)p->addr + str_pc_offset; simulate_ldm1stm1(p, regs); regs->ARM_pc = (long)p->addr + 4; @@ -525,24 +517,16 @@ static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs) regs->uregs[12] = regs->uregs[13]; } -static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs) -{ - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - int rn = (insn >> 16) & 0xf; - long rnv = regs->uregs[rn]; - - /* Save Rn in case of writeback. */ - regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn); -} - static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs) { insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; + long ppc = (long)p->addr + 8; int rd = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; /* rm may be invalid, don't care. */ + long rmv = (rm == 15) ? ppc : regs->uregs[rm]; + long rnv = (rn == 15) ? ppc : regs->uregs[rn]; /* Not following the C calling convention here, so need asm(). */ __asm__ __volatile__ ( @@ -554,29 +538,36 @@ static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs) "str r0, %[rn] \n\t" /* in case of writeback */ "str r2, %[rd0] \n\t" "str r3, %[rd1] \n\t" - : [rn] "+m" (regs->uregs[rn]), + : [rn] "+m" (rnv), [rd0] "=m" (regs->uregs[rd]), [rd1] "=m" (regs->uregs[rd+1]) - : [rm] "m" (regs->uregs[rm]), + : [rm] "m" (rmv), [cpsr] "r" (regs->ARM_cpsr), [i_fn] "r" (i_fn) : "r0", "r1", "r2", "r3", "lr", "cc" ); + if (is_writeback(insn)) + regs->uregs[rn] = rnv; } static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs) { insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; + long ppc = (long)p->addr + 8; int rd = (insn >> 12) & 0xf; int rn = (insn >> 16) & 0xf; int rm = insn & 0xf; - long rnv = regs->uregs[rn]; - long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ + long rnv = (rn == 15) ? ppc : regs->uregs[rn]; + /* rm/rmv may be invalid, don't care. */ + long rmv = (rm == 15) ? ppc : regs->uregs[rm]; + long rnv_wb; - regs->uregs[rn] = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd], + rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd], regs->uregs[rd+1], regs->ARM_cpsr, i_fn); + if (is_writeback(insn)) + regs->uregs[rn] = rnv_wb; } static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs) @@ -594,7 +585,8 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs) long cpsr = regs->ARM_cpsr; fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn); - regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ + if (rn != 15) + regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ rdv = fnr.r1; if (rd == 15) { @@ -622,35 +614,11 @@ static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs) long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd]; long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn]; long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ + long rnv_wb; - /* Save Rn in case of writeback. */ - regs->uregs[rn] = - insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); -} - -static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs) -{ - insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - union reg_pair fnr; - int rd = (insn >> 12) & 0xf; - int rn = (insn >> 16) & 0xf; - - fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn); - regs->uregs[rn] = fnr.r0; - regs->uregs[rd] = fnr.r1; -} - -static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs) -{ - insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - int rd = (insn >> 12) & 0xf; - int rn = (insn >> 16) & 0xf; - long rnv = regs->uregs[rn]; - long rdv = regs->uregs[rd]; - - insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn); + rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); + if (rn != 15) + regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */ } static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs) @@ -686,32 +654,32 @@ static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs) insnslot_0arg_rflags(regs->ARM_cpsr, i_fn); } -static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs) +static void __kprobes emulate_nop(struct kprobe *p, struct pt_regs *regs) { - insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0]; - kprobe_opcode_t insn = p->opcode; - int rd = (insn >> 12) & 0xf; - - regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn); } -static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs) +static void __kprobes +emulate_rd12_modify(struct kprobe *p, struct pt_regs *regs) { insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; - int ird = (insn >> 12) & 0xf; + int rd = (insn >> 12) & 0xf; + long rdv = regs->uregs[rd]; - insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn); + regs->uregs[rd] = insnslot_1arg_rflags(rdv, regs->ARM_cpsr, i_fn); } -static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs) +static void __kprobes +emulate_rd12rn0_modify(struct kprobe *p, struct pt_regs *regs) { - insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; + insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0]; kprobe_opcode_t insn = p->opcode; - int rn = (insn >> 16) & 0xf; + int rd = (insn >> 12) & 0xf; + int rn = insn & 0xf; + long rdv = regs->uregs[rd]; long rnv = regs->uregs[rn]; - insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn); + regs->uregs[rd] = insnslot_2arg_rflags(rdv, rnv, regs->ARM_cpsr, i_fn); } static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs) @@ -817,6 +785,17 @@ emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs) } static void __kprobes +emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs) +{ + insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0]; + kprobe_opcode_t insn = p->opcode; + int rn = (insn >> 16) & 0xf; + long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn]; + + insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn); +} + +static void __kprobes emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs) { insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0]; @@ -852,14 +831,34 @@ emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs) insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn); } +static void __kprobes +emulate_alu_tests(struct kprobe *p, struct pt_regs *regs) +{ + insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0]; + kprobe_opcode_t insn = p->opcode; + long ppc = (long)p->addr + 8; + int rn = (insn >> 16) & 0xf; + int rs = (insn >> 8) & 0xf; /* rs/rsv may be invalid, don't care. */ + int rm = insn & 0xf; + long rnv = (rn == 15) ? ppc : regs->uregs[rn]; + long rmv = (rm == 15) ? ppc : regs->uregs[rm]; + long rsv = regs->uregs[rs]; + + insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn); +} + static enum kprobe_insn __kprobes prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi) { - int ibit = (insn & (1 << 26)) ? 25 : 22; + int not_imm = (insn & (1 << 26)) ? (insn & (1 << 25)) + : (~insn & (1 << 22)); + + if (is_writeback(insn) && is_r15(insn, 16)) + return INSN_REJECTED; /* Writeback to PC */ insn &= 0xfff00fff; insn |= 0x00001000; /* Rn = r0, Rd = r1 */ - if (insn & (1 << ibit)) { + if (not_imm) { insn &= ~0xf; insn |= 2; /* Rm = r2 */ } @@ -869,20 +868,40 @@ prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi) } static enum kprobe_insn __kprobes -prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi) +prep_emulate_rd12_modify(kprobe_opcode_t insn, struct arch_specific_insn *asi) { - insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + + insn &= 0xffff0fff; /* Rd = r0 */ asi->insn[0] = insn; - asi->insn_handler = emulate_rd12rm0; + asi->insn_handler = emulate_rd12_modify; return INSN_GOOD; } static enum kprobe_insn __kprobes -prep_emulate_rd12(kprobe_opcode_t insn, struct arch_specific_insn *asi) +prep_emulate_rd12rn0_modify(kprobe_opcode_t insn, + struct arch_specific_insn *asi) { - insn &= 0xffff0fff; /* Rd = r0 */ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + + insn &= 0xffff0ff0; /* Rd = r0 */ + insn |= 0x00000001; /* Rn = r1 */ + asi->insn[0] = insn; + asi->insn_handler = emulate_rd12rn0_modify; + return INSN_GOOD; +} + +static enum kprobe_insn __kprobes +prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi) +{ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + + insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */ asi->insn[0] = insn; - asi->insn_handler = emulate_rd12; + asi->insn_handler = emulate_rd12rm0; return INSN_GOOD; } @@ -890,6 +909,9 @@ static enum kprobe_insn __kprobes prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */ insn |= 0x00000001; /* Rm = r1 */ asi->insn[0] = insn; @@ -901,6 +923,9 @@ static enum kprobe_insn __kprobes prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 16)) + return INSN_REJECTED; /* Rd is PC */ + insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */ insn |= 0x00000001; /* Rm = r1 */ asi->insn[0] = insn; @@ -912,6 +937,9 @@ static enum kprobe_insn __kprobes prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 16)) + return INSN_REJECTED; /* Rd is PC */ + insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */ insn |= 0x00000102; /* Rs = r1, Rm = r2 */ asi->insn[0] = insn; @@ -923,6 +951,9 @@ static enum kprobe_insn __kprobes prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + if (is_r15(insn, 16) || is_r15(insn, 12)) + return INSN_REJECTED; /* RdHi or RdLo is PC */ + insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */ insn |= 0x00001203; /* Rs = r2, Rm = r3 */ asi->insn[0] = insn; @@ -943,20 +974,13 @@ prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn, static enum kprobe_insn __kprobes space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi) { - /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */ - /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */ - /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */ - if ((insn & 0xfff30020) == 0xf1020000 || - (insn & 0xfe500f00) == 0xf8100a00 || - (insn & 0xfe5f0f00) == 0xf84d0500) - return INSN_REJECTED; - - /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */ - if ((insn & 0xfd700000) == 0xf4500000) { - insn &= 0xfff0ffff; /* Rn = r0 */ - asi->insn[0] = insn; - asi->insn_handler = emulate_rn16; - return INSN_GOOD; + /* memory hint : 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx : */ + /* PLDI : 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx : */ + /* PLDW : 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx : */ + /* PLD : 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx : */ + if ((insn & 0xfe300000) == 0xf4100000) { + asi->insn_handler = emulate_nop; + return INSN_GOOD_NO_SLOT; } /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */ @@ -965,41 +989,22 @@ space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi) return INSN_GOOD_NO_SLOT; } - /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */ - /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ - if ((insn & 0xffff00f0) == 0xf1010000 || - (insn & 0xff000010) == 0xfe000000) { - asi->insn[0] = insn; - asi->insn_handler = emulate_none; - return INSN_GOOD; - } + /* CPS : 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */ + /* SETEND: 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */ + + /* SRS : 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */ + /* RFE : 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ + /* Coprocessor instructions... */ /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */ /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */ - if ((insn & 0xffe00000) == 0xfc400000) { - insn &= 0xfff00fff; /* Rn = r0 */ - insn |= 0x00001000; /* Rd = r1 */ - asi->insn[0] = insn; - asi->insn_handler = - (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr; - return INSN_GOOD; - } + /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ + /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ + /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ + /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ + /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ - /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ - if ((insn & 0xfe000000) == 0xfc000000) { - insn &= 0xfff0ffff; /* Rn = r0 */ - asi->insn[0] = insn; - asi->insn_handler = emulate_ldcstc; - return INSN_GOOD; - } - - /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ - /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - insn &= 0xffff0fff; /* Rd = r0 */ - asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12; - return INSN_GOOD; + return INSN_REJECTED; } static enum kprobe_insn __kprobes @@ -1008,19 +1013,18 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */ if ((insn & 0x0f900010) == 0x01000000) { - /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ - /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ - if ((insn & 0x0ff000f0) == 0x01200020 || - (insn & 0x0fb000f0) == 0x01200000) - return INSN_REJECTED; - - /* MRS : cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx */ - if ((insn & 0x0fb00010) == 0x01000000) - return prep_emulate_rd12(insn, asi); + /* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */ + if ((insn & 0x0ff000f0) == 0x01000000) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ + asi->insn_handler = simulate_mrs; + return INSN_GOOD_NO_SLOT; + } /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */ if ((insn & 0x0ff00090) == 0x01400080) - return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi); + return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, + asi); /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */ /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */ @@ -1029,24 +1033,29 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) return prep_emulate_rd16rs8rm0_wflags(insn, asi); /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */ - /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */ - return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx : Q */ + if ((insn & 0x0ff00090) == 0x01000080 || + (insn & 0x0ff000b0) == 0x01200080) + return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */ + /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */ + /* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */ + + /* Other instruction encodings aren't yet defined */ + return INSN_REJECTED; } /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */ else if ((insn & 0x0f900090) == 0x01000010) { - /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ - if ((insn & 0xfff000f0) == 0xe1200070) - return INSN_REJECTED; - /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */ /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */ if ((insn & 0x0ff000d0) == 0x01200010) { - asi->insn[0] = truecc_insn(insn); + if ((insn & 0x0ff000ff) == 0x0120003f) + return INSN_REJECTED; /* BLX pc */ asi->insn_handler = simulate_blx2bx; - return INSN_GOOD; + return INSN_GOOD_NO_SLOT; } /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */ @@ -1057,17 +1066,27 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */ /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */ /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */ - return prep_emulate_rd12rn16rm0_wflags(insn, asi); + if ((insn & 0x0f9000f0) == 0x01000050) + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + + /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ + /* SMC : cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */ + + /* Other instruction encodings aren't yet defined */ + return INSN_REJECTED; } /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */ - else if ((insn & 0x0f000090) == 0x00000090) { + else if ((insn & 0x0f0000f0) == 0x00000090) { /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */ /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */ /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */ /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */ /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */ + /* undef : cccc 0000 0101 xxxx xxxx xxxx 1001 xxxx : */ + /* MLS : cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx : */ + /* undef : cccc 0000 0111 xxxx xxxx xxxx 1001 xxxx : */ /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */ /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */ /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */ @@ -1076,13 +1095,15 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */ /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */ /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */ - if ((insn & 0x0fe000f0) == 0x00000090) { - return prep_emulate_rd16rs8rm0_wflags(insn, asi); - } else if ((insn & 0x0fe000f0) == 0x00200090) { - return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); - } else { - return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi); - } + if ((insn & 0x00d00000) == 0x00500000) + return INSN_REJECTED; + else if ((insn & 0x00e00000) == 0x00000000) + return prep_emulate_rd16rs8rm0_wflags(insn, asi); + else if ((insn & 0x00a00000) == 0x00200000) + return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + else + return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, + asi); } /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */ @@ -1090,23 +1111,45 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */ /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */ - /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */ - /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */ + /* ??? : cccc 0001 0x01 xxxx xxxx xxxx 1001 xxxx */ + /* ??? : cccc 0001 0x10 xxxx xxxx xxxx 1001 xxxx */ + /* ??? : cccc 0001 0x11 xxxx xxxx xxxx 1001 xxxx */ /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */ /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */ + /* STREXD: cccc 0001 1010 xxxx xxxx xxxx 1001 xxxx */ + /* LDREXD: cccc 0001 1011 xxxx xxxx xxxx 1001 xxxx */ + /* STREXB: cccc 0001 1100 xxxx xxxx xxxx 1001 xxxx */ + /* LDREXB: cccc 0001 1101 xxxx xxxx xxxx 1001 xxxx */ + /* STREXH: cccc 0001 1110 xxxx xxxx xxxx 1001 xxxx */ + /* LDREXH: cccc 0001 1111 xxxx xxxx xxxx 1001 xxxx */ + + /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */ + /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */ /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */ /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */ /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */ /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */ - if ((insn & 0x0fb000f0) == 0x01000090) { - /* SWP/SWPB */ - return prep_emulate_rd12rn16rm0_wflags(insn, asi); + if ((insn & 0x0f0000f0) == 0x01000090) { + if ((insn & 0x0fb000f0) == 0x01000090) { + /* SWP/SWPB */ + return prep_emulate_rd12rn16rm0_wflags(insn, + asi); + } else { + /* STREX/LDREX variants and unallocaed space */ + return INSN_REJECTED; + } + } else if ((insn & 0x0e1000d0) == 0x00000d0) { /* STRD/LDRD */ + if ((insn & 0x0000e000) == 0x0000e000) + return INSN_REJECTED; /* Rd is LR or PC */ + if (is_writeback(insn) && is_r15(insn, 16)) + return INSN_REJECTED; /* Writeback to PC */ + insn &= 0xfff00fff; insn |= 0x00002000; /* Rn = r0, Rd = r2 */ - if (insn & (1 << 22)) { - /* I bit */ + if (!(insn & (1 << 22))) { + /* Register index */ insn &= ~0xf; insn |= 1; /* Rm = r1 */ } @@ -1116,6 +1159,9 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) return INSN_GOOD; } + /* LDRH/STRH/LDRSB/LDRSH */ + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ return prep_emulate_ldr_str(insn, asi); } @@ -1123,7 +1169,7 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* * ALU op with S bit and Rd == 15 : - * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx + * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */ if ((insn & 0x0e10f000) == 0x0010f000) return INSN_REJECTED; @@ -1152,22 +1198,61 @@ space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi) insn |= 0x00000200; /* Rs = r2 */ } asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ + + if ((insn & 0x0f900000) == 0x01100000) { + /* + * TST : cccc 0001 0001 xxxx xxxx xxxx xxxx xxxx + * TEQ : cccc 0001 0011 xxxx xxxx xxxx xxxx xxxx + * CMP : cccc 0001 0101 xxxx xxxx xxxx xxxx xxxx + * CMN : cccc 0001 0111 xxxx xxxx xxxx xxxx xxxx + */ + asi->insn_handler = emulate_alu_tests; + } else { + /* ALU ops which write to Rd */ + asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ emulate_alu_rwflags : emulate_alu_rflags; + } return INSN_GOOD; } static enum kprobe_insn __kprobes space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + /* MOVW : cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */ + /* MOVT : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */ + if ((insn & 0x0fb00000) == 0x03000000) + return prep_emulate_rd12_modify(insn, asi); + + /* hints : cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */ + if ((insn & 0x0fff0000) == 0x03200000) { + unsigned op2 = insn & 0x000000ff; + if (op2 == 0x01 || op2 == 0x04) { + /* YIELD : cccc 0011 0010 0000 xxxx xxxx 0000 0001 */ + /* SEV : cccc 0011 0010 0000 xxxx xxxx 0000 0100 */ + asi->insn[0] = insn; + asi->insn_handler = emulate_none; + return INSN_GOOD; + } else if (op2 <= 0x03) { + /* NOP : cccc 0011 0010 0000 xxxx xxxx 0000 0000 */ + /* WFE : cccc 0011 0010 0000 xxxx xxxx 0000 0010 */ + /* WFI : cccc 0011 0010 0000 xxxx xxxx 0000 0011 */ + /* + * We make WFE and WFI true NOPs to avoid stalls due + * to missing events whilst processing the probe. + */ + asi->insn_handler = emulate_nop; + return INSN_GOOD_NO_SLOT; + } + /* For DBG and unallocated hints it's safest to reject them */ + return INSN_REJECTED; + } + /* * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx - * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx * ALU op with S bit and Rd == 15 : * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */ if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */ - (insn & 0x0ff00000) == 0x03400000 || /* Undef */ (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */ return INSN_REJECTED; @@ -1178,10 +1263,22 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) * *S (bit 20) updates condition codes * ADC/SBC/RSC reads the C flag */ - insn &= 0xffff0fff; /* Rd = r0 */ + insn &= 0xfff00fff; /* Rn = r0 and Rd = r0 */ asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ + + if ((insn & 0x0f900000) == 0x03100000) { + /* + * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx + * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx + * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx + * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx + */ + asi->insn_handler = emulate_alu_tests_imm; + } else { + /* ALU ops which write to Rd */ + asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ emulate_alu_imm_rwflags : emulate_alu_imm_rflags; + } return INSN_GOOD; } @@ -1190,6 +1287,8 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) { /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */ if ((insn & 0x0ff000f0) == 0x068000b0) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */ insn |= 0x00000001; /* Rm = r1 */ asi->insn[0] = insn; @@ -1203,6 +1302,8 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */ if ((insn & 0x0fa00030) == 0x06a00010 || (insn & 0x0fb000f0) == 0x06a00030) { + if (is_r15(insn, 12)) + return INSN_REJECTED; /* Rd is PC */ insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */ asi->insn[0] = insn; asi->insn_handler = emulate_sat; @@ -1211,57 +1312,101 @@ space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */ /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */ + /* RBIT : cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */ /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */ if ((insn & 0x0ff00070) == 0x06b00030 || - (insn & 0x0ff000f0) == 0x06f000b0) + (insn & 0x0ff00070) == 0x06f00030) return prep_emulate_rd12rm0(insn, asi); + /* ??? : cccc 0110 0000 xxxx xxxx xxxx xxx1 xxxx : */ /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */ /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */ /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */ /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */ /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */ + /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1101 xxxx : */ /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */ /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */ /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */ /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */ /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */ /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1101 xxxx : */ /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */ /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */ /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */ /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */ /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */ /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1101 xxxx : */ /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */ + /* ??? : cccc 0110 0100 xxxx xxxx xxxx xxx1 xxxx : */ /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */ /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */ /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */ /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */ /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */ + /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1101 xxxx : */ /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */ /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */ /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */ /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */ /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */ /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1101 xxxx : */ /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */ /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */ /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */ /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */ /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */ /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */ + /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1011 xxxx : */ + /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1101 xxxx : */ /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */ + if ((insn & 0x0f800010) == 0x06000010) { + if ((insn & 0x00300000) == 0x00000000 || + (insn & 0x000000e0) == 0x000000a0 || + (insn & 0x000000e0) == 0x000000c0) + return INSN_REJECTED; /* Unallocated space */ + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + } + /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */ /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */ + if ((insn & 0x0ff00030) == 0x06800010) + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */ - /* SXTB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */ + /* SXTB16 : cccc 0110 1000 1111 xxxx xxxx 0111 xxxx : */ + /* ??? : cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx : */ /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */ + /* SXTB : cccc 0110 1010 1111 xxxx xxxx 0111 xxxx : */ /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */ + /* SXTH : cccc 0110 1011 1111 xxxx xxxx 0111 xxxx : */ /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */ + /* UXTB16 : cccc 0110 1100 1111 xxxx xxxx 0111 xxxx : */ + /* ??? : cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx : */ /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */ + /* UXTB : cccc 0110 1110 1111 xxxx xxxx 0111 xxxx : */ /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */ - return prep_emulate_rd12rn16rm0_wflags(insn, asi); + /* UXTH : cccc 0110 1111 1111 xxxx xxxx 0111 xxxx : */ + if ((insn & 0x0f8000f0) == 0x06800070) { + if ((insn & 0x00300000) == 0x00100000) + return INSN_REJECTED; /* Unallocated space */ + + if ((insn & 0x000f0000) == 0x000f0000) + return prep_emulate_rd12rm0(insn, asi); + else + return prep_emulate_rd12rn16rm0_wflags(insn, asi); + } + + /* Other instruction encodings aren't yet defined */ + return INSN_REJECTED; } static enum kprobe_insn __kprobes @@ -1271,29 +1416,49 @@ space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi) if ((insn & 0x0ff000f0) == 0x03f000f0) return INSN_REJECTED; - /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */ - /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */ - if ((insn & 0x0ff000f0) == 0x07800010) - return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); - /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */ /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */ if ((insn & 0x0ff00090) == 0x07400010) return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi); /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */ + /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */ /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */ + /* SMUSD : cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx : */ /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */ - /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */ + /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */ + /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx : */ + /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx : */ if ((insn & 0x0ff00090) == 0x07000010 || (insn & 0x0ff000d0) == 0x07500010 || - (insn & 0x0ff000d0) == 0x075000d0) + (insn & 0x0ff000f0) == 0x07800010) { + + if ((insn & 0x0000f000) == 0x0000f000) + return prep_emulate_rd16rs8rm0_wflags(insn, asi); + else + return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); + } + + /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */ + if ((insn & 0x0ff000d0) == 0x075000d0) return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi); - /* SMUSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx : */ - /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */ - /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */ - return prep_emulate_rd16rs8rm0_wflags(insn, asi); + /* SBFX : cccc 0111 101x xxxx xxxx xxxx x101 xxxx : */ + /* UBFX : cccc 0111 111x xxxx xxxx xxxx x101 xxxx : */ + if ((insn & 0x0fa00070) == 0x07a00050) + return prep_emulate_rd12rm0(insn, asi); + + /* BFI : cccc 0111 110x xxxx xxxx xxxx x001 xxxx : */ + /* BFC : cccc 0111 110x xxxx xxxx xxxx x001 1111 : */ + if ((insn & 0x0fe00070) == 0x07c00010) { + + if ((insn & 0x0000000f) == 0x0000000f) + return prep_emulate_rd12_modify(insn, asi); + else + return prep_emulate_rd12rn0_modify(insn, asi); + } + + return INSN_REJECTED; } static enum kprobe_insn __kprobes @@ -1307,6 +1472,10 @@ space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */ /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */ /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */ + + if ((insn & 0x00500000) == 0x00500000 && is_r15(insn, 12)) + return INSN_REJECTED; /* LDRB into PC */ + return prep_emulate_ldr_str(insn, asi); } @@ -1321,10 +1490,9 @@ space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi) /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */ /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */ - asi->insn[0] = truecc_insn(insn); asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */ simulate_stm1_pc : simulate_ldm1stm1; - return INSN_GOOD; + return INSN_GOOD_NO_SLOT; } static enum kprobe_insn __kprobes @@ -1332,58 +1500,117 @@ space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi) { /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */ /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */ - asi->insn[0] = truecc_insn(insn); asi->insn_handler = simulate_bbl; - return INSN_GOOD; + return INSN_GOOD_NO_SLOT; } static enum kprobe_insn __kprobes -space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi) +space_cccc_11xx(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + /* Coprocessor instructions... */ /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */ /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */ - insn &= 0xfff00fff; - insn |= 0x00001000; /* Rn = r0, Rd = r1 */ - asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr; - return INSN_GOOD; + /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ + /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ + /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ + /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ + /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ + + /* SVC : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */ + + return INSN_REJECTED; } -static enum kprobe_insn __kprobes -space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static unsigned long __kprobes __check_eq(unsigned long cpsr) { - /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */ - /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */ - insn &= 0xfff0ffff; /* Rn = r0 */ - asi->insn[0] = insn; - asi->insn_handler = emulate_ldcstc; - return INSN_GOOD; + return cpsr & PSR_Z_BIT; } -static enum kprobe_insn __kprobes -space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi) +static unsigned long __kprobes __check_ne(unsigned long cpsr) { - /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */ - /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */ - if ((insn & 0xfff000f0) == 0xe1200070 || - (insn & 0x0f000000) == 0x0f000000) - return INSN_REJECTED; + return (~cpsr) & PSR_Z_BIT; +} - /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */ - if ((insn & 0x0f000010) == 0x0e000000) { - asi->insn[0] = insn; - asi->insn_handler = emulate_none; - return INSN_GOOD; - } +static unsigned long __kprobes __check_cs(unsigned long cpsr) +{ + return cpsr & PSR_C_BIT; +} - /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */ - /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */ - insn &= 0xffff0fff; /* Rd = r0 */ - asi->insn[0] = insn; - asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12; - return INSN_GOOD; +static unsigned long __kprobes __check_cc(unsigned long cpsr) +{ + return (~cpsr) & PSR_C_BIT; } +static unsigned long __kprobes __check_mi(unsigned long cpsr) +{ + return cpsr & PSR_N_BIT; +} + +static unsigned long __kprobes __check_pl(unsigned long cpsr) +{ + return (~cpsr) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_vs(unsigned long cpsr) +{ + return cpsr & PSR_V_BIT; +} + +static unsigned long __kprobes __check_vc(unsigned long cpsr) +{ + return (~cpsr) & PSR_V_BIT; +} + +static unsigned long __kprobes __check_hi(unsigned long cpsr) +{ + cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return cpsr & PSR_C_BIT; +} + +static unsigned long __kprobes __check_ls(unsigned long cpsr) +{ + cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ + return (~cpsr) & PSR_C_BIT; +} + +static unsigned long __kprobes __check_ge(unsigned long cpsr) +{ + cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return (~cpsr) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_lt(unsigned long cpsr) +{ + cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + return cpsr & PSR_N_BIT; +} + +static unsigned long __kprobes __check_gt(unsigned long cpsr) +{ + unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ + return (~temp) & PSR_N_BIT; +} + +static unsigned long __kprobes __check_le(unsigned long cpsr) +{ + unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */ + temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */ + return temp & PSR_N_BIT; +} + +static unsigned long __kprobes __check_al(unsigned long cpsr) +{ + return true; +} + +static kprobe_check_cc * const condition_checks[16] = { + &__check_eq, &__check_ne, &__check_cs, &__check_cc, + &__check_mi, &__check_pl, &__check_vs, &__check_vc, + &__check_hi, &__check_ls, &__check_ge, &__check_lt, + &__check_gt, &__check_le, &__check_al, &__check_al +}; + /* Return: * INSN_REJECTED If instruction is one not allowed to kprobe, * INSN_GOOD If instruction is supported and uses instruction slot, @@ -1399,133 +1626,45 @@ space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi) enum kprobe_insn __kprobes arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi) { + asi->insn_check_cc = condition_checks[insn>>28]; asi->insn[1] = KPROBE_RETURN_INSTRUCTION; - if ((insn & 0xf0000000) == 0xf0000000) { + if ((insn & 0xf0000000) == 0xf0000000) return space_1111(insn, asi); - } else if ((insn & 0x0e000000) == 0x00000000) { + else if ((insn & 0x0e000000) == 0x00000000) return space_cccc_000x(insn, asi); - } else if ((insn & 0x0e000000) == 0x02000000) { + else if ((insn & 0x0e000000) == 0x02000000) return space_cccc_001x(insn, asi); - } else if ((insn & 0x0f000010) == 0x06000010) { + else if ((insn & 0x0f000010) == 0x06000010) return space_cccc_0110__1(insn, asi); - } else if ((insn & 0x0f000010) == 0x07000010) { + else if ((insn & 0x0f000010) == 0x07000010) return space_cccc_0111__1(insn, asi); - } else if ((insn & 0x0c000000) == 0x04000000) { + else if ((insn & 0x0c000000) == 0x04000000) return space_cccc_01xx(insn, asi); - } else if ((insn & 0x0e000000) == 0x08000000) { + else if ((insn & 0x0e000000) == 0x08000000) return space_cccc_100x(insn, asi); - } else if ((insn & 0x0e000000) == 0x0a000000) { + else if ((insn & 0x0e000000) == 0x0a000000) return space_cccc_101x(insn, asi); - } else if ((insn & 0x0fe00000) == 0x0c400000) { - - return space_cccc_1100_010x(insn, asi); - - } else if ((insn & 0x0e000000) == 0x0c000000) { - - return space_cccc_110x(insn, asi); - - } - - return space_cccc_111x(insn, asi); + return space_cccc_11xx(insn, asi); } void __init arm_kprobe_decode_init(void) { find_str_pc_offset(); } - - -/* - * All ARM instructions listed below. - * - * Instructions and their general purpose registers are given. - * If a particular register may not use R15, it is prefixed with a "!". - * If marked with a "*" means the value returned by reading R15 - * is implementation defined. - * - * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ - * TST: Rd, Rn, Rm, !Rs - * BX: Rm - * BLX(2): !Rm - * BX: Rm (R15 legal, but discouraged) - * BXJ: !Rm, - * CLZ: !Rd, !Rm - * CPY: Rd, Rm - * LDC/2,STC/2 immediate offset & unindex: Rn - * LDC/2,STC/2 immediate pre/post-indexed: !Rn - * LDM(1/3): !Rn, register_list - * LDM(2): !Rn, !register_list - * LDR,STR,PLD immediate offset: Rd, Rn - * LDR,STR,PLD register offset: Rd, Rn, !Rm - * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm - * LDR,STR immediate pre/post-indexed: Rd, !Rn - * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm - * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm - * LDRB,STRB immediate offset: !Rd, Rn - * LDRB,STRB register offset: !Rd, Rn, !Rm - * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm - * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn - * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm - * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm - * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn - * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm - * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm - * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn - * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm - * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn - * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm - * LDREX: !Rd, !Rn - * MCR/2: !Rd - * MCRR/2,MRRC/2: !Rd, !Rn - * MLA: !Rd, !Rn, !Rm, !Rs - * MOV: Rd - * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register) - * MRS,MSR: !Rd - * MUL: !Rd, !Rm, !Rs - * PKH{BT,TB}: !Rd, !Rn, !Rm - * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn - * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn - * REV/16/SH: !Rd, !Rm - * RFE: !Rn - * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm - * SEL: !Rd, !Rn, !Rm - * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs - * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs - * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs - * SSAT/16: !Rd, !Rm - * STM(1/2): !Rn, register_list* (R15 in reg list not recommended) - * STRT immediate pre/post-indexed: Rd*, !Rn - * STRT register pre/post-indexed: Rd*, !Rn, !Rm - * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm - * STREX: !Rd, !Rn, !Rm - * SWP/B: !Rd, !Rn, !Rm - * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm - * {S,U}XT{B,B16,H}: !Rd, !Rm - * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs - * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs - * - * May transfer control by writing R15 (possible mode changes or alternate - * mode accesses marked by "*"): - * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY, - * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI* - * - * Instructions that do not take general registers, nor transfer control: - * CDP/2, SETEND, SRS* - */ diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c index 2ba7deb3072..1656c87501c 100644 --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c @@ -134,7 +134,8 @@ static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) { regs->ARM_pc += 4; - p->ainsn.insn_handler(p, regs); + if (p->ainsn.insn_check_cc(regs->ARM_cpsr)) + p->ainsn.insn_handler(p, regs); } /* diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c index 31a316c1777..0f107dcb034 100644 --- a/arch/arm/kernel/leds.c +++ b/arch/arm/kernel/leds.c @@ -10,6 +10,7 @@ #include <linux/module.h> #include <linux/init.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <asm/leds.h> @@ -69,36 +70,37 @@ static ssize_t leds_store(struct sys_device *dev, static SYSDEV_ATTR(event, 0200, NULL, leds_store); -static int leds_suspend(struct sys_device *dev, pm_message_t state) +static struct sysdev_class leds_sysclass = { + .name = "leds", +}; + +static struct sys_device leds_device = { + .id = 0, + .cls = &leds_sysclass, +}; + +static int leds_suspend(void) { leds_event(led_stop); return 0; } -static int leds_resume(struct sys_device *dev) +static void leds_resume(void) { leds_event(led_start); - return 0; } -static int leds_shutdown(struct sys_device *dev) +static void leds_shutdown(void) { leds_event(led_halted); - return 0; } -static struct sysdev_class leds_sysclass = { - .name = "leds", +static struct syscore_ops leds_syscore_ops = { .shutdown = leds_shutdown, .suspend = leds_suspend, .resume = leds_resume, }; -static struct sys_device leds_device = { - .id = 0, - .cls = &leds_sysclass, -}; - static int __init leds_init(void) { int ret; @@ -107,6 +109,8 @@ static int __init leds_init(void) ret = sysdev_register(&leds_device); if (ret == 0) ret = sysdev_create_file(&leds_device, &attr_event); + if (ret == 0) + register_syscore_ops(&leds_syscore_ops); return ret; } diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 22e194eb853..d53c0abc4dd 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -79,6 +79,7 @@ struct arm_pmu { void (*write_counter)(int idx, u32 val); void (*start)(void); void (*stop)(void); + void (*reset)(void *); const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; @@ -204,11 +205,9 @@ armpmu_event_set_period(struct perf_event *event, static u64 armpmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, - int idx) + int idx, int overflow) { - int shift = 64 - 32; - s64 prev_raw_count, new_raw_count; - u64 delta; + u64 delta, prev_raw_count, new_raw_count; again: prev_raw_count = local64_read(&hwc->prev_count); @@ -218,8 +217,13 @@ again: new_raw_count) != prev_raw_count) goto again; - delta = (new_raw_count << shift) - (prev_raw_count << shift); - delta >>= shift; + new_raw_count &= armpmu->max_period; + prev_raw_count &= armpmu->max_period; + + if (overflow) + delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; + else + delta = new_raw_count - prev_raw_count; local64_add(delta, &event->count); local64_sub(delta, &hwc->period_left); @@ -236,7 +240,7 @@ armpmu_read(struct perf_event *event) if (hwc->idx < 0) return; - armpmu_event_update(event, hwc, hwc->idx); + armpmu_event_update(event, hwc, hwc->idx, 0); } static void @@ -254,7 +258,7 @@ armpmu_stop(struct perf_event *event, int flags) if (!(hwc->state & PERF_HES_STOPPED)) { armpmu->disable(hwc, hwc->idx); barrier(); /* why? */ - armpmu_event_update(event, hwc, hwc->idx); + armpmu_event_update(event, hwc, hwc->idx, 0); hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; } } @@ -556,11 +560,6 @@ static int armpmu_event_init(struct perf_event *event) event->destroy = hw_perf_event_destroy; if (!atomic_inc_not_zero(&active_events)) { - if (atomic_read(&active_events) > armpmu->num_events) { - atomic_dec(&active_events); - return -ENOSPC; - } - mutex_lock(&pmu_reserve_mutex); if (atomic_read(&active_events) == 0) { err = armpmu_reserve_hardware(); @@ -624,6 +623,19 @@ static struct pmu pmu = { #include "perf_event_v6.c" #include "perf_event_v7.c" +/* + * Ensure the PMU has sane values out of reset. + * This requires SMP to be available, so exists as a separate initcall. + */ +static int __init +armpmu_reset(void) +{ + if (armpmu && armpmu->reset) + return on_each_cpu(armpmu->reset, NULL, 1); + return 0; +} +arch_initcall(armpmu_reset); + static int __init init_hw_perf_events(void) { @@ -729,7 +741,8 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) tail = (struct frame_tail __user *)regs->ARM_fp - 1; - while (tail && !((unsigned long)tail & 0x3)) + while ((entry->nr < PERF_MAX_STACK_DEPTH) && + tail && !((unsigned long)tail & 0x3)) tail = user_backtrace(tail, entry); } diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 6fc2d228db5..f1e8dd94afe 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -474,7 +474,7 @@ armv6pmu_handle_irq(int irq_num, continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 2e1402556fa..4960686afb5 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -466,6 +466,7 @@ static inline unsigned long armv7_pmnc_read(void) static inline void armv7_pmnc_write(unsigned long val) { val &= ARMV7_PMNC_MASK; + isb(); asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); } @@ -502,6 +503,7 @@ static inline int armv7_pmnc_select_counter(unsigned int idx) val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); + isb(); return idx; } @@ -780,7 +782,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; @@ -847,6 +849,18 @@ static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, } } +static void armv7pmu_reset(void *info) +{ + u32 idx, nb_cnt = armpmu->num_events; + + /* The counter and interrupt enable registers are unknown at reset. */ + for (idx = 1; idx < nb_cnt; ++idx) + armv7pmu_disable_event(NULL, idx); + + /* Initialize & Reset PMNC: C and P bits */ + armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); +} + static struct arm_pmu armv7pmu = { .handle_irq = armv7pmu_handle_irq, .enable = armv7pmu_enable_event, @@ -856,17 +870,15 @@ static struct arm_pmu armv7pmu = { .get_event_idx = armv7pmu_get_event_idx, .start = armv7pmu_start, .stop = armv7pmu_stop, + .reset = armv7pmu_reset, .raw_event_mask = 0xFF, .max_period = (1LLU << 32) - 1, }; -static u32 __init armv7_reset_read_pmnc(void) +static u32 __init armv7_read_num_pmnc_events(void) { u32 nb_cnt; - /* Initialize & Reset PMNC: C and P bits */ - armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); - /* Read the nb of CNTx counters supported from PMNC */ nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; @@ -880,7 +892,7 @@ static const struct arm_pmu *__init armv7_a8_pmu_init(void) armv7pmu.name = "ARMv7 Cortex-A8"; armv7pmu.cache_map = &armv7_a8_perf_cache_map; armv7pmu.event_map = &armv7_a8_perf_map; - armv7pmu.num_events = armv7_reset_read_pmnc(); + armv7pmu.num_events = armv7_read_num_pmnc_events(); return &armv7pmu; } @@ -890,7 +902,7 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void) armv7pmu.name = "ARMv7 Cortex-A9"; armv7pmu.cache_map = &armv7_a9_perf_cache_map; armv7pmu.event_map = &armv7_a9_perf_map; - armv7pmu.num_events = armv7_reset_read_pmnc(); + armv7pmu.num_events = armv7_read_num_pmnc_events(); return &armv7pmu; } #else diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 28cd3b025bc..39affbe4fdb 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -246,7 +246,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev) continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; @@ -578,7 +578,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev) continue; hwc = &event->hw; - armpmu_event_update(event, hwc, idx); + armpmu_event_update(event, hwc, idx, 1); data.period = event->hw.last_period; if (!armpmu_event_set_period(event, hwc, idx)) continue; diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 94bbedbed63..5e1e5419722 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -372,6 +372,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start, if (clone_flags & CLONE_SETTLS) thread->tp_value = regs->ARM_r3; + thread_notify(THREAD_NOTIFY_COPY, thread); + return 0; } diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 2bf27f364d0..97260060bf2 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -21,6 +21,7 @@ #include <linux/uaccess.h> #include <linux/perf_event.h> #include <linux/hw_breakpoint.h> +#include <linux/regset.h> #include <asm/pgtable.h> #include <asm/system.h> @@ -308,58 +309,6 @@ static int ptrace_write_user(struct task_struct *tsk, unsigned long off, return put_user_reg(tsk, off >> 2, val); } -/* - * Get all user integer registers. - */ -static int ptrace_getregs(struct task_struct *tsk, void __user *uregs) -{ - struct pt_regs *regs = task_pt_regs(tsk); - - return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0; -} - -/* - * Set all user integer registers. - */ -static int ptrace_setregs(struct task_struct *tsk, void __user *uregs) -{ - struct pt_regs newregs; - int ret; - - ret = -EFAULT; - if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) { - struct pt_regs *regs = task_pt_regs(tsk); - - ret = -EINVAL; - if (valid_user_regs(&newregs)) { - *regs = newregs; - ret = 0; - } - } - - return ret; -} - -/* - * Get the child FPU state. - */ -static int ptrace_getfpregs(struct task_struct *tsk, void __user *ufp) -{ - return copy_to_user(ufp, &task_thread_info(tsk)->fpstate, - sizeof(struct user_fp)) ? -EFAULT : 0; -} - -/* - * Set the child FPU state. - */ -static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp) -{ - struct thread_info *thread = task_thread_info(tsk); - thread->used_cp[1] = thread->used_cp[2] = 1; - return copy_from_user(&thread->fpstate, ufp, - sizeof(struct user_fp)) ? -EFAULT : 0; -} - #ifdef CONFIG_IWMMXT /* @@ -418,56 +367,6 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp) } #endif -#ifdef CONFIG_VFP -/* - * Get the child VFP state. - */ -static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data) -{ - struct thread_info *thread = task_thread_info(tsk); - union vfp_state *vfp = &thread->vfpstate; - struct user_vfp __user *ufp = data; - - vfp_sync_hwstate(thread); - - /* copy the floating point registers */ - if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, - sizeof(vfp->hard.fpregs))) - return -EFAULT; - - /* copy the status and control register */ - if (put_user(vfp->hard.fpscr, &ufp->fpscr)) - return -EFAULT; - - return 0; -} - -/* - * Set the child VFP state. - */ -static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) -{ - struct thread_info *thread = task_thread_info(tsk); - union vfp_state *vfp = &thread->vfpstate; - struct user_vfp __user *ufp = data; - - vfp_sync_hwstate(thread); - - /* copy the floating point registers */ - if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, - sizeof(vfp->hard.fpregs))) - return -EFAULT; - - /* copy the status and control register */ - if (get_user(vfp->hard.fpscr, &ufp->fpscr)) - return -EFAULT; - - vfp_flush_hwstate(thread); - - return 0; -} -#endif - #ifdef CONFIG_HAVE_HW_BREAKPOINT /* * Convert a virtual register number into an index for a thread_info @@ -694,6 +593,219 @@ out: } #endif +/* regset get/set implementations */ + +static int gpr_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + struct pt_regs *regs = task_pt_regs(target); + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs, + 0, sizeof(*regs)); +} + +static int gpr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct pt_regs newregs; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &newregs, + 0, sizeof(newregs)); + if (ret) + return ret; + + if (!valid_user_regs(&newregs)) + return -EINVAL; + + *task_pt_regs(target) = newregs; + return 0; +} + +static int fpa_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &task_thread_info(target)->fpstate, + 0, sizeof(struct user_fp)); +} + +static int fpa_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct thread_info *thread = task_thread_info(target); + + thread->used_cp[1] = thread->used_cp[2] = 1; + + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &thread->fpstate, + 0, sizeof(struct user_fp)); +} + +#ifdef CONFIG_VFP +/* + * VFP register get/set implementations. + * + * With respect to the kernel, struct user_fp is divided into three chunks: + * 16 or 32 real VFP registers (d0-d15 or d0-31) + * These are transferred to/from the real registers in the task's + * vfp_hard_struct. The number of registers depends on the kernel + * configuration. + * + * 16 or 0 fake VFP registers (d16-d31 or empty) + * i.e., the user_vfp structure has space for 32 registers even if + * the kernel doesn't have them all. + * + * vfp_get() reads this chunk as zero where applicable + * vfp_set() ignores this chunk + * + * 1 word for the FPSCR + * + * The bounds-checking logic built into user_regset_copyout and friends + * means that we can make a simple sequence of calls to map the relevant data + * to/from the specified slice of the user regset structure. + */ +static int vfp_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + struct thread_info *thread = task_thread_info(target); + struct vfp_hard_struct const *vfp = &thread->vfpstate.hard; + const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); + const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); + + vfp_sync_hwstate(thread); + + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &vfp->fpregs, + user_fpregs_offset, + user_fpregs_offset + sizeof(vfp->fpregs)); + if (ret) + return ret; + + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + user_fpregs_offset + sizeof(vfp->fpregs), + user_fpscr_offset); + if (ret) + return ret; + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &vfp->fpscr, + user_fpscr_offset, + user_fpscr_offset + sizeof(vfp->fpscr)); +} + +/* + * For vfp_set() a read-modify-write is done on the VFP registers, + * in order to avoid writing back a half-modified set of registers on + * failure. + */ +static int vfp_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct thread_info *thread = task_thread_info(target); + struct vfp_hard_struct new_vfp = thread->vfpstate.hard; + const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs); + const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &new_vfp.fpregs, + user_fpregs_offset, + user_fpregs_offset + sizeof(new_vfp.fpregs)); + if (ret) + return ret; + + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + user_fpregs_offset + sizeof(new_vfp.fpregs), + user_fpscr_offset); + if (ret) + return ret; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &new_vfp.fpscr, + user_fpscr_offset, + user_fpscr_offset + sizeof(new_vfp.fpscr)); + if (ret) + return ret; + + vfp_sync_hwstate(thread); + thread->vfpstate.hard = new_vfp; + vfp_flush_hwstate(thread); + + return 0; +} +#endif /* CONFIG_VFP */ + +enum arm_regset { + REGSET_GPR, + REGSET_FPR, +#ifdef CONFIG_VFP + REGSET_VFP, +#endif +}; + +static const struct user_regset arm_regsets[] = { + [REGSET_GPR] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(u32), + .align = sizeof(u32), + .get = gpr_get, + .set = gpr_set + }, + [REGSET_FPR] = { + /* + * For the FPA regs in fpstate, the real fields are a mixture + * of sizes, so pretend that the registers are word-sized: + */ + .core_note_type = NT_PRFPREG, + .n = sizeof(struct user_fp) / sizeof(u32), + .size = sizeof(u32), + .align = sizeof(u32), + .get = fpa_get, + .set = fpa_set + }, +#ifdef CONFIG_VFP + [REGSET_VFP] = { + /* + * Pretend that the VFP regs are word-sized, since the FPSCR is + * a single word dangling at the end of struct user_vfp: + */ + .core_note_type = NT_ARM_VFP, + .n = ARM_VFPREGS_SIZE / sizeof(u32), + .size = sizeof(u32), + .align = sizeof(u32), + .get = vfp_get, + .set = vfp_set + }, +#endif /* CONFIG_VFP */ +}; + +static const struct user_regset_view user_arm_view = { + .name = "arm", .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, + .regsets = arm_regsets, .n = ARRAY_SIZE(arm_regsets) +}; + +const struct user_regset_view *task_user_regset_view(struct task_struct *task) +{ + return &user_arm_view; +} + long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { @@ -710,19 +822,31 @@ long arch_ptrace(struct task_struct *child, long request, break; case PTRACE_GETREGS: - ret = ptrace_getregs(child, datap); + ret = copy_regset_to_user(child, + &user_arm_view, REGSET_GPR, + 0, sizeof(struct pt_regs), + datap); break; case PTRACE_SETREGS: - ret = ptrace_setregs(child, datap); + ret = copy_regset_from_user(child, + &user_arm_view, REGSET_GPR, + 0, sizeof(struct pt_regs), + datap); break; case PTRACE_GETFPREGS: - ret = ptrace_getfpregs(child, datap); + ret = copy_regset_to_user(child, + &user_arm_view, REGSET_FPR, + 0, sizeof(union fp_state), + datap); break; - + case PTRACE_SETFPREGS: - ret = ptrace_setfpregs(child, datap); + ret = copy_regset_from_user(child, + &user_arm_view, REGSET_FPR, + 0, sizeof(union fp_state), + datap); break; #ifdef CONFIG_IWMMXT @@ -757,22 +881,36 @@ long arch_ptrace(struct task_struct *child, long request, #ifdef CONFIG_VFP case PTRACE_GETVFPREGS: - ret = ptrace_getvfpregs(child, datap); + ret = copy_regset_to_user(child, + &user_arm_view, REGSET_VFP, + 0, ARM_VFPREGS_SIZE, + datap); break; case PTRACE_SETVFPREGS: - ret = ptrace_setvfpregs(child, datap); + ret = copy_regset_from_user(child, + &user_arm_view, REGSET_VFP, + 0, ARM_VFPREGS_SIZE, + datap); break; #endif #ifdef CONFIG_HAVE_HW_BREAKPOINT case PTRACE_GETHBPREGS: + if (ptrace_get_breakpoints(child) < 0) + return -ESRCH; + ret = ptrace_gethbpregs(child, addr, (unsigned long __user *)data); + ptrace_put_breakpoints(child); break; case PTRACE_SETHBPREGS: + if (ptrace_get_breakpoints(child) < 0) + return -ESRCH; + ret = ptrace_sethbpregs(child, addr, (unsigned long __user *)data); + ptrace_put_breakpoints(child); break; #endif diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 006c1e884ea..6dce209a623 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -672,11 +672,16 @@ __tagtable(ATAG_REVISION, parse_tag_revision); static int __init parse_tag_cmdline(const struct tag *tag) { -#ifndef CONFIG_CMDLINE_FORCE - strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); -#else +#if defined(CONFIG_CMDLINE_EXTEND) + strlcat(default_command_line, " ", COMMAND_LINE_SIZE); + strlcat(default_command_line, tag->u.cmdline.cmdline, + COMMAND_LINE_SIZE); +#elif defined(CONFIG_CMDLINE_FORCE) pr_warning("Ignoring tag cmdline (using the default kernel command line)\n"); -#endif /* CONFIG_CMDLINE_FORCE */ +#else + strlcpy(default_command_line, tag->u.cmdline.cmdline, + COMMAND_LINE_SIZE); +#endif return 0; } diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index cb839831764..0340224cf73 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -597,19 +597,13 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info, return err; } -static inline void setup_syscall_restart(struct pt_regs *regs) -{ - regs->ARM_r0 = regs->ARM_ORIG_r0; - regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; -} - /* * OK, we're invoking a handler */ static int handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, - struct pt_regs * regs, int syscall) + struct pt_regs * regs) { struct thread_info *thread = current_thread_info(); struct task_struct *tsk = current; @@ -617,26 +611,6 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, int ret; /* - * If we were from a system call, check for system call restarting... - */ - if (syscall) { - switch (regs->ARM_r0) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->ARM_r0 = -EINTR; - break; - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->ARM_r0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - setup_syscall_restart(regs); - } - } - - /* * translate the signal */ if (usig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap) @@ -685,6 +659,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, */ static void do_signal(struct pt_regs *regs, int syscall) { + unsigned int retval = 0, continue_addr = 0, restart_addr = 0; struct k_sigaction ka; siginfo_t info; int signr; @@ -698,18 +673,61 @@ static void do_signal(struct pt_regs *regs, int syscall) if (!user_mode(regs)) return; + /* + * If we were from a system call, check for system call restarting... + */ + if (syscall) { + continue_addr = regs->ARM_pc; + restart_addr = continue_addr - (thumb_mode(regs) ? 2 : 4); + retval = regs->ARM_r0; + + /* + * Prepare for system call restart. We do this here so that a + * debugger will see the already changed PSW. + */ + switch (retval) { + case -ERESTARTNOHAND: + case -ERESTARTSYS: + case -ERESTARTNOINTR: + regs->ARM_r0 = regs->ARM_ORIG_r0; + regs->ARM_pc = restart_addr; + break; + case -ERESTART_RESTARTBLOCK: + regs->ARM_r0 = -EINTR; + break; + } + } + if (try_to_freeze()) goto no_signal; + /* + * Get the signal to deliver. When running under ptrace, at this + * point the debugger may change all our registers ... + */ signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { sigset_t *oldset; + /* + * Depending on the signal settings we may need to revert the + * decision to restart the system call. But skip this if a + * debugger has chosen to restart at a different PC. + */ + if (regs->ARM_pc == restart_addr) { + if (retval == -ERESTARTNOHAND + || (retval == -ERESTARTSYS + && !(ka.sa.sa_flags & SA_RESTART))) { + regs->ARM_r0 = -EINTR; + regs->ARM_pc = continue_addr; + } + } + if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = ¤t->saved_sigmask; else oldset = ¤t->blocked; - if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) { + if (handle_signal(signr, &ka, &info, oldset, regs) == 0) { /* * A signal was successfully delivered; the saved * sigmask will have been stored in the signal frame, @@ -723,11 +741,14 @@ static void do_signal(struct pt_regs *regs, int syscall) } no_signal: - /* - * No signal to deliver to the process - restart the syscall. - */ if (syscall) { - if (regs->ARM_r0 == -ERESTART_RESTARTBLOCK) { + /* + * Handle restarting a different system call. As above, + * if a debugger has chosen to restart at a different PC, + * ignore the restart. + */ + if (retval == -ERESTART_RESTARTBLOCK + && regs->ARM_pc == continue_addr) { if (thumb_mode(regs)) { regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE; regs->ARM_pc -= 2; @@ -750,11 +771,6 @@ static void do_signal(struct pt_regs *regs, int syscall) #endif } } - if (regs->ARM_r0 == -ERESTARTNOHAND || - regs->ARM_r0 == -ERESTARTSYS || - regs->ARM_r0 == -ERESTARTNOINTR) { - setup_syscall_restart(regs); - } /* If there's no signal to deliver, we just put the saved sigmask * back. diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index bfad698a02e..6398ead9d1c 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -119,11 +119,19 @@ ENTRY(cpu_resume) #else ldr r0, sleep_save_sp @ stack phys addr #endif - msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off + setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off #ifdef MULTI_CPU - ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn + @ load v:p, stack, return fn, resume fn + ARM( ldmia r0!, {r1, sp, lr, pc} ) +THUMB( ldmia r0!, {r1, r2, r3, r4} ) +THUMB( mov sp, r2 ) +THUMB( mov lr, r3 ) +THUMB( bx r4 ) #else - ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn + @ load v:p, stack, return fn + ARM( ldmia r0!, {r1, sp, lr} ) +THUMB( ldmia r0!, {r1, r2, lr} ) +THUMB( mov sp, r2 ) b cpu_do_resume #endif ENDPROC(cpu_resume) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 8fe05ad932e..d439a8f4c07 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } +static void (*smp_cross_call)(const struct cpumask *, unsigned int); + +void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) +{ + smp_cross_call = fn; +} + void arch_send_call_function_ipi_mask(const struct cpumask *mask) { smp_cross_call(mask, IPI_CALL_FUNC); @@ -479,7 +486,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode, { } -static void broadcast_timer_setup(struct clock_event_device *evt) +static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt) { evt->name = "dummy_timer"; evt->features = CLOCK_EVT_FEAT_ONESHOT | @@ -560,10 +567,7 @@ asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) break; case IPI_RESCHEDULE: - /* - * nothing more to do - eveything is - * done on the interrupt return path - */ + scheduler_ipi(); break; case IPI_CALL_FUNC: diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index 7a576092291..40ee7e5045e 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -158,7 +158,7 @@ static int emulate_swpX(unsigned int address, unsigned int *data, if (res == 0) { /* - * Barrier also required between aquiring a lock for a + * Barrier also required between acquiring a lock for a * protected resource and accessing the resource. Inserted for * same reason as above. */ diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 4ad8da15ef2..af0aaebf4de 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -311,7 +311,7 @@ asmlinkage long sys_oabi_semtimedop(int semid, long err; int i; - if (nsops < 1) + if (nsops < 1 || nsops > SEMOPM) return -EINVAL; sops = kmalloc(sizeof(*sops) * nsops, GFP_KERNEL); if (!sops) diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 1ff46cabc7e..cb634c3e28e 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -21,7 +21,7 @@ #include <linux/timex.h> #include <linux/errno.h> #include <linux/profile.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/timer.h> #include <linux/irq.h> @@ -115,48 +115,37 @@ void timer_tick(void) #endif #if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS) -static int timer_suspend(struct sys_device *dev, pm_message_t state) +static int timer_suspend(void) { - struct sys_timer *timer = container_of(dev, struct sys_timer, dev); - - if (timer->suspend != NULL) - timer->suspend(); + if (system_timer->suspend) + system_timer->suspend(); return 0; } -static int timer_resume(struct sys_device *dev) +static void timer_resume(void) { - struct sys_timer *timer = container_of(dev, struct sys_timer, dev); - - if (timer->resume != NULL) - timer->resume(); - - return 0; + if (system_timer->resume) + system_timer->resume(); } #else #define timer_suspend NULL #define timer_resume NULL #endif -static struct sysdev_class timer_sysclass = { - .name = "timer", +static struct syscore_ops timer_syscore_ops = { .suspend = timer_suspend, .resume = timer_resume, }; -static int __init timer_init_sysfs(void) +static int __init timer_init_syscore_ops(void) { - int ret = sysdev_class_register(&timer_sysclass); - if (ret == 0) { - system_timer->dev.cls = &timer_sysclass; - ret = sysdev_register(&system_timer->dev); - } + register_syscore_ops(&timer_syscore_ops); - return ret; + return 0; } -device_initcall(timer_init_sysfs); +device_initcall(timer_init_syscore_ops); void __init time_init(void) { diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index f0000e188c8..d52eec268b4 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -234,7 +234,6 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", str, err, ++die_counter); - sysfs_printk_last_file(); /* trap and error numbers are mostly meaningless on ARM */ ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV); @@ -410,8 +409,7 @@ static int bad_syscall(int n, struct pt_regs *regs) struct thread_info *thread = current_thread_info(); siginfo_t info; - if (current->personality != PER_LINUX && - current->personality != PER_LINUX_32BIT && + if ((current->personality & PER_MASK) != PER_LINUX && thread->exec_domain->handler) { thread->exec_domain->handler(n, regs); return regs->ARM_r0; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 19390231a0e..2d299bf5d72 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -83,6 +83,7 @@ config ARCH_AT91CAP9 select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL + select HAVE_NET_MACB config ARCH_AT572D940HF bool "AT572D940HF" diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index d1f775e8635..21020ceb2f3 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c @@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) return; if (cpu_is_at91cap9_revB()) - set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { @@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = { void __init at91_add_device_usba(struct usba_platform_data *data) { if (cpu_is_at91cap9_revB()) { - set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | AT91_MATRIX_UDPHS_BYPASS_LOCK); } @@ -171,7 +171,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) */ usba_udc_data.pdata.vbus_pin = -EINVAL; usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); - memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; + memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); if (data && data->vbus_pin > 0) { at91_set_gpio_input(data->vbus_pin, 0); @@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) return; if (cpu_is_at91cap9_revB()) - set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 1e8f275c17f..5e9f8a4c38d 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -256,7 +256,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) { usba_udc_data.pdata.vbus_pin = -EINVAL; usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); - memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; + memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); if (data && data->vbus_pin > 0) { at91_set_gpio_input(data->vbus_pin, 0); diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 53aaa94df75..c49262bddd8 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -145,7 +145,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) */ usba_udc_data.pdata.vbus_pin = -EINVAL; usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); - memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; + memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); if (data && data->vbus_pin > 0) { at91_set_gpio_input(data->vbus_pin, 0); diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 2e74a19874d..295e1e77fa6 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -76,7 +76,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = { .pullup_pin = AT91_PIN_PD9, }; -/* FIXME: user dependant */ +/* FIXME: user dependent */ // static struct at91_cf_data __initdata carmeva_cf_data = { // .det_pin = AT91_PIN_PB0, // .rst_pin = AT91_PIN_PC5, diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c index 1f9d3cb64c5..d8df59a3426 100644 --- a/arch/arm/mach-at91/board-eb01.c +++ b/arch/arm/mach-at91/board-eb01.c @@ -30,6 +30,11 @@ #include <mach/board.h> #include "generic.h" +static void __init at91eb01_init_irq(void) +{ + at91x40_init_interrupts(NULL); +} + static void __init at91eb01_map_io(void) { at91x40_initialize(40000000); @@ -38,7 +43,7 @@ static void __init at91eb01_map_io(void) MACHINE_START(AT91EB01, "Atmel AT91 EB01") /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ .timer = &at91x40_timer, - .init_irq = at91x40_init_interrupts, + .init_irq = at91eb01_init_irq, .map_io = at91eb01_map_io, MACHINE_END diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index af818a21587..4615528205c 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) else wakeups[bank] &= ~mask; - set_irq_wake(gpio_chip[bank].bank->id, state); + irq_set_irq_wake(gpio_chip[bank].bank->id, state); return 0; } @@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) static struct irq_chip gpio_irqchip = { .name = "GPIO", + .irq_disable = gpio_irq_mask, .irq_mask = gpio_irq_mask, .irq_unmask = gpio_irq_unmask, .irq_set_type = gpio_irq_type, @@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { unsigned pin; - struct irq_desc *gpio; - struct at91_gpio_chip *at91_gpio; - void __iomem *pio; + struct irq_data *idata = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_data_get_irq_chip(idata); + struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); + void __iomem *pio = at91_gpio->regbase; u32 isr; - at91_gpio = get_irq_chip_data(irq); - pio = at91_gpio->regbase; - /* temporarily mask (level sensitive) parent IRQ */ - desc->irq_data.chip->irq_ack(&desc->irq_data); + chip->irq_ack(idata); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. * When there none are pending, we're finished unless we need @@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) } pin = at91_gpio->chip.base; - gpio = &irq_desc[pin]; while (isr) { - if (isr & 1) { - if (unlikely(gpio->depth)) { - /* - * The core ARM interrupt handler lazily disables IRQs so - * another IRQ must be generated before it actually gets - * here to be disabled on the GPIO controller. - */ - gpio_irq_mask(irq_get_irq_data(pin)); - } - else - generic_handle_irq(pin); - } + if (isr & 1) + generic_handle_irq(pin); pin++; - gpio++; isr >>= 1; } } - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chip->irq_unmask(idata); /* now it may re-trigger */ } @@ -518,14 +505,14 @@ void __init at91_gpio_irq_setup(void) __raw_writel(~0, this->regbase + PIO_IDR); for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { - lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); + irq_set_lockdep_class(pin, &gpio_lock_class); /* * Can use the "simple" and not "edge" handler since it's * shorter, and the AIC handles interrupts sanely. */ - set_irq_chip(pin, &gpio_irqchip); - set_irq_handler(pin, handle_simple_irq); + irq_set_chip_and_handler(pin, &gpio_irqchip, + handle_simple_irq); set_irq_flags(pin, IRQF_VALID); } @@ -536,8 +523,8 @@ void __init at91_gpio_irq_setup(void) if (prev && prev->next == this) continue; - set_irq_chip_data(id, this); - set_irq_chained_handler(id, gpio_irq_handler); + irq_set_chip_data(id, this); + irq_set_chained_handler(id, gpio_irq_handler); } pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); } diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h index 2d9b0af9c4d..be510cfc56b 100644 --- a/arch/arm/mach-at91/include/mach/at572d940hf.h +++ b/arch/arm/mach-at91/include/mach/at572d940hf.h @@ -89,7 +89,7 @@ /* * System Peripherals (offset from AT91_BASE_SYS) */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h index 27ac6f550fe..02182c16a02 100644 --- a/arch/arm/mach-at91/include/mach/at91_mci.h +++ b/arch/arm/mach-at91/include/mach/at91_mci.h @@ -102,7 +102,7 @@ #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ +#define AT91_MCI_RTOE (1 << 20) /* Response Time-out Error */ #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ #define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ #define AT91_MCI_OVRE (1 << 30) /* Overrun */ diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 3bef931d0b1..0700f212530 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -27,6 +27,7 @@ #define ARCH_ID_AT91SAM9G45 0x819b05a0 #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ +#define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_AT91CAP9 0x039A03A0 #define ARCH_ID_AT91SAM9XE128 0x329973a0 @@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9G46 0x00000003 #define ARCH_EXID_AT91SAM9G45 0x00000004 +#define ARCH_EXID_AT91SAM9G15 0x00000000 +#define ARCH_EXID_AT91SAM9G35 0x00000001 +#define ARCH_EXID_AT91SAM9X35 0x00000002 +#define ARCH_EXID_AT91SAM9G25 0x00000003 +#define ARCH_EXID_AT91SAM9X25 0x00000004 + static inline unsigned long at91_exid_identify(void) { return at91_sys_read(AT91_DBGU_EXID); @@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void) #define cpu_is_at91sam9m11() (0) #endif +#ifdef CONFIG_ARCH_AT91SAM9X5 +#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5) +#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G15)) +#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G35)) +#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9X35)) +#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G25)) +#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9X25)) +#else +#define cpu_is_at91sam9x5() (0) +#define cpu_is_at91sam9g15() (0) +#define cpu_is_at91sam9g35() (0) +#define cpu_is_at91sam9x35() (0) +#define cpu_is_at91sam9g25() (0) +#define cpu_is_at91sam9x25() (0) +#endif + #ifdef CONFIG_ARCH_AT91CAP9 #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) #define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index ddeb6453675..056dc6674b6 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -208,7 +208,7 @@ extern void at91_gpio_resume(void); /*-------------------------------------------------------------------------*/ -/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should +/* wrappers for "new style" GPIO calls. the old AT91-specific ones should * eventually be removed (along with this errno.h inclusion), and the * gpio request/free calls should probably be implemented. */ diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index b56d6b3a408..9665265ec75 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) /* Active Low interrupt, with the specified priority */ at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); - set_irq_chip(i, &at91_aic_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index 73eb066d232..a604b9ebb50 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c @@ -169,6 +169,7 @@ MACHINE_START(BCMRING, "BCMRING") /* Maintainer: Broadcom Corporation */ .fixup = bcmring_fixup, .map_io = bcmring_map_io, + .init_early = bcmring_init_early, .init_irq = bcmring_init_irq, .timer = &bcmring_timer, .init_machine = bcmring_init_machine diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 8fc2035759f..43eadbcc29e 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -28,8 +28,6 @@ #include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/amba/bus.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> #include <linux/clkdev.h> #include <mach/csp/mm_addr.h> @@ -37,6 +35,7 @@ #include <linux/io.h> #include <asm/irq.h> #include <asm/hardware/arm_timer.h> +#include <asm/hardware/timer-sp.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -97,6 +96,35 @@ static struct clk dummy_apb_pclk = { .mode = CLK_MODE_XTAL, }; +/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ +#if defined(CONFIG_ARCH_FPGA11107) +/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ +/* slow down Linux's sense of time */ +#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) +#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) +#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) +#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) +#else +#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ +#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ +#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ +#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) +#endif + +static struct clk sp804_timer012_clk = { + .name = "sp804-timer-0,1,2", + .type = CLK_TYPE_PRIMARY, + .mode = CLK_MODE_XTAL, + .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000, +}; + +static struct clk sp804_timer3_clk = { + .name = "sp804-timer-3", + .type = CLK_TYPE_PRIMARY, + .mode = CLK_MODE_XTAL, + .rate_hz = TIMER3_FREQUENCY_KHZ * 1000, +}; + static struct clk_lookup lookups[] = { { /* Bus clock */ .con_id = "apb_pclk", @@ -107,6 +135,18 @@ static struct clk_lookup lookups[] = { }, { /* UART1 */ .dev_id = "uartb", .clk = &uart_clk, + }, { /* SP804 timer 0 */ + .dev_id = "sp804", + .con_id = "timer0", + .clk = &sp804_timer012_clk, + }, { /* SP804 timer 1 */ + .dev_id = "sp804", + .con_id = "timer1", + .clk = &sp804_timer012_clk, + }, { /* SP804 timer 3 */ + .dev_id = "sp804", + .con_id = "timer3", + .clk = &sp804_timer3_clk, } }; @@ -151,8 +191,6 @@ void __init bcmring_amba_init(void) chipcHw_busInterfaceClockEnable(bus_clock); - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); @@ -162,170 +200,18 @@ void __init bcmring_amba_init(void) /* * Where is the timer (VA)? */ -#define TIMER0_VA_BASE MM_IO_BASE_TMR -#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20) -#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40) -#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60) - -/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ -#if defined(CONFIG_ARCH_FPGA11107) -/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ -/* slow down Linux's sense of time */ -#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) -#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) -#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) -#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) -#else -#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ -#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ -#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ -#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) -#endif - -#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ - -/* - * These are useconds NOT ticks. - * - */ -#define mSEC_1 1000 -#define mSEC_5 (mSEC_1 * 5) -#define mSEC_10 (mSEC_1 * 10) -#define mSEC_25 (mSEC_1 * 25) -#define SEC_1 (mSEC_1 * 1000) - -/* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 8) -#define TIMER_DIVISOR (TIMER_CTRL_DIV256) -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ -#define TIMER_DIVISOR (TIMER_CTRL_DIV16) -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TIMER_RELOAD (TIMER_INTERVAL) -#define TIMER_DIVISOR (TIMER_CTRL_DIV1) -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - -static void timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - unsigned long ctrl; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); - - ctrl = TIMER_CTRL_PERIODIC; - ctrl |= - TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE | - TIMER_CTRL_ENABLE; - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl = TIMER_CTRL_ONESHOT; - ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } - - writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); -} - -static int timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); - - writel(evt, TIMER0_VA_BASE + TIMER_LOAD); - writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); - - return 0; -} - -static struct clock_event_device timer0_clockevent = { - .name = "timer0", - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = timer_set_mode, - .set_next_event = timer_set_next_event, -}; - -/* - * IRQ handler for the timer - */ -static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &timer0_clockevent; - - writel(1, TIMER0_VA_BASE + TIMER_INTCLR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction bcmring_timer_irq = { - .name = "bcmring Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = bcmring_timer_interrupt, -}; - -static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs) -{ - return ~readl(TIMER1_VA_BASE + TIMER_VALUE); -} - -static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs) -{ - return ~readl(TIMER3_VA_BASE + TIMER_VALUE); -} - -static struct clocksource clocksource_bcmring_timer1 = { - .name = "timer1", - .rating = 200, - .read = bcmring_get_cycles_timer1, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static struct clocksource clocksource_bcmring_timer3 = { - .name = "timer3", - .rating = 100, - .read = bcmring_get_cycles_timer3, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; +#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR) +#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20)) +#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40)) +#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60)) static int __init bcmring_clocksource_init(void) { /* setup timer1 as free-running clocksource */ - writel(0, TIMER1_VA_BASE + TIMER_CTRL); - writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD); - writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - TIMER1_VA_BASE + TIMER_CTRL); - - clocksource_register_khz(&clocksource_bcmring_timer1, - TIMER1_FREQUENCY_MHZ * 1000); + sp804_clocksource_init(TIMER1_VA_BASE, "timer1"); /* setup timer3 as free-running clocksource */ - writel(0, TIMER3_VA_BASE + TIMER_CTRL); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - TIMER3_VA_BASE + TIMER_CTRL); - - clocksource_register_khz(&clocksource_bcmring_timer3, - TIMER3_FREQUENCY_KHZ); + sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); return 0; } @@ -347,21 +233,16 @@ void __init bcmring_init_timer(void) /* * Make irqs happen for the system timer */ - setup_irq(IRQ_TIMER0, &bcmring_timer_irq); - bcmring_clocksource_init(); - timer0_clockevent.mult = - div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); - timer0_clockevent.max_delta_ns = - clockevent_delta2ns(0xffffffff, &timer0_clockevent); - timer0_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &timer0_clockevent); - - timer0_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&timer0_clockevent); + sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0"); } struct sys_timer bcmring_timer = { .init = bcmring_init_timer, }; + +void __init bcmring_init_early(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +} diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h index b197ba48e36..e0e02c48f9b 100644 --- a/arch/arm/mach-bcmring/core.h +++ b/arch/arm/mach-bcmring/core.h @@ -25,6 +25,7 @@ void __init bcmring_amba_init(void); void __init bcmring_map_io(void); void __init bcmring_init_irq(void); +void __init bcmring_init_early(void); extern struct sys_timer bcmring_timer; #endif diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index 77f84b40dda..a1f328357aa 100644 --- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -551,7 +551,7 @@ int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Config /****************************************************************************/ /** -* @brief Check the existance of pending descriptor +* @brief Check the existence of pending descriptor * * This function confirmes if there is any pending descriptor in the chain * to program the channel @@ -775,7 +775,7 @@ int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Cha /** * @brief Read data DMAed to memory * -* This function will read data that has been DMAed to memory while transfering from: +* This function will read data that has been DMAed to memory while transferring from: * - Memory to memory * - Peripheral to memory * @@ -941,7 +941,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configurat /** * @brief Sets channel specific user data * -* This function associates user data to a specif DMA channel +* This function associates user data to a specific DMA channel * */ /****************************************************************************/ diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c index 8d1baf3f468..d87ad30dda3 100644 --- a/arch/arm/mach-bcmring/dma.c +++ b/arch/arm/mach-bcmring/dma.c @@ -629,7 +629,7 @@ EXPORT_SYMBOL(dma_get_device_descriptor_ring); * Configures a DMA channel. * * @return -* >= 0 - Initialization was successfull. +* >= 0 - Initialization was successful. * * -EBUSY - Device is currently being used. * -ENODEV - Device handed in is invalid. @@ -673,7 +673,7 @@ static int ConfigChannel(DMA_Handle_t handle) /** * Initializes all of the data structures associated with the DMA. * @return -* >= 0 - Initialization was successfull. +* >= 0 - Initialization was successful. * * -EBUSY - Device is currently being used. * -ENODEV - Device handed in is invalid. diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h index 6c8da2b9fc1..e6a1dc484ca 100644 --- a/arch/arm/mach-bcmring/include/csp/dmacHw.h +++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h @@ -362,7 +362,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configurati /** * @brief Read data DMA transferred to memory * -* This function will read data that has been DMAed to memory while transfering from: +* This function will read data that has been DMAed to memory while transferring from: * - Memory to memory * - Peripheral to memory * @@ -446,7 +446,7 @@ void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle * /****************************************************************************/ /** -* @brief Check the existance of pending descriptor +* @brief Check the existence of pending descriptor * * This function confirmes if there is any pending descriptor in the chain * to program the channel @@ -542,7 +542,7 @@ dmacHw_HANDLE_t dmacHw_getInterruptSource(void); /** * @brief Sets channel specific user data * -* This function associates user data to a specif DMA channel +* This function associates user data to a specific DMA channel * */ /****************************************************************************/ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 70eaea866cf..161973385fa 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -180,7 +180,7 @@ typedef enum { #define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */ -/* Programable pin defines */ +/* Programmable pin defines */ #define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF) /* GPIO pin 0 - 60 */ #define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */ diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index c78833acb37..03238c29900 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -832,7 +832,7 @@ static inline void chipcHw_setUsbDevice(void) /****************************************************************************/ /** -* @brief Lower layer funtion to enable/disable a clock of a certain device +* @brief Lower layer function to enable/disable a clock of a certain device * * This function enables/disables a core clock * diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index e01fc4607c9..0aeb6a6fe7f 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -109,9 +109,9 @@ #define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM) /* INTC1 - interrupt controller 1 */ -#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */ +#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */ #define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */ -#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */ +#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */ #define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */ #define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */ /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */ diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h index 06a355481ea..0992842caa7 100644 --- a/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -88,7 +88,7 @@ /* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */ /* Enable wait pin during burst write or read */ #define REG_UMI_TCR_WAITEN 0x80000000 -/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */ +/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */ #define REG_UMI_TCR_LOWFREQ 0x40000000 /* 1=synch write, 0=async write */ #define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000 diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index 84dcda0d1d9..c48feaf4e8e 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c @@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip, unsigned int i; for (i = 0; i < 32; i++) { unsigned int irq = irq_start + i; - set_irq_chip(irq, chip); - set_irq_chip_data(irq, base); + irq_set_chip(irq, chip); + irq_set_chip_data(irq, base); if (vic_sources & (1 << i)) { - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } @@ -119,9 +119,9 @@ void __init bcmring_init_irq(void) /* special cases */ if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { - set_irq_handler(IRQ_GPIO0, handle_simple_irq); + irq_set_handler(IRQ_GPIO0, handle_simple_irq); } if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { - set_irq_handler(IRQ_GPIO1, handle_simple_irq); + irq_set_handler(IRQ_GPIO1, handle_simple_irq); } } diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c index 86da7a1b2bb..c2eceee645e 100644 --- a/arch/arm/mach-clps711x/irq.c +++ b/arch/arm/mach-clps711x/irq.c @@ -112,13 +112,13 @@ void __init clps711x_init_irq(void) for (i = 0; i < NR_IRQS; i++) { if (INT1_IRQS & (1 << i)) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &int1_chip); + irq_set_chip_and_handler(i, &int1_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } if (INT2_IRQS & (1 << i)) { - set_irq_handler(i, handle_level_irq); - set_irq_chip(i, &int2_chip); + irq_set_chip_and_handler(i, &int2_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 32f147998cd..c0deacae778 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -63,6 +63,7 @@ config MACH_DAVINCI_EVM depends on ARCH_DAVINCI_DM644x select MISC_DEVICES select EEPROM_AT24 + select I2C help Configure this option to specify the whether the board used for development is a DM644x EVM @@ -72,6 +73,7 @@ config MACH_SFFSDR depends on ARCH_DAVINCI_DM644x select MISC_DEVICES select EEPROM_AT24 + select I2C help Say Y here to select the Lyrtech Small Form Factor Software Defined Radio (SFFSDR) board. @@ -105,6 +107,7 @@ config MACH_DAVINCI_DM6467_EVM select MACH_DAVINCI_DM6467TEVM select MISC_DEVICES select EEPROM_AT24 + select I2C help Configure this option to specify the whether the board used for development is a DM6467 EVM @@ -118,6 +121,7 @@ config MACH_DAVINCI_DM365_EVM depends on ARCH_DAVINCI_DM365 select MISC_DEVICES select EEPROM_AT24 + select I2C help Configure this option to specify whether the board used for development is a DM365 EVM @@ -129,6 +133,7 @@ config MACH_DAVINCI_DA830_EVM select GPIO_PCF857X select MISC_DEVICES select EEPROM_AT24 + select I2C help Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. @@ -205,6 +210,7 @@ config MACH_MITYOMAPL138 depends on ARCH_DAVINCI_DA850 select MISC_DEVICES select EEPROM_AT24 + select I2C help Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 System on Module. Information on this SoM may be found at diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 2aa79c54f98..606a6f27ed6 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -29,7 +29,7 @@ #include <mach/mux.h> #include <mach/spi.h> -#define MITYOMAPL138_PHY_ID "0:03" +#define MITYOMAPL138_PHY_ID "" #define FACTORY_CONFIG_MAGIC 0x012C0138 #define FACTORY_CONFIG_VERSION 0x00010001 @@ -414,7 +414,7 @@ static struct resource mityomapl138_nandflash_resource[] = { static struct platform_device mityomapl138_nandflash_device = { .name = "davinci_nand", - .id = 0, + .id = 1, .dev = { .platform_data = &mityomapl138_nandflash_data, }, diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 6c389ff1020..3e7be2de96d 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -11,7 +11,7 @@ * DM644X-EVM board. It has: * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC, * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video. - * Additionaly realtime clock, IR remote control receiver, + * Additionally realtime clock, IR remote control receiver, * IR Blaster based on MSP430 (firmware although is different * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive * with PATA interface, two muxed red-green leds. diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 9abc80a86a2..f83152d643c 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -167,9 +167,9 @@ void __init cp_intc_init(void) /* Set up genirq dispatching for cp_intc */ for (i = 0; i < num_irq; i++) { - set_irq_chip(i, &cp_intc_irq_chip); + irq_set_chip(i, &cp_intc_irq_chip); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); } /* Enable global interrupt */ diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index 4a68c2b1ec1..41669ecc1f9 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -94,9 +94,7 @@ static int davinci_target(struct cpufreq_policy *policy, if (freqs.old == freqs.new) return ret; - cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, - dev_driver_string(cpufreq.dev), - "transition: %u --> %u\n", freqs.old, freqs.new); + dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new); ret = cpufreq_frequency_table_target(policy, pdata->freq_table, freqs.new, relation, &idx); @@ -167,7 +165,7 @@ static int davinci_cpu_init(struct cpufreq_policy *policy) /* * Time measurement across the target() function yields ~1500-1800us * time taken with no drivers on notification list. - * Setting the latency to 2000 us to accomodate addition of drivers + * Setting the latency to 2000 us to accommodate addition of drivers * to pre/post change notification list. */ policy->cpuinfo.transition_latency = 2000 * 1000; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 68fe4c289d7..b95b9196dee 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1123,7 +1123,7 @@ void __init da850_init(void) * This helps keeping the peripherals on this domain insulated * from CPU frequency changes caused by DVFS. The firmware sets * both PLL0 and PLL1 to the same frequency so, there should not - * be any noticible change even in non-DVFS use cases. + * be any noticeable change even in non-DVFS use cases. */ da850_set_async3_src(1); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 625d4b66718..58a02dc7b15 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -39,7 +39,8 @@ #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_I2C1_BASE 0x01e28000 #define DA8XX_SPI0_BASE 0x01c41000 -#define DA8XX_SPI1_BASE 0x01f0e000 +#define DA830_SPI1_BASE 0x01e12000 +#define DA850_SPI1_BASE 0x01f0e000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 @@ -762,8 +763,8 @@ static struct resource da8xx_spi0_resources[] = { static struct resource da8xx_spi1_resources[] = { [0] = { - .start = DA8XX_SPI1_BASE, - .end = DA8XX_SPI1_BASE + SZ_4K - 1, + .start = DA830_SPI1_BASE, + .end = DA830_SPI1_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -832,5 +833,10 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info, da8xx_spi_pdata[instance].num_chipselect = len; + if (instance == 1 && cpu_is_davinci_da850()) { + da8xx_spi1_resources[0].start = DA850_SPI1_BASE; + da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; + } + return platform_device_register(&da8xx_spi_device[instance]); } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 76364d1345d..a3a94e9c937 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -314,7 +314,7 @@ static struct clk timer2_clk = { .name = "timer2", .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ + .usecount = 1, /* REVISIT: why can't this be disabled? */ }; static struct clk timer3_clk = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 9a2376b3137..4c82c271629 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -274,7 +274,7 @@ static struct clk timer2_clk = { .name = "timer2", .parent = &pll1_aux_clk, .lpsc = DAVINCI_LPSC_TIMER2, - .usecount = 1, /* REVISIT: why cant' this be disabled? */ + .usecount = 1, /* REVISIT: why can't this be disabled? */ }; static struct clk_lookup dm644x_clks[] = { diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 20d66e5e466..a0b838894ac 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) { struct davinci_gpio_regs __iomem *g; - g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); + g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); return g; } @@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(struct irq_data *d) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); __raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_rising); @@ -217,8 +217,8 @@ static void gpio_irq_disable(struct irq_data *d) static void gpio_irq_enable(struct irq_data *d) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); - unsigned status = irq_desc[d->irq].status; + u32 mask = (u32) irq_data_get_irq_handler_data(d); + unsigned status = irqd_get_trigger_type(d); status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (!status) @@ -233,21 +233,11 @@ static void gpio_irq_enable(struct irq_data *d) static int gpio_irq_type(struct irq_data *d, unsigned trigger) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; - irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK; - irq_desc[d->irq].status |= trigger; - - /* don't enable the IRQ if it's currently disabled */ - if (irq_desc[d->irq].depth == 0) { - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) - ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) - ? &g->set_rising : &g->clr_rising); - } return 0; } @@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = { .irq_enable = gpio_irq_enable, .irq_disable = gpio_irq_disable, .irq_set_type = gpio_irq_type, + .flags = IRQCHIP_SET_TYPE_MASKED, }; static void @@ -285,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) status >>= 16; /* now demux them to the right lowlevel handler */ - n = (int)get_irq_data(irq); + n = (int)irq_get_handler_data(irq); while (status) { res = ffs(status); n += res; @@ -323,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) { struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); - u32 mask = (u32) irq_data_get_irq_data(d); + u32 mask = (u32) irq_data_get_irq_handler_data(d); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; @@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void) /* AINTC handles mask/unmask; GPIO handles triggering */ irq = bank_irq; - gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); + gpio_irqchip_unbanked = *irq_get_chip(irq); gpio_irqchip_unbanked.name = "GPIO-AINTC"; gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; @@ -406,10 +397,10 @@ static int __init davinci_gpio_irq_setup(void) /* set the direct IRQs up to use that irqchip */ for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { - set_irq_chip(irq, &gpio_irqchip_unbanked); - set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_chip_data(irq, (__force void *) g); - irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; + irq_set_chip(irq, &gpio_irqchip_unbanked); + irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); + irq_set_chip_data(irq, (__force void *)g); + irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); } goto done; @@ -430,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void) __raw_writel(~0, &g->clr_rising); /* set up all irqs in this bank */ - set_irq_chained_handler(bank_irq, gpio_irq_handler); - set_irq_chip_data(bank_irq, (__force void *) g); - set_irq_data(bank_irq, (void *) irq); + irq_set_chained_handler(bank_irq, gpio_irq_handler); + irq_set_chip_data(bank_irq, (__force void *)g); + irq_set_handler_data(bank_irq, (void *)irq); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { - set_irq_chip(irq, &gpio_irqchip); - set_irq_chip_data(irq, (__force void *) g); - set_irq_data(irq, (void *) __gpio_mask(gpio)); - set_irq_handler(irq, handle_simple_irq); + irq_set_chip(irq, &gpio_irqchip); + irq_set_chip_data(irq, (__force void *)g); + irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); + irq_set_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index cea6b897204..957fb87e832 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -4,7 +4,7 @@ * Author: Kevin Hilman, Deep Root Systems, LLC * * Defines the cpu_is_*() macros for runtime detection of DaVinci - * device type. In addtion, if support for a given device is not + * device type. In addition, if support for a given device is not * compiled in to the kernel, the macros return 0 so that * resulting code can be optimized out. * diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 9f1befc5ac3..f8b7ea4f623 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -24,6 +24,9 @@ #define UART_SHIFT 2 +#define davinci_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET) +#define davinci_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET) + .pushsection .data davinci_uart_phys: .word 0 davinci_uart_virt: .word 0 @@ -34,7 +37,7 @@ davinci_uart_virt: .word 0 /* Use davinci_uart_phys/virt if already configured */ 10: mrc p15, 0, \rp, c1, c0 tst \rp, #1 @ MMU enabled? - ldreq \rp, =__virt_to_phys(davinci_uart_phys) + ldreq \rp, =davinci_uart_v2p(davinci_uart_phys) ldrne \rp, =davinci_uart_phys add \rv, \rp, #4 @ davinci_uart_virt ldr \rp, [\rp, #0] @@ -48,18 +51,18 @@ davinci_uart_virt: .word 0 tst \rp, #1 @ MMU enabled? /* Copy uart phys address from decompressor uart info */ - ldreq \rv, =__virt_to_phys(davinci_uart_phys) + ldreq \rv, =davinci_uart_v2p(davinci_uart_phys) ldrne \rv, =davinci_uart_phys ldreq \rp, =DAVINCI_UART_INFO - ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO) + ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO) ldr \rp, [\rp, #0] str \rp, [\rv] /* Copy uart virt address from decompressor uart info */ - ldreq \rv, =__virt_to_phys(davinci_uart_virt) + ldreq \rv, =davinci_uart_v2p(davinci_uart_virt) ldrne \rv, =davinci_uart_virt ldreq \rp, =DAVINCI_UART_INFO - ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO) + ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO) ldr \rp, [\rp, #4] str \rp, [\rv] diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 78822723f38..491249ef209 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -41,27 +41,11 @@ */ #define CONSISTENT_DMA_SIZE (14<<20) -#ifndef __ASSEMBLY__ /* * Restrict DMA-able region to workaround silicon bug. The bug * restricts buffers available for DMA to video hardware to be * below 128M */ -static inline void -__arch_adjust_zones(unsigned long *size, unsigned long *holes) -{ - unsigned int sz = (128<<20) >> PAGE_SHIFT; - - size[1] = size[0] - sz; - size[0] = sz; -} - -#define arch_adjust_zones(zone_size, holes) \ - if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) - -#endif +#define ARM_DMA_ZONE_SIZE SZ_128M #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 8051110b8ac..c9e6ce185a6 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -22,7 +22,7 @@ * * This area sits just below the page tables (see arch/arm/kernel/head.S). */ -#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8) +#define DAVINCI_UART_INFO (PLAT_PHYS_OFFSET + 0x3ff8) #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 47723e8d75a..78d80683cdc 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -25,8 +25,7 @@ #include <mach/serial.h> -static u32 *uart; -static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); +u32 *uart; /* PORT_16C550A, in polled non-fifo mode */ static void putc(char c) @@ -44,6 +43,8 @@ static inline void flush(void) static inline void set_uart_info(u32 phys, void * __iomem virt) { + u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); + uart = (u32 *)phys; uart_info[0] = phys; uart_info[1] = (u32)virt; diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 5e05c9b64e1..bfe68ec4e1a 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -29,8 +29,6 @@ #include <mach/common.h> #include <asm/mach/irq.h> -#define IRQ_BIT(irq) ((irq) & 0x1f) - #define FIQ_REG0_OFFSET 0x0000 #define FIQ_REG1_OFFSET 0x0004 #define IRQ_REG0_OFFSET 0x0008 @@ -42,78 +40,33 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C -static inline unsigned int davinci_irq_readl(int offset) -{ - return __raw_readl(davinci_intc_base + offset); -} - static inline void davinci_irq_writel(unsigned long value, int offset) { __raw_writel(value, davinci_intc_base + offset); } -/* Disable interrupt */ -static void davinci_mask_irq(struct irq_data *d) +static __init void +davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) { - unsigned int mask; - u32 l; - - mask = 1 << IRQ_BIT(d->irq); - - if (d->irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } -} - -/* Enable interrupt */ -static void davinci_unmask_irq(struct irq_data *d) -{ - unsigned int mask; - u32 l; - - mask = 1 << IRQ_BIT(d->irq); - - if (d->irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + + ct->regs.ack = IRQ_REG0_OFFSET; + ct->regs.mask = IRQ_ENT_REG0_OFFSET; + irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); } -/* EOI interrupt */ -static void davinci_ack_irq(struct irq_data *d) -{ - unsigned int mask; - - mask = 1 << IRQ_BIT(d->irq); - - if (d->irq > 31) - davinci_irq_writel(mask, IRQ_REG1_OFFSET); - else - davinci_irq_writel(mask, IRQ_REG0_OFFSET); -} - -static struct irq_chip davinci_irq_chip_0 = { - .name = "AINTC", - .irq_ack = davinci_ack_irq, - .irq_mask = davinci_mask_irq, - .irq_unmask = davinci_unmask_irq, -}; - /* ARM Interrupt Controller Initialization */ void __init davinci_irq_init(void) { - unsigned i; + unsigned i, j; const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; davinci_intc_type = DAVINCI_INTC_TYPE_AINTC; @@ -144,7 +97,6 @@ void __init davinci_irq_init(void) davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { - unsigned j; u32 pri; for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) @@ -152,13 +104,8 @@ void __init davinci_irq_init(void) davinci_irq_writel(pri, i); } - /* set up genirq dispatch for ARM INTC */ - for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { - set_irq_chip(i, &davinci_irq_chip_0); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - if (i != IRQ_TINT1_TINT34) - set_irq_handler(i, handle_edge_irq); - else - set_irq_handler(i, handle_level_irq); - } + for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04) + davinci_alloc_gc(davinci_intc_base + j, i, 32); + + irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index e06a88f1f81..5ed51b84c1b 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -16,10 +16,8 @@ #include <linux/serial_8250.h> #include <linux/clk.h> #include <linux/mbus.h> -#include <linux/mv643xx_eth.h> -#include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> -#include <linux/spi/orion_spi.h> +#include <linux/serial_8250.h> #include <linux/gpio.h> #include <asm/page.h> #include <asm/setup.h> @@ -32,11 +30,12 @@ #include <mach/bridge-regs.h> #include <asm/mach/arch.h> #include <linux/irq.h> -#include <plat/mv_xor.h> -#include <plat/ehci-orion.h> #include <plat/time.h> +#include <plat/common.h> #include "common.h" +static int get_tclk(void); + /***************************************************************************** * I/O Address Mapping ****************************************************************************/ @@ -70,463 +69,106 @@ void __init dove_map_io(void) } /***************************************************************************** - * EHCI - ****************************************************************************/ -static struct orion_ehci_data dove_ehci_data = { - .dram = &dove_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - -/***************************************************************************** * EHCI0 ****************************************************************************/ -static struct resource dove_ehci0_resources[] = { - { - .start = DOVE_USB0_PHYS_BASE, - .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_USB0, - .end = IRQ_DOVE_USB0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dove_ehci_data, - }, - .resource = dove_ehci0_resources, - .num_resources = ARRAY_SIZE(dove_ehci0_resources), -}; - void __init dove_ehci0_init(void) { - platform_device_register(&dove_ehci0); + orion_ehci_init(&dove_mbus_dram_info, + DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource dove_ehci1_resources[] = { - { - .start = DOVE_USB1_PHYS_BASE, - .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_USB1, - .end = IRQ_DOVE_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dove_ehci_data, - }, - .resource = dove_ehci1_resources, - .num_resources = ARRAY_SIZE(dove_ehci1_resources), -}; - void __init dove_ehci1_init(void) { - platform_device_register(&dove_ehci1); + orion_ehci_1_init(&dove_mbus_dram_info, + DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); } /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = { - .t_clk = 0, - .dram = &dove_mbus_dram_info, -}; - -static struct resource dove_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = DOVE_GE00_PHYS_BASE + 0x2000, - .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dove_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &dove_ge00_shared_data, - }, - .num_resources = 1, - .resource = dove_ge00_shared_resources, -}; - -static struct resource dove_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_DOVE_GE00_SUM, - .end = IRQ_DOVE_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = dove_ge00_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &dove_ge00_shared; - dove_ge00.dev.platform_data = eth_data; - - platform_device_register(&dove_ge00_shared); - platform_device_register(&dove_ge00); + orion_ge00_init(eth_data, &dove_mbus_dram_info, + DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, + 0, get_tclk()); } /***************************************************************************** * SoC RTC ****************************************************************************/ -static struct resource dove_rtc_resource[] = { - { - .start = DOVE_RTC_PHYS_BASE, - .end = DOVE_RTC_PHYS_BASE + 32 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_RTC, - .flags = IORESOURCE_IRQ, - } -}; - void __init dove_rtc_init(void) { - platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); + orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); } /***************************************************************************** * SATA ****************************************************************************/ -static struct resource dove_sata_resources[] = { - { - .name = "sata base", - .start = DOVE_SATA_PHYS_BASE, - .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_DOVE_SATA, - .end = IRQ_DOVE_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(dove_sata_resources), - .resource = dove_sata_resources, -}; - void __init dove_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &dove_mbus_dram_info; - dove_sata.dev.platform_data = sata_data; - platform_device_register(&dove_sata); + orion_sata_init(sata_data, &dove_mbus_dram_info, + DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); + } /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port dove_uart0_data[] = { - { - .mapbase = DOVE_UART0_PHYS_BASE, - .membase = (char *)DOVE_UART0_VIRT_BASE, - .irq = IRQ_DOVE_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart0_resources[] = { - { - .start = DOVE_UART0_PHYS_BASE, - .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_0, - .end = IRQ_DOVE_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart0 = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = dove_uart0_data, - }, - .resource = dove_uart0_resources, - .num_resources = ARRAY_SIZE(dove_uart0_resources), -}; - void __init dove_uart0_init(void) { - platform_device_register(&dove_uart0); + orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, + IRQ_DOVE_UART_0, get_tclk()); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port dove_uart1_data[] = { - { - .mapbase = DOVE_UART1_PHYS_BASE, - .membase = (char *)DOVE_UART1_VIRT_BASE, - .irq = IRQ_DOVE_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart1_resources[] = { - { - .start = DOVE_UART1_PHYS_BASE, - .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_1, - .end = IRQ_DOVE_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart1 = { - .name = "serial8250", - .id = 1, - .dev = { - .platform_data = dove_uart1_data, - }, - .resource = dove_uart1_resources, - .num_resources = ARRAY_SIZE(dove_uart1_resources), -}; - void __init dove_uart1_init(void) { - platform_device_register(&dove_uart1); + orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, + IRQ_DOVE_UART_1, get_tclk()); } /***************************************************************************** * UART2 ****************************************************************************/ -static struct plat_serial8250_port dove_uart2_data[] = { - { - .mapbase = DOVE_UART2_PHYS_BASE, - .membase = (char *)DOVE_UART2_VIRT_BASE, - .irq = IRQ_DOVE_UART_2, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart2_resources[] = { - { - .start = DOVE_UART2_PHYS_BASE, - .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_2, - .end = IRQ_DOVE_UART_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart2 = { - .name = "serial8250", - .id = 2, - .dev = { - .platform_data = dove_uart2_data, - }, - .resource = dove_uart2_resources, - .num_resources = ARRAY_SIZE(dove_uart2_resources), -}; - void __init dove_uart2_init(void) { - platform_device_register(&dove_uart2); + orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, + IRQ_DOVE_UART_2, get_tclk()); } /***************************************************************************** * UART3 ****************************************************************************/ -static struct plat_serial8250_port dove_uart3_data[] = { - { - .mapbase = DOVE_UART3_PHYS_BASE, - .membase = (char *)DOVE_UART3_VIRT_BASE, - .irq = IRQ_DOVE_UART_3, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource dove_uart3_resources[] = { - { - .start = DOVE_UART3_PHYS_BASE, - .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_UART_3, - .end = IRQ_DOVE_UART_3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_uart3 = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = dove_uart3_data, - }, - .resource = dove_uart3_resources, - .num_resources = ARRAY_SIZE(dove_uart3_resources), -}; - void __init dove_uart3_init(void) { - platform_device_register(&dove_uart3); + orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, + IRQ_DOVE_UART_3, get_tclk()); } /***************************************************************************** - * SPI0 + * SPI ****************************************************************************/ -static struct orion_spi_info dove_spi0_data = { - .tclk = 0, -}; - -static struct resource dove_spi0_resources[] = { - { - .start = DOVE_SPI0_PHYS_BASE, - .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SPI0, - .end = IRQ_DOVE_SPI0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_spi0 = { - .name = "orion_spi", - .id = 0, - .resource = dove_spi0_resources, - .dev = { - .platform_data = &dove_spi0_data, - }, - .num_resources = ARRAY_SIZE(dove_spi0_resources), -}; - void __init dove_spi0_init(void) { - platform_device_register(&dove_spi0); + orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk()); } -/***************************************************************************** - * SPI1 - ****************************************************************************/ -static struct orion_spi_info dove_spi1_data = { - .tclk = 0, -}; - -static struct resource dove_spi1_resources[] = { - { - .start = DOVE_SPI1_PHYS_BASE, - .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SPI1, - .end = IRQ_DOVE_SPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_spi1 = { - .name = "orion_spi", - .id = 1, - .resource = dove_spi1_resources, - .dev = { - .platform_data = &dove_spi1_data, - }, - .num_resources = ARRAY_SIZE(dove_spi1_resources), -}; - void __init dove_spi1_init(void) { - platform_device_register(&dove_spi1); + orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk()); } /***************************************************************************** * I2C ****************************************************************************/ -static struct mv64xxx_i2c_pdata dove_i2c_data = { - .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource dove_i2c_resources[] = { - { - .name = "i2c base", - .start = DOVE_I2C_PHYS_BASE, - .end = DOVE_I2C_PHYS_BASE + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "i2c irq", - .start = IRQ_DOVE_I2C, - .end = IRQ_DOVE_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(dove_i2c_resources), - .resource = dove_i2c_resources, - .dev = { - .platform_data = &dove_i2c_data, - }, -}; - void __init dove_i2c_init(void) { - platform_device_register(&dove_i2c); + orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); } /***************************************************************************** @@ -554,208 +196,22 @@ struct sys_timer dove_timer = { }; /***************************************************************************** - * XOR - ****************************************************************************/ -static struct mv_xor_platform_shared_data dove_xor_shared_data = { - .dram = &dove_mbus_dram_info, -}; - -/***************************************************************************** * XOR 0 ****************************************************************************/ -static u64 dove_xor0_dmamask = DMA_BIT_MASK(32); - -static struct resource dove_xor0_shared_resources[] = { - { - .name = "xor 0 low", - .start = DOVE_XOR0_PHYS_BASE, - .end = DOVE_XOR0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 0 high", - .start = DOVE_XOR0_HIGH_PHYS_BASE, - .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dove_xor0_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &dove_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(dove_xor0_shared_resources), - .resource = dove_xor0_shared_resources, -}; - -static struct resource dove_xor00_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_00, - .end = IRQ_DOVE_XOR_00, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor00_data = { - .shared = &dove_xor0_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor00_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(dove_xor00_resources), - .resource = dove_xor00_resources, - .dev = { - .dma_mask = &dove_xor0_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor00_data, - }, -}; - -static struct resource dove_xor01_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_01, - .end = IRQ_DOVE_XOR_01, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor01_data = { - .shared = &dove_xor0_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor01_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(dove_xor01_resources), - .resource = dove_xor01_resources, - .dev = { - .dma_mask = &dove_xor0_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor01_data, - }, -}; - void __init dove_xor0_init(void) { - platform_device_register(&dove_xor0_shared); - - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask); - platform_device_register(&dove_xor00_channel); - - dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask); - dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask); - platform_device_register(&dove_xor01_channel); + orion_xor0_init(&dove_mbus_dram_info, + DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, + IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); } /***************************************************************************** * XOR 1 ****************************************************************************/ -static u64 dove_xor1_dmamask = DMA_BIT_MASK(32); - -static struct resource dove_xor1_shared_resources[] = { - { - .name = "xor 0 low", - .start = DOVE_XOR1_PHYS_BASE, - .end = DOVE_XOR1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 0 high", - .start = DOVE_XOR1_HIGH_PHYS_BASE, - .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device dove_xor1_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &dove_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(dove_xor1_shared_resources), - .resource = dove_xor1_shared_resources, -}; - -static struct resource dove_xor10_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_10, - .end = IRQ_DOVE_XOR_10, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor10_data = { - .shared = &dove_xor1_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor10_channel = { - .name = MV_XOR_NAME, - .id = 2, - .num_resources = ARRAY_SIZE(dove_xor10_resources), - .resource = dove_xor10_resources, - .dev = { - .dma_mask = &dove_xor1_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor10_data, - }, -}; - -static struct resource dove_xor11_resources[] = { - [0] = { - .start = IRQ_DOVE_XOR_11, - .end = IRQ_DOVE_XOR_11, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data dove_xor11_data = { - .shared = &dove_xor1_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device dove_xor11_channel = { - .name = MV_XOR_NAME, - .id = 3, - .num_resources = ARRAY_SIZE(dove_xor11_resources), - .resource = dove_xor11_resources, - .dev = { - .dma_mask = &dove_xor1_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &dove_xor11_data, - }, -}; - void __init dove_xor1_init(void) { - platform_device_register(&dove_xor1_shared); - - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask); - platform_device_register(&dove_xor10_channel); - - dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask); - dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask); - dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask); - platform_device_register(&dove_xor11_channel); + orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, + IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); } /***************************************************************************** @@ -833,14 +289,6 @@ void __init dove_init(void) #endif dove_setup_cpu_mbus(); - dove_ge00_shared_data.t_clk = tclk; - dove_uart0_data[0].uartclk = tclk; - dove_uart1_data[0].uartclk = tclk; - dove_uart2_data[0].uartclk = tclk; - dove_uart3_data[0].uartclk = tclk; - dove_spi0_data.tclk = tclk; - dove_spi1_data.tclk = tclk; - /* internal devices that every board has */ dove_rtc_init(); dove_xor0_init(); diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index e5fcdd3f5bf..b20ec9af788 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -136,7 +136,7 @@ #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) #define DOVE_NAND_GPIO_EN (1 << 0) -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) +#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) #define DOVE_SPI_GPIO_SEL (1 << 5) #define DOVE_UART1_GPIO_SEL (1 << 4) #define DOVE_AU1_GPIO_SEL (1 << 3) diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 101707fa2e2..f07fd16e0c9 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -86,8 +86,7 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) if (!(cause & (1 << irq))) continue; irq = pmu_to_irq(irq); - desc = irq_desc + irq; - desc_handle_irq(irq, desc); + generic_handle_irq(irq); } } @@ -103,14 +102,14 @@ void __init dove_init_irq(void) */ orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START); - set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32); - set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); + irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64); @@ -122,10 +121,9 @@ void __init dove_init_irq(void) writel(0, PMU_INTERRUPT_CAUSE); for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { - set_irq_chip(i, &pmu_irq_chip); - set_irq_handler(i, handle_level_irq); - irq_desc[i].status |= IRQ_LEVEL; + irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); + irq_set_status_flags(i, IRQ_LEVEL); set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); + irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); } diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 71db2bdf2f2..51e0e411c9c 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -11,24 +11,17 @@ #include <linux/kernel.h> #include <linux/gpio.h> #include <linux/io.h> - +#include <plat/mpp.h> #include <mach/dove.h> - #include "mpp.h" -#define MPP_NR_REGS 4 -#define MPP_CTRL(i) ((i) == 3 ? \ - DOVE_MPP_CTRL4_VIRT_BASE : \ - DOVE_MPP_VIRT_BASE + (i) * 4) -#define PMU_SIG_REGS 2 -#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4) - struct dove_mpp_grp { int start; int end; }; -static struct dove_mpp_grp dove_mpp_grp[] = { +/* Map a group to a range of GPIO pins in that group */ +static const struct dove_mpp_grp dove_mpp_grp[] = { [MPP_24_39] = { .start = 24, .end = 39, @@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = { .end = 45, }, [MPP_46_51] = { - .start = 40, - .end = 45, + .start = 46, + .end = 51, }, [MPP_58_61] = { .start = 58, @@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = { }, }; +/* Enable gpio for a range of pins. mode should be a combination of + GPIO_OUTPUT_OK | GPIO_INPUT_OK */ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) { int i; @@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) orion_gpio_set_valid(i, gpio_mode); } +/* Dump all the extra MPP registers. The platform code will dump the + registers for pins 0-23. */ static void dove_mpp_dump_regs(void) { -#ifdef DEBUG - int i; - - pr_debug("MPP_CTRL regs:"); - for (i = 0; i < MPP_NR_REGS; i++) - printk(" %08x", readl(MPP_CTRL(i))); - printk("\n"); + pr_debug("PMU_CTRL4_CTRL: %08x\n", + readl(DOVE_MPP_CTRL4_VIRT_BASE)); - pr_debug("PMU_SIG_CTRL regs:"); - for (i = 0; i < PMU_SIG_REGS; i++) - printk(" %08x", readl(PMU_SIG_CTRL(i))); - printk("\n"); + pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", + readl(DOVE_PMU_MPP_GENERAL_CTRL)); - pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL)); pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); -#endif } static void dove_mpp_cfg_nfc(int sel) @@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel) static void dove_mpp_cfg_au1(int sel) { - u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); @@ -128,85 +116,46 @@ static void dove_mpp_cfg_au1(int sel) writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); } -static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) +/* Configure the group registers, enabling GPIO if sel indicates the + pin is to be used for GPIO */ +static void dove_mpp_conf_grp(unsigned int *mpp_grp_list) { - int start = dove_mpp_grp[num].start; - int end = dove_mpp_grp[num].end; - int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + int gpio_mode; - *mpp_ctrl &= ~(0x1 << num); - *mpp_ctrl |= sel << num; - - dove_mpp_gpio_mode(start, end, gpio_mode); -} + for ( ; *mpp_grp_list; mpp_grp_list++) { + unsigned int num = MPP_NUM(*mpp_grp_list); + unsigned int sel = MPP_SEL(*mpp_grp_list); -void __init dove_mpp_conf(unsigned int *mpp_list) -{ - u32 mpp_ctrl[MPP_NR_REGS]; - u32 pmu_mpp_ctrl = 0; - u32 pmu_sig_ctrl[PMU_SIG_REGS]; - int i; - - /* Initialize gpiolib. */ - orion_gpio_init(); - - for (i = 0; i < MPP_NR_REGS; i++) - mpp_ctrl[i] = readl(MPP_CTRL(i)); - - for (i = 0; i < PMU_SIG_REGS; i++) - pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i)); - - pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL); - - dove_mpp_dump_regs(); - - for ( ; *mpp_list != MPP_END; mpp_list++) { - unsigned int num = MPP_NUM(*mpp_list); - unsigned int sel = MPP_SEL(*mpp_list); - int shift, gpio_mode; - - if (num > MPP_MAX) { - pr_err("dove: invalid MPP number (%u)\n", num); - continue; - } - - if (*mpp_list & MPP_NFC_MASK) { - dove_mpp_cfg_nfc(sel); - continue; - } - - if (*mpp_list & MPP_AU1_MASK) { - dove_mpp_cfg_au1(sel); + if (num > MPP_GRP_MAX) { + pr_err("dove: invalid MPP GRP number (%u)\n", num); continue; } - if (*mpp_list & MPP_GRP_MASK) { - dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); - continue; - } - - shift = (num & 7) << 2; - if (*mpp_list & MPP_PMU_MASK) { - pmu_mpp_ctrl |= (0x1 << num); - pmu_sig_ctrl[num / 8] &= ~(0xf << shift); - pmu_sig_ctrl[num / 8] |= 0xf << shift; - gpio_mode = 0; - } else { - mpp_ctrl[num / 8] &= ~(0xf << shift); - mpp_ctrl[num / 8] |= sel << shift; - gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK; - } + mpp_ctrl4 &= ~(0x1 << num); + mpp_ctrl4 |= sel << num; - orion_gpio_set_valid(num, gpio_mode); + gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; + dove_mpp_gpio_mode(dove_mpp_grp[num].start, + dove_mpp_grp[num].end, gpio_mode); } + writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); +} - for (i = 0; i < MPP_NR_REGS; i++) - writel(mpp_ctrl[i], MPP_CTRL(i)); +/* Configure the various MPP pins on Dove */ +void __init dove_mpp_conf(unsigned int *mpp_list, + unsigned int *mpp_grp_list, + unsigned int grp_au1_52_57, + unsigned int grp_nfc_64_71) +{ + dove_mpp_dump_regs(); - for (i = 0; i < PMU_SIG_REGS; i++) - writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); + /* Use platform code for pins 0-23 */ + orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); - writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); + dove_mpp_conf_grp(mpp_grp_list); + dove_mpp_cfg_au1(grp_au1_52_57); + dove_mpp_cfg_nfc(grp_nfc_64_71); dove_mpp_dump_regs(); } diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h index 2a43ce413b1..fbec7c52bfa 100644 --- a/arch/arm/mach-dove/mpp.h +++ b/arch/arm/mach-dove/mpp.h @@ -1,178 +1,150 @@ #ifndef __ARCH_DOVE_MPP_CODED_H #define __ARCH_DOVE_MPP_CODED_H -#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ -/* MPP/group number */ ((_num) & 0xff) | \ -/* MPP select value */ (((_mode) & 0xf) << 8) | \ -/* MPP PMU */ ((!!(_pmu)) << 12) | \ -/* group flag */ ((!!(_grp)) << 13) | \ -/* AU1 flag */ ((!!(_au1)) << 14) | \ -/* NFCE flag */ ((!!(_nfc)) << 15)) - -#define MPP_MAX 71 - -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - -#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) -#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) -#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) -#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) - -#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) - -#define MPP_PMU_DRIVE_0 0x1 -#define MPP_PMU_DRIVE_1 0x2 -#define MPP_PMU_SDI 0x3 -#define MPP_PMU_CPU_PWRDWN 0x4 -#define MPP_PMU_STBY_PWRDWN 0x5 -#define MPP_PMU_CORE_PWR_GOOD 0x8 -#define MPP_PMU_BAT_FAULT 0xa -#define MPP_PMU_EXT0_WU 0xb -#define MPP_PMU_EXT1_WU 0xc -#define MPP_PMU_EXT2_WU 0xd -#define MPP_PMU_BLINK 0xe -#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) - -#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) -#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) -#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) -#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) - -#define MPP0_GPIO0 MPP_PIN(0, 0x0) -#define MPP0_UA2_RTSn MPP_PIN(0, 0x2) -#define MPP0_SDIO0_CD MPP_PIN(0, 0x3) -#define MPP0_LCD0_PWM MPP_PIN(0, 0xf) - -#define MPP1_GPIO1 MPP_PIN(1, 0x0) -#define MPP1_UA2_CTSn MPP_PIN(1, 0x2) -#define MPP1_SDIO0_WP MPP_PIN(1, 0x3) -#define MPP1_LCD1_PWM MPP_PIN(1, 0xf) - -#define MPP2_GPIO2 MPP_PIN(2, 0x0) -#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) -#define MPP2_UA2_TXD MPP_PIN(2, 0x2) -#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) -#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) - -#define MPP3_GPIO3 MPP_PIN(3, 0x0) -#define MPP3_SATA_ACT MPP_PIN(3, 0x1) -#define MPP3_UA2_RXD MPP_PIN(3, 0x2) -#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) -#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) -#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) - -#define MPP4_GPIO4 MPP_PIN(4, 0x0) -#define MPP4_UA3_RTSn MPP_PIN(4, 0x2) -#define MPP4_SDIO1_CD MPP_PIN(4, 0x3) -#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) - -#define MPP5_GPIO5 MPP_PIN(5, 0x0) -#define MPP5_UA3_CTSn MPP_PIN(5, 0x2) -#define MPP5_SDIO1_WP MPP_PIN(5, 0x3) -#define MPP5_SPI_1_CS MPP_PIN(5, 0x4) - -#define MPP6_GPIO6 MPP_PIN(6, 0x0) -#define MPP6_UA3_TXD MPP_PIN(6, 0x2) -#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) -#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) - -#define MPP7_GPIO7 MPP_PIN(7, 0x0) -#define MPP7_UA3_RXD MPP_PIN(7, 0x2) -#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) -#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) - -#define MPP8_GPIO8 MPP_PIN(8, 0x0) -#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) - -#define MPP9_GPIO9 MPP_PIN(9, 0x0) -#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) - -#define MPP10_GPIO10 MPP_PIN(10, 0x0) -#define MPP10_SSP_SCLK MPP_PIN(10, 0x5) - -#define MPP11_GPIO11 MPP_PIN(11, 0x0) -#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) -#define MPP11_SATA_ACT MPP_PIN(11, 0x2) -#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) -#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) -#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) - -#define MPP12_GPIO12 MPP_PIN(12, 0x0) -#define MPP12_SATA_ACT MPP_PIN(12, 0x1) -#define MPP12_UA2_RTSn MPP_PIN(12, 0x2) -#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) -#define MPP12_SDIO1_CD MPP_PIN(12, 0x4) - -#define MPP13_GPIO13 MPP_PIN(13, 0x0) -#define MPP13_UA2_CTSn MPP_PIN(13, 0x2) -#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) -#define MPP13_SDIO1WP MPP_PIN(13, 0x4) -#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) - -#define MPP14_GPIO14 MPP_PIN(14, 0x0) -#define MPP14_UA2_TXD MPP_PIN(14, 0x2) -#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) -#define MPP14_SSP_RXD MPP_PIN(14, 0x5) - -#define MPP15_GPIO15 MPP_PIN(15, 0x0) -#define MPP15_UA2_RXD MPP_PIN(15, 0x2) -#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) -#define MPP15_SSP_SFRM MPP_PIN(15, 0x5) - -#define MPP16_GPIO16 MPP_PIN(16, 0x0) -#define MPP16_UA3_RTSn MPP_PIN(16, 0x2) -#define MPP16_SDIO0_CD MPP_PIN(16, 0x3) -#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) -#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) - -#define MPP17_GPIO17 MPP_PIN(17, 0x0) -#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) -#define MPP17_UA3_CTSn MPP_PIN(17, 0x2) -#define MPP17_SDIO0_WP MPP_PIN(17, 0x3) -#define MPP17_TW_SDA2 MPP_PIN(17, 0x4) -#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) - -#define MPP18_GPIO18 MPP_PIN(18, 0x0) -#define MPP18_UA3_TXD MPP_PIN(18, 0x2) -#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) -#define MPP18_LCD0_PWM MPP_PIN(18, 0x4) -#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) - -#define MPP19_GPIO19 MPP_PIN(19, 0x0) -#define MPP19_UA3_RXD MPP_PIN(19, 0x2) -#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) -#define MPP19_TW_SCK2 MPP_PIN(19, 0x4) - -#define MPP20_GPIO20 MPP_PIN(20, 0x0) -#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1) -#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2) -#define MPP20_SDIO1_CD MPP_PIN(20, 0x3) -#define MPP20_SDIO0_CD MPP_PIN(20, 0x5) -#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6) - -#define MPP21_GPIO21 MPP_PIN(21, 0x0) -#define MPP21_UA1_RTSn MPP_PIN(21, 0x1) -#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2) -#define MPP21_SDIO1_WP MPP_PIN(21, 0x3) -#define MPP21_SSP_SFRM MPP_PIN(21, 0x4) -#define MPP21_SDIO0_WP MPP_PIN(21, 0x5) -#define MPP21_SPI_1_CS MPP_PIN(21, 0x6) - -#define MPP22_GPIO22 MPP_PIN(22, 0x0) -#define MPP22_UA1_CTSn MPP_PIN(22, 0x1) -#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2) -#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3) -#define MPP22_SSP_TXD MPP_PIN(22, 0x4) -#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5) -#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6) - -#define MPP23_GPIO23 MPP_PIN(23, 0x0) -#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2) -#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3) -#define MPP23_SSP_SCLK MPP_PIN(23, 0x4) -#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5) -#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6) +#define MPP(_num, _sel, _in, _out) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13)) + +#define MPP0_GPIO0 MPP(0, 0x0, 1, 1) +#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0) +#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0) +#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0) + +#define MPP1_GPIO1 MPP(1, 0x0, 1, 1) +#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0) +#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0) +#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0) + +#define MPP2_GPIO2 MPP(2, 0x0, 1, 1) +#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0) +#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0) +#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0) +#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0) + +#define MPP3_GPIO3 MPP(3, 0x0, 1, 1) +#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0) +#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0) +#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0) +#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0) +#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0) + +#define MPP4_GPIO4 MPP(4, 0x0, 1, 1) +#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0) +#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0) +#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0) + +#define MPP5_GPIO5 MPP(5, 0x0, 1, 1) +#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0) +#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0) +#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0) + +#define MPP6_GPIO6 MPP(6, 0x0, 1, 1) +#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0) +#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0) +#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0) + +#define MPP7_GPIO7 MPP(7, 0x0, 1, 1) +#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0) +#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0) +#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0) + +#define MPP8_GPIO8 MPP(8, 0x0, 1, 1) +#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0) + +#define MPP9_GPIO9 MPP(9, 0x0, 1, 1) +#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0) + +#define MPP10_GPIO10 MPP(10, 0x0, 1, 1) +#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0) + +#define MPP11_GPIO11 MPP(11, 0x0, 1, 1) +#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0) +#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0) +#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0) +#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0) +#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0) + +#define MPP12_GPIO12 MPP(12, 0x0, 1, 1) +#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0) +#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0) +#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0) +#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0) + +#define MPP13_GPIO13 MPP(13, 0x0, 1, 1) +#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0) +#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0) +#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0) +#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0) + +#define MPP14_GPIO14 MPP(14, 0x0, 1, 1) +#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0) +#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0) +#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0) + +#define MPP15_GPIO15 MPP(15, 0x0, 1, 1) +#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0) +#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0) +#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0) + +#define MPP16_GPIO16 MPP(16, 0x0, 1, 1) +#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0) +#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0) +#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0) +#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0) + +#define MPP17_GPIO17 MPP(17, 0x0, 1, 1) +#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0) +#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0) +#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0) +#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0) +#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0) + +#define MPP18_GPIO18 MPP(18, 0x0, 1, 1) +#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0) +#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0) +#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0) +#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0) + +#define MPP19_GPIO19 MPP(19, 0x0, 1, 1) +#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0) +#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0) +#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0) + +#define MPP20_GPIO20 MPP(20, 0x0, 1, 1) +#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0) +#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0) +#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0) +#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0) +#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0) + +#define MPP21_GPIO21 MPP(21, 0x0, 1, 1) +#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0) +#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0) +#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0) +#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0) +#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0) +#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0) + +#define MPP22_GPIO22 MPP(22, 0x0, 1, 1) +#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0) +#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0) +#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0) +#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0) +#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0) +#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0) + +#define MPP23_GPIO23 MPP(23, 0x0, 1, 1) +#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0) +#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0) +#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0) +#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0) +#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0) + +#define MPP_MAX 23 + +#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0) /* for MPP groups _num is a group index */ enum dove_mpp_grp_idx { @@ -181,40 +153,44 @@ enum dove_mpp_grp_idx { MPP_46_51 = 1, MPP_58_61 = 5, MPP_62_63 = 4, + MPP_GRP_MAX = 5, }; -#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) -#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) +#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1) +#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0) -#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) -#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) +#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1) +#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0) -#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) -#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) +#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1) +#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0) -#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) -#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) +#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1) +#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0) -#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) -#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) +#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1) +#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0) /* The MPP[64:71] control differs from other groups */ -#define MPP64_71_GPO MPP_GRP_NFC(0x1) -#define MPP64_71_NFC MPP_GRP_NFC(0x0) +#define MPP_GRP_NFC_64_71_GPO 0x1 +#define MPP_GRP_NFC_64_71_NFC 0x0 /* * The MPP[52:57] functionality is encoded by 4 bits in different * registers. The _num field in this case encodes those bits in * correspodence with Table 135 of 88AP510 Functional specification */ -#define MPP52_57_AU1 MPP_GRP_AU1(0x0) -#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) -#define MPP52_57_GPIO MPP_GRP_AU1(0xa) -#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) -#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) -#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) -#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) - -void dove_mpp_conf(unsigned int *mpp_list); +#define MPP_GRP_AU1_52_57_AU1 0x0 +#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2 +#define MPP_GRP_AU1_52_57_GPIO 0xa +#define MPP_GRP_AU1_52_57_TW_GPIO 0xb +#define MPP_GRP_AU1_52_57_AU1_SSP 0xc +#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe +#define MPP_GRP_AU1_52_57_SSP_TW 0xf + +void dove_mpp_conf(unsigned int *mpp_list, + unsigned int *mpp_grp_list, + unsigned int grp_au1_52_57, + unsigned int grp_nfc_64_71); #endif /* __ARCH_DOVE_MPP_CODED_H */ diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 7df083f37fa..087bc771ac2 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void) local_irq_restore(flags); for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &ebsa110_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ebsa110_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 34e071d7976..415dce37b88 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -101,7 +101,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc) static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc) { /* - * map discontiguous hw irq range to continous sw irq range: + * map discontiguous hw irq range to continuous sw irq range: * * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) */ @@ -117,7 +117,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { gpio_int_type2[port] ^= port_mask; /* switch edge direction */ ep93xx_gpio_update_int_params(port); } @@ -131,7 +131,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) int port = line >> 3; int port_mask = 1 << (line & 7); - if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) gpio_int_type2[port] ^= port_mask; /* switch edge direction */ gpio_int_unmasked[port] &= ~port_mask; @@ -165,10 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) */ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_desc + d->irq; const int gpio = irq_to_gpio(d->irq); const int port = gpio >> 3; const int port_mask = 1 << (gpio & 7); + irq_flow_handler_t handler; gpio_direction_input(gpio); @@ -176,22 +176,22 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: gpio_int_type1[port] |= port_mask; gpio_int_type2[port] |= port_mask; - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; case IRQ_TYPE_EDGE_FALLING: gpio_int_type1[port] |= port_mask; gpio_int_type2[port] &= ~port_mask; - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: gpio_int_type1[port] &= ~port_mask; gpio_int_type2[port] |= port_mask; - desc->handle_irq = handle_level_irq; + handler = handle_level_irq; break; case IRQ_TYPE_LEVEL_LOW: gpio_int_type1[port] &= ~port_mask; gpio_int_type2[port] &= ~port_mask; - desc->handle_irq = handle_level_irq; + handler = handle_level_irq; break; case IRQ_TYPE_EDGE_BOTH: gpio_int_type1[port] |= port_mask; @@ -200,17 +200,16 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) gpio_int_type2[port] &= ~port_mask; /* falling */ else gpio_int_type2[port] |= port_mask; /* rising */ - desc->handle_irq = handle_edge_irq; + handler = handle_edge_irq; break; default: pr_err("failed to set irq type %d for gpio %d\n", type, gpio); return -EINVAL; } - gpio_int_enabled[port] |= port_mask; + __irq_set_handler_locked(d->irq, handler); - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type & IRQ_TYPE_SENSE_MASK; + gpio_int_enabled[port] |= port_mask; ep93xx_gpio_update_int_params(port); @@ -232,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void) for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { - set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); - set_irq_handler(gpio_irq, handle_level_irq); + irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, + handle_level_irq); set_irq_flags(gpio_irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); - set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, + ep93xx_gpio_ab_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, + ep93xx_gpio_f_irq_handler); + irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, + ep93xx_gpio_f_irq_handler); } @@ -348,29 +356,6 @@ static int ep93xx_gpio_set_debounce(struct gpio_chip *chip, return 0; } -static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); - u8 data_reg, data_dir_reg; - int gpio, i; - - data_reg = __raw_readb(ep93xx_chip->data_reg); - data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); - - gpio = ep93xx_chip->chip.base; - for (i = 0; i < chip->ngpio; i++, gpio++) { - int is_out = data_dir_reg & (1 << i); - int irq = gpio_to_irq(gpio); - - seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n", - chip->label, i, gpio, - gpiochip_is_requested(chip, i) ? : "", - is_out ? "out" : "in ", - (data_reg & (1<< i)) ? "hi" : "lo", - (!is_out && irq>= 0) ? "(interrupt)" : ""); - } -} - #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ { \ .chip = { \ @@ -379,7 +364,6 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) .direction_output = ep93xx_gpio_direction_output, \ .get = ep93xx_gpio_get, \ .set = ep93xx_gpio_set, \ - .dbg_show = ep93xx_gpio_dbg_show, \ .base = base_gpio, \ .ngpio = 8, \ }, \ diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index a021b5240bb..805196207ce 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -20,6 +20,11 @@ config EXYNOS4_MCT help Use MCT (Multi Core Timer) as kernel timers +config EXYNOS4_DEV_AHCI + bool + help + Compile in platform device definitions for AHCI + config EXYNOS4_DEV_PD bool help @@ -134,9 +139,9 @@ config MACH_ARMLEX4210 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 + select EXYNOS4_DEV_AHCI select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI - select SATA_AHCI_PLATFORM help Machine support for Samsung ARMLEX4210 based on EXYNOS4210 @@ -165,6 +170,7 @@ config MACH_NURI select S3C_DEV_HSMMC3 select S3C_DEV_I2C1 select S3C_DEV_I2C5 + select S5P_DEV_USB_EHCI select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C5 select EXYNOS4_SETUP_SDHCI diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index b8f0e7d82d7..777897551e4 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_MACH_NURI) += mach-nuri.o # device support obj-y += dev-audio.o +obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o @@ -53,4 +54,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o + +obj-$(CONFIG_USB_SUPPORT) += usb-phy.o diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 79301139194..08813a6f66b 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -97,7 +97,12 @@ static struct map_desc exynos4_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), .length = SZ_4K, .type = MT_DEVICE, - }, + }, { + .virtual = (unsigned long)S5P_VA_USB_HSPHY, + .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), + .length = SZ_4K, + .type = MT_DEVICE, + } }; static void exynos4_idle(void) diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S index 58bbd049a6c..a442ef86116 100644 --- a/arch/arm/mach-exynos4/include/mach/debug-macro.S +++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S @@ -21,8 +21,8 @@ */ .macro addruart, rp, rv - ldreq \rp, = S3C_PA_UART - ldrne \rv, = S3C_VA_UART + ldr \rp, = S3C_PA_UART + ldr \rv, = S3C_VA_UART #if CONFIG_DEBUG_S3C_UART != 0 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h index 939728b38d4..be9266b10fd 100644 --- a/arch/arm/mach-exynos4/include/mach/gpio.h +++ b/arch/arm/mach-exynos4/include/mach/gpio.h @@ -18,7 +18,7 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq -/* Practically, GPIO banks upto GPZ are the configurable gpio banks */ +/* Practically, GPIO banks up to GPZ are the configurable gpio banks */ /* GPIO bank sizes */ #define EXYNOS4_GPIO_A0_NR (8) diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 6330b73b9ea..0009e77a05f 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -101,6 +101,9 @@ #define EXYNOS4_PA_SROMC 0x12570000 +#define EXYNOS4_PA_EHCI 0x12580000 +#define EXYNOS4_PA_HSPHY 0x125B0000 + #define EXYNOS4_PA_UART 0x13800000 #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) @@ -143,6 +146,7 @@ #define S5P_PA_SROMC EXYNOS4_PA_SROMC #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON #define S5P_PA_TIMER EXYNOS4_PA_TIMER +#define S5P_PA_EHCI EXYNOS4_PA_EHCI #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index 62b0014d05e..a9643371f8e 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h @@ -33,6 +33,9 @@ #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) +#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) +#define S5P_USBHOST_PHY_ENABLE (1 << 0) + #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) diff --git a/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h new file mode 100644 index 00000000000..703118d5173 --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PLAT_S5P_REGS_USB_PHY_H +#define __PLAT_S5P_REGS_USB_PHY_H + +#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S5P_VA_USB_HSPHY) + +#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00) +#define PHY1_HSIC_NORMAL_MASK (0xf << 9) +#define PHY1_HSIC1_SLEEP (1 << 12) +#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11) +#define PHY1_HSIC0_SLEEP (1 << 10) +#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9) + +#define PHY1_STD_NORMAL_MASK (0x7 << 6) +#define PHY1_STD_SLEEP (1 << 8) +#define PHY1_STD_ANALOG_POWERDOWN (1 << 7) +#define PHY1_STD_FORCE_SUSPEND (1 << 6) + +#define PHY0_NORMAL_MASK (0x39 << 0) +#define PHY0_SLEEP (1 << 5) +#define PHY0_OTG_DISABLE (1 << 4) +#define PHY0_ANALOG_POWERDOWN (1 << 3) +#define PHY0_FORCE_SUSPEND (1 << 0) + +#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04) +#define PHY1_COMMON_ON_N (1 << 7) +#define PHY0_COMMON_ON_N (1 << 4) +#define PHY0_ID_PULLUP (1 << 2) +#define CLKSEL_MASK (0x3 << 0) +#define CLKSEL_SHIFT (0) +#define CLKSEL_48M (0x0 << 0) +#define CLKSEL_12M (0x2 << 0) +#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) +#define HOST_LINK_PORT_SWRST_MASK (0xf << 6) +#define HOST_LINK_PORT2_SWRST (1 << 9) +#define HOST_LINK_PORT1_SWRST (1 << 8) +#define HOST_LINK_PORT0_SWRST (1 << 7) +#define HOST_LINK_ALL_SWRST (1 << 6) + +#define PHY1_SWRST_MASK (0x7 << 3) +#define PHY1_HSIC_SWRST (1 << 5) +#define PHY1_STD_SWRST (1 << 4) +#define PHY1_ALL_SWRST (1 << 3) + +#define PHY0_SWRST_MASK (0x7 << 0) +#define PHY0_PHYLINK_SWRST (1 << 2) +#define PHY0_HLINK_SWRST (1 << 1) +#define PHY0_SWRST (1 << 0) + +#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34) +#define FPENABLEN (1 << 0) + +#endif /* __PLAT_S5P_REGS_USB_PHY_H */ diff --git a/arch/arm/mach-exynos4/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h deleted file mode 100644 index a463dcebcfd..00000000000 --- a/arch/arm/mach-exynos4/include/mach/smp.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/smp.h - * - * Cloned from arch/arm/mach-realview/include/mach/smp.h -*/ - -#ifndef ASM_ARCH_SMP_H -#define ASM_ARCH_SMP_H __FILE__ - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index 31618d91ce1..5a2758ab055 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c @@ -54,13 +54,12 @@ static void combiner_unmask_irq(struct irq_data *data) static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { - struct combiner_chip_data *chip_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + struct combiner_chip_data *chip_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); unsigned int cascade_irq, combiner_irq; unsigned long status; - /* primary controller ack'ing */ - chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); spin_lock(&irq_controller_lock); status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); @@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) generic_handle_irq(cascade_irq); out: - /* primary controller unmasking */ - chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } static struct irq_chip combiner_chip = { @@ -93,9 +91,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) { if (combiner_nr >= MAX_COMBINER_NR) BUG(); - if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) + if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) BUG(); - set_irq_chained_handler(irq, combiner_handle_cascade_irq); + irq_set_chained_handler(irq, combiner_handle_cascade_irq); } void __init combiner_init(unsigned int combiner_nr, void __iomem *base, @@ -119,9 +117,8 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, for (i = irq_start; i < combiner_data[combiner_nr].irq_offset + MAX_IRQ_IN_COMBINER; i++) { - set_irq_chip(i, &combiner_chip); - set_irq_chip_data(i, &combiner_data[combiner_nr]); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); + irq_set_chip_data(i, &combiner_data[combiner_nr]); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c index 4f7ad4a796e..9d87d2ac7f6 100644 --- a/arch/arm/mach-exynos4/irq-eint.c +++ b/arch/arm/mach-exynos4/irq-eint.c @@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) { - u32 *irq_data = get_irq_data(irq); - struct irq_chip *chip = get_irq_chip(irq); + u32 *irq_data = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); chip->irq_mask(&desc->irq_data); @@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void) int irq; for (irq = 0 ; irq <= 31 ; irq++) { - set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); - set_irq_handler(IRQ_EINT(irq), handle_level_irq); + irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, + handle_level_irq); set_irq_flags(IRQ_EINT(irq), IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); + irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); for (irq = 0 ; irq <= 15 ; irq++) { eint0_15_data[irq] = IRQ_EINT(irq); - set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); - set_irq_chained_handler(exynos4_get_irq_nr(irq), + irq_set_handler_data(exynos4_get_irq_nr(irq), + &eint0_15_data[irq]); + irq_set_chained_handler(exynos4_get_irq_nr(irq), exynos4_irq_eint0_15); } diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c index b79ad010d19..bb5d12f43af 100644 --- a/arch/arm/mach-exynos4/mach-nuri.c +++ b/arch/arm/mach-exynos4/mach-nuri.c @@ -30,6 +30,8 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> +#include <plat/ehci.h> +#include <plat/clock.h> #include <mach/map.h> @@ -262,6 +264,16 @@ static struct i2c_board_info i2c5_devs[] __initdata = { /* max8997, To be updated */ }; +/* USB EHCI */ +static struct s5p_ehci_platdata nuri_ehci_pdata; + +static void __init nuri_ehci_init(void) +{ + struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata; + + s5p_ehci_set_platdata(pdata); +} + static struct platform_device *nuri_devices[] __initdata = { /* Samsung Platform Devices */ &emmc_fixed_voltage, @@ -270,6 +282,7 @@ static struct platform_device *nuri_devices[] __initdata = { &s3c_device_hsmmc3, &s3c_device_wdt, &s3c_device_timer[0], + &s5p_device_ehci, /* NURI Devices */ &nuri_gpio_keys, @@ -291,6 +304,9 @@ static void __init nuri_machine_init(void) i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); + nuri_ehci_init(); + clk_xusbxti.rate = 24000000; + /* Last */ platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); } diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c index 25a25681812..e645f7a955f 100644 --- a/arch/arm/mach-exynos4/mach-smdkc210.c +++ b/arch/arm/mach-exynos4/mach-smdkc210.c @@ -125,7 +125,7 @@ static struct resource smdkc210_smsc911x_resources[] = { }; static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index 88e0275143b..152676471b6 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c @@ -127,7 +127,7 @@ static struct resource smdkv310_smsc911x_resources[] = { }; static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, .phy_interface = PHY_INTERFACE_MODE_MII, diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c index af82a8fbb68..14ac10b7ec0 100644 --- a/arch/arm/mach-exynos4/mct.c +++ b/arch/arm/mach-exynos4/mct.c @@ -276,7 +276,7 @@ static void exynos4_mct_tick_start(unsigned long cycles, /* update interrupt count buffer */ exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); - /* enable MCT tick interupt */ + /* enable MCT tick interrupt */ exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET); diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index 6d35878ec1a..c5e65a02be8 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <asm/unified.h> @@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -147,6 +148,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 10d917d9e3a..8755ca8dd48 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/suspend.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <asm/cacheflush.h> @@ -372,7 +373,27 @@ void exynos4_scu_enable(void __iomem *scu_base) flush_cache_all(); } -static int exynos4_pm_resume(struct sys_device *dev) +static struct sysdev_driver exynos4_pm_driver = { + .add = exynos4_pm_add, +}; + +static __init int exynos4_pm_drvinit(void) +{ + unsigned int tmp; + + s3c_pm_init(); + + /* All wakeup disable */ + + tmp = __raw_readl(S5P_WAKEUP_MASK); + tmp |= ((0xFF << 8) | (0x1F << 1)); + __raw_writel(tmp, S5P_WAKEUP_MASK); + + return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); +} +arch_initcall(exynos4_pm_drvinit); + +static void exynos4_pm_resume(void) { /* For release retention */ @@ -394,27 +415,15 @@ static int exynos4_pm_resume(struct sys_device *dev) /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif - - return 0; } -static struct sysdev_driver exynos4_pm_driver = { - .add = exynos4_pm_add, +static struct syscore_ops exynos4_pm_syscore_ops = { .resume = exynos4_pm_resume, }; -static __init int exynos4_pm_drvinit(void) +static __init int exynos4_pm_syscore_init(void) { - unsigned int tmp; - - s3c_pm_init(); - - /* All wakeup disable */ - - tmp = __raw_readl(S5P_WAKEUP_MASK); - tmp |= ((0xFF << 8) | (0x1F << 1)); - __raw_writel(tmp, S5P_WAKEUP_MASK); - - return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); + register_syscore_ops(&exynos4_pm_syscore_ops); + return 0; } -arch_initcall(exynos4_pm_drvinit); +arch_initcall(exynos4_pm_syscore_init); diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c index 1b3d3a2de95..e8d08bf8965 100644 --- a/arch/arm/mach-exynos4/setup-sdhci-gpio.c +++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c @@ -38,14 +38,14 @@ void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) switch (width) { case 8: for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-funtion 3 */ + /* Data pin GPK1[3:6] to special-function 3 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); } case 4: for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { - /* Data pin GPK0[3:6] to special-funtion 2 */ + /* Data pin GPK0[3:6] to special-function 2 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c index 85f9433d483..1e83f8cf236 100644 --- a/arch/arm/mach-exynos4/setup-sdhci.c +++ b/arch/arm/mach-exynos4/setup-sdhci.c @@ -35,7 +35,7 @@ void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, { u32 ctrl2, ctrl3; - /* don't need to alter anything acording to card-type */ + /* don't need to alter anything according to card-type */ ctrl2 = readl(r + S3C_SDHCI_CONTROL2); diff --git a/arch/arm/mach-exynos4/usb-phy.c b/arch/arm/mach-exynos4/usb-phy.c new file mode 100644 index 00000000000..0883c1b824b --- /dev/null +++ b/arch/arm/mach-exynos4/usb-phy.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <mach/regs-pmu.h> +#include <mach/regs-usb-phy.h> +#include <plat/cpu.h> +#include <plat/usb-phy.h> + +static int exynos4_usb_phy1_init(struct platform_device *pdev) +{ + struct clk *otg_clk; + struct clk *xusbxti_clk; + u32 phyclk; + u32 rstcon; + int err; + + otg_clk = clk_get(&pdev->dev, "otg"); + if (IS_ERR(otg_clk)) { + dev_err(&pdev->dev, "Failed to get otg clock\n"); + return PTR_ERR(otg_clk); + } + + err = clk_enable(otg_clk); + if (err) { + clk_put(otg_clk); + return err; + } + + writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, + S5P_USBHOST_PHY_CONTROL); + + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; + + xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); + if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { + switch (clk_get_rate(xusbxti_clk)) { + case 12 * MHZ: + phyclk |= CLKSEL_12M; + break; + case 24 * MHZ: + phyclk |= CLKSEL_24M; + break; + default: + case 48 * MHZ: + /* default reference clock */ + break; + } + clk_put(xusbxti_clk); + } + + writel(phyclk, EXYNOS4_PHYCLK); + + /* floating prevention logic: disable */ + writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); + + /* set to normal HSIC 0 and 1 of PHY1 */ + writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK), + EXYNOS4_PHYPWR); + + /* set to normal standard USB of PHY1 */ + writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR); + + /* reset all ports of both PHY and Link */ + rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK | + PHY1_SWRST_MASK; + writel(rstcon, EXYNOS4_RSTCON); + udelay(10); + + rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK); + writel(rstcon, EXYNOS4_RSTCON); + udelay(50); + + clk_disable(otg_clk); + clk_put(otg_clk); + + return 0; +} + +static int exynos4_usb_phy1_exit(struct platform_device *pdev) +{ + struct clk *otg_clk; + int err; + + otg_clk = clk_get(&pdev->dev, "otg"); + if (IS_ERR(otg_clk)) { + dev_err(&pdev->dev, "Failed to get otg clock\n"); + return PTR_ERR(otg_clk); + } + + err = clk_enable(otg_clk); + if (err) { + clk_put(otg_clk); + return err; + } + + writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN), + EXYNOS4_PHYPWR); + + writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE, + S5P_USBHOST_PHY_CONTROL); + + clk_disable(otg_clk); + clk_put(otg_clk); + + return 0; +} + +int s5p_usb_phy_init(struct platform_device *pdev, int type) +{ + if (type == S5P_USB_PHY_HOST) + return exynos4_usb_phy1_init(pdev); + + return -EINVAL; +} + +int s5p_usb_phy_exit(struct platform_device *pdev, int type) +{ + if (type == S5P_USB_PHY_HOST) + return exynos4_usb_phy1_exit(pdev); + + return -EINVAL; +} diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index bdd257921cf..46adca068f2 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -4,6 +4,7 @@ menu "Footbridge Implementations" config ARCH_CATS bool "CATS" + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA @@ -59,6 +60,7 @@ config ARCH_EBSA285_HOST config ARCH_NETWINDER bool "NetWinder" + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 84c5f258f2d..38a44f9b9da 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -102,8 +102,7 @@ static void __init __fb_init_irq(void) *CSR_FIQ_DISABLE = -1; for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { - set_irq_chip(irq, &fb_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index a921fe92b85..5f1f9867fc7 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -30,7 +30,7 @@ static int cksrc_dc21285_enable(struct clocksource *cs) return 0; } -static int cksrc_dc21285_disable(struct clocksource *cs) +static void cksrc_dc21285_disable(struct clocksource *cs) { *CSR_TIMER2_CNTL = 0; } diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index de7a5cb5dbe..c3a0abbc904 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq) if (host_irq != (unsigned int)-1) { for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { - set_irq_chip(irq, &isa_lo_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &isa_lo_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { - set_irq_chip(irq, &isa_hi_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &isa_hi_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } @@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq) request_resource(&ioport_resource, &pic2_resource); setup_irq(IRQ_ISA_CASCADE, &irq_cascade); - set_irq_chained_handler(host_irq, isa_irq_handler); + irq_set_chained_handler(host_irq, isa_irq_handler); /* * On the NetWinder, don't automatically diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c index 441c6ce0d55..7020f1a3fec 100644 --- a/arch/arm/mach-footbridge/isa-timer.c +++ b/arch/arm/mach-footbridge/isa-timer.c @@ -10,53 +10,16 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <linux/timex.h> #include <asm/irq.h> - +#include <asm/i8253.h> #include <asm/mach/time.h> #include "common.h" -#define PIT_MODE 0x43 -#define PIT_CH0 0x40 - -#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) - -static cycle_t pit_read(struct clocksource *cs) -{ - unsigned long flags; - static int old_count; - static u32 old_jifs; - int count; - u32 jifs; - - raw_local_irq_save(flags); - - jifs = jiffies; - outb_p(0x00, PIT_MODE); /* latch the count */ - count = inb_p(PIT_CH0); /* read the latched count */ - count |= inb_p(PIT_CH0) << 8; - - if (count > old_count && jifs == old_jifs) - count = old_count; - - old_count = count; - old_jifs = jifs; - - raw_local_irq_restore(flags); - - count = (PIT_LATCH - 1) - count; - - return (cycle_t)(jifs * PIT_LATCH) + count; -} - -static struct clocksource pit_cs = { - .name = "pit", - .rating = 110, - .read = pit_read, - .mask = CLOCKSOURCE_MASK(32), -}; +DEFINE_RAW_SPINLOCK(i8253_lock); static void pit_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) @@ -121,7 +84,7 @@ static void __init isa_timer_init(void) pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce); pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce); - clocksource_register_hz(&pit_cs, PIT_TICK_RATE); + clocksource_i8253_init(); setup_irq(pit_ce.irq, &pit_timer_irq); clockevents_register_device(&pit_ce); diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fa3d333f21e..fdc7ef1391d 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -127,8 +127,8 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { + unsigned int port = (unsigned int)irq_desc_get_handler_data(desc); unsigned int gpio_irq_no, irq_stat; - unsigned int port = (unsigned int)get_irq_data(irq); irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); @@ -138,9 +138,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if ((irq_stat & 1) == 0) continue; - BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); - irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, - &irq_desc[gpio_irq_no]); + generic_handle_irq(gpio_irq_no); } } @@ -219,13 +217,13 @@ void __init gemini_gpio_init(void) for (j = GPIO_IRQ_BASE + i * 32; j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_edge_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_edge_irq); set_irq_flags(j, IRQF_VALID); } - set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); - set_irq_data(IRQ_GPIO(i), (void *)i); + irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler); + irq_set_handler_data(IRQ_GPIO(i), (void *)i); } BUG_ON(gpiochip_add(&gemini_gpio_chip)); diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h index 5483f61a806..0efa2624723 100644 --- a/arch/arm/mach-gemini/include/mach/uncompress.h +++ b/arch/arm/mach-gemini/include/mach/uncompress.h @@ -16,7 +16,7 @@ #include <linux/serial_reg.h> #include <mach/hardware.h> -static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE; +static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE; /* * The following code assumes the serial port has already been diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 96bc227dd84..9485a8fdf85 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c @@ -81,13 +81,13 @@ void __init gemini_init_irq(void) request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &gemini_irq_chip); + irq_set_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 1f28c90932c..51d4e44ab97 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -199,29 +199,29 @@ void __init h720x_init_irq (void) /* Initialize global IRQ's, fast path */ for (irq = 0; irq < NR_GLBL_IRQS; irq++) { - set_irq_chip(irq, &h720x_global_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &h720x_global_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Initialize multiplexed IRQ's, slow path */ for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { - set_irq_chip(irq, &h720x_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &h720x_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); - set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); - set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); - set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); + irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); + irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); + irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); + irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); #ifdef CONFIG_CPU_H7202 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { - set_irq_chip(irq, &h720x_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &h720x_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); + irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); #endif /* Enable multiplexed irq's */ diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index ac3f9144237..c37d570b852 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -141,13 +141,18 @@ h7202_timer_interrupt(int irq, void *dev_id) /* * mask multiplexed timer IRQs */ -static void inline mask_timerx_irq(struct irq_data *d) +static void inline __mask_timerx_irq(unsigned int irq) { unsigned int bit; - bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); + bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; } +static void inline mask_timerx_irq(struct irq_data *d) +{ + __mask_timerx_irq(d->irq); +} + /* * unmask multiplexed timer IRQs */ @@ -196,12 +201,12 @@ void __init h7202_init_irq (void) for (irq = IRQ_TIMER1; irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { - mask_timerx_irq(irq); - set_irq_chip(irq, &h7202_timerx_chip); - set_irq_handler(irq, handle_edge_irq); + __mask_timerx_irq(irq); + irq_set_chip_and_handler(irq, &h7202_timerx_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID ); } - set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); + irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); h720x_init_irq(); } diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h index 9d368765146..b0b3baec9ac 100644 --- a/arch/arm/mach-h720x/include/mach/memory.h +++ b/arch/arm/mach-h720x/include/mach/memory.h @@ -13,7 +13,6 @@ * There should not be more than (0xd0000000 - 0xc0000000) * bytes of RAM. */ -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#define ARM_DMA_ZONE_SIZE SZ_256M #endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5eec099e0c7..59c97a33113 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,5 +1,15 @@ config IMX_HAVE_DMA_V1 bool +# +# ARCH_MX31 and ARCH_MX35 are left for compatibility +# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. +# To easily distinguish good and reviewed from unreviewed usages new (and IMHO +# more sensible) names are used: SOC_IMX31 and SOC_IMX35 +config ARCH_MX31 + bool + +config ARCH_MX35 + bool config SOC_IMX1 bool @@ -31,6 +41,24 @@ config SOC_IMX27 select IMX_HAVE_IOMUX_V1 select MXC_AVIC +config SOC_IMX31 + bool + select CPU_V6 + select IMX_HAVE_PLATFORM_MXC_RNGA + select ARCH_MXC_AUDMUX_V2 + select ARCH_MX31 + select MXC_AVIC + +config SOC_IMX35 + bool + select CPU_V6 + select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 + select HAVE_EPIT + select ARCH_MX35 + select MXC_AVIC + + if ARCH_MX1 comment "MX1 platforms:" @@ -40,6 +68,7 @@ config MACH_MXLADS config ARCH_MX1ADS bool "MX1ADS platform" select MACH_MXLADS + select SOC_IMX1 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART help @@ -51,6 +80,13 @@ config MACH_SCB9328 help Say Y here if you are using a Synertronixx scb9328 board +config MACH_APF9328 + bool "APF9328" + select SOC_IMX1 + select IMX_HAVE_PLATFORM_IMX_UART + help + Say Yes here if you are using the Armadeus APF9328 development board + endif if ARCH_MX2 @@ -129,6 +165,7 @@ choice config MACH_EUKREA_MBIMXSD25_BASEBOARD bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_SSI help This adds board specific devices that can be found on Eukrea's @@ -254,7 +291,9 @@ config MACH_MX27_3DS config MACH_IMX27_VISSTRIM_M10 bool "Vista Silicon i.MX27 Visstrim_m10" select SOC_IMX27 + select IMX_HAVE_PLATFORM_GPIO_KEYS select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_EHCI @@ -313,3 +352,251 @@ config MACH_IMX27IPCAM configurations for the board and its peripherals. endif + +if ARCH_MX3 + +comment "MX31 platforms:" + +config MACH_MX31ADS + bool "Support MX31ADS platforms" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_IMX_UART + default y + help + Include support for MX31ADS platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX31ADS_WM1133_EV1 + bool "Support Wolfson Microelectronics 1133-EV1 module" + depends on MACH_MX31ADS + depends on MFD_WM8350_I2C + depends on REGULATOR_WM8350 + select MFD_WM8350_CONFIG_MODE_0 + select MFD_WM8352_CONFIG_MODE_0 + help + Include support for the Wolfson Microelectronics 1133-EV1 PMU + and audio module for the MX31ADS platform. + +config MACH_MX31LILLY + bool "Support MX31 LILLY-1131 platforms (INCO startec)" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_ULPI if USB_ULPI + help + Include support for mx31 based LILLY1131 modules. This includes + specific configurations for the board and its peripherals. + +config MACH_MX31LITE + bool "Support MX31 LITEKIT (LogicPD)" + select SOC_IMX31 + select MXC_ULPI if USB_ULPI + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_RTC + select IMX_HAVE_PLATFORM_SPI_IMX + help + Include support for MX31 LITEKIT platform. This includes specific + configurations for the board and its peripherals. + +config MACH_PCM037 + bool "Support Phytec pcm037 (i.MX31) platforms" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 + select MXC_ULPI if USB_ULPI + help + Include support for Phytec pcm037 platform. This includes + specific configurations for the board and its peripherals. + +config MACH_PCM037_EET + bool "Support pcm037 EET board extensions" + depends on MACH_PCM037 + select IMX_HAVE_PLATFORM_GPIO_KEYS + select IMX_HAVE_PLATFORM_SPI_IMX + help + Add support for PCM037 EET baseboard extensions. If you are using the + OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel + command-line parameter. + +config MACH_MX31_3DS + bool "Support MX31PDK (3DS)" + select SOC_IMX31 + select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_KEYPAD + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_ULPI if USB_ULPI + help + Include support for MX31PDK (3DS) platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX31_3DS_MXC_NAND_USE_BBT + bool "Make the MXC NAND driver use the in flash Bad Block Table" + depends on MACH_MX31_3DS + depends on MTD_NAND_MXC + help + Enable this if you want that the MXC NAND driver uses the in flash + Bad Block Table to know what blocks are bad instead of scanning the + entire flash looking for bad block markers. + +config MACH_MX31MOBOARD + bool "Support mx31moboard platforms (EPFL Mobots group)" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_ULPI if USB_ULPI + help + Include support for mx31moboard platform. This includes specific + configurations for the board and its peripherals. + +config MACH_QONG + bool "Support Dave/DENX QongEVB-LITE platform" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for Dave/DENX QongEVB-LITE platform. This includes + specific configurations for the board and its peripherals. + +config MACH_ARMADILLO5X0 + bool "Support Atmark Armadillo-500 Development Base Board" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_GPIO_KEYS + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_MXC_NAND + select MXC_ULPI if USB_ULPI + help + Include support for Atmark Armadillo-500 platform. This includes + specific configurations for the board and its peripherals. + +config MACH_KZM_ARM11_01 + bool "Support KZM-ARM11-01(Kyoto Microcomputer)" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for KZM-ARM11-01. This includes specific + configurations for the board and its peripherals. + +config MACH_BUG + bool "Support Buglabs BUGBase platform" + select SOC_IMX31 + select IMX_HAVE_PLATFORM_IMX_UART + default y + help + Include support for BUGBase 1.3 platform. This includes specific + configurations for the board and its peripherals. + +comment "MX35 platforms:" + +config MACH_PCM043 + bool "Support Phytec pcm043 (i.MX35) platforms" + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select MXC_ULPI if USB_ULPI + help + Include support for Phytec pcm043 platform. This includes + specific configurations for the board and its peripherals. + +config MACH_MX35_3DS + bool "Support MX35PDK platform" + select SOC_IMX35 + select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + help + Include support for MX35PDK platform. This includes specific + configurations for the board and its peripherals. + +config MACH_EUKREA_CPUIMX35 + bool "Support Eukrea CPUIMX35 Platform" + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select MXC_ULPI if USB_ULPI + help + Include support for Eukrea CPUIMX35 platform. This includes + specific configurations for the board and its peripherals. + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX35 + default MACH_EUKREA_MBIMXSD35_BASEBOARD + +config MACH_EUKREA_MBIMXSD35_BASEBOARD + bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_GPIO_KEYS + select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_IPU_CORE + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice + +config MACH_VPR200 + bool "Support VPR200 platform" + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_GPIO_KEYS + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IPU_CORE + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + help + Include support for VPR200 platform. This includes specific + configurations for the board and its peripherals. + +endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index b85794d2799..e9eb36dad88 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,9 +1,3 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o @@ -14,18 +8,27 @@ obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o +obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o +obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o +obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o + # Support for CMOS sensor interface -obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o +obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o +# i.MX1 based machines obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o +obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o +# i.MX21 based machines obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o +# i.MX25 based machines obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o +# i.MX27 based machines obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o @@ -37,3 +40,24 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o + +# i.MX31 based machines +obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o +obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o +obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o +obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o +obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o +obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o +obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ + mx31moboard-marxbot.o mx31moboard-smartbot.o +obj-$(CONFIG_MACH_QONG) += mach-qong.o +obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o +obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o +obj-$(CONFIG_MACH_BUG) += mach-bug.o + +# i.MX35 based machines +obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o +obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o +obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 3953d60bff0..ebee18b3884 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -13,3 +13,7 @@ initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000 zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 + +zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000 +params_phys-$(CONFIG_ARCH_MX3) := 0x80000100 +initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000 diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c new file mode 100644 index 00000000000..69d1322add3 --- /dev/null +++ b/arch/arm/mach-imx/cache-l2x0.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Sascha Hauer <s.hauer@pengutronix.de> + * Juergen Beisert <j.beisert@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/err.h> +#include <linux/kernel.h> + +#include <asm/hardware/cache-l2x0.h> + +#include <mach/hardware.h> + +static int mxc_init_l2x0(void) +{ + void __iomem *l2x0_base; + void __iomem *clkctl_base; + + if (!cpu_is_mx31() && !cpu_is_mx35()) + return 0; + +/* + * First of all, we must repair broken chip settings. There are some + * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These + * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. + * Workaraound is to setup the correct register setting prior enabling the + * L2 cache. This should not hurt already working CPUs, as they are using the + * same value. + */ +#define L2_MEM_VAL 0x10 + + clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); + if (clkctl_base != NULL) { + writel(0x00000515, clkctl_base + L2_MEM_VAL); + iounmap(clkctl_base); + } else { + pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); + } + + l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); + if (IS_ERR(l2x0_base)) { + printk(KERN_ERR "remapping L2 cache area failed with %ld\n", + PTR_ERR(l2x0_base)); + return 0; + } + + l2x0_init(l2x0_base, 0x00030024, 0x00000000); + + return 0; +} +arch_initcall(mxc_init_l2x0); diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c index d423cac8cab..25f343fca2b 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-imx/clock-imx31.c @@ -32,7 +32,7 @@ #include <mach/mx31.h> #include <mach/common.h> -#include "crm_regs.h" +#include "crmregs-imx31.h" #define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ @@ -627,4 +627,3 @@ int __init mx31_clocks_init(unsigned long fref) return 0; } - diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c index 448a038cd1e..5a4cc1ea405 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-imx/clock-imx35.c @@ -547,4 +547,3 @@ int __init mx35_clocks_init() return 0; } - diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-imx/cpu-imx31.c index d1d339576fd..a3780700a88 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-imx/cpu-imx31.c @@ -1,5 +1,5 @@ /* - * MX3 CPU type detection + * MX31 CPU type detection * * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> * @@ -17,14 +17,12 @@ unsigned int mx31_cpu_rev; EXPORT_SYMBOL(mx31_cpu_rev); -struct mx3_cpu_type { +static struct { u8 srev; const char *name; const char *v; unsigned int rev; -}; - -static struct mx3_cpu_type mx31_cpu_type[] __initdata = { +} mx31_cpu_type[] __initdata = { { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, @@ -57,33 +55,3 @@ void __init mx31_read_cpu_rev(void) printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); } - -unsigned int mx35_cpu_rev; -EXPORT_SYMBOL(mx35_cpu_rev); - -void __init mx35_read_cpu_rev(void) -{ - u32 rev; - char *srev; - - rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); - switch (rev) { - case 0x00: - mx35_cpu_rev = IMX_CHIP_REVISION_1_0; - srev = "1.0"; - break; - case 0x10: - mx35_cpu_rev = IMX_CHIP_REVISION_2_0; - srev = "2.0"; - break; - case 0x11: - mx35_cpu_rev = IMX_CHIP_REVISION_2_1; - srev = "2.1"; - break; - default: - mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; - srev = "unknown"; - } - - printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); -} diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c new file mode 100644 index 00000000000..6637cd819ec --- /dev/null +++ b/arch/arm/mach-imx/cpu-imx35.c @@ -0,0 +1,44 @@ +/* + * MX35 CPU type detection + * + * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/module.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include <mach/iim.h> + +unsigned int mx35_cpu_rev; +EXPORT_SYMBOL(mx35_cpu_rev); + +void __init mx35_read_cpu_rev(void) +{ + u32 rev; + char *srev; + + rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); + switch (rev) { + case 0x00: + mx35_cpu_rev = IMX_CHIP_REVISION_1_0; + srev = "1.0"; + break; + case 0x10: + mx35_cpu_rev = IMX_CHIP_REVISION_2_0; + srev = "2.0"; + break; + case 0x11: + mx35_cpu_rev = IMX_CHIP_REVISION_2_1; + srev = "2.1"; + break; + default: + mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; + srev = "unknown"; + } + + printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); +} diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-imx/crmregs-imx31.h index 37a8a07beda..37a8a07beda 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-imx/crmregs-imx31.h diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h index da593657ff3..3aad1e70de9 100644 --- a/arch/arm/mach-imx/devices-imx1.h +++ b/arch/arm/mach-imx/devices-imx1.h @@ -9,21 +9,21 @@ #include <mach/mx1.h> #include <mach/devices-common.h> -extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst; +extern const struct imx_imx_fb_data imx1_imx_fb_data; #define imx1_add_imx_fb(pdata) \ imx_add_imx_fb(&imx1_imx_fb_data, pdata) -extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; +extern const struct imx_imx_i2c_data imx1_imx_i2c_data; #define imx1_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) -extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[]; #define imx1_add_imx_uart(id, pdata) \ imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) #define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) #define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) -extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst; +extern const struct imx_spi_imx_data imx1_cspi_data[]; #define imx1_add_cspi(id, pdata) \ imx_add_spi_imx(&imx1_cspi_data[id], pdata) diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 16744d2d9b8..2628e0c474d 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -9,31 +9,31 @@ #include <mach/mx21.h> #include <mach/devices-common.h> -extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst; +extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data; #define imx21_add_imx21_hcd(pdata) \ imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) -extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst; +extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; #define imx21_add_imx2_wdt(pdata) \ imx_add_imx2_wdt(&imx21_imx2_wdt_data) -extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst; +extern const struct imx_imx_fb_data imx21_imx_fb_data; #define imx21_add_imx_fb(pdata) \ imx_add_imx_fb(&imx21_imx_fb_data, pdata) -extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; +extern const struct imx_imx_i2c_data imx21_imx_i2c_data; #define imx21_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) -extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst; +extern const struct imx_imx_keypad_data imx21_imx_keypad_data; #define imx21_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) -extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; +extern const struct imx_imx_ssi_data imx21_imx_ssi_data[]; #define imx21_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) -extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[]; #define imx21_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) #define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) @@ -41,19 +41,19 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; #define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) #define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) -extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst; +extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[]; #define imx21_add_mxc_mmc(id, pdata) \ imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) -extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; +extern const struct imx_mxc_nand_data imx21_mxc_nand_data; #define imx21_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) -extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst; +extern const struct imx_mxc_w1_data imx21_mxc_w1_data; #define imx21_add_mxc_w1(pdata) \ imx_add_mxc_w1(&imx21_mxc_w1_data) -extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; +extern const struct imx_spi_imx_data imx21_cspi_data[]; #define imx21_add_cspi(id, pdata) \ imx_add_spi_imx(&imx21_cspi_data[id], pdata) #define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index b591d72f603..efa0761c508 100644 --- a/arch/arm/mach-imx/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h @@ -9,48 +9,48 @@ #include <mach/mx25.h> #include <mach/devices-common.h> -extern const struct imx_fec_data imx25_fec_data __initconst; +extern const struct imx_fec_data imx25_fec_data; #define imx25_add_fec(pdata) \ imx_add_fec(&imx25_fec_data, pdata) -extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst; +extern const struct imx_flexcan_data imx25_flexcan_data[]; #define imx25_add_flexcan(id, pdata) \ imx_add_flexcan(&imx25_flexcan_data[id], pdata) #define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata) #define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata) -extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst; +extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data; #define imx25_add_fsl_usb2_udc(pdata) \ imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) -extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst; +extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; #define imx25_add_imxdi_rtc(pdata) \ imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) -extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst; +extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; #define imx25_add_imx2_wdt(pdata) \ imx_add_imx2_wdt(&imx25_imx2_wdt_data) -extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst; +extern const struct imx_imx_fb_data imx25_imx_fb_data; #define imx25_add_imx_fb(pdata) \ imx_add_imx_fb(&imx25_imx_fb_data, pdata) -extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx25_imx_i2c_data[]; #define imx25_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) #define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) #define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) #define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) -extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst; +extern const struct imx_imx_keypad_data imx25_imx_keypad_data; #define imx25_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) -extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; +extern const struct imx_imx_ssi_data imx25_imx_ssi_data[]; #define imx25_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) -extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[]; #define imx25_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) #define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) @@ -59,33 +59,32 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; #define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) #define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) -extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst; +extern const struct imx_mx2_camera_data imx25_mx2_camera_data; #define imx25_add_mx2_camera(pdata) \ imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst; +extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data; #define imx25_add_mxc_ehci_otg(pdata) \ imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst; +extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data; #define imx25_add_mxc_ehci_hs(pdata) \ imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) -extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; +extern const struct imx_mxc_nand_data imx25_mxc_nand_data; #define imx25_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) -extern const struct imx_sdhci_esdhc_imx_data -imx25_sdhci_esdhc_imx_data[] __initconst; +extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[]; #define imx25_add_sdhci_esdhc_imx(id, pdata) \ imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) -extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; +extern const struct imx_spi_imx_data imx25_cspi_data[]; #define imx25_add_spi_imx(id, pdata) \ imx_add_spi_imx(&imx25_cspi_data[id], pdata) #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) -extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst; +extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[]; #define imx25_add_mxc_pwm(id) \ imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index f1272d4b5a3..7f97a3cdd41 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -9,35 +9,35 @@ #include <mach/mx27.h> #include <mach/devices-common.h> -extern const struct imx_fec_data imx27_fec_data __initconst; +extern const struct imx_fec_data imx27_fec_data; #define imx27_add_fec(pdata) \ imx_add_fec(&imx27_fec_data, pdata) -extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst; +extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; #define imx27_add_fsl_usb2_udc(pdata) \ imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) -extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst; +extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; #define imx27_add_imx2_wdt(pdata) \ imx_add_imx2_wdt(&imx27_imx2_wdt_data) -extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst; +extern const struct imx_imx_fb_data imx27_imx_fb_data; #define imx27_add_imx_fb(pdata) \ imx_add_imx_fb(&imx27_imx_fb_data, pdata) -extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx27_imx_i2c_data[]; #define imx27_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) -extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst; +extern const struct imx_imx_keypad_data imx27_imx_keypad_data; #define imx27_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) -extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; +extern const struct imx_imx_ssi_data imx27_imx_ssi_data[]; #define imx27_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) -extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[]; #define imx27_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) #define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) @@ -47,30 +47,30 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; #define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) #define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) -extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst; +extern const struct imx_mx2_camera_data imx27_mx2_camera_data; #define imx27_add_mx2_camera(pdata) \ imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst; +extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; #define imx27_add_mxc_ehci_otg(pdata) \ imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst; +extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[]; #define imx27_add_mxc_ehci_hs(id, pdata) \ imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) -extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst; +extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[]; #define imx27_add_mxc_mmc(id, pdata) \ imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) -extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; +extern const struct imx_mxc_nand_data imx27_mxc_nand_data; #define imx27_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) -extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst; +extern const struct imx_mxc_w1_data imx27_mxc_w1_data; #define imx27_add_mxc_w1(pdata) \ imx_add_mxc_w1(&imx27_mxc_w1_data) -extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; +extern const struct imx_spi_imx_data imx27_cspi_data[]; #define imx27_add_cspi(id, pdata) \ imx_add_spi_imx(&imx27_cspi_data[id], pdata) #define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index 40f4e848a67..dbe940d9c53 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h @@ -9,30 +9,30 @@ #include <mach/mx31.h> #include <mach/devices-common.h> -extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst; +extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data; #define imx31_add_fsl_usb2_udc(pdata) \ imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) -extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst; +extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; #define imx31_add_imx2_wdt(pdata) \ imx_add_imx2_wdt(&imx31_imx2_wdt_data) -extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; #define imx31_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) #define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) #define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) #define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) -extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst; +extern const struct imx_imx_keypad_data imx31_imx_keypad_data; #define imx31_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) -extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; +extern const struct imx_imx_ssi_data imx31_imx_ssi_data[]; #define imx31_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) -extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[]; #define imx31_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) #define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) @@ -41,26 +41,38 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; #define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst; +extern const struct imx_ipu_core_data imx31_ipu_core_data; +#define imx31_add_ipu_core(pdata) \ + imx_add_ipu_core(&imx31_ipu_core_data, pdata) +#define imx31_alloc_mx3_camera(pdata) \ + imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata) +#define imx31_add_mx3_sdc_fb(pdata) \ + imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata) + +extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data; #define imx31_add_mxc_ehci_otg(pdata) \ imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst; +extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[]; #define imx31_add_mxc_ehci_hs(id, pdata) \ imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) -extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst; +extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[]; #define imx31_add_mxc_mmc(id, pdata) \ imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) -extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; +extern const struct imx_mxc_nand_data imx31_mxc_nand_data; #define imx31_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) -extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst; +extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; +#define imx31_add_mxc_rtc(pdata) \ + imx_add_mxc_rtc(&imx31_mxc_rtc_data) + +extern const struct imx_mxc_w1_data imx31_mxc_w1_data; #define imx31_add_mxc_w1(pdata) \ imx_add_mxc_w1(&imx31_mxc_w1_data) -extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; +extern const struct imx_spi_imx_data imx31_cspi_data[]; #define imx31_add_cspi(id, pdata) \ imx_add_spi_imx(&imx31_cspi_data[id], pdata) #define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h index d545d86cc20..234cbd3c18a 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-imx/devices-imx35.h @@ -9,67 +9,74 @@ #include <mach/mx35.h> #include <mach/devices-common.h> -extern const struct imx_fec_data imx35_fec_data __initconst; +extern const struct imx_fec_data imx35_fec_data; #define imx35_add_fec(pdata) \ imx_add_fec(&imx35_fec_data, pdata) -extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst; +extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data; #define imx35_add_fsl_usb2_udc(pdata) \ imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) -extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst; +extern const struct imx_flexcan_data imx35_flexcan_data[]; #define imx35_add_flexcan(id, pdata) \ imx_add_flexcan(&imx35_flexcan_data[id], pdata) #define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata) #define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) -extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst; +extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; #define imx35_add_imx2_wdt(pdata) \ imx_add_imx2_wdt(&imx35_imx2_wdt_data) -extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; #define imx35_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) #define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) #define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) #define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) -extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; +extern const struct imx_imx_keypad_data imx35_imx_keypad_data; #define imx35_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) -extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; +extern const struct imx_imx_ssi_data imx35_imx_ssi_data[]; #define imx35_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) -extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[]; #define imx35_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) #define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) #define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst; +extern const struct imx_ipu_core_data imx35_ipu_core_data; +#define imx35_add_ipu_core(pdata) \ + imx_add_ipu_core(&imx35_ipu_core_data, pdata) +#define imx35_alloc_mx3_camera(pdata) \ + imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata) +#define imx35_add_mx3_sdc_fb(pdata) \ + imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata) + +extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data; #define imx35_add_mxc_ehci_otg(pdata) \ imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst; +extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data; #define imx35_add_mxc_ehci_hs(pdata) \ imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) -extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; +extern const struct imx_mxc_nand_data imx35_mxc_nand_data; #define imx35_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) -extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst; +extern const struct imx_mxc_w1_data imx35_mxc_w1_data; #define imx35_add_mxc_w1(pdata) \ imx_add_mxc_w1(&imx35_mxc_w1_data) -extern const struct imx_sdhci_esdhc_imx_data -imx35_sdhci_esdhc_imx_data[] __initconst; +extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; #define imx35_add_sdhci_esdhc_imx(id, pdata) \ imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) -extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; +extern const struct imx_spi_imx_data imx35_cspi_data[]; #define imx35_add_cspi(id, pdata) \ imx_add_spi_imx(&imx35_cspi_data[id], pdata) #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c index 314a983ac61..faad0f15ac7 100644 --- a/arch/arm/mach-mx3/ehci-imx31.c +++ b/arch/arm/mach-imx/ehci-imx31.c @@ -80,4 +80,3 @@ int mx31_initialize_usb_hw(int port, unsigned int flags) return 0; } - diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c index 33983a478c6..001ec3971f5 100644 --- a/arch/arm/mach-mx3/ehci-imx35.c +++ b/arch/arm/mach-imx/ehci-imx35.c @@ -77,4 +77,3 @@ int mx35_initialize_usb_hw(int port, unsigned int flags) return 0; } - diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index fa5288018ba..5911281da5f 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -32,7 +32,6 @@ #include <mach/common.h> #include <mach/iomux-mx27.h> #include <mach/hardware.h> -#include <mach/spi.h> #include <mach/audmux.h> #include "devices-imx27.h" diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index cb705c28de0..f9ef04acdab 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -22,7 +22,6 @@ #include <linux/gpio.h> #include <linux/leds.h> #include <linux/platform_device.h> -#include <linux/gpio_keys.h> #include <linux/input.h> #include <video/platform_lcd.h> @@ -32,7 +31,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/mx25.h> -#include <mach/imx-uart.h> #include <mach/audmux.h> #include "devices-imx25.h" @@ -207,23 +205,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { }, }; -static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { +static const struct gpio_keys_platform_data + eukrea_mbimxsd_button_data __initconst = { .buttons = eukrea_mbimxsd_gpio_buttons, .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), }; -static struct platform_device eukrea_mbimxsd_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &eukrea_mbimxsd_button_data, - } -}; - static struct platform_device *platform_devices[] __initdata = { &eukrea_mbimxsd_leds_gpio, - &eukrea_mbimxsd_button_device, &eukrea_mbimxsd_lcd_powerdev, }; @@ -242,6 +231,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; +static struct esdhc_platform_data sd1_pdata = { + .cd_gpio = GPIO_SD1CD, + .wp_gpio = -EINVAL, +}; + /* * system init for baseboard usage. Will be called by cpuimx25 init. * @@ -275,7 +269,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void) imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx25_add_flexcan1(NULL); - imx25_add_sdhci_esdhc_imx(0, NULL); + imx25_add_sdhci_esdhc_imx(0, &sd1_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); @@ -293,4 +287,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void) ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx_add_gpio_keys(&eukrea_mbimxsd_button_data); } diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c index 80761474c0f..4909ea05855 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c @@ -26,7 +26,6 @@ #include <linux/interrupt.h> #include <linux/leds.h> #include <linux/platform_device.h> -#include <linux/gpio_keys.h> #include <linux/input.h> #include <video/platform_lcd.h> #include <linux/i2c.h> @@ -38,14 +37,10 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx35.h> -#include <mach/ipu.h> -#include <mach/mx3fb.h> #include <mach/audmux.h> #include "devices-imx35.h" -#include "devices.h" static const struct fb_videomode fb_modedb[] = { { @@ -100,12 +95,11 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static struct ipu_platform_data mx3_ipu_data = { +static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, +static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "CMO-QVGA", .mode = fb_modedb, .num_modes = ARRAY_SIZE(fb_modedb), @@ -163,11 +157,14 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { MX35_PAD_SD1_DATA1__ESDHC1_DAT1, MX35_PAD_SD1_DATA2__ESDHC1_DAT2, MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD1 CD */ + MX35_PAD_LD18__GPIO3_24, }; #define GPIO_LED1 IMX_GPIO_NR(3, 29) #define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) -#define GPIO_LCDPWR (4) +#define GPIO_LCDPWR IMX_GPIO_NR(1, 4) +#define GPIO_SD1CD IMX_GPIO_NR(3, 24) static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) @@ -219,23 +216,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { }, }; -static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { +static const struct gpio_keys_platform_data + eukrea_mbimxsd_button_data __initconst = { .buttons = eukrea_mbimxsd_gpio_buttons, .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), }; -static struct platform_device eukrea_mbimxsd_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &eukrea_mbimxsd_button_data, - } -}; - static struct platform_device *platform_devices[] __initdata = { &eukrea_mbimxsd_leds_gpio, - &eukrea_mbimxsd_button_device, &eukrea_mbimxsd_lcd_powerdev, }; @@ -254,6 +242,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; +static struct esdhc_platform_data sd1_pdata = { + .cd_gpio = GPIO_SD1CD, + .wp_gpio = -EINVAL, +}; + /* * system init for baseboard usage. Will be called by cpuimx35 init. * @@ -283,13 +276,13 @@ void __init eukrea_mbimxsd35_baseboard_init(void) #endif imx35_add_imx_uart1(&uart_pdata); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); + imx35_add_ipu_core(&mx3_ipu_data); + imx35_add_mx3_sdc_fb(&mx3fb_pdata); imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx35_add_flexcan1(NULL); - imx35_add_sdhci_esdhc_imx(0, NULL); + imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); @@ -301,10 +294,10 @@ void __init eukrea_mbimxsd35_baseboard_init(void) gpio_request(GPIO_LCDPWR, "LCDPWR"); gpio_direction_output(GPIO_LCDPWR, 1); - gpio_free(GPIO_LCDPWR); i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx_add_gpio_keys(&eukrea_mbimxsd_button_data); } diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c index cf8f8099ebd..cf8f8099ebd 100644 --- a/arch/arm/mach-mx3/iomux-imx31.c +++ b/arch/arm/mach-imx/iomux-imx31.c diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c new file mode 100644 index 00000000000..15e45c84e37 --- /dev/null +++ b/arch/arm/mach-imx/mach-apf9328.c @@ -0,0 +1,144 @@ +/* + * linux/arch/arm/mach-imx/mach-apf9328.c + * + * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com> + * + * This work is based on mach-scb9328.c which is: + * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> + * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/dm9000.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/irqs.h> +#include <mach/iomux-mx1.h> + +#include "devices-imx1.h" + +static const int apf9328_pins[] __initconst = { + /* UART1 */ + PC9_PF_UART1_CTS, + PC10_PF_UART1_RTS, + PC11_PF_UART1_TXD, + PC12_PF_UART1_RXD, + /* UART2 */ + PB28_PF_UART2_CTS, + PB29_PF_UART2_RTS, + PB30_PF_UART2_TXD, + PB31_PF_UART2_RXD, +}; + +/* + * The APF9328 can have up to 32MB NOR Flash + */ +static struct resource flash_resource = { + .start = MX1_CS0_PHYS, + .end = MX1_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct physmap_flash_data apf9328_flash_data = { + .width = 2, +}; + +static struct platform_device apf9328_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &apf9328_flash_data, + }, + .resource = &flash_resource, + .num_resources = 1, +}; + +/* + * APF9328 has a DM9000 Ethernet controller + */ +static struct dm9000_plat_data dm9000_setup = { + .flags = DM9000_PLATF_16BITONLY +}; + +static struct resource dm9000_resources[] = { + { + .start = MX1_CS4_PHYS + 0x00C00000, + .end = MX1_CS4_PHYS + 0x00C00001, + .flags = IORESOURCE_MEM, + }, { + .start = MX1_CS4_PHYS + 0x00C00002, + .end = MX1_CS4_PHYS + 0x00C00003, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_GPIOB(14), + .end = IRQ_GPIOB(14), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct platform_device dm9000x_device = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(dm9000_resources), + .resource = dm9000_resources, + .dev = { + .platform_data = &dm9000_setup, + } +}; + +/* --- SERIAL RESSOURCE --- */ +static const struct imxuart_platform_data uart0_pdata __initconst = { + .flags = 0, +}; + +static const struct imxuart_platform_data uart1_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct platform_device *devices[] __initdata = { + &apf9328_flash_device, + &dm9000x_device, +}; + +static void __init apf9328_init(void) +{ + mxc_gpio_setup_multiple_pins(apf9328_pins, + ARRAY_SIZE(apf9328_pins), + "APF9328"); + + imx1_add_imx_uart0(&uart0_pdata); + imx1_add_imx_uart1(&uart1_pdata); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init apf9328_timer_init(void) +{ + mx1_clocks_init(32768); +} + +static struct sys_timer apf9328_timer = { + .init = apf9328_timer_init, +}; + +MACHINE_START(APF9328, "Armadeus APF9328") + /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */ + .map_io = mx1_map_io, + .init_early = imx1_init_early, + .init_irq = mx1_init_irq, + .timer = &apf9328_timer, + .init_machine = apf9328_init, +MACHINE_END diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 226829bf7c2..ffb40ff619b 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -34,7 +34,6 @@ #include <linux/mtd/physmap.h> #include <linux/io.h> #include <linux/input.h> -#include <linux/gpio_keys.h> #include <linux/i2c.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -49,13 +48,10 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> -#include <mach/ipu.h> -#include <mach/mx3fb.h> #include <mach/ulpi.h> #include "devices-imx31.h" -#include "devices.h" -#include "crm_regs.h" +#include "crmregs-imx31.h" static int armadillo5x0_pins[] = { /* UART1 */ @@ -280,20 +276,12 @@ static struct gpio_keys_button armadillo5x0_buttons[] = { } }; -static struct gpio_keys_platform_data armadillo5x0_button_data = { +static const struct gpio_keys_platform_data + armadillo5x0_button_data __initconst = { .buttons = armadillo5x0_buttons, .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), }; -static struct platform_device armadillo5x0_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &armadillo5x0_button_data, - } -}; - /* * NAND Flash */ @@ -383,12 +371,11 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static struct ipu_platform_data mx3_ipu_data = { +static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, +static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "CRT-VGA", .mode = fb_modedb, .num_modes = ARRAY_SIZE(fb_modedb), @@ -496,7 +483,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = { static struct platform_device *devices[] __initdata = { &armadillo5x0_smc911x_device, - &armadillo5x0_button_device, }; /* @@ -508,6 +494,7 @@ static void __init armadillo5x0_init(void) ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); platform_add_devices(devices, ARRAY_SIZE(devices)); + imx_add_gpio_keys(&armadillo5x0_button_data); imx31_add_imx_i2c1(NULL); /* Register UART */ @@ -521,8 +508,8 @@ static void __init armadillo5x0_init(void) imx31_add_mxc_mmc(0, &sdhc_pdata); /* Register FB */ - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); + imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* Register NOR Flash */ mxc_register_device(&armadillo5x0_nor_flash, diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-imx/mach-bug.c index d137d7078ee..42e4f078a19 100644 --- a/arch/arm/mach-mx3/mach-bug.c +++ b/arch/arm/mach-imx/mach-bug.c @@ -20,7 +20,6 @@ #include <linux/platform_device.h> #include <mach/iomux-mx3.h> -#include <mach/imx-uart.h> #include <mach/hardware.h> #include <mach/common.h> diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 759299bb035..46a2e41d43d 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -38,7 +38,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx27.h> -#include <mach/mxc_nand.h> #include <mach/ulpi.h> #include "devices-imx27.h" diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index ec63d998f64..3f8ef825fa6 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c @@ -41,10 +41,8 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-mx35.h> -#include <mach/mxc_nand.h> #include "devices-imx35.h" -#include "devices.h" static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index 9da8d18eeb0..148cff2819b 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -36,8 +36,6 @@ #include <asm/mach/map.h> #include <mach/common.h> #include <mach/mx25.h> -#include <mach/mxc_nand.h> -#include <mach/imxfb.h> #include <mach/iomux-mx25.h> #include "devices-imx25.h" diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index d7e0d219726..7ae43b1ec51 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -27,7 +27,6 @@ #include <linux/mtd/physmap.h> #include <linux/i2c.h> #include <linux/i2c/pca953x.h> -#include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> #include <linux/delay.h> @@ -130,19 +129,12 @@ static struct gpio_keys_button visstrim_gpio_keys[] = { } }; -static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = { +static const struct gpio_keys_platform_data + visstrim_gpio_keys_platform_data __initconst = { .buttons = visstrim_gpio_keys, .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), }; -static struct platform_device visstrim_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &visstrim_gpio_keys_platform_data, - }, -}; - /* Visstrim_SM10 has a microSD slot connected to sdhc1 */ static int visstrim_m10_sdhc1_init(struct device *dev, irq_handler_t detect_irq, void *data) @@ -186,7 +178,6 @@ static struct platform_device visstrim_m10_nor_mtd_device = { }; static struct platform_device *platform_devices[] __initdata = { - &visstrim_gpio_keys_device, &visstrim_m10_nor_mtd_device, }; @@ -255,6 +246,7 @@ static void __init visstrim_m10_board_init(void) imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); imx27_add_fec(NULL); + imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c index d35621d62b4..1ecae20cf4e 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -39,7 +39,6 @@ #include <mach/iomux-mx3.h> #include "devices-imx31.h" -#include "devices.h" #define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 47cf56ac6d5..38ec5cbbda9 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -25,7 +25,6 @@ #include <mach/common.h> #include <mach/hardware.h> -#include <mach/i2c.h> #include <mach/iomux-mx1.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index fa52a1086ea..74ac88978dd 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -25,7 +25,6 @@ #include <asm/mach/time.h> #include <asm/mach/map.h> #include <mach/iomux-mx21.h> -#include <mach/mxc_nand.h> #include "devices-imx21.h" diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index 06da438282a..58ea3fdf091 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -29,7 +29,6 @@ #include <linux/irq.h> #include <linux/gpio.h> #include <linux/platform_device.h> -#include <linux/input/matrix_keypad.h> #include <linux/usb/otg.h> #include <mach/hardware.h> @@ -103,6 +102,8 @@ static iomux_v3_cfg_t mx25pdk_pads[] = { MX25_PAD_SD1_DATA1__SD1_DATA1, MX25_PAD_SD1_DATA2__SD1_DATA2, MX25_PAD_SD1_DATA3__SD1_DATA3, + MX25_PAD_A14__GPIO_2_0, /* WriteProtect */ + MX25_PAD_A15__GPIO_2_1, /* CardDetect */ /* I2C1 */ MX25_PAD_I2C1_CLK__I2C1_CLK, @@ -208,6 +209,14 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = { .bitrate = 100000, }; +#define SD1_GPIO_WP IMX_GPIO_NR(2, 0) +#define SD1_GPIO_CD IMX_GPIO_NR(2, 1) + +static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = { + .wp_gpio = SD1_GPIO_WP, + .cd_gpio = SD1_GPIO_CD, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, @@ -225,7 +234,7 @@ static void __init mx25pdk_init(void) imx25_add_fec(&mx25_fec_pdata); imx25_add_imx_keypad(&mx25pdk_keymap_data); - imx25_add_sdhci_esdhc_imx(0, NULL); + imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata); imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); } diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 367d1e4384c..1db79506f5e 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -29,7 +29,6 @@ #include <asm/mach/map.h> #include <mach/gpio.h> #include <mach/iomux-mx27.h> -#include <mach/mxc_nand.h> #include "devices-imx27.h" diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 034be624d35..9b982449cb5 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -39,13 +39,8 @@ #include <mach/iomux-mx3.h> #include <mach/3ds_debugboard.h> #include <mach/ulpi.h> -#include <mach/mmc.h> -#include <mach/ipu.h> -#include <mach/mx3fb.h> -#include <mach/mx3_camera.h> #include "devices-imx31.h" -#include "devices.h" /* CPLD IRQ line for external uart, external ethernet etc */ #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) @@ -178,22 +173,37 @@ static struct gpio mx31_3ds_camera_gpios[] = { { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, }; -static int __init mx31_3ds_camera_alloc_dma(void) +static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = { + .flags = MX3_CAMERA_DATAWIDTH_10, + .mclk_10khz = 2600, +}; + +static int __init mx31_3ds_init_camera(void) { - int dma; + int dma, ret = -ENOMEM; + struct platform_device *pdev = + imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); + + if (IS_ERR(pdev)) + return PTR_ERR(pdev); if (!mx3_camera_base) - return -ENOMEM; + goto err; - dma = dma_declare_coherent_memory(&mx3_camera.dev, + dma = dma_declare_coherent_memory(&pdev->dev, mx3_camera_base, mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); if (!(dma & DMA_MEMORY_MAP)) - return -ENOMEM; + goto err; - return 0; + ret = platform_device_add(pdev); + if (ret) +err: + platform_device_put(pdev); + + return ret; } static int mx31_3ds_camera_power(struct device *dev, int on) @@ -241,12 +251,6 @@ static struct platform_device mx31_3ds_ov2640 = { }, }; -struct mx3_camera_pdata mx31_3ds_camera_pdata = { - .dma_dev = &mx3_ipu.dev, - .flags = MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 2600, -}; - /* * FB support */ @@ -273,8 +277,7 @@ static struct ipu_platform_data mx3_ipu_data = { .irq_base = MXC_IPU_IRQ_START, }; -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, +static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "Epson-VGA", .mode = fb_modedb, .num_modes = ARRAY_SIZE(fb_modedb), @@ -723,8 +726,8 @@ static void __init mx31_3ds_init(void) imx31_add_mxc_mmc(0, &sdhc1_pdata); imx31_add_spi_imx0(&spi0_pdata); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); + imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* CSI */ /* Camera power: default - off */ @@ -735,10 +738,7 @@ static void __init mx31_3ds_init(void) iclink_ov2640.power = NULL; } - if (!mx31_3ds_camera_alloc_dma()) - mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata); - else - pr_err("Failed to allocate dma memory for camera"); + mx31_3ds_init_camera(); } static void __init mx31_3ds_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c index 4e4b780c481..f4dee025463 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-imx/mach-mx31ads.c @@ -38,7 +38,6 @@ #endif #include "devices-imx31.h" -#include "devices.h" /* PBC Board interrupt status register */ #define PBC_INTSTATUS 0x000016 @@ -199,12 +198,11 @@ static void __init mx31ads_init_expio(void) __raw_writew(0xFFFF, PBC_INTSTATUS_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); + irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); + irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); } #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c index ed95745163b..410e676ae08 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-imx/mach-mx31lilly.c @@ -46,7 +46,6 @@ #include <mach/ulpi.h> #include "devices-imx31.h" -#include "devices.h" /* * This file contains module-specific initialization routines for LILLY-1131. diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index 24a21a384bf..ac9b4cad320 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -44,7 +44,6 @@ #include <mach/ulpi.h> #include "devices-imx31.h" -#include "devices.h" /* * This file contains the module-specific initialization routines. diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index 3a021b01161..eaa51e49ca9 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -27,6 +27,7 @@ #include <linux/mfd/mc13783.h> #include <linux/spi/spi.h> #include <linux/types.h> +#include <linux/memblock.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -39,13 +40,9 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx3.h> -#include <mach/ipu.h> -#include <mach/mx3_camera.h> -#include <mach/spi.h> #include <mach/ulpi.h> #include "devices-imx31.h" -#include "devices.h" static unsigned int moboard_pins[] = { /* UART0 */ @@ -102,7 +99,7 @@ static unsigned int moboard_pins[] = { }; static struct physmap_flash_data mx31moboard_flash_data = { - .width = 2, + .width = 2, }; static struct resource mx31moboard_flash_resource = { @@ -194,8 +191,8 @@ static struct regulator_init_data sdhc_vreg_data = { static struct regulator_consumer_supply cam_consumers[] = { { - .dev = &mx3_camera.dev, - .supply = "cam_vcc", + .dev_name = "mx3_camera.0", + .supply = "cam_vcc", }, }; @@ -430,9 +427,9 @@ static int __init moboard_usbh2_init(void) static struct gpio_led mx31moboard_leds[] = { { - .name = "coreboard-led-0:red:running", + .name = "coreboard-led-0:red:running", .default_trigger = "heartbeat", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), + .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), }, { .name = "coreboard-led-1:red", .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), @@ -446,7 +443,7 @@ static struct gpio_led mx31moboard_leds[] = { }; static struct gpio_led_platform_data mx31moboard_led_pdata = { - .num_leds = ARRAY_SIZE(mx31moboard_leds), + .num_leds = ARRAY_SIZE(mx31moboard_leds), .leds = mx31moboard_leds, }; @@ -458,7 +455,7 @@ static struct platform_device mx31moboard_leds_device = { }, }; -static struct ipu_platform_data mx3_ipu_data = { +static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; @@ -467,37 +464,39 @@ static struct platform_device *devices[] __initdata = { &mx31moboard_leds_device, }; -static struct mx3_camera_pdata camera_pdata = { - .dma_dev = &mx3_ipu.dev, +static struct mx3_camera_pdata camera_pdata __initdata = { .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, .mclk_10khz = 4800, }; -#define CAMERA_BUF_SIZE (4*1024*1024) +static phys_addr_t mx3_camera_base __initdata; +#define MX3_CAMERA_BUF_SIZE SZ_4M -static int __init mx31moboard_cam_alloc_dma(const size_t buf_size) +static int __init mx31moboard_init_cam(void) { - dma_addr_t dma_handle; - void *buf; - int dma; - - if (buf_size < 2 * 1024 * 1024) - return -EINVAL; + int dma, ret = -ENOMEM; + struct platform_device *pdev; - buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); - if (!buf) { - pr_err("%s: cannot allocate camera buffer-memory\n", __func__); - return -ENOMEM; - } + imx31_add_ipu_core(&mx3_ipu_data); - memset(buf, 0, buf_size); + pdev = imx31_alloc_mx3_camera(&camera_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); - dma = dma_declare_coherent_memory(&mx3_camera.dev, - dma_handle, dma_handle, buf_size, + dma = dma_declare_coherent_memory(&pdev->dev, + mx3_camera_base, mx3_camera_base, + MX3_CAMERA_BUF_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); + if (!(dma & DMA_MEMORY_MAP)) + goto err; + + ret = platform_device_add(pdev); + if (ret) +err: + platform_device_put(pdev); + + return ret; - /* The way we call dma_declare_coherent_memory only a malloc can fail */ - return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM; } static int mx31moboard_baseboard; @@ -529,9 +528,7 @@ static void __init mx31moboard_init(void) imx31_add_mxc_mmc(0, &sdhc1_pdata); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) - mxc_register_device(&mx3_camera, &camera_pdata); + mx31moboard_init_cam(); usb_xcvr_reset(); @@ -565,9 +562,19 @@ struct sys_timer mx31moboard_timer = { .init = mx31moboard_timer_init, }; +static void __init mx31moboard_reserve(void) +{ + /* reserve 4 MiB for mx3-camera */ + mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE, + MX3_CAMERA_BUF_SIZE); + memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE); + memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE); +} + MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ .boot_params = MX3x_PHYS_OFFSET + 0x100, + .reserve = mx31moboard_reserve, .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index ff5fe231b8d..882880ac1bb 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c @@ -42,7 +42,6 @@ #include <mach/3ds_debugboard.h> #include "devices-imx35.h" -#include "devices.h" #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1) diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index 69787c30c32..2774541511e 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -29,7 +29,6 @@ #include <asm/mach/map.h> #include <linux/gpio.h> #include <mach/iomux-mx27.h> -#include <mach/mxc_nand.h> #include <linux/i2c/pca953x.h> #include "devices-imx27.h" diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 63e18255677..bbddc5a11c4 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -37,7 +37,6 @@ #include <mach/iomux-mx27.h> #include <asm/mach/time.h> #include <mach/audmux.h> -#include <mach/mxc_nand.h> #include <mach/irqs.h> #include <mach/ulpi.h> diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index f07d3bded67..89c213b8129 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -31,6 +31,7 @@ #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> #include <linux/gfp.h> +#include <linux/memblock.h> #include <media/soc_camera.h> @@ -41,13 +42,9 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx3.h> -#include <mach/ipu.h> -#include <mach/mx3_camera.h> -#include <mach/mx3fb.h> #include <mach/ulpi.h> #include "devices-imx31.h" -#include "devices.h" #include "pcm037.h" static enum pcm037_board_variant pcm037_instance = PCM037_PCM970; @@ -404,35 +401,35 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = { .exit = pcm970_sdhc1_exit, }; -struct mx3_camera_pdata camera_pdata = { - .dma_dev = &mx3_ipu.dev, +struct mx3_camera_pdata camera_pdata __initdata = { .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, .mclk_10khz = 2000, }; -static int __init pcm037_camera_alloc_dma(const size_t buf_size) -{ - dma_addr_t dma_handle; - void *buf; - int dma; - - if (buf_size < 2 * 1024 * 1024) - return -EINVAL; +static phys_addr_t mx3_camera_base __initdata; +#define MX3_CAMERA_BUF_SIZE SZ_4M - buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); - if (!buf) { - pr_err("%s: cannot allocate camera buffer-memory\n", __func__); - return -ENOMEM; - } +static int __init pcm037_init_camera(void) +{ + int dma, ret = -ENOMEM; + struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata); - memset(buf, 0, buf_size); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); - dma = dma_declare_coherent_memory(&mx3_camera.dev, - dma_handle, dma_handle, buf_size, + dma = dma_declare_coherent_memory(&pdev->dev, + mx3_camera_base, mx3_camera_base, + MX3_CAMERA_BUF_SIZE, DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); + if (!(dma & DMA_MEMORY_MAP)) + goto err; + + ret = platform_device_add(pdev); + if (ret) +err: + platform_device_put(pdev); - /* The way we call dma_declare_coherent_memory only a malloc can fail */ - return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM; + return ret; } static struct platform_device *devices[] __initdata = { @@ -442,7 +439,7 @@ static struct platform_device *devices[] __initdata = { &pcm037_mt9v022, }; -static struct ipu_platform_data mx3_ipu_data = { +static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; @@ -500,7 +497,6 @@ static const struct fb_videomode fb_modedb[] = { }; static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, .name = "Sharp-LQ035Q7DH06-QVGA", .mode = fb_modedb, .num_modes = ARRAY_SIZE(fb_modedb), @@ -638,8 +634,8 @@ static void __init pcm037_init(void) imx31_add_mxc_nand(&pcm037_nand_board_info); imx31_add_mxc_mmc(0, &sdhc_pdata); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); + imx31_add_ipu_core(&mx3_ipu_data); + imx31_add_mx3_sdc_fb(&mx3fb_pdata); /* CSI */ /* Camera power: default - off */ @@ -649,8 +645,7 @@ static void __init pcm037_init(void) else iclink_mt9t031.power = NULL; - if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) - mxc_register_device(&mx3_camera, &camera_pdata); + pcm037_init_camera(); platform_device_register(&pcm970_sja1000); @@ -680,9 +675,19 @@ struct sys_timer pcm037_timer = { .init = pcm037_timer_init, }; +static void __init pcm037_reserve(void) +{ + /* reserve 4 MiB for mx3-camera */ + mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE, + MX3_CAMERA_BUF_SIZE); + memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE); + memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE); +} + MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ .boot_params = MX3x_PHYS_OFFSET + 0x100, + .reserve = pcm037_reserve, .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c index df6fb07d037..1b7606bef8f 100644 --- a/arch/arm/mach-mx3/mach-pcm037_eet.c +++ b/arch/arm/mach-imx/mach-pcm037_eet.c @@ -7,19 +7,16 @@ * published by the Free Software Foundation. */ #include <linux/gpio.h> -#include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <mach/common.h> #include <mach/iomux-mx3.h> -#include <mach/spi.h> #include <asm/mach-types.h> #include "pcm037.h" -#include "devices.h" #include "devices-imx31.h" static unsigned int pcm037_eet_pins[] = { @@ -156,20 +153,13 @@ static struct gpio_keys_button pcm037_gpio_keys[] = { }, }; -static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = { +static const struct gpio_keys_platform_data + pcm037_gpio_keys_platform_data __initconst = { .buttons = pcm037_gpio_keys, .nbuttons = ARRAY_SIZE(pcm037_gpio_keys), .rep = 0, /* No auto-repeat */ }; -static struct platform_device pcm037_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &pcm037_gpio_keys_platform_data, - }, -}; - static int __init eet_init_devices(void) { if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET) @@ -182,9 +172,8 @@ static int __init eet_init_devices(void) spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); imx31_add_spi_imx0(&pcm037_spi1_pdata); - platform_device_register(&pcm037_gpio_keys_device); + imx_add_gpio_keys(&pcm037_gpio_keys_platform_data); return 0; } - late_initcall(eet_init_devices); diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 4cbce6d0fef..853bb871c7e 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -36,7 +36,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx27.h> -#include <mach/mxc_nand.h> #include <mach/ulpi.h> #include "devices-imx27.h" diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index b3ecfb22d24..026441628df 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -36,13 +36,10 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-mx35.h> -#include <mach/ipu.h> -#include <mach/mx3fb.h> #include <mach/ulpi.h> #include <mach/audmux.h> #include "devices-imx35.h" -#include "devices.h" static const struct fb_videomode fb_modedb[] = { { @@ -80,12 +77,11 @@ static const struct fb_videomode fb_modedb[] = { }, }; -static struct ipu_platform_data mx3_ipu_data = { +static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, +static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "Sharp-LQ035Q7", .mode = fb_modedb, .num_modes = ARRAY_SIZE(fb_modedb), @@ -126,12 +122,12 @@ static struct at24_platform_data board_eeprom = { }; static struct i2c_board_info pcm043_i2c_devices[] = { - { + { I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ .platform_data = &board_eeprom, }, { I2C_BOARD_INFO("pcf8563", 0x51), - } + }, }; static struct platform_device *devices[] __initdata = { @@ -217,11 +213,15 @@ static iomux_v3_cfg_t pcm043_pads[] = { MX35_PAD_SD1_DATA1__ESDHC1_DAT1, MX35_PAD_SD1_DATA2__ESDHC1_DAT2, MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ + MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ }; #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) +#define SD1_GPIO_WP IMX_GPIO_NR(2, 23) +#define SD1_GPIO_CD IMX_GPIO_NR(2, 24) static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { @@ -346,6 +346,11 @@ static int __init pcm043_otg_mode(char *options) } __setup("otg_mode=", pcm043_otg_mode); +static struct esdhc_platform_data sd1_pdata = { + .wp_gpio = SD1_GPIO_WP, + .cd_gpio = SD1_GPIO_CD, +}; + /* * Board specific initialization. */ @@ -380,8 +385,8 @@ static void __init pcm043_init(void) imx35_add_imx_i2c0(&pcm043_i2c0_data); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); + imx35_add_ipu_core(&mx3_ipu_data); + imx35_add_mx3_sdc_fb(&mx3fb_pdata); if (otg_mode_host) { otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | @@ -395,7 +400,7 @@ static void __init pcm043_init(void) imx35_add_fsl_usb2_udc(&otg_device_pdata); imx35_add_flexcan1(NULL); - imx35_add_sdhci_esdhc_imx(0, NULL); + imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); } static void __init pcm043_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index 17f758b7762..c1632871593 100644 --- a/arch/arm/mach-mx3/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c @@ -33,24 +33,23 @@ #include <mach/iomux-mx3.h> #include "devices-imx31.h" -#include "devices.h" /* FPGA defines */ #define QONG_FPGA_VERSION(major, minor, rev) \ (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) -#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR -#define QONG_FPGA_PERIPH_SIZE (1 << 24) +#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR +#define QONG_FPGA_PERIPH_SIZE (1 << 24) #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR -#define QONG_FPGA_CTRL_SIZE 0x10 +#define QONG_FPGA_CTRL_SIZE 0x10 /* FPGA control registers */ #define QONG_FPGA_CTRL_VERSION 0x00 #define QONG_DNET_ID 1 #define QONG_DNET_BASEADDR \ (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) -#define QONG_DNET_SIZE 0x00001000 +#define QONG_DNET_SIZE 0x00001000 #define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) @@ -166,15 +165,15 @@ static struct platform_nand_data qong_nand_data = { .options = 0, }, .ctrl = { - .cmd_ctrl = qong_nand_cmd_ctrl, + .cmd_ctrl = qong_nand_cmd_ctrl, .dev_ready = qong_nand_device_ready, .select_chip = qong_nand_select_chip, } }; static struct resource qong_nand_resource = { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, + .start = MX31_CS3_BASE_ADDR, + .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, .flags = IORESOURCE_MEM, }; diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 2cf390fbd98..d74e3473d23 100644 --- a/arch/arm/mach-mx3/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -32,16 +32,12 @@ #include <mach/common.h> #include <mach/iomux-mx35.h> #include <mach/irqs.h> -#include <mach/ipu.h> -#include <mach/mx3fb.h> #include <linux/i2c.h> #include <linux/i2c/at24.h> #include <linux/mfd/mc13xxx.h> -#include <linux/gpio_keys.h> #include "devices-imx35.h" -#include "devices.h" #define GPIO_LCDPWR IMX_GPIO_NR(1, 2) #define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) @@ -91,12 +87,11 @@ static const struct fb_videomode fb_modedb[] = { } }; -static struct ipu_platform_data mx3_ipu_data = { +static const struct ipu_platform_data mx3_ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; -static struct mx3fb_platform_data mx3fb_pdata = { - .dma_dev = &mx3_ipu.dev, +static struct mx3fb_platform_data mx3fb_pdata __initdata = { .name = "PT0708048", .mode = fb_modedb, .num_modes = ARRAY_SIZE(fb_modedb), @@ -141,18 +136,12 @@ static struct gpio_keys_button vpr200_gpio_keys_table[] = { {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE}, }; -static struct gpio_keys_platform_data vpr200_gpio_keys_data = { +static const struct gpio_keys_platform_data + vpr200_gpio_keys_data __initconst = { .buttons = vpr200_gpio_keys_table, .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table), }; -static struct platform_device vpr200_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &vpr200_gpio_keys_data, - } -}; - static struct mc13xxx_platform_data vpr200_pmic = { .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, }; @@ -257,16 +246,20 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .workaround = FLS_USB2_WORKAROUND_ENGCM09152, }; +static int vpr200_usbh_init(struct platform_device *pdev) +{ + return mx35_initialize_usb_hw(pdev->id, + MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY); +} + /* USB HOST config */ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .portsc = MXC_EHCI_MODE_SERIAL, - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY, + .init = vpr200_usbh_init, + .portsc = MXC_EHCI_MODE_SERIAL, }; static struct platform_device *devices[] __initdata = { &vpr200_flash, - &vpr200_device_gpiokeys, }; /* @@ -278,6 +271,7 @@ static void __init vpr200_board_init(void) imx35_add_fec(NULL); imx35_add_imx2_wdt(NULL); + imx_add_gpio_keys(&vpr200_gpio_keys_data); platform_add_devices(devices, ARRAY_SIZE(devices)); @@ -294,8 +288,8 @@ static void __init vpr200_board_init(void) imx35_add_imx_uart0(NULL); imx35_add_imx_uart2(NULL); - mxc_register_device(&mx3_ipu, &mx3_ipu_data); - mxc_register_device(&mx3_fb, &mx3fb_pdata); + imx35_add_ipu_core(&mx3_ipu_data); + imx35_add_mx3_sdc_fb(&mx3fb_pdata); imx35_add_fsl_usb2_udc(&otg_device_pdata); imx35_add_mxc_ehci_hs(&usb_host_pdata); diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c new file mode 100644 index 00000000000..86b9b45864d --- /dev/null +++ b/arch/arm/mach-imx/mm-imx31.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 1999,2000 Arm Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * - add MX31 specific definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/err.h> + +#include <asm/pgtable.h> +#include <asm/mach/map.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/iomux-v3.h> +#include <mach/gpio.h> +#include <mach/irqs.h> + +static struct map_desc mx31_io_desc[] __initdata = { + imx_map_entry(MX31, X_MEMC, MT_DEVICE), + imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx31_map_io(void) +{ + iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); +} + +void __init imx31_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX31); + mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); +} + +static struct mxc_gpio_port imx31_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), +}; + +void __init mx31_init_irq(void) +{ + mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); + mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports)); +} diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c new file mode 100644 index 00000000000..c880e6d1ae5 --- /dev/null +++ b/arch/arm/mach-imx/mm-imx35.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 1999,2000 Arm Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * - add MX31 specific definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/err.h> + +#include <asm/pgtable.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/iomux-v3.h> +#include <mach/gpio.h> +#include <mach/irqs.h> + +static struct map_desc mx35_io_desc[] __initdata = { + imx_map_entry(MX35, X_MEMC, MT_DEVICE), + imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), +}; + +void __init mx35_map_io(void) +{ + iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); +} + +void __init imx35_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX35); + mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); +} + +static struct mxc_gpio_port imx35_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), +}; + +void __init mx35_init_irq(void) +{ + mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); + mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports)); +} diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c index 8f1a38ebf5c..7d26f766a4e 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-imx/mx31lilly-db.c @@ -34,11 +34,8 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/mx3fb.h> -#include <mach/ipu.h> #include "devices-imx31.h" -#include "devices.h" /* * This file contains board-specific initialization routines for the @@ -164,13 +161,13 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = { }; /* Framebuffer support */ -static struct ipu_platform_data ipu_data __initdata = { +static const struct ipu_platform_data ipu_data __initconst = { .irq_base = MXC_IPU_IRQ_START, }; static const struct fb_videomode fb_modedb = { /* 640x480 TFT panel (IPS-056T) */ - .name = "CRT-VGA", + .name = "CRT-VGA", .refresh = 64, .xres = 640, .yres = 480, @@ -187,7 +184,6 @@ static const struct fb_videomode fb_modedb = { }; static struct mx3fb_platform_data fb_pdata __initdata = { - .dma_dev = &mx3_ipu.dev, .name = "CRT-VGA", .mode = &fb_modedb, .num_modes = 1, @@ -202,8 +198,8 @@ static void __init mx31lilly_init_fb(void) return; } - mxc_register_device(&mx3_ipu, &ipu_data); - mxc_register_device(&mx3_fb, &fb_pdata); + imx31_add_ipu_core(&ipu_data); + imx31_add_mx3_sdc_fb(&fb_pdata); gpio_direction_output(LCD_VCC_EN_GPIO, 1); } @@ -218,4 +214,3 @@ void __init mx31lilly_db_init(void) imx31_add_mxc_mmc(0, &mmc_pdata); mx31lilly_init_fb(); } - diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c index 3124ea837ac..5aa053edc17 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-imx/mx31lite-db.c @@ -37,7 +37,6 @@ #include <mach/board-mx31lite.h> #include "devices-imx31.h" -#include "devices.h" /* * This file contains board-specific initialization routines for the @@ -200,5 +199,5 @@ void __init mx31lite_db_init(void) imx31_add_spi_imx0(&spi0_pdata); platform_device_register(&litekit_led_device); imx31_add_imx2_wdt(NULL); - mxc_register_device(&imx_rtc_device0, NULL); + imx31_add_mxc_rtc(NULL); } diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c index 6410b9c48a0..0aa25364360 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-imx/mx31moboard-devboard.c @@ -28,7 +28,6 @@ #include <mach/ulpi.h> #include "devices-imx31.h" -#include "devices.h" static unsigned int devboard_pins[] = { /* UART1 */ diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c index 57f7b00cb70..bb639cbda4e 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-imx/mx31moboard-marxbot.c @@ -26,14 +26,12 @@ #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/ulpi.h> #include <media/soc_camera.h> #include "devices-imx31.h" -#include "devices.h" static unsigned int marxbot_pins[] = { /* SDHC2 */ diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c index 35f806e737c..fabb801e799 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-imx/mx31moboard-smartbot.c @@ -32,7 +32,6 @@ #include <media/soc_camera.h> #include "devices-imx31.h" -#include "devices.h" static unsigned int smartbot_pins[] = { /* UART1 */ diff --git a/arch/arm/mach-mx3/pcm037.h b/arch/arm/mach-imx/pcm037.h index d6929721a5f..d6929721a5f 100644 --- a/arch/arm/mach-mx3/pcm037.h +++ b/arch/arm/mach-imx/pcm037.h diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index d701d32a07f..dfd18f3b50e 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -4,6 +4,7 @@ menu "Integrator Options" config ARCH_INTEGRATOR_AP bool "Support Integrator/AP and Integrator/PP2 platforms" + select CLKSRC_MMIO select MIGHT_HAVE_PCI help Include support for the ARM(R) Integrator/AP and diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 980803ff348..2fbbdd5eac3 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -24,13 +24,14 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/string.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/amba/bus.h> #include <linux/amba/kmi.h> #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/mtd/physmap.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -43,7 +44,6 @@ #include <mach/lm.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -180,13 +180,13 @@ static void __init ap_init_irq(void) #ifdef CONFIG_PM static unsigned long ic_irq_enable; -static int irq_suspend(struct sys_device *dev, pm_message_t state) +static int irq_suspend(void) { ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); return 0; } -static int irq_resume(struct sys_device *dev) +static void irq_resume(void) { /* disable all irq sources */ writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); @@ -194,33 +194,25 @@ static int irq_resume(struct sys_device *dev) writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); - return 0; } #else #define irq_suspend NULL #define irq_resume NULL #endif -static struct sysdev_class irq_class = { - .name = "irq", +static struct syscore_ops irq_syscore_ops = { .suspend = irq_suspend, .resume = irq_resume, }; -static struct sys_device irq_device = { - .id = 0, - .cls = &irq_class, -}; - -static int __init irq_init_sysfs(void) +static int __init irq_syscore_init(void) { - int ret = sysdev_class_register(&irq_class); - if (ret == 0) - ret = sysdev_register(&irq_device); - return ret; + register_syscore_ops(&irq_syscore_ops); + + return 0; } -device_initcall(irq_init_sysfs); +device_initcall(irq_syscore_init); /* * Flash handling. @@ -230,7 +222,7 @@ device_initcall(irq_init_sysfs); #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) -static int ap_flash_init(void) +static int ap_flash_init(struct platform_device *dev) { u32 tmp; @@ -247,7 +239,7 @@ static int ap_flash_init(void) return 0; } -static void ap_flash_exit(void) +static void ap_flash_exit(struct platform_device *dev) { u32 tmp; @@ -263,15 +255,14 @@ static void ap_flash_exit(void) } } -static void ap_flash_set_vpp(int on) +static void ap_flash_set_vpp(struct platform_device *pdev, int on) { void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); } -static struct flash_platform_data ap_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data ap_flash_data = { .width = 4, .init = ap_flash_init, .exit = ap_flash_exit, @@ -285,7 +276,7 @@ static struct resource cfi_flash_resource = { }; static struct platform_device cfi_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &ap_flash_data, @@ -343,25 +334,9 @@ static void __init ap_init(void) static unsigned long timer_reload; -static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE; - -static cycle_t timersp_read(struct clocksource *cs) -{ - return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff); -} - -static struct clocksource clocksource_timersp = { - .name = "timer2", - .rating = 200, - .read = timersp_read, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static void integrator_clocksource_init(u32 khz) { - struct clocksource *cs = &clocksource_timersp; - void __iomem *base = clksrc_base; + void __iomem *base = (void __iomem *)TIMER2_VA_BASE; u32 ctrl = TIMER_CTRL_ENABLE; if (khz >= 1500) { @@ -372,7 +347,8 @@ static void integrator_clocksource_init(u32 khz) writel(ctrl, base + TIMER_CTRL); writel(0xffff, base + TIMER_LOAD); - clocksource_register_khz(cs, khz); + clocksource_mmio_init(base + TIMER_VALUE, "timer2", + khz * 1000, 200, 16, clocksource_mmio_readl_down); } static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 9e3ce26023e..4eb03ab5cb4 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/gfp.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -35,7 +36,6 @@ #include <mach/lm.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -229,17 +229,24 @@ static struct clk cp_auxclk = { .vcoreg = CM_AUXOSC, }; +static struct clk sp804_clk = { + .rate = 1000000, +}; + static struct clk_lookup cp_lookups[] = { { /* CLCD */ .dev_id = "mb:c0", .clk = &cp_auxclk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .clk = &sp804_clk, }, }; /* * Flash handling. */ -static int intcp_flash_init(void) +static int intcp_flash_init(struct platform_device *dev) { u32 val; @@ -250,7 +257,7 @@ static int intcp_flash_init(void) return 0; } -static void intcp_flash_exit(void) +static void intcp_flash_exit(struct platform_device *dev) { u32 val; @@ -259,7 +266,7 @@ static void intcp_flash_exit(void) writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); } -static void intcp_flash_set_vpp(int on) +static void intcp_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; @@ -271,8 +278,7 @@ static void intcp_flash_set_vpp(int on) writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); } -static struct flash_platform_data intcp_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data intcp_flash_data = { .width = 4, .init = intcp_flash_init, .exit = intcp_flash_exit, @@ -286,7 +292,7 @@ static struct resource intcp_flash_resource = { }; static struct platform_device intcp_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &intcp_flash_data, @@ -476,8 +482,8 @@ static void __init intcp_timer_init(void) writel(0, TIMER1_VA_BASE + TIMER_CTRL); writel(0, TIMER2_VA_BASE + TIMER_CTRL); - sp804_clocksource_init(TIMER2_VA_BASE); - sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1); + sp804_clocksource_init(TIMER2_VA_BASE, "timer2"); + sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); } static struct sys_timer cp_timer = { diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index a233470dd10..bc739701c30 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void) for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { if (i < 32) - set_irq_chip(i, &iop13xx_irqchip1); + irq_set_chip(i, &iop13xx_irqchip1); else if (i < 64) - set_irq_chip(i, &iop13xx_irqchip2); + irq_set_chip(i, &iop13xx_irqchip2); else if (i < 96) - set_irq_chip(i, &iop13xx_irqchip3); + irq_set_chip(i, &iop13xx_irqchip3); else - set_irq_chip(i, &iop13xx_irqchip4); + irq_set_chip(i, &iop13xx_irqchip4); - set_irq_handler(i, handle_level_irq); + irq_set_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index c9c02e3698b..560d5b2dec2 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) void __init iop13xx_msi_init(void) { - set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); + irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); } /* @@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) if (irq < 0) return irq; - set_irq_msi(irq, desc); + irq_set_msi_desc(irq, desc); msg.address_hi = 0x0; msg.address_lo = IOP13XX_MU_MIMR_PCI; @@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); write_msi_msg(irq, &msg); - set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); + irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); return 0; } diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 773ea0c95b9..ba3dae352a2 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c @@ -225,7 +225,7 @@ static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where) /* This routine checks the status of the last configuration cycle. If an error * was detected it returns >0, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during + * errors occur during a config cycle where there is no device, like during * the discovery stage. */ static int iop13xx_atux_pci_status(int clear) @@ -332,7 +332,7 @@ static struct pci_ops iop13xx_atux_ops = { /* This routine checks the status of the last configuration cycle. If an error * was detected it returns >0, else it returns a 0. The errors being checked * are parity, master abort, target abort (master and target). These types of - * errors occure during a config cycle where there is no device, like during + * errors occur during a config cycle where there is no device, like during * the discovery stage. */ static int iop13xx_atue_pci_status(int clear) diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h index b247551b6f5..4fd715496f4 100644 --- a/arch/arm/mach-iop32x/include/mach/uncompress.h +++ b/arch/arm/mach-iop32x/include/mach/uncompress.h @@ -7,7 +7,7 @@ #include <linux/serial_reg.h> #include <mach/hardware.h> -static volatile u8 *uart_base; +volatile u8 *uart_base; #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index d3426a12059..d7ee2789d89 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -68,8 +68,7 @@ void __init iop32x_init_irq(void) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &ext_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h index b42423f6330..f99bb848c5a 100644 --- a/arch/arm/mach-iop33x/include/mach/uncompress.h +++ b/arch/arm/mach-iop33x/include/mach/uncompress.h @@ -7,7 +7,7 @@ #include <linux/serial_reg.h> #include <mach/hardware.h> -static volatile u32 *uart_base; +volatile u32 *uart_base; #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 0ff2f74363a..f7f5d3e451c 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -110,8 +110,9 @@ void __init iop33x_init_irq(void) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, + (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, + handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 5fc4e064b65..4068166c899 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c @@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void) */ for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { - set_irq_chip(irq, &ixp2000_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else set_irq_flags(irq, 0); } @@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void) for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & IXP2000_VALID_ERR_IRQ_MASK) { - set_irq_chip(irq, &ixp2000_err_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else set_irq_flags(irq, 0); } - set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { - set_irq_chip(irq, &ixp2000_GPIO_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); /* * Enable PCI irqs. The actual PCI[AB] decoding is done in @@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void) */ ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { - set_irq_chip(irq, &ixp2000_pci_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 7d90d3f13ee..235638f800e 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne *board_irq_mask = 0xffffffff; for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { - set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } /* Hook into PCI interrupt */ - set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); } /************************************************************************* diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 34b1b2af37c..84835b20955 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void) for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { if (irq & valid_irq_mask) { - set_irq_chip(irq, &ixdp2x01_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } else { set_irq_flags(irq, 0); @@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void) } /* Hook into PCI interrupts */ - set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); } diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 9c8a3390321..a1bee33d183 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c @@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) { switch (type) { case IXP23XX_IRQ_LEVEL: - set_irq_chip(irq, &ixp23xx_irq_level_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip, + handle_level_irq); break; case IXP23XX_IRQ_EDGE: - set_irq_chip(irq, &ixp23xx_irq_edge_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip, + handle_edge_irq); break; } set_irq_flags(irq, IRQF_VALID); @@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void) } for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { - set_irq_chip(irq, &ixp23xx_pci_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); + irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); } diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 181116aa659..8dcba17c81e 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c @@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void) irq++) { if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - set_irq_chip(irq, &ixdp2351_inta_chip); + irq_set_chip_and_handler(irq, &ixdp2351_inta_chip, + handle_level_irq); } } @@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void) irq++) { if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); - set_irq_chip(irq, &ixdp2351_intb_chip); + irq_set_chip_and_handler(irq, &ixdp2351_intb_chip, + handle_level_irq); } } - set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); - set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); + irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); + irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); } /* diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index 76c61ba7321..8fe0c627326 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c @@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) static void __init roadrunner_pci_preinit(void) { - set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); ixp23xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 845e1b50054..162043ff29f 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c @@ -39,10 +39,10 @@ void __init avila_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index a54b3db8036..e9a58939572 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); } -/* - * Only first 64MB of memory can be accessed via PCI. - * We use GFP_DMA to allocate safe buffers to do map/unmap. - * This is really ugly and we need a better way of specifying - * DMA-capable regions of memory. - */ -void __init ixp4xx_adjust_zones(unsigned long *zone_size, - unsigned long *zhole_size) -{ - unsigned int sz = SZ_64M >> PAGE_SHIFT; - - /* - * Only adjust if > 64M on current system - */ - if (zone_size[0] <= sz) - return; - - zone_size[1] = zone_size[0] - sz; - zone_size[0] = sz; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; -} - void __init ixp4xx_pci_preinit(void) { unsigned long cpuid = read_cpuid_id(); diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 9fd894271d5..74ed81a3cb1 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void) /* Default to all level triggered */ for(i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &ixp4xx_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &ixp4xx_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } @@ -419,26 +419,14 @@ static void notrace ixp4xx_update_sched_clock(void) /* * clocksource */ -static cycle_t ixp4xx_get_cycles(struct clocksource *cs) -{ - return *IXP4XX_OSTS; -} - -static struct clocksource clocksource_ixp4xx = { - .name = "OSTS", - .rating = 200, - .read = ixp4xx_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; EXPORT_SYMBOL(ixp4xx_timer_freq); static void __init ixp4xx_clocksource_init(void) { init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq); - clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq); + clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32, + clocksource_mmio_readl_up); } /* diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index b978ea8bd6f..37fda7d6e83 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c @@ -32,8 +32,8 @@ void __init coyote_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index fa70fed462b..c7612010b3f 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c @@ -35,12 +35,12 @@ void __init dsmg600_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index 5a810c93062..44ccde9d487 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c @@ -32,9 +32,9 @@ void __init fsg_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 7e93a0975c4..fc112416887 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c @@ -29,8 +29,8 @@ void __init gateway7001_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index d0e4861ac03..3e8c0e33b59 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -420,8 +420,8 @@ static void __init gmlr_init(void) gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); set_control(CONTROL_HSS0_DTR_N, 1); set_control(CONTROL_HSS1_DTR_N, 1); @@ -441,10 +441,10 @@ static void __init gmlr_init(void) #ifdef CONFIG_PCI static void __init gmlr_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 25d2c333c20..38cc0725dbd 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c @@ -43,8 +43,8 @@ */ void __init gtwx5715_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index 6d388c9d0e2..34e79404671 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -14,16 +14,8 @@ */ #define PLAT_PHYS_OFFSET UL(0x00000000) -#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) - -void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - ixp4xx_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) - +#ifdef CONFIG_PCI +#define ARM_DMA_ZONE_SIZE SZ_64M #endif #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h index 2db0078a8cf..219d7c1dcdb 100644 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -19,7 +19,7 @@ #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) -static volatile u32* uart_base; +volatile u32* uart_base; static inline void putc(int c) { diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 1ba165a6eda..58f400417ea 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c @@ -36,10 +36,10 @@ void __init ixdp425_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 4ed7ac61492..e64f6d04148 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c @@ -25,8 +25,8 @@ void __init ixdpg425_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index d0cea34cf61..428d1202b79 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c @@ -33,11 +33,11 @@ void __init nas100d_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 1eb5a90470b..2e85f76b950 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c @@ -32,9 +32,9 @@ void __init nslu2_pci_preinit(void) { - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index f3111c6840e..03bdec5140a 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c @@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void) pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", (int)(pci_cardbus_mem_size >> 20)); #endif - set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); - set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index 9b59ed03b15..17f3cf59a31 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c @@ -29,8 +29,8 @@ void __init wg302v2_pci_preinit(void) { - set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); - set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ixp4xx_pci_preinit(); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 20e71df3e3b..f3248cfbe51 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -13,11 +13,9 @@ #include <linux/platform_device.h> #include <linux/serial_8250.h> #include <linux/mbus.h> -#include <linux/mv643xx_eth.h> -#include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> #include <linux/mtd/nand.h> -#include <linux/spi/orion_spi.h> +#include <linux/dma-mapping.h> #include <net/dsa.h> #include <asm/page.h> #include <asm/timex.h> @@ -28,11 +26,9 @@ #include <mach/bridge-regs.h> #include <plat/audio.h> #include <plat/cache-feroceon-l2.h> -#include <plat/ehci-orion.h> #include <plat/mvsdio.h> -#include <plat/mv_xor.h> #include <plat/orion_nand.h> -#include <plat/orion_wdt.h> +#include <plat/common.h> #include <plat/time.h> #include "common.h" @@ -69,210 +65,52 @@ void __init kirkwood_map_io(void) * registered. Some reserved bits must be set to 1. */ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; - - -/***************************************************************************** - * EHCI - ****************************************************************************/ -static struct orion_ehci_data kirkwood_ehci_data = { - .dram = &kirkwood_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; - -static u64 ehci_dmamask = 0xffffffffUL; /***************************************************************************** * EHCI0 ****************************************************************************/ -static struct resource kirkwood_ehci_resources[] = { - { - .start = USB_PHYS_BASE, - .end = USB_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_USB, - .end = IRQ_KIRKWOOD_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ehci = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &kirkwood_ehci_data, - }, - .resource = kirkwood_ehci_resources, - .num_resources = ARRAY_SIZE(kirkwood_ehci_resources), -}; - void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; - platform_device_register(&kirkwood_ehci); + orion_ehci_init(&kirkwood_mbus_dram_info, + USB_PHYS_BASE, IRQ_KIRKWOOD_USB); } /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = { - .dram = &kirkwood_mbus_dram_info, -}; - -static struct resource kirkwood_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, { - .name = "ge00 err irq", - .start = IRQ_KIRKWOOD_GE00_ERR, - .end = IRQ_KIRKWOOD_GE00_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &kirkwood_ge00_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources), - .resource = kirkwood_ge00_shared_resources, -}; - -static struct resource kirkwood_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_KIRKWOOD_GE00_SUM, - .end = IRQ_KIRKWOOD_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = kirkwood_ge00_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { kirkwood_clk_ctrl |= CGC_GE0; - eth_data->shared = &kirkwood_ge00_shared; - kirkwood_ge00.dev.platform_data = eth_data; - platform_device_register(&kirkwood_ge00_shared); - platform_device_register(&kirkwood_ge00); + orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, + GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, + IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); } /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = { - .dram = &kirkwood_mbus_dram_info, - .shared_smi = &kirkwood_ge00_shared, -}; - -static struct resource kirkwood_ge01_shared_resources[] = { - { - .name = "ge01 base", - .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, { - .name = "ge01 err irq", - .start = IRQ_KIRKWOOD_GE01_ERR, - .end = IRQ_KIRKWOOD_GE01_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge01_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &kirkwood_ge01_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources), - .resource = kirkwood_ge01_shared_resources, -}; - -static struct resource kirkwood_ge01_resources[] = { - { - .name = "ge01 irq", - .start = IRQ_KIRKWOOD_GE01_SUM, - .end = IRQ_KIRKWOOD_GE01_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_ge01 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = kirkwood_ge01_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) { + kirkwood_clk_ctrl |= CGC_GE1; - eth_data->shared = &kirkwood_ge01_shared; - kirkwood_ge01.dev.platform_data = eth_data; - platform_device_register(&kirkwood_ge01_shared); - platform_device_register(&kirkwood_ge01); + orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, + GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, + IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); } /***************************************************************************** * Ethernet switch ****************************************************************************/ -static struct resource kirkwood_switch_resources[] = { - { - .start = 0, - .end = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_switch_device = { - .name = "dsa", - .id = 0, - .num_resources = 0, - .resource = kirkwood_switch_resources, -}; - void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) { - int i; - - if (irq != NO_IRQ) { - kirkwood_switch_resources[0].start = irq; - kirkwood_switch_resources[0].end = irq; - kirkwood_switch_device.num_resources = 1; - } - - d->netdev = &kirkwood_ge00.dev; - for (i = 0; i < d->nr_chips; i++) - d->chip[i].mii_bus = &kirkwood_ge00_shared.dev; - kirkwood_switch_device.dev.platform_data = d; - - platform_device_register(&kirkwood_switch_device); + orion_ge00_switch_init(d, irq); } @@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, /***************************************************************************** * SoC RTC ****************************************************************************/ -static struct resource kirkwood_rtc_resource = { - .start = RTC_PHYS_BASE, - .end = RTC_PHYS_BASE + SZ_16 - 1, - .flags = IORESOURCE_MEM, -}; - static void __init kirkwood_rtc_init(void) { - platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); + orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); } /***************************************************************************** * SATA ****************************************************************************/ -static struct resource kirkwood_sata_resources[] = { - { - .name = "sata base", - .start = SATA_PHYS_BASE, - .end = SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_KIRKWOOD_SATA, - .end = IRQ_KIRKWOOD_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(kirkwood_sata_resources), - .resource = kirkwood_sata_resources, -}; - void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) { kirkwood_clk_ctrl |= CGC_SATA0; if (sata_data->n_ports > 1) kirkwood_clk_ctrl |= CGC_SATA1; - sata_data->dram = &kirkwood_mbus_dram_info; - kirkwood_sata.dev.platform_data = sata_data; - platform_device_register(&kirkwood_sata); + + orion_sata_init(sata_data, &kirkwood_mbus_dram_info, + SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); } @@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = { }, }; -static u64 mvsdio_dmamask = 0xffffffffUL; +static u64 mvsdio_dmamask = DMA_BIT_MASK(32); static struct platform_device kirkwood_sdio = { .name = "mvsdio", .id = -1, .dev = { .dma_mask = &mvsdio_dmamask, - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(mvsdio_resources), .resource = mvsdio_resources, @@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) /***************************************************************************** * SPI ****************************************************************************/ -static struct orion_spi_info kirkwood_spi_plat_data = { -}; - -static struct resource kirkwood_spi_resources[] = { - { - .start = SPI_PHYS_BASE, - .end = SPI_PHYS_BASE + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device kirkwood_spi = { - .name = "orion_spi", - .id = 0, - .resource = kirkwood_spi_resources, - .dev = { - .platform_data = &kirkwood_spi_plat_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_spi_resources), -}; - void __init kirkwood_spi_init() { kirkwood_clk_ctrl |= CGC_RUNIT; - platform_device_register(&kirkwood_spi); + orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk); } /***************************************************************************** * I2C ****************************************************************************/ -static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource kirkwood_i2c_resources[] = { - { - .start = I2C_PHYS_BASE, - .end = I2C_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_TWSI, - .end = IRQ_KIRKWOOD_TWSI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(kirkwood_i2c_resources), - .resource = kirkwood_i2c_resources, - .dev = { - .platform_data = &kirkwood_i2c_pdata, - }, -}; - void __init kirkwood_i2c_init(void) { - platform_device_register(&kirkwood_i2c); + orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8); } /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port kirkwood_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_KIRKWOOD_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource kirkwood_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_UART_0, - .end = IRQ_KIRKWOOD_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_uart0 = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = kirkwood_uart0_data, - }, - .resource = kirkwood_uart0_resources, - .num_resources = ARRAY_SIZE(kirkwood_uart0_resources), -}; void __init kirkwood_uart0_init(void) { - platform_device_register(&kirkwood_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_KIRKWOOD_UART_0, kirkwood_tclk); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port kirkwood_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_KIRKWOOD_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource kirkwood_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_KIRKWOOD_UART_1, - .end = IRQ_KIRKWOOD_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_uart1 = { - .name = "serial8250", - .id = 1, - .dev = { - .platform_data = kirkwood_uart1_data, - }, - .resource = kirkwood_uart1_resources, - .num_resources = ARRAY_SIZE(kirkwood_uart1_resources), -}; - void __init kirkwood_uart1_init(void) { - platform_device_register(&kirkwood_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_KIRKWOOD_UART_1, kirkwood_tclk); } - /***************************************************************************** * Cryptographic Engines and Security Accelerator (CESA) ****************************************************************************/ - -static struct resource kirkwood_crypto_res[] = { - { - .name = "regs", - .start = CRYPTO_PHYS_BASE, - .end = CRYPTO_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .name = "sram", - .start = KIRKWOOD_SRAM_PHYS_BASE, - .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "crypto interrupt", - .start = IRQ_KIRKWOOD_CRYPTO, - .end = IRQ_KIRKWOOD_CRYPTO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kirkwood_crypto_device = { - .name = "mv_crypto", - .id = -1, - .num_resources = ARRAY_SIZE(kirkwood_crypto_res), - .resource = kirkwood_crypto_res, -}; - void __init kirkwood_crypto_init(void) { kirkwood_clk_ctrl |= CGC_CRYPTO; - platform_device_register(&kirkwood_crypto_device); + orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE, + KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO); } /***************************************************************************** - * XOR - ****************************************************************************/ -static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = { - .dram = &kirkwood_mbus_dram_info, -}; - -static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32); - - -/***************************************************************************** * XOR0 ****************************************************************************/ -static struct resource kirkwood_xor0_shared_resources[] = { - { - .name = "xor 0 low", - .start = XOR0_PHYS_BASE, - .end = XOR0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 0 high", - .start = XOR0_HIGH_PHYS_BASE, - .end = XOR0_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device kirkwood_xor0_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &kirkwood_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources), - .resource = kirkwood_xor0_shared_resources, -}; - -static struct resource kirkwood_xor00_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_00, - .end = IRQ_KIRKWOOD_XOR_00, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor00_data = { - .shared = &kirkwood_xor0_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor00_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(kirkwood_xor00_resources), - .resource = kirkwood_xor00_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor00_data, - }, -}; - -static struct resource kirkwood_xor01_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_01, - .end = IRQ_KIRKWOOD_XOR_01, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor01_data = { - .shared = &kirkwood_xor0_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor01_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(kirkwood_xor01_resources), - .resource = kirkwood_xor01_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor01_data, - }, -}; - static void __init kirkwood_xor0_init(void) { kirkwood_clk_ctrl |= CGC_XOR0; - platform_device_register(&kirkwood_xor0_shared); - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask); - platform_device_register(&kirkwood_xor00_channel); - - dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask); - dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask); - platform_device_register(&kirkwood_xor01_channel); + orion_xor0_init(&kirkwood_mbus_dram_info, + XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, + IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); } /***************************************************************************** * XOR1 ****************************************************************************/ -static struct resource kirkwood_xor1_shared_resources[] = { - { - .name = "xor 1 low", - .start = XOR1_PHYS_BASE, - .end = XOR1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor 1 high", - .start = XOR1_HIGH_PHYS_BASE, - .end = XOR1_HIGH_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device kirkwood_xor1_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &kirkwood_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources), - .resource = kirkwood_xor1_shared_resources, -}; - -static struct resource kirkwood_xor10_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_10, - .end = IRQ_KIRKWOOD_XOR_10, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor10_data = { - .shared = &kirkwood_xor1_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor10_channel = { - .name = MV_XOR_NAME, - .id = 2, - .num_resources = ARRAY_SIZE(kirkwood_xor10_resources), - .resource = kirkwood_xor10_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor10_data, - }, -}; - -static struct resource kirkwood_xor11_resources[] = { - [0] = { - .start = IRQ_KIRKWOOD_XOR_11, - .end = IRQ_KIRKWOOD_XOR_11, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data kirkwood_xor11_data = { - .shared = &kirkwood_xor1_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device kirkwood_xor11_channel = { - .name = MV_XOR_NAME, - .id = 3, - .num_resources = ARRAY_SIZE(kirkwood_xor11_resources), - .resource = kirkwood_xor11_resources, - .dev = { - .dma_mask = &kirkwood_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &kirkwood_xor11_data, - }, -}; - static void __init kirkwood_xor1_init(void) { kirkwood_clk_ctrl |= CGC_XOR1; - platform_device_register(&kirkwood_xor1_shared); - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask); - platform_device_register(&kirkwood_xor10_channel); - - dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask); - dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask); - dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask); - platform_device_register(&kirkwood_xor11_channel); + orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE, + IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11); } /***************************************************************************** * Watchdog ****************************************************************************/ -static struct orion_wdt_platform_data kirkwood_wdt_data = { - .tclk = 0, -}; - -static struct platform_device kirkwood_wdt_device = { - .name = "orion_wdt", - .id = -1, - .dev = { - .platform_data = &kirkwood_wdt_data, - }, - .num_resources = 0, -}; - static void __init kirkwood_wdt_init(void) { - kirkwood_wdt_data.tclk = kirkwood_tclk; - platform_device_register(&kirkwood_wdt_device); + orion_wdt_init(kirkwood_tclk); } @@ -984,11 +452,6 @@ void __init kirkwood_init(void) { printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); - kirkwood_ge00_shared_data.t_clk = kirkwood_tclk; - kirkwood_ge01_shared_data.t_clk = kirkwood_tclk; - kirkwood_spi_plat_data.tclk = kirkwood_tclk; - kirkwood_uart0_data[0].uartclk = kirkwood_tclk; - kirkwood_uart1_data[0].uartclk = kirkwood_tclk; kirkwood_i2s_data.tclk = kirkwood_tclk; /* diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h index 9da2eb59180..2bf8161e3b5 100644 --- a/arch/arm/mach-kirkwood/include/mach/irqs.h +++ b/arch/arm/mach-kirkwood/include/mach/irqs.h @@ -51,6 +51,7 @@ #define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 #define IRQ_KIRKWOOD_GE00_ERR 46 #define IRQ_KIRKWOOD_GE01_ERR 47 +#define IRQ_KIRKWOOD_RTC 53 /* * KIRKWOOD General Purpose Pins diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index cbdb5863d13..05d193a25b2 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void) */ orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, + gpio_irq_handler); } diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 7ce20184806..b0a7d979a8e 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -14,6 +14,7 @@ #include <linux/io.h> #include <asm/gpio.h> #include <mach/hardware.h> +#include <plat/mpp.h> #include "common.h" #include "mpp.h" @@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void) return 0; } -#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) -#define MPP_NR_REGS (1 + MPP_MAX/8) - void __init kirkwood_mpp_conf(unsigned int *mpp_list) { - u32 mpp_ctrl[MPP_NR_REGS]; - unsigned int variant_mask; - int i; - - variant_mask = kirkwood_variant(); - if (!variant_mask) - return; - - printk(KERN_DEBUG "initial MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - mpp_ctrl[i] = readl(MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); - - for ( ; *mpp_list; mpp_list++) { - unsigned int num = MPP_NUM(*mpp_list); - unsigned int sel = MPP_SEL(*mpp_list); - int shift, gpio_mode; - - if (num > MPP_MAX) { - printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP " - "number (%u)\n", num); - continue; - } - if (!(*mpp_list & variant_mask)) { - printk(KERN_WARNING - "kirkwood_mpp_conf: requested MPP%u config " - "unavailable on this hardware\n", num); - continue; - } - - shift = (num & 7) << 2; - mpp_ctrl[num / 8] &= ~(0xf << shift); - mpp_ctrl[num / 8] |= sel << shift; - - gpio_mode = 0; - if (*mpp_list & MPP_INPUT_MASK) - gpio_mode |= GPIO_INPUT_OK; - if (*mpp_list & MPP_OUTPUT_MASK) - gpio_mode |= GPIO_OUTPUT_OK; - if (sel != 0) - gpio_mode = 0; - orion_gpio_set_valid(num, gpio_mode); - } - - printk(KERN_DEBUG " final MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - writel(mpp_ctrl[i], MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); + orion_mpp_conf(mpp_list, kirkwood_variant(), + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index 9b0a94d85c3..ac787957e2d 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -22,14 +22,8 @@ /* available on F6281 */ ((!!(_F6281)) << 17) | \ /* available on F6282 */ ((!!(_F6282)) << 18)) -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - /* num sel i o 6180 6190 6192 6281 6282 */ -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 ) - #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index 0a95063f6d3..17de0bf53c0 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -58,6 +58,12 @@ static struct mvsdio_platform_data sheeva_esata_mvsdio_data = { static struct gpio_led sheevaplug_led_pins[] = { { + .name = "plug:red:misc", + .default_trigger = "none", + .gpio = 46, + .active_low = 1, + }, + { .name = "plug:green:health", .default_trigger = "default-on", .gpio = 49, @@ -80,6 +86,7 @@ static struct platform_device sheevaplug_leds = { static unsigned int sheevaplug_mpp_config[] __initdata = { MPP29_GPIO, /* USB Power Enable */ + MPP46_GPIO, /* LED Red */ MPP49_GPIO, /* LED */ 0 }; diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c index f781164e623..24294b2bc46 100644 --- a/arch/arm/mach-kirkwood/tsx1x-common.c +++ b/arch/arm/mach-kirkwood/tsx1x-common.c @@ -15,7 +15,7 @@ /**************************************************************************** * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with + * partitions on the device because we want to keep compatibility with * the QNAP firmware. * Layout as used by QNAP: * 0x00000000-0x00080000 : "U-Boot" diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index 55fbf7111a5..31e456508a6 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c @@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) local_irq_restore(flags); /* Set IRQ triggering type */ - set_irq_type(gpio_irq[pin], type); + irq_set_irq_type(gpio_irq[pin], type); /* enable interrupt mode */ ks8695_gpio_mode(pin, 0); diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 7998ccaa633..a78092dcd6f 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c @@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) } if (level_triggered) { - set_irq_chip(d->irq, &ks8695_irq_level_chip); - set_irq_handler(d->irq, handle_level_irq); + irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip, + handle_level_irq); } else { - set_irq_chip(d->irq, &ks8695_irq_edge_chip); - set_irq_handler(d->irq, handle_edge_irq); + irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip, + handle_edge_irq); } __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); @@ -158,16 +158,18 @@ void __init ks8695_init_irq(void) case KS8695_IRQ_UART_RX: case KS8695_IRQ_COMM_TX: case KS8695_IRQ_COMM_RX: - set_irq_chip(irq, &ks8695_irq_level_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, + &ks8695_irq_level_chip, + handle_level_irq); break; /* Edge-triggered interrupts */ default: /* clear pending bit */ ks8695_irq_ack(irq_get_irq_data(irq)); - set_irq_chip(irq, &ks8695_irq_edge_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, + &ks8695_irq_edge_chip, + handle_edge_irq); } set_irq_flags(irq, IRQF_VALID); diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c index e41e909cf8f..5f02664db81 100644 --- a/arch/arm/mach-loki/common.c +++ b/arch/arm/mach-loki/common.c @@ -13,7 +13,7 @@ #include <linux/platform_device.h> #include <linux/serial_8250.h> #include <linux/mbus.h> -#include <linux/mv643xx_eth.h> +#include <linux/dma-mapping.h> #include <asm/page.h> #include <asm/timex.h> #include <asm/mach/map.h> @@ -22,6 +22,7 @@ #include <mach/loki.h> #include <plat/orion_nand.h> #include <plat/time.h> +#include <plat/common.h> #include "common.h" /***************************************************************************** @@ -43,116 +44,28 @@ void __init loki_map_io(void) /***************************************************************************** - * GE0 + * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = { - .t_clk = LOKI_TCLK, - .dram = &loki_mbus_dram_info, -}; - -static struct resource loki_ge0_shared_resources[] = { - { - .name = "ge0 base", - .start = GE0_PHYS_BASE + 0x2000, - .end = GE0_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device loki_ge0_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &loki_ge0_shared_data, - }, - .num_resources = 1, - .resource = loki_ge0_shared_resources, -}; - -static struct resource loki_ge0_resources[] = { - { - .name = "ge0 irq", - .start = IRQ_LOKI_GBE_A_INT, - .end = IRQ_LOKI_GBE_A_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_ge0 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = loki_ge0_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &loki_ge0_shared; - loki_ge0.dev.platform_data = eth_data; - writel(0x00079220, GE0_VIRT_BASE + 0x20b0); - platform_device_register(&loki_ge0_shared); - platform_device_register(&loki_ge0); + + orion_ge00_init(eth_data, &loki_mbus_dram_info, + GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT, + 0, LOKI_TCLK); } /***************************************************************************** - * GE1 + * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = { - .t_clk = LOKI_TCLK, - .dram = &loki_mbus_dram_info, -}; - -static struct resource loki_ge1_shared_resources[] = { - { - .name = "ge1 base", - .start = GE1_PHYS_BASE + 0x2000, - .end = GE1_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device loki_ge1_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &loki_ge1_shared_data, - }, - .num_resources = 1, - .resource = loki_ge1_shared_resources, -}; - -static struct resource loki_ge1_resources[] = { - { - .name = "ge1 irq", - .start = IRQ_LOKI_GBE_B_INT, - .end = IRQ_LOKI_GBE_B_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_ge1 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = loki_ge1_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &loki_ge1_shared; - loki_ge1.dev.platform_data = eth_data; - writel(0x00079220, GE1_VIRT_BASE + 0x20b0); - platform_device_register(&loki_ge1_shared); - platform_device_register(&loki_ge1); + + orion_ge01_init(eth_data, &loki_mbus_dram_info, + GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT, + 0, LOKI_TCLK); } @@ -187,7 +100,7 @@ static struct platform_device loki_sas = { .name = "mvsas", .id = 0, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(loki_sas_resources), .resource = loki_sas_resources, @@ -203,88 +116,19 @@ void __init loki_sas_init(void) /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port loki_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_LOKI_UART0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = LOKI_TCLK, - }, { - }, -}; - -static struct resource loki_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LOKI_UART0, - .end = IRQ_LOKI_UART0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_uart0 = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = loki_uart0_data, - }, - .resource = loki_uart0_resources, - .num_resources = ARRAY_SIZE(loki_uart0_resources), -}; - void __init loki_uart0_init(void) { - platform_device_register(&loki_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_LOKI_UART0, LOKI_TCLK); } - /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port loki_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_LOKI_UART1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = LOKI_TCLK, - }, { - }, -}; - -static struct resource loki_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_LOKI_UART1, - .end = IRQ_LOKI_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device loki_uart1 = { - .name = "serial8250", - .id = 1, - .dev = { - .platform_data = loki_uart1_data, - }, - .resource = loki_uart1_resources, - .num_resources = ARRAY_SIZE(loki_uart1_resources), -}; - void __init loki_uart1_init(void) { - platform_device_register(&loki_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_LOKI_UART1, LOKI_TCLK); } diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 316ecbf6c58..4eae566dfdc 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) } /* Ok to use the level handler for all types */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); return 0; } @@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void) /* Configure supported IRQ's */ for (i = 0; i < NR_IRQS; i++) { - set_irq_chip(i, &lpc32xx_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &lpc32xx_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } @@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void) __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); /* MIC SUBIRQx interrupts will route handling to the chain handlers */ - set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); - set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); /* Initially disable all wake events */ __raw_writel(0, LPC32XX_CLKPWR_P01_ER); diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index e76d41bb705..b9c80597b7b 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -41,7 +41,7 @@ * DRAM clocking and refresh are slightly different for systems with DDR * DRAM or regular SDRAM devices. If SDRAM is used in the system, the * SDRAM will still be accessible in direct-run mode. In DDR based systems, - * a transistion to direct-run mode will stop all DDR accesses (no clocks). + * a transition to direct-run mode will stop all DDR accesses (no clocks). * Because of this, the code to switch power modes and the code to enter * and exit DRAM self-refresh modes must not be executed in DRAM. A small * section of IRAM is used instead for this. diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 6162ac308c2..b42c909bbee 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -31,19 +31,6 @@ #include <mach/platform.h> #include "common.h" -static cycle_t lpc32xx_clksrc_read(struct clocksource *cs) -{ - return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE)); -} - -static struct clocksource lpc32xx_clksrc = { - .name = "lpc32xx_clksrc", - .rating = 300, - .read = lpc32xx_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int lpc32xx_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) { @@ -170,7 +157,9 @@ static void __init lpc32xx_timer_init(void) __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); - clocksource_register_hz(&lpc32xx_clksrc, clkrate); + + clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE), + "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up); } struct sys_timer lpc32xx_timer = { diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h index ee8b02ed801..7bfb827f3fe 100644 --- a/arch/arm/mach-mmp/include/mach/gpio.h +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -10,7 +10,7 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) -#define NR_BUILTIN_GPIO (192) +#define NR_BUILTIN_GPIO IRQ_GPIO_NUM #define gpio_to_bank(gpio) ((gpio) >> 5) #define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index 4621067c772..713be155a44 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -8,6 +8,15 @@ #define MFP_DRIVE_MEDIUM (0x2 << 13) #define MFP_DRIVE_FAST (0x3 << 13) +#undef MFP_CFG +#undef MFP_CFG_DRV + +#define MFP_CFG(pin, af) \ + (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) + +#define MFP_CFG_DRV(pin, af, drv) \ + (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) + /* GPIO */ #define GPIO0_GPIO MFP_CFG(GPIO0, AF5) #define GPIO1_GPIO MFP_CFG(GPIO1, AF5) diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h index 85bd8a2d84b..d6daeb7e4ef 100644 --- a/arch/arm/mach-mmp/include/mach/uncompress.h +++ b/arch/arm/mach-mmp/include/mach/uncompress.h @@ -14,7 +14,7 @@ #define UART2_BASE (APB_PHYS_BASE + 0x17000) #define UART3_BASE (APB_PHYS_BASE + 0x18000) -static volatile unsigned long *UART; +volatile unsigned long *UART; static inline void putc(char c) { diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index fa037038e7b..d21c5441a3d 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) if (chip->irq_ack) chip->irq_ack(d); - set_irq_chip(irq, chip); + irq_set_chip(irq, chip); set_irq_flags(irq, IRQF_VALID); - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); } } @@ -122,7 +122,7 @@ void __init mmp2_init_icu(void) for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - set_irq_chip(irq, &icu_irq_chip); + irq_set_chip(irq, &icu_irq_chip); set_irq_flags(irq, IRQF_VALID); switch (irq) { @@ -133,7 +133,7 @@ void __init mmp2_init_icu(void) case IRQ_MMP2_SSP_MUX: break; default: - set_irq_handler(irq, handle_level_irq); + irq_set_handler(irq, handle_level_irq); break; } } @@ -149,9 +149,9 @@ void __init mmp2_init_icu(void) init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); - set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); - set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); - set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); - set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); - set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); + irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); } diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c index f86b450cb93..89706a0d08f 100644 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ b/arch/arm/mach-mmp/irq-pxa168.c @@ -48,8 +48,7 @@ void __init icu_init_irq(void) for (irq = 0; irq < 64; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - set_irq_chip(irq, &icu_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index aeb9ae23e6c..99833b9485c 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -9,7 +9,7 @@ * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> * 2008-10-08: Bin Yang <bin.yang@marvell.com> * - * The timers module actually includes three timers, each timer with upto + * The timers module actually includes three timers, each timer with up to * three match comparators. Timer #0 is used here in free-running mode as * the clock source, and match comparator #1 used as clock event device. * diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c index 7ffbd987eb5..805d4ee53f7 100644 --- a/arch/arm/mach-msm/acpuclock-arm11.c +++ b/arch/arm/mach-msm/acpuclock-arm11.c @@ -343,7 +343,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse) } } - /* Set wait states for CPU inbetween frequency changes */ + /* Set wait states for CPU between frequency changes */ reg_clkctl = readl(A11S_CLK_CNTL_ADDR); reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ writel(reg_clkctl, A11S_CLK_CNTL_ADDR); diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 1993721d472..35c7ceeb3f2 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c @@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void) */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - set_irq_handler(i, handle_percpu_irq); + irq_set_handler(i, handle_percpu_irq); } } diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index b3c55f138fc..1163b6fd05d 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void) */ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) - set_irq_handler(i, handle_percpu_irq); + irq_set_handler(i, handle_percpu_irq); } } diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 7f568611547..6a96911b0ad 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -160,10 +160,7 @@ static struct msm_mmc_platform_data qsd8x50_sdc1_data = { static void __init qsd8x50_init_mmc(void) { - if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa()) - vreg_mmc = vreg_get(NULL, "gp6"); - else - vreg_mmc = vreg_get(NULL, "gp5"); + vreg_mmc = vreg_get(NULL, "gp5"); if (IS_ERR(vreg_mmc)) { pr_err("vreg get for vreg_mmc failed (%ld)\n", diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index 31117a4499c..87e1d01edec 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -214,17 +214,17 @@ int __init trout_init_gpio(void) { int i; for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { - set_irq_chip(i, &trout_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &trout_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) gpiochip_add(&msm_gpio_banks[i].chip); - set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); - set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); - set_irq_wake(MSM_GPIO_TO_INT(17), 1); + irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); + irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); + irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1); return 0; } diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c index 44be8464657..f7a9724788b 100644 --- a/arch/arm/mach-msm/board-trout-mmc.c +++ b/arch/arm/mach-msm/board-trout-mmc.c @@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev) if (IS_ERR(vreg_sdslot)) return PTR_ERR(vreg_sdslot); - set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); + irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); if (!opt_disable_sdcard) msm_add_sdcc(2, &trout_sdslot_data, diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index 0de19ec74e3..cc9c4fd7ccc 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c @@ -27,6 +27,9 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/spinlock.h> + +#include <asm/mach/irq.h> + #include <mach/msm_iomap.h> #include "gpiomux.h" @@ -230,18 +233,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio) val, val2); } -static void msm_gpio_irq_ack(unsigned int irq) +static void msm_gpio_irq_ack(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); if (test_bit(gpio, msm_gpio.dual_edge_irqs)) msm_gpio_update_dual_edge_pos(gpio); } -static void msm_gpio_irq_mask(unsigned int irq) +static void msm_gpio_irq_mask(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); @@ -251,9 +254,9 @@ static void msm_gpio_irq_mask(unsigned int irq) spin_unlock_irqrestore(&tlmm_lock, irq_flags); } -static void msm_gpio_irq_unmask(unsigned int irq) +static void msm_gpio_irq_unmask(struct irq_data *d) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); @@ -263,9 +266,9 @@ static void msm_gpio_irq_unmask(unsigned int irq) spin_unlock_irqrestore(&tlmm_lock, irq_flags); } -static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); unsigned long irq_flags; uint32_t bits; @@ -275,14 +278,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) if (flow_type & IRQ_TYPE_EDGE_BOTH) { bits |= BIT(INTR_DECT_CTL); - irq_desc[irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) __set_bit(gpio, msm_gpio.dual_edge_irqs); else __clear_bit(gpio, msm_gpio.dual_edge_irqs); } else { bits &= ~BIT(INTR_DECT_CTL); - irq_desc[irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); __clear_bit(gpio, msm_gpio.dual_edge_irqs); } @@ -310,6 +313,9 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long i; + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); i < NR_GPIO_IRQS; @@ -318,21 +324,22 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, i)); } - desc->chip->ack(irq); + + chained_irq_exit(chip, desc); } -static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); if (on) { if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) - set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); + irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); set_bit(gpio, msm_gpio.wake_irqs); } else { clear_bit(gpio, msm_gpio.wake_irqs); if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) - set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); + irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); } return 0; @@ -340,11 +347,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) static struct irq_chip msm_gpio_irq_chip = { .name = "msmgpio", - .mask = msm_gpio_irq_mask, - .unmask = msm_gpio_irq_unmask, - .ack = msm_gpio_irq_ack, - .set_type = msm_gpio_irq_set_type, - .set_wake = msm_gpio_irq_set_wake, + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, }; static int __devinit msm_gpio_probe(struct platform_device *dev) @@ -361,12 +368,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev) for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); - set_irq_chip(irq, &msm_gpio_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, + irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ, msm_summary_irq_handler); return 0; } @@ -378,7 +385,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev) if (ret < 0) return ret; - set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); + irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); return 0; } diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 176af9dcb8e..5ea273b00da 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) val = readl(msm_chip->regs.int_edge); if (flow_type & IRQ_TYPE_EDGE_BOTH) { writel(val | mask, msm_chip->regs.int_edge); - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } else { writel(val & ~mask, msm_chip->regs.int_edge); - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { msm_chip->both_edge_detect |= mask; @@ -354,9 +354,9 @@ static int __init msm_init_gpio(void) msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.ngpio) j++; - set_irq_chip_data(i, &msm_gpio_chips[j]); - set_irq_chip(i, &msm_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_data(i, &msm_gpio_chips[j]); + irq_set_chip_and_handler(i, &msm_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); } @@ -366,10 +366,10 @@ static int __init msm_init_gpio(void) gpiochip_add(&msm_gpio_chips[i].chip); } - set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); - set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); - set_irq_wake(INT_GPIO_GROUP1, 1); - set_irq_wake(INT_GPIO_GROUP2, 2); + irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); + irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); + irq_set_irq_wake(INT_GPIO_GROUP1, 1); + irq_set_irq_wake(INT_GPIO_GROUP2, 2); return 0; } diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index c98c7591f3b..2f494b6a9d0 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -55,7 +55,7 @@ #include "msm_iomap-8960.h" -/* Virtual addressses shared across all MSM targets. */ +/* Virtual addresses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h deleted file mode 100644 index 3c01000ecc8..00000000000 --- a/arch/arm/mach-msm/include/mach/smp.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_MSM_SMP_H -#define __ASM_ARCH_MSM_SMP_H - -#include <asm/hardware/gic.h> - -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 68c28bbdc96..1b54f807c2d 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c @@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) type = msm_irq_shadow_reg[index].int_type; if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { type |= b; - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { type &= ~b; - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } writel(type, treg); msm_irq_shadow_reg[index].int_type = type; @@ -357,8 +357,7 @@ void __init msm_init_irq(void) writel(3, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { - set_irq_chip(n, &msm_irq_chip); - set_irq_handler(n, handle_level_irq); + irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); set_irq_flags(n, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 0b27d899f40..ea514be390c 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c @@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { writel(readl(treg) | b, treg); - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { writel(readl(treg) & (~b), treg); - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } return 0; } @@ -145,8 +145,7 @@ void __init msm_init_irq(void) writel(1, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { - set_irq_chip(n, &msm_irq_chip); - set_irq_handler(n, handle_level_irq); + irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); set_irq_flags(n, IRQF_VALID); } } diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 0f427bc9444..2034098cf01 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -151,6 +151,8 @@ void __init smp_init_cpus(void) for (i = 0; i < NR_CPUS; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c index cfa808dd489..232f97a0450 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-msm/scm.c @@ -46,7 +46,7 @@ static DEFINE_MUTEX(scm_lock); * @id: command to be executed * @buf: buffer returned from scm_get_command_buffer() * - * An SCM command is layed out in memory as follows: + * An SCM command is laid out in memory as follows: * * ------------------- <--- struct scm_command * | command header | diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index 11b54c7aeb0..689e78c95f3 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) val = readl(sirc_regs.int_type); if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { val |= mask; - irq_desc[d->irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(d->irq, handle_edge_irq); } else { val &= ~mask; - irq_desc[d->irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(d->irq, handle_level_irq); } writel(val, sirc_regs.int_type); @@ -158,15 +158,14 @@ void __init msm_init_sirc(void) wake_enable = 0; for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { - set_irq_chip(i, &sirc_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { - set_irq_chained_handler(sirc_reg_table[i].cascade_irq, + irq_set_chained_handler(sirc_reg_table[i].cascade_irq, sirc_irq_handler); - set_irq_wake(sirc_reg_table[i].cascade_irq, 1); + irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1); } return; } diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 56f920c55b6..38b95e949d1 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -269,7 +269,7 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt) /* Use existing clock_event for cpu 0 */ if (!smp_processor_id()) - return; + return 0; writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 44fb4e55be0..23d3980ef59 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -13,8 +13,6 @@ #include <linux/platform_device.h> #include <linux/serial_8250.h> #include <linux/mbus.h> -#include <linux/mv643xx_eth.h> -#include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> #include <linux/ethtool.h> #include <asm/mach/map.h> @@ -22,11 +20,12 @@ #include <mach/mv78xx0.h> #include <mach/bridge-regs.h> #include <plat/cache-feroceon-l2.h> -#include <plat/ehci-orion.h> #include <plat/orion_nand.h> #include <plat/time.h> +#include <plat/common.h> #include "common.h" +static int get_tclk(void); /***************************************************************************** * Common bits @@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void) /***************************************************************************** * EHCI ****************************************************************************/ -static struct orion_ehci_data mv78xx0_ehci_data = { - .dram = &mv78xx0_mbus_dram_info, - .phy_version = EHCI_PHY_NA, -}; - -static u64 ehci_dmamask = 0xffffffffUL; - - -/***************************************************************************** - * EHCI0 - ****************************************************************************/ -static struct resource mv78xx0_ehci0_resources[] = { - { - .start = USB0_PHYS_BASE, - .end = USB0_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_0, - .end = IRQ_MV78XX0_USB_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci0_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), -}; - void __init mv78xx0_ehci0_init(void) { - platform_device_register(&mv78xx0_ehci0); + orion_ehci_init(&mv78xx0_mbus_dram_info, + USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource mv78xx0_ehci1_resources[] = { - { - .start = USB1_PHYS_BASE, - .end = USB1_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_1, - .end = IRQ_MV78XX0_USB_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci1_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), -}; - void __init mv78xx0_ehci1_init(void) { - platform_device_register(&mv78xx0_ehci1); + orion_ehci_1_init(&mv78xx0_mbus_dram_info, + USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); } /***************************************************************************** * EHCI2 ****************************************************************************/ -static struct resource mv78xx0_ehci2_resources[] = { - { - .start = USB2_PHYS_BASE, - .end = USB2_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_USB_2, - .end = IRQ_MV78XX0_USB_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ehci2 = { - .name = "orion-ehci", - .id = 2, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &mv78xx0_ehci_data, - }, - .resource = mv78xx0_ehci2_resources, - .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), -}; - void __init mv78xx0_ehci2_init(void) { - platform_device_register(&mv78xx0_ehci2); + orion_ehci_2_init(&mv78xx0_mbus_dram_info, + USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); } /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, -}; - -static struct resource mv78xx0_ge00_shared_resources[] = { - { - .name = "ge00 base", - .start = GE00_PHYS_BASE + 0x2000, - .end = GE00_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, { - .name = "ge err irq", - .start = IRQ_MV78XX0_GE_ERR, - .end = IRQ_MV78XX0_GE_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge00_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &mv78xx0_ge00_shared_data, - }, - .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources), - .resource = mv78xx0_ge00_shared_resources, -}; - -static struct resource mv78xx0_ge00_resources[] = { - { - .name = "ge00 irq", - .start = IRQ_MV78XX0_GE00_SUM, - .end = IRQ_MV78XX0_GE00_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge00 = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = mv78xx0_ge00_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge00_shared; - mv78xx0_ge00.dev.platform_data = eth_data; - - platform_device_register(&mv78xx0_ge00_shared); - platform_device_register(&mv78xx0_ge00); + orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, + GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, + IRQ_MV78XX0_GE_ERR, get_tclk()); } /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge01_shared_resources[] = { - { - .name = "ge01 base", - .start = GE01_PHYS_BASE + 0x2000, - .end = GE01_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge01_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 1, - .dev = { - .platform_data = &mv78xx0_ge01_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge01_shared_resources, -}; - -static struct resource mv78xx0_ge01_resources[] = { - { - .name = "ge01 irq", - .start = IRQ_MV78XX0_GE01_SUM, - .end = IRQ_MV78XX0_GE01_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge01 = { - .name = MV643XX_ETH_NAME, - .id = 1, - .num_resources = 1, - .resource = mv78xx0_ge01_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &mv78xx0_ge01_shared; - mv78xx0_ge01.dev.platform_data = eth_data; - - platform_device_register(&mv78xx0_ge01_shared); - platform_device_register(&mv78xx0_ge01); + orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, + GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, + NO_IRQ, get_tclk()); } /***************************************************************************** * GE10 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge10_shared_resources[] = { - { - .name = "ge10 base", - .start = GE10_PHYS_BASE + 0x2000, - .end = GE10_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge10_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 2, - .dev = { - .platform_data = &mv78xx0_ge10_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge10_shared_resources, -}; - -static struct resource mv78xx0_ge10_resources[] = { - { - .name = "ge10 irq", - .start = IRQ_MV78XX0_GE10_SUM, - .end = IRQ_MV78XX0_GE10_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge10 = { - .name = MV643XX_ETH_NAME, - .id = 2, - .num_resources = 1, - .resource = mv78xx0_ge10_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) { u32 dev, rev; - eth_data->shared = &mv78xx0_ge10_shared; - mv78xx0_ge10.dev.platform_data = eth_data; - /* * On the Z0, ge10 and ge11 are internally connected back * to back, and not brought out. @@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - platform_device_register(&mv78xx0_ge10_shared); - platform_device_register(&mv78xx0_ge10); + orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, + GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, + NO_IRQ, get_tclk()); } /***************************************************************************** * GE11 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = { - .t_clk = 0, - .dram = &mv78xx0_mbus_dram_info, - .shared_smi = &mv78xx0_ge00_shared, -}; - -static struct resource mv78xx0_ge11_shared_resources[] = { - { - .name = "ge11 base", - .start = GE11_PHYS_BASE + 0x2000, - .end = GE11_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mv78xx0_ge11_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 3, - .dev = { - .platform_data = &mv78xx0_ge11_shared_data, - }, - .num_resources = 1, - .resource = mv78xx0_ge11_shared_resources, -}; - -static struct resource mv78xx0_ge11_resources[] = { - { - .name = "ge11 irq", - .start = IRQ_MV78XX0_GE11_SUM, - .end = IRQ_MV78XX0_GE11_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_ge11 = { - .name = MV643XX_ETH_NAME, - .id = 3, - .num_resources = 1, - .resource = mv78xx0_ge11_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) { u32 dev, rev; - eth_data->shared = &mv78xx0_ge11_shared; - mv78xx0_ge11.dev.platform_data = eth_data; - /* * On the Z0, ge10 and ge11 are internally connected back * to back, and not brought out. @@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - platform_device_register(&mv78xx0_ge11_shared); - platform_device_register(&mv78xx0_ge11); + orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, + GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, + NO_IRQ, get_tclk()); } /***************************************************************************** - * I2C bus 0 - ****************************************************************************/ - -static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource mv78xx0_i2c_0_resources[] = { - { - .start = I2C_0_PHYS_BASE, - .end = I2C_0_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_I2C_0, - .end = IRQ_MV78XX0_I2C_0, - .flags = IORESOURCE_IRQ, - }, -}; - - -static struct platform_device mv78xx0_i2c_0 = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources), - .resource = mv78xx0_i2c_0_resources, - .dev = { - .platform_data = &mv78xx0_i2c_0_pdata, - }, -}; - -/***************************************************************************** - * I2C bus 1 + * I2C ****************************************************************************/ - -static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource mv78xx0_i2c_1_resources[] = { - { - .start = I2C_1_PHYS_BASE, - .end = I2C_1_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_I2C_1, - .end = IRQ_MV78XX0_I2C_1, - .flags = IORESOURCE_IRQ, - }, -}; - - -static struct platform_device mv78xx0_i2c_1 = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources), - .resource = mv78xx0_i2c_1_resources, - .dev = { - .platform_data = &mv78xx0_i2c_1_pdata, - }, -}; - void __init mv78xx0_i2c_init(void) { - platform_device_register(&mv78xx0_i2c_0); - platform_device_register(&mv78xx0_i2c_1); + orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); + orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); } /***************************************************************************** * SATA ****************************************************************************/ -static struct resource mv78xx0_sata_resources[] = { - { - .name = "sata base", - .start = SATA_PHYS_BASE, - .end = SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_MV78XX0_SATA, - .end = IRQ_MV78XX0_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), - .resource = mv78xx0_sata_resources, -}; - void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &mv78xx0_mbus_dram_info; - mv78xx0_sata.dev.platform_data = sata_data; - platform_device_register(&mv78xx0_sata); + orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, + SATA_PHYS_BASE, IRQ_MV78XX0_SATA); } /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_0, - .end = IRQ_MV78XX0_UART_0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart0 = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = mv78xx0_uart0_data, - }, - .resource = mv78xx0_uart0_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources), -}; - void __init mv78xx0_uart0_init(void) { - platform_device_register(&mv78xx0_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_MV78XX0_UART_0, get_tclk()); } /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_1, - .end = IRQ_MV78XX0_UART_1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart1 = { - .name = "serial8250", - .id = 1, - .dev = { - .platform_data = mv78xx0_uart1_data, - }, - .resource = mv78xx0_uart1_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources), -}; - void __init mv78xx0_uart1_init(void) { - platform_device_register(&mv78xx0_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_MV78XX0_UART_1, get_tclk()); } /***************************************************************************** * UART2 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart2_data[] = { - { - .mapbase = UART2_PHYS_BASE, - .membase = (char *)UART2_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_2, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart2_resources[] = { - { - .start = UART2_PHYS_BASE, - .end = UART2_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_2, - .end = IRQ_MV78XX0_UART_2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart2 = { - .name = "serial8250", - .id = 2, - .dev = { - .platform_data = mv78xx0_uart2_data, - }, - .resource = mv78xx0_uart2_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources), -}; - void __init mv78xx0_uart2_init(void) { - platform_device_register(&mv78xx0_uart2); + orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, + IRQ_MV78XX0_UART_2, get_tclk()); } - /***************************************************************************** * UART3 ****************************************************************************/ -static struct plat_serial8250_port mv78xx0_uart3_data[] = { - { - .mapbase = UART3_PHYS_BASE, - .membase = (char *)UART3_VIRT_BASE, - .irq = IRQ_MV78XX0_UART_3, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource mv78xx0_uart3_resources[] = { - { - .start = UART3_PHYS_BASE, - .end = UART3_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MV78XX0_UART_3, - .end = IRQ_MV78XX0_UART_3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mv78xx0_uart3 = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = mv78xx0_uart3_data, - }, - .resource = mv78xx0_uart3_resources, - .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources), -}; - void __init mv78xx0_uart3_init(void) { - platform_device_register(&mv78xx0_uart3); + orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, + IRQ_MV78XX0_UART_3, get_tclk()); } - /***************************************************************************** * Time handling ****************************************************************************/ @@ -895,13 +400,4 @@ void __init mv78xx0_init(void) #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_l2_init(is_l2_writethrough()); #endif - - mv78xx0_ge00_shared_data.t_clk = tclk; - mv78xx0_ge01_shared_data.t_clk = tclk; - mv78xx0_ge10_shared_data.t_clk = tclk; - mv78xx0_ge11_shared_data.t_clk = tclk; - mv78xx0_uart0_data[0].uartclk = tclk; - mv78xx0_uart1_data[0].uartclk = tclk; - mv78xx0_uart2_data[0].uartclk = tclk; - mv78xx0_uart3_data[0].uartclk = tclk; } diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 08da497c39c..3e24431bb5e 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void) orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index 65b72c454cb..59b7686b920 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> +#include <plat/mpp.h> #include <asm/gpio.h> #include <mach/hardware.h> #include "common.h" @@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void) return 0; } -#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) -#define MPP_NR_REGS (1 + MPP_MAX/8) - void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { - u32 mpp_ctrl[MPP_NR_REGS]; - unsigned int variant_mask; - int i; - - variant_mask = mv78xx0_variant(); - if (!variant_mask) - return; - - printk(KERN_DEBUG "initial MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - mpp_ctrl[i] = readl(MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); - - for ( ; *mpp_list; mpp_list++) { - unsigned int num = MPP_NUM(*mpp_list); - unsigned int sel = MPP_SEL(*mpp_list); - int shift, gpio_mode; - - if (num > MPP_MAX) { - printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP " - "number (%u)\n", num); - continue; - } - if (!(*mpp_list & variant_mask)) { - printk(KERN_WARNING - "mv78xx0_mpp_conf: requested MPP%u config " - "unavailable on this hardware\n", num); - continue; - } - - shift = (num & 7) << 2; - mpp_ctrl[num / 8] &= ~(0xf << shift); - mpp_ctrl[num / 8] |= sel << shift; - - gpio_mode = 0; - if (*mpp_list & MPP_INPUT_MASK) - gpio_mode |= GPIO_INPUT_OK; - if (*mpp_list & MPP_OUTPUT_MASK) - gpio_mode |= GPIO_OUTPUT_OK; - if (sel != 0) - gpio_mode = 0; - orion_gpio_set_valid(num, gpio_mode); - } - - printk(KERN_DEBUG " final MPP regs:"); - for (i = 0; i < MPP_NR_REGS; i++) { - writel(mpp_ctrl[i], MPP_CTRL(i)); - printk(" %08x", mpp_ctrl[i]); - } - printk("\n"); + orion_mpp_conf(mpp_list, mv78xx0_variant(), + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h index 80840b781ea..b61b5092712 100644 --- a/arch/arm/mach-mv78xx0/mpp.h +++ b/arch/arm/mach-mv78xx0/mpp.h @@ -19,14 +19,8 @@ /* may be output signal */ ((!!(_out)) << 13) | \ /* available on A0 */ ((!!(_78100_A0)) << 14)) -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - /* num sel i o 78100_A0 */ -#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0) -#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0) - #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig deleted file mode 100644 index 340809a7d23..00000000000 --- a/arch/arm/mach-mx3/Kconfig +++ /dev/null @@ -1,257 +0,0 @@ -if ARCH_MX3 - -# ARCH_MX31 and ARCH_MX35 are left for compatibility -# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. -# To easily distinguish good and reviewed from unreviewed usages new (and IMHO -# more sensible) names are used: SOC_IMX31 and SOC_IMX35 -config ARCH_MX31 - bool - -config ARCH_MX35 - bool - -config SOC_IMX31 - bool - select IMX_HAVE_PLATFORM_MXC_RNGA - select ARCH_MXC_AUDMUX_V2 - select ARCH_MX31 - select MXC_AVIC - -config SOC_IMX35 - bool - select ARCH_MXC_IOMUX_V3 - select ARCH_MXC_AUDMUX_V2 - select HAVE_EPIT - select ARCH_MX35 - select MXC_AVIC - -comment "MX3 platforms:" - -config MACH_MX31ADS - bool "Support MX31ADS platforms" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - default y - help - Include support for MX31ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31ADS_WM1133_EV1 - bool "Support Wolfson Microelectronics 1133-EV1 module" - depends on MACH_MX31ADS - depends on MFD_WM8350_I2C - depends on REGULATOR_WM8350 - select MFD_WM8350_CONFIG_MODE_0 - select MFD_WM8352_CONFIG_MODE_0 - help - Include support for the Wolfson Microelectronics 1133-EV1 PMU - and audio module for the MX31ADS platform. - -config MACH_PCM037 - bool "Support Phytec pcm037 (i.MX31) platforms" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select MXC_ULPI if USB_ULPI - help - Include support for Phytec pcm037 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_PCM037_EET - bool "Support pcm037 EET board extensions" - depends on MACH_PCM037 - select IMX_HAVE_PLATFORM_SPI_IMX - help - Add support for PCM037 EET baseboard extensions. If you are using the - OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel - command-line parameter. - -config MACH_MX31LITE - bool "Support MX31 LITEKIT (LogicPD)" - select SOC_IMX31 - select MXC_ULPI if USB_ULPI - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - help - Include support for MX31 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31_3DS - bool "Support MX31PDK (3DS)" - select SOC_IMX31 - select MXC_DEBUG_BOARD - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for MX31PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31_3DS_MXC_NAND_USE_BBT - bool "Make the MXC NAND driver use the in flash Bad Block Table" - depends on MACH_MX31_3DS - depends on MTD_NAND_MXC - help - Enable this if you want that the MXC NAND driver uses the in flash - Bad Block Table to know what blocks are bad instead of scanning the - entire flash looking for bad block markers. - -config MACH_MX31MOBOARD - bool "Support mx31moboard platforms (EPFL Mobots group)" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for mx31moboard platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31LILLY - bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_ULPI if USB_ULPI - help - Include support for mx31 based LILLY1131 modules. This includes - specific configurations for the board and its peripherals. - -config MACH_QONG - bool "Support Dave/DENX QongEVB-LITE platform" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - help - Include support for Dave/DENX QongEVB-LITE platform. This includes - specific configurations for the board and its peripherals. - -config MACH_PCM043 - bool "Support Phytec pcm043 (i.MX35) platforms" - select SOC_IMX35 - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI - help - Include support for Phytec pcm043 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_ARMADILLO5X0 - bool "Support Atmark Armadillo-500 Development Base Board" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select MXC_ULPI if USB_ULPI - help - Include support for Atmark Armadillo-500 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_MX35_3DS - bool "Support MX35PDK platform" - select SOC_IMX35 - select MXC_DEBUG_BOARD - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for MX35PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_KZM_ARM11_01 - bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - help - Include support for KZM-ARM11-01. This includes specific - configurations for the board and its peripherals. - -config MACH_BUG - bool "Support Buglabs BUGBase platform" - select SOC_IMX31 - select IMX_HAVE_PLATFORM_IMX_UART - default y - help - Include support for BUGBase 1.3 platform. This includes specific - configurations for the board and its peripherals. - -config MACH_EUKREA_CPUIMX35 - bool "Support Eukrea CPUIMX35 Platform" - select SOC_IMX35 - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_ULPI if USB_ULPI - help - Include support for Eukrea CPUIMX35 platform. This includes - specific configurations for the board and its peripherals. - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX35 - default MACH_EUKREA_MBIMXSD35_BASEBOARD - -config MACH_EUKREA_MBIMXSD35_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_IMX_SSI - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -config MACH_VPR200 - bool "Support VPR200 platform" - select SOC_IMX35 - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - help - Include support for VPR200 platform. This includes specific - configurations for the board and its peripherals. - -endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile deleted file mode 100644 index a54faf2cf5f..00000000000 --- a/arch/arm/mach-mx3/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := mm.o devices.o cpu.o -obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o -obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o -obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o -obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o -obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o -obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ - mx31moboard-marxbot.o mx31moboard-smartbot.o -obj-$(CONFIG_MACH_QONG) += mach-qong.o -obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o -obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o -obj-$(CONFIG_MACH_BUG) += mach-bug.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o -obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot deleted file mode 100644 index e1dd366f836..00000000000 --- a/arch/arm/mach-mx3/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c deleted file mode 100644 index b6672db788f..00000000000 --- a/arch/arm/mach-mx3/devices.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/dma-mapping.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/serial.h> -#include <linux/gpio.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/common.h> -#include <mach/mx3_camera.h> - -#include "devices.h" - -/* i.MX31 Image Processing Unit */ - -/* The resource order is important! */ -static struct resource mx3_ipu_rsrc[] = { - { - .start = MX3x_IPU_CTRL_BASE_ADDR, - .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F, - .flags = IORESOURCE_MEM, - }, { - .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88, - .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3, - .flags = IORESOURCE_MEM, - }, { - .start = MX3x_INT_IPU_SYN, - .end = MX3x_INT_IPU_SYN, - .flags = IORESOURCE_IRQ, - }, { - .start = MX3x_INT_IPU_ERR, - .end = MX3x_INT_IPU_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx3_ipu = { - .name = "ipu-core", - .id = -1, - .num_resources = ARRAY_SIZE(mx3_ipu_rsrc), - .resource = mx3_ipu_rsrc, -}; - -static struct resource fb_resources[] = { - { - .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4, - .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mx3_fb = { - .name = "mx3_sdc_fb", - .id = -1, - .num_resources = ARRAY_SIZE(fb_resources), - .resource = fb_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource camera_resources[] = { - { - .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60, - .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mx3_camera = { - .name = "mx3-camera", - .id = 0, - .num_resources = ARRAY_SIZE(camera_resources), - .resource = camera_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource imx_rtc_resources[] = { - { - .start = MX31_RTC_BASE_ADDR, - .end = MX31_RTC_BASE_ADDR + 0x3fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX31_INT_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_rtc_device0 = { - .name = "mxc_rtc", - .id = -1, - .num_resources = ARRAY_SIZE(imx_rtc_resources), - .resource = imx_rtc_resources, -}; diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h deleted file mode 100644 index 121962c568d..00000000000 --- a/arch/arm/mach-mx3/devices.h +++ /dev/null @@ -1,4 +0,0 @@ -extern struct platform_device mx3_ipu; -extern struct platform_device mx3_fb; -extern struct platform_device mx3_camera; -extern struct platform_device imx_rtc_device0; diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c deleted file mode 100644 index 54d7174b420..00000000000 --- a/arch/arm/mach-mx3/mm.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/err.h> - -#include <asm/pgtable.h> -#include <asm/mach/map.h> -#include <asm/hardware/cache-l2x0.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-v3.h> -#include <mach/gpio.h> -#include <mach/irqs.h> - -#ifdef CONFIG_SOC_IMX31 -static struct map_desc mx31_io_desc[] __initdata = { - imx_map_entry(MX31, X_MEMC, MT_DEVICE), - imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), - imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx31_map_io(void) -{ - iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); -} - -void __init imx31_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX31); - mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); -} - -static struct mxc_gpio_port imx31_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), -}; - -void __init mx31_init_irq(void) -{ - mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); - mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports)); -} -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -static struct map_desc mx35_io_desc[] __initdata = { - imx_map_entry(MX35, X_MEMC, MT_DEVICE), - imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), - imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), -}; - -void __init mx35_map_io(void) -{ - iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); -} - -void __init imx35_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); -} - -static struct mxc_gpio_port imx35_gpio_ports[] = { - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), - DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), -}; - -void __init mx35_init_irq(void) -{ - mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); - mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports)); -} -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_CACHE_L2X0 -static int mxc_init_l2x0(void) -{ - void __iomem *l2x0_base; - void __iomem *clkctl_base; -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (IS_ERR(l2x0_base)) { - printk(KERN_ERR "remapping L2 cache area failed with %ld\n", - PTR_ERR(l2x0_base)); - return 0; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); - - return 0; -} - -arch_initcall(mxc_init_l2x0); -#endif diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 83ee08847d4..799fbc40e53 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -1,11 +1,11 @@ -if ARCH_MX5 -# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single +if ARCH_MX503 || ARCH_MX51 +# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single # image. So for most time, SOC_IMX50/51/53 should be used. -config ARCH_MX50 +config ARCH_MX5 bool -config ARCH_MX51 +config ARCH_MX50 bool config ARCH_MX53 @@ -13,27 +13,54 @@ config ARCH_MX53 config SOC_IMX50 bool + select CPU_V7 + select ARM_L1_CACHE_SHIFT_6 select MXC_TZIC select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 select ARCH_HAS_CPUFREQ + select ARCH_MX5 select ARCH_MX50 config SOC_IMX51 bool + select CPU_V7 + select ARM_L1_CACHE_SHIFT_6 select MXC_TZIC select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 select ARCH_HAS_CPUFREQ - select ARCH_MX51 + select ARCH_MX5 config SOC_IMX53 bool + select CPU_V7 + select ARM_L1_CACHE_SHIFT_6 select MXC_TZIC select ARCH_MXC_IOMUX_V3 + select ARCH_MX5 select ARCH_MX53 -comment "MX5 platforms:" +if ARCH_MX50_SUPPORTED +#comment "i.MX50 machines:" + +config MACH_MX50_RDP + bool "Support MX50 reference design platform" + depends on BROKEN + select SOC_IMX50 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_FEC + help + Include support for MX50 reference design platform (RDP) board. This + includes specific configurations for the board and its peripherals. + +endif # ARCH_MX50_SUPPORTED + +if ARCH_MX51 +comment "i.MX51 machines:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" @@ -136,6 +163,11 @@ config MACH_MX51_EFIKASB Include support for Genesi Efika Smartbook. This includes specific configurations for the board and its peripherals. +endif # ARCH_MX51 + +if ARCH_MX53_SUPPORTED +comment "i.MX53 machines:" + config MACH_MX53_EVK bool "Support MX53 EVK platforms" select SOC_IMX53 @@ -154,6 +186,7 @@ config MACH_MX53_SMD select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help Include support for MX53 SMD platform. This includes specific configurations for the board and its peripherals. @@ -165,21 +198,11 @@ config MACH_MX53_LOCO select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_GPIO_KEYS help Include support for MX53 LOCO platform. This includes specific configurations for the board and its peripherals. -config MACH_MX50_RDP - bool "Support MX50 reference design platform" - depends on BROKEN - select SOC_IMX50 - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select IMX_HAVE_PLATFORM_FEC - help - Include support for MX50 reference design platform (RDP) board. This - includes specific configurations for the board and its peripherals. +endif # ARCH_MX53_SUPPORTED endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 4f63048be3c..0b9338cec51 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,7 +3,7 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o +obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o obj-$(CONFIG_SOC_IMX50) += mm-mx50.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index d0296a94c47..4efa02ee163 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -23,13 +23,11 @@ #include <linux/io.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/fsl_devices.h> #include <mach/eukrea-baseboards.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <mach/mxc_ehci.h> #include <asm/irq.h> #include <asm/setup.h> diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 29b180823bf..5ef25a59614 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -23,7 +23,6 @@ #include <linux/io.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/fsl_devices.h> #include <linux/i2c-gpio.h> #include <linux/spi/spi.h> #include <linux/can/platform/mcp251x.h> @@ -32,7 +31,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <mach/mxc_ehci.h> #include <asm/irq.h> #include <asm/setup.h> diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index dedf7f2d6d0..11210e1ae42 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -23,7 +23,6 @@ #include <linux/gpio.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/fsl_devices.h> #include <mach/common.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index b2ecd194e76..c7b3fabf50f 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -16,9 +16,6 @@ #include <linux/gpio.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/fsl_devices.h> -#include <linux/fec.h> -#include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/spi/flash.h> #include <linux/spi/spi.h> @@ -26,7 +23,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <mach/mxc_ehci.h> #include <asm/irq.h> #include <asm/setup.h> @@ -208,18 +204,16 @@ static inline void babbage_usbhub_reset(void) { int ret; - /* Bring USB hub out of reset */ - ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7"); + /* Reset USB hub */ + ret = gpio_request_one(BABBAGE_USB_HUB_RESET, + GPIOF_OUT_INIT_LOW, "GPIO1_7"); if (ret) { printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); return; } - gpio_direction_output(BABBAGE_USB_HUB_RESET, 0); - /* USB HUB RESET - De-assert USB HUB RESET_N */ - msleep(1); - gpio_set_value(BABBAGE_USB_HUB_RESET, 0); - msleep(1); + msleep(2); + /* Deassert reset */ gpio_set_value(BABBAGE_USB_HUB_RESET, 1); } @@ -228,13 +222,12 @@ static inline void babbage_fec_reset(void) int ret; /* reset FEC PHY */ - ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); + ret = gpio_request_one(BABBAGE_FEC_PHY_RESET, + GPIOF_OUT_INIT_LOW, "fec-phy-reset"); if (ret) { printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); return; } - gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 0); msleep(1); gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); } @@ -362,7 +355,7 @@ static void __init mx51_babbage_init(void) /* Set the PAD settings for the pwr key. */ mxc_iomux_v3_setup_pad(power_key); - imx51_add_gpio_keys(&imx_button_data); + imx_add_gpio_keys(&imx_button_data); imx51_add_imx_i2c(0, &babbage_i2c_data); imx51_add_imx_i2c(1, &babbage_i2c_data); diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index acab1911cb3..6e362315291 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -22,7 +22,6 @@ #include <linux/input.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/fsl_devices.h> #include <linux/spi/flash.h> #include <linux/spi/spi.h> #include <linux/mfd/mc13892.h> @@ -32,8 +31,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <mach/i2c.h> -#include <mach/mxc_ehci.h> #include <asm/irq.h> #include <asm/setup.h> @@ -252,7 +249,7 @@ static void __init mx51_efikamx_init(void) } platform_device_register(&mx51_efikamx_leds_device); - imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); + imx_add_gpio_keys(&mx51_efikamx_powerkey_data); if (system_rev == 0x11) { gpio_request(EFIKAMX_RESET1_1, "reset"); diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c index db04ce8462d..474fc6e4c6d 100644 --- a/arch/arm/mach-mx5/board-mx51_efikasb.c +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c @@ -22,7 +22,6 @@ #include <linux/input.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/fsl_devices.h> #include <linux/spi/flash.h> #include <linux/spi/spi.h> #include <linux/mfd/mc13892.h> @@ -35,8 +34,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <mach/i2c.h> -#include <mach/mxc_ehci.h> #include <asm/irq.h> #include <asm/setup.h> @@ -260,7 +257,7 @@ static void __init efikasb_board_init(void) imx51_add_sdhci_esdhc_imx(1, NULL); platform_device_register(&mx51_efikasb_leds_device); - imx51_add_gpio_keys(&mx51_efikasb_keys_data); + imx_add_gpio_keys(&mx51_efikasb_keys_data); } diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 7b5735c5ea5..f87d571882c 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -21,7 +21,6 @@ #include <linux/init.h> #include <linux/clk.h> -#include <linux/fec.h> #include <linux/delay.h> #include <linux/gpio.h> #include <linux/spi/flash.h> @@ -31,10 +30,9 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx53.h> -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) @@ -82,15 +80,14 @@ static inline void mx53_evk_fec_reset(void) int ret; /* reset FEC PHY */ - ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); + ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, + "fec-phy-reset"); if (ret) { printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); return; } - gpio_direction_output(SMD_FEC_PHY_RST, 0); - gpio_set_value(SMD_FEC_PHY_RST, 0); msleep(1); - gpio_set_value(SMD_FEC_PHY_RST, 1); + gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); } static struct fec_platform_data mx53_evk_fec_pdata = { diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 0a18f8d23eb..1b947e8c9c0 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -20,13 +20,11 @@ #include <linux/init.h> #include <linux/clk.h> -#include <linux/fec.h> #include <linux/delay.h> #include <linux/gpio.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx53.h> #include <asm/mach-types.h> @@ -36,6 +34,9 @@ #include "crm_regs.h" #include "devices-imx53.h" +#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) +#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) +#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) static iomux_v3_cfg_t mx53_loco_pads[] = { @@ -180,6 +181,27 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { MX53_PAD_GPIO_8__GPIO1_8, }; +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +{ \ + .gpio = gpio_num, \ + .type = EV_KEY, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ + .wakeup = wake, \ +} + +static struct gpio_keys_button loco_buttons[] = { + GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), + GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), + GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), +}; + +static const struct gpio_keys_platform_data loco_button_data __initconst = { + .buttons = loco_buttons, + .nbuttons = ARRAY_SIZE(loco_buttons), +}; + static inline void mx53_loco_fec_reset(void) { int ret; @@ -215,6 +237,7 @@ static void __init mx53_loco_board_init(void) imx53_add_imx_i2c(1, &mx53_loco_i2c_data); imx53_add_sdhci_esdhc_imx(0, NULL); imx53_add_sdhci_esdhc_imx(2, NULL); + imx_add_gpio_keys(&loco_button_data); } static void __init mx53_loco_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 31e173267ed..817c08938f5 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -20,13 +20,11 @@ #include <linux/init.h> #include <linux/clk.h> -#include <linux/fec.h> #include <linux/delay.h> #include <linux/gpio.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx53.h> #include <asm/mach-types.h> @@ -52,6 +50,31 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { /* I2C1 */ MX53_PAD_CSI0_DAT8__I2C1_SDA, MX53_PAD_CSI0_DAT9__I2C1_SCL, + /* SD1 */ + MX53_PAD_SD1_CMD__ESDHC1_CMD, + MX53_PAD_SD1_CLK__ESDHC1_CLK, + MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD2 */ + MX53_PAD_SD2_CMD__ESDHC2_CMD, + MX53_PAD_SD2_CLK__ESDHC2_CLK, + MX53_PAD_SD2_DATA0__ESDHC2_DAT0, + MX53_PAD_SD2_DATA1__ESDHC2_DAT1, + MX53_PAD_SD2_DATA2__ESDHC2_DAT2, + MX53_PAD_SD2_DATA3__ESDHC2_DAT3, + /* SD3 */ + MX53_PAD_PATA_DATA8__ESDHC3_DAT0, + MX53_PAD_PATA_DATA9__ESDHC3_DAT1, + MX53_PAD_PATA_DATA10__ESDHC3_DAT2, + MX53_PAD_PATA_DATA11__ESDHC3_DAT3, + MX53_PAD_PATA_DATA0__ESDHC3_DAT4, + MX53_PAD_PATA_DATA1__ESDHC3_DAT5, + MX53_PAD_PATA_DATA2__ESDHC3_DAT6, + MX53_PAD_PATA_DATA3__ESDHC3_DAT7, + MX53_PAD_PATA_IORDY__ESDHC3_CLK, + MX53_PAD_PATA_RESET_B__ESDHC3_CMD, }; static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { @@ -97,6 +120,9 @@ static void __init mx53_smd_board_init(void) imx53_add_fec(&mx53_smd_fec_data); imx53_add_imx2_wdt(0, NULL); imx53_add_imx_i2c(0, &mx53_smd_i2c_data); + imx53_add_sdhci_esdhc_imx(0, NULL); + imx53_add_sdhci_esdhc_imx(1, NULL); + imx53_add_sdhci_esdhc_imx(2, NULL); } static void __init mx53_smd_timer_init(void) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 652ace41382..6b89c1bf4eb 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = { .disable = _clk_ccgr_disable_inwait, }; +static struct clk gpc_dvfs_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, +}; + static struct clk gpt_32k_clk = { .id = 0, .parent = &ckil_clk, @@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) + _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) }; static struct clk_lookup mx53_lookups[] = { @@ -1511,6 +1519,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&iim_clk); mx51_revision(); clk_disable(&iim_clk); + mx51_display_revision(); /* move usb_phy_clk to 24MHz */ clk_set_parent(&usb_phy1_clk, &osc_clk); @@ -1554,6 +1563,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&iim_clk); mx53_revision(); clk_disable(&iim_clk); + mx53_display_revision(); /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk, &pll2_sw_clk); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index df46b5e6085..86f87da59c6 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -21,6 +21,7 @@ static int cpu_silicon_rev = -1; #define IIM_SREV 0x24 +#define MX50_HW_ADADIG_DIGPROG 0xB0 static int get_mx51_srev(void) { @@ -51,6 +52,26 @@ int mx51_revision(void) } EXPORT_SYMBOL(mx51_revision); +void mx51_display_revision(void) +{ + int rev; + char *srev; + rev = mx51_revision(); + + switch (rev) { + case IMX_CHIP_REVISION_2_0: + srev = IMX_CHIP_REVISION_2_0_STRING; + break; + case IMX_CHIP_REVISION_3_0: + srev = IMX_CHIP_REVISION_3_0_STRING; + break; + default: + srev = IMX_CHIP_REVISION_UNKNOWN_STRING; + } + printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); +} +EXPORT_SYMBOL(mx51_display_revision); + #ifdef CONFIG_NEON /* @@ -107,6 +128,67 @@ int mx53_revision(void) } EXPORT_SYMBOL(mx53_revision); +static int get_mx50_srev(void) +{ + void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K); + u32 rev; + + if (!anatop) { + cpu_silicon_rev = -EINVAL; + return 0; + } + + rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); + rev &= 0xff; + + iounmap(anatop); + if (rev == 0x0) + return IMX_CHIP_REVISION_1_0; + else if (rev == 0x1) + return IMX_CHIP_REVISION_1_1; + return 0; +} + +/* + * Returns: + * the silicon revision of the cpu + * -EINVAL - not a mx50 + */ +int mx50_revision(void) +{ + if (!cpu_is_mx50()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = get_mx50_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx50_revision); + +void mx53_display_revision(void) +{ + int rev; + char *srev; + rev = mx53_revision(); + + switch (rev) { + case IMX_CHIP_REVISION_1_0: + srev = IMX_CHIP_REVISION_1_0_STRING; + break; + case IMX_CHIP_REVISION_2_0: + srev = IMX_CHIP_REVISION_2_0_STRING; + break; + case IMX_CHIP_REVISION_2_1: + srev = IMX_CHIP_REVISION_2_1_STRING; + break; + default: + srev = IMX_CHIP_REVISION_UNKNOWN_STRING; + } + printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); +} +EXPORT_SYMBOL(mx53_display_revision); + static int __init post_cpu_init(void) { unsigned int reg; diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h index c9e42823c7e..7216667eaaf 100644 --- a/arch/arm/mach-mx5/devices-imx50.h +++ b/arch/arm/mach-mx5/devices-imx50.h @@ -21,14 +21,14 @@ #include <mach/mx50.h> #include <mach/devices-common.h> -extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[]; #define imx50_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) -extern const struct imx_fec_data imx50_fec_data __initconst; +extern const struct imx_fec_data imx50_fec_data; #define imx50_add_fec(pdata) \ imx_add_fec(&imx50_fec_data, pdata) -extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx50_imx_i2c_data[]; #define imx50_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 7fff485e560..e11bc0e0ec4 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -9,49 +9,46 @@ #include <mach/mx51.h> #include <mach/devices-common.h> -extern const struct imx_fec_data imx51_fec_data __initconst; +extern const struct imx_fec_data imx51_fec_data; #define imx51_add_fec(pdata) \ imx_add_fec(&imx51_fec_data, pdata) -#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata) - -extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; #define imx51_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) -extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst; +extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; #define imx51_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) -extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[]; #define imx51_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) -extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; +extern const struct imx_mxc_nand_data imx51_mxc_nand_data; #define imx51_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) -extern const struct imx_sdhci_esdhc_imx_data -imx51_sdhci_esdhc_imx_data[] __initconst; +extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[]; #define imx51_add_sdhci_esdhc_imx(id, pdata) \ imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) -extern const struct imx_spi_imx_data imx51_cspi_data __initconst; +extern const struct imx_spi_imx_data imx51_cspi_data; #define imx51_add_cspi(pdata) \ imx_add_spi_imx(&imx51_cspi_data, pdata) -extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; +extern const struct imx_spi_imx_data imx51_ecspi_data[]; #define imx51_add_ecspi(id, pdata) \ imx_add_spi_imx(&imx51_ecspi_data[id], pdata) -extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst; +extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; #define imx51_add_imx2_wdt(id, pdata) \ imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) -extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst; +extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; #define imx51_add_mxc_pwm(id) \ imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) -extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst; +extern const struct imx_imx_keypad_data imx51_imx_keypad_data; #define imx51_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index 9251008dad1..48f4c8cc42f 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -8,28 +8,27 @@ #include <mach/mx53.h> #include <mach/devices-common.h> -extern const struct imx_fec_data imx53_fec_data __initconst; +extern const struct imx_fec_data imx53_fec_data; #define imx53_add_fec(pdata) \ imx_add_fec(&imx53_fec_data, pdata) -extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst; +extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[]; #define imx53_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) -extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst; +extern const struct imx_imx_i2c_data imx53_imx_i2c_data[]; #define imx53_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata) -extern const struct imx_sdhci_esdhc_imx_data -imx53_sdhci_esdhc_imx_data[] __initconst; +extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[]; #define imx53_add_sdhci_esdhc_imx(id, pdata) \ imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) -extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; +extern const struct imx_spi_imx_data imx53_ecspi_data[]; #define imx53_add_ecspi(id, pdata) \ imx_add_spi_imx(&imx53_ecspi_data[id], pdata) -extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst; +extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; #define imx53_add_imx2_wdt(id, pdata) \ imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index e83ffadb65f..97292d20f1f 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -18,13 +18,11 @@ #include <linux/io.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/fsl_devices.h> #include <linux/i2c/tsc2007.h> #include <linux/leds.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx51.h> #include <asm/mach/arch.h> @@ -212,7 +210,7 @@ void __init eukrea_mbimx51_baseboard_init(void) gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); gpio_direction_input(MBIMX51_TSC2007_GPIO); - set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); + irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); i2c_register_board_info(1, mbimx51_i2c_devices, ARRAY_SIZE(mbimx51_i2c_devices)); diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index c372a437369..31c871ec46a 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c @@ -27,7 +27,6 @@ #include <linux/irq.h> #include <linux/leds.h> #include <linux/platform_device.h> -#include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/i2c.h> @@ -38,7 +37,6 @@ #include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> #include <mach/iomux-mx51.h> #include <mach/audmux.h> @@ -67,6 +65,10 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { MX51_PAD_SD1_DATA1__SD1_DATA1, MX51_PAD_SD1_DATA2__SD1_DATA2, MX51_PAD_SD1_DATA3__SD1_DATA3, + /* SD1 CD */ + _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + PAD_CTL_PKE | PAD_CTL_SRE_FAST | + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; #define GPIO_LED1 IMX_GPIO_NR(3, 30) @@ -104,23 +106,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { }, }; -static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = { +static const struct gpio_keys_platform_data + eukrea_mbimxsd_button_data __initconst = { .buttons = eukrea_mbimxsd_gpio_buttons, .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), }; -static struct platform_device eukrea_mbimxsd_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &eukrea_mbimxsd_button_data, - } -}; - static struct platform_device *platform_devices[] __initdata = { &eukrea_mbimxsd_leds_gpio, - &eukrea_mbimxsd_button_device, }; static const struct imxuart_platform_data uart_pdata __initconst = { @@ -162,4 +155,5 @@ void __init eukrea_mbimxsd51_baseboard_init(void) ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx_add_gpio_keys(&eukrea_mbimxsd_button_data); } diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index 51a67fc7f0e..56739c23aca 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c @@ -20,7 +20,6 @@ #include <linux/input.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/fsl_devices.h> #include <linux/spi/flash.h> #include <linux/spi/spi.h> #include <linux/mfd/mc13892.h> @@ -30,8 +29,6 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/iomux-mx51.h> -#include <mach/i2c.h> -#include <mach/mxc_ehci.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -42,7 +39,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <asm/mach-types.h> #include "devices-imx51.h" #include "devices.h" @@ -572,8 +568,10 @@ static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = { static struct mc13xxx_platform_data mx51_efika_mc13892_data = { .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR, - .num_regulators = ARRAY_SIZE(mx51_efika_regulators), - .regulators = mx51_efika_regulators, + .regulators = { + .num_regulators = ARRAY_SIZE(mx51_efika_regulators), + .regulators = mx51_efika_regulators, + }, }; static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c new file mode 100644 index 00000000000..76ae8dc33e0 --- /dev/null +++ b/arch/arm/mach-mx5/system.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/platform_device.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include "crm_regs.h" + +/* set cpu low power mode before WFI instruction. This function is called + * mx5 because it can be used for mx50, mx51, and mx53.*/ +void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + u32 plat_lpc, arm_srpgcr, ccm_clpcr; + u32 empgc0, empgc1; + int stop_mode = 0; + + /* always allow platform to issue a deep sleep mode request */ + plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + ~(MXC_CORTEXA8_PLAT_LPC_DSM); + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; + break; + case WAIT_UNCLOCKED_POWER_OFF: + case STOP_POWER_OFF: + plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM + | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; + if (mode == WAIT_UNCLOCKED_POWER_OFF) { + ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; + ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; + stop_mode = 0; + } else { + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + stop_mode = 1; + } + arm_srpgcr |= MXC_SRPGCR_PCR; + + if (tzic_enable_wake(1) != 0) + return; + break; + case STOP_POWER_ON: + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + break; + default: + printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); + return; + } + + __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); + + /* Enable NEON SRPG for all but MX50TO1.0. */ + if (mx50_revision() != IMX_CHIP_REVISION_1_0) + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + + if (stop_mode) { + empgc0 |= MXC_SRPGCR_PCR; + empgc1 |= MXC_SRPGCR_PCR; + + __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); + } +} diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig deleted file mode 100644 index 8e5fa38ebb6..00000000000 --- a/arch/arm/mach-mxc91231/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -if ARCH_MXC91231 - -comment "MXC91231 platforms:" - -config MACH_MAGX_ZN5 - bool "Support Motorola Zn5 GSM phone" - default n - help - Include support for Motorola Zn5 GSM phone. - -endif diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile deleted file mode 100644 index 011d5e19712..00000000000 --- a/arch/arm/mach-mxc91231/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y := mm.o clock.o devices.o system.o iomux.o -obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot deleted file mode 100644 index 9939a19d99a..00000000000 --- a/arch/arm/mach-mxc91231/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x90008000 -params_phys-y := 0x90000100 -initrd_phys-y := 0x90800000 diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c deleted file mode 100644 index 9fab505f1eb..00000000000 --- a/arch/arm/mach-mxc91231/clock.c +++ /dev/null @@ -1,640 +0,0 @@ -#include <linux/clk.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <mach/clock.h> -#include <mach/hardware.h> -#include <mach/common.h> - -#include <asm/bug.h> -#include <asm/div64.h> - -#include "crm_regs.h" - -#define CRM_SMALL_DIVIDER(base, name) \ - crm_small_divider(base, \ - base ## _ ## name ## _OFFSET, \ - base ## _ ## name ## _MASK) -#define CRM_1DIVIDER(base, name) \ - crm_divider(base, \ - base ## _ ## name ## _OFFSET, \ - base ## _ ## name ## _MASK, 1) -#define CRM_16DIVIDER(base, name) \ - crm_divider(base, \ - base ## _ ## name ## _OFFSET, \ - base ## _ ## name ## _MASK, 16) - -static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask) -{ - static const u32 crm_small_dividers[] = { - 2, 3, 4, 5, 6, 8, 10, 12 - }; - u8 idx; - - idx = (__raw_readl(reg) & mask) >> offset; - if (idx > 7) - return 1; - - return crm_small_dividers[idx]; -} - -static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z) -{ - u32 div; - div = (__raw_readl(reg) & mask) >> offset; - return div ? div : z; -} - -static int _clk_1bit_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= 1 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void _clk_1bit_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(1 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -static int _clk_3bit_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= 0x7 << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void _clk_3bit_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(0x7 << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); -} - -static unsigned long ckih_rate; - -static unsigned long clk_ckih_get_rate(struct clk *clk) -{ - return ckih_rate; -} - -static struct clk ckih_clk = { - .get_rate = clk_ckih_get_rate, -}; - -static unsigned long clk_ckih_x2_get_rate(struct clk *clk) -{ - return 2 * clk_get_rate(clk->parent); -} - -static struct clk ckih_x2_clk = { - .parent = &ckih_clk, - .get_rate = clk_ckih_x2_get_rate, -}; - -static unsigned long clk_ckil_get_rate(struct clk *clk) -{ - return CKIL_CLK_FREQ; -} - -static struct clk ckil_clk = { - .get_rate = clk_ckil_get_rate, -}; - -/* plls stuff */ -static struct clk mcu_pll_clk; -static struct clk dsp_pll_clk; -static struct clk usb_pll_clk; - -static struct clk *pll_clk(u8 sel) -{ - switch (sel) { - case 0: - return &mcu_pll_clk; - case 1: - return &dsp_pll_clk; - case 2: - return &usb_pll_clk; - } - BUG(); -} - -static void __iomem *pll_base(struct clk *clk) -{ - if (clk == &mcu_pll_clk) - return MXC_PLL0_BASE; - else if (clk == &dsp_pll_clk) - return MXC_PLL1_BASE; - else if (clk == &usb_pll_clk) - return MXC_PLL2_BASE; - BUG(); -} - -static unsigned long clk_pll_get_rate(struct clk *clk) -{ - const void __iomem *pllbase; - unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi; - long mfn, mfn_abs, mfd, pdf; - s64 temp; - pllbase = pll_base(clk); - - pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM; - if (pll_hfsm == 0) { - dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); - } else { - dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); - } - - pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; - mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; - mfn = dp_mfn & MXC_PLL_DP_MFN_MASK; - mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000); - - if (mfn < 0) - mfn_abs = -mfn; - else - mfn_abs = mfn; - -/* XXX: actually this asumes that ckih is fed to pll, but spec says - * that ckih_x2 is also possible. need to check this out. - */ - ref_clk = clk_get_rate(&ckih_clk); - - ref_clk *= 2; - ref_clk /= pdf + 1; - - temp = (u64) ref_clk * mfn_abs; - do_div(temp, mfd); - if (mfn < 0) - temp = -temp; - temp += ref_clk * mfi; - - return temp; -} - -static int clk_pll_enable(struct clk *clk) -{ - void __iomem *ctl; - u32 reg; - - ctl = pll_base(clk); - reg = __raw_readl(ctl); - reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN); - __raw_writel(reg, ctl); - do { - reg = __raw_readl(ctl); - } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF); - return 0; -} - -static void clk_pll_disable(struct clk *clk) -{ - void __iomem *ctl; - u32 reg; - - ctl = pll_base(clk); - reg = __raw_readl(ctl); - reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN); - __raw_writel(reg, ctl); -} - -static struct clk mcu_pll_clk = { - .parent = &ckih_clk, - .get_rate = clk_pll_get_rate, - .enable = clk_pll_enable, - .disable = clk_pll_disable, -}; - -static struct clk dsp_pll_clk = { - .parent = &ckih_clk, - .get_rate = clk_pll_get_rate, - .enable = clk_pll_enable, - .disable = clk_pll_disable, -}; - -static struct clk usb_pll_clk = { - .parent = &ckih_clk, - .get_rate = clk_pll_get_rate, - .enable = clk_pll_enable, - .disable = clk_pll_disable, -}; -/* plls stuff end */ - -/* ap_ref_clk stuff */ -static struct clk ap_ref_clk; - -static unsigned long clk_ap_ref_get_rate(struct clk *clk) -{ - u32 ascsr, acsr; - u8 ap_pat_ref_div_2, ap_isel, acs, ads; - - ascsr = __raw_readl(MXC_CRMAP_ASCSR); - acsr = __raw_readl(MXC_CRMAP_ACSR); - - /* 0 for ckih, 1 for ckih*2 */ - ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL; - /* reg divider */ - ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1; - /* undocumented, 1 for disabling divider */ - ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1; - /* 0 for pat_ref, 1 for divider out */ - acs = acsr & MXC_CRMAP_ACSR_ACS; - - if (acs & !ads) - /* use divided clock */ - return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1); - - return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1); -} - -static struct clk ap_ref_clk = { - .parent = &ckih_clk, - .get_rate = clk_ap_ref_get_rate, -}; -/* ap_ref_clk stuff end */ - -/* ap_pre_dfs_clk stuff */ -static struct clk ap_pre_dfs_clk; - -static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk) -{ - u32 acsr, ascsr; - - acsr = __raw_readl(MXC_CRMAP_ACSR); - ascsr = __raw_readl(MXC_CRMAP_ASCSR); - - if (acsr & MXC_CRMAP_ACSR_ACS) { - u8 sel; - sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >> - MXC_CRMAP_ASCSR_APSEL_OFFSET; - return clk_get_rate(pll_clk(sel)) / - CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV); - } - return clk_get_rate(&ap_ref_clk); -} - -static struct clk ap_pre_dfs_clk = { - .get_rate = clk_ap_pre_dfs_get_rate, -}; -/* ap_pre_dfs_clk stuff end */ - -/* usb_clk stuff */ -static struct clk usb_clk; - -static struct clk *clk_usb_parent(struct clk *clk) -{ - u32 acsr, ascsr; - - acsr = __raw_readl(MXC_CRMAP_ACSR); - ascsr = __raw_readl(MXC_CRMAP_ASCSR); - - if (acsr & MXC_CRMAP_ACSR_ACS) { - u8 sel; - sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >> - MXC_CRMAP_ASCSR_USBSEL_OFFSET; - return pll_clk(sel); - } - return &ap_ref_clk; -} - -static unsigned long clk_usb_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / - CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV); -} - -static struct clk usb_clk = { - .enable_reg = MXC_CRMAP_ACDER2, - .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET, - .get_rate = clk_usb_get_rate, - .enable = _clk_1bit_enable, - .disable = _clk_1bit_disable, -}; -/* usb_clk stuff end */ - -static unsigned long clk_ipg_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV); -} - -static unsigned long clk_ahb_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / - CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV); -} - -static struct clk ipg_clk = { - .parent = &ap_pre_dfs_clk, - .get_rate = clk_ipg_get_rate, -}; - -static struct clk ahb_clk = { - .parent = &ap_pre_dfs_clk, - .get_rate = clk_ahb_get_rate, -}; - -/* perclk_clk stuff */ -static struct clk perclk_clk; - -static unsigned long clk_perclk_get_rate(struct clk *clk) -{ - u32 acder2; - - acder2 = __raw_readl(MXC_CRMAP_ACDER2); - if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK) - return 2 * clk_get_rate(clk->parent); - - return clk_get_rate(clk->parent); -} - -static struct clk perclk_clk = { - .parent = &ckih_clk, - .get_rate = clk_perclk_get_rate, -}; -/* perclk_clk stuff end */ - -/* uart_clk stuff */ -static struct clk uart_clk[]; - -static unsigned long clk_uart_get_rate(struct clk *clk) -{ - u32 div; - - switch (clk->id) { - case 0: - case 1: - div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV); - break; - case 2: - div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV); - break; - default: - BUG(); - } - return clk_get_rate(clk->parent) / div; -} - -static struct clk uart_clk[] = { - { - .id = 0, - .parent = &perclk_clk, - .enable_reg = MXC_CRMAP_APRA, - .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET, - .get_rate = clk_uart_get_rate, - .enable = _clk_1bit_enable, - .disable = _clk_1bit_disable, - }, { - .id = 1, - .parent = &perclk_clk, - .enable_reg = MXC_CRMAP_APRA, - .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET, - .get_rate = clk_uart_get_rate, - .enable = _clk_1bit_enable, - .disable = _clk_1bit_disable, - }, { - .id = 2, - .parent = &perclk_clk, - .enable_reg = MXC_CRMAP_APRA, - .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET, - .get_rate = clk_uart_get_rate, - .enable = _clk_1bit_enable, - .disable = _clk_1bit_disable, - }, -}; -/* uart_clk stuff end */ - -/* sdhc_clk stuff */ -static struct clk nfc_clk; - -static unsigned long clk_nfc_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / - CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV); -} - -static struct clk nfc_clk = { - .parent = &ahb_clk, - .enable_reg = MXC_CRMAP_ACDER2, - .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET, - .get_rate = clk_nfc_get_rate, - .enable = _clk_1bit_enable, - .disable = _clk_1bit_disable, -}; -/* sdhc_clk stuff end */ - -/* sdhc_clk stuff */ -static struct clk sdhc_clk[]; - -static struct clk *clk_sdhc_parent(struct clk *clk) -{ - u32 aprb; - u8 sel; - u32 mask; - int offset; - - aprb = __raw_readl(MXC_CRMAP_APRB); - - switch (clk->id) { - case 0: - mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK; - offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET; - break; - case 1: - mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK; - offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET; - break; - default: - BUG(); - } - sel = (aprb & mask) >> offset; - - switch (sel) { - case 0: - return &ckih_clk; - case 1: - return &ckih_x2_clk; - } - return &usb_clk; -} - -static unsigned long clk_sdhc_get_rate(struct clk *clk) -{ - u32 div; - - switch (clk->id) { - case 0: - div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV); - break; - case 1: - div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV); - break; - default: - BUG(); - } - - return clk_get_rate(clk->parent) / div; -} - -static int clk_sdhc_enable(struct clk *clk) -{ - u32 amlpmre1, aprb; - - amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1); - aprb = __raw_readl(MXC_CRMAP_APRB); - switch (clk->id) { - case 0: - amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET); - aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET); - break; - case 1: - amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET); - aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET); - break; - } - __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1); - __raw_writel(aprb, MXC_CRMAP_APRB); - return 0; -} - -static void clk_sdhc_disable(struct clk *clk) -{ - u32 amlpmre1, aprb; - - amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1); - aprb = __raw_readl(MXC_CRMAP_APRB); - switch (clk->id) { - case 0: - amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET); - aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET); - break; - case 1: - amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET); - aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET); - break; - } - __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1); - __raw_writel(aprb, MXC_CRMAP_APRB); -} - -static struct clk sdhc_clk[] = { - { - .id = 0, - .get_rate = clk_sdhc_get_rate, - .enable = clk_sdhc_enable, - .disable = clk_sdhc_disable, - }, { - .id = 1, - .get_rate = clk_sdhc_get_rate, - .enable = clk_sdhc_enable, - .disable = clk_sdhc_disable, - }, -}; -/* sdhc_clk stuff end */ - -/* wdog_clk stuff */ -static struct clk wdog_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable_reg = MXC_CRMAP_AMLPMRD, - .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET, - .enable = _clk_3bit_enable, - .disable = _clk_3bit_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable_reg = MXC_CRMAP_AMLPMRD, - .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET, - .enable = _clk_3bit_enable, - .disable = _clk_3bit_disable, - }, -}; -/* wdog_clk stuff end */ - -/* gpt_clk stuff */ -static struct clk gpt_clk = { - .parent = &ipg_clk, - .enable_reg = MXC_CRMAP_AMLPMRC, - .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET, - .enable = _clk_3bit_enable, - .disable = _clk_3bit_disable, -}; -/* gpt_clk stuff end */ - -/* cspi_clk stuff */ -static struct clk cspi_clk[] = { - { - .id = 0, - .parent = &ipg_clk, - .enable_reg = MXC_CRMAP_AMLPMRE2, - .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET, - .enable = _clk_3bit_enable, - .disable = _clk_3bit_disable, - }, { - .id = 1, - .parent = &ipg_clk, - .enable_reg = MXC_CRMAP_AMLPMRE1, - .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET, - .enable = _clk_3bit_enable, - .disable = _clk_3bit_disable, - }, -}; -/* cspi_clk stuff end */ - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]) - _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1]) - _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2]) - _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0]) - _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1]) - _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0]) - _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0]) - _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1]) -}; - -int __init mxc91231_clocks_init(unsigned long fref) -{ - void __iomem *gpt_base; - - ckih_rate = fref; - - usb_clk.parent = clk_usb_parent(&usb_clk); - sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]); - sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR); - mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT); - - return 0; -} diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h deleted file mode 100644 index b989baccd67..00000000000 --- a/arch/arm/mach-mxc91231/crm_regs.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor, Inc. - * Copyright 2006-2007 Motorola, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ -#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ - -#define CKIL_CLK_FREQ 32768 - -#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR) -#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR) -#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR) -#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR) -#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR) -#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR) -#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR) - -/* PLL Register Offsets */ -#define MXC_PLL_DP_CTL 0x00 -#define MXC_PLL_DP_CONFIG 0x04 -#define MXC_PLL_DP_OP 0x08 -#define MXC_PLL_DP_MFD 0x0C -#define MXC_PLL_DP_MFN 0x10 -#define MXC_PLL_DP_HFS_OP 0x1C -#define MXC_PLL_DP_HFS_MFD 0x20 -#define MXC_PLL_DP_HFS_MFN 0x24 - -/* PLL Register Bit definitions */ -#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 -#define MXC_PLL_DP_CTL_ADE 0x800 -#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 -#define MXC_PLL_DP_CTL_HFSM 0x80 -#define MXC_PLL_DP_CTL_PRE 0x40 -#define MXC_PLL_DP_CTL_UPEN 0x20 -#define MXC_PLL_DP_CTL_RST 0x10 -#define MXC_PLL_DP_CTL_RCP 0x8 -#define MXC_PLL_DP_CTL_PLM 0x4 -#define MXC_PLL_DP_CTL_BRM0 0x2 -#define MXC_PLL_DP_CTL_LRF 0x1 - -#define MXC_PLL_DP_OP_MFI_OFFSET 4 -#define MXC_PLL_DP_OP_MFI_MASK 0xF -#define MXC_PLL_DP_OP_PDF_OFFSET 0 -#define MXC_PLL_DP_OP_PDF_MASK 0xF - -#define MXC_PLL_DP_MFD_OFFSET 0 -#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF - -#define MXC_PLL_DP_MFN_OFFSET 0 -#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF - -/* CRM AP Register Offsets */ -#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00) -#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04) -#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08) -#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C) -#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10) -#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14) -#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18) -#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C) -#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20) -#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24) -#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28) -#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C) -#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30) -#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34) -#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38) -#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C) -#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40) -#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44) -#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48) -#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C) -#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50) -#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54) -#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58) -#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C) -#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60) -#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64) -#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68) - -/* CRM AP Register Bit definitions */ -#define MXC_CRMAP_ASCSR_CRS 0x10000 -#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15 -#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000 -#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13 -#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13) -#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11 -#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11) -#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7 -#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7) -#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5 -#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5) -#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3 -#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3) -#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2 -#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4 -#define MXC_CRMAP_ASCSR_APISEL 0x1 - -#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8 -#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8) -#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4 -#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4) -#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0 -#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF - -#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30 -#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24 -#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24) -#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14 -#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8 -#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8) -#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6 -#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0 -#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F - -#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24 -#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24) -#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20 -#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16 -#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16) -#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12 -#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8 -#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8) -#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5 -#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5) -#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0 -#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF - -#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22 -#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22) -#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19 -#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19) -#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12 -#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12) -#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9 -#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9) -#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6 -#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6) -#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3 -#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3) - -#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0 -#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7 - -#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28 -#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28) -#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22 -#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22) -#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16 -#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16) -#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12 -#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12) -#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9 -#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9) -#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6 -#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6) -#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3 -#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3) -#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0 -#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7 - -#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22 -#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22) -#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12 -#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12) -#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9 -#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9) -#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6 -#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6) -#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0 -#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7 - -#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28 -#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28) -#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25 -#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25) -#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22 -#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22) -#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19 -#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19) -#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16 -#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16) -#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12 -#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12) -#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9 -#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9) -#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6 -#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6) -#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3 -#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3) -#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0 -#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7 - -#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0 -#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7 - -#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19 -#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19) -#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16 -#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16) -#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9 -#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9) -#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6 -#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6) -#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3 -#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3) -#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0 -#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0) - -#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28 -#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28) -#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22 -#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22) -#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19 -#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19) -#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16 -#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16) -#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12 -#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12) -#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9 -#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9) -#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6 -#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6) -#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3 -#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3) -#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0 -#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7 - -#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20 -#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20) - -#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29 -#define MXC_CRMAP_APRA_SIMEN_OFFSET 24 -#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17 -#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17) -#define MXC_CRMAP_APRA_UART3EN_OFFSET 16 -#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14 -#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13 -#define MXC_CRMAP_APRA_UART2EN_OFFSET 8 -#define MXC_CRMAP_APRA_UART1EN_OFFSET 0 - -#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13 -#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13) -#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9 -#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9) -#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8 -#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5 -#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5) -#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1 -#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1) -#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0 - -#define MXC_CRMAP_ACSR_ADS_OFFSET 8 -#define MXC_CRMAP_ACSR_ADS (0x1 << 8) -#define MXC_CRMAP_ACSR_ACS 0x1 - -#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8) -#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8) -#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8) -#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8) -#define MXC_CRMAP_ADCR_LFDF_OFFSET 8 -#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8) -#define MXC_CRMAP_ADCR_ALT_PLL 0x80 -#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20 -#define MXC_CRMAP_ADCR_DIV_BYP 0x2 -#define MXC_CRMAP_ADCR_VSTAT 0x8 -#define MXC_CRMAP_ADCR_TSTAT 0x10 -#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10 -#define MXC_CRMAP_ADCR_CLK_ON 0x40 - -#define MXC_CRMAP_ADFMR_FC_OFFSET 16 -#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16) -#define MXC_CRMAP_ADFMR_MF_OFFSET 1 -#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1) -#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1 -#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000 - -#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18) -#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16) -#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12) -#define MXC_CRMAP_ACR_CKOHD (1 << 11) -#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8) -#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8 -#define MXC_CRMAP_ACR_CKOD (1 << 7) -#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4) - -/* AP Warm reset */ -#define MXC_CRMAP_AMCR_SW_AP (1 << 14) - -/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */ -#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001 -#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003 -#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007 -#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000 - -#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008 -#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018 -#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038 -#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000 - -#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040 -#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0 -#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0 -#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000 - -#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200 -#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600 -#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00 -#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000 - -#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000 -#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000 -#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000 -#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000 - -#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000 -#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000 -#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000 -#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000 - -#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000 -#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000 -#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000 -#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000 - -#define NUM_GATE_CTRL 6 - -/* CRM COM Register Offsets */ -#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C) -#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10) - -/* CRM COM Bit Definitions */ -#define MXC_CRMCOM_CSCR_PPD1 0x08000000 -#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18) -#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17) -#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8 -#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8) -#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0 -#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3 - -/* DSM Register Offsets */ -#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c) -#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20) -#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24) -#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28) -#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40) -#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44) -#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c) -#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50) - -/* Bit definitions of various registers in DSM */ -#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008 -#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004 -#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002 -#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001 -#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000 -#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001 -#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003 -#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200 -#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001 -#define MXC_DSM_CONTROL0_RESTART 0x00000010 -/* Counter Block reset */ -#define MXC_DSM_CONTROL1_CB_RST 0x00000002 -/* State Machine reset */ -#define MXC_DSM_CONTROL1_SM_RST 0x00000004 -/* Bit needed to reset counter block */ -#define MXC_CONTROL1_RST_CNT32 0x00000008 -#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800 -#define MXC_DSM_CONTROL1_SLEEP 0x00000100 -#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000 -#define MXC_DSM_CTREN_CNT32 0x00000001 - -/* Magic Fix enable bit */ -#define MXC_DSM_MGPER_EN_MGFX 0x80000000 -#define MXC_DSM_MGPER_PER_MASK 0x000003FF -#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n) - -/* Address offsets of the CLKCTL registers */ -#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00) -#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04) -#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08) - -#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */ diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c deleted file mode 100644 index 027af4f0d18..00000000000 --- a/arch/arm/mach-mxc91231/devices.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/serial.h> -#include <linux/gpio.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/imx-uart.h> - -static struct resource uart0[] = { - { - .start = MXC91231_UART1_BASE_ADDR, - .end = MXC91231_UART1_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_UART1_RX, - .end = MXC91231_INT_UART1_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = MXC91231_INT_UART1_TX, - .end = MXC91231_INT_UART1_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = MXC91231_INT_UART1_MINT, - .end = MXC91231_INT_UART1_MINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = MXC91231_UART2_BASE_ADDR, - .end = MXC91231_UART2_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_UART2_RX, - .end = MXC91231_INT_UART2_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = MXC91231_INT_UART2_TX, - .end = MXC91231_INT_UART2_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = MXC91231_INT_UART2_MINT, - .end = MXC91231_INT_UART2_MINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = MXC91231_UART3_BASE_ADDR, - .end = MXC91231_UART3_BASE_ADDR + 0x0B5, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_UART3_RX, - .end = MXC91231_INT_UART3_RX, - .flags = IORESOURCE_IRQ, - }, { - .start = MXC91231_INT_UART3_TX, - .end = MXC91231_INT_UART3_TX, - .flags = IORESOURCE_IRQ, - }, { - .start = MXC91231_INT_UART3_MINT, - .end = MXC91231_INT_UART3_MINT, - .flags = IORESOURCE_IRQ, - - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - -/* GPIO port description */ -static struct mxc_gpio_port mxc_gpio_ports[] = { - [0] = { - .chip.label = "gpio-0", - .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR), - .irq = MXC91231_INT_GPIO1, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, - [1] = { - .chip.label = "gpio-1", - .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR), - .irq = MXC91231_INT_GPIO2, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, - [2] = { - .chip.label = "gpio-2", - .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR), - .irq = MXC91231_INT_GPIO3, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, - [3] = { - .chip.label = "gpio-3", - .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR), - .irq = MXC91231_INT_GPIO4, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - }, -}; - -int __init mxc91231_register_gpios(void) -{ - return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); -} - -static struct resource mxc_nand_resources[] = { - { - .start = MXC91231_NFC_BASE_ADDR, - .end = MXC91231_NFC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM - }, { - .start = MXC91231_INT_NANDFC, - .end = MXC91231_INT_NANDFC, - .flags = IORESOURCE_IRQ - }, -}; - -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; - -static struct resource mxc_sdhc0_resources[] = { - { - .start = MXC91231_MMC_SDHC1_BASE_ADDR, - .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_MMC_SDHC1, - .end = MXC91231_INT_MMC_SDHC1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_sdhc1_resources[] = { - { - .start = MXC91231_MMC_SDHC2_BASE_ADDR, - .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_MMC_SDHC2, - .end = MXC91231_INT_MMC_SDHC2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_sdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_sdhc0_resources), - .resource = mxc_sdhc0_resources, -}; - -struct platform_device mxc_sdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), - .resource = mxc_sdhc1_resources, -}; - -static struct resource mxc_cspi0_resources[] = { - { - .start = MXC91231_CSPI1_BASE_ADDR, - .end = MXC91231_CSPI1_BASE_ADDR + 0x20, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_CSPI1, - .end = MXC91231_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_cspi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_cspi0_resources), - .resource = mxc_cspi0_resources, -}; - -static struct resource mxc_cspi1_resources[] = { - { - .start = MXC91231_CSPI2_BASE_ADDR, - .end = MXC91231_CSPI2_BASE_ADDR + 0x20, - .flags = IORESOURCE_MEM, - }, { - .start = MXC91231_INT_CSPI2, - .end = MXC91231_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_cspi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_cspi1_resources), - .resource = mxc_cspi1_resources, -}; - -static struct resource mxc_wdog0_resources[] = { - { - .start = MXC91231_WDOG1_BASE_ADDR, - .end = MXC91231_WDOG1_BASE_ADDR + 0x10, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_wdog_device0 = { - .name = "mxc-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdog0_resources), - .resource = mxc_wdog0_resources, -}; diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h deleted file mode 100644 index 72a2136ce27..00000000000 --- a/arch/arm/mach-mxc91231/devices.h +++ /dev/null @@ -1,13 +0,0 @@ -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; - -extern struct platform_device mxc_nand_device; - -extern struct platform_device mxc_sdhc_device0; -extern struct platform_device mxc_sdhc_device1; - -extern struct platform_device mxc_cspi_device0; -extern struct platform_device mxc_cspi_device1; - -extern struct platform_device mxc_wdog_device0; diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c deleted file mode 100644 index 66fc41cbf2c..00000000000 --- a/arch/arm/mach-mxc91231/iomux.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <mach/hardware.h> -#include <mach/gpio.h> -#include <mach/iomux-mxc91231.h> - -/* - * IOMUX register (base) addresses - */ -#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR) -#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR) -#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000) -#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000) -#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200) - -#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600) -#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004) - -static DEFINE_SPINLOCK(gpio_mux_lock); - -#define NB_PORTS ((PIN_MAX + 32) / 32) -#define PIN_GLOBAL_NUM(pin) \ - (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \ - ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \ - ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT)) - -unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; -/* - * set the mode for a IOMUX pin. - */ -int mxc_iomux_mode(unsigned int pin_mode) -{ - u32 side, field, l, mode, ret = 0; - void __iomem *reg; - - side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT; - switch (side) { - case MUX_SIDE_AP: - reg = IOMUXSW_AP_MUX_CTL; - break; - case MUX_SIDE_SP: - reg = IOMUXSW_SP_MUX_CTL; - break; - default: - return -EINVAL; - } - reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4; - field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT; - mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT; - - spin_lock(&gpio_mux_lock); - - l = __raw_readl(reg); - l &= ~(0xff << (field * 8)); - l |= mode << (field * 8); - __raw_writel(l, reg); - - spin_unlock(&gpio_mux_lock); - - return ret; -} -EXPORT_SYMBOL(mxc_iomux_mode); - -/* - * This function configures the pad value for a IOMUX pin. - */ -void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) -{ - u32 padgrp, field, l; - void __iomem *reg; - - padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT; - reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; - field = (pin + 2) % 3; - - pr_debug("%s: reg offset = 0x%x, field = %d\n", - __func__, (pin + 2) / 3, field); - - spin_lock(&gpio_mux_lock); - - l = __raw_readl(reg); - l &= ~(0x1ff << (field * 10)); - l |= config << (field * 10); - __raw_writel(l, reg); - - spin_unlock(&gpio_mux_lock); -} -EXPORT_SYMBOL(mxc_iomux_set_pad); - -/* - * allocs a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - */ -int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label) -{ - unsigned pad = PIN_GLOBAL_NUM(pin_mode); - if (pad >= (PIN_MAX + 1)) { - printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", - pad, label ? label : "?"); - return -EINVAL; - } - - if (test_and_set_bit(pad, mxc_pin_alloc_map)) { - printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", - pad, label ? label : "?"); - return -EBUSY; - } - mxc_iomux_mode(pin_mode); - - return 0; -} -EXPORT_SYMBOL(mxc_iomux_alloc_pin); - -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label) -{ - const unsigned int *p = pin_list; - int i; - int ret = -EINVAL; - - for (i = 0; i < count; i++) { - ret = mxc_iomux_alloc_pin(*p, label); - if (ret) - goto setup_error; - p++; - } - return 0; - -setup_error: - mxc_iomux_release_multiple_pins(pin_list, i); - return ret; -} -EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); - -void mxc_iomux_release_pin(unsigned int pin_mode) -{ - unsigned pad = PIN_GLOBAL_NUM(pin_mode); - - if (pad < (PIN_MAX + 1)) - clear_bit(pad, mxc_pin_alloc_map); -} -EXPORT_SYMBOL(mxc_iomux_release_pin); - -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) -{ - const unsigned int *p = pin_list; - int i; - - for (i = 0; i < count; i++) { - mxc_iomux_release_pin(*p); - p++; - } -} -EXPORT_SYMBOL(mxc_iomux_release_multiple_pins); diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c deleted file mode 100644 index f31a45e5a0b..00000000000 --- a/arch/arm/mach-mxc91231/magx-zn5.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com> - * - * This file is released under the GPLv2 or later. - */ - -#include <linux/irq.h> -#include <linux/init.h> -#include <linux/device.h> - -#include <asm/mach-types.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> - -#include <mach/common.h> -#include <mach/hardware.h> -#include <mach/iomux-mxc91231.h> -#include <mach/mmc.h> -#include <mach/imx-uart.h> - -#include "devices.h" - -static struct imxuart_platform_data uart_pdata = { -}; - -static struct imxmmc_platform_data sdhc_pdata = { -}; - -static void __init zn5_init(void) -{ - pm_power_off = mxc91231_power_off; - - mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx"); - mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx"); - - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); - - mxc_register_device(&mxc_wdog_device0, NULL); - - return; -} - -static void __init zn5_timer_init(void) -{ - mxc91231_clocks_init(26000000); /* 26mhz ckih */ -} - -struct sys_timer zn5_timer = { - .init = zn5_timer_init, -}; - -MACHINE_START(MAGX_ZN5, "Motorola Zn5") - .boot_params = MXC91231_PHYS_OFFSET + 0x100, - .map_io = mxc91231_map_io, - .init_early = mxc91231_init_early, - .init_irq = mxc91231_init_irq, - .timer = &zn5_timer, - .init_machine = zn5_init, -MACHINE_END diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c deleted file mode 100644 index a77f6daf6a2..00000000000 --- a/arch/arm/mach-mxc91231/mm.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MXC specific definitions - * Copyright 2006 Motorola, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <asm/pgtable.h> -#include <asm/mach/map.h> - -/* - * This structure defines the MXC memory map. - */ -static struct map_desc mxc91231_io_desc[] __initdata = { - imx_map_entry(MXC91231, L2CC, MT_DEVICE), - imx_map_entry(MXC91231, X_MEMC, MT_DEVICE), - imx_map_entry(MXC91231, ROMP, MT_DEVICE), - imx_map_entry(MXC91231, AVIC, MT_DEVICE), - imx_map_entry(MXC91231, AIPS1, MT_DEVICE), - imx_map_entry(MXC91231, SPBA0, MT_DEVICE), - imx_map_entry(MXC91231, SPBA1, MT_DEVICE), - imx_map_entry(MXC91231, AIPS2, MT_DEVICE), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory map for - * the IO modules. - */ -void __init mxc91231_map_io(void) -{ - iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); -} - -void __init mxc91231_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MXC91231); -} - -int mxc91231_register_gpios(void); - -void __init mxc91231_init_irq(void) -{ - mxc91231_register_gpios(); - mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR)); -} diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c deleted file mode 100644 index 736f7efd874..00000000000 --- a/arch/arm/mach-mxc91231/system.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com> - * - * This file is released under the GPLv2 or later. - */ - -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/proc-fns.h> -#include <mach/hardware.h> - -#include "crm_regs.h" - -#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR) -#define WDOG_WCR_OUT_ENABLE (1 << 6) -#define WDOG_WCR_ASSERT (1 << 5) - -void mxc91231_power_off(void) -{ - u16 wcr; - - wcr = __raw_readw(WDOG_WCR); - wcr |= WDOG_WCR_OUT_ENABLE; - wcr &= ~WDOG_WCR_ASSERT; - __raw_writew(wcr, WDOG_WCR); -} - -void mxc91231_arch_reset(char mode, const char *cmd) -{ - u32 amcr; - - /* Reset the AP using CRM */ - amcr = __raw_readl(MXC_CRMAP_AMCR); - amcr &= ~MXC_CRMAP_AMCR_SW_AP; - __raw_writel(amcr, MXC_CRMAP_AMCR); - - mdelay(10); - cpu_reset(0); -} - -void mxc91231_prepare_idle(void) -{ - u32 crm_ctl; - - /* Go to WAIT mode after WFI */ - crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL); - crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1); - crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE; - __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL); -} diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4f6f174af6c..f114960622e 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -17,13 +17,23 @@ config SOC_IMX28 comment "MXS platforms:" +config MACH_STMP378X_DEVB + bool "Support STMP378x_devb Platform" + select SOC_IMX23 + select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_MXS_MMC + help + Include support for STMP378x-devb platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX23EVK bool "Support MX23EVK Platform" select SOC_IMX23 select MXS_HAVE_AMBA_DUART select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXSFB - default y help Include support for MX23EVK platform. This includes specific configurations for the board and its peripherals. @@ -35,9 +45,9 @@ config MACH_MX28EVK select MXS_HAVE_PLATFORM_AUART select MXS_HAVE_PLATFORM_FEC select MXS_HAVE_PLATFORM_FLEXCAN + select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXSFB select MXS_OCOTP - default y help Include support for MX28EVK platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 2f1f6141ca7..58e892376bf 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o +obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o obj-$(CONFIG_MODULE_TX28) += module-tx28.o diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index d133c7f3094..0163b6d8377 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -446,6 +446,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("rtc", NULL, rtc_clk) _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) + _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk) + _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk) _REGISTER_CLOCK(NULL, "usb", usb_clk) _REGISTER_CLOCK(NULL, "audio", audio_clk) _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk) @@ -521,6 +523,15 @@ static int clk_misc_init(void) __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); + /* + * 480 MHz seems too high to be ssp clock source directly, + * so set frac to get a 288 MHz ref_io. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + reg &= ~BM_CLKCTRL_FRAC_IOFRAC; + reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + return 0; } @@ -528,6 +539,12 @@ int __init mx23_clocks_init(void) { clk_misc_init(); + /* + * source ssp clock from ref_io than ref_xtal, + * as ref_xtal only provides 24 MHz as maximum. + */ + clk_set_parent(&ssp_clk, &ref_io_clk); + clk_enable(&cpu_clk); clk_enable(&hbus_clk); clk_enable(&xbus_clk); diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5e489a2b202..5dcc59d5b9e 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -295,11 +295,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ unsigned long diff, parent_rate, calc_rate; \ int i; \ \ - parent_rate = clk_get_rate(clk->parent); \ div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ bm_busy = BM_CLKCTRL_##dr##_BUSY; \ \ if (clk->parent == &ref_xtal_clk) { \ + parent_rate = clk_get_rate(clk->parent); \ div = DIV_ROUND_UP(parent_rate, rate); \ if (clk == &cpu_clk) { \ div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \ @@ -309,6 +309,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ if (div == 0 || div > div_max) \ return -EINVAL; \ } else { \ + /* \ + * hack alert: this block modifies clk->parent, too, \ + * so the base to use it the grand parent. \ + */ \ + parent_rate = clk_get_rate(clk->parent->parent); \ rate >>= PARENT_RATE_SHIFT; \ parent_rate >>= PARENT_RATE_SHIFT; \ diff = parent_rate; \ @@ -618,6 +623,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("pll2", NULL, pll2_clk) _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) + _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk) + _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk) _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) _REGISTER_CLOCK(NULL, "usb0", usb0_clk) @@ -737,6 +744,15 @@ static int clk_misc_init(void) reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + /* + * 480 MHz seems too high to be ssp clock source directly, + * so set frac0 to get a 288 MHz ref_io0. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC; + reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + return 0; } @@ -744,6 +760,13 @@ int __init mx28_clocks_init(void) { clk_misc_init(); + /* + * source ssp clock from ref_io0 than ref_xtal, + * as ref_xtal only provides 24 MHz as maximum. + */ + clk_set_parent(&ssp0_clk, &ref_io0_clk); + clk_set_parent(&ssp1_clk, &ref_io0_clk); + clk_enable(&cpu_clk); clk_enable(&hbus_clk); clk_enable(&xbus_clk); diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index c7e14f4e366..c6f345febd3 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -21,6 +21,10 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst; #define mx23_add_auart0() mx23_add_auart(0) #define mx23_add_auart1() mx23_add_auart(1) +extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; +#define mx23_add_mxs_mmc(id, pdata) \ + mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) + #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) struct platform_device *__init mx23_add_mxsfb( diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 9d08555c4cf..79b94523954 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -34,9 +34,13 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; #define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata) #define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata) -extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; +extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst; #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) +extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; +#define mx28_add_mxs_mmc(id, pdata) \ + mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) + #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) struct platform_device *__init mx28_add_mxsfb( diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index 1451ad060d8..acf9eea124c 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -15,6 +15,9 @@ config MXS_HAVE_PLATFORM_FLEXCAN config MXS_HAVE_PLATFORM_MXS_I2C bool +config MXS_HAVE_PLATFORM_MXS_MMC + bool + config MXS_HAVE_PLATFORM_MXS_PWM bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 0d9bea30b0a..324f2824d38 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile @@ -4,5 +4,6 @@ obj-y += platform-dma.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c index eab3a06836d..79222ec8ede 100644 --- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c +++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c @@ -22,13 +22,14 @@ [_id] = mxs_i2c_data_entry_single(soc, _id) #ifdef CONFIG_SOC_IMX28 -const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { +const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = { mxs_i2c_data_entry(MX28, 0), mxs_i2c_data_entry(MX28, 1), }; #endif -struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data) +struct platform_device *__init mxs_add_mxs_i2c( + const struct mxs_mxs_i2c_data *data) { struct resource res[] = { { diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c new file mode 100644 index 00000000000..382dacbeca2 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <linux/compiler.h> +#include <linux/err.h> +#include <linux/init.h> + +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> + +#define mxs_mxs_mmc_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ + .dma = soc ## _DMA_SSP ## hwid, \ + .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ + .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ + } + +#define mxs_mxs_mmc_data_entry(soc, _id, hwid) \ + [_id] = mxs_mxs_mmc_data_entry_single(soc, _id, hwid) + + +#ifdef CONFIG_SOC_IMX23 +const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { + mxs_mxs_mmc_data_entry(MX23, 0, 1), + mxs_mxs_mmc_data_entry(MX23, 1, 2), +}; +#endif + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { + mxs_mxs_mmc_data_entry(MX28, 0, 0), + mxs_mxs_mmc_data_entry(MX28, 1, 1), +}; +#endif + +struct platform_device *__init mxs_add_mxs_mmc( + const struct mxs_mxs_mmc_data *data, + const struct mxs_mmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->dma, + .end = data->dma, + .flags = IORESOURCE_DMA, + }, { + .start = data->irq_err, + .end = data->irq_err, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq_dma, + .end = data->irq_dma, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device("mxs-mmc", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 56fa2ed1522..2c950fef71a 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c @@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); + struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq); u32 gpio_irq_no_base = port->virtual_irq_start; desc->irq_data.chip->irq_ack(&desc->irq_data); @@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); + irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); /* register gpio chip */ port[i].chip.direction_input = mxs_gpio_direction_input; diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 0f4c120fc16..23ca9d083b2 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c @@ -74,8 +74,7 @@ void __init icoll_init_irq(void) mxs_reset_block(icoll_base + HW_ICOLL_CTRL); for (i = 0; i < MXS_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxs_icoll_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } } diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 71f24484b04..7a37469ed5b 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -65,13 +65,27 @@ struct platform_device *__init mxs_add_flexcan( const struct flexcan_platform_data *pdata); /* i2c */ -struct mxs_i2c_data { +struct mxs_mxs_i2c_data { int id; resource_size_t iobase; resource_size_t errirq; resource_size_t dmairq; }; -struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); +struct platform_device * __init mxs_add_mxs_i2c( + const struct mxs_mxs_i2c_data *data); + +/* mmc */ +#include <mach/mmc.h> +struct mxs_mxs_mmc_data { + int id; + resource_size_t iobase; + resource_size_t dma; + resource_size_t irq_err; + resource_size_t irq_dma; +}; +struct platform_device *__init mxs_add_mxs_mmc( + const struct mxs_mxs_mmc_data *data, + const struct mxs_mmc_platform_data *pdata); /* pwm */ struct platform_device *__init mxs_add_mxs_pwm( diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h index c0a18c23084..599094bc99d 100644 --- a/arch/arm/mach-mxs/include/mach/mx23.h +++ b/arch/arm/mach-mxs/include/mach/mx23.h @@ -57,7 +57,7 @@ #define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) #define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) #define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) -#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) +#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) #define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) #define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) #define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h index f12a1732d8b..7f8bf653964 100644 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -20,7 +20,7 @@ #include <asm/mach-types.h> -static unsigned long mxs_duart_base; +unsigned long mxs_duart_base; #define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index a66994f0518..3c2de33803a 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -28,6 +28,8 @@ #define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) #define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) +#define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) +#define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) static const iomux_cfg_t mx23evk_pads[] __initconst = { /* duart */ @@ -73,6 +75,36 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = { MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, /* backlight control */ MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, + + /* mmc */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D08__SSP1_DATA4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D09__SSP1_DATA5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D10__SSP1_DATA6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_GPMI_D11__SSP1_DATA7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_CMD__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DETECT__SSP1_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_SSP1_SCK__SSP1_SCK | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX23_PAD_PWM4__GPIO_1_30 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX23_PAD_PWM3__GPIO_1_29 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; /* mxsfb (lcdif) */ @@ -101,6 +133,11 @@ static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { .ld_intf_width = STMLCDIF_24BIT, }; +static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { + .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, +}; + static void __init mx23evk_init(void) { int ret; @@ -110,6 +147,13 @@ static void __init mx23evk_init(void) mx23_add_duart(); mx23_add_auart0(); + /* power on mmc slot by writing 0 to the gpio */ + ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, + "mmc0-slot-power"); + if (ret) + pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); + mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); + ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); if (ret) pr_warn("failed to request gpio lcd-enable: %d\n", ret); diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 08002d02267..eacdc6b0e70 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -34,6 +34,11 @@ #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) +#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) +#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) +#define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) +#define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) + static const iomux_cfg_t mx28evk_pads[] __initconst = { /* duart */ MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, @@ -115,6 +120,65 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, /* backlight control */ MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, + /* mmc0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA1__SSP0_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA2__SSP0_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA3__SSP0_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA4__SSP0_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA5__SSP0_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA6__SSP0_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DATA7__SSP0_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_CMD__SSP0_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_SSP1_SCK__GPIO_2_12 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX28_PAD_PWM3__GPIO_3_28 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* mmc1 */ + MX28_PAD_GPMI_D00__SSP1_D0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D01__SSP1_D1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D02__SSP1_D2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D03__SSP1_D3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D04__SSP1_D4 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D05__SSP1_D5 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D06__SSP1_D6 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_D07__SSP1_D7 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RDY1__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_GPMI_WRN__SSP1_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_GPMI_RESETN__GPIO_0_28 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* slot power enable */ + MX28_PAD_PWM4__GPIO_3_29 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), }; /* fec */ @@ -258,6 +322,18 @@ static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { .ld_intf_width = STMLCDIF_24BIT, }; +static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { + { + /* mmc0 */ + .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, + }, { + /* mmc1 */ + .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, + .flags = SLOTF_8_BIT_CAPABLE, + }, +}; + static void __init mx28evk_init(void) { int ret; @@ -297,6 +373,19 @@ static void __init mx28evk_init(void) gpio_set_value(MX28EVK_BL_ENABLE, 1); mx28_add_mxsfb(&mx28evk_mxsfb_pdata); + + /* power on mmc slot by writing 0 to the gpio */ + ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, + "mmc0-slot-power"); + if (ret) + pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); + mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); + + ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, + "mmc1-slot-power"); + if (ret) + pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); + mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); } static void __init mx28evk_timer_init(void) diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c new file mode 100644 index 00000000000..7f38d82b69a --- /dev/null +++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c @@ -0,0 +1,120 @@ +/* + * board setup for STMP378x-Development-Board + * + * based on mx23evk board setup and information gained form the original + * plat-stmp based board setup, now converted to mach-mxs. + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/spi/spi.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/common.h> +#include <mach/iomux-mx23.h> + +#include "devices-mx23.h" + +#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) +#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) + +#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) + +static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { + /* duart (extended setup missing in old boardcode, too */ + MX23_PAD_PWM0__DUART_RX, + MX23_PAD_PWM1__DUART_TX, + + /* auart */ + MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, + + /* mmc */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_CMD__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DETECT__SSP1_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_SSP1_SCK__SSP1_SCK | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ + MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ +}; + +static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { + .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, +}; + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) + { + .modalias = "enc28j60", + .max_speed_hz = 6 * 1000 * 1000, + .bus_num = 1, + .chip_select = 0, + .platform_data = NULL, + }, +#endif +}; + +static void __init stmp378x_dvb_init(void) +{ + int ret; + + mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, + ARRAY_SIZE(stmp378x_dvb_pads)); + + mx23_add_duart(); + mx23_add_auart0(); + + /* power on mmc slot */ + ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, + GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); + if (ret) + pr_warn("could not power mmc (%d)\n", ret); + + mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); + + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + +static void __init stmp378x_dvb_timer_init(void) +{ + mx23_clocks_init(); +} + +static struct sys_timer stmp378x_dvb_timer = { + .init = stmp378x_dvb_timer_init, +}; + +MACHINE_START(STMP378X, "STMP378X") + .map_io = mx23_map_io, + .init_irq = mx23_init_irq, + .init_machine = stmp378x_dvb_init, + .timer = &stmp378x_dvb_timer, +MACHINE_END diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c index fa0b154da67..0fcff47009c 100644 --- a/arch/arm/mach-mxs/module-tx28.c +++ b/arch/arm/mach-mxs/module-tx28.c @@ -45,7 +45,7 @@ static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { }; #define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) -static const iomux_cfg_t tx28_fec_pads[] __initconst = { +static const iomux_cfg_t tx28_fec0_pads[] __initconst = { MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, @@ -57,7 +57,20 @@ static const iomux_cfg_t tx28_fec_pads[] __initconst = { MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, }; -static const struct fec_platform_data tx28_fec_data __initconst = { +static const iomux_cfg_t tx28_fec1_pads[] __initconst = { + MX28_PAD_ENET0_RXD2__ENET1_RXD0, + MX28_PAD_ENET0_RXD3__ENET1_RXD1, + MX28_PAD_ENET0_TXD2__ENET1_TXD0, + MX28_PAD_ENET0_TXD3__ENET1_TXD1, + MX28_PAD_ENET0_COL__ENET1_TX_EN, + MX28_PAD_ENET0_CRS__ENET1_RX_EN, +}; + +static struct fec_platform_data tx28_fec0_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static struct fec_platform_data tx28_fec1_data = { .phy = PHY_INTERFACE_MODE_RMII, }; @@ -108,15 +121,15 @@ int __init tx28_add_fec0(void) pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); gpio_set_value(TX28_FEC_PHY_RESET, 1); - ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads, - ARRAY_SIZE(tx28_fec_pads)); + ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, + ARRAY_SIZE(tx28_fec0_pads)); if (ret) { pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", __func__, ret); goto free_gpios; } - pr_debug("%s: Registering FEC device\n", __func__); - mx28_add_fec(0, &tx28_fec_data); + pr_debug("%s: Registering FEC0 device\n", __func__); + mx28_add_fec(0, &tx28_fec0_data); return 0; free_gpios: @@ -129,3 +142,19 @@ free_gpios: return ret; } + +int __init tx28_add_fec1(void) +{ + int ret; + + ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, + ARRAY_SIZE(tx28_fec1_pads)); + if (ret) { + pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", + __func__, ret); + return ret; + } + pr_debug("%s: Registering FEC1 device\n", __func__); + mx28_add_fec(1, &tx28_fec1_data); + return 0; +} diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h index df9e1b6e81b..8ed425457d3 100644 --- a/arch/arm/mach-mxs/module-tx28.h +++ b/arch/arm/mach-mxs/module-tx28.h @@ -7,3 +7,4 @@ * Free Software Foundation. */ int __init tx28_add_fec0(void); +int __init tx28_add_fec1(void); diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 13647f30186..cace0d2e5a5 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -101,11 +101,6 @@ static cycle_t timrotv1_get_cycles(struct clocksource *cs) & 0xffff0000) >> 16); } -static cycle_t timrotv2_get_cycles(struct clocksource *cs) -{ - return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); -} - static int timrotv1_set_next_event(unsigned long evt, struct clock_event_device *dev) { @@ -230,8 +225,8 @@ static int __init mxs_clockevent_init(struct clk *timer_clk) static struct clocksource clocksource_mxs = { .name = "mxs_timer", .rating = 200, - .read = timrotv2_get_cycles, - .mask = CLOCKSOURCE_MASK(32), + .read = timrotv1_get_cycles, + .mask = CLOCKSOURCE_MASK(16), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -239,12 +234,11 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (timrot_is_v1()) { - clocksource_mxs.read = timrotv1_get_cycles; - clocksource_mxs.mask = CLOCKSOURCE_MASK(16); - } - - clocksource_register_hz(&clocksource_mxs, c); + if (timrot_is_v1()) + clocksource_register_hz(&clocksource_mxs, c); + else + clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), + "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); return 0; } diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 29ffa750fbe..00023b5cf12 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -171,13 +171,13 @@ void __init netx_init_irq(void) vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { - set_irq_chip(irq, &netx_hif_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &netx_hif_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); - set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); + irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); } static int __init netx_init(void) diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index f12f22d09b6..e24c141ba48 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c @@ -104,19 +104,6 @@ static struct irqaction netx_timer_irq = { .handler = netx_timer_interrupt, }; -cycle_t netx_get_cycles(struct clocksource *cs) -{ - return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); -} - -static struct clocksource clocksource_netx = { - .name = "netx_timer", - .rating = 200, - .read = netx_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - /* * Set up timer interrupt */ @@ -150,7 +137,8 @@ static void __init netx_timer_init(void) writel(NETX_GPIO_COUNTER_CTRL_RUN, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); - clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE); + clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), + "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, netx_clockevent.shift); diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig deleted file mode 100644 index dd0cd5ac4b8..00000000000 --- a/arch/arm/mach-ns9xxx/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -if ARCH_NS9XXX - -menu "NS9xxx Implementations" - -config NS9XXX_HAVE_SERIAL8250 - bool - -config PROCESSOR_NS9360 - bool - -config MODULE_CC9P9360 - bool - select PROCESSOR_NS9360 - -config BOARD_A9M9750DEV - select NS9XXX_HAVE_SERIAL8250 - bool - -config BOARD_JSCC9P9360 - bool - -config MACH_CC9P9360DEV - bool "ConnectCore 9P 9360 on an A9M9750 Devboard" - select MODULE_CC9P9360 - select BOARD_A9M9750DEV - help - Say Y here if you are using the Digi ConnectCore 9P 9360 - on an A9M9750 Development Board. - -config MACH_CC9P9360JS - bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" - select MODULE_CC9P9360 - select BOARD_JSCC9P9360 - help - Say Y here if you are using the Digi ConnectCore 9P 9360 - on an JSCC9P9360 Development Board. - -endmenu - -endif diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile deleted file mode 100644 index 41efaf9ad50..00000000000 --- a/arch/arm/mach-ns9xxx/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -obj-y := clock.o generic.o gpio.o irq.o - -obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o -obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o - -obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o - -obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o -obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o - -# platform devices -obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot deleted file mode 100644 index 54654919229..00000000000 --- a/arch/arm/mach-ns9xxx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ -zreladdr-y := 0x8000 -params_phys-y := 0x100 diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c deleted file mode 100644 index 0c0d5248c36..00000000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-a9m9750dev.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/irq.h> - -#include <asm/mach/map.h> -#include <asm/gpio.h> - -#include <mach/board.h> -#include <mach/processor-ns9360.h> -#include <mach/regs-sys-ns9360.h> -#include <mach/regs-mem.h> -#include <mach/regs-bbu.h> -#include <mach/regs-board-a9m9750dev.h> - -#include "board-a9m9750dev.h" - -static struct map_desc board_a9m9750dev_io_desc[] __initdata = { - { /* FPGA on CS0 */ - .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)), - .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)), - .length = NS9XXX_CS0STAT_LENGTH, - .type = MT_DEVICE, - }, -}; - -void __init board_a9m9750dev_map_io(void) -{ - iotable_init(board_a9m9750dev_io_desc, - ARRAY_SIZE(board_a9m9750dev_io_desc)); -} - -static void a9m9750dev_fpga_ack_irq(struct irq_data *d) -{ - /* nothing */ -} - -static void a9m9750dev_fpga_mask_irq(struct irq_data *d) -{ - u8 ier; - - ier = __raw_readb(FPGA_IER); - - ier &= ~(1 << (d->irq - FPGA_IRQ(0))); - - __raw_writeb(ier, FPGA_IER); -} - -static void a9m9750dev_fpga_maskack_irq(struct irq_data *d) -{ - a9m9750dev_fpga_mask_irq(d); - a9m9750dev_fpga_ack_irq(d); -} - -static void a9m9750dev_fpga_unmask_irq(struct irq_data *d) -{ - u8 ier; - - ier = __raw_readb(FPGA_IER); - - ier |= 1 << (d->irq - FPGA_IRQ(0)); - - __raw_writeb(ier, FPGA_IER); -} - -static struct irq_chip a9m9750dev_fpga_chip = { - .irq_ack = a9m9750dev_fpga_ack_irq, - .irq_mask = a9m9750dev_fpga_mask_irq, - .irq_mask_ack = a9m9750dev_fpga_maskack_irq, - .irq_unmask = a9m9750dev_fpga_unmask_irq, -}; - -static void a9m9750dev_fpga_demux_handler(unsigned int irq, - struct irq_desc *desc) -{ - u8 stat = __raw_readb(FPGA_ISR); - - desc->irq_data.chip->irq_mask_ack(&desc->irq_data); - - while (stat != 0) { - int irqno = fls(stat) - 1; - - stat &= ~(1 << irqno); - - generic_handle_irq(FPGA_IRQ(irqno)); - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -void __init board_a9m9750dev_init_irq(void) -{ - u32 eic; - int i; - - if (gpio_request(11, "board a9m9750dev extirq2") == 0) - ns9360_gpio_configure(11, 0, 1); - else - printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", - __func__); - - for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { - set_irq_chip(i, &a9m9750dev_fpga_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - - /* IRQ_NS9XXX_EXT2: level sensitive + active low */ - eic = __raw_readl(SYS_EIC(2)); - REGSET(eic, SYS_EIC, PLTY, AL); - REGSET(eic, SYS_EIC, LVEDG, LEVEL); - __raw_writel(eic, SYS_EIC(2)); - - set_irq_chained_handler(IRQ_NS9XXX_EXT2, - a9m9750dev_fpga_demux_handler); -} - -void __init board_a9m9750dev_init_machine(void) -{ - u32 reg; - - /* setup static CS0: memory base ... */ - reg = __raw_readl(SYS_SMCSSMB(0)); - REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); - __raw_writel(reg, SYS_SMCSSMB(0)); - - /* ... and mask */ - reg = __raw_readl(SYS_SMCSSMM(0)); - REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); - REGSET(reg, SYS_SMCSSMM, CSEx, EN); - __raw_writel(reg, SYS_SMCSSMM(0)); - - /* setup static CS0: memory configuration */ - reg = __raw_readl(MEM_SMC(0)); - REGSET(reg, MEM_SMC, PSMC, OFF); - REGSET(reg, MEM_SMC, BSMC, OFF); - REGSET(reg, MEM_SMC, EW, OFF); - REGSET(reg, MEM_SMC, PB, 1); - REGSET(reg, MEM_SMC, PC, AL); - REGSET(reg, MEM_SMC, PM, DIS); - REGSET(reg, MEM_SMC, MW, 8); - __raw_writel(reg, MEM_SMC(0)); - - /* setup static CS0: timing */ - __raw_writel(0x2, MEM_SMWED(0)); - __raw_writel(0x2, MEM_SMOED(0)); - __raw_writel(0x6, MEM_SMRD(0)); - __raw_writel(0x6, MEM_SMWD(0)); -} diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.h b/arch/arm/mach-ns9xxx/board-a9m9750dev.h deleted file mode 100644 index edc75abbc5d..00000000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-a9m9750dev.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/init.h> - -void __init board_a9m9750dev_map_io(void); -void __init board_a9m9750dev_init_machine(void); -void __init board_a9m9750dev_init_irq(void); diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.c b/arch/arm/mach-ns9xxx/board-jscc9p9360.c deleted file mode 100644 index 4bd3eec04bf..00000000000 --- a/arch/arm/mach-ns9xxx/board-jscc9p9360.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-jscc9p9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include "board-jscc9p9360.h" - -void __init board_jscc9p9360_init_machine(void) -{ - /* TODO: reserve GPIOs for push buttons, etc pp */ -} - diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.h b/arch/arm/mach-ns9xxx/board-jscc9p9360.h deleted file mode 100644 index 1a81a074df4..00000000000 --- a/arch/arm/mach-ns9xxx/board-jscc9p9360.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-jscc9p9360.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/init.h> - -void __init board_jscc9p9360_init_machine(void); diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c deleted file mode 100644 index cf81cbc5754..00000000000 --- a/arch/arm/mach-ns9xxx/clock.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/clock.c - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/err.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/semaphore.h> - -#include "clock.h" - -static LIST_HEAD(clocks); -static DEFINE_SPINLOCK(clk_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *ret = NULL, *retgen = NULL; - unsigned long flags; - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - spin_lock_irqsave(&clk_lock, flags); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0) { - if (p->id == idno) { - if (!try_module_get(p->owner)) - continue; - ret = p; - break; - } else if (p->id == -1) - /* remember match with id == -1 in case there is - * no clock for idno */ - retgen = p; - } - } - - if (!ret && retgen && try_module_get(retgen->owner)) - ret = retgen; - - if (ret) - ++ret->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret ? ret : ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); - --clk->refcount; -} -EXPORT_SYMBOL(clk_put); - -static int clk_enable_unlocked(struct clk *clk) -{ - int ret = 0; - if (clk->parent) { - ret = clk_enable_unlocked(clk->parent); - if (ret) - return ret; - } - - if (clk->usage++ == 0 && clk->endisable) - ret = clk->endisable(clk, 1); - - return ret; -} - -int clk_enable(struct clk *clk) -{ - int ret; - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - ret = clk_enable_unlocked(clk); - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -static void clk_disable_unlocked(struct clk *clk) -{ - if (--clk->usage == 0 && clk->endisable) - clk->endisable(clk, 0); - - if (clk->parent) - clk_disable_unlocked(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - clk_disable_unlocked(clk); - - spin_unlock_irqrestore(&clk_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk->get_rate) - return clk->get_rate(clk); - - if (clk->rate) - return clk->rate; - - if (clk->parent) - return clk_get_rate(clk->parent); - - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - -int clk_register(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - list_add(&clk->node, &clocks); - - if (clk->parent) - ++clk->parent->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} - -int clk_unregister(struct clk *clk) -{ - int ret = 0; - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - if (clk->usage || clk->refcount) - ret = -EBUSY; - else - list_del(&clk->node); - - if (clk->parent) - --clk->parent->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret; -} - -#if defined CONFIG_DEBUG_FS - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static int clk_debugfs_show(struct seq_file *s, void *null) -{ - unsigned long flags; - struct clk *p; - - spin_lock_irqsave(&clk_lock, flags); - - list_for_each_entry(p, &clocks, node) - seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n", - p->name, p->id, p->usage, p->refcount, - p->usage ? clk_get_rate(p) : 0); - - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} - -static int clk_debugfs_open(struct inode *inode, struct file *file) -{ - return single_open(file, clk_debugfs_show, NULL); -} - -static const struct file_operations clk_debugfs_operations = { - .open = clk_debugfs_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init clk_debugfs_init(void) -{ - struct dentry *dentry; - - dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL, - &clk_debugfs_operations); - return IS_ERR(dentry) ? PTR_ERR(dentry) : 0; -} -subsys_initcall(clk_debugfs_init); - -#endif /* if defined CONFIG_DEBUG_FS */ diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h deleted file mode 100644 index b86c30dd79e..00000000000 --- a/arch/arm/mach-ns9xxx/clock.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/clock.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __NS9XXX_CLOCK_H -#define __NS9XXX_CLOCK_H - -#include <linux/list.h> - -struct clk { - struct module *owner; - const char *name; - int id; - - struct clk *parent; - - unsigned long rate; - int (*endisable)(struct clk *, int enable); - unsigned long (*get_rate)(struct clk *); - - struct list_head node; - unsigned long refcount; - unsigned long usage; -}; - -int clk_register(struct clk *clk); -int clk_unregister(struct clk *clk); - -#endif /* ifndef __NS9XXX_CLOCK_H */ diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c deleted file mode 100644 index 1e0f467879c..00000000000 --- a/arch/arm/mach-ns9xxx/generic.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/generic.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <asm/memory.h> - -#include "generic.h" - -void __init ns9xxx_init_machine(void) -{ -} diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h deleted file mode 100644 index 82493191aad..00000000000 --- a/arch/arm/mach-ns9xxx/generic.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/generic.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/time.h> -#include <asm/mach/time.h> -#include <linux/init.h> - -void __init ns9xxx_init_irq(void); -void __init ns9xxx_init_machine(void); diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c deleted file mode 100644 index 377330c1b25..00000000000 --- a/arch/arm/mach-ns9xxx/gpio-ns9360.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio-ns9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/bug.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/module.h> - -#include <mach/regs-bbu.h> -#include <mach/processor-ns9360.h> - -#include "gpio-ns9360.h" - -static inline int ns9360_valid_gpio(unsigned gpio) -{ - return gpio <= 72; -} - -static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio) -{ - if (gpio < 56) - return BBU_GCONFb1(gpio / 8); - else - /* - * this could be optimised away on - * ns9750 only builds, but it isn't ... - */ - return BBU_GCONFb2((gpio - 56) / 8); -} - -static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio) -{ - if (gpio < 32) - return BBU_GCTRL1; - else if (gpio < 64) - return BBU_GCTRL2; - else - /* this could be optimised away on ns9750 only builds */ - return BBU_GCTRL3; -} - -static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio) -{ - if (gpio < 32) - return BBU_GSTAT1; - else if (gpio < 64) - return BBU_GSTAT2; - else - /* this could be optimised away on ns9750 only builds */ - return BBU_GSTAT3; -} - -/* - * each gpio can serve for 4 different purposes [0..3]. These are called - * "functions" and passed in the parameter func. Functions 0-2 are always some - * special things, function 3 is GPIO. If func == 3 dir specifies input or - * output, and with inv you can enable an inverter (independent of func). - */ -int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func) -{ - void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio); - u32 confval; - - confval = __raw_readl(conf); - REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); - REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); - REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); - __raw_writel(confval, conf); - - return 0; -} - -int ns9360_gpio_configure(unsigned gpio, int inv, int func) -{ - if (likely(ns9360_valid_gpio(gpio))) { - if (func == 3) { - printk(KERN_WARNING "use gpio_direction_input " - "or gpio_direction_output\n"); - return -EINVAL; - } else - return __ns9360_gpio_configure(gpio, 0, inv, func); - } else - return -EINVAL; -} -EXPORT_SYMBOL(ns9360_gpio_configure); - -int ns9360_gpio_get_value(unsigned gpio) -{ - void __iomem *stat = ns9360_gpio_get_gstataddr(gpio); - int ret; - - ret = 1 & (__raw_readl(stat) >> (gpio & 31)); - - return ret; -} - -void ns9360_gpio_set_value(unsigned gpio, int value) -{ - void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio); - u32 ctrlval; - - ctrlval = __raw_readl(ctrl); - - if (value) - ctrlval |= 1 << (gpio & 31); - else - ctrlval &= ~(1 << (gpio & 31)); - - __raw_writel(ctrlval, ctrl); -} diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h deleted file mode 100644 index 131cd1715ca..00000000000 --- a/arch/arm/mach-ns9xxx/gpio-ns9360.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio-ns9360.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func); -int ns9360_gpio_get_value(unsigned gpio); -void ns9360_gpio_set_value(unsigned gpio, int value); diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c deleted file mode 100644 index 5503ca09c4a..00000000000 --- a/arch/arm/mach-ns9xxx/gpio.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/compiler.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/module.h> -#include <linux/bitops.h> - -#include <mach/gpio.h> -#include <mach/processor.h> -#include <mach/processor-ns9360.h> -#include <asm/bug.h> -#include <asm/types.h> - -#include "gpio-ns9360.h" - -#if defined(CONFIG_PROCESSOR_NS9360) -#define GPIO_MAX 72 -#elif defined(CONFIG_PROCESSOR_NS9750) -#define GPIO_MAX 49 -#endif - -/* protects BBU_GCONFx and BBU_GCTRLx */ -static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock); - -/* only access gpiores with atomic ops */ -static DECLARE_BITMAP(gpiores, GPIO_MAX + 1); - -static inline int ns9xxx_valid_gpio(unsigned gpio) -{ -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - return gpio <= 72; - else -#endif -#if defined(CONFIG_PROCESSOR_NS9750) - if (processor_is_ns9750()) - return gpio <= 49; - else -#endif - { - BUG(); - return 0; - } -} - -int gpio_request(unsigned gpio, const char *label) -{ - if (likely(ns9xxx_valid_gpio(gpio))) - return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0; - else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_request); - -void gpio_free(unsigned gpio) -{ - might_sleep(); - clear_bit(gpio, gpiores); - return; -} -EXPORT_SYMBOL(gpio_free); - -int gpio_direction_input(unsigned gpio) -{ - if (likely(ns9xxx_valid_gpio(gpio))) { - int ret = -EINVAL; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ret = __ns9360_gpio_configure(gpio, 0, 0, 3); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return ret; - - } else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_direction_input); - -int gpio_direction_output(unsigned gpio, int value) -{ - if (likely(ns9xxx_valid_gpio(gpio))) { - int ret = -EINVAL; - unsigned long flags; - - gpio_set_value(gpio, value); - - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ret = __ns9360_gpio_configure(gpio, 1, 0, 3); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return ret; - } else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_direction_output); - -int gpio_get_value(unsigned gpio) -{ -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - return ns9360_gpio_get_value(gpio); - else -#endif - { - BUG(); - return -EINVAL; - } -} -EXPORT_SYMBOL(gpio_get_value); - -void gpio_set_value(unsigned gpio, int value) -{ - unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ns9360_gpio_set_value(gpio, value); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(gpio_set_value); diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h deleted file mode 100644 index f7e9196eb9a..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/board.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include <asm/mach-types.h> - -#define board_is_a9m9750dev() (0 \ - || machine_is_cc9p9360dev() \ - || machine_is_cc9p9750dev() \ - ) - -#define board_is_a9mvali() (0 \ - || machine_is_cc9p9360val() \ - || machine_is_cc9p9750val() \ - ) - -#define board_is_jscc9p9210() (0 \ - || machine_is_cc9p9210js() \ - ) - -#define board_is_jscc9p9215() (0 \ - || machine_is_cc9p9215js() \ - ) - -#define board_is_jscc9p9360() (0 \ - || machine_is_cc9p9360js() \ - ) - -#define board_is_uncbas() (0 \ - || machine_is_cc7ucamry() \ - ) - -#endif /* ifndef __ASM_ARCH_BOARD_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S deleted file mode 100644 index 5a2acbdc3d6..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/debug-macro.S - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <mach/hardware.h> -#include <asm/memory.h> - -#include <mach/regs-board-a9m9750dev.h> - - .macro addruart, rp, rv - ldr \rp, =NS9XXX_CSxSTAT_PHYS(0) - ldr \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0)) - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S deleted file mode 100644 index 71ca0319b54..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/entry-macro.S - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <mach/hardware.h> -#include <mach/regs-sys-common.h> - - .macro get_irqnr_preamble, base, tmp - ldr \base, =SYS_ISRADDR - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] - cmp \irqstat, #0 - ldrne \irqnr, [\base] - .endm - - .macro disable_fiq - .endm diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h deleted file mode 100644 index 5eb34903257..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/gpio.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/gpio.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. -*/ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#include <asm/errno.h> - -int gpio_request(unsigned gpio, const char *label); - -void gpio_free(unsigned gpio); - -int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); - -int gpio_direction_input(unsigned gpio); - -int gpio_direction_output(unsigned gpio, int value); - -int gpio_get_value(unsigned gpio); - -void gpio_set_value(unsigned gpio, int value); - -/* - * ns9xxx can use gpio pins to trigger an irq, but it's not generic - * enough to be supported by the gpio_to_irq/irq_to_gpio interface - */ -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -/* get the cansleep() stubs */ -#include <asm-generic/gpio.h> - -#endif /* ifndef __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h deleted file mode 100644 index 76631128e11..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/hardware.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/hardware.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * NetSilicon NS9xxx internal mapping: - * - * physical <--> virtual - * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff - * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff - */ -#define io_p2v(x) (0xf0000000 \ - + (((x) & 0xf0000000) >> 4) \ - + ((x) & 0x00ffffff)) - -#define io_v2p(x) ((((x) & 0x0f000000) << 4) \ - + ((x) & 0x00ffffff)) - -#define __REGSHIFT(mask) ((mask) & (-(mask))) - -#define __REGBIT(bit) ((u32)1 << (bit)) -#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) -#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) - -#ifndef __ASSEMBLY__ - -# define __REG(x) ((void __iomem __force *)io_p2v((x))) -# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) - -# define __REGSET(var, field, value) \ - ((var) = (((var) & ~((field) & ~(value))) | (value))) - -# define REGSET(var, reg, field, value) \ - __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value) - -# define REGSET_IDX(var, reg, field, idx, value) \ - __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx))) - -# define REGSETIM(var, reg, field, value) \ - __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value))) - -# define REGSETIM_IDX(var, reg, field, idx, value) \ - __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value))) - -# define __REGGET(var, field) \ - (((var) & (field))) - -# define REGGET(var, reg, field) \ - __REGGET(var, reg ## _ ## field) - -# define REGGET_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) - -# define REGGETIM(var, reg, field) \ - __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) - -# define REGGETIM_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) / \ - __REGSHIFT(reg ## _ ## field((idx))) - -#else - -# define __REG(x) io_p2v(x) -# define __REG2(x, y) io_p2v((x) + 4 * (y)) - -#endif - -#endif /* ifndef __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h deleted file mode 100644 index f08451d2e1b..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/io.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/io.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff /* XXX */ - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (IO_BASE + (a)) - -#endif /* ifndef __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h deleted file mode 100644 index 13483949e21..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/irqs.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/irqs.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* NetSilicon 9360 */ -#define IRQ_NS9XXX_WATCHDOG 0 -#define IRQ_NS9XXX_AHBBUSERR 1 -#define IRQ_NS9360_BBUSAGG 2 -/* irq 3 is reserved for NS9360 */ -#define IRQ_NS9XXX_ETHRX 4 -#define IRQ_NS9XXX_ETHTX 5 -#define IRQ_NS9XXX_ETHPHY 6 -#define IRQ_NS9360_LCD 7 -#define IRQ_NS9360_SERBRX 8 -#define IRQ_NS9360_SERBTX 9 -#define IRQ_NS9360_SERARX 10 -#define IRQ_NS9360_SERATX 11 -#define IRQ_NS9360_SERCRX 12 -#define IRQ_NS9360_SERCTX 13 -#define IRQ_NS9360_I2C 14 -#define IRQ_NS9360_BBUSDMA 15 -#define IRQ_NS9360_TIMER0 16 -#define IRQ_NS9360_TIMER1 17 -#define IRQ_NS9360_TIMER2 18 -#define IRQ_NS9360_TIMER3 19 -#define IRQ_NS9360_TIMER4 20 -#define IRQ_NS9360_TIMER5 21 -#define IRQ_NS9360_TIMER6 22 -#define IRQ_NS9360_TIMER7 23 -#define IRQ_NS9360_RTC 24 -#define IRQ_NS9360_USBHOST 25 -#define IRQ_NS9360_USBDEVICE 26 -#define IRQ_NS9360_IEEE1284 27 -#define IRQ_NS9XXX_EXT0 28 -#define IRQ_NS9XXX_EXT1 29 -#define IRQ_NS9XXX_EXT2 30 -#define IRQ_NS9XXX_EXT3 31 - -#define BBUS_IRQ(irq) (32 + irq) - -#define IRQ_BBUS_DMA BBUS_IRQ(0) -#define IRQ_BBUS_SERBRX BBUS_IRQ(2) -#define IRQ_BBUS_SERBTX BBUS_IRQ(3) -#define IRQ_BBUS_SERARX BBUS_IRQ(4) -#define IRQ_BBUS_SERATX BBUS_IRQ(5) -#define IRQ_BBUS_SERCRX BBUS_IRQ(6) -#define IRQ_BBUS_SERCTX BBUS_IRQ(7) -#define IRQ_BBUS_SERDRX BBUS_IRQ(8) -#define IRQ_BBUS_SERDTX BBUS_IRQ(9) -#define IRQ_BBUS_I2C BBUS_IRQ(10) -#define IRQ_BBUS_1284 BBUS_IRQ(11) -#define IRQ_BBUS_UTIL BBUS_IRQ(12) -#define IRQ_BBUS_RTC BBUS_IRQ(13) -#define IRQ_BBUS_USBHST BBUS_IRQ(14) -#define IRQ_BBUS_USBDEV BBUS_IRQ(15) -#define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24) -#define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25) - -/* - * these Interrupts are specific for the a9m9750dev board. - * They are generated by an FPGA that interrupts the CPU on - * IRQ_NS9360_EXT2 - */ -#define FPGA_IRQ(irq) (64 + irq) - -#define IRQ_FPGA_UARTA FPGA_IRQ(0) -#define IRQ_FPGA_UARTB FPGA_IRQ(1) -#define IRQ_FPGA_UARTC FPGA_IRQ(2) -#define IRQ_FPGA_UARTD FPGA_IRQ(3) -#define IRQ_FPGA_TOUCH FPGA_IRQ(4) -#define IRQ_FPGA_CF FPGA_IRQ(5) -#define IRQ_FPGA_CAN0 FPGA_IRQ(6) -#define IRQ_FPGA_CAN1 FPGA_IRQ(7) - -#define NR_IRQS 72 - -#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h deleted file mode 100644 index 5c65aee6e7a..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/memory.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/memory.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. -*/ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* x in [0..3] */ -#define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28) - -#define NS9XXX_CS0STAT_LENGTH UL(0x1000) -#define NS9XXX_CS1STAT_LENGTH UL(0x1000) -#define NS9XXX_CS2STAT_LENGTH UL(0x1000) -#define NS9XXX_CS3STAT_LENGTH UL(0x1000) - -#define PLAT_PHYS_OFFSET UL(0x00000000) - -#endif diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h deleted file mode 100644 index f851a6b7da6..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/module.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_MODULE_H -#define __ASM_ARCH_MODULE_H - -#include <asm/mach-types.h> - -#define module_is_cc7ucamry() (0 \ - || machine_is_cc7ucamry() \ - ) - -#define module_is_cc9c() (0 \ - || machine_is_cc9c() \ - ) - -#define module_is_cc9p9210() (0 \ - || machine_is_cc9p9210() \ - || machine_is_cc9p9210js() \ - ) - -#define module_is_cc9p9215() (0 \ - || machine_is_cc9p9215() \ - || machine_is_cc9p9215js() \ - ) - -#define module_is_cc9p9360() (0 \ - || machine_is_a9m9360() \ - || machine_is_cc9p9360dev() \ - || machine_is_cc9p9360js() \ - || machine_is_cc9p9360val() \ - ) - -#define module_is_cc9p9750() (0 \ - || machine_is_a9m9750() \ - || machine_is_cc9p9750dev() \ - || machine_is_cc9p9750js() \ - || machine_is_cc9p9750val() \ - ) - -#define module_is_ccw9c() (0 \ - || machine_is_ccw9c() \ - ) - -#define module_is_inc20otter() (0 \ - || machine_is_inc20otter() \ - ) - -#define module_is_otter() (0 \ - || machine_is_otter() \ - ) - -#endif /* ifndef __ASM_ARCH_MODULE_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h deleted file mode 100644 index f41deda5129..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_PROCESSORNS9360_H -#define __ASM_ARCH_PROCESSORNS9360_H - -#include <linux/init.h> - -void ns9360_reset(char mode); - -unsigned long ns9360_systemclock(void) __attribute__((const)); - -static inline unsigned long ns9360_cpuclock(void) __attribute__((const)); -static inline unsigned long ns9360_cpuclock(void) -{ - return ns9360_systemclock() / 2; -} - -void __init ns9360_map_io(void); - -extern struct sys_timer ns9360_timer; - -int ns9360_gpio_configure(unsigned gpio, int inv, int func); - -#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h deleted file mode 100644 index 9f77f746a38..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/processor.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/processor.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_PROCESSOR_H -#define __ASM_ARCH_PROCESSOR_H - -#include <mach/module.h> - -#define processor_is_ns9210() (0 \ - || module_is_cc7ucamry() \ - || module_is_cc9p9210() \ - || module_is_inc20otter() \ - || module_is_otter() \ - ) - -#define processor_is_ns9215() (0 \ - || module_is_cc9p9215() \ - ) - -#define processor_is_ns9360() (0 \ - || module_is_cc9p9360() \ - || module_is_cc9c() \ - || module_is_ccw9c() \ - ) - -#define processor_is_ns9750() (0 \ - || module_is_cc9p9750() \ - ) - -#define processor_is_ns921x() (0 \ - || processor_is_ns9210() \ - || processor_is_ns9215() \ - ) - -#endif /* ifndef __ASM_ARCH_PROCESSOR_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h deleted file mode 100644 index af227c058fb..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSBBU_H -#define __ASM_ARCH_REGSBBU_H - -#include <mach/hardware.h> - -/* BBus Utility */ - -/* GPIO Configuration Registers block 1 */ -/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is - * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register - * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ -#define BBU_GCONFb1(x) __REG2(0x90600010, (x)) -#define BBU_GCONFb2(x) __REG2(0x90600100, (x)) - -#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) -#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) -#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) -#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) -#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) -#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) -#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) -#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) -#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) -#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) -#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) - -#define BBU_GCTRL1 __REG(0x90600030) -#define BBU_GCTRL2 __REG(0x90600034) -#define BBU_GCTRL3 __REG(0x90600120) - -#define BBU_GSTAT1 __REG(0x90600040) -#define BBU_GSTAT2 __REG(0x90600044) -#define BBU_GSTAT3 __REG(0x90600130) - -#endif /* ifndef __ASM_ARCH_REGSBBU_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h deleted file mode 100644 index cd1593693f5..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSBOARDA9M9750_H -#define __ASM_ARCH_REGSBOARDA9M9750_H - -#include <mach/hardware.h> - -#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0)) -#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08) -#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) -#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) - -#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50) -#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60) - -#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h deleted file mode 100644 index f1625bf8cdc..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-mem.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSMEM_H -#define __ASM_ARCH_REGSMEM_H - -#include <mach/hardware.h> - -/* Memory Module */ - -/* Control register */ -#define MEM_CTRL __REG(0xa0700000) - -/* Status register */ -#define MEM_STAT __REG(0xa0700004) - -/* Configuration register */ -#define MEM_CONF __REG(0xa0700008) - -/* Dynamic Memory Control register */ -#define MEM_DMCTRL __REG(0xa0700020) - -/* Dynamic Memory Refresh Timer */ -#define MEM_DMRT __REG(0xa0700024) - -/* Dynamic Memory Read Configuration register */ -#define MEM_DMRC __REG(0xa0700028) - -/* Dynamic Memory Precharge Command Period (tRP) */ -#define MEM_DMPCP __REG(0xa0700030) - -/* Dynamic Memory Active to Precharge Command Period (tRAS) */ -#define MEM_DMAPCP __REG(0xa0700034) - -/* Dynamic Memory Self-Refresh Exit Time (tSREX) */ -#define MEM_DMSRET __REG(0xa0700038) - -/* Dynamic Memory Last Data Out to Active Time (tAPR) */ -#define MEM_DMLDOAT __REG(0xa070003c) - -/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */ -#define MEM_DMDIACT __REG(0xa0700040) - -/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */ -#define MEM_DMWRT __REG(0xa0700044) - -/* Dynamic Memory Active to Active Command Period (tRC) */ -#define MEM_DMAACP __REG(0xa0700048) - -/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */ -#define MEM_DMARP __REG(0xa070004c) - -/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */ -#define MEM_DMESRAC __REG(0xa0700050) - -/* Dynamic Memory Active Bank A to Active B Time (tRRD) */ -#define MEM_DMABAABT __REG(0xa0700054) - -/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */ -#define MEM_DMLMACT __REG(0xa0700058) - -/* Static Memory Extended Wait */ -#define MEM_SMEW __REG(0xa0700080) - -/* Dynamic Memory Configuration Register x */ -#define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3) - -/* Dynamic Memory RAS and CAS Delay x */ -#define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3) - -/* Static Memory Configuration Register x */ -#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3) - -/* Static Memory Configuration Register x: Write protect */ -#define MEM_SMC_PSMC __REGBIT(20) -#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0) -#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1) - -/* Static Memory Configuration Register x: Buffer enable */ -#define MEM_SMC_BSMC __REGBIT(19) -#define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0) -#define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1) - -/* Static Memory Configuration Register x: Extended Wait */ -#define MEM_SMC_EW __REGBIT(8) -#define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0) -#define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1) - -/* Static Memory Configuration Register x: Byte lane state */ -#define MEM_SMC_PB __REGBIT(7) -#define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0) -#define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1) - -/* Static Memory Configuration Register x: Chip select polarity */ -#define MEM_SMC_PC __REGBIT(6) -#define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0) -#define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1) - -/* static memory configuration register x: page mode*/ -#define MEM_SMC_PM __REGBIT(3) -#define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0) -#define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1) - -/* static memory configuration register x: Memory width */ -#define MEM_SMC_MW __REGBITS(1, 0) -#define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0) -#define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1) -#define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2) - -/* Static Memory Write Enable Delay x */ -#define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3) - -/* Static Memory Output Enable Delay x */ -#define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3) - -/* Static Memory Read Delay x */ -#define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3) - -/* Static Memory Page Mode Read Delay 0 */ -#define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3) - -/* Static Memory Write Delay */ -#define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3) - -/* Static Memory Turn Round Delay x */ -#define MEM_SWT(x) __REG2(0xa0700218, (x) << 3) - -#endif /* ifndef __ASM_ARCH_REGSMEM_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h deleted file mode 100644 index 14f91dfd573..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_REGSSYSCOMMON_H -#define __ASM_ARCH_REGSSYSCOMMON_H -#include <mach/hardware.h> - -/* Interrupt Vector Address Register Level x */ -#define SYS_IVA(x) __REG2(0xa09000c4, (x)) - -/* Interrupt Configuration registers */ -#define SYS_IC(x) __REG2(0xa0900144, (x)) - -/* ISRADDR */ -#define SYS_ISRADDR __REG(0xa0900164) - -/* Interrupt Status Active */ -#define SYS_ISA __REG(0xa0900168) - -/* Interrupt Status Raw */ -#define SYS_ISR __REG(0xa090016c) - -#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h deleted file mode 100644 index 8ff254d9901..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSSYSNS9360_H -#define __ASM_ARCH_REGSSYSNS9360_H - -#include <mach/hardware.h> - -/* System Control Module */ - -/* AHB Arbiter Gen Configuration */ -#define SYS_AHBAGENCONF __REG(0xa0900000) - -/* BRC */ -#define SYS_BRC(x) __REG2(0xa0900004, (x)) - -/* Timer x Reload Count register */ -#define SYS_TRC(x) __REG2(0xa0900044, (x)) - -/* Timer x Read register */ -#define SYS_TR(x) __REG2(0xa0900084, (x)) - -/* Timer Interrupt Status register */ -#define SYS_TIS __REG(0xa0900170) - -/* PLL Configuration register */ -#define SYS_PLL __REG(0xa0900188) - -/* PLL FS status */ -#define SYS_PLL_FS __REGBITS(24, 23) - -/* PLL ND status */ -#define SYS_PLL_ND __REGBITS(20, 16) - -/* PLL Configuration register: PLL SW change */ -#define SYS_PLL_SWC __REGBIT(15) -#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0) -#define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1) - -/* Timer x Control register */ -#define SYS_TC(x) __REG2(0xa0900190, (x)) - -/* Timer x Control register: Timer enable */ -#define SYS_TCx_TEN __REGBIT(15) -#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0) -#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1) - -/* Timer x Control register: CPU debug mode */ -#define SYS_TCx_TDBG __REGBIT(10) -#define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0) -#define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1) - -/* Timer x Control register: Interrupt clear */ -#define SYS_TCx_INTC __REGBIT(9) -#define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0) -#define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1) - -/* Timer x Control register: Timer clock select */ -#define SYS_TCx_TLCS __REGBITS(8, 6) -#define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */ -#define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */ -#define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */ -#define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */ -#define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */ -#define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */ -#define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */ -#define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7) - -/* Timer x Control register: Timer mode */ -#define SYS_TCx_TM __REGBITS(5, 4) -#define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */ -#define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */ -#define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */ -#define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */ - -/* Timer x Control register: Interrupt select */ -#define SYS_TCx_INTS __REGBIT(3) -#define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0) -#define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1) - -/* Timer x Control register: Up/down select */ -#define SYS_TCx_UDS __REGBIT(2) -#define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0) -#define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1) - -/* Timer x Control register: 32- or 16-bit timer */ -#define SYS_TCx_TSZ __REGBIT(1) -#define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0) -#define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1) - -/* Timer x Control register: Reload enable */ -#define SYS_TCx_REN __REGBIT(0) -#define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0) -#define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1) - -/* System Memory Chip Select x Dynamic Memory Base */ -#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1) - -/* System Memory Chip Select x Dynamic Memory Mask */ -#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1) - -/* System Memory Chip Select x Static Memory Base */ -#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1) - -/* System Memory Chip Select x Static Memory Base: Chip select x base */ -#define SYS_SMCSSMB_CSxB __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask */ -#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1) - -/* System Memory Chip Select x Static Memory Mask: Chip select x mask */ -#define SYS_SMCSSMM_CSxM __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask: Chip select x enable */ -#define SYS_SMCSSMM_CSEx __REGBIT(0) -#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0) -#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1) - -/* General purpose, user-defined ID register */ -#define SYS_GENID __REG(0xa0900210) - -/* External Interrupt x Control register */ -#define SYS_EIC(x) __REG2(0xa0900214, (x)) - -/* External Interrupt x Control register: Status */ -#define SYS_EIC_STS __REGBIT(3) - -/* External Interrupt x Control register: Clear */ -#define SYS_EIC_CLR __REGBIT(2) - -/* External Interrupt x Control register: Polarity */ -#define SYS_EIC_PLTY __REGBIT(1) -#define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0) -#define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1) - -/* External Interrupt x Control register: Level edge */ -#define SYS_EIC_LVEDG __REGBIT(0) -#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) -#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) - -#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h deleted file mode 100644 index 1561588ca36..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/system.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/system.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <asm/proc-fns.h> -#include <mach/processor.h> -#include <mach/processor-ns9360.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ -#ifdef CONFIG_PROCESSOR_NS9360 - if (processor_is_ns9360()) - ns9360_reset(mode); - else -#endif - BUG(); - - BUG(); -} - -#endif /* ifndef __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h deleted file mode 100644 index 734a8d8bd57..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/timex.h - * - * Copyright (C) 2005-2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* - * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h. - * See there for an explanation. - */ -#define CLOCK_TICK_RATE 12000000 - -#endif /* ifndef __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h deleted file mode 100644 index 770a68c46e8..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/uncompress.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> - -#define __REG(x) ((void __iomem __force *)(x)) - -static void putc_dummy(char c, void __iomem *base) -{ - /* nothing */ -} - -static int timeout; - -static void putc_ns9360(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (__raw_readl(base + 8) & (1 << 3)) { - __raw_writeb(c, base + 16); - timeout = 0x10000; - break; - } - } while (timeout); -} - -static void putc_a9m9750dev(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (__raw_readb(base + 5) & (1 << 5)) { - __raw_writeb(c, base); - timeout = 0x10000; - break; - } - } while (timeout); - -} - -static void putc_ns921x(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (!(__raw_readl(base) & (1 << 11))) { - __raw_writeb(c, base + 0x0028); - timeout = 0x10000; - break; - } - } while (timeout); -} - -#define MSCS __REG(0xA0900184) - -#define NS9360_UARTA __REG(0x90200040) -#define NS9360_UARTB __REG(0x90200000) -#define NS9360_UARTC __REG(0x90300000) -#define NS9360_UARTD __REG(0x90300040) - -#define NS9360_UART_ENABLED(base) \ - (__raw_readl(NS9360_UARTA) & (1 << 31)) - -#define A9M9750DEV_UARTA __REG(0x40000000) - -#define NS921XSYS_CLOCK __REG(0xa090017c) -#define NS921X_UARTA __REG(0x90010000) -#define NS921X_UARTB __REG(0x90018000) -#define NS921X_UARTC __REG(0x90020000) -#define NS921X_UARTD __REG(0x90028000) - -#define NS921X_UART_ENABLED(base) \ - (__raw_readl((base) + 0x1000) & (1 << 29)) - -static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) -{ - timeout = 0x10000; - if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { - /* ns9360 or ns9750 */ - if (NS9360_UART_ENABLED(NS9360_UARTA)) { - *putc = putc_ns9360; - *base = NS9360_UARTA; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { - *putc = putc_ns9360; - *base = NS9360_UARTB; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { - *putc = putc_ns9360; - *base = NS9360_UARTC; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { - *putc = putc_ns9360; - *base = NS9360_UARTD; - return; - } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { - *putc = putc_a9m9750dev; - *base = A9M9750DEV_UARTA; - return; - } - } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { - /* ns921x */ - u32 clock = __raw_readl(NS921XSYS_CLOCK); - - if ((clock & (1 << 1)) && - NS921X_UART_ENABLED(NS921X_UARTA)) { - *putc = putc_ns921x; - *base = NS921X_UARTA; - return; - } else if ((clock & (1 << 2)) && - NS921X_UART_ENABLED(NS921X_UARTB)) { - *putc = putc_ns921x; - *base = NS921X_UARTB; - return; - } else if ((clock & (1 << 3)) && - NS921X_UART_ENABLED(NS921X_UARTC)) { - *putc = putc_ns921x; - *base = NS921X_UARTC; - return; - } else if ((clock & (1 << 4)) && - NS921X_UART_ENABLED(NS921X_UARTD)) { - *putc = putc_ns921x; - *base = NS921X_UARTD; - return; - } - } - - *putc = putc_dummy; -} - -void (*myputc)(char, void __iomem *); -void __iomem *base; - -static void putc(char c) -{ - myputc(c, base); -} - -static void arch_decomp_setup(void) -{ - autodetect(&myputc, &base); -} -#define arch_decomp_wdog() - -static void flush(void) -{ - /* nothing */ -} - -#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h deleted file mode 100644 index c8651974c4b..00000000000 --- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/vmalloc.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END (0xf0000000UL) - -#endif /* ifndef __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c deleted file mode 100644 index 389fa5c669d..00000000000 --- a/arch/arm/mach-ns9xxx/irq.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/irq.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/io.h> -#include <asm/mach/irq.h> -#include <mach/regs-sys-common.h> -#include <mach/irqs.h> -#include <mach/board.h> - -#include "generic.h" - -/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */ -#define irq2prio(i) (i) -#define prio2irq(p) (p) - -static void ns9xxx_mask_irq(struct irq_data *d) -{ - /* XXX: better use cpp symbols */ - int prio = irq2prio(d->irq); - u32 ic = __raw_readl(SYS_IC(prio / 4)); - ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); - __raw_writel(ic, SYS_IC(prio / 4)); -} - -static void ns9xxx_ack_irq(struct irq_data *d) -{ - __raw_writel(0, SYS_ISRADDR); -} - -static void ns9xxx_maskack_irq(struct irq_data *d) -{ - ns9xxx_mask_irq(d); - ns9xxx_ack_irq(d); -} - -static void ns9xxx_unmask_irq(struct irq_data *d) -{ - /* XXX: better use cpp symbols */ - int prio = irq2prio(d->irq); - u32 ic = __raw_readl(SYS_IC(prio / 4)); - ic |= 1 << (7 + 8 * (3 - (prio & 3))); - __raw_writel(ic, SYS_IC(prio / 4)); -} - -static struct irq_chip ns9xxx_chip = { - .irq_ack = ns9xxx_ack_irq, - .irq_mask = ns9xxx_mask_irq, - .irq_mask_ack = ns9xxx_maskack_irq, - .irq_unmask = ns9xxx_unmask_irq, -}; - -#if 0 -#define handle_irq handle_level_irq -#else -static void handle_prio_irq(unsigned int irq, struct irq_desc *desc) -{ - struct irqaction *action; - irqreturn_t action_ret; - - raw_spin_lock(&desc->lock); - - BUG_ON(desc->status & IRQ_INPROGRESS); - - desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); - kstat_incr_irqs_this_cpu(irq, desc); - - action = desc->action; - if (unlikely(!action || (desc->status & IRQ_DISABLED))) - goto out_mask; - - desc->status |= IRQ_INPROGRESS; - raw_spin_unlock(&desc->lock); - - action_ret = handle_IRQ_event(irq, action); - - /* XXX: There is no direct way to access noirqdebug, so check - * unconditionally for spurious irqs... - * Maybe this function should go to kernel/irq/chip.c? */ - note_interrupt(irq, desc, action_ret); - - raw_spin_lock(&desc->lock); - desc->status &= ~IRQ_INPROGRESS; - - if (desc->status & IRQ_DISABLED) -out_mask: - desc->irq_data.chip->irq_mask(&desc->irq_data); - - /* ack unconditionally to unmask lower prio irqs */ - desc->irq_data.chip->irq_ack(&desc->irq_data); - - raw_spin_unlock(&desc->lock); -} -#define handle_irq handle_prio_irq -#endif - -void __init ns9xxx_init_irq(void) -{ - int i; - - /* disable all IRQs */ - for (i = 0; i < 8; ++i) - __raw_writel(prio2irq(4 * i) << 24 | - prio2irq(4 * i + 1) << 16 | - prio2irq(4 * i + 2) << 8 | - prio2irq(4 * i + 3), - SYS_IC(i)); - - for (i = 0; i < 32; ++i) - __raw_writel(prio2irq(i), SYS_IVA(i)); - - for (i = 0; i <= 31; ++i) { - set_irq_chip(i, &ns9xxx_chip); - set_irq_handler(i, handle_irq); - set_irq_flags(i, IRQF_VALID); - } -} diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c deleted file mode 100644 index 2858417d8d8..00000000000 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/processor-ns9360.h> - -#include "board-a9m9750dev.h" -#include "generic.h" - -static void __init mach_cc9p9360dev_map_io(void) -{ - ns9360_map_io(); - board_a9m9750dev_map_io(); -} - -static void __init mach_cc9p9360dev_init_irq(void) -{ - ns9xxx_init_irq(); - board_a9m9750dev_init_irq(); -} - -static void __init mach_cc9p9360dev_init_machine(void) -{ - ns9xxx_init_machine(); - board_a9m9750dev_init_machine(); -} - -MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard") - .map_io = mach_cc9p9360dev_map_io, - .init_irq = mach_cc9p9360dev_init_irq, - .init_machine = mach_cc9p9360dev_init_machine, - .timer = &ns9360_timer, - .boot_params = 0x100, -MACHINE_END diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c deleted file mode 100644 index 729f68da429..00000000000 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/mach-cc9p9360js.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/processor-ns9360.h> - -#include "board-jscc9p9360.h" -#include "generic.h" - -static void __init mach_cc9p9360js_init_machine(void) -{ - ns9xxx_init_machine(); - board_jscc9p9360_init_machine(); -} - -MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") - .map_io = ns9360_map_io, - .init_irq = ns9xxx_init_irq, - .init_machine = mach_cc9p9360js_init_machine, - .timer = &ns9360_timer, - .boot_params = 0x100, -MACHINE_END diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c deleted file mode 100644 index 463e92465fd..00000000000 --- a/arch/arm/mach-ns9xxx/plat-serial8250.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/plat-serial8250.c - * - * Copyright (C) 2008 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/slab.h> - -#include <mach/regs-board-a9m9750dev.h> -#include <mach/board.h> - -#define DRIVER_NAME "serial8250" - -static int __init ns9xxx_plat_serial8250_init(void) -{ - struct plat_serial8250_port *pdata; - struct platform_device *pdev; - int ret = -ENOMEM; - int i; - - if (!board_is_a9m9750dev()) - return -ENODEV; - - pdev = platform_device_alloc(DRIVER_NAME, 0); - if (!pdev) - goto err; - - pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL); - if (!pdata) - goto err; - - pdev->dev.platform_data = pdata; - - pdata[0].iobase = FPGA_UARTA_BASE; - pdata[1].iobase = FPGA_UARTB_BASE; - pdata[2].iobase = FPGA_UARTC_BASE; - pdata[3].iobase = FPGA_UARTD_BASE; - - for (i = 0; i < 4; ++i) { - pdata[i].membase = (void __iomem *)pdata[i].iobase; - pdata[i].mapbase = pdata[i].iobase; - pdata[i].iotype = UPIO_MEM; - pdata[i].uartclk = 18432000; - pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; - } - - pdata[0].irq = IRQ_FPGA_UARTA; - pdata[1].irq = IRQ_FPGA_UARTB; - pdata[2].irq = IRQ_FPGA_UARTC; - pdata[3].irq = IRQ_FPGA_UARTD; - - ret = platform_device_add(pdev); - if (ret) { -err: - platform_device_put(pdev); - - printk(KERN_WARNING "Could not add %s (errno=%d)\n", - DRIVER_NAME, ret); - } - - return 0; -} - -arch_initcall(ns9xxx_plat_serial8250_init); diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c deleted file mode 100644 index aed1999d24f..00000000000 --- a/arch/arm/mach-ns9xxx/processor-ns9360.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/processor-ns9360.c - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/io.h> -#include <linux/kernel.h> - -#include <asm/page.h> -#include <asm/mach/map.h> -#include <mach/processor-ns9360.h> -#include <mach/regs-sys-ns9360.h> - -void ns9360_reset(char mode) -{ - u32 reg; - - reg = __raw_readl(SYS_PLL) >> 16; - REGSET(reg, SYS_PLL, SWC, YES); - __raw_writel(reg, SYS_PLL); -} - -#define CRYSTAL 29491200 /* Hz */ -unsigned long ns9360_systemclock(void) -{ - u32 pll = __raw_readl(SYS_PLL); - return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) - >> REGGETIM(pll, SYS_PLL, FS); -} - -static struct map_desc ns9360_io_desc[] __initdata = { - { /* BBus */ - .virtual = io_p2v(0x90000000), - .pfn = __phys_to_pfn(0x90000000), - .length = 0x00700000, - .type = MT_DEVICE, - }, { /* AHB */ - .virtual = io_p2v(0xa0100000), - .pfn = __phys_to_pfn(0xa0100000), - .length = 0x00900000, - .type = MT_DEVICE, - }, -}; - -void __init ns9360_map_io(void) -{ - iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc)); -} diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c deleted file mode 100644 index 9ca32f55728..00000000000 --- a/arch/arm/mach-ns9xxx/time-ns9360.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/time-ns9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/jiffies.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/stringify.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> - -#include <mach/processor-ns9360.h> -#include <mach/regs-sys-ns9360.h> -#include <mach/irqs.h> -#include <mach/system.h> -#include "generic.h" - -#define TIMER_CLOCKSOURCE 0 -#define TIMER_CLOCKEVENT 1 -static u32 latch; - -static cycle_t ns9360_clocksource_read(struct clocksource *cs) -{ - return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); -} - -static struct clocksource ns9360_clocksource = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE), - .rating = 300, - .read = ns9360_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void ns9360_clockevent_setmode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); - REGSET(tc, SYS_TCx, REN, EN); - REGSET(tc, SYS_TCx, INTS, EN); - REGSET(tc, SYS_TCx, TEN, EN); - break; - - case CLOCK_EVT_MODE_ONESHOT: - REGSET(tc, SYS_TCx, REN, DIS); - REGSET(tc, SYS_TCx, INTS, EN); - - /* fall through */ - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - default: - REGSET(tc, SYS_TCx, TEN, DIS); - break; - } - - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); -} - -static int ns9360_clockevent_setnextevent(unsigned long evt, - struct clock_event_device *clk) -{ - u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - - if (REGGET(tc, SYS_TCx, TEN)) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - } - - REGSET(tc, SYS_TCx, TEN, EN); - - __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT)); - - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - - return 0; -} - -static struct clock_event_device ns9360_clockevent_device = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), - .shift = 20, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = ns9360_clockevent_setmode, - .set_next_event = ns9360_clockevent_setnextevent, -}; - -static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id) -{ - int timerno = irq - IRQ_NS9360_TIMER0; - u32 tc; - - struct clock_event_device *evt = &ns9360_clockevent_device; - - /* clear irq */ - tc = __raw_readl(SYS_TC(timerno)); - if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(timerno)); - } - REGSET(tc, SYS_TCx, INTC, SET); - __raw_writel(tc, SYS_TC(timerno)); - REGSET(tc, SYS_TCx, INTC, UNSET); - __raw_writel(tc, SYS_TC(timerno)); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction ns9360_clockevent_action = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ns9360_clockevent_handler, -}; - -static void __init ns9360_timer_init(void) -{ - int tc; - - tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE)); - if (REGGET(tc, SYS_TCx, TEN)) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); - } - - __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE)); - - REGSET(tc, SYS_TCx, TEN, EN); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TLCS, CPU); - REGSET(tc, SYS_TCx, TM, IEE); - REGSET(tc, SYS_TCx, INTS, DIS); - REGSET(tc, SYS_TCx, UDS, UP); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - - __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); - - clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock()); - - latch = SH_DIV(ns9360_cpuclock(), HZ, 0); - - tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - REGSET(tc, SYS_TCx, TEN, DIS); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TLCS, CPU); - REGSET(tc, SYS_TCx, TM, IEE); - REGSET(tc, SYS_TCx, INTS, DIS); - REGSET(tc, SYS_TCx, UDS, DOWN); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - - ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(), - NSEC_PER_SEC, ns9360_clockevent_device.shift); - ns9360_clockevent_device.max_delta_ns = - clockevent_delta2ns(-1, &ns9360_clockevent_device); - ns9360_clockevent_device.min_delta_ns = - clockevent_delta2ns(1, &ns9360_clockevent_device); - - ns9360_clockevent_device.cpumask = cpumask_of(0); - clockevents_register_device(&ns9360_clockevent_device); - - setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT, - &ns9360_clockevent_action); -} - -struct sys_timer ns9360_timer = { - .init = ns9360_timer_init, -}; diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h index 73082cd61e8..381cb9baadd 100644 --- a/arch/arm/mach-nuc93x/include/mach/uncompress.h +++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h @@ -27,7 +27,7 @@ #define arch_decomp_wdog() #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) -static u32 * uart_base = (u32 *)UART0_PA; +static u32 * const uart_base = (u32 *)UART0_PA; static void putc(int ch) { diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c index 1f8a05a2283..aa279f23e34 100644 --- a/arch/arm/mach-nuc93x/irq.c +++ b/arch/arm/mach-nuc93x/irq.c @@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void) __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { - set_irq_chip(irqno, &nuc93x_irq_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &nuc93x_irq_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S index 927d5a18176..c1c5fb6a5b4 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -79,7 +79,7 @@ /* - * Register useage + * Register usage * r8 - temporary * r9 - the driver buffer * r10 - temporary diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7c5e2112c77..e68dfde1918 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -276,7 +276,7 @@ static void __init osk_init_cf(void) return; } /* the CF I/O IRQ is really active-low */ - set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); } static void __init osk_init_irq(void) @@ -482,7 +482,7 @@ static void __init osk_mistral_init(void) omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ gpio_request(4, "ts_int"); gpio_direction_input(4); - set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); spi_register_board_info(mistral_boardinfo, ARRAY_SIZE(mistral_boardinfo)); @@ -500,7 +500,7 @@ static void __init osk_mistral_init(void) int irq = gpio_to_irq(OMAP_MPUIO(2)); gpio_direction_input(OMAP_MPUIO(2)); - set_irq_type(irq, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_PM /* share the IRQ in case someone wants to use the * button for more than wakeup from system sleep. diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index d7bbbe721a7..45f01d2c3a7 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id) { if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { printk(KERN_INFO "PM: Power cable connected\n"); - set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), + IRQ_TYPE_EDGE_FALLING); } else { printk(KERN_INFO "PM: Power cable disconnected\n"); - set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), + IRQ_TYPE_EDGE_RISING); } return IRQ_HANDLED; } diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index d41fe2d0616..0ad781db4e6 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -399,7 +399,7 @@ static void __init omap_sx1_init(void) sx1_mmc_init(); /* turn on USB power */ - /* sx1_setusbpower(1); cant do it here because i2c is not ready */ + /* sx1_setusbpower(1); can't do it here because i2c is not ready */ gpio_request(1, "A_IRDA_OFF"); gpio_request(11, "A_SWITCH"); gpio_request(15, "A_USB_ON"); diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index bdc0ac8dc21..65d24204937 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -279,10 +279,10 @@ static void __init voiceblue_init(void) gpio_request(13, "16C554 irq"); gpio_request(14, "16C554 irq"); gpio_request(15, "16C554 irq"); - set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); omap_board_config = voiceblue_config; diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index b0f4c231595..36f26c3fa25 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -281,7 +281,7 @@ static inline void omap_init_audio(void) {} * Claiming GPIOs, and setting their direction and initial values, is the * responsibility of the device drivers. So is responding to probe(). * - * Board-specific knowlege like creating devices or pin setup is to be + * Board-specific knowledge like creating devices or pin setup is to be * kept out of drivers as much as possible. In particular, pin setup * may be handled by the boot loader, and drivers should expect it will * normally have been done by the time they're probed. diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index acd16166640..1749cb37dda 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c @@ -13,7 +13,7 @@ #include <plat/tc.h> #include <plat/flash.h> -void omap1_set_vpp(struct map_info *map, int enable) +void omap1_set_vpp(struct platform_device *pdev, int enable) { static int count; u32 l; diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0ace7998aaa..cddbf8b089c 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void) * The touchscreen interrupt is level-sensitive, so * we'll use the regular mask_ack routine for it. */ - set_irq_chip(i, &omap_fpga_irq_ack); + irq_set_chip(i, &omap_fpga_irq_ack); } else { /* * All FPGA interrupts except the touchscreen are * edge-sensitive, so we won't mask them. */ - set_irq_chip(i, &omap_fpga_irq); + irq_set_chip(i, &omap_fpga_irq); } - set_irq_handler(i, handle_edge_irq); + irq_set_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } @@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void) return; } gpio_direction_input(13); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); + irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); } diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h index 7a2df29400c..23eed0035ed 100644 --- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h @@ -31,7 +31,7 @@ #endif /* - * These are the offsets from the begining of the fiq_buffer. They are put here + * These are the offsets from the beginning of the fiq_buffer. They are put here * since the buffer and header need to be accessed by drivers servicing devices * which generate GPIO interrupts - e.g. keyboard, modem, hook switch. */ diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 731dd33bff5..5d3da7a63af 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -230,8 +230,8 @@ void __init omap_init_irq(void) irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); - set_irq_chip(j, &omap_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_chip_and_handler(j, &omap_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } } diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 6588c22b8a6..fe31d933f0e 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -24,75 +24,50 @@ #ifdef CONFIG_PM_RUNTIME static int omap1_pm_runtime_suspend(struct device *dev) { - struct clk *iclk, *fclk; - int ret = 0; + int ret; dev_dbg(dev, "%s\n", __func__); ret = pm_generic_runtime_suspend(dev); + if (ret) + return ret; - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_disable(fclk); - clk_put(fclk); - } - - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_disable(iclk); - clk_put(iclk); + ret = pm_runtime_clk_suspend(dev); + if (ret) { + pm_generic_runtime_resume(dev); + return ret; } return 0; -}; +} static int omap1_pm_runtime_resume(struct device *dev) { - struct clk *iclk, *fclk; - dev_dbg(dev, "%s\n", __func__); - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_enable(iclk); - clk_put(iclk); - } + pm_runtime_clk_resume(dev); + return pm_generic_runtime_resume(dev); +} - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_enable(fclk); - clk_put(fclk); - } +static struct dev_power_domain default_power_domain = { + .ops = { + .runtime_suspend = omap1_pm_runtime_suspend, + .runtime_resume = omap1_pm_runtime_resume, + USE_PLATFORM_PM_SLEEP_OPS + }, +}; - return pm_generic_runtime_resume(dev); +static struct pm_clk_notifier_block platform_bus_notifier = { + .pwr_domain = &default_power_domain, + .con_ids = { "ick", "fck", NULL, }, }; static int __init omap1_pm_runtime_init(void) { - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - if (!cpu_class_is_omap1()) return -ENODEV; - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap1_pm_runtime_suspend; - omap_pm->runtime_resume = omap1_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); + pm_runtime_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); return 0; } diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 6885d2fac18..03e1e1062ad 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -68,49 +68,50 @@ typedef struct { } omap_mpu_timer_regs_t; #define omap_mpu_timer_base(n) \ -((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ +((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ (n)*OMAP_MPU_TIMER_OFFSET)) static inline unsigned long notrace omap_mpu_timer_read(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); - return timer->read_tim; + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); + return readl(&timer->read_tim); } static inline void omap_mpu_set_autoreset(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); - timer->cntl = timer->cntl | MPU_TIMER_AR; + writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); } static inline void omap_mpu_remove_autoreset(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); - timer->cntl = timer->cntl & ~MPU_TIMER_AR; + writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); } static inline void omap_mpu_timer_start(int nr, unsigned long load_val, int autoreset) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); - unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); + unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST; - if (autoreset) timerflags |= MPU_TIMER_AR; + if (autoreset) + timerflags |= MPU_TIMER_AR; - timer->cntl = MPU_TIMER_CLOCK_ENABLE; + writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); udelay(1); - timer->load_tim = load_val; + writel(load_val, &timer->load_tim); udelay(1); - timer->cntl = timerflags; + writel(timerflags, &timer->cntl); } static inline void omap_mpu_timer_stop(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); - timer->cntl &= ~MPU_TIMER_ST; + writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); } /* @@ -189,38 +190,11 @@ static __init void omap_init_mpu_timer(unsigned long rate) * --------------------------------------------------------------------------- */ -static unsigned long omap_mpu_timer2_overflows; - -static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id) -{ - omap_mpu_timer2_overflows++; - return IRQ_HANDLED; -} - -static struct irqaction omap_mpu_timer2_irq = { - .name = "mpu_timer2", - .flags = IRQF_DISABLED, - .handler = omap_mpu_timer2_interrupt, -}; - -static cycle_t mpu_read(struct clocksource *cs) -{ - return ~omap_mpu_timer_read(1); -} - -static struct clocksource clocksource_mpu = { - .name = "mpu_timer2", - .rating = 300, - .read = mpu_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static DEFINE_CLOCK_DATA(cd); static inline unsigned long long notrace _omap_mpu_sched_clock(void) { - u32 cyc = mpu_read(&clocksource_mpu); + u32 cyc = ~omap_mpu_timer_read(1); return cyc_to_sched_clock(&cd, cyc, (u32)~0); } @@ -238,21 +212,22 @@ static unsigned long long notrace omap_mpu_sched_clock(void) static void notrace mpu_update_sched_clock(void) { - u32 cyc = mpu_read(&clocksource_mpu); + u32 cyc = ~omap_mpu_timer_read(1); update_sched_clock(&cd, cyc, (u32)~0); } static void __init omap_init_clocksource(unsigned long rate) { + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1); static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; - setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); omap_mpu_timer_start(1, ~0, 1); init_sched_clock(&cd, mpu_update_sched_clock, 32, rate); - if (clocksource_register_hz(&clocksource_mpu, rate)) - printk(err, clocksource_mpu.name); + if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, + 300, 32, clocksource_mmio_readl_down)) + printk(err, "mpu_timer2"); } static void __init omap_mpu_timer_init(void) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a45cd640968..66dfbccacd2 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -59,16 +59,16 @@ endif # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \ - cpuidle34xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o + cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 -AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a +AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) ifeq ($(CONFIG_PM_VERBOSE),y) CFLAGS_pm_bus.o += -DDEBUG diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 5f8a2fd0633..34cf982b967 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -696,7 +696,7 @@ static void __init igep2_init(void) igep2_init_smsc911x(); /* - * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * WLAN-BT combo module from MuRata which has a Marvell WLAN * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. */ igep2_wlan_bt_init(); diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index b10db0e6ee6..2cf86c3cb1a 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -440,7 +440,7 @@ static void __init igep3_init(void) igep3_leds_init(); /* - * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * WLAN-BT combo module from MuRata which has a Marvell WLAN * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. */ igep3_wifi_bt_init(); diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index e964895b80e..f8ba20a14e6 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -141,14 +141,19 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { omap2_set_globals_3xxx(); - rx51_video_mem_init(); omap34xx_map_common_io(); } +static void __init rx51_reserve(void) +{ + rx51_video_mem_init(); + omap_reserve(); +} + MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ .boot_params = 0x80000100, - .reserve = omap_reserve, + .reserve = rx51_reserve, .map_io = rx51_map_io, .init_early = rx51_init_early, .init_irq = omap_init_irq, diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index b2b1e37bb6b..d6e34dd9e7e 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); + clk->rate = rate; return 0; } diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 276992d3b7f..8c965671b4d 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3116,14 +3116,9 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), - CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X), CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), - CLK("omapdss_dss", "fck", &dss_fck, CK_443X), - /* - * On OMAP4, DSS ick is a dummy clock; this is needed for compatibility - * with OMAP2/3. - */ - CLK("omapdss_dss", "ick", &dummy_ck, CK_443X), + CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index ab878545bd9..6cb6c03293d 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -258,7 +258,7 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm, * clkdm_init - set up the clockdomain layer * @clkdms: optional pointer to an array of clockdomains to register * @init_autodeps: optional pointer to an array of autodeps to register - * @custom_funcs: func pointers for arch specfic implementations + * @custom_funcs: func pointers for arch specific implementations * * Set up internal state. If a pointer to an array of clockdomains * @clkdms was supplied, loop through the list of clockdomains, diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 85b3dce6564..5823584d9cd 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -125,7 +125,7 @@ struct clockdomain { }; /** - * struct clkdm_ops - Arch specfic function implementations + * struct clkdm_ops - Arch specific function implementations * @clkdm_add_wkdep: Add a wakeup dependency between clk domains * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains * @clkdm_read_wkdep: Read wakeup dependency state between clk domains diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 9d0dec806e9..38830d8d478 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -247,6 +247,7 @@ struct omap3_cm_regs { u32 per_cm_clksel; u32 emu_cm_clksel; u32 emu_cm_clkstctrl; + u32 pll_cm_autoidle; u32 pll_cm_autoidle2; u32 pll_cm_clksel4; u32 pll_cm_clksel5; @@ -319,6 +320,15 @@ void omap3_cm_save_context(void) omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); cm_context.emu_cm_clkstctrl = omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. + * In this case, even though this register has been saved in + * scratchpad contents, we need to restore AUTO_PERIPH_DPLL + * by ourselves. So, we need to save it anyway. + */ + cm_context.pll_cm_autoidle = + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); cm_context.pll_cm_autoidle2 = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); cm_context.pll_cm_clksel4 = @@ -441,6 +451,13 @@ void omap3_cm_restore_context(void) CM_CLKSEL1); omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. + * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves. + */ + omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, + CM_AUTOIDLE); omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, CM_AUTOIDLE2); omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 69527941902..da53ba3917c 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -316,8 +316,14 @@ void omap3_save_scratchpad_contents(void) omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); prcm_block_contents.cm_clken_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + /* + * As per erratum i671, ROM code does not respect the PER DPLL + * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. + * Then, in anycase, clear these bits to avoid extra latencies. + */ prcm_block_contents.cm_autoidle_pll = - omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & + ~OMAP3430_AUTO_PERIPH_DPLL_MASK; prcm_block_contents.cm_clksel1_pll = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll = diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index c2804c1c4ef..a016c8b59e0 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -236,7 +236,7 @@ #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) -/* 36xx-only RTA - Retention till Accesss control registers and bits */ +/* 36xx-only RTA - Retention till Access control registers and bits */ #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C #define OMAP36XX_RTA_DISABLE 0x0 diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index a44c5230340..1c240eff391 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -297,8 +297,8 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); /** * omap3_cpuidle_update_states() - Update the cpuidle states - * @mpu_deepest_state: Enable states upto and including this for mpu domain - * @core_deepest_state: Enable states upto and including this for core domain + * @mpu_deepest_state: Enable states up to and including this for mpu domain + * @core_deepest_state: Enable states up to and including this for core domain * * This goes through the list of states available and enables and disables the * validity of C states based on deepest state that can be achieved for the diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 84d1b735fe8..7b855856459 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -253,7 +253,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data ARRAY_SIZE(omap_keyboard_latency), 0); if (IS_ERR(od)) { - WARN(1, "Cant build omap_device for %s:%s.\n", + WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); return PTR_ERR(od); } @@ -373,7 +373,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) od = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata), omap_mcspi_latency, ARRAY_SIZE(omap_mcspi_latency), 0); - WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", + WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n", name, oh->name); kfree(pdata); return 0; @@ -725,7 +725,7 @@ static int __init omap_init_wdt(void) od = omap_device_build(dev_name, id, oh, NULL, 0, omap_wdt_latency, ARRAY_SIZE(omap_wdt_latency), 0); - WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", + WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n", dev_name, oh->name); return 0; } diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 34922b2d2e3..c9ff0e79703 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -262,7 +262,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); kfree(p); if (IS_ERR(od)) { - pr_err("%s: Cant build omap_device for %s:%s.\n", + pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); return PTR_ERR(od); } diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 413de18c1d2..9529842ae05 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -82,7 +82,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) kfree(pdata); if (IS_ERR(od)) { - WARN(1, "Cant build omap_device for %s:%s.\n", + WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); return PTR_ERR(od); } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 493505c3b2f..130034bf01d 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -743,7 +743,7 @@ static int __init gpmc_init(void) /* initalize the irq_chained */ irq = OMAP_GPMC_IRQ_BASE; for (cs = 0; cs < GPMC_CS_NUM; cs++) { - set_irq_chip_and_handler(irq, &dummy_irq_chip, + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); irq++; diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 137e1a5f3d8..b2f30bed5a2 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -465,7 +465,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); if (IS_ERR(od)) { - WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name); + WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); kfree(mmc_data->slots[0].name); goto done; } diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index de441c05a6a..e4bd8761973 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr; extern void __init gic_init_irq(void); extern void omap_smc1(u32 fn, u32 arg); +#ifdef CONFIG_SMP +/* Needed for secondary core boot */ +extern void omap_secondary_startup(void); +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); +extern void omap_auxcoreboot_addr(u32 cpu_addr); +extern u32 omap_read_auxcoreboot0(void); +#endif #endif diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bc524b94fd5..3af2b7a1045 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -73,83 +73,18 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) return __raw_readl(bank->base_reg + reg); } -static int previous_irq; - -/* - * On 34xx we can get occasional spurious interrupts if the ack from - * an interrupt handler does not get posted before we unmask. Warn about - * the interrupt handlers that need to flush posted writes. - */ -static int omap_check_spurious(unsigned int irq) -{ - u32 sir, spurious; - - sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); - spurious = sir >> 7; - - if (spurious) { - printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " - "posted write for irq %i\n", - irq, sir, previous_irq); - return spurious; - } - - return 0; -} - /* XXX: FIQ and additional INTC support (only MPU at the moment) */ static void omap_ack_irq(struct irq_data *d) { intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); } -static void omap_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - - if (cpu_is_omap34xx() && !cpu_is_ti816x()) { - int spurious = 0; - - /* - * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because - * it is the highest irq number? - */ - if (irq == INT_34XX_GPT12_IRQ) - spurious = omap_check_spurious(irq); - - if (!spurious) - previous_irq = irq; - } - - irq &= (IRQ_BITS_PER_REG - 1); - - intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); -} - -static void omap_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq; - int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - - irq &= (IRQ_BITS_PER_REG - 1); - - intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset); -} - static void omap_mask_ack_irq(struct irq_data *d) { - omap_mask_irq(d); + irq_gc_mask_disable_reg(d); omap_ack_irq(d); } -static struct irq_chip omap_irq_chip = { - .name = "INTC", - .irq_ack = omap_mask_ack_irq, - .irq_mask = omap_mask_irq, - .irq_unmask = omap_unmask_irq, -}; - static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) { unsigned long tmp; @@ -186,11 +121,31 @@ int omap_irq_pending(void) return 0; } +static __init void +omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = omap_mask_ack_irq; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + + ct->regs.ack = INTC_CONTROL; + ct->regs.enable = INTC_MIR_CLEAR0; + ct->regs.disable = INTC_MIR_SET0; + irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); +} + void __init omap_init_irq(void) { unsigned long nr_of_irqs = 0; unsigned int nr_banks = 0; - int i; + int i, j; for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { unsigned long base = 0; @@ -215,18 +170,15 @@ void __init omap_init_irq(void) omap_irq_bank_init_one(bank); + for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20) + omap_alloc_gc(bank->base_reg + j, i, 32); + nr_of_irqs += bank->nr_irqs; nr_banks++; } printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); - - for (i = 0; i < nr_of_irqs; i++) { - set_irq_chip(i, &omap_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } } #ifdef CONFIG_ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 565b9064a32..4a6ef6ab845 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -149,7 +149,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) ARRAY_SIZE(omap2_mcbsp_latency), false); kfree(pdata); if (IS_ERR(od)) { - pr_err("%s: Cant build omap_device for %s:%s.\n", __func__, + pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, name, oh->name); return PTR_ERR(od); } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index bb043cbb388..a4ab1e36431 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -518,7 +518,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) seq_printf(s, "/* %s */\n", m->muxnames[mode]); /* - * XXX: Might be revisited to support differences accross + * XXX: Might be revisited to support differences across * same OMAP generation. */ seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def); diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h index adbea0d03e0..9fd93149ebd 100644 --- a/arch/arm/mach-omap2/mux2430.h +++ b/arch/arm/mach-omap2/mux2430.h @@ -22,7 +22,7 @@ * absolute addresses. The name in the macro is the mode-0 name of * the pin. NOTE: These registers are 8-bits wide. * - * Note that these defines use SDMMC instead of MMC for compability + * Note that these defines use SDMMC instead of MMC for compatibility * with signal names used in 3630. */ #define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index b66cfe8bc46..ecfe93c4b58 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -21,6 +21,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <mach/hardware.h> #include <mach/omap4-common.h> @@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); /* * Now the secondary core is starting up let it run its @@ -118,6 +119,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 8eb3ce1bbfb..c4d0ae87d62 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1639,6 +1639,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { static struct omap_hwmod omap2420_gpio1_hwmod = { .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), .main_clk = "gpios_fck", @@ -1669,6 +1670,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { static struct omap_hwmod omap2420_gpio2_hwmod = { .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), .main_clk = "gpios_fck", @@ -1699,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { static struct omap_hwmod omap2420_gpio3_hwmod = { .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), .main_clk = "gpios_fck", @@ -1729,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { static struct omap_hwmod omap2420_gpio4_hwmod = { .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap242x_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), .main_clk = "gpios_fck", @@ -1782,7 +1786,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { { .pa_start = 0x48056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x48056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index a860fb5024c..9682dd519f8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1559,7 +1559,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { * I2CHS IP's do not follow the usual pattern. * prcm_reg_id alone cannot be used to program * the iclk and fclk. Needs to be handled using - * additonal flags when clk handling is moved + * additional flags when clk handling is moved * to hwmod framework. */ .module_offs = CORE_MOD, @@ -1742,6 +1742,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { static struct omap_hwmod omap2430_gpio1_hwmod = { .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), .main_clk = "gpios_fck", @@ -1772,6 +1773,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { static struct omap_hwmod omap2430_gpio2_hwmod = { .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), .main_clk = "gpios_fck", @@ -1802,6 +1804,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { static struct omap_hwmod omap2430_gpio3_hwmod = { .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), .main_clk = "gpios_fck", @@ -1832,6 +1835,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { static struct omap_hwmod omap2430_gpio4_hwmod = { .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), .main_clk = "gpios_fck", @@ -1862,6 +1866,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { static struct omap_hwmod omap2430_gpio5_hwmod = { .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap243x_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), .main_clk = "gpio5_fck", @@ -1915,7 +1920,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { { .pa_start = 0x48056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x48056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b98e2dfcba2..909a84de668 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2141,6 +2141,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { static struct omap_hwmod omap3xxx_gpio1_hwmod = { .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), .main_clk = "gpio1_ick", @@ -2177,6 +2178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { static struct omap_hwmod omap3xxx_gpio2_hwmod = { .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), .main_clk = "gpio2_ick", @@ -2213,6 +2215,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { static struct omap_hwmod omap3xxx_gpio3_hwmod = { .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), .main_clk = "gpio3_ick", @@ -2249,6 +2252,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { static struct omap_hwmod omap3xxx_gpio4_hwmod = { .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), .main_clk = "gpio4_ick", @@ -2285,6 +2289,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { static struct omap_hwmod omap3xxx_gpio5_hwmod = { .name = "gpio5", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), .main_clk = "gpio5_ick", @@ -2321,6 +2326,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { static struct omap_hwmod omap3xxx_gpio6_hwmod = { .name = "gpio6", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap3xxx_gpio6_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), .main_clk = "gpio6_ick", @@ -2386,7 +2392,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { { .pa_start = 0x48056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x48056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 3e88dd3f8ef..abc548a0c98 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -885,7 +885,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { { .pa_start = 0x4a056000, - .pa_end = 0x4a0560ff, + .pa_end = 0x4a056fff, .flags = ADDR_TYPE_RT }, }; diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c index 5f2da7565b6..4321e793892 100644 --- a/arch/arm/mach-omap2/omap_l3_smx.c +++ b/arch/arm/mach-omap2/omap_l3_smx.c @@ -196,11 +196,11 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) /* No timeout error for debug sources */ } - base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source))); - /* identify the error source */ for (err_source = 0; !(status & (1 << err_source)); err_source++) ; + + base = l3->rt + *(omap3_l3_bases[int_type] + err_source); error = omap3_l3_readll(base, L3_ERROR_LOG); if (error) { diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index e2e605fe913..05f6abc96b0 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -112,12 +112,12 @@ int omap4430_phy_power(struct device *dev, int ID, int on) else /* * Enable VBUS Valid, AValid and IDDIG - * high impedence + * high impedance */ __raw_writel(IDDIG | AVALID | VBUSVALID, ctrl_base + USBOTGHS_CONTROL); } else { - /* Enable session END and IDIG to high impedence. */ + /* Enable session END and IDIG to high impedance. */ __raw_writel(SESSEND | IDDIG, ctrl_base + USBOTGHS_CONTROL); } diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 0a8e74e3e81..07d6140baa9 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -308,7 +308,7 @@ int __init omap3_twl_init(void) * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, * in those scenarios this bit is to be cleared (enable = false). * - * Returns 0 on sucess, error is returned if I2C read/write fails. + * Returns 0 on success, error is returned if I2C read/write fails. */ int __init omap3_twl_set_sr_bit(bool enable) { diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 30af3351c2d..49486f522dc 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -89,6 +89,7 @@ static void omap2_init_processor_devices(void) if (cpu_is_omap44xx()) { _init_omap_device("l3_main_1", &l3_dev); _init_omap_device("dsp", &dsp_dev); + _init_omap_device("iva", &iva_dev); } else { _init_omap_device("l3_main", &l3_dev); } diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c deleted file mode 100644 index 5acd2ab298b..00000000000 --- a/arch/arm/mach-omap2/pm_bus.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Runtime PM support code for OMAP - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/pm_runtime.h> -#include <linux/platform_device.h> -#include <linux/mutex.h> - -#include <plat/omap_device.h> -#include <plat/omap-pm.h> - -#ifdef CONFIG_PM_RUNTIME -static int omap_pm_runtime_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r, ret = 0; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - - if (!ret && dev->parent == &omap_device_parent) { - r = omap_device_idle(pdev); - WARN_ON(r); - } - - return ret; -}; - -static int omap_pm_runtime_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r; - - dev_dbg(dev, "%s\n", __func__); - - if (dev->parent == &omap_device_parent) { - r = omap_device_enable(pdev); - WARN_ON(r); - } - - return pm_generic_runtime_resume(dev); -}; -#else -#define omap_pm_runtime_suspend NULL -#define omap_pm_runtime_resume NULL -#endif /* CONFIG_PM_RUNTIME */ - -static int __init omap_pm_runtime_init(void) -{ - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap_pm_runtime_suspend; - omap_pm->runtime_resume = omap_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); - - return 0; -} -core_initcall(omap_pm_runtime_init); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 49c6513e90d..9af08473bf1 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -196,7 +196,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) /** * pwrdm_init - set up the powerdomain layer * @pwrdm_list: array of struct powerdomain pointers to register - * @custom_funcs: func pointers for arch specfic implementations + * @custom_funcs: func pointers for arch specific implementations * * Loop through the array of powerdomains @pwrdm_list, registering all * that are available on the current CPU. If pwrdm_list is supplied diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 027f40bd235..d23d979b9c3 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -121,7 +121,7 @@ struct powerdomain { }; /** - * struct pwrdm_ops - Arch specfic function implementations + * struct pwrdm_ops - Arch specific function implementations * @pwrdm_set_next_pwrst: Set the target power state for a pd * @pwrdm_read_next_pwrst: Read the target power state set for a pd * @pwrdm_read_pwrst: Read the current power state of a pd diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 9c9c113788b..469a920a74d 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -72,7 +72,7 @@ static struct powerdomain mpu_3xxx_pwrdm = { /* * The USBTLL Save-and-Restore mechanism is broken on - * 3430s upto ES3.0 and 3630ES1.0. Hence this feature + * 3430s up to ES3.0 and 3630ES1.0. Hence this feature * needs to be disabled on these chips. * Refer: 3430 errata ID i459 and 3630 errata ID i579 * diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 8f674c9442b..13e24f913dd 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -247,7 +247,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr) * driver register and sr device intializtion API's. Only one call * will ultimately succeed. * - * Currenly this function registers interrrupt handler for a particular SR + * Currently this function registers interrrupt handler for a particular SR * if smartreflex class driver is already registered and has * requested for interrupts and the SR interrupt line in present. */ diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index c6facf7becf..0c1552d9d99 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -114,7 +114,6 @@ static int __init _config_common_vdd_data(struct omap_vdd_info *vdd) sys_clk_speed /= 1000; /* Generic voltage parameters */ - vdd->curr_volt = 1200000; vdd->volt_scale = vp_forceupdate_scale_voltage; vdd->vp_enabled = false; @@ -851,7 +850,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm, * @voltdm: pointer to the VDD whose voltage is to be reset. * * This API finds out the correct voltage the voltage domain is supposed - * to be at and resets the voltage to that level. Should be used expecially + * to be at and resets the voltage to that level. Should be used especially * while disabling any voltage compensation modules. */ void omap_voltage_reset(struct voltagedomain *voltdm) @@ -912,7 +911,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm, * This API searches only through the non-compensated voltages int the * voltage table. * Returns pointer to the voltage table entry corresponding to volt on - * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage + * success. Returns -ENODATA if no voltage table exisits for the passed voltage * domain or if there is no matching entry. */ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 1a5d6a0e260..5ceafdccc45 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -19,7 +19,7 @@ #include "common.h" /* - * The Orion has fully programable address map. There's a separate address + * The Orion has fully programmable address map. There's a separate address * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own * address decode windows that allow it to access any of the Orion resources. diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 986c3bf4e6b..0ab531d047f 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -13,12 +13,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/dma-mapping.h> #include <linux/serial_8250.h> #include <linux/mbus.h> -#include <linux/mv643xx_eth.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> -#include <linux/spi/orion_spi.h> #include <net/dsa.h> #include <asm/page.h> #include <asm/setup.h> @@ -29,11 +28,9 @@ #include <mach/bridge-regs.h> #include <mach/hardware.h> #include <mach/orion5x.h> -#include <plat/ehci-orion.h> -#include <plat/mv_xor.h> #include <plat/orion_nand.h> -#include <plat/orion_wdt.h> #include <plat/time.h> +#include <plat/common.h> #include "common.h" /***************************************************************************** @@ -70,530 +67,124 @@ void __init orion5x_map_io(void) /***************************************************************************** - * EHCI - ****************************************************************************/ -static struct orion_ehci_data orion5x_ehci_data = { - .dram = &orion5x_mbus_dram_info, - .phy_version = EHCI_PHY_ORION, -}; - -static u64 ehci_dmamask = 0xffffffffUL; - - -/***************************************************************************** * EHCI0 ****************************************************************************/ -static struct resource orion5x_ehci0_resources[] = { - { - .start = ORION5X_USB0_PHYS_BASE, - .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_USB0_CTRL, - .end = IRQ_ORION5X_USB0_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_ehci0 = { - .name = "orion-ehci", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &orion5x_ehci_data, - }, - .resource = orion5x_ehci0_resources, - .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), -}; - void __init orion5x_ehci0_init(void) { - platform_device_register(&orion5x_ehci0); + orion_ehci_init(&orion5x_mbus_dram_info, + ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); } /***************************************************************************** * EHCI1 ****************************************************************************/ -static struct resource orion5x_ehci1_resources[] = { - { - .start = ORION5X_USB1_PHYS_BASE, - .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_USB1_CTRL, - .end = IRQ_ORION5X_USB1_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_ehci1 = { - .name = "orion-ehci", - .id = 1, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &orion5x_ehci_data, - }, - .resource = orion5x_ehci1_resources, - .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), -}; - void __init orion5x_ehci1_init(void) { - platform_device_register(&orion5x_ehci1); + orion_ehci_1_init(&orion5x_mbus_dram_info, + ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); } /***************************************************************************** - * GigE + * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { - .dram = &orion5x_mbus_dram_info, -}; - -static struct resource orion5x_eth_shared_resources[] = { - { - .start = ORION5X_ETH_PHYS_BASE + 0x2000, - .end = ORION5X_ETH_PHYS_BASE + 0x3fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_ETH_ERR, - .end = IRQ_ORION5X_ETH_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_eth_shared = { - .name = MV643XX_ETH_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &orion5x_eth_shared_data, - }, - .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources), - .resource = orion5x_eth_shared_resources, -}; - -static struct resource orion5x_eth_resources[] = { - { - .name = "eth irq", - .start = IRQ_ORION5X_ETH_SUM, - .end = IRQ_ORION5X_ETH_SUM, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_eth = { - .name = MV643XX_ETH_NAME, - .id = 0, - .num_resources = 1, - .resource = orion5x_eth_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; - void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - eth_data->shared = &orion5x_eth_shared; - orion5x_eth.dev.platform_data = eth_data; - - platform_device_register(&orion5x_eth_shared); - platform_device_register(&orion5x_eth); + orion_ge00_init(eth_data, &orion5x_mbus_dram_info, + ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, + IRQ_ORION5X_ETH_ERR, orion5x_tclk); } /***************************************************************************** * Ethernet switch ****************************************************************************/ -static struct resource orion5x_switch_resources[] = { - { - .start = 0, - .end = 0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_switch_device = { - .name = "dsa", - .id = 0, - .num_resources = 0, - .resource = orion5x_switch_resources, -}; - void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) { - int i; - - if (irq != NO_IRQ) { - orion5x_switch_resources[0].start = irq; - orion5x_switch_resources[0].end = irq; - orion5x_switch_device.num_resources = 1; - } - - d->netdev = &orion5x_eth.dev; - for (i = 0; i < d->nr_chips; i++) - d->chip[i].mii_bus = &orion5x_eth_shared.dev; - orion5x_switch_device.dev.platform_data = d; - - platform_device_register(&orion5x_switch_device); + orion_ge00_switch_init(d, irq); } /***************************************************************************** * I2C ****************************************************************************/ -static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { - .freq_m = 8, /* assumes 166 MHz TCLK */ - .freq_n = 3, - .timeout = 1000, /* Default timeout of 1 second */ -}; - -static struct resource orion5x_i2c_resources[] = { - { - .start = I2C_PHYS_BASE, - .end = I2C_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_I2C, - .end = IRQ_ORION5X_I2C, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_i2c = { - .name = MV64XXX_I2C_CTLR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion5x_i2c_resources), - .resource = orion5x_i2c_resources, - .dev = { - .platform_data = &orion5x_i2c_pdata, - }, -}; - void __init orion5x_i2c_init(void) { - platform_device_register(&orion5x_i2c); + orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); + } /***************************************************************************** * SATA ****************************************************************************/ -static struct resource orion5x_sata_resources[] = { - { - .name = "sata base", - .start = ORION5X_SATA_PHYS_BASE, - .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_ORION5X_SATA, - .end = IRQ_ORION5X_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_sata = { - .name = "sata_mv", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(orion5x_sata_resources), - .resource = orion5x_sata_resources, -}; - void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &orion5x_mbus_dram_info; - orion5x_sata.dev.platform_data = sata_data; - platform_device_register(&orion5x_sata); + orion_sata_init(sata_data, &orion5x_mbus_dram_info, + ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); } /***************************************************************************** * SPI ****************************************************************************/ -static struct orion_spi_info orion5x_spi_plat_data = { - .tclk = 0, - .enable_clock_fix = 1, -}; - -static struct resource orion5x_spi_resources[] = { - { - .name = "spi base", - .start = SPI_PHYS_BASE, - .end = SPI_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device orion5x_spi = { - .name = "orion_spi", - .id = 0, - .dev = { - .platform_data = &orion5x_spi_plat_data, - }, - .num_resources = ARRAY_SIZE(orion5x_spi_resources), - .resource = orion5x_spi_resources, -}; - void __init orion5x_spi_init() { - platform_device_register(&orion5x_spi); + orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); } /***************************************************************************** * UART0 ****************************************************************************/ -static struct plat_serial8250_port orion5x_uart0_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION5X_UART0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource orion5x_uart0_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_UART0, - .end = IRQ_ORION5X_UART0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_uart0 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = orion5x_uart0_data, - }, - .resource = orion5x_uart0_resources, - .num_resources = ARRAY_SIZE(orion5x_uart0_resources), -}; - void __init orion5x_uart0_init(void) { - platform_device_register(&orion5x_uart0); + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + IRQ_ORION5X_UART0, orion5x_tclk); } - /***************************************************************************** * UART1 ****************************************************************************/ -static struct plat_serial8250_port orion5x_uart1_data[] = { - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION5X_UART1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 0, - }, { - }, -}; - -static struct resource orion5x_uart1_resources[] = { - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_ORION5X_UART1, - .end = IRQ_ORION5X_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_uart1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = orion5x_uart1_data, - }, - .resource = orion5x_uart1_resources, - .num_resources = ARRAY_SIZE(orion5x_uart1_resources), -}; - void __init orion5x_uart1_init(void) { - platform_device_register(&orion5x_uart1); + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + IRQ_ORION5X_UART1, orion5x_tclk); } - /***************************************************************************** * XOR engine ****************************************************************************/ -struct mv_xor_platform_shared_data orion5x_xor_shared_data = { - .dram = &orion5x_mbus_dram_info, -}; - -static struct resource orion5x_xor_shared_resources[] = { - { - .name = "xor low", - .start = ORION5X_XOR_PHYS_BASE, - .end = ORION5X_XOR_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .name = "xor high", - .start = ORION5X_XOR_PHYS_BASE + 0x200, - .end = ORION5X_XOR_PHYS_BASE + 0x2ff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device orion5x_xor_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .dev = { - .platform_data = &orion5x_xor_shared_data, - }, - .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), - .resource = orion5x_xor_shared_resources, -}; - -static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32); - -static struct resource orion5x_xor0_resources[] = { - [0] = { - .start = IRQ_ORION5X_XOR0, - .end = IRQ_ORION5X_XOR0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data orion5x_xor0_data = { - .shared = &orion5x_xor_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device orion5x_xor0_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion5x_xor0_resources), - .resource = orion5x_xor0_resources, - .dev = { - .dma_mask = &orion5x_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion5x_xor0_data, - }, -}; - -static struct resource orion5x_xor1_resources[] = { - [0] = { - .start = IRQ_ORION5X_XOR1, - .end = IRQ_ORION5X_XOR1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data orion5x_xor1_data = { - .shared = &orion5x_xor_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, -}; - -static struct platform_device orion5x_xor1_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(orion5x_xor1_resources), - .resource = orion5x_xor1_resources, - .dev = { - .dma_mask = &orion5x_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion5x_xor1_data, - }, -}; - void __init orion5x_xor_init(void) { - platform_device_register(&orion5x_xor_shared); - - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask); - dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask); - platform_device_register(&orion5x_xor0_channel); - - dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask); - dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask); - dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask); - platform_device_register(&orion5x_xor1_channel); + orion_xor0_init(&orion5x_mbus_dram_info, + ORION5X_XOR_PHYS_BASE, + ORION5X_XOR_PHYS_BASE + 0x200, + IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } -static struct resource orion5x_crypto_res[] = { - { - .name = "regs", - .start = ORION5X_CRYPTO_PHYS_BASE, - .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .name = "sram", - .start = ORION5X_SRAM_PHYS_BASE, - .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "crypto interrupt", - .start = IRQ_ORION5X_CESA, - .end = IRQ_ORION5X_CESA, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device orion5x_crypto_device = { - .name = "mv_crypto", - .id = -1, - .num_resources = ARRAY_SIZE(orion5x_crypto_res), - .resource = orion5x_crypto_res, -}; - -static int __init orion5x_crypto_init(void) +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +static void __init orion5x_crypto_init(void) { int ret; ret = orion5x_setup_sram_win(); if (ret) - return ret; + return; - return platform_device_register(&orion5x_crypto_device); + orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, + SZ_8K, IRQ_ORION5X_CESA); } /***************************************************************************** * Watchdog ****************************************************************************/ -static struct orion_wdt_platform_data orion5x_wdt_data = { - .tclk = 0, -}; - -static struct platform_device orion5x_wdt_device = { - .name = "orion_wdt", - .id = -1, - .dev = { - .platform_data = &orion5x_wdt_data, - }, - .num_resources = 0, -}; - void __init orion5x_wdt_init(void) { - orion5x_wdt_data.tclk = orion5x_tclk; - platform_device_register(&orion5x_wdt_device); + orion_wdt_init(orion5x_tclk); } @@ -685,11 +276,6 @@ void __init orion5x_init(void) orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); - orion5x_eth_shared_data.t_clk = orion5x_tclk; - orion5x_spi_plat_data.tclk = orion5x_tclk; - orion5x_uart0_data[0].uartclk = orion5x_tclk; - orion5x_uart1_data[0].uartclk = orion5x_tclk; - /* * Setup Orion address map */ diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 42580757930..19cf5bf99f1 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = { * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Board ID (bit 0) */ - { 1, MPP_GPIO }, /* Board ID (bit 1) */ - { 2, MPP_GPIO }, /* Board ID (bit 2) */ - { 3, MPP_GPIO }, /* SATA 0 power */ - { 4, MPP_UNUSED }, - { 5, MPP_GPIO }, /* Fan fail detection */ - { 6, MPP_GPIO }, /* Red front LED */ - { 7, MPP_UNUSED }, - { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ - { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_GPIO }, /* SATA 1 power */ - { 13, MPP_UNUSED }, - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_GPIO }, /* Blue front LED blink control */ - { 17, MPP_UNUSED }, - { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ - { 19, MPP_UNUSED }, - { -1 } +static unsigned int d2net_mpp_modes[] __initdata = { + MPP0_GPIO, /* Board ID (bit 0) */ + MPP1_GPIO, /* Board ID (bit 1) */ + MPP2_GPIO, /* Board ID (bit 2) */ + MPP3_GPIO, /* SATA 0 power */ + MPP4_UNUSED, + MPP5_GPIO, /* Fan fail detection */ + MPP6_GPIO, /* Red front LED */ + MPP7_UNUSED, + MPP8_GPIO, /* Rear power switch (on|auto) */ + MPP9_GPIO, /* Rear power switch (auto|off) */ + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_GPIO, /* SATA 1 power */ + MPP13_UNUSED, + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_GPIO, /* Blue front LED blink control */ + MPP17_UNUSED, + MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */ + MPP19_UNUSED, + 0, /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ /* 23: Blue front LED off */ /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index c10a1171537..f95d3cb01cb 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) pin = DB88F5281_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "db88f5281_pci_preinit faield " "to set_irq_type pin %d\n", pin); @@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* USB Over Current */ - { 1, MPP_GPIO }, /* USB Vbat input */ - { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ - { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ - { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ - { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ - { 6, MPP_GPIO }, /* JP0, CON17.2 */ - { 7, MPP_GPIO }, /* JP1, CON17.1 */ - { 8, MPP_GPIO }, /* JP2, CON11.2 */ - { 9, MPP_GPIO }, /* JP3, CON11.3 */ - { 10, MPP_GPIO }, /* RTC int */ - { 11, MPP_GPIO }, /* Baud Rate Generator */ - { 12, MPP_GPIO }, /* PCI int 1 */ - { 13, MPP_GPIO }, /* PCI int 2 */ - { 14, MPP_NAND }, /* NAND_REn[2] */ - { 15, MPP_NAND }, /* NAND_WEn[2] */ - { 16, MPP_UART }, /* UART1_RX */ - { 17, MPP_UART }, /* UART1_TX */ - { 18, MPP_UART }, /* UART1_CTSn */ - { 19, MPP_UART }, /* UART1_RTSn */ - { -1 }, +static unsigned int db88f5281_mpp_modes[] __initdata = { + MPP0_GPIO, /* USB Over Current */ + MPP1_GPIO, /* USB Vbat input */ + MPP2_PCI_ARB, /* PCI_REQn[2] */ + MPP3_PCI_ARB, /* PCI_GNTn[2] */ + MPP4_PCI_ARB, /* PCI_REQn[3] */ + MPP5_PCI_ARB, /* PCI_GNTn[3] */ + MPP6_GPIO, /* JP0, CON17.2 */ + MPP7_GPIO, /* JP1, CON17.1 */ + MPP8_GPIO, /* JP2, CON11.2 */ + MPP9_GPIO, /* JP3, CON11.3 */ + MPP10_GPIO, /* RTC int */ + MPP11_GPIO, /* Baud Rate Generator */ + MPP12_GPIO, /* PCI int 1 */ + MPP13_GPIO, /* PCI int 2 */ + MPP14_NAND, /* NAND_REn[2] */ + MPP15_NAND, /* NAND_WEn[2] */ + MPP16_UART, /* UART1_RX */ + MPP17_UART, /* UART1_TX */ + MPP18_UART, /* UART1_CTSn */ + MPP19_UART, /* UART1_RTSn */ + 0, }; static void __init db88f5281_init(void) diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 90ab022eabe..855e0e77d56 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = { /**************************************************************************** * General Setup */ -static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = { - { 0, MPP_PCIE_RST_OUTn }, - { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ - { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ - { 3, MPP_UNUSED }, - { 4, MPP_GPIO }, /* power button LED */ - { 5, MPP_GPIO }, /* power button LED */ - { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ - { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ - { 8, MPP_GPIO }, /* triggers power off */ - { 9, MPP_GPIO }, /* power button switch */ - { 10, MPP_GPIO }, /* reset button switch */ - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_UNUSED }, - { 15, MPP_UNUSED }, - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int dns323a_mpp_modes[] __initdata = { + MPP0_PCIE_RST_OUTn, + MPP1_GPIO, /* right amber LED (sata ch0) */ + MPP2_GPIO, /* left amber LED (sata ch1) */ + MPP3_UNUSED, + MPP4_GPIO, /* power button LED */ + MPP5_GPIO, /* power button LED */ + MPP6_GPIO, /* GMT G751-2f overtemp */ + MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ + MPP8_GPIO, /* triggers power off */ + MPP9_GPIO, /* power button switch */ + MPP10_GPIO, /* reset button switch */ + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_UNUSED, + MPP15_UNUSED, + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; -static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ - { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ - { 3, MPP_GPIO }, /* system up flag */ - { 4, MPP_GPIO }, /* power button LED */ - { 5, MPP_GPIO }, /* power button LED */ - { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ - { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ - { 8, MPP_GPIO }, /* triggers power off */ - { 9, MPP_GPIO }, /* power button switch */ - { 10, MPP_GPIO }, /* reset button switch */ - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, - { 13, MPP_SATA_LED }, - { 14, MPP_SATA_LED }, - { 15, MPP_SATA_LED }, - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int dns323b_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_GPIO, /* right amber LED (sata ch0) */ + MPP2_GPIO, /* left amber LED (sata ch1) */ + MPP3_GPIO, /* system up flag */ + MPP4_GPIO, /* power button LED */ + MPP5_GPIO, /* power button LED */ + MPP6_GPIO, /* GMT G751-2f overtemp */ + MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */ + MPP8_GPIO, /* triggers power off */ + MPP9_GPIO, /* power button switch */ + MPP10_GPIO, /* reset button switch */ + MPP11_UNUSED, + MPP12_SATA_LED, + MPP13_SATA_LED, + MPP14_SATA_LED, + MPP15_SATA_LED, + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; -static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* ? input */ - { 1, MPP_GPIO }, /* input power switch (0 = pressed) */ - { 2, MPP_GPIO }, /* output power off */ - { 3, MPP_UNUSED }, /* ? output */ - { 4, MPP_UNUSED }, /* ? output */ - { 5, MPP_UNUSED }, /* ? output */ - { 6, MPP_UNUSED }, /* ? output */ - { 7, MPP_UNUSED }, /* ? output */ - { 8, MPP_GPIO }, /* i/o right amber LED */ - { 9, MPP_GPIO }, /* i/o left amber LED */ - { 10, MPP_GPIO }, /* input */ - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, - { 13, MPP_SATA_LED }, - { 14, MPP_SATA_LED }, - { 15, MPP_SATA_LED }, - { 16, MPP_UNUSED }, - { 17, MPP_GPIO }, /* power button LED */ - { 18, MPP_GPIO }, /* fan speed bit 0 */ - { 19, MPP_GPIO }, /* fan speed bit 1 */ - { -1 }, +static unsigned int dns323c_mpp_modes[] __initdata = { + MPP0_GPIO, /* ? input */ + MPP1_GPIO, /* input power switch (0 = pressed) */ + MPP2_GPIO, /* output power off */ + MPP3_UNUSED, /* ? output */ + MPP4_UNUSED, /* ? output */ + MPP5_UNUSED, /* ? output */ + MPP6_UNUSED, /* ? output */ + MPP7_UNUSED, /* ? output */ + MPP8_GPIO, /* i/o right amber LED */ + MPP9_GPIO, /* i/o left amber LED */ + MPP10_GPIO, /* input */ + MPP11_UNUSED, + MPP12_SATA_LED, + MPP13_SATA_LED, + MPP14_SATA_LED, + MPP15_SATA_LED, + MPP16_UNUSED, + MPP17_GPIO, /* power button LED */ + MPP18_GPIO, /* fan speed bit 0 */ + MPP19_GPIO, /* fan speed bit 1 */ + 0, }; /* Rev C1 Fan speed notes: diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index d037a90c216..b67cff0d4cf 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_UNUSED }, - { 2, MPP_UNUSED }, - { 3, MPP_GPIO }, /* RTC interrupt */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_UNUSED }, - { 7, MPP_UNUSED }, - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ +static unsigned int edminiv2_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_UNUSED, + MPP2_UNUSED, + MPP3_GPIO, /* RTC interrupt */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_UNUSED, + MPP7_UNUSED, + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ /* 16: Power LED control (0 = On, 1 = Off) */ - { 16, MPP_GPIO }, + MPP16_GPIO, /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ - { 17, MPP_GPIO }, + MPP17_GPIO, /* 18: Power button status (0 = Released, 1 = Pressed) */ - { 18, MPP_GPIO }, - { 19, MPP_UNUSED }, - { -1 } + MPP18_GPIO, + MPP19_UNUSED, + 0, }; static void __init edmini_v2_init(void) diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ed85891f869..43cf8bc9767 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -34,8 +34,8 @@ void __init orion5x_init_irq(void) * Initialize gpiolib for GPIOs 0-31. */ orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); - set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); + irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 47497c76162..c0eb6462633 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void) /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_UNUSED }, - { 2, MPP_GPIO }, /* GPIO Micon */ - { 3, MPP_GPIO }, /* GPIO Rtc */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_NAND }, /* NAND Flash REn */ - { 7, MPP_NAND }, /* NAND Flash WEn */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_UART }, /* UART1 CTSn */ - { 19, MPP_UART }, /* UART1 RTSn */ - { -1 }, +static unsigned int kurobox_pro_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_UNUSED, + MPP2_GPIO, /* GPIO Micon */ + MPP3_GPIO, /* GPIO Rtc */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_NAND, /* NAND Flash REn */ + MPP7_NAND, /* NAND Flash WEn */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_UART, /* UART1 CTSn */ + MPP19_UART, /* UART1 RTSn */ + 0, }; static void __init kurobox_pro_init(void) diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 6ae12aa6d75..5065803ca82 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = { * GPIO Data ****************************************************************************/ -static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED POWER */ - { 1, MPP_GPIO }, /* HDD POWER */ - { 2, MPP_GPIO }, /* LED ALARM */ - { 3, MPP_GPIO }, /* LED INFO */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_GPIO }, /* FAN LOCK */ - { 7, MPP_GPIO }, /* SW INIT */ - { 8, MPP_GPIO }, /* SW POWER */ - { 9, MPP_GPIO }, /* USB POWER */ - { 10, MPP_GPIO }, /* SW AUTO POWER */ - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* FAN HIGH */ - { 15, MPP_GPIO }, /* SW FUNC */ - { 16, MPP_GPIO }, /* FAN LOW */ - { 17, MPP_GPIO }, /* LED FUNC */ - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int lschl_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED POWER */ + MPP1_GPIO, /* HDD POWER */ + MPP2_GPIO, /* LED ALARM */ + MPP3_GPIO, /* LED INFO */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_GPIO, /* FAN LOCK */ + MPP7_GPIO, /* SW INIT */ + MPP8_GPIO, /* SW POWER */ + MPP9_GPIO, /* USB POWER */ + MPP10_GPIO, /* SW AUTO POWER */ + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_GPIO, /* FAN HIGH */ + MPP15_GPIO, /* SW FUNC */ + MPP16_GPIO, /* FAN LOW */ + MPP17_GPIO, /* LED FUNC */ + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init lschl_init(void) diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index 7adafd79cf9..8503d0a42d4 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -200,28 +200,28 @@ static void ls_hgl_power_off(void) #define LS_HGL_GPIO_HDD_POWER 1 -static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED_PWR */ - { 1, MPP_GPIO }, /* HDD_PWR */ - { 2, MPP_GPIO }, /* LED_ALARM */ - { 3, MPP_GPIO }, /* LED_INFO */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_GPIO }, /* FAN_LCK */ - { 7, MPP_GPIO }, /* INIT */ - { 8, MPP_GPIO }, /* POWER */ - { 9, MPP_GPIO }, /* USB_PWR */ - { 10, MPP_GPIO }, /* AUTO_POWER */ - { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_UNUSED }, - { 15, MPP_GPIO }, /* FUNC */ - { 16, MPP_UNUSED }, - { 17, MPP_GPIO }, /* LED_FUNC */ - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int ls_hgl_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED_PWR */ + MPP1_GPIO, /* HDD_PWR */ + MPP2_GPIO, /* LED_ALARM */ + MPP3_GPIO, /* LED_INFO */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_GPIO, /* FAN_LCK */ + MPP7_GPIO, /* INIT */ + MPP8_GPIO, /* POWER */ + MPP9_GPIO, /* USB_PWR */ + MPP10_GPIO, /* AUTO_POWER */ + MPP11_UNUSED, /* LED_ETH (dummy) */ + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_UNUSED, + MPP15_GPIO, /* FUNC */ + MPP16_UNUSED, + MPP17_GPIO, /* LED_FUNC */ + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init ls_hgl_init(void) diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index 869958f5c39..9c82723c05c 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -201,28 +201,28 @@ static void lsmini_power_off(void) #define LSMINI_GPIO_HDD_POWER0 1 #define LSMINI_GPIO_HDD_POWER1 19 -static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */ - { 1, MPP_GPIO }, /* HDD_PWR */ - { 2, MPP_GPIO }, /* LED_ALARM */ - { 3, MPP_GPIO }, /* LED_INFO */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_UNUSED }, - { 7, MPP_UNUSED }, - { 8, MPP_UNUSED }, - { 9, MPP_GPIO }, /* LED_FUNC */ - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* LED_PWR */ - { 15, MPP_GPIO }, /* FUNC */ - { 16, MPP_GPIO }, /* USB_PWR */ - { 17, MPP_GPIO }, /* AUTO_POWER */ - { 18, MPP_GPIO }, /* POWER */ - { 19, MPP_GPIO }, /* HDD_PWR1 */ - { -1 }, +static unsigned int lsmini_mpp_modes[] __initdata = { + MPP0_UNUSED, /* LED_RESERVE1 (unused) */ + MPP1_GPIO, /* HDD_PWR */ + MPP2_GPIO, /* LED_ALARM */ + MPP3_GPIO, /* LED_INFO */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_UNUSED, + MPP7_UNUSED, + MPP8_UNUSED, + MPP9_GPIO, /* LED_FUNC */ + MPP10_UNUSED, + MPP11_UNUSED, /* LED_ETH (dummy) */ + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_GPIO, /* LED_PWR */ + MPP15_GPIO, /* FUNC */ + MPP16_GPIO, /* USB_PWR */ + MPP17_GPIO, /* AUTO_POWER */ + MPP18_GPIO, /* POWER */ + MPP19_GPIO, /* HDD_PWR1 */ + 0, }; static void __init lsmini_init(void) diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 2288207726e..f12c41b98d4 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -12,154 +12,34 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> -#include <asm/gpio.h> #include <mach/hardware.h> -#include "common.h" +#include <plat/mpp.h> #include "mpp.h" +#include "common.h" -static int is_5181l(void) -{ - u32 dev; - u32 rev; - - orion5x_pcie_id(&dev, &rev); - - return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0); -} - -static int is_5182(void) +static unsigned int __init orion5x_variant(void) { u32 dev; u32 rev; orion5x_pcie_id(&dev, &rev); - return !!(dev == MV88F5182_DEV_ID); -} + if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) + return MPP_F5181_MASK; -static int is_5281(void) -{ - u32 dev; - u32 rev; + if (dev == MV88F5182_DEV_ID) + return MPP_F5182_MASK; - orion5x_pcie_id(&dev, &rev); + if (dev == MV88F5281_DEV_ID) + return MPP_F5281_MASK; - return !!(dev == MV88F5281_DEV_ID); + printk(KERN_ERR "MPP setup: unknown orion5x variant " + "(dev %#x rev %#x)\n", dev, rev); + return 0; } -static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type) +void __init orion5x_mpp_conf(unsigned int *mpp_list) { - switch (type) { - case MPP_UNUSED: - case MPP_GPIO: - if (mpp == 0) - return 3; - if (mpp >= 1 && mpp <= 15) - return 0; - if (mpp >= 16 && mpp <= 19) { - if (is_5182()) - return 5; - if (type == MPP_UNUSED) - return 0; - } - return -1; - - case MPP_PCIE_RST_OUTn: - if (mpp == 0) - return 0; - return -1; - - case MPP_PCI_ARB: - if (mpp >= 0 && mpp <= 7) - return 2; - return -1; - - case MPP_PCI_PMEn: - if (mpp == 2) - return 3; - return -1; - - case MPP_GIGE: - if (mpp >= 8 && mpp <= 19) - return 1; - return -1; - - case MPP_NAND: - if (is_5182() || is_5281()) { - if (mpp >= 4 && mpp <= 7) - return 4; - if (mpp >= 12 && mpp <= 17) - return 4; - } - return -1; - - case MPP_PCI_CLK: - if (is_5181l() && mpp >= 6 && mpp <= 7) - return 5; - return -1; - - case MPP_SATA_LED: - if (is_5182()) { - if (mpp >= 4 && mpp <= 7) - return 5; - if (mpp >= 12 && mpp <= 15) - return 5; - } - return -1; - - case MPP_UART: - if (mpp >= 16 && mpp <= 19) - return 0; - return -1; - } - - printk(KERN_INFO "unknown MPP type %d\n", type); - - return -1; -} - -void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) -{ - u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL); - u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); - u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); - - for ( ; mode->mpp >= 0; mode++) { - u32 *reg; - int num_type; - int shift; - - if (mode->mpp >= 0 && mode->mpp <= 7) - reg = &mpp_0_7_ctrl; - else if (mode->mpp >= 8 && mode->mpp <= 15) - reg = &mpp_8_15_ctrl; - else if (mode->mpp >= 16 && mode->mpp <= 19) - reg = &mpp_16_19_ctrl; - else { - printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " - "(%d)\n", mode->mpp); - continue; - } - - num_type = determine_type_encoding(mode->mpp, mode->type); - if (num_type < 0) { - printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " - "combination (%d, %d)\n", mode->mpp, - mode->type); - continue; - } - - shift = (mode->mpp & 7) << 2; - *reg &= ~(0xf << shift); - *reg |= (num_type & 0xf) << shift; - - if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182())) - orion_gpio_set_unused(mode->mpp); - - orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); - } - - writel(mpp_0_7_ctrl, MPP_0_7_CTRL); - writel(mpp_8_15_ctrl, MPP_8_15_CTRL); - writel(mpp_16_19_ctrl, MPP_16_19_CTRL); + orion_mpp_conf(mpp_list, orion5x_variant(), + MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h index 290e610dc01..eac68978a2c 100644 --- a/arch/arm/mach-orion5x/mpp.h +++ b/arch/arm/mach-orion5x/mpp.h @@ -1,74 +1,129 @@ #ifndef __ARCH_ORION5X_MPP_H #define __ARCH_ORION5X_MPP_H -enum orion5x_mpp_type { - /* - * This MPP is unused. - */ - MPP_UNUSED, - - /* - * This MPP pin is used as a generic GPIO pin. Valid for - * MPPs 0-15 and device bus data pins 16-31. On 5182, also - * valid for MPPs 16-19. - */ - MPP_GPIO, - - /* - * This MPP is used as PCIe_RST_OUTn pin. Valid for - * MPP 0 only. - */ - MPP_PCIE_RST_OUTn, - - /* - * This MPP is used as PCI arbiter pin (REQn/GNTn). - * Valid for MPPs 0-7 only. - */ - MPP_PCI_ARB, - - /* - * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only. - */ - MPP_PCI_PMEn, - - /* - * This MPP is used as GigE half-duplex (COL, CRS) or GMII - * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for - * MPPs 8-19 only. - */ - MPP_GIGE, - - /* - * This MPP is used as NAND REn/WEn pin. Valid for MPPs - * 4-7 and 12-17 only, and only on the 5181l/5182/5281. - */ - MPP_NAND, - - /* - * This MPP is used as a PCI clock output pin. Valid for - * MPPs 6-7 only, and only on the 5181l. - */ - MPP_PCI_CLK, - - /* - * This MPP is used as a SATA presence/activity LED. - * Valid for MPPs 4-7 and 12-15 only, and only on the 5182. - */ - MPP_SATA_LED, - - /* - * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin. - * Valid for MPPs 16-19 only. - */ - MPP_UART, -}; - -struct orion5x_mpp_mode { - int mpp; - enum orion5x_mpp_type type; -}; - -void orion5x_mpp_conf(struct orion5x_mpp_mode *mode); +#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on F5181l */ ((!!(_F5181l)) << 14) | \ + /* available on F5182 */ ((!!(_F5182)) << 15) | \ + /* available on F5281 */ ((!!(_F5281)) << 16)) + /* num sel i o 5181 5182 5281 */ + +#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0) +#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0) +#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1) + +#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1) +#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1) +#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1) +#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1) + +#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1) +#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1) +#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1) + +#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1) +#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1) +#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1) +#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1) + +#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1) +#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1) +#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1) + +#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1) +#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1) +#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1) +#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1) +#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0) + +#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1) +#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1) +#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1) +#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1) +#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0) + +#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1) +#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1) +#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1) +#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1) +#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0) +#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0) + +#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1) +#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1) +#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1) +#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1) +#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0) +#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0) + +#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1) +#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1) +#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1) + +#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1) +#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1) +#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1) + +#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1) +#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1) +#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1) + +#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1) +#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1) +#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1) + +#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1) +#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1) +#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1) +#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1) +#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0) + +#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1) +#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1) +#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1) +#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1) +#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0) + +#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1) +#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1) +#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1) +#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1) +#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0) + +#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1) +#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1) +#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1) +#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1) +#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0) + +#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1) +#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0) +#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1) +#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1) +#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1) + +#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1) +#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0) +#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1) +#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1) +#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1) + +#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1) +#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0) +#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1) +#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1) + +#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1) +#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0) +#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1) +#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1) + +#define MPP_MAX 19 + +void orion5x_mpp_conf(unsigned int *mpp_list); #endif diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index b43b208153c..59263b73d1e 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -193,28 +193,28 @@ static void mss2_power_off(void) /**************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Power LED */ - { 1, MPP_GPIO }, /* Error LED */ - { 2, MPP_UNUSED }, - { 3, MPP_GPIO }, /* RTC interrupt */ - { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/ - { 5, MPP_GPIO }, /* HD0 5V control */ - { 6, MPP_GPIO }, /* HD0 12V control */ - { 7, MPP_GPIO }, /* HD1 5V control */ - { 8, MPP_GPIO }, /* HD1 12V control */ - { 9, MPP_UNUSED }, - { 10, MPP_GPIO }, /* Fan control */ - { 11, MPP_GPIO }, /* Power button */ - { 12, MPP_GPIO }, /* Reset button */ - { 13, MPP_UNUSED }, - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int mss2_mpp_modes[] __initdata = { + MPP0_GPIO, /* Power LED */ + MPP1_GPIO, /* Error LED */ + MPP2_UNUSED, + MPP3_GPIO, /* RTC interrupt */ + MPP4_GPIO, /* HDD ind. (Single/Dual)*/ + MPP5_GPIO, /* HD0 5V control */ + MPP6_GPIO, /* HD0 12V control */ + MPP7_GPIO, /* HD1 5V control */ + MPP8_GPIO, /* HD1 12V control */ + MPP9_UNUSED, + MPP10_GPIO, /* Fan control */ + MPP11_GPIO, /* Power button */ + MPP12_GPIO, /* Reset button */ + MPP13_UNUSED, + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init mss2_init(void) diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index c55d071707f..63ff10c3c46 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = { /**************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Sys status LED */ - { 1, MPP_GPIO }, /* Sys error LED */ - { 2, MPP_GPIO }, /* OverTemp interrupt */ - { 3, MPP_GPIO }, /* RTC interrupt */ - { 4, MPP_GPIO }, /* V_LED 5V */ - { 5, MPP_GPIO }, /* V_LED 3.3V */ - { 6, MPP_UNUSED }, - { 7, MPP_UNUSED }, - { 8, MPP_GPIO }, /* SATA 0 fail LED */ - { 9, MPP_GPIO }, /* SATA 1 fail LED */ - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UNUSED }, - { 17, MPP_GPIO }, /* Reset button */ - { 18, MPP_GPIO }, /* Power button */ - { 19, MPP_GPIO }, /* Power off */ - { -1 }, +static unsigned int mv2120_mpp_modes[] __initdata = { + MPP0_GPIO, /* Sys status LED */ + MPP1_GPIO, /* Sys error LED */ + MPP2_GPIO, /* OverTemp interrupt */ + MPP3_GPIO, /* RTC interrupt */ + MPP4_GPIO, /* V_LED 5V */ + MPP5_GPIO, /* V_LED 3.3V */ + MPP6_UNUSED, + MPP7_UNUSED, + MPP8_GPIO, /* SATA 0 fail LED */ + MPP9_GPIO, /* SATA 1 fail LED */ + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UNUSED, + MPP17_GPIO, /* Reset button */ + MPP18_GPIO, /* Power button */ + MPP19_GPIO, /* Power off */ + 0, }; static struct i2c_board_info __initdata mv2120_i2c_rtc = { diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 429ecafe9fd..e43b39cc7fe 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -190,7 +190,7 @@ err_free_1: * The power front LEDs (blue and red) and SATA red LEDs are controlled via a * single GPIO line and are compatible with the leds-gpio driver. * - * The SATA blue LEDs have some hardware blink capabilities which are detailled + * The SATA blue LEDs have some hardware blink capabilities which are detailed * in the following array: * * SATAx blue LED | SATAx activity | LED state @@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = { * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Raid mode (bit 0) */ - { 1, MPP_GPIO }, /* USB port 2 fuse (0 = Fail, 1 = Ok) */ - { 2, MPP_GPIO }, /* Raid mode (bit 1) */ - { 3, MPP_GPIO }, /* Board ID (bit 0) */ - { 4, MPP_GPIO }, /* Fan activity (0 = Off, 1 = On) */ - { 5, MPP_GPIO }, /* Fan fail detection */ - { 6, MPP_GPIO }, /* Red front LED (0 = Off, 1 = On) */ - { 7, MPP_GPIO }, /* Disable initial blinking on front LED */ - { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ - { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ - { 10, MPP_GPIO }, /* SATA 1 red LED (0 = Off, 1 = On) */ - { 11, MPP_GPIO }, /* SATA 0 red LED (0 = Off, 1 = On) */ - { 12, MPP_GPIO }, /* Board ID (bit 1) */ - { 13, MPP_GPIO }, /* SATA 1 blue LED blink control */ - { 14, MPP_SATA_LED }, - { 15, MPP_SATA_LED }, - { 16, MPP_GPIO }, /* Blue front LED control */ - { 17, MPP_GPIO }, /* SATA 0 blue LED blink control */ - { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ - { 19, MPP_GPIO }, /* SATA{0,1} power On/Off request */ - { -1 } +static unsigned int net2big_mpp_modes[] __initdata = { + MPP0_GPIO, /* Raid mode (bit 0) */ + MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */ + MPP2_GPIO, /* Raid mode (bit 1) */ + MPP3_GPIO, /* Board ID (bit 0) */ + MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */ + MPP5_GPIO, /* Fan fail detection */ + MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */ + MPP7_GPIO, /* Disable initial blinking on front LED */ + MPP8_GPIO, /* Rear power switch (on|auto) */ + MPP9_GPIO, /* Rear power switch (auto|off) */ + MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */ + MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */ + MPP12_GPIO, /* Board ID (bit 1) */ + MPP13_GPIO, /* SATA 1 blue LED blink control */ + MPP14_SATA_LED, + MPP15_SATA_LED, + MPP16_GPIO, /* Blue front LED control */ + MPP17_GPIO, /* SATA 0 blue LED blink control */ + MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */ + MPP19_GPIO, /* SATA{0,1} power On/Off request */ + 0, /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ /* 23: SATA 0 power status */ /* 24: Board power off */ diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 34310ab56e2..9eec7c2375e 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */ - { 1, MPP_GPIO }, /* PCI_intA */ - { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/ - { 3, MPP_GPIO }, /* FXS or DAA select */ - { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */ - { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */ - { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ - { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ - { 8, MPP_GPIO }, /* CardBus reset */ - { 9, MPP_GPIO }, /* GE_RXERR */ - { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */ - { 11, MPP_GPIO }, /* Lifeline control */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED1 CardBus LED (front panel) */ + MPP1_GPIO, /* PCI_intA */ + MPP2_GPIO, /* Hard Reset / Factory Init*/ + MPP3_GPIO, /* FXS or DAA select */ + MPP4_GPIO, /* LED6 - phone LED (front panel) */ + MPP5_GPIO, /* LED5 - phone LED (front panel) */ + MPP6_PCI_CLK, /* CPU PCI refclk */ + MPP7_PCI_CLK, /* PCI/PCIe refclk */ + MPP8_GPIO, /* CardBus reset */ + MPP9_GPIO, /* GE_RXERR */ + MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */ + MPP11_GPIO, /* Lifeline control */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index c1f79fa014e..0cc90bbfd32 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* LED1 */ - { 1, MPP_GPIO }, /* LED5 */ - { 2, MPP_GPIO }, /* LED4 */ - { 3, MPP_GPIO }, /* LED3 */ - { 4, MPP_GPIO }, /* PCI_intA */ - { 5, MPP_GPIO }, /* RTC interrupt */ - { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ - { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ - { 8, MPP_GPIO }, /* 88e6131 interrupt */ - { 9, MPP_GPIO }, /* GE_RXERR */ - { 10, MPP_GPIO }, /* PCI_intB */ - { 11, MPP_GPIO }, /* LED2 */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = { + MPP0_GPIO, /* LED1 */ + MPP1_GPIO, /* LED5 */ + MPP2_GPIO, /* LED4 */ + MPP3_GPIO, /* LED3 */ + MPP4_GPIO, /* PCI_intA */ + MPP5_GPIO, /* RTC interrupt */ + MPP6_PCI_CLK, /* CPU PCI refclk */ + MPP7_PCI_CLK, /* PCI/PCIe refclk */ + MPP8_GPIO, /* 88e6131 interrupt */ + MPP9_GPIO, /* GE_RXERR */ + MPP10_GPIO, /* PCI_intB */ + MPP11_GPIO, /* LED2 */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 67ec6959b26..48da39b9bdb 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; if (gpio_request(pin, "PCI IntA") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; if (gpio_request(pin, "PCI IntB") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "rd88f5182_pci_preinit faield to " "set_irq_type pin %d\n", pin); @@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Debug Led */ - { 1, MPP_GPIO }, /* Reset Switch */ - { 2, MPP_UNUSED }, - { 3, MPP_GPIO }, /* RTC Int */ - { 4, MPP_GPIO }, - { 5, MPP_GPIO }, - { 6, MPP_GPIO }, /* PCI_intA */ - { 7, MPP_GPIO }, /* PCI_intB */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UNUSED }, - { 17, MPP_UNUSED }, - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int rd88f5182_mpp_modes[] __initdata = { + MPP0_GPIO, /* Debug Led */ + MPP1_GPIO, /* Reset Switch */ + MPP2_UNUSED, + MPP3_GPIO, /* RTC Int */ + MPP4_GPIO, + MPP5_GPIO, + MPP6_GPIO, /* PCI_intA */ + MPP7_GPIO, /* PCI_intB */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UNUSED, + MPP17_UNUSED, + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init rd88f5182_init(void) diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index b080c6966d1..ad2eba9286a 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -27,7 +27,6 @@ #include <asm/mach/pci.h> #include <mach/orion5x.h> #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { .phy_addr = -1, diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 5653ee6c71d..29ce826c3c2 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void) pin = TSP2_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "tsp2_pci_preinit failed " "to set_irq_type pin %d\n", pin); @@ -295,28 +295,28 @@ static void tsp2_power_off(void) /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = { - { 0, MPP_PCIE_RST_OUTn }, - { 1, MPP_UNUSED }, - { 2, MPP_UNUSED }, - { 3, MPP_UNUSED }, - { 4, MPP_NAND }, /* BOOT NAND Flash REn */ - { 5, MPP_NAND }, /* BOOT NAND Flash WEn */ - { 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */ - { 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */ - { 8, MPP_GPIO }, /* MICON int */ - { 9, MPP_GPIO }, /* RTC int */ - { 10, MPP_UNUSED }, - { 11, MPP_GPIO }, /* PCI Int A */ - { 12, MPP_UNUSED }, - { 13, MPP_GPIO }, /* UPS on UART0 enable */ - { 14, MPP_GPIO }, /* UPS low battery detection */ - { 15, MPP_UNUSED }, - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_UART }, /* UART1 CTSn */ - { 19, MPP_UART }, /* UART1 RTSn */ - { -1 }, +static unsigned int tsp2_mpp_modes[] __initdata = { + MPP0_PCIE_RST_OUTn, + MPP1_UNUSED, + MPP2_UNUSED, + MPP3_UNUSED, + MPP4_NAND, /* BOOT NAND Flash REn */ + MPP5_NAND, /* BOOT NAND Flash WEn */ + MPP6_NAND, /* BOOT NAND Flash HREn[0] */ + MPP7_NAND, /* BOOT NAND Flash WEn[0] */ + MPP8_GPIO, /* MICON int */ + MPP9_GPIO, /* RTC int */ + MPP10_UNUSED, + MPP11_GPIO, /* PCI Int A */ + MPP12_UNUSED, + MPP13_GPIO, /* UPS on UART0 enable */ + MPP14_GPIO, /* UPS low battery detection */ + MPP15_UNUSED, + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_UART, /* UART1 CTSn */ + MPP19_UART, /* UART1 RTSn */ + 0, }; static void __init tsp2_init(void) diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 8bbd27ea673..47162fd5f04 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -36,7 +36,7 @@ /**************************************************************************** * 8MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with + * partitions on the device because we want to keep compatibility with * existing QNAP firmware. * * Layout as used by QNAP: @@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed to " "set_irq_type pin %d\n", pin); @@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_direction_input(pin) == 0) { - set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); } else { printk(KERN_ERR "qnap_ts209_pci_preinit failed " "to set_irq_type pin %d\n", pin); @@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = { * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_GPIO }, /* USB copy button */ - { 2, MPP_GPIO }, /* Load defaults button */ - { 3, MPP_GPIO }, /* GPIO RTC */ - { 4, MPP_UNUSED }, - { 5, MPP_UNUSED }, - { 6, MPP_GPIO }, /* PCI Int A */ - { 7, MPP_GPIO }, /* PCI Int B */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_SATA_LED }, /* SATA 0 presence */ - { 13, MPP_SATA_LED }, /* SATA 1 presence */ - { 14, MPP_SATA_LED }, /* SATA 0 active */ - { 15, MPP_SATA_LED }, /* SATA 1 active */ - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_GPIO }, /* SW_RST */ - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int ts209_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_GPIO, /* USB copy button */ + MPP2_GPIO, /* Load defaults button */ + MPP3_GPIO, /* GPIO RTC */ + MPP4_UNUSED, + MPP5_UNUSED, + MPP6_GPIO, /* PCI Int A */ + MPP7_GPIO, /* PCI Int B */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_SATA_LED, /* SATA 0 presence */ + MPP13_SATA_LED, /* SATA 1 presence */ + MPP14_SATA_LED, /* SATA 0 active */ + MPP15_SATA_LED, /* SATA 1 active */ + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_GPIO, /* SW_RST */ + MPP19_UNUSED, + 0, }; static void __init qnap_ts209_init(void) diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 92f393f08fa..5aacc7ac5cf 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -56,7 +56,7 @@ /**************************************************************************** * 8MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with + * partitions on the device because we want to keep compatibility with * existing QNAP firmware. * * Layout as used by QNAP: @@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = { /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_UNUSED }, - { 2, MPP_UNUSED }, - { 3, MPP_UNUSED }, - { 4, MPP_GPIO }, /* HDD 1 status */ - { 5, MPP_GPIO }, /* HDD 2 status */ - { 6, MPP_GPIO }, /* HDD 3 status */ - { 7, MPP_GPIO }, /* HDD 4 status */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_GPIO }, /* RTC int */ - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* SW_RST */ - { 15, MPP_GPIO }, /* USB copy button */ - { 16, MPP_UART }, /* UART1 RXD */ - { 17, MPP_UART }, /* UART1 TXD */ - { 18, MPP_UNUSED }, - { 19, MPP_UNUSED }, - { -1 }, +static unsigned int ts409_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_UNUSED, + MPP2_UNUSED, + MPP3_UNUSED, + MPP4_GPIO, /* HDD 1 status */ + MPP5_GPIO, /* HDD 2 status */ + MPP6_GPIO, /* HDD 3 status */ + MPP7_GPIO, /* HDD 4 status */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_GPIO, /* RTC int */ + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_GPIO, /* SW_RST */ + MPP15_GPIO, /* USB copy button */ + MPP16_UART, /* UART1 RXD */ + MPP17_UART, /* UART1 TXD */ + MPP18_UNUSED, + MPP19_UNUSED, + 0, }; static void __init qnap_ts409_init(void) diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 8554707d20a..6b7b54116f3 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -402,7 +402,7 @@ static void ts78xx_fpga_supports(void) /* enable devices if magic matches */ switch ((ts78xx_fpga.id >> 8) & 0xffffff) { case TS7800_FPGA_MAGIC: - printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n", + pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n", ts78xx_fpga.id & 0xff); ts78xx_fpga.supports.ts_rtc.present = 1; ts78xx_fpga.supports.ts_nand.present = 1; @@ -423,7 +423,7 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_rtc.present == 1) { tmp = ts78xx_ts_rtc_load(); if (tmp) { - printk(KERN_INFO "TS-78xx: RTC not registered\n"); + pr_info("TS-78xx: RTC not registered\n"); ts78xx_fpga.supports.ts_rtc.present = 0; } ret |= tmp; @@ -431,7 +431,7 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_nand.present == 1) { tmp = ts78xx_ts_nand_load(); if (tmp) { - printk(KERN_INFO "TS-78xx: NAND not registered\n"); + pr_info("TS-78xx: NAND not registered\n"); ts78xx_fpga.supports.ts_nand.present = 0; } ret |= tmp; @@ -439,7 +439,7 @@ static int ts78xx_fpga_load_devices(void) if (ts78xx_fpga.supports.ts_rng.present == 1) { tmp = ts78xx_ts_rng_load(); if (tmp) { - printk(KERN_INFO "TS-78xx: RNG not registered\n"); + pr_info("TS-78xx: RNG not registered\n"); ts78xx_fpga.supports.ts_rng.present = 0; } ret |= tmp; @@ -466,7 +466,7 @@ static int ts78xx_fpga_load(void) { ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); - printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", + pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff); @@ -494,7 +494,7 @@ static int ts78xx_fpga_unload(void) * UrJTAG SVN since r1381 can be used to reprogram the FPGA */ if (ts78xx_fpga.id != fpga_id) { - printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n" + pr_err("TS-78xx FPGA: magic/rev mismatch\n" "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); @@ -525,7 +525,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, int value, ret; if (ts78xx_fpga.state < 0) { - printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n"); + pr_err("TS-78xx FPGA: borked, you must powercycle asap\n"); return -EBUSY; } @@ -534,7 +534,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) value = 0; else { - printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n"); + pr_err("ts78xx_fpga_store: Invalid value\n"); return -EINVAL; } @@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr = /***************************************************************************** * General Setup ****************************************************************************/ -static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { - { 0, MPP_UNUSED }, - { 1, MPP_GPIO }, /* JTAG Clock */ - { 2, MPP_GPIO }, /* JTAG Data In */ - { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */ - { 4, MPP_GPIO }, /* JTAG Data Out */ - { 5, MPP_GPIO }, /* JTAG TMS */ - { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ - { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */ - { 8, MPP_UNUSED }, - { 9, MPP_UNUSED }, - { 10, MPP_UNUSED }, - { 11, MPP_UNUSED }, - { 12, MPP_UNUSED }, - { 13, MPP_UNUSED }, - { 14, MPP_UNUSED }, - { 15, MPP_UNUSED }, - { 16, MPP_UART }, - { 17, MPP_UART }, - { 18, MPP_UART }, - { 19, MPP_UART }, +static unsigned int ts78xx_mpp_modes[] __initdata = { + MPP0_UNUSED, + MPP1_GPIO, /* JTAG Clock */ + MPP2_GPIO, /* JTAG Data In */ + MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */ + MPP4_GPIO, /* JTAG Data Out */ + MPP5_GPIO, /* JTAG TMS */ + MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ + MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */ + MPP8_UNUSED, + MPP9_UNUSED, + MPP10_UNUSED, + MPP11_UNUSED, + MPP12_UNUSED, + MPP13_UNUSED, + MPP14_UNUSED, + MPP15_UNUSED, + MPP16_UART, + MPP17_UART, + MPP18_UART, + MPP19_UART, /* * MPP[20] PCI Clock Out 1 * MPP[21] PCI Clock Out 0 @@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { * MPP[24] Unused * MPP[25] Unused */ - { -1 }, + 0, }; static void __init ts78xx_init(void) @@ -616,7 +616,7 @@ static void __init ts78xx_init(void) ret = ts78xx_fpga_load(); ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); if (ret) - printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); + pr_err("sysfs_create_file failed: %d\n", ret); } MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 4e5216be074..444a1c7fdfd 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -24,28 +24,28 @@ #include "common.h" #include "mpp.h" -static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Power LED green (0=on) */ - { 1, MPP_GPIO }, /* Reset Button (0=off) */ - { 2, MPP_GPIO }, /* Power LED blink (0=off) */ - { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */ - { 4, MPP_GPIO }, /* PCI int */ - { 5, MPP_GPIO }, /* ??? */ - { 6, MPP_GPIO }, /* ??? */ - { 7, MPP_GPIO }, /* ??? */ - { 8, MPP_UNUSED }, /* ??? */ - { 9, MPP_GIGE }, /* GE_RXERR */ - { 10, MPP_UNUSED }, /* ??? */ - { 11, MPP_UNUSED }, /* ??? */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int wnr854t_mpp_modes[] __initdata = { + MPP0_GPIO, /* Power LED green (0=on) */ + MPP1_GPIO, /* Reset Button (0=off) */ + MPP2_GPIO, /* Power LED blink (0=off) */ + MPP3_GPIO, /* WAN Status LED amber (0=off) */ + MPP4_GPIO, /* PCI int */ + MPP5_GPIO, /* ??? */ + MPP6_GPIO, /* ??? */ + MPP7_GPIO, /* ??? */ + MPP8_UNUSED, /* ??? */ + MPP9_GIGE, /* GE_RXERR */ + MPP10_UNUSED, /* ??? */ + MPP11_UNUSED, /* ??? */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; /* diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index fab79d09cc5..d1952be0ae1 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = { /* * General setup */ -static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { - { 0, MPP_GPIO }, /* Power LED green (0=on) */ - { 1, MPP_GPIO }, /* Security LED (0=on) */ - { 2, MPP_GPIO }, /* Internal Button (0=on) */ - { 3, MPP_GPIO }, /* Reset Button (0=on) */ - { 4, MPP_GPIO }, /* PCI int */ - { 5, MPP_GPIO }, /* Power LED orange (0=on) */ - { 6, MPP_GPIO }, /* USB LED (0=on) */ - { 7, MPP_GPIO }, /* Wireless LED (0=on) */ - { 8, MPP_UNUSED }, /* ??? */ - { 9, MPP_GIGE }, /* GE_RXERR */ - { 10, MPP_UNUSED }, /* ??? */ - { 11, MPP_UNUSED }, /* ??? */ - { 12, MPP_GIGE }, /* GE_TXD[4] */ - { 13, MPP_GIGE }, /* GE_TXD[5] */ - { 14, MPP_GIGE }, /* GE_TXD[6] */ - { 15, MPP_GIGE }, /* GE_TXD[7] */ - { 16, MPP_GIGE }, /* GE_RXD[4] */ - { 17, MPP_GIGE }, /* GE_RXD[5] */ - { 18, MPP_GIGE }, /* GE_RXD[6] */ - { 19, MPP_GIGE }, /* GE_RXD[7] */ - { -1 }, +static unsigned int wrt350n_v2_mpp_modes[] __initdata = { + MPP0_GPIO, /* Power LED green (0=on) */ + MPP1_GPIO, /* Security LED (0=on) */ + MPP2_GPIO, /* Internal Button (0=on) */ + MPP3_GPIO, /* Reset Button (0=on) */ + MPP4_GPIO, /* PCI int */ + MPP5_GPIO, /* Power LED orange (0=on) */ + MPP6_GPIO, /* USB LED (0=on) */ + MPP7_GPIO, /* Wireless LED (0=on) */ + MPP8_UNUSED, /* ??? */ + MPP9_GIGE, /* GE_RXERR */ + MPP10_UNUSED, /* ??? */ + MPP11_UNUSED, /* ??? */ + MPP12_GIGE, /* GE_TXD[4] */ + MPP13_GIGE, /* GE_TXD[5] */ + MPP14_GIGE, /* GE_TXD[6] */ + MPP15_GIGE, /* GE_TXD[7] */ + MPP16_GIGE, /* GE_RXD[4] */ + MPP17_GIGE, /* GE_RXD[5] */ + MPP18_GIGE, /* GE_RXD[6] */ + MPP19_GIGE, /* GE_RXD[7] */ + 0, }; /* diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index c69c180aec7..7608c7a288c 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c @@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ - set_irq_handler(d->irq, handle_edge_irq); + irq_set_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_EDGE_FALLING: __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ - set_irq_handler(d->irq, handle_edge_irq); + irq_set_handler(d->irq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); break; case IRQ_TYPE_LEVEL_HIGH: __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ - set_irq_handler(d->irq, handle_level_irq); + irq_set_handler(d->irq, handle_level_irq); break; /* IRQ_TYPE_EDGE_BOTH is not supported */ @@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void) /* configure IRQ's */ for (i = 0; i < NR_IRQS; i++) { set_irq_flags(i, IRQF_VALID); - set_irq_chip(i, &pnx4008_irq_chip); + irq_set_chip(i, &pnx4008_irq_chip); pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); } diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 3499fada73a..4cb069fd9af 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -128,8 +128,8 @@ static int am200_init_gpio_regs(struct metronomefb_par *par) return 0; err_req_gpio: - while (i > 0) - gpio_free(gpios[i--]); + while (--i >= 0) + gpio_free(gpios[i]); return err; } @@ -194,7 +194,7 @@ static struct notifier_block am200_fb_notif = { }; /* this gets called as part of our init. these steps must be done now so - * that we can use set_pxa_fb_info */ + * that we can use pxa_set_fb_info */ static void __init am200_presetup_fb(void) { int fw; @@ -249,7 +249,7 @@ static void __init am200_presetup_fb(void) /* we divide since we told the LCD controller we're 16bpp */ am200_fb_info.modes->xres /= 2; - set_pxa_fb_info(&am200_fb_info); + pxa_set_fb_info(NULL, &am200_fb_info); } diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 993d75e6639..fa8bad235d9 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -125,10 +125,7 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par) if (err) { dev_err(&am300_device->dev, "failed requesting " "gpio %d, err=%d\n", i, err); - while (i >= DB0_GPIO_PIN) - gpio_free(i--); - i = ARRAY_SIZE(gpios) - 1; - goto err_req_gpio; + goto err_req_gpio2; } } @@ -159,9 +156,13 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par) return 0; +err_req_gpio2: + while (--i >= DB0_GPIO_PIN) + gpio_free(i); + i = ARRAY_SIZE(gpios); err_req_gpio: - while (i > 0) - gpio_free(gpios[i--]); + while (--i >= 0) + gpio_free(gpios[i]); return err; } diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index d2af73321da..810a982a66f 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> @@ -263,7 +262,7 @@ static void __init balloon3_lcd_init(void) } balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power; - set_pxa_fb_info(&balloon3_lcd_screen); + pxa_set_fb_info(NULL, &balloon3_lcd_screen); return; err2: @@ -527,13 +526,13 @@ static void __init balloon3_init_irq(void) pxa27x_init_irq(); /* setup extra Balloon3 irqs */ for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { - set_irq_chip(irq, &balloon3_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &balloon3_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); - set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); + irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); pr_debug("%s: chained handler installed - irq %d automatically " "enabled\n", __func__, BALLOON3_AUX_NIRQ); diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c index 1ce09044849..1d5859d9a0e 100644 --- a/arch/arm/mach-pxa/clock-pxa2xx.c +++ b/arch/arm/mach-pxa/clock-pxa2xx.c @@ -9,7 +9,7 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/pxa2xx-regs.h> @@ -33,32 +33,22 @@ const struct clkops clk_pxa2xx_cken_ops = { #ifdef CONFIG_PM static uint32_t saved_cken; -static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state) +static int pxa2xx_clock_suspend(void) { saved_cken = CKEN; return 0; } -static int pxa2xx_clock_resume(struct sys_device *d) +static void pxa2xx_clock_resume(void) { CKEN = saved_cken; - return 0; } #else #define pxa2xx_clock_suspend NULL #define pxa2xx_clock_resume NULL #endif -struct sysdev_class pxa2xx_clock_sysclass = { - .name = "pxa2xx-clock", +struct syscore_ops pxa2xx_clock_syscore_ops = { .suspend = pxa2xx_clock_suspend, .resume = pxa2xx_clock_resume, }; - -static int __init pxa2xx_clock_init(void) -{ - if (cpu_is_pxa2xx()) - return sysdev_class_register(&pxa2xx_clock_sysclass); - return 0; -} -postcore_initcall(pxa2xx_clock_init); diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 3f864cd0bd2..2a37a9a8f62 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/syscore_ops.h> #include <mach/smemc.h> #include <mach/pxa3xx-regs.h> @@ -182,7 +183,7 @@ const struct clkops clk_pxa3xx_pout_ops = { static uint32_t cken[2]; static uint32_t accr; -static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state) +static int pxa3xx_clock_suspend(void) { cken[0] = CKENA; cken[1] = CKENB; @@ -190,28 +191,18 @@ static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state) return 0; } -static int pxa3xx_clock_resume(struct sys_device *d) +static void pxa3xx_clock_resume(void) { ACCR = accr; CKENA = cken[0]; CKENB = cken[1]; - return 0; } #else #define pxa3xx_clock_suspend NULL #define pxa3xx_clock_resume NULL #endif -struct sysdev_class pxa3xx_clock_sysclass = { - .name = "pxa3xx-clock", +struct syscore_ops pxa3xx_clock_syscore_ops = { .suspend = pxa3xx_clock_suspend, .resume = pxa3xx_clock_resume, }; - -static int __init pxa3xx_clock_init(void) -{ - if (cpu_is_pxa3xx() || cpu_is_pxa95x()) - return sysdev_class_register(&pxa3xx_clock_sysclass); - return 0; -} -postcore_initcall(pxa3xx_clock_init); diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index f9f349a21b5..1f2fb9c43f0 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h @@ -1,5 +1,5 @@ #include <linux/clkdev.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> struct clkops { void (*enable)(struct clk *); @@ -54,7 +54,7 @@ extern const struct clkops clk_pxa2xx_cken_ops; void clk_pxa2xx_cken_enable(struct clk *clk); void clk_pxa2xx_cken_disable(struct clk *clk); -extern struct sysdev_class pxa2xx_clock_sysclass; +extern struct syscore_ops pxa2xx_clock_syscore_ops; #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ @@ -74,5 +74,6 @@ extern const struct clkops clk_pxa3xx_smemc_ops; extern void clk_pxa3xx_cken_enable(struct clk *); extern void clk_pxa3xx_cken_disable(struct clk *); -extern struct sysdev_class pxa3xx_clock_sysclass; +extern struct syscore_ops pxa3xx_clock_syscore_ops; + #endif diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index b88d601a809..13518a70539 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -10,7 +10,6 @@ */ #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/irq.h> #include <linux/gpio.h> #include <linux/delay.h> diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index a2380cd76f8..1afc0fb7d6d 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -29,33 +29,6 @@ unsigned long it8152_base_address; static int cmx2xx_it8152_irq_gpio; -/* - * Only first 64MB of memory can be accessed via PCI. - * We use GFP_DMA to allocate safe buffers to do map/unmap. - * This is really ugly and we need a better way of specifying - * DMA-capable regions of memory. - */ -void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size, - unsigned long *zhole_size) -{ - unsigned int sz = SZ_64M >> PAGE_SHIFT; - - if (machine_is_armcore()) { - pr_info("Adjusting zones for CM-X2XX\n"); - - /* - * Only adjust if > 64M on current system - */ - if (zone_size[0] <= sz) - return; - - zone_size[1] = zone_size[0] - sz; - zone_size[0] = sz; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; - } -} - static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) { /* clear our parent irq */ @@ -70,9 +43,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio) cmx2xx_it8152_irq_gpio = irq_gpio; - set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); + irq_set_chained_handler(gpio_to_irq(irq_gpio), + cmx2xx_it8152_irq_demux); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index b734d846816..a1099678247 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -10,7 +10,7 @@ */ #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/irq.h> #include <linux/gpio.h> @@ -379,7 +379,7 @@ __setup("monitor=", cmx2xx_set_display); static void __init cmx2xx_init_display(void) { - set_pxa_fb_info(cmx2xx_display); + pxa_set_fb_info(NULL, cmx2xx_display); } #else static inline void cmx2xx_init_display(void) {} @@ -388,7 +388,7 @@ static inline void cmx2xx_init_display(void) {} #ifdef CONFIG_PM static unsigned long sleep_save_msc[10]; -static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state) +static int cmx2xx_suspend(void) { cmx2xx_pci_suspend(); @@ -412,7 +412,7 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int cmx2xx_resume(struct sys_device *dev) +static void cmx2xx_resume(void) { cmx2xx_pci_resume(); @@ -420,27 +420,18 @@ static int cmx2xx_resume(struct sys_device *dev) __raw_writel(sleep_save_msc[0], MSC0); __raw_writel(sleep_save_msc[1], MSC1); __raw_writel(sleep_save_msc[2], MSC2); - - return 0; } -static struct sysdev_class cmx2xx_pm_sysclass = { - .name = "pm", +static struct syscore_ops cmx2xx_pm_syscore_ops = { .resume = cmx2xx_resume, .suspend = cmx2xx_suspend, }; -static struct sys_device cmx2xx_pm_device = { - .cls = &cmx2xx_pm_sysclass, -}; - static int __init cmx2xx_pm_init(void) { - int error; - error = sysdev_class_register(&cmx2xx_pm_sysclass); - if (error == 0) - error = sysdev_register(&cmx2xx_pm_device); - return error; + register_syscore_ops(&cmx2xx_pm_syscore_ops); + + return 0; } #else static int __init cmx2xx_pm_init(void) { return 0; } diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index bfca7ed2fea..b2248e76ec8 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -296,7 +296,7 @@ static struct pxafb_mach_info cm_x300_lcd = { static void __init cm_x300_init_lcd(void) { - set_pxa_fb_info(&cm_x300_lcd); + pxa_set_fb_info(NULL, &cm_x300_lcd); } #else static inline void cm_x300_init_lcd(void) {} @@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void) { pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); i2c_register_board_info(1, &cm_x300_pmic_info, 1); - set_irq_wake(IRQ_WAKEUP0, 1); + irq_set_irq_wake(IRQ_WAKEUP0, 1); } static void __init cm_x300_init_wi2wi(void) diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index 81c3c433e2d..d28e802e244 100644 --- a/arch/arm/mach-pxa/colibri-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c @@ -13,7 +13,6 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/gpio.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index ee797397dc5..80538b8806e 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -22,7 +22,6 @@ #include <linux/platform_device.h> #include <linux/pwm_backlight.h> #include <linux/i2c/pxa-i2c.h> -#include <linux/sysdev.h> #include <asm/irq.h> #include <asm/mach-types.h> @@ -175,7 +174,7 @@ static struct pxafb_mach_info income_lcd_screen = { static void __init income_lcd_init(void) { - set_pxa_fb_info(&income_lcd_screen); + pxa_set_fb_info(NULL, &income_lcd_screen); } #else static inline void income_lcd_init(void) {} diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 6fc5d328ba7..7545a48ed88 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -17,7 +17,6 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/ucb1400.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 96b2d9fbfef..3f9be419959 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -105,7 +105,7 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin) lcd_bl_pin = bl_pin; gpio_request(bl_pin, "lcd backlight"); gpio_direction_output(bl_pin, 0); - set_pxa_fb_info(&sharp_lq43_info); + pxa_set_fb_info(NULL, &sharp_lq43_info); } #endif diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index d4e705caefe..3a5507e3191 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -462,7 +462,6 @@ static struct pxaficp_platform_data corgi_ficp_platform_data = { * USB Device Controller */ static struct pxa2xx_udc_mach_info udc_info __initdata = { - .gpio_vbus = -1, /* no connect GPIO; corgi can't tell connection status */ .gpio_pullup = CORGI_GPIO_USB_PULLUP, }; diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index c4bf08b3eb6..2e0425404de 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -90,7 +90,6 @@ void __init pxa_set_mci_info(struct pxamci_platform_data *info) static struct pxa2xx_udc_mach_info pxa_udc_info = { .gpio_pullup = -1, - .gpio_vbus = -1, }; void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) @@ -188,16 +187,12 @@ struct platform_device pxa_device_fb = { .resource = pxafb_resources, }; -void __init set_pxa_fb_info(struct pxafb_mach_info *info) +void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info) { + pxa_device_fb.dev.parent = parent; pxa_register_device(&pxa_device_fb, info); } -void __init set_pxa_fb_parent(struct device *parent_dev) -{ - pxa_device_fb.dev.parent = parent_dev; -} - static struct resource pxa_resource_ffuart[] = { { .start = 0x40100000, diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index b411d7cbf5a..f8a6e9d79a3 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -689,7 +689,7 @@ static struct pxafb_mach_info em_x270_lcd = { static void __init em_x270_init_lcd(void) { - set_pxa_fb_info(&em_x270_lcd); + pxa_set_fb_info(NULL, &em_x270_lcd); } #else static inline void em_x270_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index edca0a04329..2e3970fdde0 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -20,6 +20,7 @@ #include <linux/mfd/t7l66xb.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/usb/gpio_vbus.h> #include <video/w100fb.h> @@ -51,12 +52,20 @@ void __init eseries_fixup(struct machine_desc *desc, mi->bank[0].size = (64*1024*1024); } -struct pxa2xx_udc_mach_info e7xx_udc_mach_info = { +struct gpio_vbus_mach_info e7xx_udc_info = { .gpio_vbus = GPIO_E7XX_USB_DISC, .gpio_pullup = GPIO_E7XX_USB_PULLUP, .gpio_pullup_inverted = 1 }; +static struct platform_device e7xx_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &e7xx_udc_info, + }, +}; + struct pxaficp_platform_data e7xx_ficp_platform_data = { .gpio_pwdown = GPIO_E7XX_IR_OFF, .transceiver_cap = IR_SIRMODE | IR_OFF, @@ -165,6 +174,7 @@ static struct platform_device e330_tc6387xb_device = { static struct platform_device *e330_devices[] __initdata = { &e330_tc6387xb_device, + &e7xx_gpio_vbus, }; static void __init e330_init(void) @@ -175,7 +185,6 @@ static void __init e330_init(void) eseries_register_clks(); eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e330_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); } MACHINE_START(E330, "Toshiba e330") @@ -214,6 +223,7 @@ static struct platform_device e350_t7l66xb_device = { static struct platform_device *e350_devices[] __initdata = { &e350_t7l66xb_device, + &e7xx_gpio_vbus, }; static void __init e350_init(void) @@ -224,7 +234,6 @@ static void __init e350_init(void) eseries_register_clks(); eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e350_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); } MACHINE_START(E350, "Toshiba e350") @@ -333,6 +342,7 @@ static struct platform_device e400_t7l66xb_device = { static struct platform_device *e400_devices[] __initdata = { &e400_t7l66xb_device, + &e7xx_gpio_vbus, }; static void __init e400_init(void) @@ -344,9 +354,8 @@ static void __init e400_init(void) /* Fixme - e400 may have a switched clock */ eseries_register_clks(); eseries_get_tmio_gpios(); - set_pxa_fb_info(&e400_pxafb_mach_info); + pxa_set_fb_info(NULL, &e400_pxafb_mach_info); platform_add_devices(ARRAY_AND_SIZE(e400_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); } MACHINE_START(E400, "Toshiba e400") @@ -519,6 +528,7 @@ static struct platform_device e740_t7l66xb_device = { static struct platform_device *e740_devices[] __initdata = { &e740_fb_device, &e740_t7l66xb_device, + &e7xx_gpio_vbus, }; static void __init e740_init(void) @@ -532,7 +542,6 @@ static void __init e740_init(void) "UDCCLK", &pxa25x_device_udc.dev), eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e740_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&e7xx_ficp_platform_data); } @@ -711,6 +720,7 @@ static struct platform_device e750_tc6393xb_device = { static struct platform_device *e750_devices[] __initdata = { &e750_fb_device, &e750_tc6393xb_device, + &e7xx_gpio_vbus, }; static void __init e750_init(void) @@ -723,7 +733,6 @@ static void __init e750_init(void) "GPIO11_CLK", NULL), eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e750_devices)); - pxa_set_udc_info(&e7xx_udc_mach_info); pxa_set_ac97_info(NULL); pxa_set_ficp_info(&e7xx_ficp_platform_data); } @@ -873,12 +882,21 @@ static struct platform_device e800_fb_device = { /* --------------------------- UDC definitions --------------------------- */ -static struct pxa2xx_udc_mach_info e800_udc_mach_info = { +static struct gpio_vbus_mach_info e800_udc_info = { .gpio_vbus = GPIO_E800_USB_DISC, .gpio_pullup = GPIO_E800_USB_PULLUP, .gpio_pullup_inverted = 1 }; +static struct platform_device e800_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &e800_udc_info, + }, +}; + + /* ----------------- e800 tc6393xb parameters ------------------ */ static struct tc6393xb_platform_data e800_tc6393xb_info = { @@ -907,6 +925,7 @@ static struct platform_device e800_tc6393xb_device = { static struct platform_device *e800_devices[] __initdata = { &e800_fb_device, &e800_tc6393xb_device, + &e800_gpio_vbus, }; static void __init e800_init(void) @@ -919,7 +938,6 @@ static void __init e800_init(void) "GPIO11_CLK", NULL), eseries_get_tmio_gpios(); platform_add_devices(ARRAY_AND_SIZE(e800_devices)); - pxa_set_udc_info(&e800_udc_mach_info); pxa_set_ac97_info(NULL); } diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 93f05e02431..d88aed8fbe1 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -783,7 +783,7 @@ static void __init a780_init(void) pxa_set_i2c_info(NULL); - set_pxa_fb_info(&ezx_fb_info_1); + pxa_set_fb_info(NULL, &ezx_fb_info_1); pxa_set_keypad_info(&a780_keypad_platform_data); @@ -853,7 +853,7 @@ static void __init e680_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_1); + pxa_set_fb_info(NULL, &ezx_fb_info_1); pxa_set_keypad_info(&e680_keypad_platform_data); @@ -918,7 +918,7 @@ static void __init a1200_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&a1200_keypad_platform_data); @@ -1103,7 +1103,7 @@ static void __init a910_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&a910_keypad_platform_data); @@ -1173,7 +1173,7 @@ static void __init e6_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&e6_keypad_platform_data); @@ -1212,7 +1212,7 @@ static void __init e2_init(void) pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); - set_pxa_fb_info(&ezx_fb_info_2); + pxa_set_fb_info(NULL, &ezx_fb_info_2); pxa_set_keypad_info(&e2_keypad_platform_data); diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index a079d8baa45..e6c9344a95a 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -61,10 +61,10 @@ extern unsigned pxa3xx_get_clk_frequency_khz(int); #define pxa3xx_get_clk_frequency_khz(x) (0) #endif -extern struct sysdev_class pxa_irq_sysclass; -extern struct sysdev_class pxa_gpio_sysclass; -extern struct sysdev_class pxa2xx_mfp_sysclass; -extern struct sysdev_class pxa3xx_mfp_sysclass; +extern struct syscore_ops pxa_irq_syscore_ops; +extern struct syscore_ops pxa_gpio_syscore_ops; +extern struct syscore_ops pxa2xx_mfp_syscore_ops; +extern struct syscore_ops pxa3xx_mfp_syscore_ops; void __init pxa_set_ffuart_info(void *info); void __init pxa_set_btuart_info(void *info); diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 6fd319ea528..d65e4bde9b9 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -26,6 +26,7 @@ #include <linux/gpio.h> #include <linux/err.h> #include <linux/clk.h> +#include <linux/usb/gpio_vbus.h> #include <asm/setup.h> #include <asm/memory.h> @@ -106,14 +107,22 @@ static void __init gumstix_mmc_init(void) #endif #ifdef CONFIG_USB_GADGET_PXA25X -static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { +static struct gpio_vbus_mach_info gumstix_udc_info = { .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, }; +static struct platform_device gumstix_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &gumstix_udc_info, + }, +}; + static void __init gumstix_udc_init(void) { - pxa_set_udc_info(&gumstix_udc_info); + platform_device_register(&gumstix_gpio_vbus); } #else static void gumstix_udc_init(void) diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 6de0ad0eea6..f941a495a4a 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -711,7 +711,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = { static struct regulator_init_data bq24022_init_data = { .constraints = { .max_uA = 500000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT|REGULATOR_CHANGE_STATUS, }, .num_consumer_supplies = ARRAY_SIZE(bq24022_consumers), .consumer_supplies = bq24022_consumers, @@ -735,7 +735,7 @@ static struct platform_device bq24022 = { * StrataFlash */ -static void hx4700_set_vpp(struct map_info *map, int vpp) +static void hx4700_set_vpp(struct platform_device *pdev, int vpp) { gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp); } diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index dd40e4a9291..f7fb64f11a7 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -167,7 +167,7 @@ static void __init idp_init(void) platform_device_register(&smc91x_device); //platform_device_register(&mst_audio_device); - set_pxa_fb_info(&sharp_lm8v31); + pxa_set_fb_info(NULL, &sharp_lm8v31); pxa_set_mci_info(&idp_mci_platform_data); } diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h index b024a8b3743..c4639502efc 100644 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ b/arch/arm/mach-pxa/include/mach/gpio.h @@ -99,11 +99,24 @@ #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) -#define NR_BUILTIN_GPIO 128 +#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM #define gpio_to_bank(gpio) ((gpio) >> 5) #define gpio_to_irq(gpio) IRQ_GPIO(gpio) -#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) + +static inline int irq_to_gpio(unsigned int irq) +{ + int gpio; + + if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1) + return irq - IRQ_GPIO0; + + gpio = irq - PXA_GPIO_IRQ_BASE; + if (gpio >= 2 && gpio < NR_BUILTIN_GPIO) + return gpio; + + return -1; +} #ifdef CONFIG_CPU_PXA26x /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index a4285fc0087..038402404e3 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -93,9 +93,6 @@ #define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) -#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) -#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) - /* * The following interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 7f68724dcc2..07734f37f8f 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -17,14 +17,8 @@ */ #define PLAT_PHYS_OFFSET UL(0xa0000000) -#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - cmx2xx_pci_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +#define ARM_DMA_ZONE_SIZE SZ_64M #endif #endif diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 2bbcf70dd93..0d4700a7961 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h @@ -44,6 +44,11 @@ #define GPIO_NR_PALMZ72_BT_POWER 17 #define GPIO_NR_PALMZ72_BT_RESET 83 +/* Camera */ +#define GPIO_NR_PALMZ72_CAM_PWDN 56 +#define GPIO_NR_PALMZ72_CAM_RESET 57 +#define GPIO_NR_PALMZ72_CAM_POWER 91 + /** Initial values **/ /* Battery */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index e4fb4668c26..207ecb49a61 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -38,7 +38,7 @@ #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) /* - * Slave Power Managment Unit + * Slave Power Management Unit */ #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index 160ec83f51a..01a45ac4811 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -154,8 +154,8 @@ struct pxafb_mach_info { void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); void (*smart_update)(struct fb_info *); }; -void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); -void set_pxa_fb_parent(struct device *parent_dev); + +void pxa_set_fb_info(struct device *, struct pxafb_mach_info *); unsigned long pxafb_get_hsync_time(struct device *dev); extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 759b851ec98..5519a34b667 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -16,9 +16,9 @@ #define BTUART_BASE (0x40200000) #define STUART_BASE (0x40700000) -static unsigned long uart_base; -static unsigned int uart_shift; -static unsigned int uart_is_pxa; +unsigned long uart_base; +unsigned int uart_shift; +unsigned int uart_is_pxa; static inline unsigned char uart_read(int offset) { diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h index 8835c16bc82..7b0f71ef316 100644 --- a/arch/arm/mach-pxa/include/mach/z2.h +++ b/arch/arm/mach-pxa/include/mach/z2.h @@ -25,8 +25,7 @@ #define GPIO98_ZIPITZ2_LID_BUTTON 98 /* Libertas GSPI8686 WiFi */ -#define GPIO14_ZIPITZ2_WIFI_RESET 14 -#define GPIO15_ZIPITZ2_WIFI_POWER 15 +#define GPIO14_ZIPITZ2_WIFI_POWER 14 #define GPIO24_ZIPITZ2_WIFI_CS 24 #define GPIO36_ZIPITZ2_WIFI_IRQ 36 diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index faa408ab7ad..0641f31a56b 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -64,7 +64,7 @@ /* * CPLD registers: - * Only 4 registers, but spreaded over a 32MB address space. + * Only 4 registers, but spread over a 32MB address space. * Be gentle, and remap that over 32kB... */ diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 2693e3c3776..32ed551bf9c 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <linux/irq.h> @@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) GEDR0 = 0x3; for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { - set_irq_chip(irq, &pxa_low_gpio_chip); - set_irq_chip_data(irq, irq_base(0)); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, + handle_edge_irq); + irq_set_chip_data(irq, irq_base(0)); set_irq_flags(irq, IRQF_VALID); } @@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); irq = PXA_IRQ(i); - set_irq_chip(irq, &pxa_internal_irq_chip); - set_irq_chip_data(irq, base); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID); } } @@ -183,7 +183,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; -static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) +static int pxa_irq_suspend(void) { int i; @@ -202,7 +202,7 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int pxa_irq_resume(struct sys_device *dev) +static void pxa_irq_resume(void) { int i; @@ -218,22 +218,13 @@ static int pxa_irq_resume(struct sys_device *dev) __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); __raw_writel(1, IRQ_BASE + ICCR); - return 0; } #else #define pxa_irq_suspend NULL #define pxa_irq_resume NULL #endif -struct sysdev_class pxa_irq_sysclass = { - .name = "irq", +struct syscore_ops pxa_irq_syscore_ops = { .suspend = pxa_irq_suspend, .resume = pxa_irq_resume, }; - -static int __init pxa_irq_init(void) -{ - return sysdev_class_register(&pxa_irq_sysclass); -} - -core_initcall(pxa_irq_init); diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 87c1ed9ccd2..e5e326d2cdc 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -185,7 +185,7 @@ static struct pxafb_mach_info littleton_lcd_info = { static void littleton_init_lcd(void) { - set_pxa_fb_info(&littleton_lcd_info); + pxa_set_fb_info(NULL, &littleton_lcd_info); } #else static inline void littleton_init_lcd(void) {}; diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index c9a3e775c2d..6cf8180bf5b 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> @@ -149,40 +149,32 @@ static void __init lpd270_init_irq(void) /* setup extra LogicPD PXA270 irqs */ for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { - set_irq_chip(irq, &lpd270_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &lpd270_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM -static int lpd270_irq_resume(struct sys_device *dev) +static void lpd270_irq_resume(void) { __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); - return 0; } -static struct sysdev_class lpd270_irq_sysclass = { - .name = "cpld_irq", +static struct syscore_ops lpd270_irq_syscore_ops = { .resume = lpd270_irq_resume, }; -static struct sys_device lpd270_irq_device = { - .cls = &lpd270_irq_sysclass, -}; - static int __init lpd270_irq_device_init(void) { - int ret = -ENODEV; if (machine_is_logicpd_pxa270()) { - ret = sysdev_class_register(&lpd270_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&lpd270_irq_device); + register_syscore_ops(&lpd270_irq_syscore_ops); + return 0; } - return ret; + return -ENODEV; } device_initcall(lpd270_irq_device_init); @@ -480,7 +472,7 @@ static void __init lpd270_init(void) pxa_set_ac97_info(NULL); if (lpd270_lcd_to_use != NULL) - set_pxa_fb_info(lpd270_lcd_to_use); + pxa_set_fb_info(NULL, lpd270_lcd_to_use); pxa_set_ohci_info(&lpd270_ohci_platform_data); } diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index dca20de306b..e10ddb82714 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -15,7 +15,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/major.h> #include <linux/fb.h> #include <linux/interrupt.h> @@ -165,42 +165,33 @@ static void __init lubbock_init_irq(void) /* setup extra lubbock irqs */ for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { - set_irq_chip(irq, &lubbock_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &lubbock_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM -static int lubbock_irq_resume(struct sys_device *dev) +static void lubbock_irq_resume(void) { LUB_IRQ_MASK_EN = lubbock_irq_enabled; - return 0; } -static struct sysdev_class lubbock_irq_sysclass = { - .name = "cpld_irq", +static struct syscore_ops lubbock_irq_syscore_ops = { .resume = lubbock_irq_resume, }; -static struct sys_device lubbock_irq_device = { - .cls = &lubbock_irq_sysclass, -}; - static int __init lubbock_irq_device_init(void) { - int ret = -ENODEV; - if (machine_is_lubbock()) { - ret = sysdev_class_register(&lubbock_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&lubbock_irq_device); + register_syscore_ops(&lubbock_irq_syscore_ops); + return 0; } - return ret; + return -ENODEV; } device_initcall(lubbock_irq_device_init); @@ -521,7 +512,7 @@ static void __init lubbock_init(void) clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); pxa_set_udc_info(&udc_info); - set_pxa_fb_info(&sharp_lm8v31); + pxa_set_fb_info(NULL, &sharp_lm8v31); pxa_set_mci_info(&lubbock_mci_platform_data); pxa_set_ficp_info(&lubbock_ficp_platform_data); pxa_set_ac97_info(NULL); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 5535991c4a3..e1920572948 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -599,7 +599,7 @@ static struct regulator_consumer_supply bq24022_consumers[] = { static struct regulator_init_data bq24022_init_data = { .constraints = { .max_uA = 500000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS, }, .num_consumer_supplies = ARRAY_SIZE(bq24022_consumers), .consumer_supplies = bq24022_consumers, @@ -662,7 +662,7 @@ static struct pxaohci_platform_data magician_ohci_info = { * StrataFlash */ -static void magician_set_vpp(struct map_info *map, int vpp) +static void magician_set_vpp(struct platform_device *pdev, int vpp) { gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); } @@ -757,7 +757,7 @@ static void __init magician_init(void) gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0); gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0); gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0); - set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info); + pxa_set_fb_info(NULL, lcd_select ? &samsung_info : &toppoly_info); } else pr_err("LCD detection: CPLD mapping failed\n"); } diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f9542220595..3479e2b3b51 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> @@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void) /* setup extra Mainstone irqs */ for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { - set_irq_chip(irq, &mainstone_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &mainstone_irq_chip, + handle_level_irq); if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); else @@ -179,37 +179,27 @@ static void __init mainstone_init_irq(void) MST_INTMSKENA = 0; MST_INTSETCLR = 0; - set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); - set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); + irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); + irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); } #ifdef CONFIG_PM -static int mainstone_irq_resume(struct sys_device *dev) +static void mainstone_irq_resume(void) { MST_INTMSKENA = mainstone_irq_enabled; - return 0; } -static struct sysdev_class mainstone_irq_sysclass = { - .name = "cpld_irq", +static struct syscore_ops mainstone_irq_syscore_ops = { .resume = mainstone_irq_resume, }; -static struct sys_device mainstone_irq_device = { - .cls = &mainstone_irq_sysclass, -}; - static int __init mainstone_irq_device_init(void) { - int ret = -ENODEV; + if (machine_is_mainstone()) + register_syscore_ops(&mainstone_irq_syscore_ops); - if (machine_is_mainstone()) { - ret = sysdev_class_register(&mainstone_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&mainstone_irq_device); - } - return ret; + return 0; } device_initcall(mainstone_irq_device_init); @@ -592,7 +582,7 @@ static void __init mainstone_init(void) else mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; - set_pxa_fb_info(&mainstone_pxafb_info); + pxa_set_fb_info(NULL, &mainstone_pxafb_info); mainstone_backlight_register(); pxa_set_mci_info(&mainstone_mci_platform_data); diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 1d1419b7345..87ae3129f4f 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -16,7 +16,7 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/gpio.h> #include <mach/pxa2xx-regs.h> @@ -338,7 +338,7 @@ static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; static unsigned long saved_pgsr[4]; -static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) +static int pxa2xx_mfp_suspend(void) { int i; @@ -365,7 +365,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) return 0; } -static int pxa2xx_mfp_resume(struct sys_device *d) +static void pxa2xx_mfp_resume(void) { int i; @@ -376,15 +376,13 @@ static int pxa2xx_mfp_resume(struct sys_device *d) PGSR(i) = saved_pgsr[i]; } PSSR = PSSR_RDH | PSSR_PH; - return 0; } #else #define pxa2xx_mfp_suspend NULL #define pxa2xx_mfp_resume NULL #endif -struct sysdev_class pxa2xx_mfp_sysclass = { - .name = "mfp", +struct syscore_ops pxa2xx_mfp_syscore_ops = { .suspend = pxa2xx_mfp_suspend, .resume = pxa2xx_mfp_resume, }; @@ -409,6 +407,6 @@ static int __init pxa2xx_mfp_init(void) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); - return sysdev_class_register(&pxa2xx_mfp_sysclass); + return 0; } postcore_initcall(pxa2xx_mfp_init); diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index 7a270eecd48..89863a01ecd 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -17,7 +17,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <mach/mfp-pxa3xx.h> @@ -31,13 +31,13 @@ * a pull-down mode if they're an active low chip select, and we're * just entering standby. */ -static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) +static int pxa3xx_mfp_suspend(void) { mfp_config_lpm(); return 0; } -static int pxa3xx_mfp_resume(struct sys_device *d) +static void pxa3xx_mfp_resume(void) { mfp_config_run(); @@ -47,24 +47,13 @@ static int pxa3xx_mfp_resume(struct sys_device *d) * preserve them here in case they will be referenced later */ ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); - return 0; } #else #define pxa3xx_mfp_suspend NULL #define pxa3xx_mfp_resume NULL #endif -struct sysdev_class pxa3xx_mfp_sysclass = { - .name = "mfp", +struct syscore_ops pxa3xx_mfp_syscore_ops = { .suspend = pxa3xx_mfp_suspend, - .resume = pxa3xx_mfp_resume, + .resume = pxa3xx_mfp_resume, }; - -static int __init mfp_init_devicefs(void) -{ - if (cpu_is_pxa3xx()) - return sysdev_class_register(&pxa3xx_mfp_sysclass); - - return 0; -} -postcore_initcall(mfp_init_devicefs); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 78d98a8607e..e3470137c93 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -22,7 +22,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/input.h> #include <linux/delay.h> #include <linux/gpio_keys.h> @@ -458,7 +458,7 @@ static struct platform_device strataflash = { /* * Suspend/Resume bootstrap management * - * MIO A701 reboot sequence is highly ROM dependant. From the one dissassembled, + * MIO A701 reboot sequence is highly ROM dependent. From the one dissassembled, * this sequence is as follows : * - disables interrupts * - initialize SDRAM (self refresh RAM into active RAM) @@ -488,7 +488,7 @@ static void install_bootstrap(void) } -static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state) +static int mioa701_sys_suspend(void) { int i = 0, is_bt_on; u32 *mem_resume_vector = phys_to_virt(RESUME_VECTOR_ADDR); @@ -514,7 +514,7 @@ static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state) return 0; } -static int mioa701_sys_resume(struct sys_device *sysdev) +static void mioa701_sys_resume(void) { int i = 0; u32 *mem_resume_vector = phys_to_virt(RESUME_VECTOR_ADDR); @@ -527,43 +527,18 @@ static int mioa701_sys_resume(struct sys_device *sysdev) *mem_resume_enabler = save_buffer[i++]; *mem_resume_bt = save_buffer[i++]; *mem_resume_unknown = save_buffer[i++]; - - return 0; } -static struct sysdev_class mioa701_sysclass = { - .name = "mioa701", -}; - -static struct sys_device sysdev_bootstrap = { - .cls = &mioa701_sysclass, -}; - -static struct sysdev_driver driver_bootstrap = { - .suspend = &mioa701_sys_suspend, - .resume = &mioa701_sys_resume, +static struct syscore_ops mioa701_syscore_ops = { + .suspend = mioa701_sys_suspend, + .resume = mioa701_sys_resume, }; static int __init bootstrap_init(void) { - int rc; int save_size = mioa701_bootstrap_lg + (sizeof(u32) * 3); - rc = sysdev_class_register(&mioa701_sysclass); - if (rc) { - printk(KERN_ERR "Failed registering mioa701 sys class\n"); - return -ENODEV; - } - rc = sysdev_register(&sysdev_bootstrap); - if (rc) { - printk(KERN_ERR "Failed registering mioa701 sys device\n"); - return -ENODEV; - } - rc = sysdev_driver_register(&mioa701_sysclass, &driver_bootstrap); - if (rc) { - printk(KERN_ERR "Failed registering PMU sys driver\n"); - return -ENODEV; - } + register_syscore_ops(&mioa701_syscore_ops); save_buffer = kmalloc(save_size, GFP_KERNEL); if (!save_buffer) @@ -576,9 +551,7 @@ static int __init bootstrap_init(void) static void bootstrap_exit(void) { kfree(save_buffer); - sysdev_driver_unregister(&mioa701_sysclass, &driver_bootstrap); - sysdev_unregister(&sysdev_bootstrap); - sysdev_class_unregister(&mioa701_sysclass); + unregister_syscore_ops(&mioa701_syscore_ops); printk(KERN_CRIT "Unregistering mioa701 suspend will hang next" "resume !!!\n"); @@ -795,7 +768,7 @@ static void __init mioa701_machine_init(void) pxa_set_stuart_info(NULL); mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); bootstrap_init(); - set_pxa_fb_info(&mioa701_pxafb_info); + pxa_set_fb_info(NULL, &mioa701_pxafb_info); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); pxa_set_udc_info(&mioa701_udc_info); diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 72adb3ae2b4..325c245c0a0 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -1,8 +1,7 @@ /* * Common code for Palm LD, T5, TX, Z72 * - * Copyright (C) 2010 - * Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2010-2011 Marek Vasut <marek.vasut@gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -158,7 +157,7 @@ void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode) palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl; } - set_pxa_fb_info(&palm27x_lcd_screen); + pxa_set_fb_info(NULL, &palm27x_lcd_screen); } #endif diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index a6f898cbfac..4061ecddee7 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -24,7 +24,6 @@ #include <linux/gpio.h> #include <linux/wm97xx.h> #include <linux/power_supply.h> -#include <linux/sysdev.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index a09a2374697..fb06bd04727 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -507,7 +507,7 @@ static struct pxafb_mach_info palmtc_lcd_screen = { static void __init palmtc_lcd_init(void) { - set_pxa_fb_info(&palmtc_lcd_screen); + pxa_set_fb_info(NULL, &palmtc_lcd_screen); } #else static inline void palmtc_lcd_init(void) {} diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 3f25014a136..726f5b98dcd 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -136,30 +136,14 @@ static struct platform_device palmte2_pxa_keys = { /****************************************************************************** * Backlight ******************************************************************************/ +static struct gpio palmte_bl_gpios[] = { + { GPIO_NR_PALMTE2_BL_POWER, GPIOF_INIT_LOW, "Backlight power" }, + { GPIO_NR_PALMTE2_LCD_POWER, GPIOF_INIT_LOW, "LCD power" }, +}; + static int palmte2_backlight_init(struct device *dev) { - int ret; - - ret = gpio_request(GPIO_NR_PALMTE2_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_PALMTE2_BL_POWER, 0); - if (ret) - goto err2; - ret = gpio_request(GPIO_NR_PALMTE2_LCD_POWER, "LCD POWER"); - if (ret) - goto err2; - ret = gpio_direction_output(GPIO_NR_PALMTE2_LCD_POWER, 0); - if (ret) - goto err3; - - return 0; -err3: - gpio_free(GPIO_NR_PALMTE2_LCD_POWER); -err2: - gpio_free(GPIO_NR_PALMTE2_BL_POWER); -err: - return ret; + return gpio_request_array(ARRAY_AND_SIZE(palmte_bl_gpios)); } static int palmte2_backlight_notify(struct device *dev, int brightness) @@ -171,8 +155,7 @@ static int palmte2_backlight_notify(struct device *dev, int brightness) static void palmte2_backlight_exit(struct device *dev) { - gpio_free(GPIO_NR_PALMTE2_BL_POWER); - gpio_free(GPIO_NR_PALMTE2_LCD_POWER); + gpio_free_array(ARRAY_AND_SIZE(palmte_bl_gpios)); } static struct platform_pwm_backlight_data palmte2_backlight_data = { @@ -363,7 +346,7 @@ static void __init palmte2_init(void) pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - set_pxa_fb_info(&palmte2_lcd_screen); + pxa_set_fb_info(NULL, &palmte2_lcd_screen); pxa_set_mci_info(&palmte2_mci_platform_data); palmte2_udc_init(); pxa_set_ac97_info(&palmte2_ac97_pdata); diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 8aadad55fbe..20d1b18b173 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -25,7 +25,6 @@ #include <linux/pwm_backlight.h> #include <linux/gpio.h> #include <linux/power_supply.h> -#include <linux/sysdev.h> #include <linux/w1-gpio.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 3010193b081..65f24f0b77e 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -19,7 +19,7 @@ */ #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/delay.h> #include <linux/irq.h> #include <linux/gpio_keys.h> @@ -30,6 +30,7 @@ #include <linux/wm97xx.h> #include <linux/power_supply.h> #include <linux/usb/gpio_vbus.h> +#include <linux/i2c-gpio.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -47,6 +48,9 @@ #include <mach/palm27x.h> #include <mach/pm.h> +#include <mach/camera.h> + +#include <media/soc_camera.h> #include "generic.h" #include "devices.h" @@ -103,6 +107,28 @@ static unsigned long palmz72_pin_config[] __initdata = { GPIO22_GPIO, /* LCD border color */ GPIO96_GPIO, /* lcd power */ + /* PXA Camera */ + GPIO81_CIF_DD_0, + GPIO48_CIF_DD_5, + GPIO50_CIF_DD_3, + GPIO51_CIF_DD_2, + GPIO52_CIF_DD_4, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO55_CIF_DD_1, + GPIO84_CIF_FV, + GPIO85_CIF_LV, + GPIO93_CIF_DD_6, + GPIO108_CIF_DD_7, + + GPIO56_GPIO, /* OV9640 Powerdown */ + GPIO57_GPIO, /* OV9640 Reset */ + GPIO91_GPIO, /* OV9640 Power */ + + /* I2C */ + GPIO117_GPIO, /* I2C_SCL */ + GPIO118_GPIO, /* I2C_SDA */ + /* Misc. */ GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */ GPIO88_GPIO, /* green led */ @@ -207,9 +233,9 @@ static struct palmz72_resume_info palmz72_resume_info = { static unsigned long store_ptr; -/* sys_device for Palm Zire 72 PM */ +/* syscore_ops for Palm Zire 72 PM */ -static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg) +static int palmz72_pm_suspend(void) { /* setup the resume_info struct for the original bootloader */ palmz72_resume_info.resume_addr = (u32) cpu_resume; @@ -223,37 +249,129 @@ static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg) return 0; } -static int palmz72_pm_resume(struct sys_device *dev) +static void palmz72_pm_resume(void) { *PALMZ72_SAVE_DWORD = store_ptr; - return 0; } -static struct sysdev_class palmz72_pm_sysclass = { - .name = "palmz72_pm", +static struct syscore_ops palmz72_pm_syscore_ops = { .suspend = palmz72_pm_suspend, .resume = palmz72_pm_resume, }; -static struct sys_device palmz72_pm_device = { - .cls = &palmz72_pm_sysclass, -}; - static int __init palmz72_pm_init(void) { - int ret = -ENODEV; if (machine_is_palmz72()) { - ret = sysdev_class_register(&palmz72_pm_sysclass); - if (ret == 0) - ret = sysdev_register(&palmz72_pm_device); + register_syscore_ops(&palmz72_pm_syscore_ops); + return 0; } - return ret; + return -ENODEV; } device_initcall(palmz72_pm_init); #endif /****************************************************************************** + * SoC Camera + ******************************************************************************/ +#if defined(CONFIG_SOC_CAMERA_OV9640) || \ + defined(CONFIG_SOC_CAMERA_OV9640_MODULE) +static struct pxacamera_platform_data palmz72_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 2600, +}; + +/* Board I2C devices. */ +static struct i2c_board_info palmz72_i2c_device[] = { + { + I2C_BOARD_INFO("ov9640", 0x30), + } +}; + +static int palmz72_camera_power(struct device *dev, int power) +{ + gpio_set_value(GPIO_NR_PALMZ72_CAM_PWDN, !power); + mdelay(50); + return 0; +} + +static int palmz72_camera_reset(struct device *dev) +{ + gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 1); + mdelay(50); + gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 0); + mdelay(50); + return 0; +} + +static struct soc_camera_link palmz72_iclink = { + .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */ + .board_info = &palmz72_i2c_device[0], + .i2c_adapter_id = 0, + .module_name = "ov96xx", + .power = &palmz72_camera_power, + .reset = &palmz72_camera_reset, + .flags = SOCAM_DATAWIDTH_8, +}; + +static struct i2c_gpio_platform_data palmz72_i2c_bus_data = { + .sda_pin = 118, + .scl_pin = 117, + .udelay = 10, + .timeout = 100, +}; + +static struct platform_device palmz72_i2c_bus_device = { + .name = "i2c-gpio", + .id = 0, /* we use this as a replacement for i2c-pxa */ + .dev = { + .platform_data = &palmz72_i2c_bus_data, + } +}; + +static struct platform_device palmz72_camera = { + .name = "soc-camera-pdrv", + .id = -1, + .dev = { + .platform_data = &palmz72_iclink, + }, +}; + +/* Here we request the camera GPIOs and configure them. We power up the camera + * module, deassert the reset pin, but put it into powerdown (low to no power + * consumption) mode. This allows us to later bring the module up fast. */ +static struct gpio palmz72_camera_gpios[] = { + { GPIO_NR_PALMZ72_CAM_POWER, GPIOF_INIT_HIGH,"Camera DVDD" }, + { GPIO_NR_PALMZ72_CAM_RESET, GPIOF_INIT_LOW, "Camera RESET" }, + { GPIO_NR_PALMZ72_CAM_PWDN, GPIOF_INIT_LOW, "Camera PWDN" }, +}; + +static inline void __init palmz72_cam_gpio_init(void) +{ + int ret; + + ret = gpio_request_array(ARRAY_AND_SIZE(palmz72_camera_gpios)); + if (!ret) + gpio_free_array(ARRAY_AND_SIZE(palmz72_camera_gpios)); + else + printk(KERN_ERR "Camera GPIO init failed!\n"); + + return; +} + +static void __init palmz72_camera_init(void) +{ + palmz72_cam_gpio_init(); + pxa_set_camera_info(&palmz72_pxacamera_platform_data); + platform_device_register(&palmz72_i2c_bus_device); + platform_device_register(&palmz72_camera); +} +#else +static inline void palmz72_camera_init(void) {} +#endif + +/****************************************************************************** * Machine init ******************************************************************************/ static void __init palmz72_init(void) @@ -276,6 +394,7 @@ static void __init palmz72_init(void) palm27x_pmic_init(); palmz72_kpc_init(); palmz72_leds_init(); + palmz72_camera_init(); } MACHINE_START(PALMZ72, "Palm Zire72") diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9dbf3ccd415..6d5b7e06212 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void) /* setup extra PCM990 irqs */ for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { - set_irq_chip(irq, &pcm990_irq_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &pcm990_irq_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ PCM990_INTSETCLR = 0xFF; - set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); - set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); + irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); + irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); } static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, @@ -515,7 +515,7 @@ void __init pcm990_baseboard_init(void) pcm990_init_irq(); #ifndef CONFIG_PCM990_DISPLAY_NONE - set_pxa_fb_info(&pcm990_fbinfo); + pxa_set_fb_info(NULL, &pcm990_fbinfo); #endif platform_device_register(&pcm990_backlight_device); diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 35353af345d..16d14fd79b4 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -445,8 +445,7 @@ static void __init poodle_init(void) if (ret) pr_warning("poodle: Unable to register LoCoMo device\n"); - set_pxa_fb_parent(&poodle_locomo_device.dev); - set_pxa_fb_info(&poodle_fb_info); + pxa_set_fb_info(&poodle_locomo_device.dev, &poodle_fb_info); pxa_set_udc_info(&udc_info); pxa_set_mci_info(&poodle_mci_platform_data); pxa_set_ficp_info(&poodle_ficp_platform_data); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6bde5956358..fed363cec9c 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/suspend.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/irq.h> #include <asm/mach/map.h> @@ -285,7 +285,7 @@ static inline void pxa25x_init_pm(void) {} static int pxa25x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = IRQ_TO_GPIO(d->irq); + int gpio = irq_to_gpio(d->irq); uint32_t mask = 0; if (gpio >= 0 && gpio < 85) @@ -350,21 +350,9 @@ static struct platform_device *pxa25x_devices[] __initdata = { &pxa_device_asoc_platform, }; -static struct sys_device pxa25x_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa2xx_mfp_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa2xx_clock_sysclass, - } -}; - static int __init pxa25x_init(void) { - int i, ret = 0; + int ret = 0; if (cpu_is_pxa25x()) { @@ -377,11 +365,10 @@ static int __init pxa25x_init(void) pxa25x_init_pm(); - for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { - ret = sysdev_register(&pxa25x_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa2xx_mfp_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa2xx_clock_syscore_ops); ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 1cb5d0f9723..2fecbec58d8 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -16,7 +16,7 @@ #include <linux/init.h> #include <linux/suspend.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/i2c/pxa-i2c.h> @@ -345,7 +345,7 @@ static inline void pxa27x_init_pm(void) {} */ static int pxa27x_set_wake(struct irq_data *d, unsigned int on) { - int gpio = IRQ_TO_GPIO(d->irq); + int gpio = irq_to_gpio(d->irq); uint32_t mask; if (gpio >= 0 && gpio < 128) @@ -428,21 +428,9 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_pwm1, }; -static struct sys_device pxa27x_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa2xx_mfp_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa2xx_clock_sysclass, - } -}; - static int __init pxa27x_init(void) { - int i, ret = 0; + int ret = 0; if (cpu_is_pxa27x()) { @@ -455,11 +443,10 @@ static int __init pxa27x_init(void) pxa27x_init_pm(); - for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { - ret = sysdev_register(&pxa27x_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa2xx_mfp_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa2xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f374247b846..8521d7d6f1d 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -20,7 +20,7 @@ #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/i2c/pxa-i2c.h> #include <asm/mach/map.h> @@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) int irq; for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { - set_irq_chip(irq, &pxa_ext_wakeup_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID); } @@ -427,21 +427,9 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_pwm1, }; -static struct sys_device pxa3xx_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa3xx_mfp_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa3xx_clock_sysclass, - } -}; - static int __init pxa3xx_init(void) { - int i, ret = 0; + int ret = 0; if (cpu_is_pxa3xx()) { @@ -462,11 +450,10 @@ static int __init pxa3xx_init(void) pxa3xx_init_pm(); - for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { - ret = sysdev_register(&pxa3xx_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa3xx_mfp_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa3xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c index 23b229bd06e..ecc82a330fa 100644 --- a/arch/arm/mach-pxa/pxa95x.c +++ b/arch/arm/mach-pxa/pxa95x.c @@ -18,7 +18,7 @@ #include <linux/i2c/pxa-i2c.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -260,16 +260,6 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_pwm1, }; -static struct sys_device pxa95x_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa3xx_clock_sysclass, - } -}; - static int __init pxa95x_init(void) { int ret = 0, i; @@ -293,11 +283,9 @@ static int __init pxa95x_init(void) if ((ret = pxa_init_dma(IRQ_DMA, 32))) return ret; - for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) { - ret = sysdev_register(&pxa95x_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa3xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 47094188e02..d130f77b6d1 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -18,7 +18,6 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <linux/sysdev.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/gpio.h> @@ -597,7 +596,7 @@ static void __init raumfeld_lcd_init(void) { int ret; - set_pxa_fb_info(&raumfeld_sharp_lcd_info); + pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info); /* Earlier devices had the backlight regulator controlled * via PWM, later versions use another controller for that */ diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index eb83c89428e..fee97a93512 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -473,7 +473,7 @@ static struct pxafb_mach_info saar_lcd_info = { static void __init saar_init_lcd(void) { - set_pxa_fb_info(&saar_lcd_info); + pxa_set_fb_info(NULL, &saar_lcd_info); } #else static inline void saar_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index 232b7316ec0..79923058d10 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -6,7 +6,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <mach/smemc.h> @@ -16,7 +16,7 @@ static unsigned long msc[2]; static unsigned long sxcnfg, memclkcfg; static unsigned long csadrcfg[4]; -static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) +static int pxa3xx_smemc_suspend(void) { msc[0] = __raw_readl(MSC0); msc[1] = __raw_readl(MSC1); @@ -30,7 +30,7 @@ static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int pxa3xx_smemc_resume(struct sys_device *dev) +static void pxa3xx_smemc_resume(void) { __raw_writel(msc[0], MSC0); __raw_writel(msc[1], MSC1); @@ -40,34 +40,19 @@ static int pxa3xx_smemc_resume(struct sys_device *dev) __raw_writel(csadrcfg[1], CSADRCFG1); __raw_writel(csadrcfg[2], CSADRCFG2); __raw_writel(csadrcfg[3], CSADRCFG3); - - return 0; } -static struct sysdev_class smemc_sysclass = { - .name = "smemc", +static struct syscore_ops smemc_syscore_ops = { .suspend = pxa3xx_smemc_suspend, .resume = pxa3xx_smemc_resume, }; -static struct sys_device smemc_sysdev = { - .id = 0, - .cls = &smemc_sysclass, -}; - static int __init smemc_init(void) { - int ret = 0; + if (cpu_is_pxa3xx()) + register_syscore_ops(&smemc_syscore_ops); - if (cpu_is_pxa3xx()) { - ret = sysdev_class_register(&smemc_sysclass); - if (ret) - return ret; - - ret = sysdev_register(&smemc_sysdev); - } - - return ret; + return 0; } subsys_initcall(smemc_init); #endif diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 38e2c0912b9..01c576963e9 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -724,7 +724,7 @@ static struct pxafb_mach_info spitz_pxafb_info = { static void __init spitz_lcd_init(void) { - set_pxa_fb_info(&spitz_pxafb_info); + pxa_set_fb_info(NULL, &spitz_pxafb_info); } #else static inline void spitz_lcd_init(void) {} diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 9cecf8366db..53d4a472b69 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -466,7 +466,7 @@ static void __init tavorevb_init_lcd(void) { platform_device_register(&tavorevb_backlight_devices[0]); platform_device_register(&tavorevb_backlight_devices[1]); - set_pxa_fb_info(&tavorevb_lcd_info); + pxa_set_fb_info(NULL, &tavorevb_lcd_info); } #else static inline void tavorevb_init_lcd(void) {} diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index e7f64d9b4f2..de684701449 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -100,25 +100,11 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) static struct clock_event_device ckevt_pxa_osmr0 = { .name = "osmr0", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_next_event = pxa_osmr0_set_next_event, .set_mode = pxa_osmr0_set_mode, }; -static cycle_t pxa_read_oscr(struct clocksource *cs) -{ - return OSCR; -} - -static struct clocksource cksrc_pxa_oscr0 = { - .name = "oscr0", - .rating = 200, - .read = pxa_read_oscr, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static struct irqaction pxa_ost0_irq = { .name = "ost0", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, @@ -135,8 +121,7 @@ static void __init pxa_timer_init(void) init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); - ckevt_pxa_osmr0.mult = - div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); + clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); ckevt_pxa_osmr0.min_delta_ns = @@ -145,7 +130,8 @@ static void __init pxa_timer_init(void) setup_irq(IRQ_OST0, &pxa_ost0_irq); - clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate); + clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32, + clocksource_mmio_readl_up); clockevents_register_device(&ckevt_pxa_osmr0); } diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 5ad3807af33..5fa145778e7 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -35,6 +35,7 @@ #include <linux/spi/pxa2xx_spi.h> #include <linux/input/matrix_keypad.h> #include <linux/i2c/pxa-i2c.h> +#include <linux/usb/gpio_vbus.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -240,12 +241,20 @@ static struct scoop_pcmcia_config tosa_pcmcia_config = { /* * USB Device Controller */ -static struct pxa2xx_udc_mach_info udc_info __initdata = { +static struct gpio_vbus_mach_info tosa_udc_info = { .gpio_pullup = TOSA_GPIO_USB_PULLUP, .gpio_vbus = TOSA_GPIO_USB_IN, .gpio_vbus_inverted = 1, }; +static struct platform_device tosa_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &tosa_udc_info, + }, +}; + /* * MMC/SD Device */ @@ -891,6 +900,7 @@ static struct platform_device *devices[] __initdata = { &tosa_bt_device, &sharpsl_rom_device, &wm9712_device, + &tosa_gpio_vbus, }; static void tosa_poweroff(void) @@ -937,7 +947,6 @@ static void __init tosa_init(void) dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); pxa_set_mci_info(&tosa_mci_platform_data); - pxa_set_udc_info(&udc_info); pxa_set_ficp_info(&tosa_ficp_platform_data); pxa_set_i2c_info(NULL); pxa_set_ac97_info(NULL); diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 857bb2e6348..687417a9369 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> @@ -516,9 +515,9 @@ static void __init trizeps4_init(void) pxa_set_stuart_info(NULL); if (0) /* dont know how to determine LCD */ - set_pxa_fb_info(&sharp_lcd); + pxa_set_fb_info(NULL, &sharp_lcd); else - set_pxa_fb_info(&toshiba_lcd); + pxa_set_fb_info(NULL, &toshiba_lcd); pxa_set_mci_info(&trizeps4_mci_platform_data); #ifndef STATUS_LEDS_ON_STUART_PINS diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 12279214c87..903218eab56 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -44,6 +44,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> +#include <linux/syscore_ops.h> #include <mach/pxa25x.h> #include <mach/audio.h> @@ -130,20 +131,19 @@ static u8 viper_hw_version(void) return v1; } -/* CPU sysdev */ -static int viper_cpu_suspend(struct sys_device *sysdev, pm_message_t state) +/* CPU system core operations. */ +static int viper_cpu_suspend(void) { viper_icr_set_bit(VIPER_ICR_R_DIS); return 0; } -static int viper_cpu_resume(struct sys_device *sysdev) +static void viper_cpu_resume(void) { viper_icr_clear_bit(VIPER_ICR_R_DIS); - return 0; } -static struct sysdev_driver viper_cpu_sysdev_driver = { +static struct syscore_ops viper_cpu_syscore_ops = { .suspend = viper_cpu_suspend, .resume = viper_cpu_resume, }; @@ -310,14 +310,14 @@ static void __init viper_init_irq(void) /* setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { isa_irq = viper_bit_to_irq(level); - set_irq_chip(isa_irq, &viper_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); + irq_set_chip_and_handler(isa_irq, &viper_irq_chip, + handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } - set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), + irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), viper_irq_handler); - set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); } /* Flat Panel */ @@ -932,7 +932,7 @@ static void __init viper_init(void) /* Wake-up serial console */ viper_init_serial_gpio(); - set_pxa_fb_info(&fb_info); + pxa_set_fb_info(NULL, &fb_info); /* v1 hardware cannot use the datacs line */ version = viper_hw_version(); @@ -945,7 +945,7 @@ static void __init viper_init(void) viper_init_vcore_gpios(); viper_init_cpufreq(); - sysdev_driver_register(&cpu_sysdev_class, &viper_cpu_sysdev_driver); + register_syscore_ops(&viper_cpu_syscore_ops); if (version) { pr_info("viper: hardware v%di%d detected. " diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index e709fd45926..67bd41488bf 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -16,7 +16,6 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> -#include <linux/sysdev.h> #include <linux/usb/gpio_vbus.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> @@ -572,7 +571,7 @@ static void __init vpac270_lcd_init(void) } vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power; - set_pxa_fb_info(&vpac270_lcd_screen); + pxa_set_fb_info(NULL, &vpac270_lcd_screen); return; err2: diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index aaf883754ef..fbe9e02e2f9 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -91,13 +91,13 @@ static unsigned long z2_pin_config[] = { GPIO47_STUART_TXD, /* Keypad */ - GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, - GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, - GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, - GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, - GPIO38_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, - GPIO16_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, - GPIO17_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH, + GPIO100_KP_MKIN_0, + GPIO101_KP_MKIN_1, + GPIO102_KP_MKIN_2, + GPIO34_KP_MKIN_3, + GPIO38_KP_MKIN_4, + GPIO16_KP_MKIN_5, + GPIO17_KP_MKIN_6, GPIO103_KP_MKOUT_0, GPIO104_KP_MKOUT_1, GPIO105_KP_MKOUT_2, @@ -138,8 +138,7 @@ static unsigned long z2_pin_config[] = { GPIO1_GPIO, /* Power button */ GPIO37_GPIO, /* Headphone detect */ GPIO98_GPIO, /* Lid switch */ - GPIO14_GPIO, /* WiFi Reset */ - GPIO15_GPIO, /* WiFi Power */ + GPIO14_GPIO, /* WiFi Power */ GPIO24_GPIO, /* WiFi CS */ GPIO36_GPIO, /* WiFi IRQ */ GPIO88_GPIO, /* LCD CS */ @@ -204,7 +203,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { /* Keypad Backlight */ .pwm_id = 1, .max_brightness = 1023, - .dft_brightness = 512, + .dft_brightness = 0, .pwm_period_ns = 1260320, }, [1] = { @@ -271,7 +270,7 @@ static struct pxafb_mach_info z2_lcd_screen = { static void __init z2_lcd_init(void) { - set_pxa_fb_info(&z2_lcd_screen); + pxa_set_fb_info(NULL, &z2_lcd_screen); } #else static inline void z2_lcd_init(void) {} @@ -309,12 +308,12 @@ struct gpio_led z2_gpio_leds[] = { .active_low = 1, }, { .name = "z2:green:charged", - .default_trigger = "none", + .default_trigger = "mmc0", .gpio = GPIO85_ZIPITZ2_LED_CHARGED, .active_low = 1, }, { .name = "z2:amber:charging", - .default_trigger = "none", + .default_trigger = "Z2-charging-or-full", .gpio = GPIO83_ZIPITZ2_LED_CHARGING, .active_low = 1, }, @@ -427,8 +426,22 @@ static inline void z2_mkp_init(void) {} ******************************************************************************/ #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button z2_pxa_buttons[] = { - {KEY_POWER, GPIO1_ZIPITZ2_POWER_BUTTON, 0, "Power Button" }, - {KEY_CLOSE, GPIO98_ZIPITZ2_LID_BUTTON, 0, "Lid Button" }, + { + .code = KEY_POWER, + .gpio = GPIO1_ZIPITZ2_POWER_BUTTON, + .active_low = 0, + .desc = "Power Button", + .wakeup = 1, + .type = EV_KEY, + }, + { + .code = SW_LID, + .gpio = GPIO98_ZIPITZ2_LID_BUTTON, + .active_low = 1, + .desc = "Lid Switch", + .wakeup = 0, + .type = EV_SW, + }, }; static struct gpio_keys_platform_data z2_pxa_keys_data = { @@ -461,9 +474,9 @@ static struct z2_battery_info batt_chip_info = { .batt_I2C_addr = 0x55, .batt_I2C_reg = 2, .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT, - .min_voltage = 2400000, - .max_voltage = 3700000, - .batt_div = 69, + .min_voltage = 3475000, + .max_voltage = 4190000, + .batt_div = 59, .batt_mult = 1000000, .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, .batt_name = "Z2", @@ -497,26 +510,16 @@ static int z2_lbs_spi_setup(struct spi_device *spi) { int ret = 0; - ret = gpio_request(GPIO15_ZIPITZ2_WIFI_POWER, "WiFi Power"); + ret = gpio_request(GPIO14_ZIPITZ2_WIFI_POWER, "WiFi Power"); if (ret) goto err; - ret = gpio_direction_output(GPIO15_ZIPITZ2_WIFI_POWER, 1); + ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_POWER, 1); if (ret) goto err2; - ret = gpio_request(GPIO14_ZIPITZ2_WIFI_RESET, "WiFi Reset"); - if (ret) - goto err2; - - ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_RESET, 0); - if (ret) - goto err3; - - /* Reset the card */ + /* Wait until card is powered on */ mdelay(180); - gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 1); - mdelay(20); spi->bits_per_word = 16; spi->mode = SPI_MODE_2, @@ -525,22 +528,18 @@ static int z2_lbs_spi_setup(struct spi_device *spi) return 0; -err3: - gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); err2: - gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); + gpio_free(GPIO14_ZIPITZ2_WIFI_POWER); err: return ret; }; static int z2_lbs_spi_teardown(struct spi_device *spi) { - gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 0); - gpio_set_value(GPIO15_ZIPITZ2_WIFI_POWER, 0); - gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); - gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); - return 0; + gpio_set_value(GPIO14_ZIPITZ2_WIFI_POWER, 0); + gpio_free(GPIO14_ZIPITZ2_WIFI_POWER); + return 0; }; static struct pxa2xx_spi_chip z2_lbs_chip_info = { diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 730f51e57c1..00363c7ac18 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -136,22 +136,23 @@ static void __init zeus_init_irq(void) /* Peripheral IRQs. It would be nice to move those inside driver configuration, but it is not supported at the moment. */ - set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); - set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), + IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); /* Setup ISA IRQs */ for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { isa_irq = zeus_bit_to_irq(level); - set_irq_chip(isa_irq, &zeus_irq_chip); - set_irq_handler(isa_irq, handle_edge_irq); + irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, + handle_edge_irq); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); } - set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); + irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); } @@ -846,7 +847,7 @@ static void __init zeus_init(void) if (zeus_setup_fb_gpios()) pr_err("Failed to setup fb gpios\n"); else - set_pxa_fb_info(&zeus_fb_info); + pxa_set_fb_info(NULL, &zeus_fb_info); pxa_set_mci_info(&zeus_mci_platform_data); pxa_set_udc_info(&zeus_udc_info); diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index a4c784aab76..5821185f77a 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -208,7 +208,7 @@ static void __init zylonite_init_lcd(void) platform_device_register(&zylonite_backlight_device); if (lcd_id & 0x20) { - set_pxa_fb_info(&zylonite_sharp_lcd_info); + pxa_set_fb_info(NULL, &zylonite_sharp_lcd_info); return; } @@ -220,7 +220,7 @@ static void __init zylonite_init_lcd(void) else zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; - set_pxa_fb_info(&zylonite_toshiba_lcd_info); + pxa_set_fb_info(NULL, &zylonite_toshiba_lcd_info); } #else static inline void zylonite_init_lcd(void) {} diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 75dbc8791d0..5c23450d2d1 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -31,6 +31,7 @@ #include <linux/amba/mmci.h> #include <linux/gfp.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <asm/system.h> #include <mach/hardware.h> @@ -41,7 +42,6 @@ #include <asm/hardware/icst.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> @@ -56,48 +56,9 @@ #include "core.h" -#ifdef CONFIG_ZONE_DMA -/* - * Adjust the zones if there are restrictions for DMA access. - */ -void __init realview_adjust_zones(unsigned long *size, unsigned long *hole) -{ - unsigned long dma_size = SZ_256M >> PAGE_SHIFT; - - if (!machine_is_realview_pbx() || size[0] <= dma_size) - return; - - size[ZONE_NORMAL] = size[0] - dma_size; - size[ZONE_DMA] = dma_size; - hole[ZONE_NORMAL] = hole[0]; - hole[ZONE_DMA] = 0; -} -#endif - - #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) -static int realview_flash_init(void) -{ - u32 val; - - val = __raw_readl(REALVIEW_FLASHCTRL); - val &= ~REALVIEW_FLASHPROG_FLVPPEN; - __raw_writel(val, REALVIEW_FLASHCTRL); - - return 0; -} - -static void realview_flash_exit(void) -{ - u32 val; - - val = __raw_readl(REALVIEW_FLASHCTRL); - val &= ~REALVIEW_FLASHPROG_FLVPPEN; - __raw_writel(val, REALVIEW_FLASHCTRL); -} - -static void realview_flash_set_vpp(int on) +static void realview_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; @@ -109,16 +70,13 @@ static void realview_flash_set_vpp(int on) __raw_writel(val, REALVIEW_FLASHCTRL); } -static struct flash_platform_data realview_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data realview_flash_data = { .width = 4, - .init = realview_flash_init, - .exit = realview_flash_exit, .set_vpp = realview_flash_set_vpp, }; struct platform_device realview_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &realview_flash_data, @@ -315,6 +273,10 @@ static struct clk ref24_clk = { .rate = 24000000, }; +static struct clk sp804_clk = { + .rate = 1000000, +}; + static struct clk dummy_apb_pclk; static struct clk_lookup lookups[] = { @@ -357,7 +319,10 @@ static struct clk_lookup lookups[] = { }, { /* SSP */ .dev_id = "dev:ssp0", .clk = &ref24_clk, - } + }, { /* SP804 timers */ + .dev_id = "sp804", + .clk = &sp804_clk, + }, }; void __init realview_init_early(void) @@ -545,8 +510,8 @@ void __init realview_timer_init(unsigned int timer_irq) writel(0, timer2_va_base + TIMER_CTRL); writel(0, timer3_va_base + TIMER_CTRL); - sp804_clocksource_init(timer3_va_base); - sp804_clockevents_init(timer0_va_base, timer_irq); + sp804_clocksource_init(timer3_va_base, "timer3"); + sp804_clockevents_init(timer0_va_base, timer_irq, "timer0"); } /* diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h index 0c5d749d7b5..9a732195aa1 100644 --- a/arch/arm/mach-realview/include/mach/barriers.h +++ b/arch/arm/mach-realview/include/mach/barriers.h @@ -4,5 +4,5 @@ * operation to deadlock the system. */ #define mb() dsb() -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index e05fc2c4c08..1759fa673ee 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -29,13 +29,8 @@ #define PLAT_PHYS_OFFSET UL(0x00000000) #endif -#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) -extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); -#define arch_adjust_zones(size, hole) \ - realview_adjust_zones(size, hole) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#ifdef CONFIG_ZONE_DMA +#define ARM_DMA_ZONE_SIZE SZ_256M #endif #ifdef CONFIG_SPARSEMEM diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h deleted file mode 100644 index c8221b38ee7..00000000000 --- a/arch/arm/mach-realview/include/mach/smp.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 23919229e12..963bf0d8119 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -14,6 +14,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> #include <asm/unified.h> @@ -61,6 +62,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 2ecc1d94284..10e75faba4c 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -348,7 +348,7 @@ static void __init gic_init_irq(void) #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ - gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), + gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE), __io_address(REALVIEW_EB_GIC_CPU_BASE)); gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h index 8c9e2c7161c..9cd9bcdad6c 100644 --- a/arch/arm/mach-rpc/include/mach/uncompress.h +++ b/arch/arm/mach-rpc/include/mach/uncompress.h @@ -66,12 +66,12 @@ extern __attribute__((pure)) struct param_struct *params(void); #define params (params()) #ifndef STANDALONE_DEBUG -static unsigned long video_num_cols; -static unsigned long video_num_rows; -static unsigned long video_x; -static unsigned long video_y; -static unsigned char bytes_per_char_v; -static int white; +unsigned long video_num_cols; +unsigned long video_num_rows; +unsigned long video_x; +unsigned long video_y; +unsigned char bytes_per_char_v; +int white; /* * This does not append a newline diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index d29cd9b737f..2e1b5309fba 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -133,25 +133,25 @@ void __init rpc_init_irq(void) switch (irq) { case 0 ... 7: - set_irq_chip(irq, &iomd_a_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_a_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 8 ... 15: - set_irq_chip(irq, &iomd_b_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_b_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 16 ... 21: - set_irq_chip(irq, &iomd_dma_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &iomd_dma_chip, + handle_level_irq); set_irq_flags(irq, flags); break; case 64 ... 71: - set_irq_chip(irq, &iomd_fiq_chip); + irq_set_chip(irq, &iomd_fiq_chip); set_irq_flags(irq, IRQF_VALID); break; } diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 606cb6b1cc4..bc53d2d16d1 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c @@ -147,15 +147,15 @@ static __init int bast_irq_init(void) __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); - set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); + irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); /* register our IRQs */ for (i = 0; i < 4; i++) { unsigned int irqno = bast_pc104_irqs[i]; - set_irq_chip(irqno, &bast_pc104_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &bast_pc104_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index cf68136cc66..b2b2a5bb275 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -19,7 +19,7 @@ #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ /* We use `virtual` dma channels to hide the fact we have only a limited - * number of DMA channels, and not of all of them (dependant on the device) + * number of DMA channels, and not of all of them (dependent on the device) * can be attached to any DMA source. We therefore let the DMA core handle * the allocation of hardware channels to clients. */ diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 25bbf5a942d..425552d84b6 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -21,6 +21,10 @@ /* USB host controller */ #define S3C2410_PA_USBHOST (0x49000000) +/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */ +#define S3C2416_PA_HSUDC (0x49800000) +#define S3C2416_SZ_HSUDC (SZ_4K) + /* DMA controller */ #define S3C2410_PA_DMA (0x4B000000) #define S3C24XX_SZ_DMA SZ_1M diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h index 7f7c5294796..988a6863e54 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h @@ -101,7 +101,7 @@ #define S3C2410_BANKCON_PMC16 (0x03) /* bank configurations for banks 0..7, note banks - * 6 and 7 have differnt configurations depending on + * 6 and 7 have different configurations depending on * the memory type bits */ #define S3C2410_BANKCON_Tacp2 (0x0 << 2) diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h index 44494a56e68..5e06c726583 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h @@ -37,6 +37,10 @@ #define S3C2443_SYSID S3C2443_CLKREG(0x5C) #define S3C2443_PWRCFG S3C2443_CLKREG(0x60) #define S3C2443_RSTCON S3C2443_CLKREG(0x64) +#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80) +#define S3C2443_PHYPWR S3C2443_CLKREG(0x84) +#define S3C2443_URSTCON S3C2443_CLKREG(0x88) +#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) #define S3C2443_SWRST_RESET (0x533c2443) @@ -121,6 +125,27 @@ #define S3C2443_PWRCFG_SLEEP (1<<15) +#define S3C2443_PWRCFG_USBPHY (1 << 4) + +#define S3C2443_URSTCON_FUNCRST (1 << 2) +#define S3C2443_URSTCON_PHYRST (1 << 0) + +#define S3C2443_PHYCTRL_CLKSEL (1 << 3) +#define S3C2443_PHYCTRL_EXTCLK (1 << 2) +#define S3C2443_PHYCTRL_PLLSEL (1 << 1) +#define S3C2443_PHYCTRL_DSPORT (1 << 0) + +#define S3C2443_PHYPWR_COMMON_ON (1 << 31) +#define S3C2443_PHYPWR_ANALOG_PD (1 << 4) +#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3) +#define S3C2443_PHYPWR_XO_ON (1 << 2) +#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1) +#define S3C2443_PHYPWR_FSUSPEND (1 << 0) + +#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31) +#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2) +#define S3C2443_UCLKCON_TCLKEN (1 << 0) + #include <asm/div64.h> static inline unsigned int diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 5e2f3533205..2854129f8cc 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c @@ -23,38 +23,12 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <plat/cpu.h> #include <plat/pm.h> -static int s3c2410_irq_add(struct sys_device *sysdev) -{ - return 0; -} - -static struct sysdev_driver s3c2410_irq_driver = { - .add = s3c2410_irq_add, +struct syscore_ops s3c24xx_irq_syscore_ops = { .suspend = s3c24xx_irq_suspend, .resume = s3c24xx_irq_resume, }; - -static int __init s3c2410_irq_init(void) -{ - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); -} - -arch_initcall(s3c2410_irq_init); - -static struct sysdev_driver s3c2410a_irq_driver = { - .add = s3c2410_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - -static int __init s3c2410a_irq_init(void) -{ - return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver); -} - -arch_initcall(s3c2410a_irq_init); diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 2970ea9f7c2..1e2d536adda 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -17,7 +17,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/dm9000.h> @@ -214,17 +214,16 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { /* NAND Flash on BAST board */ #ifdef CONFIG_PM -static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) +static int bast_pm_suspend(void) { /* ensure that an nRESET is not generated on resume. */ gpio_direction_output(S3C2410_GPA(21), 1); return 0; } -static int bast_pm_resume(struct sys_device *sd) +static void bast_pm_resume(void) { s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); - return 0; } #else @@ -232,16 +231,11 @@ static int bast_pm_resume(struct sys_device *sd) #define bast_pm_resume NULL #endif -static struct sysdev_class bast_pm_sysclass = { - .name = "mach-bast", +static struct syscore_ops bast_pm_syscore_ops = { .suspend = bast_pm_suspend, .resume = bast_pm_resume, }; -static struct sys_device bast_pm_sysdev = { - .cls = &bast_pm_sysclass, -}; - static int smartmedia_map[] = { 0 }; static int chip0_map[] = { 1 }; static int chip1_map[] = { 2 }; @@ -642,8 +636,7 @@ static void __init bast_map_io(void) static void __init bast_init(void) { - sysdev_class_register(&bast_pm_sysclass); - sysdev_register(&bast_pm_sysdev); + register_syscore_ops(&bast_pm_syscore_ops); s3c_i2c0_set_platdata(&bast_i2c_info); s3c_nand_set_platdata(&bast_nand_info); diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 66f44440d5d..079dcaa602d 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -252,7 +252,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { .def_trigger = "", }; -/* This is the blue LED on the device. Originaly used to indicate GPS activity +/* This is the blue LED on the device. Originally used to indicate GPS activity * by flashing. */ static struct s3c24xx_led_platdata n35_blue_led_pdata = { .name = "blue_led", diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c index 598d130633d..ad9f750f1e5 100644 --- a/arch/arm/mach-s3c2410/nor-simtec.c +++ b/arch/arm/mach-s3c2410/nor-simtec.c @@ -32,7 +32,7 @@ #include "nor-simtec.h" -static void simtec_nor_vpp(struct map_info *map, int vpp) +static void simtec_nor_vpp(struct platform_device *pdev, int vpp) { unsigned int val; unsigned long flags; diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 725636fc4dc..4728f9aa7df 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -25,6 +25,7 @@ #include <linux/errno.h> #include <linux/time.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/gpio.h> #include <linux/io.h> @@ -92,7 +93,7 @@ static void s3c2410_pm_prepare(void) } } -static int s3c2410_pm_resume(struct sys_device *dev) +static void s3c2410_pm_resume(void) { unsigned long tmp; @@ -104,10 +105,12 @@ static int s3c2410_pm_resume(struct sys_device *dev) if ( machine_is_aml_m5900() ) s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - - return 0; } +struct syscore_ops s3c2410_pm_syscore_ops = { + .resume = s3c2410_pm_resume, +}; + static int s3c2410_pm_add(struct sys_device *dev) { pm_cpu_prep = s3c2410_pm_prepare; @@ -119,7 +122,6 @@ static int s3c2410_pm_add(struct sys_device *dev) #if defined(CONFIG_CPU_S3C2410) static struct sysdev_driver s3c2410_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; /* register ourselves */ @@ -133,7 +135,6 @@ arch_initcall(s3c2410_pm_drvinit); static struct sysdev_driver s3c2410a_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; static int __init s3c2410a_pm_drvinit(void) @@ -147,7 +148,6 @@ arch_initcall(s3c2410a_pm_drvinit); #if defined(CONFIG_CPU_S3C2440) static struct sysdev_driver s3c2440_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; static int __init s3c2440_pm_drvinit(void) @@ -161,7 +161,6 @@ arch_initcall(s3c2440_pm_drvinit); #if defined(CONFIG_CPU_S3C2442) static struct sysdev_driver s3c2442_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; static int __init s3c2442_pm_drvinit(void) diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index adc90a3c589..f1d3bd8f6f1 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/clk.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -40,6 +41,7 @@ #include <plat/devs.h> #include <plat/clock.h> #include <plat/pll.h> +#include <plat/pm.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -168,6 +170,9 @@ int __init s3c2410_init(void) { printk("S3C2410: Initialising architecture\n"); + register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2410_sysdev); } diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index eddb52ba5b6..1a1aa220972 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev) unsigned int irqno; for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_eint0t4); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } /* add demux support for CF/SDI */ - set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { - set_irq_chip(irqno, &s3c2412_irq_cfsdi); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } @@ -195,15 +195,13 @@ static int s3c2412_irq_add(struct sys_device *sysdev) s3c2412_irq_rtc_chip = s3c_irq_chip; s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; - set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); + irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); return 0; } static struct sysdev_driver s3c2412_irq_driver = { .add = s3c2412_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; static int s3c2412_irq_init(void) diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 923e01bdf01..85dcaeb9e62 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -17,7 +17,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/i2c.h> @@ -486,7 +486,7 @@ static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { /* Jive power management device */ #ifdef CONFIG_PM -static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) +static int jive_pm_suspend(void) { /* Write the magic value u-boot uses to check for resume into * the INFORM0 register, and ensure INFORM1 is set to the @@ -498,10 +498,9 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) return 0; } -static int jive_pm_resume(struct sys_device *sd) +static void jive_pm_resume(void) { __raw_writel(0x0, S3C2412_INFORM0); - return 0; } #else @@ -509,16 +508,11 @@ static int jive_pm_resume(struct sys_device *sd) #define jive_pm_resume NULL #endif -static struct sysdev_class jive_pm_sysclass = { - .name = "jive-pm", +static struct syscore_ops jive_pm_syscore_ops = { .suspend = jive_pm_suspend, .resume = jive_pm_resume, }; -static struct sys_device jive_pm_sysdev = { - .cls = &jive_pm_sysclass, -}; - static void __init jive_map_io(void) { s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); @@ -536,10 +530,9 @@ static void jive_power_off(void) static void __init jive_machine_init(void) { - /* register system devices for managing low level suspend */ + /* register system core operations for managing low level suspend */ - sysdev_class_register(&jive_pm_sysclass); - sysdev_register(&jive_pm_sysdev); + register_syscore_ops(&jive_pm_syscore_ops); /* write our sleep configurations for the IO. Pull down all unused * IO, ensure that we have turned off all peripherals we do not diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index a7417c479ff..752b13a7b3d 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c @@ -17,6 +17,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -86,13 +87,24 @@ static struct sleep_save s3c2412_sleep[] = { SAVE_ITEM(S3C2413_GPJSLPCON), }; -static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) +static struct sysdev_driver s3c2412_pm_driver = { + .add = s3c2412_pm_add, +}; + +static __init int s3c2412_pm_init(void) +{ + return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); +} + +arch_initcall(s3c2412_pm_init); + +static int s3c2412_pm_suspend(void) { s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); return 0; } -static int s3c2412_pm_resume(struct sys_device *dev) +static void s3c2412_pm_resume(void) { unsigned long tmp; @@ -102,18 +114,9 @@ static int s3c2412_pm_resume(struct sys_device *dev) __raw_writel(tmp, S3C2412_PWRCFG); s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); - return 0; } -static struct sysdev_driver s3c2412_pm_driver = { - .add = s3c2412_pm_add, +struct syscore_ops s3c2412_pm_syscore_ops = { .suspend = s3c2412_pm_suspend, .resume = s3c2412_pm_resume, }; - -static __init int s3c2412_pm_init(void) -{ - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); -} - -arch_initcall(s3c2412_pm_init); diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 4c6df51ddf3..ef0958d3e5c 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -19,6 +19,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -244,5 +245,8 @@ int __init s3c2412_init(void) { printk("S3C2412: Initialising architecture\n"); + register_syscore_ops(&s3c2412_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2412_sysdev); } diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 680fe386aca..28ad20d4244 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c @@ -202,13 +202,11 @@ static int __init s3c2416_add_sub(unsigned int base, { unsigned int irqno; - set_irq_chip(base, &s3c_irq_level_chip); - set_irq_handler(base, handle_level_irq); - set_irq_chained_handler(base, demux); + irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); + irq_set_chained_handler(base, demux); for (irqno = start; irqno <= end; irqno++) { - set_irq_chip(irqno, chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, chip, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } @@ -238,8 +236,6 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev) static struct sysdev_driver s3c2416_irq_driver = { .add = s3c2416_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; static int __init s3c2416_irq_init(void) diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c index 3f83177246c..ac27ebb31c9 100644 --- a/arch/arm/mach-s3c2416/mach-smdk2416.c +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c @@ -23,6 +23,7 @@ #include <linux/mtd/partitions.h> #include <linux/gpio.h> #include <linux/fb.h> +#include <linux/delay.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -35,6 +36,7 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> +#include <mach/regs-s3c2443-clock.h> #include <mach/idle.h> #include <mach/leds-gpio.h> @@ -47,6 +49,7 @@ #include <plat/cpu.h> #include <plat/nand.h> #include <plat/sdhci.h> +#include <plat/udc.h> #include <plat/regs-fb-v4.h> #include <plat/fb.h> @@ -121,6 +124,27 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = { } }; +void smdk2416_hsudc_gpio_init(void) +{ + s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(1)); + s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0); +} + +void smdk2416_hsudc_gpio_uninit(void) +{ + s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1); + s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0)); +} + +struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = { + .epnum = 9, + .gpio_init = smdk2416_hsudc_gpio_init, + .gpio_uninit = smdk2416_hsudc_gpio_uninit, +}; + struct s3c_fb_pd_win smdk2416_fb_win[] = { [0] = { /* think this is the same as the smdk6410 */ @@ -186,6 +210,7 @@ static struct platform_device *smdk2416_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_hsmmc0, &s3c_device_hsmmc1, + &s3c_device_usb_hsudc, }; static void __init smdk2416_map_io(void) @@ -203,6 +228,8 @@ static void __init smdk2416_machine_init(void) s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata); s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata); + s3c24xx_hsudc_set_platdata(&smdk2416_hsudc_platdata); + gpio_request(S3C2410_GPB(4), "USBHost Power"); gpio_direction_output(S3C2410_GPB(4), 1); diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c index 4a04205b04d..41db2b21e21 100644 --- a/arch/arm/mach-s3c2416/pm.c +++ b/arch/arm/mach-s3c2416/pm.c @@ -11,6 +11,7 @@ */ #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <asm/cacheflush.h> @@ -55,30 +56,26 @@ static int s3c2416_pm_add(struct sys_device *sysdev) return 0; } -static int s3c2416_pm_suspend(struct sys_device *dev, pm_message_t state) +static struct sysdev_driver s3c2416_pm_driver = { + .add = s3c2416_pm_add, +}; + +static __init int s3c2416_pm_init(void) { - return 0; + return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver); } -static int s3c2416_pm_resume(struct sys_device *dev) +arch_initcall(s3c2416_pm_init); + + +static void s3c2416_pm_resume(void) { /* unset the return-from-sleep amd inform flags */ __raw_writel(0x0, S3C2443_PWRMODE); __raw_writel(0x0, S3C2412_INFORM0); __raw_writel(0x0, S3C2412_INFORM1); - - return 0; } -static struct sysdev_driver s3c2416_pm_driver = { - .add = s3c2416_pm_add, - .suspend = s3c2416_pm_suspend, +struct syscore_ops s3c2416_pm_syscore_ops = { .resume = s3c2416_pm_resume, }; - -static __init int s3c2416_pm_init(void) -{ - return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver); -} - -arch_initcall(s3c2416_pm_init); diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index ba7fd873743..494ce913dc9 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -32,6 +32,7 @@ #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> @@ -54,6 +55,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/sdhci.h> +#include <plat/pm.h> #include <plat/iic-core.h> #include <plat/fb-core.h> @@ -95,6 +97,9 @@ int __init s3c2416_init(void) s3c_fb_setname("s3c2443-fb"); + register_syscore_ops(&s3c2416_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2416_sysdev); } diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index acad4428bef..eb1cc0f0705 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c @@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev) /* add new chained handler for wdt, ac7 */ - set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); - set_irq_handler(IRQ_WDT, handle_level_irq); - set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { - set_irq_chip(irqno, &s3c_irq_wdtac97); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c index 0db2411ef4b..716662008ce 100644 --- a/arch/arm/mach-s3c2440/mach-gta02.c +++ b/arch/arm/mach-s3c2440/mach-gta02.c @@ -409,6 +409,10 @@ struct platform_device s3c24xx_pwm_device = { .num_resources = 0, }; +static struct platform_device gta02_dfbmcs320_device = { + .name = "dfbmcs320", +}; + static struct i2c_board_info gta02_i2c_devs[] __initdata = { { I2C_BOARD_INFO("pcf50633", 0x73), @@ -523,6 +527,7 @@ static struct platform_device *gta02_devices[] __initdata = { &s3c_device_iis, &samsung_asoc_dma, &s3c_device_i2c0, + >a02_dfbmcs320_device, >a02_buttons_device, &s3c_device_adc, &s3c_device_ts, diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index dfedc9c9e00..dd3120df09f 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -155,7 +155,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { * the same timings, however, anything smaller than 1024x768 * will only be displayed in the top left corner of a 1024x768 * XGA output unless you add optional dip switches to the shield. - * Therefore timings for other resolutions have been ommited here. + * Therefore timings for other resolutions have been omitted here. */ [2] = { _LCD_DECLARE( diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 14dc6789775..d8853639331 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -17,7 +17,7 @@ #include <linux/init.h> #include <linux/gpio.h> #include <linux/device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/clk.h> #include <linux/i2c.h> @@ -284,7 +284,7 @@ static struct platform_device osiris_pcmcia = { #ifdef CONFIG_PM static unsigned char pm_osiris_ctrl0; -static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) +static int osiris_pm_suspend(void) { unsigned int tmp; @@ -304,7 +304,7 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) return 0; } -static int osiris_pm_resume(struct sys_device *sd) +static void osiris_pm_resume(void) { if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8) __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1); @@ -312,8 +312,6 @@ static int osiris_pm_resume(struct sys_device *sd) __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); - - return 0; } #else @@ -321,16 +319,11 @@ static int osiris_pm_resume(struct sys_device *sd) #define osiris_pm_resume NULL #endif -static struct sysdev_class osiris_pm_sysclass = { - .name = "mach-osiris", +static struct syscore_ops osiris_pm_syscore_ops = { .suspend = osiris_pm_suspend, .resume = osiris_pm_resume, }; -static struct sys_device osiris_pm_sysdev = { - .cls = &osiris_pm_sysclass, -}; - /* Link for DVS driver to TPS65011 */ static void osiris_tps_release(struct device *dev) @@ -439,8 +432,7 @@ static void __init osiris_map_io(void) static void __init osiris_init(void) { - sysdev_class_register(&osiris_pm_sysclass); - sysdev_register(&osiris_pm_sysdev); + register_syscore_ops(&osiris_pm_syscore_ops); s3c_i2c0_set_platdata(NULL); s3c_nand_set_platdata(&osiris_nand_info); diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index f7663f731ea..ce99ff72838 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/gpio.h> #include <linux/clk.h> #include <linux/io.h> @@ -33,6 +34,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/s3c244x.h> +#include <plat/pm.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -51,6 +53,12 @@ int __init s3c2440_init(void) s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT; + /* register suspend/resume handlers */ + + register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c244x_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + /* register our system device for everything else */ return sysdev_register(&s3c2440_sysdev); diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index ecf81354655..6224bad4d60 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c @@ -29,6 +29,7 @@ #include <linux/err.h> #include <linux/device.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/mutex.h> @@ -45,6 +46,7 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/s3c244x.h> +#include <plat/pm.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -167,6 +169,10 @@ int __init s3c2442_init(void) { printk("S3C2442: Initialising architecture\n"); + register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c244x_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2442_sysdev); } diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index 83daf4ece76..c63e8f26d90 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev) { unsigned int irqno; - set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); - set_irq_handler(IRQ_NFCON, handle_level_irq); + irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, + handle_level_irq); set_irq_flags(IRQ_NFCON, IRQF_VALID); /* add chained handler for camera */ - set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); - set_irq_handler(IRQ_CAM, handle_level_irq); - set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); + irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { - set_irq_chip(irqno, &s3c_irq_cam); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_cam, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } @@ -116,8 +116,6 @@ static int s3c244x_irq_add(struct sys_device *sysdev) static struct sysdev_driver s3c2440_irq_driver = { .add = s3c244x_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; static int s3c2440_irq_init(void) @@ -129,8 +127,6 @@ arch_initcall(s3c2440_irq_init); static struct sysdev_driver s3c2442_irq_driver = { .add = s3c244x_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c index 90c1707b9c9..7e8a23d2098 100644 --- a/arch/arm/mach-s3c2440/s3c244x.c +++ b/arch/arm/mach-s3c2440/s3c244x.c @@ -19,6 +19,7 @@ #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> @@ -134,45 +135,14 @@ void __init s3c244x_init_clocks(int xtal) s3c2410_baseclk_add(); } -#ifdef CONFIG_PM - -static struct sleep_save s3c244x_sleep[] = { - SAVE_ITEM(S3C2440_DSC0), - SAVE_ITEM(S3C2440_DSC1), - SAVE_ITEM(S3C2440_GPJDAT), - SAVE_ITEM(S3C2440_GPJCON), - SAVE_ITEM(S3C2440_GPJUP) -}; - -static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) -{ - s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); - return 0; -} - -static int s3c244x_resume(struct sys_device *dev) -{ - s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); - return 0; -} - -#else -#define s3c244x_suspend NULL -#define s3c244x_resume NULL -#endif - /* Since the S3C2442 and S3C2440 share items, put both sysclasses here */ struct sysdev_class s3c2440_sysclass = { .name = "s3c2440-core", - .suspend = s3c244x_suspend, - .resume = s3c244x_resume }; struct sysdev_class s3c2442_sysclass = { .name = "s3c2442-core", - .suspend = s3c244x_suspend, - .resume = s3c244x_resume }; /* need to register class before we actually register the device, and @@ -194,3 +164,33 @@ static int __init s3c2442_core_init(void) } core_initcall(s3c2442_core_init); + + +#ifdef CONFIG_PM +static struct sleep_save s3c244x_sleep[] = { + SAVE_ITEM(S3C2440_DSC0), + SAVE_ITEM(S3C2440_DSC1), + SAVE_ITEM(S3C2440_GPJDAT), + SAVE_ITEM(S3C2440_GPJCON), + SAVE_ITEM(S3C2440_GPJUP) +}; + +static int s3c244x_suspend(void) +{ + s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); + return 0; +} + +static void s3c244x_resume(void) +{ + s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); +} +#else +#define s3c244x_suspend NULL +#define s3c244x_resume NULL +#endif + +struct syscore_ops s3c244x_pm_syscore_ops = { + .suspend = s3c244x_suspend, + .resume = s3c244x_resume, +}; diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index c7820f9c135..83ecb1173fb 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -230,13 +230,11 @@ static int __init s3c2443_add_sub(unsigned int base, { unsigned int irqno; - set_irq_chip(base, &s3c_irq_level_chip); - set_irq_handler(base, handle_level_irq); - set_irq_chained_handler(base, demux); + irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); + irq_set_chained_handler(base, demux); for (irqno = start; irqno <= end; irqno++) { - set_irq_chip(irqno, chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, chip, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index c35585cf8c4..b197171e7d0 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -315,7 +315,7 @@ int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) case S3C2410_DMAOP_FLUSH: return s3c64xx_dma_flush(chan); - /* belive PAUSE/RESUME are no-ops */ + /* believe PAUSE/RESUME are no-ops */ case S3C2410_DMAOP_PAUSE: case S3C2410_DMAOP_RESUME: case S3C2410_DMAOP_STARTED: diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 2ead8189da7..4d203be1f4c 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c @@ -197,16 +197,15 @@ static int __init s3c64xx_init_irq_eint(void) int irq; for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { - set_irq_chip(irq, &s3c_irq_eint); - set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); + irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); - set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); - set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); - set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); + irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); + irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); + irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); + irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); return 0; } diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c index da1bec64b9d..8bec61e242c 100644 --- a/arch/arm/mach-s3c64xx/irq-pm.c +++ b/arch/arm/mach-s3c64xx/irq-pm.c @@ -13,7 +13,7 @@ */ #include <linux/kernel.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/serial_core.h> #include <linux/irq.h> @@ -54,7 +54,7 @@ static struct irq_grp_save { static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; -static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) +static int s3c64xx_irq_pm_suspend(void) { struct irq_grp_save *grp = eint_grp_save; int i; @@ -75,7 +75,7 @@ static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int s3c64xx_irq_pm_resume(struct sys_device *dev) +static void s3c64xx_irq_pm_resume(void) { struct irq_grp_save *grp = eint_grp_save; int i; @@ -94,18 +94,18 @@ static int s3c64xx_irq_pm_resume(struct sys_device *dev) } S3C_PMDBG("%s: IRQ configuration restored\n", __func__); - return 0; } -static struct sysdev_driver s3c64xx_irq_driver = { +struct syscore_ops s3c64xx_irq_syscore_ops = { .suspend = s3c64xx_irq_pm_suspend, .resume = s3c64xx_irq_pm_resume, }; -static int __init s3c64xx_irq_pm_init(void) +static __init int s3c64xx_syscore_init(void) { - return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver); -} + register_syscore_ops(&s3c64xx_irq_syscore_ops); -arch_initcall(s3c64xx_irq_pm_init); + return 0; +} +core_initcall(s3c64xx_syscore_init); diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 67a145d440f..97660c8141a 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c @@ -58,12 +58,7 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); /* add the timer sub-irqs */ - - s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); - s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); - s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); - s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); - s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); + s3c_init_vic_timer_irq(5, IRQ_TIMER0); s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c index b8d02eb4cf3..a5c00952ea3 100644 --- a/arch/arm/mach-s5p64x0/cpu.c +++ b/arch/arm/mach-s5p64x0/cpu.c @@ -119,7 +119,7 @@ void __init s5p6450_map_io(void) s3c_adc_setname("s3c64xx-adc"); iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); - iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc)); + iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); } /* diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h index c65b229aab2..1608faf870f 100644 --- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h +++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h @@ -24,8 +24,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ /* uart setup */ -static unsigned int fifo_mask; -static unsigned int fifo_max; +unsigned int fifo_mask; +unsigned int fifo_max; /* forward declerations */ @@ -43,7 +43,7 @@ static void arch_detect_cpu(void); /* how many bytes we allow into the FIFO at a time in FIFO mode */ #define FIFO_MAX (14) -static unsigned long uart_base; +unsigned long uart_base; static __inline__ void get_uart_base(void) { diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h index 4be4cc9abf7..07aa4d6054f 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h @@ -29,7 +29,7 @@ #define WPALCON_H (0x19c) #define WPALCON_L (0x1a0) -/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but +/* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but * different for WPAL2-4 */ /* In WPALCON_L (aka WPALCON) */ diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c index f16946e456e..be25879bb2e 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ b/arch/arm/mach-s5pc100/setup-sdhci.c @@ -40,7 +40,7 @@ void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, { u32 ctrl2, ctrl3; - /* don't need to alter anything acording to card-type */ + /* don't need to alter anything according to card-type */ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index 1f4b595534c..a5a1e331f8e 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -18,7 +18,7 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq -/* Practically, GPIO banks upto MP03 are the configurable gpio banks */ +/* Practically, GPIO banks up to MP03 are the configurable gpio banks */ /* GPIO bank sizes */ #define S5PV210_GPIO_A0_NR (8) diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 26710b35ef8..b9f9ec33384 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -99,9 +99,9 @@ #define IRQ_TC IRQ_PENDN #define IRQ_KEYPAD S5P_IRQ_VIC2(25) #define IRQ_CG S5P_IRQ_VIC2(26) -#define IRQ_SEC S5P_IRQ_VIC2(27) -#define IRQ_SECRX S5P_IRQ_VIC2(28) -#define IRQ_SECTX S5P_IRQ_VIC2(29) +#define IRQ_SSS_INT S5P_IRQ_VIC2(27) +#define IRQ_SSS_HASH S5P_IRQ_VIC2(28) +#define IRQ_PCM2 S5P_IRQ_VIC2(29) #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index bc08ac42e7c..c6a9e86c2d5 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -44,7 +44,6 @@ #include <plat/keypad.h> #include <plat/pm.h> #include <plat/fb.h> -#include <plat/gpio-cfg.h> #include <plat/s5p-time.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 549d7924fd4..24febae3d4c 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/suspend.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <plat/cpu.h> @@ -140,7 +141,17 @@ static int s5pv210_pm_add(struct sys_device *sysdev) return 0; } -static int s5pv210_pm_resume(struct sys_device *dev) +static struct sysdev_driver s5pv210_pm_driver = { + .add = s5pv210_pm_add, +}; + +static __init int s5pv210_pm_drvinit(void) +{ + return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver); +} +arch_initcall(s5pv210_pm_drvinit); + +static void s5pv210_pm_resume(void) { u32 tmp; @@ -150,17 +161,15 @@ static int s5pv210_pm_resume(struct sys_device *dev) __raw_writel(tmp , S5P_OTHERS); s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); - - return 0; } -static struct sysdev_driver s5pv210_pm_driver = { - .add = s5pv210_pm_add, +static struct syscore_ops s5pv210_pm_syscore_ops = { .resume = s5pv210_pm_resume, }; -static __init int s5pv210_pm_drvinit(void) +static __init int s5pv210_pm_syscore_init(void) { - return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver); + register_syscore_ops(&s5pv210_pm_syscore_ops); + return 0; } -arch_initcall(s5pv210_pm_drvinit); +arch_initcall(s5pv210_pm_syscore_init); diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 746777d56df..3e3ac05bb7b 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -32,10 +32,10 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) switch (width) { case 8: - /* GPG1[3:6] special-funtion 3 */ + /* GPG1[3:6] special-function 3 */ s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3)); case 4: - /* GPG0[3:6] special-funtion 2 */ + /* GPG0[3:6] special-function 2 */ s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2)); default: break; diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index c32e202731c..a83b6c909f6 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -38,7 +38,7 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, { u32 ctrl2, ctrl3; - /* don't need to alter anything acording to card-type */ + /* don't need to alter anything according to card-type */ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index e697691eed2..41252d22e65 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile @@ -50,7 +50,7 @@ led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o # LEDs support obj-$(CONFIG_LEDS) += $(led-y) -# Miscelaneous functions +# Miscellaneous functions obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_SA1100_SSP) += ssp.o diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 98d780608c7..7f3da4b11ec 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = { static void __init cerf_init_irq(void) { sa1100_init_irq(); - set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); } static struct map_desc cerf_io_desc[] __initdata = { diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index 07d4e8ba371..aaa8acf76b7 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -68,7 +68,7 @@ * clock change in ROM and jump to that code from the kernel. The main * disadvantage is that the ROM has to be modified, which is not * possible on all SA-1100 platforms. Another disadvantage is that - * jumping to ROM makes clock switching unecessary complicated. + * jumping to ROM makes clock switching unnecessary complicated. * * The idea behind this driver is that the memory configuration can be * changed while running from DRAM (even with interrupts turned on!) diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h index 4f7ea012e1e..bae8296f5db 100644 --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h @@ -1794,7 +1794,7 @@ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) -#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_RUN 0x00000001 /* DMA running */ #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ #define DCSR_ERROR 0x00000004 /* DMA ERROR */ #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index a44da6a2916..cff31ee246b 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -14,18 +14,8 @@ */ #define PLAT_PHYS_OFFSET UL(0xc0000000) -#ifndef __ASSEMBLY__ - #ifdef CONFIG_SA1111 -void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - sa1111_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) - -#endif +#define ARM_DMA_ZONE_SIZE SZ_1M #endif /* diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3d85dfad9c1..dfbf824a69f 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -14,7 +14,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <asm/mach/irq.h> @@ -234,7 +234,7 @@ static struct sa1100irq_state { unsigned int iccr; } sa1100irq_state; -static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) +static int sa1100irq_suspend(void) { struct sa1100irq_state *st = &sa1100irq_state; @@ -264,7 +264,7 @@ static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int sa1100irq_resume(struct sys_device *dev) +static void sa1100irq_resume(void) { struct sa1100irq_state *st = &sa1100irq_state; @@ -277,24 +277,17 @@ static int sa1100irq_resume(struct sys_device *dev) ICMR = st->icmr; } - return 0; } -static struct sysdev_class sa1100irq_sysclass = { - .name = "sa11x0-irq", +static struct syscore_ops sa1100irq_syscore_ops = { .suspend = sa1100irq_suspend, .resume = sa1100irq_resume, }; -static struct sys_device sa1100irq_device = { - .id = 0, - .cls = &sa1100irq_sysclass, -}; - static int __init sa1100irq_init_devicefs(void) { - sysdev_class_register(&sa1100irq_sysclass); - return sysdev_register(&sa1100irq_device); + register_syscore_ops(&sa1100irq_syscore_ops); + return 0; } device_initcall(sa1100irq_init_devicefs); @@ -323,28 +316,28 @@ void __init sa1100_init_irq(void) ICCR = 1; for (irq = 0; irq <= 10; irq++) { - set_irq_chip(irq, &sa1100_low_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = 12; irq <= 31; irq++) { - set_irq_chip(irq, &sa1100_normal_chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &sa1100_normal_chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID); } for (irq = 32; irq <= 48; irq++) { - set_irq_chip(irq, &sa1100_high_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* * Install handler for GPIO 11-27 edge detect interrupts */ - set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); - set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); + irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); + irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); sa1100_init_gpio(); } diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c index 9d490c66891..f50b00bd18a 100644 --- a/arch/arm/mach-sa1100/jornada720_ssp.c +++ b/arch/arm/mach-sa1100/jornada720_ssp.c @@ -29,7 +29,7 @@ static unsigned long jornada_ssp_flags; /** * jornada_ssp_reverse - reverses input byte * - * we need to reverse all data we recieve from the mcu due to its physical location + * we need to reverse all data we receive from the mcu due to its physical location * returns : 01110111 -> 11101110 */ u8 inline jornada_ssp_reverse(u8 byte) @@ -179,7 +179,7 @@ static int __devinit jornada_ssp_probe(struct platform_device *dev) static int jornada_ssp_remove(struct platform_device *dev) { - /* Note that this doesnt actually remove the driver, since theres nothing to remove + /* Note that this doesn't actually remove the driver, since theres nothing to remove * It just makes sure everything is turned off */ GPSR = GPIO_GPIO25; ssp_exit(); diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 4aad01f7366..b4fa53a1427 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev) /* * Install handler for GPIO25. */ - set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); - set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); + irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); + irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); /* * We would set IRQ_GPIO25 to be a wake-up IRQ, but @@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev) * Setup other Neponset IRQs. SA1111 will be done by the * generic SA1111 code. */ - set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); + irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); - set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); + irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq); set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); /* diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index 42b80400c10..65161f2bea2 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -142,7 +142,7 @@ static void __init pleb_map_io(void) GPDR &= ~GPIO_ETH0_IRQ; - set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); + irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); } MACHINE_START(PLEB, "PLEB") diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index ae4f3d80416..fa6602491d5 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -92,25 +92,11 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) static struct clock_event_device ckevt_sa1100_osmr0 = { .name = "osmr0", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_next_event = sa1100_osmr0_set_next_event, .set_mode = sa1100_osmr0_set_mode, }; -static cycle_t sa1100_read_oscr(struct clocksource *s) -{ - return OSCR; -} - -static struct clocksource cksrc_sa1100_oscr = { - .name = "oscr", - .rating = 200, - .read = sa1100_read_oscr, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static struct irqaction sa1100_timer_irq = { .name = "ost0", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, @@ -120,14 +106,13 @@ static struct irqaction sa1100_timer_irq = { static void __init sa1100_timer_init(void) { - OIER = 0; /* disable any timer interrupts */ - OSSR = 0xf; /* clear status on all timers */ + OIER = 0; + OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32, 3686400, SC_MULT, SC_SHIFT); - ckevt_sa1100_osmr0.mult = - div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); + clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4); ckevt_sa1100_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); ckevt_sa1100_osmr0.min_delta_ns = @@ -136,7 +121,8 @@ static void __init sa1100_timer_init(void) setup_irq(IRQ_OST0, &sa1100_timer_irq); - clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE); + clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, + clocksource_mmio_readl_up); clockevents_register_device(&ckevt_sa1100_osmr0); } diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index 9afb1700000..4c0831f83b0 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -17,25 +17,7 @@ */ #define PLAT_PHYS_OFFSET UL(0x08000000) -#ifndef __ASSEMBLY__ - -static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size) -{ - /* Only the first 4 MB (=1024 Pages) are usable for DMA */ - /* See dev / -> .properties in OpenFirmware. */ - zone_size[1] = zone_size[0] - 1024; - zone_size[0] = 1024; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; -} - -#define arch_adjust_zones(size, holes) \ - __arch_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M) - -#endif +#define ARM_DMA_ZONE_SIZE SZ_4M /* * Cache flushing area diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c index 831fc66dfa4..5dce13e429f 100644 --- a/arch/arm/mach-shark/irq.c +++ b/arch/arm/mach-shark/irq.c @@ -80,8 +80,7 @@ void __init shark_init_irq(void) int irq; for (irq = 0; irq < NR_IRQS; irq++) { - set_irq_chip(irq, &fb_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index a94f29da5d3..1e35fa976d6 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -24,9 +24,9 @@ #include <linux/irq.h> #include <linux/platform_device.h> #include <linux/delay.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/mmc/host.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> @@ -312,7 +312,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0xe6850000, - .end = 0xe68501ff, + .end = 0xe68500ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -345,7 +345,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0xe6860000, - .end = 0xe68601ff, + .end = 0xe68600ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -947,7 +947,7 @@ static struct platform_device *ap4evb_devices[] __initdata = { &ap4evb_camera, }; -static int __init hdmi_init_pm_clock(void) +static void __init hdmi_init_pm_clock(void) { struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); int ret; @@ -988,20 +988,15 @@ static int __init hdmi_init_pm_clock(void) pr_debug("PLLC2 set frequency %lu\n", rate); ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); - if (ret < 0) { + if (ret < 0) pr_err("Cannot set HDMI parent: %d\n", ret); - goto out; - } out: if (!IS_ERR(hdmi_ick)) clk_put(hdmi_ick); - return ret; } -device_initcall(hdmi_init_pm_clock); - -static int __init fsi_init_pm_clock(void) +static void __init fsi_init_pm_clock(void) { struct clk *fsia_ick; int ret; @@ -1010,7 +1005,7 @@ static int __init fsi_init_pm_clock(void) if (IS_ERR(fsia_ick)) { ret = PTR_ERR(fsia_ick); pr_err("Cannot get FSI ICK: %d\n", ret); - return ret; + return; } ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk); @@ -1018,10 +1013,7 @@ static int __init fsi_init_pm_clock(void) pr_err("Cannot set FSI-A parent: %d\n", ret); clk_put(fsia_ick); - - return ret; } -device_initcall(fsi_init_pm_clock); /* * FIXME !! @@ -1255,7 +1247,7 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_KEYIN4, NULL); /* enable TouchScreen */ - set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ28; i2c_register_board_info(1, &tsc_device, 1); @@ -1311,7 +1303,7 @@ static void __init ap4evb_init(void) lcdc_info.ch[0].lcd_size_cfg.height = 91; /* enable TouchScreen */ - set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ7; i2c_register_board_info(0, &tsc_device, 1); @@ -1348,6 +1340,9 @@ static void __init ap4evb_init(void) __raw_writel(srcr4 & ~(1 << 13), SRCR4); platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); + + hdmi_init_pm_clock(); + fsi_init_pm_clock(); } static void __init ap4evb_timer_init(void) diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index dee3e9231fb..c87a7b7c583 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c @@ -31,7 +31,7 @@ #include <linux/input.h> #include <linux/input/sh_keysc.h> #include <linux/mmc/host.h> -#include <linux/mfd/sh_mobile_sdhi.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/gpio.h> #include <mach/sh7377.h> #include <mach/common.h> @@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0xe6d50000, - .end = 0xe6d501ff, + .end = 0xe6d50nff, .flags = IORESOURCE_MEM, }, [1] = { @@ -232,7 +232,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0xe6d60000, - .end = 0xe6d601ff, + .end = 0xe6d600ff, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 49bc0748217..7da2ca24229 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -32,10 +32,10 @@ #include <linux/io.h> #include <linux/i2c.h> #include <linux/leds.h> -#include <linux/mfd/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> @@ -423,7 +423,7 @@ static struct platform_device fsi_hdmi_device = { .name = "sh_fsi2_b_hdmi", }; -static int __init hdmi_init_pm_clock(void) +static void __init hdmi_init_pm_clock(void) { struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); int ret; @@ -467,17 +467,13 @@ static int __init hdmi_init_pm_clock(void) pr_debug("PLLC2 set frequency %lu\n", rate); ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); - if (ret < 0) { + if (ret < 0) pr_err("Cannot set HDMI parent: %d\n", ret); - goto out; - } out: if (!IS_ERR(hdmi_ick)) clk_put(hdmi_ick); - return ret; } -device_initcall(hdmi_init_pm_clock); /* USB1 (Host) */ static void usb1_host_port_power(int port, int power) @@ -690,7 +686,7 @@ static struct resource sdhi0_resources[] = { [0] = { .name = "SDHI0", .start = 0xe6850000, - .end = 0xe68501ff, + .end = 0xe68500ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -725,7 +721,7 @@ static struct resource sdhi1_resources[] = { [0] = { .name = "SDHI1", .start = 0xe6860000, - .end = 0xe68601ff, + .end = 0xe68600ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -768,7 +764,7 @@ static struct resource sdhi2_resources[] = { [0] = { .name = "SDHI2", .start = 0xe6870000, - .end = 0xe68701ff, + .end = 0xe68700ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -1124,15 +1120,15 @@ static void __init mackerel_init(void) /* enable Keypad */ gpio_request(GPIO_FN_IRQ9_42, NULL); - set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); /* enable Touchscreen */ gpio_request(GPIO_FN_IRQ7_40, NULL); - set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); /* enable Accelerometer */ gpio_request(GPIO_FN_IRQ21, NULL); - set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); /* enable SDHI0 */ gpio_request(GPIO_FN_SDHICD0, NULL); @@ -1218,6 +1214,8 @@ static void __init mackerel_init(void) sh7372_add_standard_devices(); platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); + + hdmi_init_pm_clock(); } static void __init mackerel_timer_init(void) diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h index e11560a525a..21a59db638b 100644 --- a/arch/arm/mach-shmobile/include/mach/mmc.h +++ b/arch/arm/mach-shmobile/include/mach/mmc.h @@ -9,7 +9,7 @@ #ifdef CONFIG_MACH_AP4EVB #include "mach/mmc-ap4eb.h" -#elif CONFIG_MACH_MACKEREL +#elif defined(CONFIG_MACH_MACKEREL) #include "mach/mmc-mackerel.h" #else #error "unsupported board." diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h deleted file mode 100644 index 50db94e927a..00000000000 --- a/arch/arm/mach-shmobile/include/mach/smp.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __MACH_SMP_H -#define __MACH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ -#if defined(CONFIG_ARM_GIC) - gic_raise_softirq(mask, ipi); -#endif -} - -#endif diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h index 6d6a205bcf9..9320aff0a20 100644 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -13,7 +13,7 @@ #ifdef CONFIG_MACH_AP4EVB #define MACH_TYPE MACH_TYPE_AP4EVB #include "mach/head-ap4evb.txt" -#elif CONFIG_MACH_MACKEREL +#elif defined(CONFIG_MACH_MACKEREL) #define MACH_TYPE MACH_TYPE_MACKEREL #include "mach/head-mackerel.txt" #else diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 2fe9704d5ea..cc442d198cd 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c @@ -421,7 +421,7 @@ static struct intc_desc intcs_desc __initdata = { static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); @@ -435,6 +435,6 @@ void __init sh7367_init_irq(void) register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(0xf80), (void *)intevtsa); - set_irq_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index ca5f9d17b39..7a4960f9c1e 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -601,7 +601,7 @@ static struct intc_desc intcs_desc __initdata = { static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); @@ -615,6 +615,6 @@ void __init sh7372_init_irq(void) register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(0xf80), (void *)intevtsa); - set_irq_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index dd568382cc9..fe45154ce66 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c @@ -626,7 +626,7 @@ static struct intc_desc intcs_desc __initdata = { static void intcs_demux(unsigned int irq, struct irq_desc *desc) { - void __iomem *reg = (void *)get_irq_data(irq); + void __iomem *reg = (void *)irq_get_handler_data(irq); unsigned int evtcodeas = ioread32(reg); generic_handle_irq(intcs_evt2irq(evtcodeas)); @@ -641,6 +641,6 @@ void __init sh7377_init_irq(void) register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ - set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); - set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); + irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); + irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); } diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 65e879bab4d..f3888feb1c6 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -16,6 +16,7 @@ #include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> +#include <asm/hardware/gic.h> #include <asm/localtimer.h> #include <asm/mach-types.h> #include <mach/common.h> @@ -57,6 +58,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c index 94912d3944d..2d1b67a59e4 100644 --- a/arch/arm/mach-shmobile/pm_runtime.c +++ b/arch/arm/mach-shmobile/pm_runtime.c @@ -18,152 +18,41 @@ #include <linux/clk.h> #include <linux/sh_clk.h> #include <linux/bitmap.h> +#include <linux/slab.h> #ifdef CONFIG_PM_RUNTIME -#define BIT_ONCE 0 -#define BIT_ACTIVE 1 -#define BIT_CLK_ENABLED 2 -struct pm_runtime_data { - unsigned long flags; - struct clk *clk; -}; - -static void __devres_release(struct device *dev, void *res) -{ - struct pm_runtime_data *prd = res; - - dev_dbg(dev, "__devres_release()\n"); - - if (test_bit(BIT_CLK_ENABLED, &prd->flags)) - clk_disable(prd->clk); - - if (test_bit(BIT_ACTIVE, &prd->flags)) - clk_put(prd->clk); -} - -static struct pm_runtime_data *__to_prd(struct device *dev) -{ - return devres_find(dev, __devres_release, NULL, NULL); -} - -static void platform_pm_runtime_init(struct device *dev, - struct pm_runtime_data *prd) -{ - if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) { - prd->clk = clk_get(dev, NULL); - if (!IS_ERR(prd->clk)) { - set_bit(BIT_ACTIVE, &prd->flags); - dev_info(dev, "clocks managed by runtime pm\n"); - } - } -} - -static void platform_pm_runtime_bug(struct device *dev, - struct pm_runtime_data *prd) -{ - if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) - dev_err(dev, "runtime pm suspend before resume\n"); -} - -int platform_pm_runtime_suspend(struct device *dev) -{ - struct pm_runtime_data *prd = __to_prd(dev); - - dev_dbg(dev, "platform_pm_runtime_suspend()\n"); - - platform_pm_runtime_bug(dev, prd); - - if (prd && test_bit(BIT_ACTIVE, &prd->flags)) { - clk_disable(prd->clk); - clear_bit(BIT_CLK_ENABLED, &prd->flags); - } - - return 0; -} - -int platform_pm_runtime_resume(struct device *dev) -{ - struct pm_runtime_data *prd = __to_prd(dev); - - dev_dbg(dev, "platform_pm_runtime_resume()\n"); - - platform_pm_runtime_init(dev, prd); - - if (prd && test_bit(BIT_ACTIVE, &prd->flags)) { - clk_enable(prd->clk); - set_bit(BIT_CLK_ENABLED, &prd->flags); - } - - return 0; -} - -int platform_pm_runtime_idle(struct device *dev) +static int default_platform_runtime_idle(struct device *dev) { /* suspend synchronously to disable clocks immediately */ return pm_runtime_suspend(dev); } -static int platform_bus_notify(struct notifier_block *nb, - unsigned long action, void *data) -{ - struct device *dev = data; - struct pm_runtime_data *prd; - - dev_dbg(dev, "platform_bus_notify() %ld !\n", action); - - if (action == BUS_NOTIFY_BIND_DRIVER) { - prd = devres_alloc(__devres_release, sizeof(*prd), GFP_KERNEL); - if (prd) - devres_add(dev, prd); - else - dev_err(dev, "unable to alloc memory for runtime pm\n"); - } - - return 0; -} - -#else /* CONFIG_PM_RUNTIME */ - -static int platform_bus_notify(struct notifier_block *nb, - unsigned long action, void *data) -{ - struct device *dev = data; - struct clk *clk; +static struct dev_power_domain default_power_domain = { + .ops = { + .runtime_suspend = pm_runtime_clk_suspend, + .runtime_resume = pm_runtime_clk_resume, + .runtime_idle = default_platform_runtime_idle, + USE_PLATFORM_PM_SLEEP_OPS + }, +}; - dev_dbg(dev, "platform_bus_notify() %ld !\n", action); +#define DEFAULT_PWR_DOMAIN_PTR (&default_power_domain) - switch (action) { - case BUS_NOTIFY_BIND_DRIVER: - clk = clk_get(dev, NULL); - if (!IS_ERR(clk)) { - clk_enable(clk); - clk_put(clk); - dev_info(dev, "runtime pm disabled, clock forced on\n"); - } - break; - case BUS_NOTIFY_UNBOUND_DRIVER: - clk = clk_get(dev, NULL); - if (!IS_ERR(clk)) { - clk_disable(clk); - clk_put(clk); - dev_info(dev, "runtime pm disabled, clock forced off\n"); - } - break; - } +#else - return 0; -} +#define DEFAULT_PWR_DOMAIN_PTR NULL #endif /* CONFIG_PM_RUNTIME */ -static struct notifier_block platform_bus_notifier = { - .notifier_call = platform_bus_notify +static struct pm_clk_notifier_block platform_bus_notifier = { + .pwr_domain = DEFAULT_PWR_DOMAIN_PTR, + .con_ids = { NULL, }, }; static int __init sh_pm_runtime_init(void) { - bus_register_notifier(&platform_bus_type, &platform_bus_notifier); + pm_runtime_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); return 0; } core_initcall(sh_pm_runtime_init); diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig index 20d1317cc48..2cee6b0de37 100644 --- a/arch/arm/mach-spear3xx/Kconfig +++ b/arch/arm/mach-spear3xx/Kconfig @@ -4,9 +4,26 @@ if ARCH_SPEAR3XX -choice - prompt "SPEAr3XX Family" - default MACH_SPEAR300 +menu "SPEAr3xx Implementations" +config BOARD_SPEAR300_EVB + bool "SPEAr300 Evaluation Board" + select MACH_SPEAR300 + help + Supports ST SPEAr300 Evaluation Board + +config BOARD_SPEAR310_EVB + bool "SPEAr310 Evaluation Board" + select MACH_SPEAR310 + help + Supports ST SPEAr310 Evaluation Board + +config BOARD_SPEAR320_EVB + bool "SPEAr320 Evaluation Board" + select MACH_SPEAR320 + help + Supports ST SPEAr320 Evaluation Board + +endmenu config MACH_SPEAR300 bool "SPEAr300" @@ -23,11 +40,4 @@ config MACH_SPEAR320 help Supports ST SPEAr320 Machine -endchoice - -# Adding SPEAr3XX machine specific configuration files -source "arch/arm/mach-spear3xx/Kconfig300" -source "arch/arm/mach-spear3xx/Kconfig310" -source "arch/arm/mach-spear3xx/Kconfig320" - endif #ARCH_SPEAR3XX diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300 deleted file mode 100644 index c519a05b4ab..00000000000 --- a/arch/arm/mach-spear3xx/Kconfig300 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr300 machine configuration file -# - -if MACH_SPEAR300 - -choice - prompt "SPEAr300 Boards" - default BOARD_SPEAR300_EVB - -config BOARD_SPEAR300_EVB - bool "SPEAr300 Evaluation Board" - help - Supports ST SPEAr300 Evaluation Board -endchoice - -endif #MACH_SPEAR300 diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310 deleted file mode 100644 index 60e7442d75b..00000000000 --- a/arch/arm/mach-spear3xx/Kconfig310 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr310 machine configuration file -# - -if MACH_SPEAR310 - -choice - prompt "SPEAr310 Boards" - default BOARD_SPEAR310_EVB - -config BOARD_SPEAR310_EVB - bool "SPEAr310 Evaluation Board" - help - Supports ST SPEAr310 Evaluation Board -endchoice - -endif #MACH_SPEAR310 diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320 deleted file mode 100644 index 1c1d438399b..00000000000 --- a/arch/arm/mach-spear3xx/Kconfig320 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr320 machine configuration file -# - -if MACH_SPEAR320 - -choice - prompt "SPEAr320 Boards" - default BOARD_SPEAR320_EVB - -config BOARD_SPEAR320_EVB - bool "SPEAr320 Evaluation Board" - help - Supports ST SPEAr320 Evaluation Board -endchoice - -endif #MACH_SPEAR320 diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c index 98bc7edc95a..f67860cd649 100644 --- a/arch/arm/mach-spear3xx/clock.c +++ b/arch/arm/mach-spear3xx/clock.c @@ -13,6 +13,7 @@ #include <linux/init.h> #include <linux/kernel.h> +#include <asm/mach-types.h> #include <plat/clock.h> #include <mach/misc_regs.h> @@ -688,56 +689,71 @@ static struct clk_lookup spear_clk_lookups[] = { { .dev_id = "adc", .clk = &adc_clk}, { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, { .dev_id = "gpio", .clk = &gpio_clk}, -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) - { .dev_id = "physmap-flash", .clk = &emi_clk}, -#endif -#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \ - defined(CONFIG_MACH_SPEAR320) - { .con_id = "fsmc", .clk = &fsmc_clk}, -#endif - -/* common clocks to spear310 and spear320 */ -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) - { .dev_id = "uart1", .clk = &uart1_clk}, - { .dev_id = "uart2", .clk = &uart2_clk}, -#endif - - /* common clock to spear300 and spear320 */ -#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320) - { .dev_id = "clcd", .clk = &clcd_clk}, - { .dev_id = "sdhci", .clk = &sdhci_clk}, -#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */ +}; - /* spear300 machine specific clock structures */ +/* array of all spear 300 clock lookups */ #ifdef CONFIG_MACH_SPEAR300 +static struct clk_lookup spear300_clk_lookups[] = { + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, { .dev_id = "gpio1", .clk = &gpio1_clk}, { .dev_id = "keyboard", .clk = &kbd_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, +}; #endif - /* spear310 machine specific clock structures */ +/* array of all spear 310 clock lookups */ #ifdef CONFIG_MACH_SPEAR310 +static struct clk_lookup spear310_clk_lookups[] = { + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, { .dev_id = "uart3", .clk = &uart3_clk}, { .dev_id = "uart4", .clk = &uart4_clk}, { .dev_id = "uart5", .clk = &uart5_clk}, - +}; #endif - /* spear320 machine specific clock structures */ + +/* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 +static struct clk_lookup spear320_clk_lookups[] = { + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "pwm", .clk = &pwm_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, { .dev_id = "c_can_platform.0", .clk = &can0_clk}, { .dev_id = "c_can_platform.1", .clk = &can1_clk}, - { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, - { .dev_id = "pwm", .clk = &pwm_clk}, -#endif + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, }; +#endif -void __init clk_init(void) +void __init spear3xx_clk_init(void) { - int i; + int i, cnt; + struct clk_lookup *lookups; + + if (machine_is_spear300()) { + cnt = ARRAY_SIZE(spear300_clk_lookups); + lookups = spear300_clk_lookups; + } else if (machine_is_spear310()) { + cnt = ARRAY_SIZE(spear310_clk_lookups); + lookups = spear310_clk_lookups; + } else { + cnt = ARRAY_SIZE(spear320_clk_lookups); + lookups = spear320_clk_lookups; + } for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) clk_register(&spear_clk_lookups[i]); - recalc_root_clocks(); + for (i = 0; i < cnt; i++) + clk_register(&lookups[i]); + + clk_init(); } diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index 8e30636909e..b8f31c3935f 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -27,16 +27,16 @@ * Following GPT channels will be used as clock source and clockevent */ #define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 +#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1 +#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 /* Add spear3xx family device structure declarations here */ -extern struct amba_device gpio_device; -extern struct amba_device uart_device; +extern struct amba_device spear3xx_gpio_device; +extern struct amba_device spear3xx_uart_device; extern struct sys_timer spear3xx_timer; /* Add spear3xx family function declarations here */ -void __init clk_init(void); +void __init spear3xx_clk_init(void); void __init spear_setup_timer(void); void __init spear3xx_map_io(void); void __init spear3xx_init_irq(void); @@ -60,81 +60,80 @@ void __init spear3xx_init(void); #define PMX_TIMER_1_2_MASK (1 << 0) /* pad mux devices */ -extern struct pmx_dev pmx_firda; -extern struct pmx_dev pmx_i2c; -extern struct pmx_dev pmx_ssp_cs; -extern struct pmx_dev pmx_ssp; -extern struct pmx_dev pmx_mii; -extern struct pmx_dev pmx_gpio_pin0; -extern struct pmx_dev pmx_gpio_pin1; -extern struct pmx_dev pmx_gpio_pin2; -extern struct pmx_dev pmx_gpio_pin3; -extern struct pmx_dev pmx_gpio_pin4; -extern struct pmx_dev pmx_gpio_pin5; -extern struct pmx_dev pmx_uart0_modem; -extern struct pmx_dev pmx_uart0; -extern struct pmx_dev pmx_timer_3_4; -extern struct pmx_dev pmx_timer_1_2; +extern struct pmx_dev spear3xx_pmx_firda; +extern struct pmx_dev spear3xx_pmx_i2c; +extern struct pmx_dev spear3xx_pmx_ssp_cs; +extern struct pmx_dev spear3xx_pmx_ssp; +extern struct pmx_dev spear3xx_pmx_mii; +extern struct pmx_dev spear3xx_pmx_gpio_pin0; +extern struct pmx_dev spear3xx_pmx_gpio_pin1; +extern struct pmx_dev spear3xx_pmx_gpio_pin2; +extern struct pmx_dev spear3xx_pmx_gpio_pin3; +extern struct pmx_dev spear3xx_pmx_gpio_pin4; +extern struct pmx_dev spear3xx_pmx_gpio_pin5; +extern struct pmx_dev spear3xx_pmx_uart0_modem; +extern struct pmx_dev spear3xx_pmx_uart0; +extern struct pmx_dev spear3xx_pmx_timer_3_4; +extern struct pmx_dev spear3xx_pmx_timer_1_2; #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) /* padmux plgpio devices */ -extern struct pmx_dev pmx_plgpio_0_1; -extern struct pmx_dev pmx_plgpio_2_3; -extern struct pmx_dev pmx_plgpio_4_5; -extern struct pmx_dev pmx_plgpio_6_9; -extern struct pmx_dev pmx_plgpio_10_27; -extern struct pmx_dev pmx_plgpio_28; -extern struct pmx_dev pmx_plgpio_29; -extern struct pmx_dev pmx_plgpio_30; -extern struct pmx_dev pmx_plgpio_31; -extern struct pmx_dev pmx_plgpio_32; -extern struct pmx_dev pmx_plgpio_33; -extern struct pmx_dev pmx_plgpio_34_36; -extern struct pmx_dev pmx_plgpio_37_42; -extern struct pmx_dev pmx_plgpio_43_44_47_48; -extern struct pmx_dev pmx_plgpio_45_46_49_50; +extern struct pmx_dev spear3xx_pmx_plgpio_0_1; +extern struct pmx_dev spear3xx_pmx_plgpio_2_3; +extern struct pmx_dev spear3xx_pmx_plgpio_4_5; +extern struct pmx_dev spear3xx_pmx_plgpio_6_9; +extern struct pmx_dev spear3xx_pmx_plgpio_10_27; +extern struct pmx_dev spear3xx_pmx_plgpio_28; +extern struct pmx_dev spear3xx_pmx_plgpio_29; +extern struct pmx_dev spear3xx_pmx_plgpio_30; +extern struct pmx_dev spear3xx_pmx_plgpio_31; +extern struct pmx_dev spear3xx_pmx_plgpio_32; +extern struct pmx_dev spear3xx_pmx_plgpio_33; +extern struct pmx_dev spear3xx_pmx_plgpio_34_36; +extern struct pmx_dev spear3xx_pmx_plgpio_37_42; +extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48; +extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; #endif -extern struct pmx_driver pmx_driver; - /* spear300 declarations */ #ifdef CONFIG_MACH_SPEAR300 /* Add spear300 machine device structure declarations here */ -extern struct amba_device gpio1_device; +extern struct amba_device spear300_gpio1_device; /* pad mux modes */ -extern struct pmx_mode nand_mode; -extern struct pmx_mode nor_mode; -extern struct pmx_mode photo_frame_mode; -extern struct pmx_mode lend_ip_phone_mode; -extern struct pmx_mode hend_ip_phone_mode; -extern struct pmx_mode lend_wifi_phone_mode; -extern struct pmx_mode hend_wifi_phone_mode; -extern struct pmx_mode ata_pabx_wi2s_mode; -extern struct pmx_mode ata_pabx_i2s_mode; -extern struct pmx_mode caml_lcdw_mode; -extern struct pmx_mode camu_lcd_mode; -extern struct pmx_mode camu_wlcd_mode; -extern struct pmx_mode caml_lcd_mode; +extern struct pmx_mode spear300_nand_mode; +extern struct pmx_mode spear300_nor_mode; +extern struct pmx_mode spear300_photo_frame_mode; +extern struct pmx_mode spear300_lend_ip_phone_mode; +extern struct pmx_mode spear300_hend_ip_phone_mode; +extern struct pmx_mode spear300_lend_wifi_phone_mode; +extern struct pmx_mode spear300_hend_wifi_phone_mode; +extern struct pmx_mode spear300_ata_pabx_wi2s_mode; +extern struct pmx_mode spear300_ata_pabx_i2s_mode; +extern struct pmx_mode spear300_caml_lcdw_mode; +extern struct pmx_mode spear300_camu_lcd_mode; +extern struct pmx_mode spear300_camu_wlcd_mode; +extern struct pmx_mode spear300_caml_lcd_mode; /* pad mux devices */ -extern struct pmx_dev pmx_fsmc_2_chips; -extern struct pmx_dev pmx_fsmc_4_chips; -extern struct pmx_dev pmx_keyboard; -extern struct pmx_dev pmx_clcd; -extern struct pmx_dev pmx_telecom_gpio; -extern struct pmx_dev pmx_telecom_tdm; -extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk; -extern struct pmx_dev pmx_telecom_camera; -extern struct pmx_dev pmx_telecom_dac; -extern struct pmx_dev pmx_telecom_i2s; -extern struct pmx_dev pmx_telecom_boot_pins; -extern struct pmx_dev pmx_telecom_sdhci_4bit; -extern struct pmx_dev pmx_telecom_sdhci_8bit; -extern struct pmx_dev pmx_gpio1; +extern struct pmx_dev spear300_pmx_fsmc_2_chips; +extern struct pmx_dev spear300_pmx_fsmc_4_chips; +extern struct pmx_dev spear300_pmx_keyboard; +extern struct pmx_dev spear300_pmx_clcd; +extern struct pmx_dev spear300_pmx_telecom_gpio; +extern struct pmx_dev spear300_pmx_telecom_tdm; +extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk; +extern struct pmx_dev spear300_pmx_telecom_camera; +extern struct pmx_dev spear300_pmx_telecom_dac; +extern struct pmx_dev spear300_pmx_telecom_i2s; +extern struct pmx_dev spear300_pmx_telecom_boot_pins; +extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; +extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; +extern struct pmx_dev spear300_pmx_gpio1; /* Add spear300 machine function declarations here */ -void __init spear300_init(void); +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR300 */ @@ -143,17 +142,18 @@ void __init spear300_init(void); /* Add spear310 machine device structure declarations here */ /* pad mux devices */ -extern struct pmx_dev pmx_emi_cs_0_1_4_5; -extern struct pmx_dev pmx_emi_cs_2_3; -extern struct pmx_dev pmx_uart1; -extern struct pmx_dev pmx_uart2; -extern struct pmx_dev pmx_uart3_4_5; -extern struct pmx_dev pmx_fsmc; -extern struct pmx_dev pmx_rs485_0_1; -extern struct pmx_dev pmx_tdm0; +extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; +extern struct pmx_dev spear310_pmx_emi_cs_2_3; +extern struct pmx_dev spear310_pmx_uart1; +extern struct pmx_dev spear310_pmx_uart2; +extern struct pmx_dev spear310_pmx_uart3_4_5; +extern struct pmx_dev spear310_pmx_fsmc; +extern struct pmx_dev spear310_pmx_rs485_0_1; +extern struct pmx_dev spear310_pmx_tdm0; /* Add spear310 machine function declarations here */ -void __init spear310_init(void); +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR310 */ @@ -162,37 +162,38 @@ void __init spear310_init(void); /* Add spear320 machine device structure declarations here */ /* pad mux modes */ -extern struct pmx_mode auto_net_smii_mode; -extern struct pmx_mode auto_net_mii_mode; -extern struct pmx_mode auto_exp_mode; -extern struct pmx_mode small_printers_mode; +extern struct pmx_mode spear320_auto_net_smii_mode; +extern struct pmx_mode spear320_auto_net_mii_mode; +extern struct pmx_mode spear320_auto_exp_mode; +extern struct pmx_mode spear320_small_printers_mode; /* pad mux devices */ -extern struct pmx_dev pmx_clcd; -extern struct pmx_dev pmx_emi; -extern struct pmx_dev pmx_fsmc; -extern struct pmx_dev pmx_spp; -extern struct pmx_dev pmx_sdhci; -extern struct pmx_dev pmx_i2s; -extern struct pmx_dev pmx_uart1; -extern struct pmx_dev pmx_uart1_modem; -extern struct pmx_dev pmx_uart2; -extern struct pmx_dev pmx_touchscreen; -extern struct pmx_dev pmx_can; -extern struct pmx_dev pmx_sdhci_led; -extern struct pmx_dev pmx_pwm0; -extern struct pmx_dev pmx_pwm1; -extern struct pmx_dev pmx_pwm2; -extern struct pmx_dev pmx_pwm3; -extern struct pmx_dev pmx_ssp1; -extern struct pmx_dev pmx_ssp2; -extern struct pmx_dev pmx_mii1; -extern struct pmx_dev pmx_smii0; -extern struct pmx_dev pmx_smii1; -extern struct pmx_dev pmx_i2c1; +extern struct pmx_dev spear320_pmx_clcd; +extern struct pmx_dev spear320_pmx_emi; +extern struct pmx_dev spear320_pmx_fsmc; +extern struct pmx_dev spear320_pmx_spp; +extern struct pmx_dev spear320_pmx_sdhci; +extern struct pmx_dev spear320_pmx_i2s; +extern struct pmx_dev spear320_pmx_uart1; +extern struct pmx_dev spear320_pmx_uart1_modem; +extern struct pmx_dev spear320_pmx_uart2; +extern struct pmx_dev spear320_pmx_touchscreen; +extern struct pmx_dev spear320_pmx_can; +extern struct pmx_dev spear320_pmx_sdhci_led; +extern struct pmx_dev spear320_pmx_pwm0; +extern struct pmx_dev spear320_pmx_pwm1; +extern struct pmx_dev spear320_pmx_pwm2; +extern struct pmx_dev spear320_pmx_pwm3; +extern struct pmx_dev spear320_pmx_ssp1; +extern struct pmx_dev spear320_pmx_ssp2; +extern struct pmx_dev spear320_pmx_mii1; +extern struct pmx_dev spear320_pmx_smii0; +extern struct pmx_dev spear320_pmx_smii1; +extern struct pmx_dev spear320_pmx_i2c1; /* Add spear320 machine function declarations here */ -void __init spear320_init(void); +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR320 */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index a1a7f481866..6e265442808 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -15,138 +15,140 @@ #define __MACH_IRQS_H /* SPEAr3xx IRQ definitions */ -#define IRQ_HW_ACCEL_MOD_0 0 -#define IRQ_INTRCOMM_RAS_ARM 1 -#define IRQ_CPU_GPT1_1 2 -#define IRQ_CPU_GPT1_2 3 -#define IRQ_BASIC_GPT1_1 4 -#define IRQ_BASIC_GPT1_2 5 -#define IRQ_BASIC_GPT2_1 6 -#define IRQ_BASIC_GPT2_2 7 -#define IRQ_BASIC_DMA 8 -#define IRQ_BASIC_SMI 9 -#define IRQ_BASIC_RTC 10 -#define IRQ_BASIC_GPIO 11 -#define IRQ_BASIC_WDT 12 -#define IRQ_DDR_CONTROLLER 13 -#define IRQ_SYS_ERROR 14 -#define IRQ_WAKEUP_RCV 15 -#define IRQ_JPEG 16 -#define IRQ_IRDA 17 -#define IRQ_ADC 18 -#define IRQ_UART 19 -#define IRQ_SSP 20 -#define IRQ_I2C 21 -#define IRQ_MAC_1 22 -#define IRQ_MAC_2 23 -#define IRQ_USB_DEV 24 -#define IRQ_USB_H_OHCI_0 25 -#define IRQ_USB_H_EHCI_0 26 -#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 -#define IRQ_USB_H_OHCI_1 27 -#define IRQ_GEN_RAS_1 28 -#define IRQ_GEN_RAS_2 29 -#define IRQ_GEN_RAS_3 30 -#define IRQ_HW_ACCEL_MOD_1 31 -#define IRQ_VIC_END 32 - -#define VIRQ_START IRQ_VIC_END +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0 +#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 +#define SPEAR3XX_IRQ_CPU_GPT1_1 2 +#define SPEAR3XX_IRQ_CPU_GPT1_2 3 +#define SPEAR3XX_IRQ_BASIC_GPT1_1 4 +#define SPEAR3XX_IRQ_BASIC_GPT1_2 5 +#define SPEAR3XX_IRQ_BASIC_GPT2_1 6 +#define SPEAR3XX_IRQ_BASIC_GPT2_2 7 +#define SPEAR3XX_IRQ_BASIC_DMA 8 +#define SPEAR3XX_IRQ_BASIC_SMI 9 +#define SPEAR3XX_IRQ_BASIC_RTC 10 +#define SPEAR3XX_IRQ_BASIC_GPIO 11 +#define SPEAR3XX_IRQ_BASIC_WDT 12 +#define SPEAR3XX_IRQ_DDR_CONTROLLER 13 +#define SPEAR3XX_IRQ_SYS_ERROR 14 +#define SPEAR3XX_IRQ_WAKEUP_RCV 15 +#define SPEAR3XX_IRQ_JPEG 16 +#define SPEAR3XX_IRQ_IRDA 17 +#define SPEAR3XX_IRQ_ADC 18 +#define SPEAR3XX_IRQ_UART 19 +#define SPEAR3XX_IRQ_SSP 20 +#define SPEAR3XX_IRQ_I2C 21 +#define SPEAR3XX_IRQ_MAC_1 22 +#define SPEAR3XX_IRQ_MAC_2 23 +#define SPEAR3XX_IRQ_USB_DEV 24 +#define SPEAR3XX_IRQ_USB_H_OHCI_0 25 +#define SPEAR3XX_IRQ_USB_H_EHCI_0 26 +#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0 +#define SPEAR3XX_IRQ_USB_H_OHCI_1 27 +#define SPEAR3XX_IRQ_GEN_RAS_1 28 +#define SPEAR3XX_IRQ_GEN_RAS_2 29 +#define SPEAR3XX_IRQ_GEN_RAS_3 30 +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31 +#define SPEAR3XX_IRQ_VIC_END 32 + +#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END /* SPEAr300 Virtual irq definitions */ -#ifdef CONFIG_MACH_SPEAR300 /* IRQs sharing IRQ_GEN_RAS_1 */ -#define VIRQ_IT_PERS_S (VIRQ_START + 0) -#define VIRQ_IT_CHANGE_S (VIRQ_START + 1) -#define VIRQ_I2S (VIRQ_START + 2) -#define VIRQ_TDM (VIRQ_START + 3) -#define VIRQ_CAMERA_L (VIRQ_START + 4) -#define VIRQ_CAMERA_F (VIRQ_START + 5) -#define VIRQ_CAMERA_V (VIRQ_START + 6) -#define VIRQ_KEYBOARD (VIRQ_START + 7) -#define VIRQ_GPIO1 (VIRQ_START + 8) +#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) +#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) +#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) +#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) +#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) +#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) +#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) +#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) +#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) /* IRQs sharing IRQ_GEN_RAS_3 */ -#define IRQ_CLCD IRQ_GEN_RAS_3 +#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM - -/* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9) -#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8) +#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM /* SPEAr310 Virtual irq definitions */ -#elif defined(CONFIG_MACH_SPEAR310) /* IRQs sharing IRQ_GEN_RAS_1 */ -#define VIRQ_SMII0 (VIRQ_START + 0) -#define VIRQ_SMII1 (VIRQ_START + 1) -#define VIRQ_SMII2 (VIRQ_START + 2) -#define VIRQ_SMII3 (VIRQ_START + 3) -#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4) -#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5) -#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6) -#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7) +#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) +#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) +#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) +#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) +#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) +#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) +#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) +#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) /* IRQs sharing IRQ_GEN_RAS_2 */ -#define VIRQ_UART1 (VIRQ_START + 8) -#define VIRQ_UART2 (VIRQ_START + 9) -#define VIRQ_UART3 (VIRQ_START + 10) -#define VIRQ_UART4 (VIRQ_START + 11) -#define VIRQ_UART5 (VIRQ_START + 12) +#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) /* IRQs sharing IRQ_GEN_RAS_3 */ -#define VIRQ_EMI (VIRQ_START + 13) -#define VIRQ_PLGPIO (VIRQ_START + 14) +#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) +#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define VIRQ_TDM_HDLC (VIRQ_START + 15) -#define VIRQ_RS485_0 (VIRQ_START + 16) -#define VIRQ_RS485_1 (VIRQ_START + 17) - -/* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18) +#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) +#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) +#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) /* SPEAr320 Virtual irq definitions */ -#else /* IRQs sharing IRQ_GEN_RAS_1 */ -#define VIRQ_EMI (VIRQ_START + 0) -#define VIRQ_CLCD (VIRQ_START + 1) -#define VIRQ_SPP (VIRQ_START + 2) +#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) +#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) +#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) /* IRQs sharing IRQ_GEN_RAS_2 */ -#define IRQ_SDHCI IRQ_GEN_RAS_2 +#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 /* IRQs sharing IRQ_GEN_RAS_3 */ -#define VIRQ_PLGPIO (VIRQ_START + 3) -#define VIRQ_I2S_PLAY (VIRQ_START + 4) -#define VIRQ_I2S_REC (VIRQ_START + 5) +#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) +#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) +#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define VIRQ_CANU (VIRQ_START + 6) -#define VIRQ_CANL (VIRQ_START + 7) -#define VIRQ_UART1 (VIRQ_START + 8) -#define VIRQ_UART2 (VIRQ_START + 9) -#define VIRQ_SSP1 (VIRQ_START + 10) -#define VIRQ_SSP2 (VIRQ_START + 11) -#define VIRQ_SMII0 (VIRQ_START + 12) -#define VIRQ_MII1_SMII1 (VIRQ_START + 13) -#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14) -#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15) -#define VIRQ_I2C (VIRQ_START + 16) - -/* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17) +#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) +#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) +#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) +#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) +#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) +#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) +#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) +/* + * GPIO pins virtual irqs + * Use the lowest number for the GPIO virtual IRQs base on which subarchs + * we have compiled in + */ +#if defined(CONFIG_MACH_SPEAR310) +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18) +#elif defined(CONFIG_MACH_SPEAR320) +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17) +#else +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9) #endif -/* PLGPIO Virtual IRQs */ +#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) +#define SPEAR3XX_PLGPIO_COUNT 102 + #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102) +#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) +#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \ + SPEAR3XX_PLGPIO_COUNT) +#else +#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8) #endif -#define VIRQ_END SPEAR_GPIO_INT_END -#define NR_IRQS VIRQ_END +#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END +#define NR_IRQS SPEAR3XX_VIRQ_END #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index c723515f885..3b6ea072904 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -20,19 +20,19 @@ #define SPEAR300_TELECOM_BASE UL(0x50000000) /* Interrupt registers offsets and masks */ -#define INT_ENB_MASK_REG 0x54 -#define INT_STS_MASK_REG 0x58 -#define IT_PERS_S_IRQ_MASK (1 << 0) -#define IT_CHANGE_S_IRQ_MASK (1 << 1) -#define I2S_IRQ_MASK (1 << 2) -#define TDM_IRQ_MASK (1 << 3) -#define CAMERA_L_IRQ_MASK (1 << 4) -#define CAMERA_F_IRQ_MASK (1 << 5) -#define CAMERA_V_IRQ_MASK (1 << 6) -#define KEYBOARD_IRQ_MASK (1 << 7) -#define GPIO1_IRQ_MASK (1 << 8) - -#define SHIRQ_RAS1_MASK 0x1FF +#define SPEAR300_INT_ENB_MASK_REG 0x54 +#define SPEAR300_INT_STS_MASK_REG 0x58 +#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) +#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) +#define SPEAR300_I2S_IRQ_MASK (1 << 2) +#define SPEAR300_TDM_IRQ_MASK (1 << 3) +#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) +#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) +#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) +#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) +#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) + +#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF #define SPEAR300_CLCD_BASE UL(0x60000000) #define SPEAR300_SDHCI_BASE UL(0x70000000) diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index 1e853479b8c..1567d0da725 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -29,29 +29,29 @@ #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) /* Interrupt registers offsets and masks */ -#define INT_STS_MASK_REG 0x04 -#define SMII0_IRQ_MASK (1 << 0) -#define SMII1_IRQ_MASK (1 << 1) -#define SMII2_IRQ_MASK (1 << 2) -#define SMII3_IRQ_MASK (1 << 3) -#define WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define UART1_IRQ_MASK (1 << 8) -#define UART2_IRQ_MASK (1 << 9) -#define UART3_IRQ_MASK (1 << 10) -#define UART4_IRQ_MASK (1 << 11) -#define UART5_IRQ_MASK (1 << 12) -#define EMI_IRQ_MASK (1 << 13) -#define TDM_HDLC_IRQ_MASK (1 << 14) -#define RS485_0_IRQ_MASK (1 << 15) -#define RS485_1_IRQ_MASK (1 << 16) +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) -#define SHIRQ_RAS1_MASK 0x000FF -#define SHIRQ_RAS2_MASK 0x01F00 -#define SHIRQ_RAS3_MASK 0x02000 -#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 #endif /* __MACH_SPEAR310_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 940f0d85d95..8cfa83fa129 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -36,31 +36,31 @@ #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) /* Interrupt registers offsets and masks */ -#define INT_STS_MASK_REG 0x04 -#define INT_CLR_MASK_REG 0x04 -#define INT_ENB_MASK_REG 0x08 -#define GPIO_IRQ_MASK (1 << 0) -#define I2S_PLAY_IRQ_MASK (1 << 1) -#define I2S_REC_IRQ_MASK (1 << 2) -#define EMI_IRQ_MASK (1 << 7) -#define CLCD_IRQ_MASK (1 << 8) -#define SPP_IRQ_MASK (1 << 9) -#define SDHCI_IRQ_MASK (1 << 10) -#define CAN_U_IRQ_MASK (1 << 11) -#define CAN_L_IRQ_MASK (1 << 12) -#define UART1_IRQ_MASK (1 << 13) -#define UART2_IRQ_MASK (1 << 14) -#define SSP1_IRQ_MASK (1 << 15) -#define SSP2_IRQ_MASK (1 << 16) -#define SMII0_IRQ_MASK (1 << 17) -#define MII1_SMII1_IRQ_MASK (1 << 18) -#define WAKEUP_SMII0_IRQ_MASK (1 << 19) -#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) -#define I2C1_IRQ_MASK (1 << 21) +#define SPEAR320_INT_STS_MASK_REG 0x04 +#define SPEAR320_INT_CLR_MASK_REG 0x04 +#define SPEAR320_INT_ENB_MASK_REG 0x08 +#define SPEAR320_GPIO_IRQ_MASK (1 << 0) +#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) +#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) +#define SPEAR320_EMI_IRQ_MASK (1 << 7) +#define SPEAR320_CLCD_IRQ_MASK (1 << 8) +#define SPEAR320_SPP_IRQ_MASK (1 << 9) +#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) +#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) +#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) +#define SPEAR320_UART1_IRQ_MASK (1 << 13) +#define SPEAR320_UART2_IRQ_MASK (1 << 14) +#define SPEAR320_SSP1_IRQ_MASK (1 << 15) +#define SPEAR320_SSP2_IRQ_MASK (1 << 16) +#define SPEAR320_SMII0_IRQ_MASK (1 << 17) +#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) +#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define SPEAR320_I2C1_IRQ_MASK (1 << 21) -#define SHIRQ_RAS1_MASK 0x000380 -#define SHIRQ_RAS3_MASK 0x000007 -#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 +#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 +#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 +#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 #endif /* __MACH_SPEAR320_H */ diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index 2697e65adf8..a5e46b4ade2 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -40,86 +40,86 @@ #define CAML_LCD_MODE (1 << 12) #define ALL_MODES 0x1FFF -struct pmx_mode nand_mode = { +struct pmx_mode spear300_nand_mode = { .id = NAND_MODE, .name = "nand mode", .mask = 0x00, }; -struct pmx_mode nor_mode = { +struct pmx_mode spear300_nor_mode = { .id = NOR_MODE, .name = "nor mode", .mask = 0x01, }; -struct pmx_mode photo_frame_mode = { +struct pmx_mode spear300_photo_frame_mode = { .id = PHOTO_FRAME_MODE, .name = "photo frame mode", .mask = 0x02, }; -struct pmx_mode lend_ip_phone_mode = { +struct pmx_mode spear300_lend_ip_phone_mode = { .id = LEND_IP_PHONE_MODE, .name = "lend ip phone mode", .mask = 0x03, }; -struct pmx_mode hend_ip_phone_mode = { +struct pmx_mode spear300_hend_ip_phone_mode = { .id = HEND_IP_PHONE_MODE, .name = "hend ip phone mode", .mask = 0x04, }; -struct pmx_mode lend_wifi_phone_mode = { +struct pmx_mode spear300_lend_wifi_phone_mode = { .id = LEND_WIFI_PHONE_MODE, .name = "lend wifi phone mode", .mask = 0x05, }; -struct pmx_mode hend_wifi_phone_mode = { +struct pmx_mode spear300_hend_wifi_phone_mode = { .id = HEND_WIFI_PHONE_MODE, .name = "hend wifi phone mode", .mask = 0x06, }; -struct pmx_mode ata_pabx_wi2s_mode = { +struct pmx_mode spear300_ata_pabx_wi2s_mode = { .id = ATA_PABX_WI2S_MODE, .name = "ata pabx wi2s mode", .mask = 0x07, }; -struct pmx_mode ata_pabx_i2s_mode = { +struct pmx_mode spear300_ata_pabx_i2s_mode = { .id = ATA_PABX_I2S_MODE, .name = "ata pabx i2s mode", .mask = 0x08, }; -struct pmx_mode caml_lcdw_mode = { +struct pmx_mode spear300_caml_lcdw_mode = { .id = CAML_LCDW_MODE, .name = "caml lcdw mode", .mask = 0x0C, }; -struct pmx_mode camu_lcd_mode = { +struct pmx_mode spear300_camu_lcd_mode = { .id = CAMU_LCD_MODE, .name = "camu lcd mode", .mask = 0x0D, }; -struct pmx_mode camu_wlcd_mode = { +struct pmx_mode spear300_camu_wlcd_mode = { .id = CAMU_WLCD_MODE, .name = "camu wlcd mode", .mask = 0x0E, }; -struct pmx_mode caml_lcd_mode = { +struct pmx_mode spear300_caml_lcd_mode = { .id = CAML_LCD_MODE, .name = "caml lcd mode", .mask = 0x0F, }; /* devices */ -struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { +static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { { .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, @@ -127,14 +127,14 @@ struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { }, }; -struct pmx_dev pmx_fsmc_2_chips = { +struct pmx_dev spear300_pmx_fsmc_2_chips = { .name = "fsmc_2_chips", .modes = pmx_fsmc_2_chips_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { +static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { { .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, @@ -142,14 +142,14 @@ struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { }, }; -struct pmx_dev pmx_fsmc_4_chips = { +struct pmx_dev spear300_pmx_fsmc_4_chips = { .name = "fsmc_4_chips", .modes = pmx_fsmc_4_chips_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_keyboard_modes[] = { +static struct pmx_dev_mode pmx_keyboard_modes[] = { { .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | @@ -159,14 +159,14 @@ struct pmx_dev_mode pmx_keyboard_modes[] = { }, }; -struct pmx_dev pmx_keyboard = { +struct pmx_dev spear300_pmx_keyboard = { .name = "keyboard", .modes = pmx_keyboard_modes, .mode_count = ARRAY_SIZE(pmx_keyboard_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_clcd_modes[] = { +static struct pmx_dev_mode pmx_clcd_modes[] = { { .ids = PHOTO_FRAME_MODE, .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , @@ -177,14 +177,14 @@ struct pmx_dev_mode pmx_clcd_modes[] = { }, }; -struct pmx_dev pmx_clcd = { +struct pmx_dev spear300_pmx_clcd = { .name = "clcd", .modes = pmx_clcd_modes, .mode_count = ARRAY_SIZE(pmx_clcd_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_gpio_modes[] = { +static struct pmx_dev_mode pmx_telecom_gpio_modes[] = { { .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, .mask = PMX_MII_MASK, @@ -204,14 +204,14 @@ struct pmx_dev_mode pmx_telecom_gpio_modes[] = { }, }; -struct pmx_dev pmx_telecom_gpio = { +struct pmx_dev spear300_pmx_telecom_gpio = { .name = "telecom_gpio", .modes = pmx_telecom_gpio_modes, .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_tdm_modes[] = { +static struct pmx_dev_mode pmx_telecom_tdm_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE @@ -222,14 +222,14 @@ struct pmx_dev_mode pmx_telecom_tdm_modes[] = { }, }; -struct pmx_dev pmx_telecom_tdm = { +struct pmx_dev spear300_pmx_telecom_tdm = { .name = "telecom_tdm", .modes = pmx_telecom_tdm_modes, .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { +static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { { .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE @@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { }, }; -struct pmx_dev pmx_telecom_spi_cs_i2c_clk = { +struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = { .name = "telecom_spi_cs_i2c_clk", .modes = pmx_telecom_spi_cs_i2c_clk_modes, .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_camera_modes[] = { +static struct pmx_dev_mode pmx_telecom_camera_modes[] = { { .ids = CAML_LCDW_MODE | CAML_LCD_MODE, .mask = PMX_MII_MASK, @@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_telecom_camera_modes[] = { }, }; -struct pmx_dev pmx_telecom_camera = { +struct pmx_dev spear300_pmx_telecom_camera = { .name = "telecom_camera", .modes = pmx_telecom_camera_modes, .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_dac_modes[] = { +static struct pmx_dev_mode pmx_telecom_dac_modes[] = { { .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | CAML_LCD_MODE, @@ -271,14 +271,14 @@ struct pmx_dev_mode pmx_telecom_dac_modes[] = { }, }; -struct pmx_dev pmx_telecom_dac = { +struct pmx_dev spear300_pmx_telecom_dac = { .name = "telecom_dac", .modes = pmx_telecom_dac_modes, .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_i2s_modes[] = { +static struct pmx_dev_mode pmx_telecom_i2s_modes[] = { { .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | @@ -288,14 +288,14 @@ struct pmx_dev_mode pmx_telecom_i2s_modes[] = { }, }; -struct pmx_dev pmx_telecom_i2s = { +struct pmx_dev spear300_pmx_telecom_i2s = { .name = "telecom_i2s", .modes = pmx_telecom_i2s_modes, .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { +static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { { .ids = NAND_MODE | NOR_MODE, .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | @@ -303,14 +303,14 @@ struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { }, }; -struct pmx_dev pmx_telecom_boot_pins = { +struct pmx_dev spear300_pmx_telecom_boot_pins = { .name = "telecom_boot_pins", .modes = pmx_telecom_boot_pins_modes, .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { +static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | @@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { }, }; -struct pmx_dev pmx_telecom_sdhci_4bit = { +struct pmx_dev spear300_pmx_telecom_sdhci_4bit = { .name = "telecom_sdhci_4bit", .modes = pmx_telecom_sdhci_4bit_modes, .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { +static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | @@ -342,14 +342,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { }, }; -struct pmx_dev pmx_telecom_sdhci_8bit = { +struct pmx_dev spear300_pmx_telecom_sdhci_8bit = { .name = "telecom_sdhci_8bit", .modes = pmx_telecom_sdhci_8bit_modes, .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_gpio1_modes[] = { +static struct pmx_dev_mode pmx_gpio1_modes[] = { { .ids = PHOTO_FRAME_MODE, .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | @@ -357,7 +357,7 @@ struct pmx_dev_mode pmx_gpio1_modes[] = { }, }; -struct pmx_dev pmx_gpio1 = { +struct pmx_dev spear300_pmx_gpio1 = { .name = "arm gpio1", .modes = pmx_gpio1_modes, .mode_count = ARRAY_SIZE(pmx_gpio1_modes), @@ -365,60 +365,60 @@ struct pmx_dev pmx_gpio1 = { }; /* pmx driver structure */ -struct pmx_driver pmx_driver = { +static struct pmx_driver pmx_driver = { .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; /* spear3xx shared irq */ -struct shirq_dev_config shirq_ras1_config[] = { +static struct shirq_dev_config shirq_ras1_config[] = { { - .virq = VIRQ_IT_PERS_S, - .enb_mask = IT_PERS_S_IRQ_MASK, - .status_mask = IT_PERS_S_IRQ_MASK, + .virq = SPEAR300_VIRQ_IT_PERS_S, + .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK, + .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK, }, { - .virq = VIRQ_IT_CHANGE_S, - .enb_mask = IT_CHANGE_S_IRQ_MASK, - .status_mask = IT_CHANGE_S_IRQ_MASK, + .virq = SPEAR300_VIRQ_IT_CHANGE_S, + .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK, + .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK, }, { - .virq = VIRQ_I2S, - .enb_mask = I2S_IRQ_MASK, - .status_mask = I2S_IRQ_MASK, + .virq = SPEAR300_VIRQ_I2S, + .enb_mask = SPEAR300_I2S_IRQ_MASK, + .status_mask = SPEAR300_I2S_IRQ_MASK, }, { - .virq = VIRQ_TDM, - .enb_mask = TDM_IRQ_MASK, - .status_mask = TDM_IRQ_MASK, + .virq = SPEAR300_VIRQ_TDM, + .enb_mask = SPEAR300_TDM_IRQ_MASK, + .status_mask = SPEAR300_TDM_IRQ_MASK, }, { - .virq = VIRQ_CAMERA_L, - .enb_mask = CAMERA_L_IRQ_MASK, - .status_mask = CAMERA_L_IRQ_MASK, + .virq = SPEAR300_VIRQ_CAMERA_L, + .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK, + .status_mask = SPEAR300_CAMERA_L_IRQ_MASK, }, { - .virq = VIRQ_CAMERA_F, - .enb_mask = CAMERA_F_IRQ_MASK, - .status_mask = CAMERA_F_IRQ_MASK, + .virq = SPEAR300_VIRQ_CAMERA_F, + .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK, + .status_mask = SPEAR300_CAMERA_F_IRQ_MASK, }, { - .virq = VIRQ_CAMERA_V, - .enb_mask = CAMERA_V_IRQ_MASK, - .status_mask = CAMERA_V_IRQ_MASK, + .virq = SPEAR300_VIRQ_CAMERA_V, + .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK, + .status_mask = SPEAR300_CAMERA_V_IRQ_MASK, }, { - .virq = VIRQ_KEYBOARD, - .enb_mask = KEYBOARD_IRQ_MASK, - .status_mask = KEYBOARD_IRQ_MASK, + .virq = SPEAR300_VIRQ_KEYBOARD, + .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK, + .status_mask = SPEAR300_KEYBOARD_IRQ_MASK, }, { - .virq = VIRQ_GPIO1, - .enb_mask = GPIO1_IRQ_MASK, - .status_mask = GPIO1_IRQ_MASK, + .virq = SPEAR300_VIRQ_GPIO1, + .enb_mask = SPEAR300_GPIO1_IRQ_MASK, + .status_mask = SPEAR300_GPIO1_IRQ_MASK, }, }; -struct spear_shirq shirq_ras1 = { - .irq = IRQ_GEN_RAS_1, +static struct spear_shirq shirq_ras1 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_1, .dev_config = shirq_ras1_config, .dev_count = ARRAY_SIZE(shirq_ras1_config), .regs = { - .enb_reg = INT_ENB_MASK_REG, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS1_MASK, + .enb_reg = SPEAR300_INT_ENB_MASK_REG, + .status_reg = SPEAR300_INT_STS_MASK_REG, + .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK, .clear_reg = -1, }, }; @@ -427,10 +427,10 @@ struct spear_shirq shirq_ras1 = { /* arm gpio1 device registration */ static struct pl061_platform_data gpio1_plat_data = { .gpio_base = 8, - .irq_base = SPEAR_GPIO1_INT_BASE, + .irq_base = SPEAR300_GPIO1_INT_BASE, }; -struct amba_device gpio1_device = { +struct amba_device spear300_gpio1_device = { .dev = { .init_name = "gpio1", .platform_data = &gpio1_plat_data, @@ -440,11 +440,12 @@ struct amba_device gpio1_device = { .end = SPEAR300_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {VIRQ_GPIO1, NO_IRQ}, + .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ}, }; /* spear300 routines */ -void __init spear300_init(void) +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { int ret = 0; @@ -460,6 +461,10 @@ void __init spear300_init(void) } /* pmx initialization */ + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); if (pmx_driver.base) { ret = pmx_register(&pmx_driver); diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c index 42d2253ef54..69006f69422 100644 --- a/arch/arm/mach-spear3xx/spear300_evb.c +++ b/arch/arm/mach-spear3xx/spear300_evb.c @@ -19,26 +19,26 @@ /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { /* spear3xx specific devices */ - &pmx_i2c, - &pmx_ssp_cs, - &pmx_ssp, - &pmx_mii, - &pmx_uart0, + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp_cs, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, /* spear300 specific devices */ - &pmx_fsmc_2_chips, - &pmx_clcd, - &pmx_telecom_sdhci_4bit, - &pmx_gpio1, + &spear300_pmx_fsmc_2_chips, + &spear300_pmx_clcd, + &spear300_pmx_telecom_sdhci_4bit, + &spear300_pmx_gpio1, }; static struct amba_device *amba_devs[] __initdata = { /* spear3xx specific devices */ - &gpio_device, - &uart_device, + &spear3xx_gpio_device, + &spear3xx_uart_device, /* spear300 specific devices */ - &gpio1_device, + &spear300_gpio1_device, }; static struct platform_device *plat_devs[] __initdata = { @@ -51,13 +51,9 @@ static void __init spear300_evb_init(void) { unsigned int i; - /* padmux initialization, must be done before spear300_init */ - pmx_driver.mode = &photo_frame_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - /* call spear300 machine init function */ - spear300_init(); + spear300_init(&spear300_photo_frame_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index 5c0a67b60c2..9004cf9f01b 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -22,112 +22,112 @@ #define PAD_MUX_CONFIG_REG 0x08 /* devices */ -struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { +static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_emi_cs_0_1_4_5 = { +struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { .name = "emi_cs_0_1_4_5", .modes = pmx_emi_cs_0_1_4_5_modes, .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { +static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_emi_cs_2_3 = { +struct pmx_dev spear310_pmx_emi_cs_2_3 = { .name = "emi_cs_2_3", .modes = pmx_emi_cs_2_3_modes, .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart1_modes[] = { +static struct pmx_dev_mode pmx_uart1_modes[] = { { .ids = 0x00, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_uart1 = { +struct pmx_dev spear310_pmx_uart1 = { .name = "uart1", .modes = pmx_uart1_modes, .mode_count = ARRAY_SIZE(pmx_uart1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart2_modes[] = { +static struct pmx_dev_mode pmx_uart2_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_uart2 = { +struct pmx_dev spear310_pmx_uart2 = { .name = "uart2", .modes = pmx_uart2_modes, .mode_count = ARRAY_SIZE(pmx_uart2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart3_4_5_modes[] = { +static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_uart3_4_5 = { +struct pmx_dev spear310_pmx_uart3_4_5 = { .name = "uart3_4_5", .modes = pmx_uart3_4_5_modes, .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_fsmc_modes[] = { +static struct pmx_dev_mode pmx_fsmc_modes[] = { { .ids = 0x00, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_fsmc = { +struct pmx_dev spear310_pmx_fsmc = { .name = "fsmc", .modes = pmx_fsmc_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_rs485_0_1_modes[] = { +static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_rs485_0_1 = { +struct pmx_dev spear310_pmx_rs485_0_1 = { .name = "rs485_0_1", .modes = pmx_rs485_0_1_modes, .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_tdm0_modes[] = { +static struct pmx_dev_mode pmx_tdm0_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_tdm0 = { +struct pmx_dev spear310_pmx_tdm0 = { .name = "tdm0", .modes = pmx_tdm0_modes, .mode_count = ARRAY_SIZE(pmx_tdm0_modes), @@ -135,122 +135,122 @@ struct pmx_dev pmx_tdm0 = { }; /* pmx driver structure */ -struct pmx_driver pmx_driver = { +static struct pmx_driver pmx_driver = { .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; /* spear3xx shared irq */ -struct shirq_dev_config shirq_ras1_config[] = { +static struct shirq_dev_config shirq_ras1_config[] = { { - .virq = VIRQ_SMII0, - .status_mask = SMII0_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII0, + .status_mask = SPEAR310_SMII0_IRQ_MASK, }, { - .virq = VIRQ_SMII1, - .status_mask = SMII1_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII1, + .status_mask = SPEAR310_SMII1_IRQ_MASK, }, { - .virq = VIRQ_SMII2, - .status_mask = SMII2_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII2, + .status_mask = SPEAR310_SMII2_IRQ_MASK, }, { - .virq = VIRQ_SMII3, - .status_mask = SMII3_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII3, + .status_mask = SPEAR310_SMII3_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII0, - .status_mask = WAKEUP_SMII0_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII0, + .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII1, - .status_mask = WAKEUP_SMII1_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII1, + .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII2, - .status_mask = WAKEUP_SMII2_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII2, + .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII3, - .status_mask = WAKEUP_SMII3_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII3, + .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, }, }; -struct spear_shirq shirq_ras1 = { - .irq = IRQ_GEN_RAS_1, +static struct spear_shirq shirq_ras1 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_1, .dev_config = shirq_ras1_config, .dev_count = ARRAY_SIZE(shirq_ras1_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS1_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, .clear_reg = -1, }, }; -struct shirq_dev_config shirq_ras2_config[] = { +static struct shirq_dev_config shirq_ras2_config[] = { { - .virq = VIRQ_UART1, - .status_mask = UART1_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART1, + .status_mask = SPEAR310_UART1_IRQ_MASK, }, { - .virq = VIRQ_UART2, - .status_mask = UART2_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART2, + .status_mask = SPEAR310_UART2_IRQ_MASK, }, { - .virq = VIRQ_UART3, - .status_mask = UART3_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART3, + .status_mask = SPEAR310_UART3_IRQ_MASK, }, { - .virq = VIRQ_UART4, - .status_mask = UART4_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART4, + .status_mask = SPEAR310_UART4_IRQ_MASK, }, { - .virq = VIRQ_UART5, - .status_mask = UART5_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART5, + .status_mask = SPEAR310_UART5_IRQ_MASK, }, }; -struct spear_shirq shirq_ras2 = { - .irq = IRQ_GEN_RAS_2, +static struct spear_shirq shirq_ras2 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_2, .dev_config = shirq_ras2_config, .dev_count = ARRAY_SIZE(shirq_ras2_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS2_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, .clear_reg = -1, }, }; -struct shirq_dev_config shirq_ras3_config[] = { +static struct shirq_dev_config shirq_ras3_config[] = { { - .virq = VIRQ_EMI, - .status_mask = EMI_IRQ_MASK, + .virq = SPEAR310_VIRQ_EMI, + .status_mask = SPEAR310_EMI_IRQ_MASK, }, }; -struct spear_shirq shirq_ras3 = { - .irq = IRQ_GEN_RAS_3, +static struct spear_shirq shirq_ras3 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_3, .dev_config = shirq_ras3_config, .dev_count = ARRAY_SIZE(shirq_ras3_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS3_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, .clear_reg = -1, }, }; -struct shirq_dev_config shirq_intrcomm_ras_config[] = { +static struct shirq_dev_config shirq_intrcomm_ras_config[] = { { - .virq = VIRQ_TDM_HDLC, - .status_mask = TDM_HDLC_IRQ_MASK, + .virq = SPEAR310_VIRQ_TDM_HDLC, + .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, }, { - .virq = VIRQ_RS485_0, - .status_mask = RS485_0_IRQ_MASK, + .virq = SPEAR310_VIRQ_RS485_0, + .status_mask = SPEAR310_RS485_0_IRQ_MASK, }, { - .virq = VIRQ_RS485_1, - .status_mask = RS485_1_IRQ_MASK, + .virq = SPEAR310_VIRQ_RS485_1, + .status_mask = SPEAR310_RS485_1_IRQ_MASK, }, }; -struct spear_shirq shirq_intrcomm_ras = { - .irq = IRQ_INTRCOMM_RAS_ARM, +static struct spear_shirq shirq_intrcomm_ras = { + .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, .dev_config = shirq_intrcomm_ras_config, .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, .clear_reg = -1, }, }; @@ -258,7 +258,8 @@ struct spear_shirq shirq_intrcomm_ras = { /* Add spear310 specific devices here */ /* spear310 routines */ -void __init spear310_init(void) +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; int ret = 0; @@ -296,6 +297,10 @@ void __init spear310_init(void) /* pmx initialization */ pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + ret = pmx_register(&pmx_driver); if (ret) printk(KERN_ERR "padmux: registeration failed. err no: %d\n", diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c index 2d7f333bd67..c8684ce1f9b 100644 --- a/arch/arm/mach-spear3xx/spear310_evb.c +++ b/arch/arm/mach-spear3xx/spear310_evb.c @@ -19,31 +19,31 @@ /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { /* spear3xx specific devices */ - &pmx_i2c, - &pmx_ssp, - &pmx_gpio_pin0, - &pmx_gpio_pin1, - &pmx_gpio_pin2, - &pmx_gpio_pin3, - &pmx_gpio_pin4, - &pmx_gpio_pin5, - &pmx_uart0, + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_gpio_pin0, + &spear3xx_pmx_gpio_pin1, + &spear3xx_pmx_gpio_pin2, + &spear3xx_pmx_gpio_pin3, + &spear3xx_pmx_gpio_pin4, + &spear3xx_pmx_gpio_pin5, + &spear3xx_pmx_uart0, /* spear310 specific devices */ - &pmx_emi_cs_0_1_4_5, - &pmx_emi_cs_2_3, - &pmx_uart1, - &pmx_uart2, - &pmx_uart3_4_5, - &pmx_fsmc, - &pmx_rs485_0_1, - &pmx_tdm0, + &spear310_pmx_emi_cs_0_1_4_5, + &spear310_pmx_emi_cs_2_3, + &spear310_pmx_uart1, + &spear310_pmx_uart2, + &spear310_pmx_uart3_4_5, + &spear310_pmx_fsmc, + &spear310_pmx_rs485_0_1, + &spear310_pmx_tdm0, }; static struct amba_device *amba_devs[] __initdata = { /* spear3xx specific devices */ - &gpio_device, - &uart_device, + &spear3xx_gpio_device, + &spear3xx_uart_device, /* spear310 specific devices */ }; @@ -58,13 +58,8 @@ static void __init spear310_evb_init(void) { unsigned int i; - /* padmux initialization, must be done before spear310_init */ - pmx_driver.mode = NULL; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - /* call spear310 machine init function */ - spear310_init(); + spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs)); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index 741c1f414cb..ee29bef4307 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -29,88 +29,88 @@ #define SMALL_PRINTERS_MODE (1 << 3) #define ALL_MODES 0xF -struct pmx_mode auto_net_smii_mode = { +struct pmx_mode spear320_auto_net_smii_mode = { .id = AUTO_NET_SMII_MODE, .name = "Automation Networking SMII Mode", .mask = 0x00, }; -struct pmx_mode auto_net_mii_mode = { +struct pmx_mode spear320_auto_net_mii_mode = { .id = AUTO_NET_MII_MODE, .name = "Automation Networking MII Mode", .mask = 0x01, }; -struct pmx_mode auto_exp_mode = { +struct pmx_mode spear320_auto_exp_mode = { .id = AUTO_EXP_MODE, .name = "Automation Expanded Mode", .mask = 0x02, }; -struct pmx_mode small_printers_mode = { +struct pmx_mode spear320_small_printers_mode = { .id = SMALL_PRINTERS_MODE, .name = "Small Printers Mode", .mask = 0x03, }; /* devices */ -struct pmx_dev_mode pmx_clcd_modes[] = { +static struct pmx_dev_mode pmx_clcd_modes[] = { { .ids = AUTO_NET_SMII_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_clcd = { +struct pmx_dev spear320_pmx_clcd = { .name = "clcd", .modes = pmx_clcd_modes, .mode_count = ARRAY_SIZE(pmx_clcd_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_emi_modes[] = { +static struct pmx_dev_mode pmx_emi_modes[] = { { .ids = AUTO_EXP_MODE, .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_emi = { +struct pmx_dev spear320_pmx_emi = { .name = "emi", .modes = pmx_emi_modes, .mode_count = ARRAY_SIZE(pmx_emi_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_fsmc_modes[] = { +static struct pmx_dev_mode pmx_fsmc_modes[] = { { .ids = ALL_MODES, .mask = 0x0, }, }; -struct pmx_dev pmx_fsmc = { +struct pmx_dev spear320_pmx_fsmc = { .name = "fsmc", .modes = pmx_fsmc_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_spp_modes[] = { +static struct pmx_dev_mode pmx_spp_modes[] = { { .ids = SMALL_PRINTERS_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_spp = { +struct pmx_dev spear320_pmx_spp = { .name = "spp", .modes = pmx_spp_modes, .mode_count = ARRAY_SIZE(pmx_spp_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_sdhci_modes[] = { +static struct pmx_dev_mode pmx_sdhci_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | SMALL_PRINTERS_MODE, @@ -118,42 +118,42 @@ struct pmx_dev_mode pmx_sdhci_modes[] = { }, }; -struct pmx_dev pmx_sdhci = { +struct pmx_dev spear320_pmx_sdhci = { .name = "sdhci", .modes = pmx_sdhci_modes, .mode_count = ARRAY_SIZE(pmx_sdhci_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_i2s_modes[] = { +static struct pmx_dev_mode pmx_i2s_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_i2s = { +struct pmx_dev spear320_pmx_i2s = { .name = "i2s", .modes = pmx_i2s_modes, .mode_count = ARRAY_SIZE(pmx_i2s_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart1_modes[] = { +static struct pmx_dev_mode pmx_uart1_modes[] = { { .ids = ALL_MODES, .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_uart1 = { +struct pmx_dev spear320_pmx_uart1 = { .name = "uart1", .modes = pmx_uart1_modes, .mode_count = ARRAY_SIZE(pmx_uart1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart1_modem_modes[] = { +static struct pmx_dev_mode pmx_uart1_modem_modes[] = { { .ids = AUTO_EXP_MODE, .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | @@ -165,42 +165,42 @@ struct pmx_dev_mode pmx_uart1_modem_modes[] = { }, }; -struct pmx_dev pmx_uart1_modem = { +struct pmx_dev spear320_pmx_uart1_modem = { .name = "uart1_modem", .modes = pmx_uart1_modem_modes, .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart2_modes[] = { +static struct pmx_dev_mode pmx_uart2_modes[] = { { .ids = ALL_MODES, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_uart2 = { +struct pmx_dev spear320_pmx_uart2 = { .name = "uart2", .modes = pmx_uart2_modes, .mode_count = ARRAY_SIZE(pmx_uart2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_touchscreen_modes[] = { +static struct pmx_dev_mode pmx_touchscreen_modes[] = { { .ids = AUTO_NET_SMII_MODE, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_touchscreen = { +struct pmx_dev spear320_pmx_touchscreen = { .name = "touchscreen", .modes = pmx_touchscreen_modes, .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_can_modes[] = { +static struct pmx_dev_mode pmx_can_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | @@ -208,28 +208,28 @@ struct pmx_dev_mode pmx_can_modes[] = { }, }; -struct pmx_dev pmx_can = { +struct pmx_dev spear320_pmx_can = { .name = "can", .modes = pmx_can_modes, .mode_count = ARRAY_SIZE(pmx_can_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_sdhci_led_modes[] = { +static struct pmx_dev_mode pmx_sdhci_led_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_sdhci_led = { +struct pmx_dev spear320_pmx_sdhci_led = { .name = "sdhci_led", .modes = pmx_sdhci_led_modes, .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm0_modes[] = { +static struct pmx_dev_mode pmx_pwm0_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_UART0_MODEM_MASK, @@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_pwm0_modes[] = { }, }; -struct pmx_dev pmx_pwm0 = { +struct pmx_dev spear320_pmx_pwm0 = { .name = "pwm0", .modes = pmx_pwm0_modes, .mode_count = ARRAY_SIZE(pmx_pwm0_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm1_modes[] = { +static struct pmx_dev_mode pmx_pwm1_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_UART0_MODEM_MASK, @@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_pwm1_modes[] = { }, }; -struct pmx_dev pmx_pwm1 = { +struct pmx_dev spear320_pmx_pwm1 = { .name = "pwm1", .modes = pmx_pwm1_modes, .mode_count = ARRAY_SIZE(pmx_pwm1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm2_modes[] = { +static struct pmx_dev_mode pmx_pwm2_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_SSP_CS_MASK, @@ -273,105 +273,105 @@ struct pmx_dev_mode pmx_pwm2_modes[] = { }, }; -struct pmx_dev pmx_pwm2 = { +struct pmx_dev spear320_pmx_pwm2 = { .name = "pwm2", .modes = pmx_pwm2_modes, .mode_count = ARRAY_SIZE(pmx_pwm2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm3_modes[] = { +static struct pmx_dev_mode pmx_pwm3_modes[] = { { .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_pwm3 = { +struct pmx_dev spear320_pmx_pwm3 = { .name = "pwm3", .modes = pmx_pwm3_modes, .mode_count = ARRAY_SIZE(pmx_pwm3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_ssp1_modes[] = { +static struct pmx_dev_mode pmx_ssp1_modes[] = { { .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_ssp1 = { +struct pmx_dev spear320_pmx_ssp1 = { .name = "ssp1", .modes = pmx_ssp1_modes, .mode_count = ARRAY_SIZE(pmx_ssp1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_ssp2_modes[] = { +static struct pmx_dev_mode pmx_ssp2_modes[] = { { .ids = AUTO_NET_SMII_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_ssp2 = { +struct pmx_dev spear320_pmx_ssp2 = { .name = "ssp2", .modes = pmx_ssp2_modes, .mode_count = ARRAY_SIZE(pmx_ssp2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_mii1_modes[] = { +static struct pmx_dev_mode pmx_mii1_modes[] = { { .ids = AUTO_NET_MII_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_mii1 = { +struct pmx_dev spear320_pmx_mii1 = { .name = "mii1", .modes = pmx_mii1_modes, .mode_count = ARRAY_SIZE(pmx_mii1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_smii0_modes[] = { +static struct pmx_dev_mode pmx_smii0_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_smii0 = { +struct pmx_dev spear320_pmx_smii0 = { .name = "smii0", .modes = pmx_smii0_modes, .mode_count = ARRAY_SIZE(pmx_smii0_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_smii1_modes[] = { +static struct pmx_dev_mode pmx_smii1_modes[] = { { .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_smii1 = { +struct pmx_dev spear320_pmx_smii1 = { .name = "smii1", .modes = pmx_smii1_modes, .mode_count = ARRAY_SIZE(pmx_smii1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_i2c1_modes[] = { +static struct pmx_dev_mode pmx_i2c1_modes[] = { { .ids = AUTO_EXP_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_i2c1 = { +struct pmx_dev spear320_pmx_i2c1 = { .name = "i2c1", .modes = pmx_i2c1_modes, .mode_count = ARRAY_SIZE(pmx_i2c1_modes), @@ -379,131 +379,131 @@ struct pmx_dev pmx_i2c1 = { }; /* pmx driver structure */ -struct pmx_driver pmx_driver = { +static struct pmx_driver pmx_driver = { .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; /* spear3xx shared irq */ -struct shirq_dev_config shirq_ras1_config[] = { +static struct shirq_dev_config shirq_ras1_config[] = { { - .virq = VIRQ_EMI, - .status_mask = EMI_IRQ_MASK, - .clear_mask = EMI_IRQ_MASK, + .virq = SPEAR320_VIRQ_EMI, + .status_mask = SPEAR320_EMI_IRQ_MASK, + .clear_mask = SPEAR320_EMI_IRQ_MASK, }, { - .virq = VIRQ_CLCD, - .status_mask = CLCD_IRQ_MASK, - .clear_mask = CLCD_IRQ_MASK, + .virq = SPEAR320_VIRQ_CLCD, + .status_mask = SPEAR320_CLCD_IRQ_MASK, + .clear_mask = SPEAR320_CLCD_IRQ_MASK, }, { - .virq = VIRQ_SPP, - .status_mask = SPP_IRQ_MASK, - .clear_mask = SPP_IRQ_MASK, + .virq = SPEAR320_VIRQ_SPP, + .status_mask = SPEAR320_SPP_IRQ_MASK, + .clear_mask = SPEAR320_SPP_IRQ_MASK, }, }; -struct spear_shirq shirq_ras1 = { - .irq = IRQ_GEN_RAS_1, +static struct spear_shirq shirq_ras1 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_1, .dev_config = shirq_ras1_config, .dev_count = ARRAY_SIZE(shirq_ras1_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS1_MASK, - .clear_reg = INT_CLR_MASK_REG, + .status_reg = SPEAR320_INT_STS_MASK_REG, + .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK, + .clear_reg = SPEAR320_INT_CLR_MASK_REG, .reset_to_clear = 1, }, }; -struct shirq_dev_config shirq_ras3_config[] = { +static struct shirq_dev_config shirq_ras3_config[] = { { - .virq = VIRQ_PLGPIO, - .enb_mask = GPIO_IRQ_MASK, - .status_mask = GPIO_IRQ_MASK, - .clear_mask = GPIO_IRQ_MASK, + .virq = SPEAR320_VIRQ_PLGPIO, + .enb_mask = SPEAR320_GPIO_IRQ_MASK, + .status_mask = SPEAR320_GPIO_IRQ_MASK, + .clear_mask = SPEAR320_GPIO_IRQ_MASK, }, { - .virq = VIRQ_I2S_PLAY, - .enb_mask = I2S_PLAY_IRQ_MASK, - .status_mask = I2S_PLAY_IRQ_MASK, - .clear_mask = I2S_PLAY_IRQ_MASK, + .virq = SPEAR320_VIRQ_I2S_PLAY, + .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK, + .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK, + .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK, }, { - .virq = VIRQ_I2S_REC, - .enb_mask = I2S_REC_IRQ_MASK, - .status_mask = I2S_REC_IRQ_MASK, - .clear_mask = I2S_REC_IRQ_MASK, + .virq = SPEAR320_VIRQ_I2S_REC, + .enb_mask = SPEAR320_I2S_REC_IRQ_MASK, + .status_mask = SPEAR320_I2S_REC_IRQ_MASK, + .clear_mask = SPEAR320_I2S_REC_IRQ_MASK, }, }; -struct spear_shirq shirq_ras3 = { - .irq = IRQ_GEN_RAS_3, +static struct spear_shirq shirq_ras3 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_3, .dev_config = shirq_ras3_config, .dev_count = ARRAY_SIZE(shirq_ras3_config), .regs = { - .enb_reg = INT_ENB_MASK_REG, + .enb_reg = SPEAR320_INT_ENB_MASK_REG, .reset_to_enb = 1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS3_MASK, - .clear_reg = INT_CLR_MASK_REG, + .status_reg = SPEAR320_INT_STS_MASK_REG, + .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK, + .clear_reg = SPEAR320_INT_CLR_MASK_REG, .reset_to_clear = 1, }, }; -struct shirq_dev_config shirq_intrcomm_ras_config[] = { +static struct shirq_dev_config shirq_intrcomm_ras_config[] = { { - .virq = VIRQ_CANU, - .status_mask = CAN_U_IRQ_MASK, - .clear_mask = CAN_U_IRQ_MASK, + .virq = SPEAR320_VIRQ_CANU, + .status_mask = SPEAR320_CAN_U_IRQ_MASK, + .clear_mask = SPEAR320_CAN_U_IRQ_MASK, }, { - .virq = VIRQ_CANL, - .status_mask = CAN_L_IRQ_MASK, - .clear_mask = CAN_L_IRQ_MASK, + .virq = SPEAR320_VIRQ_CANL, + .status_mask = SPEAR320_CAN_L_IRQ_MASK, + .clear_mask = SPEAR320_CAN_L_IRQ_MASK, }, { - .virq = VIRQ_UART1, - .status_mask = UART1_IRQ_MASK, - .clear_mask = UART1_IRQ_MASK, + .virq = SPEAR320_VIRQ_UART1, + .status_mask = SPEAR320_UART1_IRQ_MASK, + .clear_mask = SPEAR320_UART1_IRQ_MASK, }, { - .virq = VIRQ_UART2, - .status_mask = UART2_IRQ_MASK, - .clear_mask = UART2_IRQ_MASK, + .virq = SPEAR320_VIRQ_UART2, + .status_mask = SPEAR320_UART2_IRQ_MASK, + .clear_mask = SPEAR320_UART2_IRQ_MASK, }, { - .virq = VIRQ_SSP1, - .status_mask = SSP1_IRQ_MASK, - .clear_mask = SSP1_IRQ_MASK, + .virq = SPEAR320_VIRQ_SSP1, + .status_mask = SPEAR320_SSP1_IRQ_MASK, + .clear_mask = SPEAR320_SSP1_IRQ_MASK, }, { - .virq = VIRQ_SSP2, - .status_mask = SSP2_IRQ_MASK, - .clear_mask = SSP2_IRQ_MASK, + .virq = SPEAR320_VIRQ_SSP2, + .status_mask = SPEAR320_SSP2_IRQ_MASK, + .clear_mask = SPEAR320_SSP2_IRQ_MASK, }, { - .virq = VIRQ_SMII0, - .status_mask = SMII0_IRQ_MASK, - .clear_mask = SMII0_IRQ_MASK, + .virq = SPEAR320_VIRQ_SMII0, + .status_mask = SPEAR320_SMII0_IRQ_MASK, + .clear_mask = SPEAR320_SMII0_IRQ_MASK, }, { - .virq = VIRQ_MII1_SMII1, - .status_mask = MII1_SMII1_IRQ_MASK, - .clear_mask = MII1_SMII1_IRQ_MASK, + .virq = SPEAR320_VIRQ_MII1_SMII1, + .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK, + .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII0, - .status_mask = WAKEUP_SMII0_IRQ_MASK, - .clear_mask = WAKEUP_SMII0_IRQ_MASK, + .virq = SPEAR320_VIRQ_WAKEUP_SMII0, + .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, + .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_MII1_SMII1, - .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, - .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, + .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1, + .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, + .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, }, { - .virq = VIRQ_I2C, - .status_mask = I2C1_IRQ_MASK, - .clear_mask = I2C1_IRQ_MASK, + .virq = SPEAR320_VIRQ_I2C1, + .status_mask = SPEAR320_I2C1_IRQ_MASK, + .clear_mask = SPEAR320_I2C1_IRQ_MASK, }, }; -struct spear_shirq shirq_intrcomm_ras = { - .irq = IRQ_INTRCOMM_RAS_ARM, +static struct spear_shirq shirq_intrcomm_ras = { + .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, .dev_config = shirq_intrcomm_ras_config, .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, - .clear_reg = INT_CLR_MASK_REG, + .status_reg = SPEAR320_INT_STS_MASK_REG, + .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK, + .clear_reg = SPEAR320_INT_CLR_MASK_REG, .reset_to_clear = 1, }, }; @@ -511,7 +511,8 @@ struct spear_shirq shirq_intrcomm_ras = { /* Add spear320 specific devices here */ /* spear320 routines */ -void __init spear320_init(void) +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; int ret = 0; @@ -543,6 +544,10 @@ void __init spear320_init(void) /* pmx initialization */ pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + ret = pmx_register(&pmx_driver); if (ret) printk(KERN_ERR "padmux: registeration failed. err no: %d\n", diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c index 8213e4b66c1..a12b353940d 100644 --- a/arch/arm/mach-spear3xx/spear320_evb.c +++ b/arch/arm/mach-spear3xx/spear320_evb.c @@ -19,28 +19,28 @@ /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { /* spear3xx specific devices */ - &pmx_i2c, - &pmx_ssp, - &pmx_mii, - &pmx_uart0, + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, /* spear320 specific devices */ - &pmx_fsmc, - &pmx_sdhci, - &pmx_i2s, - &pmx_uart1, - &pmx_uart2, - &pmx_can, - &pmx_pwm0, - &pmx_pwm1, - &pmx_pwm2, - &pmx_mii1, + &spear320_pmx_fsmc, + &spear320_pmx_sdhci, + &spear320_pmx_i2s, + &spear320_pmx_uart1, + &spear320_pmx_uart2, + &spear320_pmx_can, + &spear320_pmx_pwm0, + &spear320_pmx_pwm1, + &spear320_pmx_pwm2, + &spear320_pmx_mii1, }; static struct amba_device *amba_devs[] __initdata = { /* spear3xx specific devices */ - &gpio_device, - &uart_device, + &spear3xx_gpio_device, + &spear3xx_uart_device, /* spear320 specific devices */ }; @@ -55,13 +55,9 @@ static void __init spear320_evb_init(void) { unsigned int i; - /* padmux initialization, must be done before spear320_init */ - pmx_driver.mode = &auto_net_mii_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - /* call spear320 machine init function */ - spear320_init(); + spear320_init(&spear320_auto_net_mii_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index d3ba8ca1bc5..10af45da86a 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -25,10 +25,10 @@ /* gpio device registration */ static struct pl061_platform_data gpio_plat_data = { .gpio_base = 0, - .irq_base = SPEAR_GPIO_INT_BASE, + .irq_base = SPEAR3XX_GPIO_INT_BASE, }; -struct amba_device gpio_device = { +struct amba_device spear3xx_gpio_device = { .dev = { .init_name = "gpio", .platform_data = &gpio_plat_data, @@ -38,11 +38,11 @@ struct amba_device gpio_device = { .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_BASIC_GPIO, NO_IRQ}, + .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ}, }; /* uart device registration */ -struct amba_device uart_device = { +struct amba_device spear3xx_uart_device = { .dev = { .init_name = "uart", }, @@ -51,7 +51,7 @@ struct amba_device uart_device = { .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_UART, NO_IRQ}, + .irq = {SPEAR3XX_IRQ_UART, NO_IRQ}, }; /* Do spear3xx familiy common initialization part here */ @@ -97,215 +97,215 @@ void __init spear3xx_map_io(void) iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); /* This will initialize clock framework */ - clk_init(); + spear3xx_clk_init(); } /* pad multiplexing support */ /* devices */ -struct pmx_dev_mode pmx_firda_modes[] = { +static struct pmx_dev_mode pmx_firda_modes[] = { { .ids = 0xffffffff, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_firda = { +struct pmx_dev spear3xx_pmx_firda = { .name = "firda", .modes = pmx_firda_modes, .mode_count = ARRAY_SIZE(pmx_firda_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_i2c_modes[] = { +static struct pmx_dev_mode pmx_i2c_modes[] = { { .ids = 0xffffffff, .mask = PMX_I2C_MASK, }, }; -struct pmx_dev pmx_i2c = { +struct pmx_dev spear3xx_pmx_i2c = { .name = "i2c", .modes = pmx_i2c_modes, .mode_count = ARRAY_SIZE(pmx_i2c_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_ssp_cs_modes[] = { +static struct pmx_dev_mode pmx_ssp_cs_modes[] = { { .ids = 0xffffffff, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_ssp_cs = { +struct pmx_dev spear3xx_pmx_ssp_cs = { .name = "ssp_chip_selects", .modes = pmx_ssp_cs_modes, .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_ssp_modes[] = { +static struct pmx_dev_mode pmx_ssp_modes[] = { { .ids = 0xffffffff, .mask = PMX_SSP_MASK, }, }; -struct pmx_dev pmx_ssp = { +struct pmx_dev spear3xx_pmx_ssp = { .name = "ssp", .modes = pmx_ssp_modes, .mode_count = ARRAY_SIZE(pmx_ssp_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_mii_modes[] = { +static struct pmx_dev_mode pmx_mii_modes[] = { { .ids = 0xffffffff, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_mii = { +struct pmx_dev spear3xx_pmx_mii = { .name = "mii", .modes = pmx_mii_modes, .mode_count = ARRAY_SIZE(pmx_mii_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin0_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN0_MASK, }, }; -struct pmx_dev pmx_gpio_pin0 = { +struct pmx_dev spear3xx_pmx_gpio_pin0 = { .name = "gpio_pin0", .modes = pmx_gpio_pin0_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin1_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_gpio_pin1 = { +struct pmx_dev spear3xx_pmx_gpio_pin1 = { .name = "gpio_pin1", .modes = pmx_gpio_pin1_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin2_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN2_MASK, }, }; -struct pmx_dev pmx_gpio_pin2 = { +struct pmx_dev spear3xx_pmx_gpio_pin2 = { .name = "gpio_pin2", .modes = pmx_gpio_pin2_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin3_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN3_MASK, }, }; -struct pmx_dev pmx_gpio_pin3 = { +struct pmx_dev spear3xx_pmx_gpio_pin3 = { .name = "gpio_pin3", .modes = pmx_gpio_pin3_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin4_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN4_MASK, }, }; -struct pmx_dev pmx_gpio_pin4 = { +struct pmx_dev spear3xx_pmx_gpio_pin4 = { .name = "gpio_pin4", .modes = pmx_gpio_pin4_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin5_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN5_MASK, }, }; -struct pmx_dev pmx_gpio_pin5 = { +struct pmx_dev spear3xx_pmx_gpio_pin5 = { .name = "gpio_pin5", .modes = pmx_gpio_pin5_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_uart0_modem_modes[] = { +static struct pmx_dev_mode pmx_uart0_modem_modes[] = { { .ids = 0xffffffff, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_uart0_modem = { +struct pmx_dev spear3xx_pmx_uart0_modem = { .name = "uart0_modem", .modes = pmx_uart0_modem_modes, .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_uart0_modes[] = { +static struct pmx_dev_mode pmx_uart0_modes[] = { { .ids = 0xffffffff, .mask = PMX_UART0_MASK, }, }; -struct pmx_dev pmx_uart0 = { +struct pmx_dev spear3xx_pmx_uart0 = { .name = "uart0", .modes = pmx_uart0_modes, .mode_count = ARRAY_SIZE(pmx_uart0_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_timer_3_4_modes[] = { +static struct pmx_dev_mode pmx_timer_3_4_modes[] = { { .ids = 0xffffffff, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_timer_3_4 = { +struct pmx_dev spear3xx_pmx_timer_3_4 = { .name = "timer_3_4", .modes = pmx_timer_3_4_modes, .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_timer_1_2_modes[] = { +static struct pmx_dev_mode pmx_timer_1_2_modes[] = { { .ids = 0xffffffff, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_timer_1_2 = { +struct pmx_dev spear3xx_pmx_timer_1_2 = { .name = "timer_1_2", .modes = pmx_timer_1_2_modes, .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), @@ -314,210 +314,210 @@ struct pmx_dev pmx_timer_1_2 = { #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) /* plgpios devices */ -struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { +static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { { .ids = 0x00, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_plgpio_0_1 = { +struct pmx_dev spear3xx_pmx_plgpio_0_1 = { .name = "plgpio 0 and 1", .modes = pmx_plgpio_0_1_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { +static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MASK, }, }; -struct pmx_dev pmx_plgpio_2_3 = { +struct pmx_dev spear3xx_pmx_plgpio_2_3 = { .name = "plgpio 2 and 3", .modes = pmx_plgpio_2_3_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { +static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { { .ids = 0x00, .mask = PMX_I2C_MASK, }, }; -struct pmx_dev pmx_plgpio_4_5 = { +struct pmx_dev spear3xx_pmx_plgpio_4_5 = { .name = "plgpio 4 and 5", .modes = pmx_plgpio_4_5_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { +static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { { .ids = 0x00, .mask = PMX_SSP_MASK, }, }; -struct pmx_dev pmx_plgpio_6_9 = { +struct pmx_dev spear3xx_pmx_plgpio_6_9 = { .name = "plgpio 6 to 9", .modes = pmx_plgpio_6_9_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { +static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_plgpio_10_27 = { +struct pmx_dev spear3xx_pmx_plgpio_10_27 = { .name = "plgpio 10 to 27", .modes = pmx_plgpio_10_27_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_28_modes[] = { +static struct pmx_dev_mode pmx_plgpio_28_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN0_MASK, }, }; -struct pmx_dev pmx_plgpio_28 = { +struct pmx_dev spear3xx_pmx_plgpio_28 = { .name = "plgpio 28", .modes = pmx_plgpio_28_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_29_modes[] = { +static struct pmx_dev_mode pmx_plgpio_29_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_plgpio_29 = { +struct pmx_dev spear3xx_pmx_plgpio_29 = { .name = "plgpio 29", .modes = pmx_plgpio_29_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_30_modes[] = { +static struct pmx_dev_mode pmx_plgpio_30_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN2_MASK, }, }; -struct pmx_dev pmx_plgpio_30 = { +struct pmx_dev spear3xx_pmx_plgpio_30 = { .name = "plgpio 30", .modes = pmx_plgpio_30_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_31_modes[] = { +static struct pmx_dev_mode pmx_plgpio_31_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN3_MASK, }, }; -struct pmx_dev pmx_plgpio_31 = { +struct pmx_dev spear3xx_pmx_plgpio_31 = { .name = "plgpio 31", .modes = pmx_plgpio_31_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_32_modes[] = { +static struct pmx_dev_mode pmx_plgpio_32_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN4_MASK, }, }; -struct pmx_dev pmx_plgpio_32 = { +struct pmx_dev spear3xx_pmx_plgpio_32 = { .name = "plgpio 32", .modes = pmx_plgpio_32_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_33_modes[] = { +static struct pmx_dev_mode pmx_plgpio_33_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN5_MASK, }, }; -struct pmx_dev pmx_plgpio_33 = { +struct pmx_dev spear3xx_pmx_plgpio_33 = { .name = "plgpio 33", .modes = pmx_plgpio_33_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { +static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { { .ids = 0x00, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_plgpio_34_36 = { +struct pmx_dev spear3xx_pmx_plgpio_34_36 = { .name = "plgpio 34 to 36", .modes = pmx_plgpio_34_36_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { +static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_plgpio_37_42 = { +struct pmx_dev spear3xx_pmx_plgpio_37_42 = { .name = "plgpio 37 to 42", .modes = pmx_plgpio_37_42_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { +static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_plgpio_43_44_47_48 = { +struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { .name = "plgpio 43, 44, 47 and 48", .modes = pmx_plgpio_43_44_47_48_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_plgpio_45_46_49_50 = { +struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { .name = "plgpio 45, 46, 49 and 50", .modes = pmx_plgpio_45_46_49_50_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig index bddba034f86..ff4ae5ba00f 100644 --- a/arch/arm/mach-spear6xx/Kconfig +++ b/arch/arm/mach-spear6xx/Kconfig @@ -4,17 +4,18 @@ if ARCH_SPEAR6XX -choice - prompt "SPEAr6XX Family" - default MACH_SPEAR600 +menu "SPEAr6xx Implementations" +config BOARD_SPEAR600_EVB + bool "SPEAr600 Evaluation Board" + select MACH_SPEAR600 + help + Supports ST SPEAr600 Evaluation Board + +endmenu config MACH_SPEAR600 bool "SPEAr600" help Supports ST SPEAr600 Machine -endchoice - -# Adding SPEAr6XX machine specific configuration files -source "arch/arm/mach-spear6xx/Kconfig600" endif #ARCH_SPEAR6XX diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600 deleted file mode 100644 index 9e19f65eb78..00000000000 --- a/arch/arm/mach-spear6xx/Kconfig600 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr600 machine configuration file -# - -if MACH_SPEAR600 - -choice - prompt "SPEAr600 Boards" - default BOARD_SPEAR600_EVB - -config BOARD_SPEAR600_EVB - bool "SPEAr600 Evaluation Board" - help - Supports ST SPEAr600 Evaluation Board -endchoice - -endif #MACH_SPEAR600 diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c index 88b748b5be8..ac70e0d88fe 100644 --- a/arch/arm/mach-spear6xx/clock.c +++ b/arch/arm/mach-spear6xx/clock.c @@ -671,12 +671,12 @@ static struct clk_lookup spear_clk_lookups[] = { { .dev_id = "gpio2", .clk = &gpio2_clk}, }; -void __init clk_init(void) +void __init spear6xx_clk_init(void) { int i; for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) clk_register(&spear_clk_lookups[i]); - recalc_root_clocks(); + clk_init(); } diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h index 94cf4a648b5..183f0238c5e 100644 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -39,7 +39,7 @@ void __init spear6xx_map_io(void); void __init spear6xx_init_irq(void); void __init spear6xx_init(void); void __init spear600_init(void); -void __init clk_init(void); +void __init spear6xx_clk_init(void); /* Add spear600 machine device structure declarations here */ diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 981812961ac..e0f6628c8b2 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -148,7 +148,7 @@ void __init spear6xx_map_io(void) iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); /* This will initialize clock framework */ - clk_init(); + spear6xx_clk_init(); } static void __init spear6xx_timer_init(void) diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile deleted file mode 100644 index d156f76b379..00000000000 --- a/arch/arm/mach-stmp378x/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o -obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot deleted file mode 100644 index 1568ad404d5..00000000000 --- a/arch/arm/mach-stmp378x/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x40008000 -params_phys-y := 0x40000100 -initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S deleted file mode 100644 index 731a92286da..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP378X - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT - cmp \irqnr, #0x7f - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h deleted file mode 100644 index cc59673becd..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/irqs.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Freescale STMP378X interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_BCH 56 -#define IRQ_PXP 57 -#define IRQ_UARTAPP2_TX_DMA 58 -#define IRQ_UARTAPP2_INTERNAL 59 -#define IRQ_UARTAPP2_RX_DMA 60 -#define IRQ_VDAC_DETECT 61 -#define IRQ_VDD5V_DROOP 64 -#define IRQ_DCDC4P2_BO 65 - - -#define NR_REAL_IRQS 128 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* All interrupts are FIQ capable */ -#define FIQ_START IRQ_DEBUG_UART - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h deleted file mode 100644 index 93f952d3596..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/pins.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Freescale STMP378X SoC pin multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16) -#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17) -#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22) -#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26) -#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27) -#define PINID_AUART1_RX STMP3XXX_PINID(0, 28) -#define PINID_AUART1_TX STMP3XXX_PINID(0, 29) -#define PINID_I2C_SCL STMP3XXX_PINID(0, 30) -#define PINID_I2C_SDA STMP3XXX_PINID(0, 31) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_D16 STMP3XXX_PINID(1, 16) -#define PINID_LCD_D17 STMP3XXX_PINID(1, 17) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 18) -#define PINID_LCD_RS STMP3XXX_PINID(1, 19) -#define PINID_LCD_WR STMP3XXX_PINID(1, 20) -#define PINID_LCD_CS STMP3XXX_PINID(1, 21) -#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22) -#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23) -#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24) -#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25) -#define PINID_PWM0 STMP3XXX_PINID(1, 26) -#define PINID_PWM1 STMP3XXX_PINID(1, 27) -#define PINID_PWM2 STMP3XXX_PINID(1, 28) -#define PINID_PWM3 STMP3XXX_PINID(1, 29) -#define PINID_PWM4 STMP3XXX_PINID(1, 30) - -/* Bank 2 */ -#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0) -#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5) -#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6) -#define PINID_ROTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 9) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 10) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 11) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 12) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 13) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 14) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 15) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 21) -#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22) -#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 24) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26) -#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27) -#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 29) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h deleted file mode 100644 index dbcf85b6ac2..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp378x: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) -#define REGS_APBH_PHYS 0x80004000 -#define REGS_APBH_SIZE 0x2000 - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_CTRL2 0x20 - -#define HW_APBH_DEVSEL 0x30 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBH_CHn_CMD_COMMAND 0x00000003 -#define BP_APBH_CHn_CMD_COMMAND 0 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h deleted file mode 100644 index 3b934a4d27f..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * stmp378x: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) -#define REGS_APBX_PHYS 0x80024000 -#define REGS_APBX_SIZE 0x2000 - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_CTRL2 0x20 - -#define HW_APBX_CHANNEL_CTRL 0x30 -#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 -#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 - -#define HW_APBX_DEVSEL 0x40 - -#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x110 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x130 - -#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x140 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif - diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h deleted file mode 100644 index 641ac6126f8..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) -#define REGS_AUDIOIN_PHYS 0x8004C000 -#define REGS_AUDIOIN_SIZE 0x2000 - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h deleted file mode 100644 index f533e23694a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * stmp378x: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) -#define REGS_AUDIOOUT_PHYS 0x80048000 -#define REGS_AUDIOOUT_SIZE 0x2000 - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_SPEAKERCTRL 0x100 -#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h deleted file mode 100644 index 532d2465071..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp378x: BCH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000) -#define REGS_BCH_PHYS 0x8000A000 -#define REGS_BCH_SIZE 0x2000 - -#define HW_BCH_CTRL 0x0 -#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_BCH_CTRL_COMPLETE_IRQ 0 -#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 - -#define HW_BCH_STATUS0 0x10 -#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_BCH_STATUS0_CORRECTED 0x00000008 -#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 -#define BP_BCH_STATUS0_STATUS_BLK0 8 -#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_BCH_STATUS0_COMPLETED_CE 16 - -#define HW_BCH_LAYOUTSELECT 0x70 - -#define HW_BCH_FLASH0LAYOUT0 0x80 -#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 -#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 -#define BP_BCH_FLASH0LAYOUT0_ECC0 12 -#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 -#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 -#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 -#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 -#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 -#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 -#define BP_BCH_FLASH0LAYOUT1_ECCN 12 -#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 -#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 - -#define HW_BCH_BLOCKNAME 0x150 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h deleted file mode 100644 index 7c546afd57a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp378x: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) -#define REGS_CLKCTRL_PHYS 0x80040000 -#define REGS_CLKCTRL_SIZE 0x2000 - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 -#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 -#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00000FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 -#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F -#define BP_CLKCTRL_EMI_DIV_EMI 0 -#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 -#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 -#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_TV 0xD0 - -#define HW_CLKCTRL_ETM 0xE0 - -#define HW_CLKCTRL_FRAC 0xF0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_FRAC1 0x100 - -#define HW_CLKCTRL_CLKSEQ 0x110 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0x120 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h deleted file mode 100644 index fdedd00c0e2..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: DCP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000) -#define REGS_DCP_PHYS 0x80028000 -#define REGS_DCP_SIZE 0x2000 - -#define HW_DCP_CTRL 0x0 -#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF -#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 -#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 -#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 -#define BM_DCP_CTRL_CLKGATE 0x40000000 -#define BM_DCP_CTRL_SFTRST 0x80000000 - -#define HW_DCP_STAT 0x10 -#define BM_DCP_STAT_IRQ 0x0000000F -#define BP_DCP_STAT_IRQ 0 - -#define HW_DCP_CHANNELCTRL 0x20 -#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF -#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 - -#define HW_DCP_CONTEXT 0x50 -#define BM_DCP_PACKET1_INTERRUPT 0x00000001 -#define BP_DCP_PACKET1_INTERRUPT 0 -#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 -#define BM_DCP_PACKET1_CHAIN 0x00000004 -#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 -#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 -#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 -#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 -#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 -#define BM_DCP_PACKET1_OTP_KEY 0x00000400 -#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 -#define BM_DCP_PACKET1_HASH_INIT 0x00001000 -#define BM_DCP_PACKET1_HASH_TERM 0x00002000 -#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F -#define BP_DCP_PACKET2_CIPHER_SELECT 0 -#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 -#define BP_DCP_PACKET2_CIPHER_MODE 4 -#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 -#define BP_DCP_PACKET2_KEY_SELECT 8 -#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 -#define BP_DCP_PACKET2_HASH_SELECT 16 -#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 -#define BP_DCP_PACKET2_CIPHER_CFG 24 - -#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40) -#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40) -#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40) -#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40) - -#define HW_DCP_CHnCMDPTR 0x100 - -#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40) -#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40) -#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40) -#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40) - -#define HW_DCP_CHnSEMA 0x110 -#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF -#define BP_DCP_CHnSEMA_INCREMENT 0 - -#define HW_DCP_CH0STAT (0x120 + 0 * 0x40) -#define HW_DCP_CH1STAT (0x120 + 1 * 0x40) -#define HW_DCP_CH2STAT (0x120 + 2 * 0x40) -#define HW_DCP_CH3STAT (0x120 + 3 * 0x40) - -#define HW_DCP_CHnSTAT 0x120 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h deleted file mode 100644 index 5293005523b..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * stmp378x: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) -#define REGS_DIGCTL_PHYS 0x8001C000 -#define REGS_DIGCTL_SIZE 0x2000 - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 - -#define HW_DIGCTL_ARMCACHE 0x2B0 -#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 -#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 -#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 -#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 -#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 -#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 -#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 -#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 -#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 -#define BP_DIGCTL_ARMCACHE_VALID_SS 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h deleted file mode 100644 index 02851431677..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * stmp378x: DRAM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000) -#define REGS_DRAM_PHYS 0x800E0000 -#define REGS_DRAM_SIZE 0x2000 - -#define HW_DRAM_CTL06 0x18 - -#define HW_DRAM_CTL08 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h deleted file mode 100644 index da25f7e397e..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: DRI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000) -#define REGS_DRI_PHYS 0x80074000 -#define REGS_DRI_SIZE 0x2000 - -#define HW_DRI_CTRL 0x0 -#define BM_DRI_CTRL_RUN 0x00000001 -#define BP_DRI_CTRL_RUN 0 -#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004 -#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008 -#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400 -#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800 -#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000 -#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000 -#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000 -#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 -#define BM_DRI_CTRL_CLKGATE 0x40000000 -#define BM_DRI_CTRL_SFTRST 0x80000000 - -#define HW_DRI_TIMING 0x10 -#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF -#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 -#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000 -#define BP_DRI_TIMING_PILOT_REP_RATE 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h deleted file mode 100644 index cc353bec331..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * stmp378x: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) -#define REGS_ECC8_PHYS 0x80008000 -#define REGS_ECC8_SIZE 0x2000 - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h deleted file mode 100644 index 98773fc33d7..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * stmp378x: EMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000) -#define REGS_EMI_PHYS 0x80020000 -#define REGS_EMI_SIZE 0x2000 - -#define HW_EMI_STAT 0x10 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h deleted file mode 100644 index 2cc8bbe9168..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * stmp378x: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 -#define BP_GPMI_CTRL0_ADDRESS 17 -#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 -#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 -#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 -#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF -#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 -#define BP_GPMI_CTRL1_RDN_DELAY 12 -#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 -#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 -#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h deleted file mode 100644 index 13a234c9943..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp378x: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h deleted file mode 100644 index f996e80f40e..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) -#define REGS_ICOLL_PHYS 0x80000000 -#define REGS_ICOLL_SIZE 0x2000 - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 -#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F -#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x70 - -#define HW_ICOLL_INTERRUPTn 0x120 - -#define HW_ICOLL_INTERRUPTn 0x120 -#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h deleted file mode 100644 index a5b4ef10fab..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: IR register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000) -#define REGS_IR_PHYS 0x80078000 -#define REGS_IR_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h deleted file mode 100644 index 9cdbef4badc..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * stmp378x: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_RUN 0x00000001 -#define BP_LCDIF_CTRL_RUN 0 -#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 -#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 -#define BP_LCDIF_CTRL_WORD_LENGTH 8 -#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 -#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 -#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 -#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 -#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 -#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 -#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 - -#define HW_LCDIF_TRANSFER_COUNT 0x20 -#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF -#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 -#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 -#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 - -#define HW_LCDIF_CUR_BUF 0x30 - -#define HW_LCDIF_NEXT_BUF 0x40 - -#define HW_LCDIF_TIMING 0x60 - -#define HW_LCDIF_VDCTRL0 0x70 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF -#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x80 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 - -#define HW_LCDIF_VDCTRL2 0x90 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 - -#define HW_LCDIF_VDCTRL3 0xA0 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 - -#define HW_LCDIF_VDCTRL4 0xB0 -#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF -#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 - -#define HW_LCDIF_DVICTRL0 0xC0 -#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF -#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 -#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 -#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 -#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 -#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 - -#define HW_LCDIF_DVICTRL1 0xD0 -#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF -#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 -#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 -#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 - -#define HW_LCDIF_DVICTRL2 0xE0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 -#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 - -#define HW_LCDIF_DVICTRL3 0xF0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 -#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 - -#define HW_LCDIF_DVICTRL4 0x100 -#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF -#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 -#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 -#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 -#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 -#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 -#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 -#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 - -#define HW_LCDIF_CSC_COEFF0 0x110 -#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 -#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 -#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 -#define BP_LCDIF_CSC_COEFF0_C0 16 - -#define HW_LCDIF_CSC_COEFF1 0x120 -#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF -#define BP_LCDIF_CSC_COEFF1_C1 0 -#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 -#define BP_LCDIF_CSC_COEFF1_C2 16 - -#define HW_LCDIF_CSC_COEFF2 0x130 -#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF -#define BP_LCDIF_CSC_COEFF2_C3 0 -#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 -#define BP_LCDIF_CSC_COEFF2_C4 16 - -#define HW_LCDIF_CSC_COEFF3 0x140 -#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF -#define BP_LCDIF_CSC_COEFF3_C5 0 -#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 -#define BP_LCDIF_CSC_COEFF3_C6 16 - -#define HW_LCDIF_CSC_COEFF4 0x150 -#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF -#define BP_LCDIF_CSC_COEFF4_C7 0 -#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 -#define BP_LCDIF_CSC_COEFF4_C8 16 - -#define HW_LCDIF_CSC_OFFSET 0x160 -#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF -#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 -#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 -#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 - -#define HW_LCDIF_CSC_LIMIT 0x170 -#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF -#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 -#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 -#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 -#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 -#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 - -#define HW_LCDIF_STAT 0x1D0 -#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h deleted file mode 100644 index cb8cb06f827..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * stmp378x: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) -#define REGS_LRADC_PHYS 0x80050000 -#define REGS_LRADC_SIZE 0x2000 - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h deleted file mode 100644 index f0af64d9937..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: OCOTP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000) -#define REGS_OCOTP_PHYS 0x8002C000 -#define REGS_OCOTP_SIZE 0x2000 - -#define HW_OCOTP_CTRL 0x0 -#define BM_OCOTP_CTRL_BUSY 0x00000100 -#define BM_OCOTP_CTRL_ERROR 0x00000200 -#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 -#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 -#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 -#define BP_OCOTP_CTRL_WR_UNLOCK 16 - -#define HW_OCOTP_DATA 0x10 - -#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10) -#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10) -#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10) -#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10) - -#define HW_OCOTP_CUSTn 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h deleted file mode 100644 index 50d90ea1b13..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * stmp378x: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) -#define REGS_PINCTRL_PHYS 0x80018000 -#define REGS_PINCTRL_SIZE 0x2000 - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x400 -#define HW_PINCTRL_PULL1 0x410 -#define HW_PINCTRL_PULL2 0x420 -#define HW_PINCTRL_PULL3 0x430 - -#define HW_PINCTRL_DOUT0 0x500 -#define HW_PINCTRL_DOUT1 0x510 -#define HW_PINCTRL_DOUT2 0x520 - -#define HW_PINCTRL_DIN0 0x600 -#define HW_PINCTRL_DIN1 0x610 -#define HW_PINCTRL_DIN2 0x620 - -#define HW_PINCTRL_DOE0 0x700 -#define HW_PINCTRL_DOE1 0x710 -#define HW_PINCTRL_DOE2 0x720 - -#define HW_PINCTRL_PIN2IRQ0 0x800 -#define HW_PINCTRL_PIN2IRQ1 0x810 -#define HW_PINCTRL_PIN2IRQ2 0x820 - -#define HW_PINCTRL_IRQEN0 0x900 -#define HW_PINCTRL_IRQEN1 0x910 -#define HW_PINCTRL_IRQEN2 0x920 - -#define HW_PINCTRL_IRQLEVEL0 0xA00 -#define HW_PINCTRL_IRQLEVEL1 0xA10 -#define HW_PINCTRL_IRQLEVEL2 0xA20 - -#define HW_PINCTRL_IRQPOL0 0xB00 -#define HW_PINCTRL_IRQPOL1 0xB10 -#define HW_PINCTRL_IRQPOL2 0xB20 - -#define HW_PINCTRL_IRQSTAT0 0xC00 -#define HW_PINCTRL_IRQSTAT1 0xC10 -#define HW_PINCTRL_IRQSTAT2 0xC20 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h deleted file mode 100644 index e454c830f07..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-power.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) -#define REGS_POWER_PHYS 0x80044000 -#define REGS_POWER_SIZE 0x2000 - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 -#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 -#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 -#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 -#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xC0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000200 - -#define HW_POWER_RESET 0x100 - -#define HW_POWER_DEBUG 0x110 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h deleted file mode 100644 index 0d0f9e56ec7..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * stmp378x: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) -#define REGS_PWM_PHYS 0x80064000 -#define REGS_PWM_SIZE 0x2000 - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h deleted file mode 100644 index 54d297896de..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * stmp378x: PXP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000) -#define REGS_PXP_PHYS 0x8002A000 -#define REGS_PXP_SIZE 0x2000 - -#define HW_PXP_CTRL 0x0 -#define BM_PXP_CTRL_ENABLE 0x00000001 -#define BP_PXP_CTRL_ENABLE 0 -#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 -#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 -#define BM_PXP_CTRL_ROTATE 0x00000300 -#define BP_PXP_CTRL_ROTATE 8 -#define BM_PXP_CTRL_HFLIP 0x00000400 -#define BM_PXP_CTRL_VFLIP 0x00000800 -#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 -#define BP_PXP_CTRL_S0_FORMAT 12 -#define BM_PXP_CTRL_SCALE 0x00040000 -#define BM_PXP_CTRL_CROP 0x00080000 - -#define HW_PXP_STAT 0x10 -#define BM_PXP_STAT_IRQ 0x00000001 -#define BP_PXP_STAT_IRQ 0 - -#define HW_PXP_RGBBUF 0x20 - -#define HW_PXP_RGBSIZE 0x40 -#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF -#define BP_PXP_RGBSIZE_HEIGHT 0 -#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 -#define BP_PXP_RGBSIZE_WIDTH 12 - -#define HW_PXP_S0BUF 0x50 - -#define HW_PXP_S0UBUF 0x60 - -#define HW_PXP_S0VBUF 0x70 - -#define HW_PXP_S0PARAM 0x80 -#define BM_PXP_S0PARAM_HEIGHT 0x000000FF -#define BP_PXP_S0PARAM_HEIGHT 0 -#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 -#define BP_PXP_S0PARAM_WIDTH 8 -#define BM_PXP_S0PARAM_YBASE 0x00FF0000 -#define BP_PXP_S0PARAM_YBASE 16 -#define BM_PXP_S0PARAM_XBASE 0xFF000000 -#define BP_PXP_S0PARAM_XBASE 24 - -#define HW_PXP_S0BACKGROUND 0x90 - -#define HW_PXP_S0CROP 0xA0 -#define BM_PXP_S0CROP_HEIGHT 0x000000FF -#define BP_PXP_S0CROP_HEIGHT 0 -#define BM_PXP_S0CROP_WIDTH 0x0000FF00 -#define BP_PXP_S0CROP_WIDTH 8 -#define BM_PXP_S0CROP_YBASE 0x00FF0000 -#define BP_PXP_S0CROP_YBASE 16 -#define BM_PXP_S0CROP_XBASE 0xFF000000 -#define BP_PXP_S0CROP_XBASE 24 - -#define HW_PXP_S0SCALE 0xB0 -#define BM_PXP_S0SCALE_XSCALE 0x00003FFF -#define BP_PXP_S0SCALE_XSCALE 0 -#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 -#define BP_PXP_S0SCALE_YSCALE 16 - -#define HW_PXP_CSCCOEFF0 0xD0 - -#define HW_PXP_CSCCOEFF1 0xE0 - -#define HW_PXP_CSCCOEFF2 0xF0 - -#define HW_PXP_S0COLORKEYLOW 0x180 - -#define HW_PXP_S0COLORKEYHIGH 0x190 - -#define HW_PXP_OL0 (0x200 + 0 * 0x40) -#define HW_PXP_OL1 (0x200 + 1 * 0x40) -#define HW_PXP_OL2 (0x200 + 2 * 0x40) -#define HW_PXP_OL3 (0x200 + 3 * 0x40) -#define HW_PXP_OL4 (0x200 + 4 * 0x40) -#define HW_PXP_OL5 (0x200 + 5 * 0x40) -#define HW_PXP_OL6 (0x200 + 6 * 0x40) -#define HW_PXP_OL7 (0x200 + 7 * 0x40) - -#define HW_PXP_OLn 0x200 - -#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40) -#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40) -#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40) -#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40) -#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40) -#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40) -#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40) -#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40) - -#define HW_PXP_OLnSIZE 0x210 -#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF -#define BP_PXP_OLnSIZE_HEIGHT 0 -#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 -#define BP_PXP_OLnSIZE_WIDTH 8 - -#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40) -#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40) -#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40) -#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40) -#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40) -#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40) -#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40) -#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40) - -#define HW_PXP_OLnPARAM 0x220 -#define BM_PXP_OLnPARAM_ENABLE 0x00000001 -#define BP_PXP_OLnPARAM_ENABLE 0 -#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 -#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 -#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 -#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 -#define BP_PXP_OLnPARAM_FORMAT 4 -#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 -#define BP_PXP_OLnPARAM_ALPHA 8 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h deleted file mode 100644 index b8dbd6742d9..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * stmp378x: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 -#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF -#define BP_RTC_PERSISTENT1_GENERAL 0 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h deleted file mode 100644 index 6df41762c2a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * stmp378x: SAIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SAIF_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h deleted file mode 100644 index 801539848c2..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp378x: SPDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) -#define REGS_SPDIF_PHYS 0x80054000 -#define REGS_SPDIF_SIZE 0x2000 - -#define HW_SPDIF_CTRL 0x0 -#define BM_SPDIF_CTRL_RUN 0x00000001 -#define BP_SPDIF_CTRL_RUN 0 -#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 -#define BM_SPDIF_CTRL_CLKGATE 0x40000000 -#define BM_SPDIF_CTRL_SFTRST 0x80000000 - -#define HW_SPDIF_STAT 0x10 - -#define HW_SPDIF_FRAMECTRL 0x20 - -#define HW_SPDIF_SRR 0x30 -#define BM_SPDIF_SRR_RATE 0x000FFFFF -#define BP_SPDIF_SRR_RATE 0 -#define BM_SPDIF_SRR_BASEMULT 0x70000000 -#define BP_SPDIF_SRR_BASEMULT 28 - -#define HW_SPDIF_DEBUG 0x40 - -#define HW_SPDIF_DATA 0x50 - -#define HW_SPDIF_VERSION 0x60 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h deleted file mode 100644 index 28aacf0f58e..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * stmp378x: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h deleted file mode 100644 index 08343a8b556..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: SYDMA register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000) -#define REGS_SYDMA_PHYS 0x80026000 -#define REGS_SYDMA_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h deleted file mode 100644 index b5527957c67..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * stmp378x: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) -#define REGS_TIMROT_PHYS 0x80068000 -#define REGS_TIMROT_SIZE 0x2000 - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 -#define BP_TIMROT_ROTCTRL_SELECT_A 0 -#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 -#define BP_TIMROT_ROTCTRL_SELECT_B 4 -#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 -#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 -#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 -#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 -#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 -#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 -#define BP_TIMROT_ROTCTRL_DIVIDER 16 -#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_ROTCOUNT 0x10 -#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF -#define BP_TIMROT_ROTCOUNT_UPDOWN 0 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h deleted file mode 100644 index 7f895cb3435..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * stmp378x: TVENC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000) -#define REGS_TVENC_PHYS 0x80038000 -#define REGS_TVENC_SIZE 0x2000 - -#define HW_TVENC_CTRL 0x0 -#define BM_TVENC_CTRL_CLKGATE 0x40000000 -#define BM_TVENC_CTRL_SFTRST 0x80000000 - -#define HW_TVENC_CONFIG 0x10 -#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 -#define BP_TVENC_CONFIG_ENCD_MODE 0 -#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 -#define BP_TVENC_CONFIG_SYNC_MODE 4 -#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 -#define BM_TVENC_CONFIG_CGAIN 0x0000C000 -#define BP_TVENC_CONFIG_CGAIN 14 -#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 -#define BP_TVENC_CONFIG_YGAIN_SEL 16 -#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000 - -#define HW_TVENC_SYNCOFFSET 0x30 - -#define HW_TVENC_COLORSUB0 0xC0 - -#define HW_TVENC_COLORBURST 0x140 -#define BM_TVENC_COLORBURST_PBA 0x00FF0000 -#define BP_TVENC_COLORBURST_PBA 16 -#define BM_TVENC_COLORBURST_NBA 0xFF000000 -#define BP_TVENC_COLORBURST_NBA 24 - -#define HW_TVENC_MACROVISION0 0x150 - -#define HW_TVENC_MACROVISION1 0x160 - -#define HW_TVENC_MACROVISION2 0x170 - -#define HW_TVENC_MACROVISION3 0x180 - -#define HW_TVENC_MACROVISION4 0x190 - -#define HW_TVENC_DACCTRL 0x1A0 -#define BM_TVENC_DACCTRL_RVAL 0x00000070 -#define BP_TVENC_DACCTRL_RVAL 4 -#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 -#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 -#define BM_TVENC_DACCTRL_GAINUP 0x00040000 -#define BM_TVENC_DACCTRL_GAINDN 0x00080000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h deleted file mode 100644 index a251e68bb3a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000) -#define REGS_UARTAPP2_PHYS 0x8006E000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb552a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h deleted file mode 100644 index 25112c1aa60..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 -#define REGS_USBCTRL_SIZE 0x2000 - -#define HW_USBCTRL_USBCMD 0x140 -#define BM_USBCTRL_USBCMD_RS 0x00000001 -#define BP_USBCTRL_USBCMD_RS 0 -#define BM_USBCTRL_USBCMD_RST 0x00000002 - -#define HW_USBCTRL_USBINTR 0x148 -#define BM_USBCTRL_USBINTR_UE 0x00000001 -#define BP_USBCTRL_USBINTR_UE 0 - -#define HW_USBCTRL_PORTSC1 0x184 -#define BM_USBCTRL_PORTSC1_PHCD 0x00800000 - -#define HW_USBCTRL_OTGSC 0x1A4 -#define BM_USBCTRL_OTGSC_ID 0x00000100 -#define BM_USBCTRL_OTGSC_IDIS 0x00010000 -#define BM_USBCTRL_OTGSC_IDIE 0x01000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h deleted file mode 100644 index 11f3b732dc9..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp378x: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) -#define REGS_USBPHY_PHYS 0x8007C000 -#define REGS_USBPHY_SIZE 0x2000 - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c deleted file mode 100644 index c2f9fe04c11..00000000000 --- a/arch/arm/mach-stmp378x/stmp378x.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Freescale STMP378X platform support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/dma-mapping.h> - -#include <asm/dma.h> -#include <asm/setup.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include <mach/pins.h> -#include <mach/pinmux.h> -#include <mach/dma.h> -#include <mach/hardware.h> -#include <mach/system.h> -#include <mach/platform.h> -#include <mach/stmp3xxx.h> -#include <mach/regs-icoll.h> -#include <mach/regs-apbh.h> -#include <mach/regs-apbx.h> -#include <mach/regs-pxp.h> -#include <mach/regs-i2c.h> - -#include "stmp378x.h" -/* - * IRQ handling - */ -static void stmp378x_ack_irq(struct irq_data *d) -{ - /* Tell ICOLL to release IRQ line */ - __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - - /* ACK current interrupt */ - __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */, - REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - -static void stmp378x_mask_irq(struct irq_data *d) -{ - /* IRQ disable */ - stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); -} - -static void stmp378x_unmask_irq(struct irq_data *d) -{ - /* IRQ enable */ - stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); -} - -static struct irq_chip stmp378x_chip = { - .irq_ack = stmp378x_ack_irq, - .irq_mask = stmp378x_mask_irq, - .irq_unmask = stmp378x_unmask_irq, -}; - -void __init stmp378x_init_irq(void) -{ - stmp3xxx_init_irq(&stmp378x_chip); -} - -/* - * DMA interrupt handling - */ -void stmp3xxx_arch_dma_enable_interrupt(int channel) -{ - void __iomem *c1, *c2; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c1 = REGS_APBH_BASE + HW_APBH_CTRL1; - c2 = REGS_APBH_BASE + HW_APBH_CTRL2; - break; - - case STMP3XXX_BUS_APBX: - c1 = REGS_APBX_BASE + HW_APBX_CTRL1; - c2 = REGS_APBX_BASE + HW_APBX_CTRL2; - break; - - default: - return; - } - stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1); - stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); - -void stmp3xxx_arch_dma_clear_interrupt(int channel) -{ - void __iomem *c1, *c2; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c1 = REGS_APBH_BASE + HW_APBH_CTRL1; - c2 = REGS_APBH_BASE + HW_APBH_CTRL2; - break; - - case STMP3XXX_BUS_APBX: - c1 = REGS_APBX_BASE + HW_APBX_CTRL1; - c2 = REGS_APBX_BASE + HW_APBX_CTRL2; - break; - - default: - return; - } - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1); - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); - -int stmp3xxx_arch_dma_is_interrupt(int channel) -{ - int r = 0; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - - case STMP3XXX_BUS_APBX: - r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); - -void stmp3xxx_arch_dma_reset_channel(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - void __iomem *c0; - u32 mask; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c0 = REGS_APBH_BASE + HW_APBH_CTRL0; - mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL; - break; - case STMP3XXX_BUS_APBX: - c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL; - mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL; - break; - default: - return; - } - - /* Reset channel and wait for it to complete */ - stmp3xxx_setl(mask, c0); - while (__raw_readl(c0) & mask) - cpu_relax(); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); - -void stmp3xxx_arch_dma_freeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - u32 mask = 1 << chbit; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); - -void stmp3xxx_arch_dma_unfreeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - u32 mask = 1 << chbit; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); - -/* - * The registers are all very closely mapped, so we might as well map them all - * with a single mapping - * - * Logical Physical - * f0000000 80000000 On-chip registers - * f1000000 00000000 32k on-chip SRAM - */ - -static struct map_desc stmp378x_io_desc[] __initdata = { - { - .virtual = (u32)STMP3XXX_REGS_BASE, - .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), - .length = STMP3XXX_REGS_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (u32)STMP3XXX_OCRAM_BASE, - .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), - .length = STMP3XXX_OCRAM_SIZE, - .type = MT_DEVICE, - }, -}; - - -static u64 common_dmamask = DMA_BIT_MASK(32); - -/* - * devices that are present only on stmp378x, not on all 3xxx boards: - * PxP - * I2C - */ -static struct resource pxp_resource[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_PXP_PHYS, - .end = REGS_PXP_PHYS + REGS_PXP_SIZE, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_PXP, - .end = IRQ_PXP, - }, -}; - -struct platform_device stmp378x_pxp = { - .name = "stmp3xxx-pxp", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(pxp_resource), - .resource = pxp_resource, -}; - -static struct resource i2c_resources[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_I2C_ERROR, - .end = IRQ_I2C_ERROR, - }, { - .flags = IORESOURCE_MEM, - .start = REGS_I2C_PHYS, - .end = REGS_I2C_PHYS + REGS_I2C_SIZE, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), - }, -}; - -struct platform_device stmp378x_i2c = { - .name = "i2c_stmp3xxx", - .id = 0, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = i2c_resources, - .num_resources = ARRAY_SIZE(i2c_resources), -}; - -void __init stmp378x_map_io(void) -{ - iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc)); -} diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h deleted file mode 100644 index 0dc15b3c891..00000000000 --- a/arch/arm/mach-stmp378x/stmp378x.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X internal functions and data declarations - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_STMP378X_H -#define __MACH_STMP378X_H - -void stmp378x_map_io(void); -void stmp378x_init_irq(void); - -extern struct platform_device stmp378x_pxp, stmp378x_i2c; -#endif /* __MACH_STMP378X_COMMON_H */ diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c deleted file mode 100644 index 06158848afd..00000000000 --- a/arch/arm/mach-stmp378x/stmp378x_devb.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Freescale STMP378X development board support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/spi/spi.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/pins.h> -#include <mach/pinmux.h> -#include <mach/platform.h> -#include <mach/stmp3xxx.h> -#include <mach/mmc.h> -#include <mach/gpmi.h> - -#include "stmp378x.h" - -static struct platform_device *devices[] = { - &stmp3xxx_dbguart, - &stmp3xxx_appuart, - &stmp3xxx_watchdog, - &stmp3xxx_touchscreen, - &stmp3xxx_rtc, - &stmp3xxx_keyboard, - &stmp3xxx_framebuffer, - &stmp3xxx_backlight, - &stmp3xxx_rotdec, - &stmp3xxx_persistent, - &stmp3xxx_dcp_bootstream, - &stmp3xxx_dcp, - &stmp3xxx_battery, - &stmp378x_pxp, - &stmp378x_i2c, -}; - -static struct pin_desc i2c_pins_desc[] = { - { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, -}; - -static struct pin_group i2c_pins = { - .pins = i2c_pins_desc, - .nr_pins = ARRAY_SIZE(i2c_pins_desc), -}; - -static struct pin_desc dbguart_pins_0[] = { - { PINID_PWM0, PIN_FUN3, }, - { PINID_PWM1, PIN_FUN3, }, -}; - -static struct pin_group dbguart_pins[] = { - [0] = { - .pins = dbguart_pins_0, - .nr_pins = ARRAY_SIZE(dbguart_pins_0), - }, -}; - -static int dbguart_pins_control(int id, int request) -{ - int r = 0; - - if (request) - r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); - else - stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); - return r; -} - -static struct pin_desc appuart_pins_0[] = { - { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -}; - -static struct pin_desc appuart_pins_1[] = { -#if 0 /* enable these when second appuart will be connected */ - { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -#endif -}; - -static struct pin_desc mmc_pins_desc[] = { - { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, - { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, -}; - -static struct pin_group mmc_pins = { - .pins = mmc_pins_desc, - .nr_pins = ARRAY_SIZE(mmc_pins_desc), -}; - -static int stmp3xxxmmc_get_wp(void) -{ - return gpio_get_value(PINID_PWM4); -} - -static int stmp3xxxmmc_hw_init_ssp1(void) -{ - int ret; - - ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc"); - if (ret) - goto out; - - /* Configure write protect GPIO pin */ - ret = gpio_request(PINID_PWM4, "mmc wp"); - if (ret) - goto out_wp; - - gpio_direction_input(PINID_PWM4); - - /* Configure POWER pin as gpio to drive power to MMC slot */ - ret = gpio_request(PINID_PWM3, "mmc power"); - if (ret) - goto out_power; - - gpio_direction_output(PINID_PWM3, 0); - mdelay(100); - - return 0; - -out_power: - gpio_free(PINID_PWM4); -out_wp: - stmp3xxx_release_pin_group(&mmc_pins, "mmc"); -out: - return ret; -} - -static void stmp3xxxmmc_hw_release_ssp1(void) -{ - gpio_free(PINID_PWM3); - gpio_free(PINID_PWM4); - stmp3xxx_release_pin_group(&mmc_pins, "mmc"); -} - -static void stmp3xxxmmc_cmd_pullup_ssp1(int enable) -{ - stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc"); -} - -static unsigned long -stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz) -{ - struct clk *ssp, *parent; - char *p; - long r; - - ssp = clk_get(NULL, "ssp"); - - /* using SSP1, no timeout, clock rate 1 */ - writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) | - BF(0xFFFF, SSP_TIMING_TIMEOUT), - base + HW_SSP_TIMING); - - p = (hz > 1000000) ? "io" : "osc_24M"; - parent = clk_get(NULL, p); - clk_set_parent(ssp, parent); - r = clk_set_rate(ssp, 2 * hz / 1000); - clk_put(parent); - clk_put(ssp); - - return hz; -} - -static struct stmp3xxxmmc_platform_data mmc_data = { - .hw_init = stmp3xxxmmc_hw_init_ssp1, - .hw_release = stmp3xxxmmc_hw_release_ssp1, - .get_wp = stmp3xxxmmc_get_wp, - .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1, - .setclock = stmp3xxxmmc_setclock_ssp1, -}; - - -static struct pin_group appuart_pins[] = { - [0] = { - .pins = appuart_pins_0, - .nr_pins = ARRAY_SIZE(appuart_pins_0), - }, - [1] = { - .pins = appuart_pins_1, - .nr_pins = ARRAY_SIZE(appuart_pins_1), - }, -}; - -static struct pin_desc ssp1_pins_desc[] = { - { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, }, - { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, - { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, - { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, -}; - -static struct pin_desc ssp2_pins_desc[] = { - { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, }, - { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, - { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, - { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, -}; - -static struct pin_group ssp1_pins = { - .pins = ssp1_pins_desc, - .nr_pins = ARRAY_SIZE(ssp1_pins_desc), -}; - -static struct pin_group ssp2_pins = { - .pins = ssp1_pins_desc, - .nr_pins = ARRAY_SIZE(ssp2_pins_desc), -}; - -static struct pin_desc gpmi_pins_desc[] = { - { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, -}; - -static struct pin_group gpmi_pins = { - .pins = gpmi_pins_desc, - .nr_pins = ARRAY_SIZE(gpmi_pins_desc), -}; - -static struct mtd_partition gpmi_partitions[] = { - [0] = { - .name = "boot", - .size = 10 * SZ_1M, - .offset = 0, - }, - [1] = { - .name = "data", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct gpmi_platform_data gpmi_data = { - .pins = &gpmi_pins, - .nr_parts = ARRAY_SIZE(gpmi_partitions), - .parts = gpmi_partitions, - .part_types = { "cmdline", NULL }, -}; - -static struct spi_board_info spi_board_info[] __initdata = { -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - { - .modalias = "enc28j60", - .max_speed_hz = 6 * 1000 * 1000, - .bus_num = 1, - .chip_select = 0, - .platform_data = NULL, - }, -#endif -}; - -static void __init stmp378x_devb_init(void) -{ - stmp3xxx_pinmux_init(NR_REAL_IRQS); - - /* init stmp3xxx platform */ - stmp3xxx_init(); - - stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; - stmp3xxx_appuart.dev.platform_data = appuart_pins; - stmp3xxx_mmc.dev.platform_data = &mmc_data; - stmp3xxx_gpmi.dev.platform_data = &gpmi_data; - stmp3xxx_spi1.dev.platform_data = &ssp1_pins; - stmp3xxx_spi2.dev.platform_data = &ssp2_pins; - stmp378x_i2c.dev.platform_data = &i2c_pins; - - /* register spi devices */ - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - - /* add board's devices */ - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* add devices selected by command line ssp1= and ssp2= options */ - stmp3xxx_ssp1_device_register(); - stmp3xxx_ssp2_device_register(); -} - -MACHINE_START(STMP378X, "STMP378X") - .boot_params = 0x40000100, - .map_io = stmp378x_map_io, - .init_irq = stmp378x_init_irq, - .timer = &stmp3xxx_timer, - .init_machine = stmp378x_devb_init, -MACHINE_END diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile deleted file mode 100644 index 57deffd09fb..00000000000 --- a/arch/arm/mach-stmp37xx/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o -obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot deleted file mode 100644 index 1568ad404d5..00000000000 --- a/arch/arm/mach-stmp37xx/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x40008000 -params_phys-y := 0x40000100 -initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S deleted file mode 100644 index fed2787b6c3..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP37XX - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT - cmp \irqnr, #0x3f - movne \irqstat, #0 @ Ack this IRQ - strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h deleted file mode 100644 index 98f12938550..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/irqs.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Freescale STMP37XX interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef _ASM_ARCH_IRQS_H -#define _ASM_ARCH_IRQS_H - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_RESERVED_55 55 -#define IRQ_RESERVED_56 56 -#define IRQ_RESERVED_57 57 -#define IRQ_RESERVED_58 58 -#define IRQ_RESERVED_59 59 -#define SW_IRQ_60 60 -#define SW_IRQ_61 61 -#define SW_IRQ_62 62 -#define SW_IRQ_63 63 - -#define NR_REAL_IRQS 64 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* TIMER and BRNOUT are FIQ capable */ -#define FIQ_START IRQ_TIMER0 - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION - -#endif /* _ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h deleted file mode 100644 index d56de0c471d..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/pins.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Freescale STMP37XX SoC pin multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16) -#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17) -#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22) -#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_UART2_CTS STMP3XXX_PINID(0, 26) -#define PINID_UART2_RTS STMP3XXX_PINID(0, 27) -#define PINID_UART2_RX STMP3XXX_PINID(0, 28) -#define PINID_UART2_TX STMP3XXX_PINID(0, 29) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 16) -#define PINID_LCD_RS STMP3XXX_PINID(1, 17) -#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18) -#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19) -#define PINID_LCD_CS STMP3XXX_PINID(1, 20) -#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21) -#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22) -#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27) -#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28) - -/* Bank 2 */ -#define PINID_PWM0 STMP3XXX_PINID(2, 0) -#define PINID_PWM1 STMP3XXX_PINID(2, 1) -#define PINID_PWM2 STMP3XXX_PINID(2, 2) -#define PINID_PWM3 STMP3XXX_PINID(2, 3) -#define PINID_PWM4 STMP3XXX_PINID(2, 4) -#define PINID_I2C_SCL STMP3XXX_PINID(2, 5) -#define PINID_I2C_SDA STMP3XXX_PINID(2, 6) -#define PINID_ROTTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 9) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 10) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 11) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13) -#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14) -#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 21) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 22) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 23) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 24) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 25) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 26) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 27) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 28) -#define PINID_EMI_A13 STMP3XXX_PINID(2, 29) -#define PINID_EMI_A14 STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h deleted file mode 100644 index a323aa9a21f..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * stmp37xx: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_DEVSEL 0x20 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BM_APBH_CHn_CMD_MODE 0x00000003 -#define BP_APBH_CHn_CMD_MODE 0x00000001 -#define BV_APBH_CHn_CMD_MODE_NOOP 0 -#define BV_APBH_CHn_CMD_MODE_WRITE 1 -#define BV_APBH_CHn_CMD_MODE_READ 2 -#define BV_APBH_CHn_CMD_MODE_SENSE 3 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h deleted file mode 100644 index 6d080cd5b70..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * stmp37xx: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBX_CTRL0_RESET_CHANNEL 16 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_DEVSEL 0x20 - -#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x50 -#define BM_APBX_CHn_CMD_MODE 0x00000003 -#define BP_APBX_CHn_CMD_MODE 0x00000001 -#define BV_APBX_CHn_CMD_MODE_NOOP 0 -#define BV_APBX_CHn_CMD_MODE_WRITE 1 -#define BV_APBX_CHn_CMD_MODE_READ 2 -#define BV_APBX_CHn_CMD_MODE_SENSE 3 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x70 - -#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x80 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h deleted file mode 100644 index 3b511f947a5..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * stmp37xx: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h deleted file mode 100644 index ca1942b8a3e..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * stmp37xx: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_LINEOUTCTRL 0x100 -#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F -#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0 -#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00 -#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8 -#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000 -#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12 -#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000 -#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20 -#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000 -#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h deleted file mode 100644 index 47f5c92fdaf..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * stmp37xx: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00007FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_FRAC 0xD0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_CLKSEQ 0xE0 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0xF0 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h deleted file mode 100644 index ba1bbe265c2..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * stmp37xx: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h deleted file mode 100644 index 3b6d990a3af..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp37xx: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h deleted file mode 100644 index f2b304f5449..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp37xx: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000 -#define BP_GPMI_CTRL1_DSAMPLE_TIME 12 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h deleted file mode 100644 index 35882a9b8bc..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp37xx: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h deleted file mode 100644 index 3b7c92239e2..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * stmp37xx: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x30 - -#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10) -#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10) -#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10) -#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10) - -#define HW_ICOLL_PRIORITYn 0x60 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h deleted file mode 100644 index 72514e8b073..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * stmp37xx: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_COUNT 0x0000FFFF -#define BP_LCDIF_CTRL_COUNT 0 -#define BM_LCDIF_CTRL_RUN 0x00010000 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000 -#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000 -#define BP_LCDIF_CTRL_DATA_SWIZZLE 21 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 - -#define HW_LCDIF_TIMING 0x20 - -#define HW_LCDIF_VDCTRL0 0x30 -#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF -#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x40 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000 -#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20 - -#define HW_LCDIF_VDCTRL2 0x50 -#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF -#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800 -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23 - -#define HW_LCDIF_VDCTRL3 0x60 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12 -#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h deleted file mode 100644 index cc7b4702d1c..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * stmp37xx: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h deleted file mode 100644 index d5efce2388c..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp37xx: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x300 -#define HW_PINCTRL_PULL1 0x310 -#define HW_PINCTRL_PULL2 0x320 -#define HW_PINCTRL_PULL3 0x330 - -#define HW_PINCTRL_DOUT0 0x400 -#define HW_PINCTRL_DOUT1 0x410 -#define HW_PINCTRL_DOUT2 0x420 - -#define HW_PINCTRL_DIN0 0x500 -#define HW_PINCTRL_DIN1 0x510 -#define HW_PINCTRL_DIN2 0x520 - -#define HW_PINCTRL_DOE0 0x600 -#define HW_PINCTRL_DOE1 0x610 -#define HW_PINCTRL_DOE2 0x620 - -#define HW_PINCTRL_PIN2IRQ0 0x700 -#define HW_PINCTRL_PIN2IRQ1 0x710 -#define HW_PINCTRL_PIN2IRQ2 0x720 - -#define HW_PINCTRL_IRQEN0 0x800 -#define HW_PINCTRL_IRQEN1 0x810 -#define HW_PINCTRL_IRQEN2 0x820 - -#define HW_PINCTRL_IRQLEVEL0 0x900 -#define HW_PINCTRL_IRQLEVEL1 0x910 -#define HW_PINCTRL_IRQLEVEL2 0x920 - -#define HW_PINCTRL_IRQPOL0 0xA00 -#define HW_PINCTRL_IRQPOL1 0xA10 -#define HW_PINCTRL_IRQPOL2 0xA20 - -#define HW_PINCTRL_IRQSTAT0 0xB00 -#define HW_PINCTRL_IRQSTAT1 0xB10 -#define HW_PINCTRL_IRQSTAT2 0xB20 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h deleted file mode 100644 index 0e733d74a22..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp37xx: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xB0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000100 - -#define HW_POWER_RESET 0xE0 - -#define HW_POWER_DEBUG 0xF0 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h deleted file mode 100644 index 15966a1b62e..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * stmp37xx: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h deleted file mode 100644 index fac40edc38a..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * stmp37xx: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h deleted file mode 100644 index cbde891a06c..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp37xx: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h deleted file mode 100644 index 4af0f6edfa7..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp37xx: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h deleted file mode 100644 index 0594275d860..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * stmp37xx: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb552a..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h deleted file mode 100644 index 9145e22df32..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * stmp37xx: USBCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTL_PHYS 0x80000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h deleted file mode 100644 index 1a2ae9cbdfe..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * stmp37xx: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h deleted file mode 100644 index b7fce0fbc56..00000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp37xx: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001 -#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c deleted file mode 100644 index a9aed06ff37..00000000000 --- a/arch/arm/mach-stmp37xx/stmp37xx.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Freescale STMP37XX platform support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include <mach/stmp3xxx.h> -#include <mach/dma.h> - -#include <mach/platform.h> -#include <mach/regs-icoll.h> -#include <mach/regs-apbh.h> -#include <mach/regs-apbx.h> -#include "stmp37xx.h" - -/* - * IRQ handling - */ -static void stmp37xx_ack_irq(struct irq_data *d) -{ - /* Disable IRQ */ - stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); - - /* ACK current interrupt */ - __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - -static void stmp37xx_mask_irq(struct irq_data *d) -{ - /* IRQ disable */ - stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); -} - -static void stmp37xx_unmask_irq(struct irq_data *d) -{ - /* IRQ enable */ - stmp3xxx_setl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); -} - -static struct irq_chip stmp37xx_chip = { - .irq_ack = stmp37xx_ack_irq, - .irq_mask = stmp37xx_mask_irq, - .irq_unmask = stmp37xx_unmask_irq, -}; - -void __init stmp37xx_init_irq(void) -{ - stmp3xxx_init_irq(&stmp37xx_chip); -} - -/* - * DMA interrupt handling - */ -void stmp3xxx_arch_dma_enable_interrupt(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), - REGS_APBH_BASE + HW_APBH_CTRL1); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), - REGS_APBX_BASE + HW_APBX_CTRL1); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); - -void stmp3xxx_arch_dma_clear_interrupt(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), - REGS_APBH_BASE + HW_APBH_CTRL1); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), - REGS_APBX_BASE + HW_APBX_CTRL1); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); - -int stmp3xxx_arch_dma_is_interrupt(int channel) -{ - int r = 0; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - - case STMP3XXX_BUS_APBX: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); - -void stmp3xxx_arch_dma_reset_channel(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - /* Reset channel and wait for it to complete */ - stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL, - REGS_APBH_BASE + HW_APBH_CTRL0); - while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) & - (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) - cpu_relax(); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL, - REGS_APBX_BASE + HW_APBX_CTRL0); - while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) & - (chbit << BP_APBX_CTRL0_RESET_CHANNEL)) - cpu_relax(); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); - -void stmp3xxx_arch_dma_freeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); - -void stmp3xxx_arch_dma_unfreeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); - -/* - * The registers are all very closely mapped, so we might as well map them all - * with a single mapping - * - * Logical Physical - * f0000000 80000000 On-chip registers - * f1000000 00000000 32k on-chip SRAM - */ -static struct map_desc stmp37xx_io_desc[] __initdata = { - { - .virtual = (u32)STMP3XXX_REGS_BASE, - .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), - .length = SZ_1M, - .type = MT_DEVICE - }, - { - .virtual = (u32)STMP3XXX_OCRAM_BASE, - .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), - .length = STMP3XXX_OCRAM_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init stmp37xx_map_io(void) -{ - iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc)); -} diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h deleted file mode 100644 index 0b75fb796a6..00000000000 --- a/arch/arm/mach-stmp37xx/stmp37xx.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X internal functions and data declarations - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_STMP37XX_H -#define __MACH_STMP37XX_H - -void stmp37xx_map_io(void); -void stmp37xx_init_irq(void); - -#endif /* __MACH_STMP37XX_H */ diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c deleted file mode 100644 index 311d8552d36..00000000000 --- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Freescale STMP37XX development board support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/stmp3xxx.h> -#include <mach/pins.h> -#include <mach/pinmux.h> -#include "stmp37xx.h" - -/* - * List of STMP37xx development board specific devices - */ -static struct platform_device *stmp37xx_devb_devices[] = { - &stmp3xxx_dbguart, - &stmp3xxx_appuart, -}; - -static struct pin_desc dbguart_pins_0[] = { - { PINID_PWM0, PIN_FUN3, }, - { PINID_PWM1, PIN_FUN3, }, -}; - -struct pin_desc appuart_pins_0[] = { - { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -}; - -static struct pin_group appuart_pins[] = { - [0] = { - .pins = appuart_pins_0, - .nr_pins = ARRAY_SIZE(appuart_pins_0), - }, - /* 37xx has the only app uart */ -}; - -static struct pin_group dbguart_pins[] = { - [0] = { - .pins = dbguart_pins_0, - .nr_pins = ARRAY_SIZE(dbguart_pins_0), - }, -}; - -static int dbguart_pins_control(int id, int request) -{ - int r = 0; - - if (request) - r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); - else - stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); - return r; -} - - -static void __init stmp37xx_devb_init(void) -{ - stmp3xxx_pinmux_init(NR_REAL_IRQS); - - /* Init STMP3xxx platform */ - stmp3xxx_init(); - - stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; - stmp3xxx_appuart.dev.platform_data = appuart_pins; - - /* Add STMP37xx development board devices */ - platform_add_devices(stmp37xx_devb_devices, - ARRAY_SIZE(stmp37xx_devb_devices)); -} - -MACHINE_START(STMP37XX, "STMP37XX") - .boot_params = 0x40000100, - .map_io = stmp37xx_map_io, - .init_irq = stmp37xx_init_irq, - .timer = &stmp3xxx_timer, - .init_machine = stmp37xx_devb_init, -MACHINE_END diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c index aa9231f4fc6..209fa5c65d4 100644 --- a/arch/arm/mach-tcc8k/irq.c +++ b/arch/arm/mach-tcc8k/irq.c @@ -102,10 +102,10 @@ void __init tcc8k_init_irq(void) for (irqno = 0; irqno < NR_IRQS; irqno++) { if (irqno < 32) - set_irq_chip(irqno, &tcc8000_irq_chip0); + irq_set_chip(irqno, &tcc8000_irq_chip0); else - set_irq_chip(irqno, &tcc8000_irq_chip1); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip(irqno, &tcc8000_irq_chip1); + irq_set_handler(irqno, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c index e0a8d609afe..a96babe8377 100644 --- a/arch/arm/mach-tcc8k/time.c +++ b/arch/arm/mach-tcc8k/time.c @@ -25,19 +25,6 @@ static void __iomem *timer_base; -static cycle_t tcc_get_cycles(struct clocksource *cs) -{ - return __raw_readl(timer_base + TC32MCNT_OFFS); -} - -static struct clocksource clocksource_tcc = { - .name = "tcc_tc32", - .rating = 200, - .read = tcc_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int tcc_set_next_event(unsigned long evt, struct clock_event_device *unused) { @@ -102,7 +89,8 @@ static int __init tcc_clockevent_init(struct clk *clock) { unsigned int c = clk_get_rate(clock); - clocksource_register_hz(&clocksource_tcc, c); + clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c, + 200, 32, clocksource_mmio_readl_up); clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, clockevent_tcc.shift); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 3cdeffc97b4..5ec1846aa1d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -27,12 +27,14 @@ comment "Tegra board type" config MACH_HARMONY bool "Harmony board" + select MACH_HAS_SND_SOC_TEGRA_WM8903 help Support for nVidia Harmony development platform config MACH_KAEN bool "Kaen board" select MACH_SEABOARD + select MACH_HAS_SND_SOC_TEGRA_WM8903 help Support for the Kaen version of Seaboard @@ -43,6 +45,7 @@ config MACH_PAZ00 config MACH_SEABOARD bool "Seaboard board" + select MACH_HAS_SND_SOC_TEGRA_WM8903 help Support for nVidia Seaboard development platform. It will also be included for some of the derivative boards that diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 1afe05038c2..823c703e573 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,7 +1,7 @@ obj-y += common.o obj-y += devices.o obj-y += io.o -obj-y += irq.o legacy_irq.o +obj-y += irq.o obj-y += clock.o obj-y += timer.o obj-y += gpio.o diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index 75c918a86a3..30e18bc6064 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -34,7 +34,7 @@ #include <asm/mach/time.h> #include <asm/setup.h> -#include <mach/harmony_audio.h> +#include <mach/tegra_wm8903_pdata.h> #include <mach/iomap.h> #include <mach/irqs.h> #include <mach/sdhci.h> @@ -67,15 +67,16 @@ static struct platform_device debug_uart = { }, }; -static struct harmony_audio_platform_data harmony_audio_pdata = { +static struct tegra_wm8903_platform_data harmony_audio_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, + .gpio_hp_mute = -1, .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, }; static struct platform_device harmony_audio_device = { - .name = "tegra-snd-harmony", + .name = "tegra-snd-wm8903", .id = 0, .dev = { .platform_data = &harmony_audio_pdata, diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c index e945ae28ee7..f4ef5eb317b 100644 --- a/arch/arm/mach-tegra/dma.c +++ b/arch/arm/mach-tegra/dma.c @@ -223,7 +223,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, * - Change the source selector to invalid to stop the DMA from * FIFO to memory. * - Read the status register to know the number of pending - * bytes to be transfered. + * bytes to be transferred. * - Finally stop or program the DMA to the next buffer in the * list. */ @@ -244,7 +244,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch, if (status & STA_BUSY) req->bytes_transferred -= to_transfer; - /* In continous transfer mode, DMA only tracks the count of the + /* In continuous transfer mode, DMA only tracks the count of the * half DMA buffer. So, if the DMA already finished half the DMA * then add the half buffer to the completed count. * diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 12090a2cf3e..919d6383773 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c @@ -24,6 +24,8 @@ #include <linux/io.h> #include <linux/gpio.h> +#include <asm/mach/irq.h> + #include <mach/iomap.h> #include <mach/suspend.h> @@ -208,9 +210,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_unlock_irqrestore(&bank->lvl_lock[port], flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __set_irq_handler_unlocked(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __set_irq_handler_unlocked(d->irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); return 0; } @@ -221,10 +223,11 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) int port; int pin; int unmasked = 0; + struct irq_chip *chip = irq_desc_get_chip(desc); - desc->irq_data.chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); - bank = get_irq_data(irq); + bank = irq_get_handler_data(irq); for (port = 0; port < 4; port++) { int gpio = tegra_gpio_compose(bank->bank, port, 0); @@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) */ if (lvl & (0x100 << pin)) { unmasked = 1; - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } generic_handle_irq(gpio_to_irq(gpio + pin)); @@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) } if (!unmasked) - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } @@ -257,7 +260,8 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) void tegra_gpio_resume(void) { unsigned long flags; - int b, p, i; + int b; + int p; local_irq_save(flags); @@ -275,31 +279,13 @@ void tegra_gpio_resume(void) } local_irq_restore(flags); - - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc || (desc->status & IRQ_WAKEUP)) - continue; - enable_irq(i); - } } void tegra_gpio_suspend(void) { unsigned long flags; - int b, p, i; - - for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { - struct irq_desc *desc = irq_to_desc(i); - if (!desc) - continue; - if (desc->status & IRQ_WAKEUP) { - int gpio = i - INT_GPIO_BASE; - pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7); - continue; - } - disable_irq(i); - } + int b; + int p; local_irq_save(flags); for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { @@ -320,7 +306,7 @@ void tegra_gpio_suspend(void) static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) { struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); - return set_irq_wake(bank->irq, enable); + return irq_set_irq_wake(bank->irq, enable); } #endif @@ -359,18 +345,18 @@ static int __init tegra_gpio_init(void) for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; - lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); - set_irq_chip_data(i, bank); - set_irq_chip(i, &tegra_gpio_irq_chip); - set_irq_handler(i, handle_simple_irq); + irq_set_lockdep_class(i, &gpio_lock_class); + irq_set_chip_data(i, bank); + irq_set_chip_and_handler(i, &tegra_gpio_irq_chip, + handle_simple_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { bank = &tegra_gpio_banks[i]; - set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); + irq_set_handler_data(bank->irq, bank); for (j = 0; j < 4; j++) spin_lock_init(&bank->lvl_lock[j]); diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h index cc115174899..425b42e91ef 100644 --- a/arch/arm/mach-tegra/include/mach/barriers.h +++ b/arch/arm/mach-tegra/include/mach/barriers.h @@ -23,7 +23,7 @@ #include <asm/outercache.h> -#define rmb() dmb() +#define rmb() dsb() #define wmb() do { dsb(); outer_sync(); } while (0) #define mb() wmb() diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h index 39011bd9a92..d0132e8031a 100644 --- a/arch/arm/mach-tegra/include/mach/dma.h +++ b/arch/arm/mach-tegra/include/mach/dma.h @@ -92,11 +92,11 @@ struct tegra_dma_req { /* This is a called from the DMA ISR context when the DMA is still in * progress and is actively filling same buffer. * - * In case of continous mode receive, this threshold is 1/2 the buffer + * In case of continuous mode receive, this threshold is 1/2 the buffer * size. In other cases, this will not even be called as there is no * hardware support for it. * - * In the case of continous mode receive, if there is next req already + * In the case of continuous mode receive, if there is next req already * queued, DMA programs the HW to use that req when this req is * completed. If there is no "next req" queued, then DMA ISR doesn't do * anything before calling this callback. diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h deleted file mode 100644 index d898c0e3d90..00000000000 --- a/arch/arm/mach-tegra/include/mach/legacy_irq.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/legacy_irq.h - * - * Copyright (C) 2010 Google, Inc. - * Author: Colin Cross <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H -#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H - -void tegra_legacy_mask_irq(unsigned int irq); -void tegra_legacy_unmask_irq(unsigned int irq); -void tegra_legacy_select_fiq(unsigned int irq, bool fiq); -void tegra_legacy_force_irq_set(unsigned int irq); -void tegra_legacy_force_irq_clr(unsigned int irq); -int tegra_legacy_force_irq_status(unsigned int irq); -void tegra_legacy_select_fiq(unsigned int irq, bool fiq); -unsigned long tegra_legacy_vfiq(int nr); -unsigned long tegra_legacy_class(int nr); -int tegra_legacy_irq_set_wake(int irq, int enable); -void tegra_legacy_irq_set_lp1_wake_mask(void); -void tegra_legacy_irq_restore_mask(void); -void tegra_init_legacy_irq(void); - -#endif diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h deleted file mode 100644 index c8221b38ee7..00000000000 --- a/arch/arm/mach-tegra/include/mach/smp.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-tegra/include/mach/harmony_audio.h b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h index af086500ab7..9d293344a7f 100644 --- a/arch/arm/mach-tegra/include/mach/harmony_audio.h +++ b/arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/harmony_audio.h + * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h * * Copyright 2011 NVIDIA, Inc. * @@ -14,9 +14,10 @@ * */ -struct harmony_audio_platform_data { +struct tegra_wm8903_platform_data { int gpio_spkr_en; int gpio_hp_det; + int gpio_hp_mute; int gpio_int_mic_en; int gpio_ext_mic_en; }; diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index dfbc219ea49..4956c3cea73 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -1,8 +1,8 @@ /* - * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2011 Google, Inc. * * Author: - * Colin Cross <ccross@google.com> + * Colin Cross <ccross@android.com> * * Copyright (C) 2010, NVIDIA Corporation * @@ -18,8 +18,6 @@ */ #include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> @@ -27,135 +25,110 @@ #include <asm/hardware/gic.h> #include <mach/iomap.h> -#include <mach/legacy_irq.h> -#include <mach/suspend.h> #include "board.h" -#define PMC_CTRL 0x0 -#define PMC_CTRL_LATCH_WAKEUPS (1 << 5) -#define PMC_WAKE_MASK 0xc -#define PMC_WAKE_LEVEL 0x10 -#define PMC_WAKE_STATUS 0x14 -#define PMC_SW_WAKE_STATUS 0x18 -#define PMC_DPD_SAMPLE 0x20 +#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) +#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) +#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) + +#define ICTLR_CPU_IEP_VFIQ 0x08 +#define ICTLR_CPU_IEP_FIR 0x14 +#define ICTLR_CPU_IEP_FIR_SET 0x18 +#define ICTLR_CPU_IEP_FIR_CLR 0x1c + +#define ICTLR_CPU_IER 0x20 +#define ICTLR_CPU_IER_SET 0x24 +#define ICTLR_CPU_IER_CLR 0x28 +#define ICTLR_CPU_IEP_CLASS 0x2C + +#define ICTLR_COP_IER 0x30 +#define ICTLR_COP_IER_SET 0x34 +#define ICTLR_COP_IER_CLR 0x38 +#define ICTLR_COP_IEP_CLASS 0x3c + +#define NUM_ICTLRS 4 +#define FIRST_LEGACY_IRQ 32 + +static void __iomem *ictlr_reg_base[] = { + IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), + IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), +}; -static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); +static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) +{ + void __iomem *base; + u32 mask; -static u32 tegra_lp0_wake_enb; -static u32 tegra_lp0_wake_level; -static u32 tegra_lp0_wake_level_any; + BUG_ON(irq < FIRST_LEGACY_IRQ || + irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32); -static void (*tegra_gic_mask_irq)(struct irq_data *d); -static void (*tegra_gic_unmask_irq)(struct irq_data *d); -static void (*tegra_gic_ack_irq)(struct irq_data *d); + base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; + mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); -/* ensures that sufficient time is passed for a register write to - * serialize into the 32KHz domain */ -static void pmc_32kwritel(u32 val, unsigned long offs) -{ - writel(val, pmc + offs); - udelay(130); + __raw_writel(mask, base + reg); } -int tegra_set_lp1_wake(int irq, int enable) +static void tegra_mask(struct irq_data *d) { - return tegra_legacy_irq_set_wake(irq, enable); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR); } -void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) +static void tegra_unmask(struct irq_data *d) { - u32 temp; - u32 status; - u32 lvl; - - wake_level &= wake_enb; - wake_any &= wake_enb; + if (d->irq < FIRST_LEGACY_IRQ) + return; - wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); - wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb); - - wake_enb |= tegra_lp0_wake_enb; - - pmc_32kwritel(0, PMC_SW_WAKE_STATUS); - temp = readl(pmc + PMC_CTRL); - temp |= PMC_CTRL_LATCH_WAKEUPS; - pmc_32kwritel(temp, PMC_CTRL); - temp &= ~PMC_CTRL_LATCH_WAKEUPS; - pmc_32kwritel(temp, PMC_CTRL); - status = readl(pmc + PMC_SW_WAKE_STATUS); - lvl = readl(pmc + PMC_WAKE_LEVEL); - - /* flip the wakeup trigger for any-edge triggered pads - * which are currently asserting as wakeups */ - lvl ^= status; - lvl &= wake_any; - - wake_level |= lvl; - - writel(wake_level, pmc + PMC_WAKE_LEVEL); - /* Enable DPD sample to trigger sampling pads data and direction - * in which pad will be driven during lp0 mode*/ - writel(0x1, pmc + PMC_DPD_SAMPLE); - - writel(wake_enb, pmc + PMC_WAKE_MASK); + tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET); } -static void tegra_mask(struct irq_data *d) +static void tegra_ack(struct irq_data *d) { - tegra_gic_mask_irq(d); - tegra_legacy_mask_irq(d->irq); -} + if (d->irq < FIRST_LEGACY_IRQ) + return; -static void tegra_unmask(struct irq_data *d) -{ - tegra_gic_unmask_irq(d); - tegra_legacy_unmask_irq(d->irq); + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); } -static void tegra_ack(struct irq_data *d) +static void tegra_eoi(struct irq_data *d) { - tegra_legacy_force_irq_clr(d->irq); - tegra_gic_ack_irq(d); + if (d->irq < FIRST_LEGACY_IRQ) + return; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); } static int tegra_retrigger(struct irq_data *d) { - tegra_legacy_force_irq_set(d->irq); + if (d->irq < FIRST_LEGACY_IRQ) + return 0; + + tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET); + return 1; } -static struct irq_chip tegra_irq = { - .name = "PPI", - .irq_ack = tegra_ack, - .irq_mask = tegra_mask, - .irq_unmask = tegra_unmask, - .irq_retrigger = tegra_retrigger, -}; - void __init tegra_init_irq(void) { - struct irq_chip *gic; - unsigned int i; - int irq; + int i; - tegra_init_legacy_irq(); + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_CPU_IER_CLR); + writel(0, ictlr + ICTLR_CPU_IEP_CLASS); + } + + gic_arch_extn.irq_ack = tegra_ack; + gic_arch_extn.irq_eoi = tegra_eoi; + gic_arch_extn.irq_mask = tegra_mask; + gic_arch_extn.irq_unmask = tegra_unmask; + gic_arch_extn.irq_retrigger = tegra_retrigger; gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); - - gic = get_irq_chip(29); - tegra_gic_unmask_irq = gic->irq_unmask; - tegra_gic_mask_irq = gic->irq_mask; - tegra_gic_ack_irq = gic->irq_ack; -#ifdef CONFIG_SMP - tegra_irq.irq_set_affinity = gic->irq_set_affinity; -#endif - - for (i = 0; i < INT_MAIN_NR; i++) { - irq = INT_PRI_BASE + i; - set_irq_chip(irq, &tegra_irq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } } diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c deleted file mode 100644 index 38eb719a4f5..00000000000 --- a/arch/arm/mach-tegra/legacy_irq.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * arch/arm/mach-tegra/legacy_irq.c - * - * Copyright (C) 2010 Google, Inc. - * Author: Colin Cross <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/io.h> -#include <linux/kernel.h> -#include <mach/iomap.h> -#include <mach/irqs.h> -#include <mach/legacy_irq.h> - -#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE) -#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE) -#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ) - -#define ICTLR_CPU_IEP_VFIQ 0x08 -#define ICTLR_CPU_IEP_FIR 0x14 -#define ICTLR_CPU_IEP_FIR_SET 0x18 -#define ICTLR_CPU_IEP_FIR_CLR 0x1c - -#define ICTLR_CPU_IER 0x20 -#define ICTLR_CPU_IER_SET 0x24 -#define ICTLR_CPU_IER_CLR 0x28 -#define ICTLR_CPU_IEP_CLASS 0x2C - -#define ICTLR_COP_IER 0x30 -#define ICTLR_COP_IER_SET 0x34 -#define ICTLR_COP_IER_CLR 0x38 -#define ICTLR_COP_IEP_CLASS 0x3c - -#define NUM_ICTLRS 4 - -static void __iomem *ictlr_reg_base[] = { - IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), -}; - -static u32 tegra_legacy_wake_mask[4]; -static u32 tegra_legacy_saved_mask[4]; - -/* When going into deep sleep, the CPU is powered down, taking the GIC with it - In order to wake, the wake interrupts need to be enabled in the legacy - interrupt controller. */ -void tegra_legacy_unmask_irq(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET); -} - -void tegra_legacy_mask_irq(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR); -} - -void tegra_legacy_force_irq_set(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET); -} - -void tegra_legacy_force_irq_clr(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR); -} - -int tegra_legacy_force_irq_status(unsigned int irq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31))); -} - -void tegra_legacy_select_fiq(unsigned int irq, bool fiq) -{ - void __iomem *base; - pr_debug("%s: %d\n", __func__, irq); - - irq -= 32; - base = ictlr_reg_base[irq>>5]; - writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS); -} - -unsigned long tegra_legacy_vfiq(int nr) -{ - void __iomem *base; - base = ictlr_reg_base[nr]; - return readl(base + ICTLR_CPU_IEP_VFIQ); -} - -unsigned long tegra_legacy_class(int nr) -{ - void __iomem *base; - base = ictlr_reg_base[nr]; - return readl(base + ICTLR_CPU_IEP_CLASS); -} - -int tegra_legacy_irq_set_wake(int irq, int enable) -{ - irq -= 32; - if (enable) - tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31); - else - tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31)); - - return 0; -} - -void tegra_legacy_irq_set_lp1_wake_mask(void) -{ - void __iomem *base; - int i; - - for (i = 0; i < NUM_ICTLRS; i++) { - base = ictlr_reg_base[i]; - tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER); - writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER); - } -} - -void tegra_legacy_irq_restore_mask(void) -{ - void __iomem *base; - int i; - - for (i = 0; i < NUM_ICTLRS; i++) { - base = ictlr_reg_base[i]; - writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER); - } -} - -void tegra_init_legacy_irq(void) -{ - int i; - - for (i = 0; i < NUM_ICTLRS; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - writel(~0, ictlr + ICTLR_CPU_IER_CLR); - writel(0, ictlr + ICTLR_CPU_IEP_CLASS); - } -} - -#ifdef CONFIG_PM -static u32 cop_ier[NUM_ICTLRS]; -static u32 cpu_ier[NUM_ICTLRS]; -static u32 cpu_iep[NUM_ICTLRS]; - -void tegra_irq_suspend(void) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i < NUM_ICTLRS; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER); - cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS); - cop_ier[i] = readl(ictlr + ICTLR_COP_IER); - writel(~0, ictlr + ICTLR_COP_IER_CLR); - } - local_irq_restore(flags); -} - -void tegra_irq_resume(void) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i < NUM_ICTLRS; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS); - writel(~0ul, ictlr + ICTLR_CPU_IER_CLR); - writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET); - writel(0, ictlr + ICTLR_COP_IEP_CLASS); - writel(~0ul, ictlr + ICTLR_COP_IER_CLR); - writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET); - } - local_irq_restore(flags); -} -#endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index ec1f68924ed..b8ae3c978de 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -20,6 +20,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> @@ -122,6 +123,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) cpu_set(i, cpu_possible_map); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 6d7c4eea4dc..bb618075fab 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -337,7 +337,7 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) const struct clk_mux_sel *sel; int shift; - val = clk_readl(c->reg + SUPER_CLK_MUX);; + val = clk_readl(c->reg + SUPER_CLK_MUX); BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? @@ -1362,14 +1362,15 @@ static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate) { unsigned long flags; int ret; + long new_rate = rate; - rate = clk_round_rate(c->parent, rate); - if (rate < 0) - return rate; + new_rate = clk_round_rate(c->parent, new_rate); + if (new_rate < 0) + return new_rate; spin_lock_irqsave(&c->parent->spinlock, flags); - c->u.shared_bus_user.rate = rate; + c->u.shared_bus_user.rate = new_rate; ret = tegra_clk_shared_bus_update(c->parent); spin_unlock_irqrestore(&c->parent->spinlock, flags); diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 0fcb1eb4214..90350420c4e 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -98,11 +98,6 @@ static void tegra_timer_set_mode(enum clock_event_mode mode, } } -static cycle_t tegra_clocksource_read(struct clocksource *cs) -{ - return timer_readl(TIMERUS_CNTR_1US); -} - static struct clock_event_device tegra_clockevent = { .name = "timer0", .rating = 300, @@ -111,14 +106,6 @@ static struct clock_event_device tegra_clockevent = { .set_mode = tegra_timer_set_mode, }; -static struct clocksource tegra_clocksource = { - .name = "timer_us", - .rating = 300, - .read = tegra_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static DEFINE_CLOCK_DATA(cd); /* @@ -234,7 +221,8 @@ static void __init tegra_init_timer(void) init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, 1000000, SC_MULT, SC_SHIFT); - if (clocksource_register_hz(&tegra_clocksource, 1000000)) { + if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { printk(KERN_ERR "Failed to register clocksource\n"); BUG(); } diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index fabcc49abe8..5535dd0a78c 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c @@ -263,7 +263,7 @@ static void disable_i2s0_vcxo(void) val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); - /* Deactivate VCXO if noone else is using VCXO */ + /* Deactivate VCXO if no one else is using VCXO */ if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO)) val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); @@ -283,7 +283,7 @@ static void disable_i2s1_vcxo(void) val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR); val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); - /* Deactivate VCXO if noone else is using VCXO */ + /* Deactivate VCXO if no one else is using VCXO */ if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO)) val &= ~U300_SYSCON_CCR_TURN_VCXO_ON; writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR); @@ -649,7 +649,7 @@ static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate) */ long clk_round_rate(struct clk *clk, unsigned long rate) { - /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */ + /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */ /* Else default to fixed value */ if (clk->round_rate) { diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 3ec58bd2d6e..891cf44591e 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -333,20 +333,6 @@ static struct irqaction u300_timer_irq = { .handler = u300_timer_interrupt, }; -/* Use general purpose timer 2 as clock source */ -static cycle_t u300_get_cycles(struct clocksource *cs) -{ - return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); -} - -static struct clocksource clocksource_u300_1mhz = { - .name = "GPT2", - .rating = 300, /* Reasonably fast and accurate clock source */ - .read = u300_get_cycles, - .mask = CLOCKSOURCE_MASK(32), /* 32 bits */ - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - /* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some @@ -422,7 +408,9 @@ static void __init u300_timer_init(void) writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); - if (clocksource_register_hz(&clocksource_u300_1mhz, rate)) + /* Use general purpose timer 2 as clock source */ + if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, + "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) printk(KERN_ERR "timer: failed to initialize clock " "source %s\n", clocksource_u300_1mhz.name); diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 203b986280f..58626013aa3 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -23,6 +23,7 @@ menu "Ux500 target platform" config MACH_U8500 bool "U8500 Development platform" depends on UX500_SOC_DB8500 + select TPS6105X help Include support for the mop500 development platform. diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 875c91b2f8a..9ed0f90cfe2 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -13,6 +13,30 @@ #include <linux/regulator/ab8500.h> #include "board-mop500-regulators.h" +/* + * TPS61052 regulator + */ +static struct regulator_consumer_supply tps61052_vaudio_consumers[] = { + /* + * Boost converter supply to raise voltage on audio speaker, this + * is actually connected to three pins, VInVhfL (left amplifier) + * VInVhfR (right amplifier) and VIntDClassInt - all three must + * be connected to the same voltage. + */ + REGULATOR_SUPPLY("vintdclassint", "ab8500-codec.0"), +}; + +struct regulator_init_data tps61052_regulator = { + .constraints = { + .name = "vaudio-hf", + .min_uV = 4500000, + .max_uV = 4500000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(tps61052_vaudio_consumers), + .consumer_supplies = tps61052_vaudio_consumers, +}; + static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { /* External displays, connector on board 2v5 power supply */ REGULATOR_SUPPLY("vaux12v5", "mcde.0"), @@ -62,6 +86,182 @@ static struct regulator_consumer_supply ab8500_vana_consumers[] = { REGULATOR_SUPPLY("vsmps2", "mcde.0"), }; +/* ab8500 regulator register initialization */ +struct ab8500_regulator_reg_init +ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = { + /* + * VanaRequestCtrl = HP/LP depending on VxRequest + * VextSupply1RequestCtrl = HP/LP depending on VxRequest + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00), + /* + * VextSupply2RequestCtrl = HP/LP depending on VxRequest + * VextSupply3RequestCtrl = HP/LP depending on VxRequest + * Vaux1RequestCtrl = HP/LP depending on VxRequest + * Vaux2RequestCtrl = HP/LP depending on VxRequest + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00), + /* + * Vaux3RequestCtrl = HP/LP depending on VxRequest + * SwHPReq = Control through SWValid disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00), + /* + * VanaSysClkReq1HPValid = disabled + * Vaux1SysClkReq1HPValid = disabled + * Vaux2SysClkReq1HPValid = disabled + * Vaux3SysClkReq1HPValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00), + /* + * VextSupply1SysClkReq1HPValid = disabled + * VextSupply2SysClkReq1HPValid = disabled + * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40), + /* + * VanaHwHPReq1Valid = disabled + * Vaux1HwHPreq1Valid = disabled + * Vaux2HwHPReq1Valid = disabled + * Vaux3HwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00), + /* + * VextSupply1HwHPReq1Valid = disabled + * VextSupply2HwHPReq1Valid = disabled + * VextSupply3HwHPReq1Valid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00), + /* + * VanaHwHPReq2Valid = disabled + * Vaux1HwHPReq2Valid = disabled + * Vaux2HwHPReq2Valid = disabled + * Vaux3HwHPReq2Valid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00), + /* + * VextSupply1HwHPReq2Valid = disabled + * VextSupply2HwHPReq2Valid = disabled + * VextSupply3HwHPReq2Valid = HWReq2 controlled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04), + /* + * VanaSwHPReqValid = disabled + * Vaux1SwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00), + /* + * Vaux2SwHPReqValid = disabled + * Vaux3SwHPReqValid = disabled + * VextSupply1SwHPReqValid = disabled + * VextSupply2SwHPReqValid = disabled + * VextSupply3SwHPReqValid = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00), + /* + * SysClkReq2Valid1 = SysClkReq2 controlled + * SysClkReq3Valid1 = disabled + * SysClkReq4Valid1 = SysClkReq4 controlled + * SysClkReq5Valid1 = disabled + * SysClkReq6Valid1 = SysClkReq6 controlled + * SysClkReq7Valid1 = disabled + * SysClkReq8Valid1 = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a), + /* + * SysClkReq2Valid2 = disabled + * SysClkReq3Valid2 = disabled + * SysClkReq4Valid2 = disabled + * SysClkReq5Valid2 = disabled + * SysClkReq6Valid2 = SysClkReq6 controlled + * SysClkReq7Valid2 = disabled + * SysClkReq8Valid2 = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20), + /* + * VTVoutEna = disabled + * Vintcore12Ena = disabled + * Vintcore12Sel = 1.25 V + * Vintcore12LP = inactive (HP) + * VTVoutLP = inactive (HP) + */ + INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10), + /* + * VaudioEna = disabled + * VdmicEna = disabled + * Vamic1Ena = disabled + * Vamic2Ena = disabled + */ + INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00), + /* + * Vamic1_dzout = high-Z when Vamic1 is disabled + * Vamic2_dzout = high-Z when Vamic2 is disabled + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00), + /* + * VPll = Hw controlled + * VanaRegu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02), + /* + * VrefDDREna = disabled + * VrefDDRSleepMode = inactive (no pulldown) + */ + INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00), + /* + * VextSupply1Regu = HW control + * VextSupply2Regu = HW control + * VextSupply3Regu = HW control + * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 + * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 + */ + INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a), + /* + * Vaux1Regu = force HP + * Vaux2Regu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01), + /* + * Vaux3regu = force off + */ + INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00), + /* + * Vsmps1 = 1.15V + */ + INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24), + /* + * Vaux1Sel = 2.5 V + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08), + /* + * Vaux2Sel = 2.9 V + */ + INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d), + /* + * Vaux3Sel = 2.91 V + */ + INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07), + /* + * VextSupply12LP = disabled (no LP) + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00), + /* + * Vaux1Disch = short discharge time + * Vaux2Disch = short discharge time + * Vaux3Disch = short discharge time + * Vintcore12Disch = short discharge time + * VTVoutDisch = short discharge time + * VaudioDisch = short discharge time + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00), + /* + * VanaDisch = short discharge time + * VdmicPullDownEna = pulldown disabled when Vdmic is disabled + * VdmicDisch = short discharge time + */ + INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00), +}; + /* AB8500 regulators */ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { /* supplies to the display/camera */ @@ -72,6 +272,7 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { .max_uV = 2900000, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, + .boot_on = 1, /* must be on for display */ }, .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), .consumer_supplies = ab8500_vaux1_consumers, diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index f979b892e4f..94992158d96 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -17,5 +17,6 @@ extern struct ab8500_regulator_reg_init ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS]; +extern struct regulator_init_data tps61052_regulator; #endif diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index d0076453d7f..6e1907fa94f 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -22,6 +22,8 @@ #include <linux/mfd/ab8500.h> #include <linux/regulator/ab8500.h> #include <linux/mfd/tc3589x.h> +#include <linux/mfd/tps6105x.h> +#include <linux/mfd/ab8500/gpio.h> #include <linux/leds-lp5521.h> #include <linux/input.h> #include <linux/gpio_keys.h> @@ -42,10 +44,35 @@ #include "board-mop500.h" #include "board-mop500-regulators.h" +static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { + .gpio_base = MOP500_AB8500_GPIO(0), + .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, + /* config_reg is the initial configuration of ab8500 pins. + * The pins can be configured as GPIO or alt functions based + * on value present in GpioSel1 to GpioSel6 and AlternatFunction + * register. This is the array of 7 configuration settings. + * One has to compile time decide these settings. Below is the + * explanation of these setting + * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO + * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO + * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO + * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO + * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO + * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO + * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured + * as GPIO then this register selectes the alternate fucntions + */ + .config_reg = {0x00, 0x1E, 0x80, 0x01, + 0x7A, 0x00, 0x00}, +}; + static struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, + .regulator_reg_init = ab8500_regulator_reg_init, + .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init), .regulator = ab8500_regulators, .num_regulator = ARRAY_SIZE(ab8500_regulators), + .gpio = &ab8500_gpio_pdata, }; static struct resource ab8500_resources[] = { @@ -67,6 +94,15 @@ struct platform_device ab8500_device = { }; /* + * TPS61052 + */ + +static struct tps6105x_platform_data mop500_tps61052_data = { + .mode = TPS6105X_MODE_VOLTAGE, + .regulator_data = &tps61052_regulator, +}; + +/* * TC35892 */ @@ -136,14 +172,21 @@ static struct lp5521_platform_data __initdata lp5521_sec_data = { .clock_mode = LP5521_CLOCK_EXT, }; -static struct i2c_board_info mop500_i2c0_devices[] = { +static struct i2c_board_info __initdata mop500_i2c0_devices[] = { { I2C_BOARD_INFO("tc3589x", 0x42), .irq = NOMADIK_GPIO_TO_IRQ(217), .platform_data = &mop500_tc35892_data, }, + /* I2C0 devices only available prior to HREFv60 */ + { + I2C_BOARD_INFO("tps61052", 0x33), + .platform_data = &mop500_tps61052_data, + }, }; +#define NUM_PRE_V60_I2C0_DEVICES 1 + static struct i2c_board_info __initdata mop500_i2c2_devices[] = { { /* lp5521 LED driver, 1st device */ @@ -381,6 +424,8 @@ static void __init mop500_uart_init(void) static void __init mop500_init_machine(void) { + int i2c0_devs; + /* * The HREFv60 board removed a GPIO expander and routed * all these GPIO pins to the internal GPIO controller @@ -404,8 +449,11 @@ static void __init mop500_init_machine(void) platform_device_register(&ab8500_device); - i2c_register_board_info(0, mop500_i2c0_devices, - ARRAY_SIZE(mop500_i2c0_devices)); + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); + if (machine_is_hrefv60()) + i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; + + i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, ARRAY_SIZE(mop500_i2c2_devices)); } diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 56722f4be71..03a31cc9b08 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -27,6 +27,10 @@ #define GPIO_BU21013_CS MOP500_EGPIO(13) #define GPIO_SDMMC_EN MOP500_EGPIO(17) #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) +#define MOP500_EGPIO_END MOP500_EGPIO(24) + +/* GPIOs on the AB8500 mixed-signals circuit */ +#define MOP500_AB8500_GPIO(x) (MOP500_EGPIO_END + (x)) struct i2c_board_info; diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 0fefb34c11e..16647b25537 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -58,7 +58,7 @@ #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) -/* per7 base addressess */ +/* per7 base addresses */ #define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) #define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) #define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) @@ -68,7 +68,7 @@ #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -/* per6 base addressess */ +/* per6 base addresses */ #define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) #define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) #define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) @@ -79,11 +79,11 @@ #define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) -/* per5 base addressess */ +/* per5 base addresses */ #define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) -/* per4 base addressess */ +/* per4 base addresses */ #define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) #define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) #define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) @@ -106,7 +106,7 @@ #define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) -/* per2 base addressess */ +/* per2 base addresses */ #define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) #define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) #define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index 7cdeb2af0eb..97ef55f8493 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -35,9 +35,20 @@ #define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END #define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) -#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) +#define MOP500_STMPE1601_IRQ_END \ + MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) -#define MOP500_IRQ_END MOP500_NR_IRQS +/* AB8500 virtual gpio IRQ */ +#define AB8500_VIR_GPIO_NR_IRQS 16 + +#define MOP500_AB8500_VIR_GPIO_IRQ_BASE \ + MOP500_STMPE1601_IRQ_END +#define MOP500_AB8500_VIR_GPIO_IRQ_END \ + (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS) + +#define MOP500_NR_IRQS MOP500_AB8500_VIR_GPIO_IRQ_END + +#define MOP500_IRQ_END MOP500_NR_IRQS #if MOP500_IRQ_END > IRQ_BOARD_END #undef IRQ_BOARD_END diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h deleted file mode 100644 index ca2b15b1b3b..00000000000 --- a/arch/arm/mach-ux500/include/mach/smp.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is based ARM realview platform. - * Copyright (C) ARM Limited. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* This is required to wakeup the secondary core */ -extern void u8500_secondary_startup(void); - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} -#endif diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index ab0fe1432fa..088b550c40d 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -24,7 +24,7 @@ #include <linux/amba/serial.h> #include <mach/hardware.h> -static u32 ux500_uart_base; +u32 ux500_uart_base; static void putc(const char c) { diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c index a4ffb9f4f46..2b2d51caf9d 100644 --- a/arch/arm/mach-ux500/mbox-db5500.c +++ b/arch/arm/mach-ux500/mbox-db5500.c @@ -416,8 +416,7 @@ struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) dev_dbg(&(mbox->pdev->dev), "Resource name: %s start: 0x%X, end: 0x%X\n", resource->name, resource->start, resource->end); - mbox->virtbase_peer = - ioremap(resource->start, resource->end - resource->start); + mbox->virtbase_peer = ioremap(resource->start, resource_size(resource)); if (!mbox->virtbase_peer) { dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n"); mbox = NULL; @@ -440,8 +439,7 @@ struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) dev_dbg(&(mbox->pdev->dev), "Resource name: %s start: 0x%X, end: 0x%X\n", resource->name, resource->start, resource->end); - mbox->virtbase_local = - ioremap(resource->start, resource->end - resource->start); + mbox->virtbase_local = ioremap(resource->start, resource_size(resource)); if (!mbox->virtbase_local) { dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n"); mbox = NULL; diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c index e1296a7447c..6b86416c94c 100644 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c @@ -90,8 +90,7 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data) static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) { - set_irq_chip(irq, modem_irq_chip); - set_irq_handler(irq, handle_simple_irq); + irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); pr_debug("modem_irq: Created virtual IRQ %d\n", irq); diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 4fff4d40841..0c527fe2ceb 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -18,10 +18,14 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <mach/hardware.h> #include <mach/setup.h> +/* This is called from headsmp.S to wakeup the secondary core */ +extern void u8500_secondary_startup(void); + /* * control for which core is the next to come out of the secondary * boot "holding pen" @@ -94,7 +98,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(cpu); - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -162,6 +166,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index eb7ffa0ee8b..0c99cf076c6 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -32,6 +32,7 @@ #include <linux/io.h> #include <linux/gfp.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <asm/system.h> #include <asm/irq.h> @@ -42,7 +43,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> #include <asm/mach/map.h> @@ -190,27 +190,7 @@ void __init versatile_map_io(void) #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) -static int versatile_flash_init(void) -{ - u32 val; - - val = __raw_readl(VERSATILE_FLASHCTRL); - val &= ~VERSATILE_FLASHPROG_FLVPPEN; - __raw_writel(val, VERSATILE_FLASHCTRL); - - return 0; -} - -static void versatile_flash_exit(void) -{ - u32 val; - - val = __raw_readl(VERSATILE_FLASHCTRL); - val &= ~VERSATILE_FLASHPROG_FLVPPEN; - __raw_writel(val, VERSATILE_FLASHCTRL); -} - -static void versatile_flash_set_vpp(int on) +static void versatile_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; @@ -222,11 +202,8 @@ static void versatile_flash_set_vpp(int on) __raw_writel(val, VERSATILE_FLASHCTRL); } -static struct flash_platform_data versatile_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data versatile_flash_data = { .width = 4, - .init = versatile_flash_init, - .exit = versatile_flash_exit, .set_vpp = versatile_flash_set_vpp, }; @@ -237,7 +214,7 @@ static struct resource versatile_flash_resource = { }; static struct platform_device versatile_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &versatile_flash_data, @@ -375,6 +352,10 @@ static struct clk ref24_clk = { .rate = 24000000, }; +static struct clk sp804_clk = { + .rate = 1000000, +}; + static struct clk dummy_apb_pclk; static struct clk_lookup lookups[] = { @@ -411,7 +392,10 @@ static struct clk_lookup lookups[] = { }, { /* CLCD */ .dev_id = "dev:20", .clk = &osc4_clk, - } + }, { /* SP804 timers */ + .dev_id = "sp804", + .clk = &sp804_clk, + }, }; /* @@ -764,8 +748,8 @@ static void __init versatile_timer_init(void) writel(0, TIMER2_VA_BASE + TIMER_CTRL); writel(0, TIMER3_VA_BASE + TIMER_CTRL); - sp804_clocksource_init(TIMER3_VA_BASE); - sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1); + sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); + sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0"); } struct sys_timer versatile_timer = { diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index ebc22e75932..765a71ff7f3 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -71,8 +71,9 @@ static void __init ct_ca9x4_timer_init(void) writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); - sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1)); - sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0); + sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1"); + sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0, + "ct-timer0"); } static struct sys_timer ct_ca9x4_timer = { @@ -141,10 +142,22 @@ static struct clk osc1_clk = { .rate = 24000000, }; +static struct clk ct_sp804_clk = { + .rate = 1000000, +}; + static struct clk_lookup lookups[] = { { /* CLCD */ .dev_id = "ct:clcd", .clk = &osc1_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "ct-timer0", + .clk = &ct_sp804_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "ct-timer1", + .clk = &ct_sp804_clk, }, }; @@ -210,6 +223,8 @@ static void ct_ca9x4_init_cpu_map(void) for (i = 0; i < ncores; ++i) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } static void ct_ca9x4_smp_enable(unsigned int max_cpus) diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h deleted file mode 100644 index 4c05e4a9713..00000000000 --- a/arch/arm/mach-vexpress/include/mach/smp.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __MACH_SMP_H -#define __MACH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} -#endif diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index ba46e8e0743..285edcd2da2 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -13,11 +13,11 @@ #include <linux/sysdev.h> #include <linux/usb/isp1760.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <asm/mach-types.h> #include <asm/sizes.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/hardware/arm_timer.h> @@ -65,8 +65,9 @@ static void __init v2m_timer_init(void) writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); - sp804_clocksource_init(MMIO_P2V(V2M_TIMER1)); - sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0); + sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1"); + sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0, + "v2m-timer0"); } static struct sys_timer v2m_timer = { @@ -206,27 +207,13 @@ static struct platform_device v2m_usb_device = { .dev.platform_data = &v2m_usb_config, }; -static int v2m_flash_init(void) -{ - writel(0, MMIO_P2V(V2M_SYS_FLASH)); - return 0; -} - -static void v2m_flash_exit(void) -{ - writel(0, MMIO_P2V(V2M_SYS_FLASH)); -} - -static void v2m_flash_set_vpp(int on) +static void v2m_flash_set_vpp(struct platform_device *pdev, int on) { writel(on != 0, MMIO_P2V(V2M_SYS_FLASH)); } -static struct flash_platform_data v2m_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data v2m_flash_data = { .width = 4, - .init = v2m_flash_init, - .exit = v2m_flash_exit, .set_vpp = v2m_flash_set_vpp, }; @@ -243,7 +230,7 @@ static struct resource v2m_flash_resources[] = { }; static struct platform_device v2m_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = -1, .resource = v2m_flash_resources, .num_resources = ARRAY_SIZE(v2m_flash_resources), @@ -333,6 +320,10 @@ static struct clk osc2_clk = { .rate = 24000000, }; +static struct clk v2m_sp804_clk = { + .rate = 1000000, +}; + static struct clk dummy_apb_pclk; static struct clk_lookup v2m_lookups[] = { @@ -363,6 +354,14 @@ static struct clk_lookup v2m_lookups[] = { }, { /* CLCD */ .dev_id = "mb:clcd", .clk = &osc1_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "v2m-timer0", + .clk = &v2m_sp804_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "v2m-timer1", + .clk = &v2m_sp804_clk, }, }; diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index 5f4ddde4f02..245140c0df1 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c @@ -97,15 +97,15 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) return -EINVAL; case IRQF_TRIGGER_HIGH: dctr |= VT8500_TRIGGER_HIGH; - irq_desc[orig_irq].handle_irq = handle_level_irq; + __irq_set_handler_locked(orig_irq, handle_level_irq); break; case IRQF_TRIGGER_FALLING: dctr |= VT8500_TRIGGER_FALLING; - irq_desc[orig_irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(orig_irq, handle_edge_irq); break; case IRQF_TRIGGER_RISING: dctr |= VT8500_TRIGGER_RISING; - irq_desc[orig_irq].handle_irq = handle_edge_irq; + __irq_set_handler_locked(orig_irq, handle_edge_irq); break; } writeb(dctr, base + VT8500_IC_DCTR + irq); @@ -136,8 +136,8 @@ void __init vt8500_init_irq(void) /* Disable all interrupts and route them to IRQ */ writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); - set_irq_chip(i, &vt8500_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &vt8500_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } else { @@ -167,8 +167,8 @@ void __init wm8505_init_irq(void) writeb(0x00, sic_regbase + VT8500_IC_DCTR + i - 64); - set_irq_chip(i, &vt8500_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &vt8500_irq_chip, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } } else { diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h index 56f1a74d701..03130212ace 100644 --- a/arch/arm/mach-w90x900/include/mach/uncompress.h +++ b/arch/arm/mach-w90x900/include/mach/uncompress.h @@ -27,7 +27,7 @@ #define arch_decomp_wdog() #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) -static volatile u32 * uart_base = (u32 *)UART0_PA; +static volatile u32 * const uart_base = (u32 *)UART0_PA; static void putc(int ch) { diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 9c350103dcd..7bf143c443f 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c @@ -207,8 +207,8 @@ void __init nuc900_init_irq(void) __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { - set_irq_chip(irqno, &nuc900_irq_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &nuc900_irq_chip, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index 4b089cb930d..a2c4e2d0a0d 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c @@ -43,7 +43,6 @@ #define PRESCALE 0x63 /* Divider = prescale + 1 */ #define TDR_SHIFT 24 -#define TDR_MASK ((1 << TDR_SHIFT) - 1) static unsigned int timer0_load; @@ -143,19 +142,6 @@ static void __init nuc900_clockevents_init(void) clockevents_register_device(&nuc900_clockevent_device); } -static cycle_t nuc900_get_cycles(struct clocksource *cs) -{ - return (~__raw_readl(REG_TDR1)) & TDR_MASK; -} - -static struct clocksource clocksource_nuc900 = { - .name = "nuc900-timer1", - .rating = 200, - .read = nuc900_get_cycles, - .mask = CLOCKSOURCE_MASK(TDR_SHIFT), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static void __init nuc900_clocksource_init(void) { unsigned int val; @@ -175,7 +161,8 @@ static void __init nuc900_clocksource_init(void) val |= (COUNTEN | PERIOD | PRESCALE); __raw_writel(val, REG_TCSR1); - clocksource_register_hz(&clocksource_nuc900, rate); + clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200, + TDR_SHIFT, clocksource_mmio_readl_down); } static void __init nuc900_timer_init(void) diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index d3644db467b..f40c69656d8 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -32,7 +32,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. * * Size Clean (ticks) Dirty (ticks) * 4096 21 20 21 53 55 54 diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 49c2b66cf3d..a7b276dbda1 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -34,7 +34,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. * * *** This needs benchmarking */ diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68ce95..dc18d81ef8c 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 2b269c95552..1a8d4aa821b 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -253,8 +253,8 @@ void __sync_icache_dcache(pte_t pteval) if (!test_and_set_bit(PG_dcache_clean, &page->flags)) __flush_dcache_page(mapping, page); - /* pte_exec() already checked above for non-aliasing VIPT cache */ - if (cache_is_vipt_nonaliasing() || pte_exec(pteval)) + + if (pte_exec(pteval)) __flush_icache_all(); } #endif @@ -275,7 +275,8 @@ void __sync_icache_dcache(pte_t pteval) * kernel cache lines for later. Otherwise, we assume we have * aliasing mappings. * - * Note that we disable the lazy flush for SMP. + * Note that we disable the lazy flush for SMP configurations where + * the cache maintenance operations are not automatically broadcasted. */ void flush_dcache_page(struct page *page) { diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index e5f6fc42834..76f82ae44ef 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn, } } +#ifdef CONFIG_ZONE_DMA +static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole, + unsigned long dma_size) +{ + if (size[0] <= dma_size) + return; + + size[ZONE_NORMAL] = size[0] - dma_size; + size[ZONE_DMA] = dma_size; + hole[ZONE_NORMAL] = hole[0]; + hole[ZONE_DMA] = 0; +} +#endif + static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, unsigned long max_high) { @@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, #endif } +#ifdef ARM_DMA_ZONE_SIZE +#ifndef CONFIG_ZONE_DMA +#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations +#endif + /* * Adjust the sizes according to any special requirements for * this machine type. */ - arch_adjust_zones(zone_size, zhole_size); + arm_adjust_dma_zone(zone_size, zhole_size, + ARM_DMA_ZONE_SIZE >> PAGE_SHIFT); +#endif free_area_init_node(0, zone_size, min, zhole_size); } @@ -392,7 +413,7 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn) * Convert start_pfn/end_pfn to a struct page pointer. */ start_pg = pfn_to_page(start_pfn - 1) + 1; - end_pg = pfn_to_page(end_pfn); + end_pg = pfn_to_page(end_pfn - 1) + 1; /* * Convert to physical addresses, and @@ -426,6 +447,14 @@ static void __init free_unused_memmap(struct meminfo *mi) bank_start = bank_pfn_start(bank); +#ifdef CONFIG_SPARSEMEM + /* + * Take care not to free memmap entries that don't exist + * due to SPARSEMEM sections which aren't present. + */ + bank_start = min(bank_start, + ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#endif /* * If we had a previous bank, and there is a space * between the current bank and the previous, free it. @@ -440,6 +469,12 @@ static void __init free_unused_memmap(struct meminfo *mi) */ prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES); } + +#ifdef CONFIG_SPARSEMEM + if (!IS_ALIGNED(prev_bank_end, PAGES_PER_SECTION)) + free_memmap(prev_bank_end, + ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#endif } static void __init free_highpages(void) diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index afe209e1e1f..74be05f3e03 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -7,6 +7,7 @@ #include <linux/shm.h> #include <linux/sched.h> #include <linux/io.h> +#include <linux/personality.h> #include <linux/random.h> #include <asm/cputype.h> #include <asm/system.h> @@ -82,7 +83,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, mm->cached_hole_size = 0; } /* 8 bits of randomness in 20 address space bits */ - if (current->flags & PF_RANDOMIZE) + if ((current->flags & PF_RANDOMIZE) && + !(current->personality & ADDR_NO_RANDOMIZE)) addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT; full_search: diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 226e3d8351c..6c4e7fd6c8a 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -64,7 +64,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 86d9c2cf0bc..4ce947c1962 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -64,7 +64,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 83d3dd34f84..c8884c5413a 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -53,7 +53,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 686043ee728..413684660aa 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -53,7 +53,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 32768 diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 665266da143..7a06e5964f5 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -63,7 +63,7 @@ ENTRY(cpu_arm720_proc_fin) /* * Function: arm720_proc_do_idle(void) * Params : r0 = unused - * Purpose : put the processer in proper idle mode + * Purpose : put the processor in proper idle mode */ ENTRY(cpu_arm720_do_idle) mov pc, lr diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 219980ec8b6..bf8a1d1cccb 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -53,7 +53,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 65536 @@ -390,7 +390,7 @@ ENTRY(cpu_arm920_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size .equ cpu_arm920_suspend_size, 4 * 3 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm920_do_suspend) stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 36154b1e792..95ba1fc56e4 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -54,7 +54,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. (I think this should + * cache line maintenance instructions. (I think this should * be 32768). */ #define CACHE_DLIMIT 8192 diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 89c5e0009c4..541e4774eea 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -77,7 +77,7 @@ /* * This is the size at which it becomes more efficient to * clean the whole cache, rather than using the individual - * cache line maintainence instructions. + * cache line maintenance instructions. */ #define CACHE_DLIMIT 8192 diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 6a4bdb2c94a..0ed85d930c0 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -404,7 +404,7 @@ ENTRY(cpu_arm926_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm926_suspend_size .equ cpu_arm926_suspend_size, 4 * 3 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm926_do_suspend) stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index e32fa499194..34261f9486b 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -85,7 +85,7 @@ /* * Sanity check the PTE configuration for the code below - which makes - * certain assumptions about how these bits are layed out. + * certain assumptions about how these bits are laid out. */ #ifdef CONFIG_MMU #if L_PTE_SHARED != PTE_EXT_SHARED diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 74483d1977f..184a9c997e3 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -171,7 +171,7 @@ ENTRY(cpu_sa1100_set_pte_ext) .globl cpu_sa1100_suspend_size .equ cpu_sa1100_suspend_size, 4*4 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_sa1100_do_suspend) stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c3, c0, 0 @ domain ID diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 832b6bdc192..ab17cc0d3fa 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -124,7 +124,7 @@ ENTRY(cpu_v6_set_pte_ext) /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ .globl cpu_v6_suspend_size .equ cpu_v6_suspend_size, 4 * 8 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_v6_do_suspend) stmfd sp!, {r4 - r11, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID @@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend) mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 - mrc p15, 0, r9, c1, c0, 1 @ auxillary control register + mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register mrc p15, 0, r10, c1, c0, 2 @ co-processor access control mrc p15, 0, r11, c1, c0, 0 @ control register stmia r0, {r4 - r11} @@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume) mcr p15, 0, r6, c3, c0, 0 @ Domain ID mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 - mcr p15, 0, r9, c1, c0, 1 @ auxillary control register + mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register mcr p15, 0, r10, c1, c0, 2 @ co-processor access control mcr p15, 0, ip, c2, c0, 2 @ TTB control register mcr p15, 0, ip, c7, c5, 4 @ ISB @@ -175,11 +175,6 @@ cpu_v6_name: .asciz "ARMv6-compatible processor" .size cpu_v6_name, . - cpu_v6_name - .type cpu_pj4_name, #object -cpu_pj4_name: - .asciz "Marvell PJ4 processor" - .size cpu_pj4_name, . - cpu_pj4_name - .align __CPUINIT @@ -305,32 +300,3 @@ __v6_proc_info: .long v6_user_fns .long v6_cache_fns .size __v6_proc_info, . - __v6_proc_info - - .type __pj4_v6_proc_info, #object -__pj4_v6_proc_info: - .long 0x560f5810 - .long 0xff0ffff0 - ALT_SMP(.long \ - PMD_TYPE_SECT | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ | \ - PMD_FLAGS_SMP) - ALT_UP(.long \ - PMD_TYPE_SECT | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ | \ - PMD_FLAGS_UP) - .long PMD_TYPE_SECT | \ - PMD_SECT_XN | \ - PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ - b __v6_setup - .long cpu_arch_name - .long cpu_elf_name - .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS - .long cpu_pj4_name - .long v6_processor_functions - .long v6wbi_tlb_fns - .long v6_user_fns - .long v6_cache_fns - .size __pj4_v6_proc_info, . - __pj4_v6_proc_info diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 262fa88a743..babfba09c89 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -211,7 +211,7 @@ cpu_v7_name: /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ .globl cpu_v7_suspend_size .equ cpu_v7_suspend_size, 4 * 8 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_v7_do_suspend) stmfd sp!, {r4 - r11, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID @@ -237,7 +237,7 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register - mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register + mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 63d8b2044e8..596213699f3 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -417,7 +417,7 @@ ENTRY(cpu_xsc3_set_pte_ext) .globl cpu_xsc3_suspend_size .equ cpu_xsc3_suspend_size, 4 * 8 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_xsc3_do_suspend) stmfd sp!, {r4 - r10, lr} mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 086038cd86a..42af97664c9 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -395,7 +395,7 @@ ENTRY(xscale_dma_a0_map_area) teq r2, #DMA_TO_DEVICE beq xscale_dma_clean_range b xscale_dma_flush_range -ENDPROC(xscsale_dma_a0_map_area) +ENDPROC(xscale_dma_a0_map_area) /* * dma_unmap_area(start, size, dir) @@ -518,7 +518,7 @@ ENTRY(cpu_xscale_set_pte_ext) .globl cpu_xscale_suspend_size .equ cpu_xscale_suspend_size, 4 * 7 -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP ENTRY(cpu_xscale_do_suspend) stmfd sp!, {r4 - r10, lr} mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 07f23bb42be..7cdc5161ff2 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -17,7 +17,6 @@ #include <linux/interrupt.h> #include <linux/time.h> #include <linux/init.h> -#include <linux/sched.h> #include <linux/timex.h> #include <linux/sched.h> #include <linux/io.h> diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c index c856fa39760..f0ba0726306 100644 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -100,14 +100,9 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) expio_irq = MXC_BOARD_IRQ_START; for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - struct irq_desc *d; if ((int_valid & 1) == 0) continue; - d = irq_desc + expio_irq; - if (unlikely(!(d->handle_irq))) - pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); - else - d->handle_irq(expio_irq, d); + generic_handle_irq(expio_irq); } desc->irq_data.chip->irq_ack(&desc->irq_data); @@ -186,12 +181,11 @@ int __init mxc_expio_init(u32 base, u32 p_irq) __raw_writew(0x1F, brd_io + INTR_MASK_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } - set_irq_type(p_irq, IRQF_TRIGGER_LOW); - set_irq_chained_handler(p_irq, mxc_expio_irq_handler); + irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); + irq_set_chained_handler(p_irq, mxc_expio_irq_handler); /* Register Lan device on the debugboard */ smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index b0cb4258e38..a5353fc0793 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -4,13 +4,18 @@ source "arch/arm/plat-mxc/devices/Kconfig" menu "Freescale MXC Implementations" +config ARCH_MX50_SUPPORTED + bool + +config ARCH_MX53_SUPPORTED + bool + choice prompt "Freescale CPU family:" default ARCH_MX3 config ARCH_MX1 bool "MX1-based" - select SOC_IMX1 help This enables support for systems based on the Freescale i.MX1 family @@ -26,29 +31,26 @@ config ARCH_MX25 config ARCH_MX3 bool "MX3-based" - select CPU_V6 help This enables support for systems based on the Freescale i.MX3 family -config ARCH_MXC91231 - bool "MXC91231-based" - select CPU_V6 - select MXC_AVIC +config ARCH_MX503 + bool "i.MX50 + i.MX53" + select ARCH_MX50_SUPPORTED + select ARCH_MX53_SUPPORTED help - This enables support for systems based on the Freescale MXC91231 family + This enables support for machines using Freescale's i.MX50 and i.MX51 + processors. -config ARCH_MX5 - bool "MX5-based" - select CPU_V7 - select ARM_L1_CACHE_SHIFT_6 +config ARCH_MX51 + bool "i.MX51" + select ARCH_MX51_SUPPORTED help This enables support for systems based on the Freescale i.MX51 family endchoice source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-mx3/Kconfig" -source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mx5/Kconfig" endmenu diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index deb284bc7c4..09e2bd0fcdc 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c @@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase) __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_avic_chip.base); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxc_avic_chip.base, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index ce81481becf..74aac96cda2 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -13,7 +13,7 @@ /* * A driver for the Freescale Semiconductor i.MXC CPUfreq module. - * The CPUFREQ driver is for controling CPU frequency. It allows you to change + * The CPUFREQ driver is for controlling CPU frequency. It allows you to change * the CPU clock speed on the fly. */ @@ -153,8 +153,8 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy) ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); if (ret < 0) { - printk(KERN_ERR "%s: failed to register i.MXC CPUfreq \ - with error code %d\n", __func__, ret); + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n", + __func__, ret); goto err; } diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index b9ab1d58b5e..bd294add932 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -24,7 +24,6 @@ config IMX_HAVE_PLATFORM_IMXDI_RTC config IMX_HAVE_PLATFORM_IMX_FB bool - select HAVE_FB_IMX config IMX_HAVE_PLATFORM_IMX_I2C bool @@ -41,6 +40,9 @@ config IMX_HAVE_PLATFORM_IMX_UART config IMX_HAVE_PLATFORM_IMX_UDC bool +config IMX_HAVE_PLATFORM_IPU_CORE + bool + config IMX_HAVE_PLATFORM_MX1_CAMERA bool @@ -63,6 +65,9 @@ config IMX_HAVE_PLATFORM_MXC_RNGA bool select ARCH_HAS_RNGA +config IMX_HAVE_PLATFORM_MXC_RTC + bool + config IMX_HAVE_PLATFORM_MXC_W1 bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 75cd2ece905..ad2922acf48 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o @@ -19,6 +20,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 6561c9df5f0..ccc789e21da 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -53,7 +53,7 @@ struct platform_device *__init imx_add_fec( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_4K, + .end = data->iobase + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c index 10653cc8d1f..805336fdc25 100644 --- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -27,7 +27,7 @@ struct platform_device *__init imx_add_imxdi_rtc( struct resource res[] = { { .start = data->iobase, - .end = data->iobase + SZ_16K, + .end = data->iobase + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { .start = data->irq, diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c new file mode 100644 index 00000000000..edf65034aea --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2011 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_ipu_core_entry_single(soc) \ +{ \ + .iobase = soc ## _IPU_CTRL_BASE_ADDR, \ + .synirq = soc ## _INT_IPU_SYN, \ + .errirq = soc ## _INT_IPU_ERR, \ +} + +#ifdef CONFIG_SOC_IMX31 +const struct imx_ipu_core_data imx31_ipu_core_data __initconst = + imx_ipu_core_entry_single(MX31); +#endif + +#ifdef CONFIG_SOC_IMX35 +const struct imx_ipu_core_data imx35_ipu_core_data __initconst = + imx_ipu_core_entry_single(MX35); +#endif + +static struct platform_device *imx_ipu_coredev __initdata; + +struct platform_device *__init imx_add_ipu_core( + const struct imx_ipu_core_data *data, + const struct ipu_platform_data *pdata) +{ + /* The resource order is important! */ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + 0x5f, + .flags = IORESOURCE_MEM, + }, { + .start = data->iobase + 0x88, + .end = data->iobase + 0xb3, + .flags = IORESOURCE_MEM, + }, { + .start = data->synirq, + .end = data->synirq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->errirq, + .end = data->errirq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_alloc_mx3_camera( + const struct imx_ipu_core_data *data, + const struct mx3_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase + 0x60, + .end = data->iobase + 0x87, + .flags = IORESOURCE_MEM, + }, + }; + int ret = -ENOMEM; + struct platform_device *pdev; + + if (IS_ERR_OR_NULL(imx_ipu_coredev)) + return ERR_PTR(-ENODEV); + + pdev = platform_device_alloc("mx3-camera", 0); + if (!pdev) + goto err; + + pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + goto err; + + *pdev->dev.dma_mask = DMA_BIT_MASK(32); + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret) + goto err; + + if (pdata) { + struct mx3_camera_pdata *copied_pdata; + + ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (ret) { +err: + kfree(pdev->dev.dma_mask); + platform_device_put(pdev); + return ERR_PTR(-ENODEV); + } + copied_pdata = dev_get_platdata(&pdev->dev); + copied_pdata->dma_dev = &imx_ipu_coredev->dev; + } + + return pdev; +} + +struct platform_device *__init imx_add_mx3_sdc_fb( + const struct imx_ipu_core_data *data, + struct mx3fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase + 0xb4, + .end = data->iobase + 0x1bf, + .flags = IORESOURCE_MEM, + }, + }; + + if (IS_ERR_OR_NULL(imx_ipu_coredev)) + return ERR_PTR(-ENODEV); + + pdata->dma_dev = &imx_ipu_coredev->dev; + + return imx_add_platform_device_dmamask("mx3_sdc_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), + DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c new file mode 100644 index 00000000000..16d0ec4df5f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2010-2011 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _RTC_BASE_ADDR, \ + .irq = soc ## _INT_RTC, \ + } + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = + imx_mxc_rtc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_rtc( + const struct imx_mxc_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_rtc", -1, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index f4a60ab6763..f97eb3615b2 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -80,7 +80,7 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #ifdef CONFIG_SOC_IMX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = - imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); + imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K); const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { #define imx51_ecspi_data_entry(_id, _hwid) \ diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c index d69d343ff61..d3467f818c3 100644 --- a/arch/arm/plat-mxc/epit.c +++ b/arch/arm/plat-mxc/epit.c @@ -83,26 +83,12 @@ static void epit_irq_acknowledge(void) __raw_writel(EPITSR_OCIF, timer_base + EPITSR); } -static cycle_t epit_read(struct clocksource *cs) -{ - return 0 - __raw_readl(timer_base + EPITCNR); -} - -static struct clocksource clocksource_epit = { - .name = "epit", - .rating = 200, - .read = epit_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int __init epit_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - clocksource_register_hz(&clocksource_epit, c); - - return 0; + return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, + clocksource_mmio_readl_down); } /* clock event */ diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 57d59855f9e..6cd6d7f686f 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = get_irq_data(irq); + struct mxc_gpio_port *port = irq_get_handler_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = get_irq_data(irq); + struct mxc_gpio_port *port = irq_get_handler_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { @@ -295,6 +295,12 @@ static int mxc_gpio_direction_output(struct gpio_chip *chip, return 0; } +/* + * This lock class tells lockdep that GPIO irqs are in a different + * category than their parents, so it won't report false recursion. + */ +static struct lock_class_key gpio_lock_class; + int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) { int i, j; @@ -311,8 +317,9 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) __raw_writel(~0, port[i].base + GPIO_ISR); for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_level_irq); + irq_set_lockdep_class(j, &gpio_lock_class); + irq_set_chip_and_handler(j, &gpio_irq_chip, + handle_level_irq); set_irq_flags(j, IRQF_VALID); } @@ -331,21 +338,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { /* setup one handler for each entry */ - set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); - set_irq_data(port[i].irq, &port[i]); + irq_set_chained_handler(port[i].irq, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq, &port[i]); if (port[i].irq_high) { /* setup handler for GPIO 16 to 31 */ - set_irq_chained_handler(port[i].irq_high, - mx3_gpio_irq_handler); - set_irq_data(port[i].irq_high, &port[i]); + irq_set_chained_handler(port[i].irq_high, + mx3_gpio_irq_handler); + irq_set_handler_data(port[i].irq_high, + &port[i]); } } } if (cpu_is_mx2()) { /* setup one handler for all GPIO interrupts */ - set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); - set_irq_data(port[0].irq, port); + irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); + irq_set_handler_data(port[0].irq, port); } return 0; diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h index 5cd6466964a..6fda788ed0e 100644 --- a/arch/arm/plat-mxc/include/mach/audmux.h +++ b/arch/arm/plat-mxc/include/mach/audmux.h @@ -15,6 +15,14 @@ #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 +#define MX51_AUDMUX_PORT1_SSI0 0 +#define MX51_AUDMUX_PORT2_SSI1 1 +#define MX51_AUDMUX_PORT3 2 +#define MX51_AUDMUX_PORT4 3 +#define MX51_AUDMUX_PORT5 4 +#define MX51_AUDMUX_PORT6 5 +#define MX51_AUDMUX_PORT7 6 + /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ #define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) #define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) @@ -28,7 +36,7 @@ #define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) #define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) -/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */ +/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ #define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) #define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) #define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index a22ebe11a60..da7991832af 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -23,7 +23,6 @@ extern void mx35_map_io(void); extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); -extern void mxc91231_map_io(void); extern void imx1_init_early(void); extern void imx21_init_early(void); extern void imx25_init_early(void); @@ -33,7 +32,6 @@ extern void imx35_init_early(void); extern void imx50_init_early(void); extern void imx51_init_early(void); extern void imx53_init_early(void); -extern void mxc91231_init_early(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); @@ -45,7 +43,6 @@ extern void mx35_init_irq(void); extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); -extern void mxc91231_init_irq(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); @@ -58,14 +55,11 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); -extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); extern void mxc_arch_reset_init(void __iomem *); -extern void mxc91231_power_off(void); -extern void mxc91231_arch_reset(int, const char *); -extern void mxc91231_prepare_idle(void); extern void mx51_efikamx_reset(void); extern int mx53_revision(void); +extern int mx53_display_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 3b3a37c25c5..8e8d175e507 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -44,13 +44,6 @@ #define UART_PADDR MX51_UART1_BASE_ADDR #endif -#ifdef CONFIG_ARCH_MXC91231 -#ifdef UART_PADDR -#error "CONFIG_DEBUG_LL is incompatible with multiple archs" -#endif -#define UART_PADDR MXC91231_UART2_BASE_ADDR -#endif - #define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) .macro addruart, rp, rv diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8658c9caa65..fa8477337f9 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -166,6 +166,24 @@ struct platform_device *__init imx_add_imx_udc( const struct imx_imx_udc_data *data, const struct imxusb_platform_data *pdata); +#include <mach/ipu.h> +#include <mach/mx3fb.h> +#include <mach/mx3_camera.h> +struct imx_ipu_core_data { + resource_size_t iobase; + resource_size_t synirq; + resource_size_t errirq; +}; +struct platform_device *__init imx_add_ipu_core( + const struct imx_ipu_core_data *data, + const struct ipu_platform_data *pdata); +struct platform_device *__init imx_alloc_mx3_camera( + const struct imx_ipu_core_data *data, + const struct mx3_camera_pdata *pdata); +struct platform_device *__init imx_add_mx3_sdc_fb( + const struct imx_ipu_core_data *data, + struct mx3fb_platform_data *pdata); + #include <mach/mx1_camera.h> struct imx_mx1_camera_data { resource_size_t iobase; @@ -237,6 +255,15 @@ struct imx_mxc_pwm_data { struct platform_device *__init imx_add_mxc_pwm( const struct imx_mxc_pwm_data *data); +/* mxc_rtc */ +struct imx_mxc_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_rtc( + const struct imx_mxc_rtc_data *data); + +/* mxc_w1 */ struct imx_mxc_w1_data { resource_size_t iobase; }; diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index bd9bb979914..2e49e71b1b9 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -33,9 +33,9 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm - @ this macro checks which interrupt occured + @ this macro checks which interrupt occurred @ and returns its number in irqnr - @ and returns if an interrupt occured in irqstat + @ and returns if an interrupt occurred in irqstat .macro get_irqnr_and_base, irqnr, irqstat, base, tmp #ifndef CONFIG_MXC_TZIC @ Load offset & priority of the highest priority diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 26bb1bab4ae..67d3e2bed06 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -86,15 +86,6 @@ * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 - * mxc91231: - * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 - * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 - * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 - * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 - * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 - * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 */ #define IMX_IO_P2V(x) ( \ 0xf4000000 + \ @@ -104,6 +95,8 @@ #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) +#include <mach/mxc.h> + #ifdef CONFIG_ARCH_MX5 #include <mach/mx50.h> #include <mach/mx51.h> @@ -134,12 +127,6 @@ # include <mach/mx25.h> #endif -#ifdef CONFIG_ARCH_MXC91231 -# include <mach/mxc91231.h> -#endif - -#include <mach/mxc.h> - #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index b4f2de76946..4347a87d2bb 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -14,19 +14,26 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -#ifdef CONFIG_ARCH_MX3 -#define __arch_ioremap __mx3_ioremap +#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35) +#include <mach/hardware.h> + +#define __arch_ioremap __imx_ioremap #define __arch_iounmap __iounmap +#define addr_in_module(addr, mod) \ + ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) + static inline void __iomem * -__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) { - if (mtype == MT_DEVICE) { - /* Access all peripherals below 0x80000000 as nonshared device - * but leave l2cc alone. + if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) { + /* + * Access all peripherals below 0x80000000 as nonshared device + * on mx3, but leave l2cc alone. Otherwise cache corruptions + * can occur. */ - if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || - (phys_addr >= 0x30000000 + SZ_1M))) + if (phys_addr < 0x80000000 && + !addr_in_module(phys_addr, MX3x_L2CC)) mtype = MT_DEVICE_NONSHARED; } diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index d7f52c91f82..2e5244de7ff 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -89,13 +89,16 @@ #define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) #define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h index c4f116d214f..7a9b20abda0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h @@ -90,12 +90,12 @@ #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) +#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) +#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h deleted file mode 100644 index bf28df0d58b..00000000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_IOMUX_MXC91231_H__ -#define __MACH_IOMUX_MXC91231_H__ - -/* - * various IOMUX output functions - */ - -#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ -#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ -#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ -#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ -#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ -#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ -#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ -#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ -#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ -#define IOMUX_ICONFIG_FUNC 2 /* used as function */ -#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ -#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ - -#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) -#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) -#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) -#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) - -/* - * setups a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - * - if the pin is configured as a GPIO, we claim it through kernel gpiolib - */ -int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label); -/* - * setups mutliple pins - * convenient way to call the above function with tables - */ -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label); - -/* - * releases a single pin: - * - make it available for a future use by another driver - * - frees the GPIO if the pin was configured as GPIO - * - DOES NOT reconfigure the IOMUX in its reset state - */ -void mxc_iomux_release_pin(unsigned int pin_mode); -/* - * releases multiple pins - * convenvient way to call the above function with tables - */ -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); - -#define MUX_SIDE_AP (0) -#define MUX_SIDE_SP (1) - -#define MUX_SIDE_SHIFT (26) -#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT) - -#define MUX_GPIO_PORT_SHIFT (23) -#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT) - -#define MUX_GPIO_PIN_SHIFT (20) -#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT) - -#define MUX_REG_SHIFT (15) -#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT) - -#define MUX_FIELD_SHIFT (13) -#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT) - -#define MUX_PADGRP_SHIFT (8) -#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT) - -#define MUX_PIN_MASK (0xffffff << 8) - -#define GPIO_PORT_MAX (3) - -#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \ - (((side) << MUX_SIDE_SHIFT) | \ - (gport << MUX_GPIO_PORT_SHIFT) | \ - ((gpin) << MUX_GPIO_PIN_SHIFT) | \ - ((ctlreg) << MUX_REG_SHIFT) | \ - ((ctlfield) << MUX_FIELD_SHIFT) | \ - ((padgrp) << MUX_PADGRP_SHIFT)) - -#define MUX_MODE_OUT_SHIFT (4) -#define MUX_MODE_IN_SHIFT (0) -#define MUX_MODE_SHIFT (0) -#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT) - -#define IOMUX_MODE(pin, mode) \ - (pin | (mode << MUX_MODE_SHIFT)) - -enum iomux_pins { - /* AP Side pins */ - MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24), - MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24), - MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24), - MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24), - MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24), - MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24), - MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24), - MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28), - MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28), - MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28), - MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28), - MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9), - MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9), - MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9), - MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9), - MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9), - MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9), - MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9), - MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9), - MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28), - MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28), - MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28), - MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28), - MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28), - MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28), - MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28), - MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28), - MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28), - MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28), - MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28), - MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28), - MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28), - MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28), - MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28), - MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28), - MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28), - MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28), - MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28), - MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28), - MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28), - MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28), - MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28), - MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28), - MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28), - MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28), - MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28), - MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28), - MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28), - MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28), - MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28), - MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10), - MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10), - MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10), - MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10), - MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11), - MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11), - MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11), - MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11), - MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11), - MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21), - MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21), - MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21), - MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21), - MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21), - MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21), - MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21), - MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21), - MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21), - MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21), - MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21), - MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21), - MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21), - MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21), - MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12), - MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12), - MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9), - MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9), - MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9), - MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9), - MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9), - MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28), - MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28), - MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9), - MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9), - MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9), - MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22), - MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22), - MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22), - MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22), - MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23), - MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23), - MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23), - MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23), - MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28), - MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28), - MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28), - MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28), - MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10), - MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10), - MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10), - MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10), - MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11), - MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11), - MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11), - - /* Shared pins */ - MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28), - MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28), - MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28), - MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28), - MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28), - MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28), - MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28), - MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28), - MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28), - MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28), - MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28), - MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28), - MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28), - MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28), - MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28), - MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28), - MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25), - MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25), - MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25), - MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25), - MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25), - MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25), - MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26), - MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26), - MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26), - MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26), - MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28), - MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13), - MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13), - MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13), - MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13), - MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13), - MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26), - MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26), - MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28), - MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28), - MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28), - MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28), - MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28), - MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28), - MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28), -}; - -#define PIN_AP_MAX (104) -#define PIN_SP_MAX (41) - -#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX) - -/* - * Convenience values for use with mxc_iomux_mode() - * - * Format here is MXC91231_PIN_(pin name)__(function) - */ - -#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \ - IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC) -#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \ - IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC) -#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \ - IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1) -#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \ - IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1) - - -#endif /* __MACH_IOMUX_MXC91231_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index a3d930d3e65..35c89bcdf75 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -35,8 +35,6 @@ #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_SOC_IMX51 #define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MXC91231 -#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX3 #define MXC_GPIO_IRQS (32 * 3) #endif diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 5d51cbb9889..11be5cdbdd1 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -19,7 +19,6 @@ #define MX50_PHYS_OFFSET UL(0x70000000) #define MX51_PHYS_OFFSET UL(0x90000000) #define MX53_PHYS_OFFSET UL(0x70000000) -#define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 @@ -32,8 +31,6 @@ # define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET # elif defined CONFIG_ARCH_MX3 # define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET -# elif defined CONFIG_ARCH_MXC91231 -# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET # elif defined CONFIG_ARCH_MX50 # define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX51 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index cbc43ad5ef4..1dc1c522601 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -60,8 +60,8 @@ #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) +#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) +#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h index aaec2a6e7b3..5f2da75a47f 100644 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -282,4 +282,8 @@ #define MX50_INT_APBHDMA_CHAN6 116 #define MX50_INT_APBHDMA_CHAN7 117 +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) +extern int mx50_revision(void); +#endif + #endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 1eb339e6c85..dede19a766f 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -347,6 +347,7 @@ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); +extern void mx51_display_revision(void); #endif /* tape-out 1 defines */ diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index ace17864575..9d2a1ef84de 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -337,17 +337,4 @@ #define MX53_INT_GPIO7_LOW 107 #define MX53_INT_GPIO7_HIGH 108 -/* silicon revisions specific to i.MX53 */ -#define MX53_CHIP_REV_1_0 0x10 -#define MX53_CHIP_REV_1_1 0x11 -#define MX53_CHIP_REV_1_2 0x12 -#define MX53_CHIP_REV_1_3 0x13 -#define MX53_CHIP_REV_2_0 0x20 -#define MX53_CHIP_REV_2_1 0x21 -#define MX53_CHIP_REV_2_2 0x22 -#define MX53_CHIP_REV_2_3 0x23 -#define MX53_CHIP_REV_3_0 0x30 -#define MX53_CHIP_REV_3_1 0x31 -#define MX53_CHIP_REV_3_2 0x32 - #endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 7e072637eef..4ac53ce97c2 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -35,7 +35,6 @@ #define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 -#define MXC_CPU_MXC91231 91231 #define IMX_CHIP_REVISION_1_0 0x10 #define IMX_CHIP_REVISION_1_1 0x11 @@ -51,6 +50,20 @@ #define IMX_CHIP_REVISION_3_3 0x33 #define IMX_CHIP_REVISION_UNKNOWN 0xff +#define IMX_CHIP_REVISION_1_0_STRING "1.0" +#define IMX_CHIP_REVISION_1_1_STRING "1.1" +#define IMX_CHIP_REVISION_1_2_STRING "1.2" +#define IMX_CHIP_REVISION_1_3_STRING "1.3" +#define IMX_CHIP_REVISION_2_0_STRING "2.0" +#define IMX_CHIP_REVISION_2_1_STRING "2.1" +#define IMX_CHIP_REVISION_2_2_STRING "2.2" +#define IMX_CHIP_REVISION_2_3_STRING "2.3" +#define IMX_CHIP_REVISION_3_0_STRING "3.0" +#define IMX_CHIP_REVISION_3_1_STRING "3.1" +#define IMX_CHIP_REVISION_3_2_STRING "3.2" +#define IMX_CHIP_REVISION_3_3_STRING "3.3" +#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown" + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif @@ -163,35 +176,25 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx53() (0) #endif -#ifdef CONFIG_ARCH_MXC91231 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MXC91231 -# endif -# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231) -#else -# define cpu_is_mxc91231() (0) -#endif - #ifndef __ASSEMBLY__ struct cpu_op { u32 cpu_rate; }; -extern struct cpu_op *(*get_cpu_op)(int *op); -#endif +int tzic_enable_wake(int is_idle); +enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ + WAIT_UNCLOCKED, /* WAIT */ + WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ + STOP_POWER_ON, /* just STOP */ + STOP_POWER_OFF, /* STOP + SRPG */ +}; -#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) -/* These are deprecated, use mx[23][157]_setup_weimcs instead. */ -#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) -#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) -#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) +extern struct cpu_op *(*get_cpu_op)(int *op); #endif -#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) +#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) #endif /* __ASM_ARCH_MXC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h deleted file mode 100644 index 765190fe633..00000000000 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * - Platform specific register memory map - * - * Copyright 2005-2007 Motorola, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __MACH_MXC91231_H__ -#define __MACH_MXC91231_H__ - -/* - * L2CC - */ -#define MXC91231_L2CC_BASE_ADDR 0x30000000 -#define MXC91231_L2CC_SIZE SZ_64K - -/* - * AIPS 1 - */ -#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 -#define MXC91231_AIPS1_SIZE SZ_1M - -#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR -#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000) -#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000) -#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000) -#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000) -#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000) -#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000) -#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000) -#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000) -#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000) -#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000) -#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000) -#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000) -#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000) -#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000) -#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000) -#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000) - -/* - * AIPS 2 - */ -#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 -#define MXC91231_AIPS2_SIZE SZ_1M - -#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) -#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000) -#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000) -#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000) -#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000) -#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000) -#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000) -#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000) -#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000) -#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000) -#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000) -#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000) -#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000) -#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000) -#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000) -#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000) -#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000) -#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000) - -/* - * SPBA global module 0 - */ -#define MXC91231_SPBA0_BASE_ADDR 0x50000000 -#define MXC91231_SPBA0_SIZE SZ_1M - -#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) -#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000) -#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000) -#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000) -#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000) -#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000) -#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000) -#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000) -#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000) -#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000) -#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000) -#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000) -#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000) -#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000) -#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000) -#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000) -#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000) -#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000) -#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000) -#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) -#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000) -#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000) - -/* - * SPBA global module 1 - */ -#define MXC91231_SPBA1_BASE_ADDR 0x52000000 -#define MXC91231_SPBA1_SIZE SZ_1M - -#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) -#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000) - -/*! - * Defines for SPBA modules - */ -#define MXC91231_SPBA_SDHC1 0x04 -#define MXC91231_SPBA_SDHC2 0x08 -#define MXC91231_SPBA_UART3 0x0C -#define MXC91231_SPBA_CSPI2 0x10 -#define MXC91231_SPBA_SSI2 0x14 -#define MXC91231_SPBA_SIM 0x18 -#define MXC91231_SPBA_IIM 0x1C -#define MXC91231_SPBA_CTI_SDMA 0x20 -#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24 -#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28 -#define MXC91231_SPBA_CSPI1 0x30 -#define MXC91231_SPBA_MQSPI 0x34 -#define MXC91231_SPBA_EL1T 0x38 -#define MXC91231_SPBA_IOMUX 0x40 -#define MXC91231_SPBA_CRM_COM 0x44 -#define MXC91231_SPBA_CRM_AP 0x48 -#define MXC91231_SPBA_PLL0 0x4C -#define MXC91231_SPBA_PLL1 0x50 -#define MXC91231_SPBA_PLL2 0x54 -#define MXC91231_SPBA_GPIO4 0x58 -#define MXC91231_SPBA_SAHARA 0x5C - -/* - * ROMP and AVIC - */ -#define MXC91231_ROMP_BASE_ADDR 0x60000000 -#define MXC91231_ROMP_SIZE SZ_64K - -#define MXC91231_AVIC_BASE_ADDR 0x68000000 -#define MXC91231_AVIC_SIZE SZ_64K - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ -#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 -#define MXC91231_X_MEMC_SIZE SZ_64K - -#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) -#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000) -#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000) -#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000) -#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000) - -/* - * Memory regions and CS - * CPLD is connected on CS4 - * CS5 is TP1021 or it is not connected - * */ -#define MXC91231_FB_RAM_BASE_ADDR 0x78000000 -#define MXC91231_FB_RAM_SIZE SZ_256K -#define MXC91231_CSD0_BASE_ADDR 0x80000000 -#define MXC91231_CSD1_BASE_ADDR 0x90000000 -#define MXC91231_CS0_BASE_ADDR 0xA0000000 -#define MXC91231_CS1_BASE_ADDR 0xA8000000 -#define MXC91231_CS2_BASE_ADDR 0xB0000000 -#define MXC91231_CS3_BASE_ADDR 0xB2000000 -#define MXC91231_CS4_BASE_ADDR 0xB4000000 -#define MXC91231_CS5_BASE_ADDR 0xB6000000 - -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. - */ -#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) -#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#define MXC91231_INT_GPIO3 0 -#define MXC91231_INT_EL1T_CI 1 -#define MXC91231_INT_EL1T_RFCI 2 -#define MXC91231_INT_EL1T_RFI 3 -#define MXC91231_INT_EL1T_MCU 4 -#define MXC91231_INT_EL1T_IPI 5 -#define MXC91231_INT_MU_GEN 6 -#define MXC91231_INT_GPIO4 7 -#define MXC91231_INT_MMC_SDHC2 8 -#define MXC91231_INT_MMC_SDHC1 9 -#define MXC91231_INT_I2C 10 -#define MXC91231_INT_SSI2 11 -#define MXC91231_INT_SSI1 12 -#define MXC91231_INT_CSPI2 13 -#define MXC91231_INT_CSPI1 14 -#define MXC91231_INT_RTIC 15 -#define MXC91231_INT_SAHARA 15 -#define MXC91231_INT_HAC 15 -#define MXC91231_INT_UART3_RX 16 -#define MXC91231_INT_UART3_TX 17 -#define MXC91231_INT_UART3_MINT 18 -#define MXC91231_INT_ECT 19 -#define MXC91231_INT_SIM_IPB 20 -#define MXC91231_INT_SIM_DATA 21 -#define MXC91231_INT_RNGA 22 -#define MXC91231_INT_DSM_AP 23 -#define MXC91231_INT_KPP 24 -#define MXC91231_INT_RTC 25 -#define MXC91231_INT_PWM 26 -#define MXC91231_INT_GEMK_AP 27 -#define MXC91231_INT_EPIT 28 -#define MXC91231_INT_GPT 29 -#define MXC91231_INT_UART2_RX 30 -#define MXC91231_INT_UART2_TX 31 -#define MXC91231_INT_UART2_MINT 32 -#define MXC91231_INT_NANDFC 33 -#define MXC91231_INT_SDMA 34 -#define MXC91231_INT_USB_WAKEUP 35 -#define MXC91231_INT_USB_SOF 36 -#define MXC91231_INT_PMU_EVTMON 37 -#define MXC91231_INT_USB_FUNC 38 -#define MXC91231_INT_USB_DMA 39 -#define MXC91231_INT_USB_CTRL 40 -#define MXC91231_INT_IPU_ERR 41 -#define MXC91231_INT_IPU_SYN 42 -#define MXC91231_INT_UART1_RX 43 -#define MXC91231_INT_UART1_TX 44 -#define MXC91231_INT_UART1_MINT 45 -#define MXC91231_INT_IIM 46 -#define MXC91231_INT_MU_RX_OR 47 -#define MXC91231_INT_MU_TX_OR 48 -#define MXC91231_INT_SCC_SCM 49 -#define MXC91231_INT_SCC_SMN 50 -#define MXC91231_INT_GPIO2 51 -#define MXC91231_INT_GPIO1 52 -#define MXC91231_INT_MQSPI1 53 -#define MXC91231_INT_MQSPI2 54 -#define MXC91231_INT_WDOG2 55 -#define MXC91231_INT_EXT_INT7 56 -#define MXC91231_INT_EXT_INT6 57 -#define MXC91231_INT_EXT_INT5 58 -#define MXC91231_INT_EXT_INT4 59 -#define MXC91231_INT_EXT_INT3 60 -#define MXC91231_INT_EXT_INT2 61 -#define MXC91231_INT_EXT_INT1 62 -#define MXC91231_INT_EXT_INT0 63 - -#define MXC91231_MAX_INT_LINES 63 -#define MXC91231_MAX_EXT_LINES 8 - -#endif /* __MACH_MXC91231_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h index 04c0d060d81..6bb96ef1600 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -24,7 +24,7 @@ struct mxc_nand_platform_data { unsigned int width; /* data bus width in bytes */ - unsigned int hw_ecc:1; /* 0 if supress hardware ECC */ + unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */ unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */ struct mtd_partition *parts; /* partition table */ int nr_parts; /* size of parts */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 95be51bfe9a..51f02a9d41a 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -20,14 +20,10 @@ #include <mach/hardware.h> #include <mach/common.h> +extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); + static inline void arch_idle(void) { -#ifdef CONFIG_ARCH_MXC91231 - if (cpu_is_mxc91231()) { - /* Need this to set DSM low-power mode */ - mxc91231_prepare_idle(); - } -#endif /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ if (cpu_is_mx31() || cpu_is_mx35()) { unsigned long reg = 0; @@ -54,7 +50,9 @@ static inline void arch_idle(void) "orr %0, %0, #0x00000004\n" "mcr p15, 0, %0, c1, c0, 0\n" : "=r" (reg)); - } else + } else if (cpu_is_mx51()) + mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + else cpu_do_idle(); } diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 2d9624697cc..d61d5c74817 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -26,8 +26,6 @@ #define CLOCK_TICK_RATE 16000000 #elif defined CONFIG_ARCH_MX5 #define CLOCK_TICK_RATE 8000000 -#elif defined CONFIG_ARCH_MXC91231 -#define CLOCK_TICK_RATE 13000000 #endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 4864b0afd44..d85e2d1c032 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -21,7 +21,7 @@ #include <asm/mach-types.h> -static unsigned long uart_base; +unsigned long uart_base; #define UART(x) (*(volatile unsigned long *)(uart_base + (x))) diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index 0c799ac2773..e1c6eff7258 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c @@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) ret = -ENOSYS; - base = get_irq_chip(irq); + base = irq_get_chip(irq); if (base) { chip = container_of(base, struct mxc_irq_chip, base); if (chip->set_priority) @@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) ret = -ENOSYS; - base = get_irq_chip(irq); + base = irq_get_chip(irq); if (base) { chip = container_of(base, struct mxc_irq_chip, base); if (chip->set_irq_fiq) diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S index 4ddce565b35..8397a2dd19f 100644 --- a/arch/arm/plat-mxc/ssi-fiq.S +++ b/arch/arm/plat-mxc/ssi-fiq.S @@ -124,6 +124,8 @@ imx_ssi_fiq_start: 1: @ return from FIQ subs pc, lr, #4 + + .align imx_ssi_fiq_base: .word 0x0 imx_ssi_fiq_rx_buffer: diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 3455fc0575a..8024f2ac177 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -37,12 +37,6 @@ void arch_reset(char mode, const char *cmd) { unsigned int wcr_enable; -#ifdef CONFIG_ARCH_MXC91231 - if (cpu_is_mxc91231()) { - mxc91231_arch_reset(mode, cmd); - return; - } -#endif #ifdef CONFIG_MACH_MX51_EFIKAMX if (machine_is_mx51_efikamx()) { mx51_efikamx_reset(); diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 9f0c2610595..4b0fe285e83 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -27,6 +27,7 @@ #include <linux/clk.h> #include <mach/hardware.h> +#include <asm/sched_clock.h> #include <asm/mach/time.h> #include <mach/common.h> @@ -53,7 +54,7 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35, MX25, MXC91231, MX5 */ +/* MX31, MX35, MX25, MX5 */ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define V2_TCTL_CLK_IPG (1 << 6) #define V2_TCTL_FRR (1 << 9) @@ -105,34 +106,32 @@ static void gpt_irq_acknowledge(void) __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); } -static cycle_t mx1_2_get_cycles(struct clocksource *cs) +static void __iomem *sched_clock_reg; + +static DEFINE_CLOCK_DATA(cd); +unsigned long long notrace sched_clock(void) { - return __raw_readl(timer_base + MX1_2_TCN); + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + + return cyc_to_sched_clock(&cd, cyc, (u32)~0); } -static cycle_t v2_get_cycles(struct clocksource *cs) +static void notrace mxc_update_sched_clock(void) { - return __raw_readl(timer_base + V2_TCN); + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; + update_sched_clock(&cd, cyc, (u32)~0); } -static struct clocksource clocksource_mxc = { - .name = "mxc_timer1", - .rating = 200, - .read = mx1_2_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); + void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); - if (timer_is_v2()) - clocksource_mxc.read = v2_get_cycles; - - clocksource_register_hz(&clocksource_mxc, c); + sched_clock_reg = reg; - return 0; + init_sched_clock(&cd, mxc_update_sched_clock, 32, c); + return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, + clocksource_mmio_readl_up); } /* clock event */ diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index bc3a6be8a27..57f9395f87c 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_tzic_chip.base); - set_irq_handler(i, handle_level_irq); + irq_set_chip_and_handler(i, &mxc_tzic_chip.base, + handle_level_irq); set_irq_flags(i, IRQF_VALID); } diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig index 187f4e84bb2..18296ee6880 100644 --- a/arch/arm/plat-nomadik/Kconfig +++ b/arch/arm/plat-nomadik/Kconfig @@ -5,6 +5,7 @@ config PLAT_NOMADIK bool depends on ARCH_NOMADIK || ARCH_U8500 + select CLKSRC_MMIO default y help Common platform code for Nomadik and other ST-Ericsson diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 80643bc38e1..307b8131aa8 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -23,6 +23,8 @@ #include <linux/irq.h> #include <linux/slab.h> +#include <asm/mach/irq.h> + #include <plat/pincfg.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -54,6 +56,7 @@ struct nmk_gpio_chip { u32 rwimsc; u32 fwimsc; u32 slpm; + u32 enabled; }; static struct nmk_gpio_chip * @@ -318,7 +321,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) struct nmk_gpio_chip *nmk_chip; int pin = PIN_NUM(cfgs[i]); - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); if (!nmk_chip) { ret = -EINVAL; break; @@ -397,7 +400,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -430,7 +433,7 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -456,7 +459,7 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) struct nmk_gpio_chip *nmk_chip; unsigned long flags; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -473,7 +476,7 @@ int nmk_gpio_get_mode(int gpio) struct nmk_gpio_chip *nmk_chip; u32 afunc, bfunc, bit; - nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); + nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); if (!nmk_chip) return -EINVAL; @@ -541,13 +544,6 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, int gpio, bool on) { -#ifdef CONFIG_ARCH_U8500 - if (cpu_is_u8500v2()) { - __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, - on ? NMK_GPIO_SLPM_WAKEUP_ENABLE - : NMK_GPIO_SLPM_WAKEUP_DISABLE); - } -#endif __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); } @@ -564,6 +560,11 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) if (!nmk_chip) return -EINVAL; + if (enable) + nmk_chip->enabled |= bitmask; + else + nmk_chip->enabled &= ~bitmask; + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); @@ -590,8 +591,6 @@ static void nmk_gpio_irq_unmask(struct irq_data *d) static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) { - struct irq_desc *desc = irq_to_desc(d->irq); - bool enabled = !(desc->status & IRQ_DISABLED); struct nmk_gpio_chip *nmk_chip; unsigned long flags; u32 bitmask; @@ -606,7 +605,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); spin_lock(&nmk_chip->lock); - if (!enabled) + if (!(nmk_chip->enabled & bitmask)) __nmk_gpio_set_wake(nmk_chip, gpio, on); if (on) @@ -622,9 +621,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - struct irq_desc *desc = irq_to_desc(d->irq); - bool enabled = !(desc->status & IRQ_DISABLED); - bool wake = desc->wake_depth; + bool enabled, wake = irqd_is_wakeup_set(d); int gpio; struct nmk_gpio_chip *nmk_chip; unsigned long flags; @@ -641,6 +638,8 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (type & IRQ_TYPE_LEVEL_LOW) return -EINVAL; + enabled = nmk_chip->enabled & bitmask; + spin_lock_irqsave(&nmk_chip->lock, flags); if (enabled) @@ -681,18 +680,12 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, u32 status) { struct nmk_gpio_chip *nmk_chip; - struct irq_chip *host_chip = get_irq_chip(irq); + struct irq_chip *host_chip = irq_get_chip(irq); unsigned int first_irq; - if (host_chip->irq_mask_ack) - host_chip->irq_mask_ack(&desc->irq_data); - else { - host_chip->irq_mask(&desc->irq_data); - if (host_chip->irq_ack) - host_chip->irq_ack(&desc->irq_data); - } + chained_irq_enter(host_chip, desc); - nmk_chip = get_irq_data(irq); + nmk_chip = irq_get_handler_data(irq); first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); while (status) { int bit = __ffs(status); @@ -701,12 +694,12 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, status &= ~BIT(bit); } - host_chip->irq_unmask(&desc->irq_data); + chained_irq_exit(host_chip, desc); } static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); __nmk_gpio_irq_handler(irq, desc, status); @@ -715,7 +708,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) static void nmk_gpio_secondary_irq_handler(unsigned int irq, struct irq_desc *desc) { - struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); __nmk_gpio_irq_handler(irq, desc, status); @@ -728,20 +721,20 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { - set_irq_chip(i, &nmk_gpio_irq_chip); - set_irq_handler(i, handle_edge_irq); + irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, + handle_edge_irq); set_irq_flags(i, IRQF_VALID); - set_irq_chip_data(i, nmk_chip); - set_irq_type(i, IRQ_TYPE_EDGE_FALLING); + irq_set_chip_data(i, nmk_chip); + irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); } - set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); - set_irq_data(nmk_chip->parent_irq, nmk_chip); + irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); + irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); if (nmk_chip->secondary_parent_irq >= 0) { - set_irq_chained_handler(nmk_chip->secondary_parent_irq, + irq_set_chained_handler(nmk_chip->secondary_parent_irq, nmk_gpio_secondary_irq_handler); - set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); + irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); } return 0; diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 41723402006..ef74e157a9d 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -26,29 +26,6 @@ void __iomem *mtu_base; /* Assigned by machine code */ /* - * Kernel assumes that sched_clock can be called early - * but the MTU may not yet be initialized. - */ -static cycle_t nmdk_read_timer_dummy(struct clocksource *cs) -{ - return 0; -} - -/* clocksource: MTU decrements, so we negate the value being read. */ -static cycle_t nmdk_read_timer(struct clocksource *cs) -{ - return -readl(mtu_base + MTU_VAL(0)); -} - -static struct clocksource nmdk_clksrc = { - .name = "mtu_0", - .rating = 200, - .read = nmdk_read_timer_dummy, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some * better resolution when scheduling the kernel. @@ -172,12 +149,10 @@ void __init nmdk_timer_init(void) writel(0, mtu_base + MTU_BGLR(0)); writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); - /* Now the clock source is ready */ - nmdk_clksrc.read = nmdk_read_timer; - - if (clocksource_register_hz(&nmdk_clksrc, rate)) + if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", + rate, 200, 32, clocksource_mmio_readl_down)) pr_err("timer: failed to initialize clock source %s\n", - nmdk_clksrc.name); + "mtu_0"); init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index cd5f993612f..49a4c75243f 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -12,12 +12,14 @@ choice config ARCH_OMAP1 bool "TI OMAP1" select CLKDEV_LOOKUP + select CLKSRC_MMIO help "Systems based on omap7xx, omap15xx or omap16xx" config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select CLKDEV_LOOKUP + select GENERIC_IRQ_CHIP select OMAP_DM_TIMER help "Systems based on OMAP2, OMAP3 or OMAP4" diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 7d9f815cede..ea28f98d5d6 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -280,7 +280,7 @@ EXPORT_SYMBOL(omap_dsp_get_mempool_base); * Claiming GPIOs, and setting their direction and initial values, is the * responsibility of the device drivers. So is responding to probe(). * - * Board-specific knowlege like creating devices or pin setup is to be + * Board-specific knowledge like creating devices or pin setup is to be * kept out of drivers as much as possible. In particular, pin setup * may be handled by the boot loader, and drivers should expect it will * normally have been done by the time they're probed. diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 2ec3b5d9f21..c22217c2ee5 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1019,7 +1019,7 @@ EXPORT_SYMBOL(omap_set_dma_callback); * If the channel is running the caller must disable interrupts prior calling * this function and process the returned value before re-enabling interrupt to * prevent races with the interrupt handler. Note that in continuous mode there - * is a chance for CSSA_L register overflow inbetween the two reads resulting + * is a chance for CSSA_L register overflow between the two reads resulting * in incorrect return value. */ dma_addr_t omap_get_dma_src_pos(int lch) @@ -1046,7 +1046,7 @@ EXPORT_SYMBOL(omap_get_dma_src_pos); * If the channel is running the caller must disable interrupts prior calling * this function and process the returned value before re-enabling interrupt to * prevent races with the interrupt handler. Note that in continuous mode there - * is a chance for CDSA_L register overflow inbetween the two reads resulting + * is a chance for CDSA_L register overflow between the two reads resulting * in incorrect return value. */ dma_addr_t omap_get_dma_dst_pos(int lch) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 971d1863694..efb86939019 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -17,7 +17,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> @@ -755,18 +755,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) bank = irq_data_get_irq_chip_data(d); spin_lock_irqsave(&bank->lock, flags); retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); - if (retval == 0) { - struct irq_desc *desc = irq_to_desc(d->irq); - - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type; - } spin_unlock_irqrestore(&bank->lock, flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __set_irq_handler_unlocked(d->irq, handle_level_irq); + __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __set_irq_handler_unlocked(d->irq, handle_edge_irq); + __irq_set_handler_locked(d->irq, handle_edge_irq); return retval; } @@ -1143,10 +1137,11 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) struct gpio_bank *bank; u32 retrigger = 0; int unmasked = 0; + struct irq_chip *chip = irq_desc_get_chip(desc); - desc->irq_data.chip->irq_ack(&desc->irq_data); + chained_irq_enter(chip, desc); - bank = get_irq_data(irq); + bank = irq_get_handler_data(irq); #ifdef CONFIG_ARCH_OMAP1 if (bank->method == METHOD_MPUIO) isr_reg = bank->base + @@ -1201,7 +1196,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) configured, we could unmask GPIO bank interrupt immediately */ if (!level_mask && !unmasked) { unmasked = 1; - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } isr |= retrigger; @@ -1237,7 +1232,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) interrupt */ exit: if (!unmasked) - desc->irq_data.chip->irq_unmask(&desc->irq_data); + chained_irq_exit(chip, desc); } static void gpio_irq_shutdown(struct irq_data *d) @@ -1270,8 +1265,7 @@ static void gpio_unmask_irq(struct irq_data *d) unsigned int gpio = d->irq - IH_GPIO_BASE; struct gpio_bank *bank = irq_data_get_irq_chip_data(d); unsigned int irq_mask = 1 << get_gpio_index(gpio); - struct irq_desc *desc = irq_to_desc(d->irq); - u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; + u32 trigger = irqd_get_trigger_type(d); if (trigger) _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); @@ -1379,9 +1373,7 @@ static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { .resume_noirq = omap_mpuio_resume_noirq, }; -/* use platform_driver for this, now that there's no longer any - * point to sys_device (other than not disturbing old code). - */ +/* use platform_driver for this. */ static struct platform_driver omap_mpuio_driver = { .driver = { .name = "mpuio", @@ -1672,19 +1664,17 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + bank_width; j++) { - struct irq_desc *d = irq_to_desc(j); - - lockdep_set_class(&d->lock, &gpio_lock_class); - set_irq_chip_data(j, bank); + irq_set_lockdep_class(j, &gpio_lock_class); + irq_set_chip_data(j, bank); if (bank_is_mpuio(bank)) - set_irq_chip(j, &mpuio_irq_chip); + irq_set_chip(j, &mpuio_irq_chip); else - set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_simple_irq); + irq_set_chip(j, &gpio_irq_chip); + irq_set_handler(j, handle_simple_irq); set_irq_flags(j, IRQF_VALID); } - set_irq_chained_handler(bank->irq, gpio_irq_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, gpio_irq_handler); + irq_set_handler_data(bank->irq, bank); } static int __devinit omap_gpio_probe(struct platform_device *pdev) @@ -1754,7 +1744,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) } #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) -static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) +static int omap_gpio_suspend(void) { int i; @@ -1804,12 +1794,12 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) return 0; } -static int omap_gpio_resume(struct sys_device *dev) +static void omap_gpio_resume(void) { int i; if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) - return 0; + return; for (i = 0; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; @@ -1845,21 +1835,13 @@ static int omap_gpio_resume(struct sys_device *dev) __raw_writel(bank->saved_wakeup, wake_set); spin_unlock_irqrestore(&bank->lock, flags); } - - return 0; } -static struct sysdev_class omap_gpio_sysclass = { - .name = "gpio", +static struct syscore_ops omap_gpio_syscore_ops = { .suspend = omap_gpio_suspend, .resume = omap_gpio_resume, }; -static struct sys_device omap_gpio_device = { - .id = 0, - .cls = &omap_gpio_sysclass, -}; - #endif #ifdef CONFIG_ARCH_OMAP2PLUS @@ -2117,21 +2099,14 @@ postcore_initcall(omap_gpio_drv_reg); static int __init omap_gpio_sysinit(void) { - int ret = 0; - mpuio_init(); #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) - if (cpu_is_omap16xx() || cpu_class_is_omap2()) { - if (ret == 0) { - ret = sysdev_class_register(&omap_gpio_sysclass); - if (ret == 0) - ret = sysdev_register(&omap_gpio_device); - } - } + if (cpu_is_omap16xx() || cpu_class_is_omap2()) + register_syscore_ops(&omap_gpio_syscore_ops); #endif - return ret; + return 0; } arch_initcall(omap_gpio_sysinit); diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h index 3e6327016b4..3083195123e 100644 --- a/arch/arm/plat-omap/include/plat/flash.h +++ b/arch/arm/plat-omap/include/plat/flash.h @@ -11,6 +11,6 @@ #include <linux/mtd/map.h> -extern void omap1_set_vpp(struct map_info *map, int enable); +extern void omap1_set_vpp(struct platform_device *pdev, int enable); #endif diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index d6f9fa0f62a..cac2e8ac696 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -93,7 +93,7 @@ extern void omap_gpio_restore_context(void); /* Wrappers for "new style" GPIO calls, using the new infrastructure * which lets us plug in FPGA, I2C, and other implementations. * * - * The original OMAP-specfic calls should eventually be removed. + * The original OMAP-specific calls should eventually be removed. */ #include <linux/errno.h> diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 12b31616503..1527929b445 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -90,7 +90,7 @@ enum omap_ecc { /* 1-bit ecc: stored at end of spare area */ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ - /* 1-bit ecc: stored at begining of spare area as romcode */ + /* 1-bit ecc: stored at beginning of spare area as romcode */ OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */ }; diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h deleted file mode 100644 index 7a10257909e..00000000000 --- a/arch/arm/plat-omap/include/plat/smp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * OMAP4 machine specific smp.h - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Author: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Interface functions needed for the SMP. This file is based on arm - * realview smp platform. - * Copyright (c) 2003 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef OMAP_ARCH_SMP_H -#define OMAP_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* Needed for secondary core boot */ -extern void omap_secondary_startup(void); -extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); -extern void omap_auxcoreboot_addr(u32 cpu_addr); -extern u32 omap_read_auxcoreboot0(void); - -/* - * We use Soft IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 30b891c4a93..565d2664f5a 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -27,8 +27,8 @@ #define MDR1_MODE_MASK 0x07 -static volatile u8 *uart_base; -static int uart_shift; +volatile u8 *uart_base; +int uart_shift; /* * Store the DEBUG_LL uart number into memory. diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 8a51fd58f65..34fc31ee908 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -793,6 +793,8 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) clk_enable(obj->clk); errs = iommu_report_fault(obj, &da); clk_disable(obj->clk); + if (errs == 0) + return IRQ_HANDLED; /* Fault callback or TLB/PTE Dynamic loading */ if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index d598d9fd65a..5587acf0eb2 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1103,7 +1103,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf) /* resend */ return -1; } else { - /* wait for recieve confirmation */ + /* wait for receive confirmation */ int attemps = 0; while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) { if (attemps++ > 1000) { diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 9bbda9acb73..a37b8eb65b7 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -536,6 +536,28 @@ int omap_early_device_register(struct omap_device *od) return 0; } +static int _od_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + return omap_device_idle(pdev); +} + +static int _od_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + return omap_device_enable(pdev); +} + +static struct dev_power_domain omap_device_power_domain = { + .ops = { + .runtime_suspend = _od_runtime_suspend, + .runtime_resume = _od_runtime_resume, + USE_PLATFORM_PM_SLEEP_OPS + } +}; + /** * omap_device_register - register an omap_device with one omap_hwmod * @od: struct omap_device * to register @@ -549,6 +571,7 @@ int omap_device_register(struct omap_device *od) pr_debug("omap_device: %s: registering\n", od->pdev.name); od->pdev.dev.parent = &omap_device_parent; + od->pdev.dev.pwr_domain = &omap_device_power_domain; return platform_device_register(&od->pdev); } diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 56021a72e10..95a5fc53b6d 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o +obj-y := irq.o pcie.o time.o common.o mpp.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c new file mode 100644 index 00000000000..9e5451b3c8e --- /dev/null +++ b/arch/arm/plat-orion/common.c @@ -0,0 +1,957 @@ +/* + * arch/arm/plat-orion/common.c + * + * Marvell Orion SoC common setup code used by multiple mach-/common.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/serial_8250.h> +#include <linux/mbus.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/mv643xx_i2c.h> +#include <net/dsa.h> +#include <linux/spi/orion_spi.h> +#include <plat/orion_wdt.h> +#include <plat/mv_xor.h> +#include <plat/ehci-orion.h> + +/* Fill in the resources structure and link it into the platform + device structure. There is always a memory region, and nearly + always an interrupt.*/ +static void fill_resources(struct platform_device *device, + struct resource *resources, + resource_size_t mapbase, + resource_size_t size, + unsigned int irq) +{ + device->resource = resources; + device->num_resources = 1; + resources[0].flags = IORESOURCE_MEM; + resources[0].start = mapbase; + resources[0].end = mapbase + size; + + if (irq != NO_IRQ) { + device->num_resources++; + resources[1].flags = IORESOURCE_IRQ; + resources[1].start = irq; + resources[1].end = irq; + } +} + +/***************************************************************************** + * UART + ****************************************************************************/ +static void __init uart_complete( + struct platform_device *orion_uart, + struct plat_serial8250_port *data, + struct resource *resources, + unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + data->mapbase = mapbase; + data->membase = (void __iomem *)membase; + data->irq = irq; + data->uartclk = uartclk; + orion_uart->dev.platform_data = data; + + fill_resources(orion_uart, resources, mapbase, 0xff, irq); + platform_device_register(orion_uart); +} + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart0_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart0_resources[2]; + +static struct platform_device orion_uart0 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, +}; + +void __init orion_uart0_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart1_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart1_resources[2]; + +static struct platform_device orion_uart1 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, +}; + +void __init orion_uart1_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * UART2 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart2_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart2_resources[2]; + +static struct platform_device orion_uart2 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, +}; + +void __init orion_uart2_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * UART3 + ****************************************************************************/ +static struct plat_serial8250_port orion_uart3_data[] = { + { + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + }, { + }, +}; + +static struct resource orion_uart3_resources[2]; + +static struct platform_device orion_uart3 = { + .name = "serial8250", + .id = 3, +}; + +void __init orion_uart3_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk) +{ + uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources, + membase, mapbase, irq, uartclk); +} + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static struct resource orion_rtc_resource[2]; + +void __init orion_rtc_init(unsigned long mapbase, + unsigned long irq) +{ + orion_rtc_resource[0].start = mapbase; + orion_rtc_resource[0].end = mapbase + SZ_32 - 1; + orion_rtc_resource[0].flags = IORESOURCE_MEM; + orion_rtc_resource[1].start = irq; + orion_rtc_resource[1].end = irq; + orion_rtc_resource[1].flags = IORESOURCE_IRQ; + + platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2); +} + +/***************************************************************************** + * GE + ****************************************************************************/ +static __init void ge_complete( + struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, + struct mbus_dram_target_info *mbus_dram_info, int tclk, + struct resource *orion_ge_resource, unsigned long irq, + struct platform_device *orion_ge_shared, + struct mv643xx_eth_platform_data *eth_data, + struct platform_device *orion_ge) +{ + orion_ge_shared_data->dram = mbus_dram_info; + orion_ge_shared_data->t_clk = tclk; + orion_ge_resource->start = irq; + orion_ge_resource->end = irq; + eth_data->shared = orion_ge_shared; + orion_ge->dev.platform_data = eth_data; + + platform_device_register(orion_ge_shared); + platform_device_register(orion_ge); +} + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; + +static struct resource orion_ge00_shared_resources[] = { + { + .name = "ge00 base", + }, { + .name = "ge00 err irq", + }, +}; + +static struct platform_device orion_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &orion_ge00_shared_data, + }, +}; + +static struct resource orion_ge00_resources[] = { + { + .name = "ge00 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = orion_ge00_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, + orion_ge00_resources, irq, &orion_ge00_shared, + eth_data, &orion_ge00); +} + +/***************************************************************************** + * GE01 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = { + .shared_smi = &orion_ge00_shared, +}; + +static struct resource orion_ge01_shared_resources[] = { + { + .name = "ge01 base", + }, { + .name = "ge01 err irq", + }, +}; + +static struct platform_device orion_ge01_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_ge01_shared_data, + }, +}; + +static struct resource orion_ge01_resources[] = { + { + .name = "ge01 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge01 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 1, + .resource = orion_ge01_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, + orion_ge01_resources, irq, &orion_ge01_shared, + eth_data, &orion_ge01); +} + +/***************************************************************************** + * GE10 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = { + .shared_smi = &orion_ge00_shared, +}; + +static struct resource orion_ge10_shared_resources[] = { + { + .name = "ge10 base", + }, { + .name = "ge10 err irq", + }, +}; + +static struct platform_device orion_ge10_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_ge10_shared_data, + }, +}; + +static struct resource orion_ge10_resources[] = { + { + .name = "ge10 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge10 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 2, + .resource = orion_ge10_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, + orion_ge10_resources, irq, &orion_ge10_shared, + eth_data, &orion_ge10); +} + +/***************************************************************************** + * GE11 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = { + .shared_smi = &orion_ge00_shared, +}; + +static struct resource orion_ge11_shared_resources[] = { + { + .name = "ge11 base", + }, { + .name = "ge11 err irq", + }, +}; + +static struct platform_device orion_ge11_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_ge11_shared_data, + }, +}; + +static struct resource orion_ge11_resources[] = { + { + .name = "ge11 irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_ge11 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 2, + .resource = orion_ge11_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk) +{ + fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, + mapbase + 0x2000, SZ_16K - 1, irq_err); + ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, + orion_ge11_resources, irq, &orion_ge11_shared, + eth_data, &orion_ge11); +} + +/***************************************************************************** + * Ethernet switch + ****************************************************************************/ +static struct resource orion_switch_resources[] = { + { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion_switch_device = { + .name = "dsa", + .id = 0, + .num_resources = 0, + .resource = orion_switch_resources, +}; + +void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq) +{ + int i; + + if (irq != NO_IRQ) { + orion_switch_resources[0].start = irq; + orion_switch_resources[0].end = irq; + orion_switch_device.num_resources = 1; + } + + d->netdev = &orion_ge00.dev; + for (i = 0; i < d->nr_chips; i++) + d->chip[i].mii_bus = &orion_ge00_shared.dev; + orion_switch_device.dev.platform_data = d; + + platform_device_register(&orion_switch_device); +} + +/***************************************************************************** + * I2C + ****************************************************************************/ +static struct mv64xxx_i2c_pdata orion_i2c_pdata = { + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource orion_i2c_resources[2]; + +static struct platform_device orion_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .dev = { + .platform_data = &orion_i2c_pdata, + }, +}; + +static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = { + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource orion_i2c_1_resources[2]; + +static struct platform_device orion_i2c_1 = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 1, + .dev = { + .platform_data = &orion_i2c_1_pdata, + }, +}; + +void __init orion_i2c_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m) +{ + orion_i2c_pdata.freq_m = freq_m; + fill_resources(&orion_i2c, orion_i2c_resources, mapbase, + SZ_32 - 1, irq); + platform_device_register(&orion_i2c); +} + +void __init orion_i2c_1_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m) +{ + orion_i2c_1_pdata.freq_m = freq_m; + fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase, + SZ_32 - 1, irq); + platform_device_register(&orion_i2c_1); +} + +/***************************************************************************** + * SPI + ****************************************************************************/ +static struct orion_spi_info orion_spi_plat_data; +static struct resource orion_spi_resources; + +static struct platform_device orion_spi = { + .name = "orion_spi", + .id = 0, + .dev = { + .platform_data = &orion_spi_plat_data, + }, +}; + +static struct orion_spi_info orion_spi_1_plat_data; +static struct resource orion_spi_1_resources; + +static struct platform_device orion_spi_1 = { + .name = "orion_spi", + .id = 1, + .dev = { + .platform_data = &orion_spi_1_plat_data, + }, +}; + +/* Note: The SPI silicon core does have interrupts. However the + * current Linux software driver does not use interrupts. */ + +void __init orion_spi_init(unsigned long mapbase, + unsigned long tclk) +{ + orion_spi_plat_data.tclk = tclk; + fill_resources(&orion_spi, &orion_spi_resources, + mapbase, SZ_512 - 1, NO_IRQ); + platform_device_register(&orion_spi); +} + +void __init orion_spi_1_init(unsigned long mapbase, + unsigned long tclk) +{ + orion_spi_1_plat_data.tclk = tclk; + fill_resources(&orion_spi_1, &orion_spi_1_resources, + mapbase, SZ_512 - 1, NO_IRQ); + platform_device_register(&orion_spi_1); +} + +/***************************************************************************** + * Watchdog + ****************************************************************************/ +static struct orion_wdt_platform_data orion_wdt_data; + +static struct platform_device orion_wdt_device = { + .name = "orion_wdt", + .id = -1, + .dev = { + .platform_data = &orion_wdt_data, + }, + .num_resources = 0, +}; + +void __init orion_wdt_init(unsigned long tclk) +{ + orion_wdt_data.tclk = tclk; + platform_device_register(&orion_wdt_device); +} + +/***************************************************************************** + * XOR + ****************************************************************************/ +static struct mv_xor_platform_shared_data orion_xor_shared_data; + +static u64 orion_xor_dmamask = DMA_BIT_MASK(32); + +void __init orion_xor_init_channels( + struct mv_xor_platform_data *orion_xor0_data, + struct platform_device *orion_xor0_channel, + struct mv_xor_platform_data *orion_xor1_data, + struct platform_device *orion_xor1_channel) +{ + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask); + dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask); + platform_device_register(orion_xor0_channel); + + dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask); + dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask); + dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask); + platform_device_register(orion_xor1_channel); +} + +/***************************************************************************** + * XOR0 + ****************************************************************************/ +static struct resource orion_xor0_shared_resources[] = { + { + .name = "xor 0 low", + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &orion_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), + .resource = orion_xor0_shared_resources, +}; + +static struct resource orion_xor00_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor00_data = { + .shared = &orion_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor00_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion_xor00_resources), + .resource = orion_xor00_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor00_data, + }, +}; + +static struct resource orion_xor01_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor01_data = { + .shared = &orion_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor01_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(orion_xor01_resources), + .resource = orion_xor01_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor01_data, + }, +}; + +void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1) +{ + orion_xor_shared_data.dram = mbus_dram_info; + + orion_xor0_shared_resources[0].start = mapbase_low; + orion_xor0_shared_resources[0].end = mapbase_low + 0xff; + orion_xor0_shared_resources[1].start = mapbase_high; + orion_xor0_shared_resources[1].end = mapbase_high + 0xff; + + orion_xor00_resources[0].start = irq_0; + orion_xor00_resources[0].end = irq_0; + orion_xor01_resources[0].start = irq_1; + orion_xor01_resources[0].end = irq_1; + + platform_device_register(&orion_xor0_shared); + + orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel, + &orion_xor01_data, &orion_xor01_channel); +} + +/***************************************************************************** + * XOR1 + ****************************************************************************/ +static struct resource orion_xor1_shared_resources[] = { + { + .name = "xor 1 low", + .flags = IORESOURCE_MEM, + }, { + .name = "xor 1 high", + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion_xor1_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &orion_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), + .resource = orion_xor1_shared_resources, +}; + +static struct resource orion_xor10_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor10_data = { + .shared = &orion_xor1_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor10_channel = { + .name = MV_XOR_NAME, + .id = 2, + .num_resources = ARRAY_SIZE(orion_xor10_resources), + .resource = orion_xor10_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor10_data, + }, +}; + +static struct resource orion_xor11_resources[] = { + [0] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data orion_xor11_data = { + .shared = &orion_xor1_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device orion_xor11_channel = { + .name = MV_XOR_NAME, + .id = 3, + .num_resources = ARRAY_SIZE(orion_xor11_resources), + .resource = orion_xor11_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor11_data, + }, +}; + +void __init orion_xor1_init(unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1) +{ + orion_xor1_shared_resources[0].start = mapbase_low; + orion_xor1_shared_resources[0].end = mapbase_low + 0xff; + orion_xor1_shared_resources[1].start = mapbase_high; + orion_xor1_shared_resources[1].end = mapbase_high + 0xff; + + orion_xor10_resources[0].start = irq_0; + orion_xor10_resources[0].end = irq_0; + orion_xor11_resources[0].start = irq_1; + orion_xor11_resources[0].end = irq_1; + + platform_device_register(&orion_xor1_shared); + + orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel, + &orion_xor11_data, &orion_xor11_channel); +} + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data orion_ehci_data = { + .phy_version = EHCI_PHY_NA, +}; + +static u64 ehci_dmamask = DMA_BIT_MASK(32); + + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource orion_ehci_resources[2]; + +static struct platform_device orion_ehci = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &orion_ehci_data, + }, +}; + +void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + orion_ehci_data.dram = mbus_dram_info; + fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, + irq); + + platform_device_register(&orion_ehci); +} + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +static struct resource orion_ehci_1_resources[2]; + +static struct platform_device orion_ehci_1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &orion_ehci_data, + }, +}; + +void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + orion_ehci_data.dram = mbus_dram_info; + fill_resources(&orion_ehci_1, orion_ehci_1_resources, + mapbase, SZ_4K - 1, irq); + + platform_device_register(&orion_ehci_1); +} + +/***************************************************************************** + * EHCI2 + ****************************************************************************/ +static struct resource orion_ehci_2_resources[2]; + +static struct platform_device orion_ehci_2 = { + .name = "orion-ehci", + .id = 2, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &orion_ehci_data, + }, +}; + +void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + orion_ehci_data.dram = mbus_dram_info; + fill_resources(&orion_ehci_2, orion_ehci_2_resources, + mapbase, SZ_4K - 1, irq); + + platform_device_register(&orion_ehci_2); +} + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource orion_sata_resources[2] = { + { + .name = "sata base", + }, { + .name = "sata irq", + }, +}; + +static struct platform_device orion_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init orion_sata_init(struct mv_sata_platform_data *sata_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq) +{ + sata_data->dram = mbus_dram_info; + orion_sata.dev.platform_data = sata_data; + fill_resources(&orion_sata, orion_sata_resources, + mapbase, 0x5000 - 1, irq); + + platform_device_register(&orion_sata); +} + +/***************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) + ****************************************************************************/ +static struct resource orion_crypto_resources[] = { + { + .name = "regs", + }, { + .name = "crypto interrupt", + }, { + .name = "sram", + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device orion_crypto = { + .name = "mv_crypto", + .id = -1, +}; + +void __init orion_crypto_init(unsigned long mapbase, + unsigned long srambase, + unsigned long sram_size, + unsigned long irq) +{ + fill_resources(&orion_crypto, orion_crypto_resources, + mapbase, 0xffff, irq); + orion_crypto.num_resources = 3; + orion_crypto_resources[2].start = srambase; + orion_crypto_resources[2].end = srambase + sram_size - 1; + + platform_device_register(&orion_crypto); +} diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 078894bc3b9..5b4fffab1eb 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -321,62 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink); * polarity LEVEL mask * ****************************************************************************/ -static void gpio_irq_ack(struct irq_data *d) -{ - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type; - - type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - int pin = d->irq - ochip->secondary_irq_base; - - writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip)); - } -} - -static void gpio_irq_mask(struct irq_data *d) -{ - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type; - void __iomem *reg; - int pin; - - type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - reg = GPIO_EDGE_MASK(ochip); - else - reg = GPIO_LEVEL_MASK(ochip); - - pin = d->irq - ochip->secondary_irq_base; - - writel(readl(reg) & ~(1 << pin), reg); -} - -static void gpio_irq_unmask(struct irq_data *d) -{ - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); - int type; - void __iomem *reg; - int pin; - - type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - reg = GPIO_EDGE_MASK(ochip); - else - reg = GPIO_LEVEL_MASK(ochip); - - pin = d->irq - ochip->secondary_irq_base; - - writel(readl(reg) | (1 << pin), reg); -} static int gpio_irq_set_type(struct irq_data *d, u32 type) { - struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); + struct orion_gpio_chip *ochip = gc->private; int pin; u32 u; - pin = d->irq - ochip->secondary_irq_base; + pin = d->irq - gc->irq_base; u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); if (!u) { @@ -385,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) return -EINVAL; } - /* - * Set edge/level type. - */ - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - set_irq_handler(d->irq, handle_edge_irq); - } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - set_irq_handler(d->irq, handle_level_irq); - } else { - printk(KERN_ERR "failed to set irq=%d (type=%d)\n", - d->irq, type); + type &= IRQ_TYPE_SENSE_MASK; + if (type == IRQ_TYPE_NONE) return -EINVAL; - } + + /* Check if we need to change chip and handler */ + if (!(ct->type & type)) + if (irq_setup_alt_chip(d, type)) + return -EINVAL; /* * Configure interrupt polarity. @@ -428,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) return 0; } -struct irq_chip orion_gpio_irq_chip = { - .name = "orion_gpio_irq", - .irq_ack = gpio_irq_ack, - .irq_mask = gpio_irq_mask, - .irq_unmask = gpio_irq_unmask, - .irq_set_type = gpio_irq_set_type, -}; - void __init orion_gpio_init(int gpio_base, int ngpio, u32 base, int mask_offset, int secondary_irq_base) { struct orion_gpio_chip *ochip; - int i; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) return; @@ -474,21 +417,35 @@ void __init orion_gpio_init(int gpio_base, int ngpio, writel(0, GPIO_EDGE_MASK(ochip)); writel(0, GPIO_LEVEL_MASK(ochip)); - for (i = 0; i < ngpio; i++) { - unsigned int irq = secondary_irq_base + i; - - set_irq_chip(irq, &orion_gpio_irq_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_chip_data(irq, ochip); - irq_desc[irq].status |= IRQ_LEVEL; - set_irq_flags(irq, IRQF_VALID); - } + gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base, + ochip->base, handle_level_irq); + gc->private = ochip; + + ct = gc->chip_types; + ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; + ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_set_type = gpio_irq_set_type; + + ct++; + ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; + ct->regs.ack = GPIO_EDGE_CAUSE_OFF; + ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_set_type = gpio_irq_set_type; + ct->handler = handle_edge_irq; + + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); } void orion_gpio_irq_handler(int pinoff) { struct orion_gpio_chip *ochip; - u32 cause; + u32 cause, type; int i; ochip = orion_gpio_chip_find(pinoff); @@ -500,15 +457,14 @@ void orion_gpio_irq_handler(int pinoff) for (i = 0; i < ochip->chip.ngpio; i++) { int irq; - struct irq_desc *desc; irq = ochip->secondary_irq_base + i; if (!(cause & (1 << i))) continue; - desc = irq_desc + irq; - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + type = irqd_get_trigger_type(irq_get_irq_data(irq)); + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { /* Swap polarity (race with GPIO line) */ u32 polarity; @@ -516,7 +472,6 @@ void orion_gpio_irq_handler(int pinoff) polarity ^= 1 << i; writel(polarity, GPIO_IN_POL(ochip)); } - - desc_handle_irq(irq, desc); + generic_handle_irq(irq); } } diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h new file mode 100644 index 00000000000..a63c357e2ab --- /dev/null +++ b/arch/arm/plat-orion/include/plat/common.h @@ -0,0 +1,117 @@ +/* + * arch/arm/plat-orion/include/plat/common.h + * + * Marvell Orion SoC common setup code used by different mach-/common.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_COMMON_H +#include <linux/mv643xx_eth.h> + +struct dsa_platform_data; + +void __init orion_uart0_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_uart1_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_uart2_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_uart3_init(unsigned int membase, + resource_size_t mapbase, + unsigned int irq, + unsigned int uartclk); + +void __init orion_rtc_init(unsigned long mapbase, + unsigned long irq); + +void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq, + unsigned long irq_err, + int tclk); + +void __init orion_ge00_switch_init(struct dsa_platform_data *d, + int irq); +void __init orion_i2c_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m); + +void __init orion_i2c_1_init(unsigned long mapbase, + unsigned long irq, + unsigned long freq_m); + +void __init orion_spi_init(unsigned long mapbase, + unsigned long tclk); + +void __init orion_spi_1_init(unsigned long mapbase, + unsigned long tclk); + +void __init orion_wdt_init(unsigned long tclk); + +void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1); + +void __init orion_xor1_init(unsigned long mapbase_low, + unsigned long mapbase_high, + unsigned long irq_0, + unsigned long irq_1); + +void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); + +void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); + +void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); + +void __init orion_sata_init(struct mv_sata_platform_data *sata_data, + struct mbus_dram_target_info *mbus_dram_info, + unsigned long mapbase, + unsigned long irq); + +void __init orion_crypto_init(unsigned long mapbase, + unsigned long srambase, + unsigned long sram_size, + unsigned long irq); +#endif diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h index 5578b9803fc..3075b9fdde8 100644 --- a/arch/arm/plat-orion/include/plat/gpio.h +++ b/arch/arm/plat-orion/include/plat/gpio.h @@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio, /* * GPIO interrupt handling. */ -extern struct irq_chip orion_gpio_irq_chip; void orion_gpio_irq_handler(int irqoff); diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h new file mode 100644 index 00000000000..723adce99f4 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/mpp.h @@ -0,0 +1,34 @@ +/* + * arch/arm/plat-orion/include/plat/mpp.h + * + * Marvell Orion SoC MPP handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_MPP_H +#define __PLAT_MPP_H + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + +/* This is the generic MPP macro, without any variant information. + Each machine architecture is expected to extend this with further + bit fields indicating which MPP configurations are valid for a + specific variant. */ + +#define GENERIC_MPP(_num, _sel, _in, _out) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13)) + +#define MPP_INPUT_MASK GENERIC_MPP(0, 0x0, 1, 0) +#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1) + +void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, + unsigned int mpp_max, unsigned int dev_bus); + +#endif diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 7d0c7eb59f0..2d5b9c1ef38 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -14,52 +14,21 @@ #include <linux/io.h> #include <plat/irq.h> -static void orion_irq_mask(struct irq_data *d) -{ - void __iomem *maskaddr = irq_data_get_irq_chip_data(d); - u32 mask; - - mask = readl(maskaddr); - mask &= ~(1 << (d->irq & 31)); - writel(mask, maskaddr); -} - -static void orion_irq_unmask(struct irq_data *d) -{ - void __iomem *maskaddr = irq_data_get_irq_chip_data(d); - u32 mask; - - mask = readl(maskaddr); - mask |= 1 << (d->irq & 31); - writel(mask, maskaddr); -} - -static struct irq_chip orion_irq_chip = { - .name = "orion_irq", - .irq_mask = orion_irq_mask, - .irq_mask_ack = orion_irq_mask, - .irq_unmask = orion_irq_unmask, -}; - void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { - unsigned int i; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; /* * Mask all interrupts initially. */ writel(0, maskaddr); - /* - * Register IRQ sources. - */ - for (i = 0; i < 32; i++) { - unsigned int irq = irq_start + i; - - set_irq_chip(irq, &orion_irq_chip); - set_irq_chip_data(irq, maskaddr); - set_irq_handler(irq, handle_level_irq); - irq_desc[irq].status |= IRQ_LEVEL; - set_irq_flags(irq, IRQF_VALID); - } + gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); } diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c new file mode 100644 index 00000000000..91553432711 --- /dev/null +++ b/arch/arm/plat-orion/mpp.c @@ -0,0 +1,78 @@ +/* + * arch/arm/plat-orion/mpp.c + * + * MPP functions for Marvell orion SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <mach/hardware.h> +#include <plat/mpp.h> + +/* Address of the ith MPP control register */ +static __init unsigned long mpp_ctrl_addr(unsigned int i, + unsigned long dev_bus) +{ + return dev_bus + (i) * 4; +} + + +void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, + unsigned int mpp_max, unsigned int dev_bus) +{ + unsigned int mpp_nr_regs = (1 + mpp_max/8); + u32 mpp_ctrl[mpp_nr_regs]; + int i; + + printk(KERN_DEBUG "initial MPP regs:"); + for (i = 0; i < mpp_nr_regs; i++) { + mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); + + for ( ; *mpp_list; mpp_list++) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift, gpio_mode; + + if (num > mpp_max) { + printk(KERN_ERR "orion_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (variant_mask & !(*mpp_list & variant_mask)) { + printk(KERN_WARNING + "orion_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + gpio_mode = 0; + if (*mpp_list & MPP_INPUT_MASK) + gpio_mode |= GPIO_INPUT_OK; + if (*mpp_list & MPP_OUTPUT_MASK) + gpio_mode |= GPIO_OUTPUT_OK; + if (sel != 0) + gpio_mode = 0; + orion_gpio_set_valid(num, gpio_mode); + } + + printk(KERN_DEBUG " final MPP regs:"); + for (i = 0; i < mpp_nr_regs; i++) { + writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); +} diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 742b0323c57..69a61367e4b 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -81,24 +81,6 @@ static void __init setup_sched_clock(unsigned long tclk) } /* - * Clocksource handling. - */ -static cycle_t orion_clksrc_read(struct clocksource *cs) -{ - return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF); -} - -static struct clocksource orion_clksrc = { - .name = "orion_clocksource", - .rating = 300, - .read = orion_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - - -/* * Clockevent handling. */ static int @@ -247,7 +229,8 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); u = readl(timer_base + TIMER_CTRL_OFF); writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); - clocksource_register_hz(&orion_clksrc, tclk); + clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource", + tclk, 300, 32, clocksource_mmio_readl_down); /* * Setup clockevent timer (interrupt-driven). diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index e7de6ae2a1e..48ebb9479b6 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/slab.h> #include <mach/gpio.h> @@ -284,18 +284,18 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) } for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { - set_irq_chip(irq, &pxa_muxed_gpio_chip); - set_irq_handler(irq, handle_edge_irq); + irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, + handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* Install handler for GPIO>=2 edge detect interrupts */ - set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); + irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler); pxa_muxed_gpio_chip.irq_set_wake = fn; } #ifdef CONFIG_PM -static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) +static int pxa_gpio_suspend(void) { struct pxa_gpio_chip *c; int gpio; @@ -312,7 +312,7 @@ static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int pxa_gpio_resume(struct sys_device *dev) +static void pxa_gpio_resume(void) { struct pxa_gpio_chip *c; int gpio; @@ -326,22 +326,13 @@ static int pxa_gpio_resume(struct sys_device *dev) __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); } - return 0; } #else #define pxa_gpio_suspend NULL #define pxa_gpio_resume NULL #endif -struct sysdev_class pxa_gpio_sysclass = { - .name = "gpio", +struct syscore_ops pxa_gpio_syscore_ops = { .suspend = pxa_gpio_suspend, .resume = pxa_gpio_resume, }; - -static int __init pxa_gpio_init(void) -{ - return sysdev_class_register(&pxa_gpio_sysclass); -} - -core_initcall(pxa_gpio_init); diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 75f65647124..89e68e07b0a 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -434,7 +434,7 @@ typedef unsigned long mfp_cfg_t; * * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which * represents a range of MFP pins from "start" to "end", with the offset - * begining at "offset", to define a single pin, let "end" = -1. + * beginning at "offset", to define a single pin, let "end" = -1. * * use * diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index a9aa5ad3f4e..be12eadcce2 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -17,7 +17,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> #include <plat/mfp.h> diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index c2064c30871..0291bd6e236 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o -# Architecture dependant builds +# Architecture dependent builds obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_PM) += pm.o diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index eea75ff81d1..b3d3d027899 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c @@ -455,7 +455,7 @@ static int s3c_cpufreq_resume(struct cpufreq_policy *policy) /* whilst we will be called later on, we try and re-set the * cpu frequencies as soon as possible so that we do not end - * up resuming devices and then immediatley having to re-set + * up resuming devices and then immediately having to re-set * a number of settings once these devices have restarted. * * as a note, it is expected devices are not used until they diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 268f3ed0a10..73667994518 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/slab.h> #include <linux/string.h> +#include <linux/dma-mapping.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -233,6 +234,46 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) } } +/* USB High Speed 2.0 Device (Gadget) */ +static struct resource s3c_hsudc_resource[] = { + [0] = { + .start = S3C2416_PA_HSUDC, + .end = S3C2416_PA_HSUDC + S3C2416_SZ_HSUDC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USBD, + .end = IRQ_USBD, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_hsudc_dmamask = DMA_BIT_MASK(32); + +struct platform_device s3c_device_usb_hsudc = { + .name = "s3c-hsudc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_hsudc_resource), + .resource = s3c_hsudc_resource, + .dev = { + .dma_mask = &s3c_hsudc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) +{ + struct s3c24xx_hsudc_platdata *npd; + + npd = kmalloc(sizeof(*npd), GFP_KERNEL); + if (npd) { + memcpy(npd, pd, sizeof(*npd)); + s3c_device_usb_hsudc.dev.platform_data = npd; + } else { + printk(KERN_ERR "no memory for udc platform data\n"); + } +} + /* IIS */ static struct resource s3c_iis_resource[] = { diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 6ad274e7593..c10d10c56e2 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -22,7 +22,7 @@ #include <linux/sched.h> #include <linux/spinlock.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/slab.h> #include <linux/errno.h> #include <linux/io.h> @@ -557,7 +557,7 @@ s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) break; case S3C2410_DMALOAD_1LOADED_1RUNNING: - /* I belive in this case we do not have anything to do + /* I believe in this case we do not have anything to do * until the next buffer comes along, and we turn off the * reload */ return; @@ -1195,19 +1195,12 @@ int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *d EXPORT_SYMBOL(s3c2410_dma_getposition); -static inline struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev) -{ - return container_of(dev, struct s3c2410_dma_chan, dev); -} - -/* system device class */ +/* system core operations */ #ifdef CONFIG_PM -static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) +static void s3c2410_dma_suspend_chan(s3c2410_dma_chan *cp) { - struct s3c2410_dma_chan *cp = to_dma_chan(dev); - printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { @@ -1222,13 +1215,21 @@ static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) s3c2410_dma_dostop(cp); } +} + +static int s3c2410_dma_suspend(void) +{ + struct s3c2410_dma_chan *cp = s3c2410_chans; + int channel; + + for (channel = 0; channel < dma_channels; cp++, channel++) + s3c2410_dma_suspend_chan(cp); return 0; } -static int s3c2410_dma_resume(struct sys_device *dev) +static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp) { - struct s3c2410_dma_chan *cp = to_dma_chan(dev); unsigned int no = cp->number | DMACH_LOW_LEVEL; /* restore channel's hardware configuration */ @@ -1249,13 +1250,21 @@ static int s3c2410_dma_resume(struct sys_device *dev) return 0; } +static void s3c2410_dma_resume(void) +{ + struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1; + int channel; + + for (channel = dma_channels - 1; channel >= 0; cp++, channel--) + s3c2410_dma_resume_chan(cp); +} + #else #define s3c2410_dma_suspend NULL #define s3c2410_dma_resume NULL #endif /* CONFIG_PM */ -struct sysdev_class dma_sysclass = { - .name = "s3c24xx-dma", +struct syscore_ops dma_syscore_ops = { .suspend = s3c2410_dma_suspend, .resume = s3c2410_dma_resume, }; @@ -1269,39 +1278,14 @@ static void s3c2410_dma_cache_ctor(void *p) /* initialisation code */ -static int __init s3c24xx_dma_sysclass_init(void) +static int __init s3c24xx_dma_syscore_init(void) { - int ret = sysdev_class_register(&dma_sysclass); - - if (ret != 0) - printk(KERN_ERR "dma sysclass registration failed\n"); - - return ret; -} - -core_initcall(s3c24xx_dma_sysclass_init); - -static int __init s3c24xx_dma_sysdev_register(void) -{ - struct s3c2410_dma_chan *cp = s3c2410_chans; - int channel, ret; - - for (channel = 0; channel < dma_channels; cp++, channel++) { - cp->dev.cls = &dma_sysclass; - cp->dev.id = channel; - ret = sysdev_register(&cp->dev); - - if (ret) { - printk(KERN_ERR "error registering dev for dma %d\n", - channel); - return ret; - } - } + register_syscore_ops(&dma_syscore_ops); return 0; } -late_initcall(s3c24xx_dma_sysdev_register); +late_initcall(s3c24xx_dma_syscore_init); int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, unsigned int stride) diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h index 80457c6414a..f6388424250 100644 --- a/arch/arm/plat-s3c24xx/include/plat/udc.h +++ b/arch/arm/plat-s3c24xx/include/plat/udc.h @@ -37,4 +37,21 @@ struct s3c2410_udc_mach_info { extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *); +/** + * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller. + * @epnum: Number of endpoints to be instantiated by the controller driver. + * @gpio_init: Platform specific USB related GPIO initialization. + * @gpio_uninit: Platform specific USB releted GPIO uninitialzation. + * + * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget + * controllers. + */ +struct s3c24xx_hsudc_platdata { + unsigned int epnum; + void (*gpio_init)(void); + void (*gpio_uninit)(void); +}; + +extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd); + #endif /* __ASM_ARM_ARCH_UDC_H */ diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c index c3624d89863..0efb2e2848c 100644 --- a/arch/arm/plat-s3c24xx/irq-pm.c +++ b/arch/arm/plat-s3c24xx/irq-pm.c @@ -14,7 +14,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> #include <linux/irq.h> #include <plat/cpu.h> @@ -65,7 +64,7 @@ static unsigned long save_extint[3]; static unsigned long save_eintflt[4]; static unsigned long save_eintmask; -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) +int s3c24xx_irq_suspend(void) { unsigned int i; @@ -81,7 +80,7 @@ int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -int s3c24xx_irq_resume(struct sys_device *dev) +void s3c24xx_irq_resume(void) { unsigned int i; @@ -93,6 +92,4 @@ int s3c24xx_irq_resume(struct sys_device *dev) s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); __raw_writel(save_eintmask, S3C24XX_EINTMASK); - - return 0; } diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 4434cb56bd9..9aee7e1668b 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void) case IRQ_UART1: case IRQ_UART2: case IRQ_ADCPARENT: - set_irq_chip(irqno, &s3c_irq_level_chip); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_level_chip, + handle_level_irq); break; case IRQ_RESERVED6: @@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void) default: //irqdbf("registering irq %d (s3c irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_chip); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_chip, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } } /* setup the cascade irq handlers */ - set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); - set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); + irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); + irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); - set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); - set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); - set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); - set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); + irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); + irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); + irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); + irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); /* external interrupts */ for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { irqdbf("registering irq %d (ext int)\n", irqno); - set_irq_chip(irqno, &s3c_irq_eint0t4); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { irqdbf("registering irq %d (extended s3c irq)\n", irqno); - set_irq_chip(irqno, &s3c_irqext_chip); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irqext_chip, + handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } @@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void) for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_uart0); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_uart0, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_uart1); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_uart1, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_uart2); - set_irq_handler(irqno, handle_level_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_uart2, + handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { irqdbf("registering irq %d (s3c adc irq)\n", irqno); - set_irq_chip(irqno, &s3c_irq_adc); - set_irq_handler(irqno, handle_edge_irq); + irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq); set_irq_flags(irqno, IRQF_VALID); } diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 84922971658..6751bcf7b88 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -85,6 +85,11 @@ config S5P_DEV_CSIS1 help Compile in platform device definitions for MIPI-CSIS channel 1 +config S5P_DEV_USB_EHCI + bool + help + Compile in platform device definition for USB EHCI + config S5P_SETUP_MIPIPHY bool help diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 42afff7f60b..e234cc4d49a 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -33,4 +33,5 @@ obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o +obj-$(CONFIG_S5P_DEV_USB_EHCI) += dev-ehci.o obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index c3bfe9b13ac..5cf5e721e6c 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -39,7 +39,7 @@ static const char name_exynos4210[] = "EXYNOS4210"; static struct cpu_table cpu_ids[] __initdata = { { .idcode = 0x56440100, - .idmask = 0xffffff00, + .idmask = 0xfffff000, .map_io = s5p6440_map_io, .init_clocks = s5p6440_init_clocks, .init_uarts = s5p6440_init_uarts, @@ -47,7 +47,7 @@ static struct cpu_table cpu_ids[] __initdata = { .name = name_s5p6440, }, { .idcode = 0x36442000, - .idmask = 0xffffff00, + .idmask = 0xfffff000, .map_io = s5p6442_map_io, .init_clocks = s5p6442_init_clocks, .init_uarts = s5p6442_init_uarts, @@ -55,7 +55,7 @@ static struct cpu_table cpu_ids[] __initdata = { .name = name_s5p6442, }, { .idcode = 0x36450000, - .idmask = 0xffffff00, + .idmask = 0xfffff000, .map_io = s5p6450_map_io, .init_clocks = s5p6450_init_clocks, .init_uarts = s5p6450_init_uarts, @@ -79,7 +79,7 @@ static struct cpu_table cpu_ids[] __initdata = { .name = name_s5pv210, }, { .idcode = 0x43210000, - .idmask = 0xfffff000, + .idmask = 0xfffe0000, .map_io = exynos4_map_io, .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, diff --git a/arch/arm/plat-s5p/dev-ehci.c b/arch/arm/plat-s5p/dev-ehci.c new file mode 100644 index 00000000000..94080fff9e9 --- /dev/null +++ b/arch/arm/plat-s5p/dev-ehci.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/platform_device.h> +#include <mach/irqs.h> +#include <mach/map.h> +#include <plat/devs.h> +#include <plat/ehci.h> +#include <plat/usb-phy.h> + +/* USB EHCI Host Controller registration */ +static struct resource s5p_ehci_resource[] = { + [0] = { + .start = S5P_PA_EHCI, + .end = S5P_PA_EHCI + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB_HOST, + .end = IRQ_USB_HOST, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s5p_device_ehci_dmamask = 0xffffffffUL; + +struct platform_device s5p_device_ehci = { + .name = "s5p-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_ehci_resource), + .resource = s5p_ehci_resource, + .dev = { + .dma_mask = &s5p_device_ehci_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd) +{ + struct s5p_ehci_platdata *npd; + + npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata), + &s5p_device_ehci); + + if (!npd->phy_init) + npd->phy_init = s5p_usb_phy_init; + if (!npd->phy_exit) + npd->phy_exit = s5p_usb_phy_exit; +} diff --git a/arch/arm/plat-s5p/include/plat/ehci.h b/arch/arm/plat-s5p/include/plat/ehci.h new file mode 100644 index 00000000000..6ae6810c756 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/ehci.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PLAT_S5P_EHCI_H +#define __PLAT_S5P_EHCI_H + +struct s5p_ehci_platdata { + int (*phy_init)(struct platform_device *pdev, int type); + int (*phy_exit)(struct platform_device *pdev, int type); +}; + +extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd); + +#endif /* __PLAT_S5P_EHCI_H */ diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h index d973d39666a..a6c3d327ce7 100644 --- a/arch/arm/plat-s5p/include/plat/map-s5p.h +++ b/arch/arm/plat-s5p/include/plat/map-s5p.h @@ -39,7 +39,7 @@ #define S5P_VA_TWD S5P_VA_COREPERI(0x600) #define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000) -#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000) +#define S5P_VA_USB_HSPHY S3C_ADDR(0x02900000) #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) diff --git a/arch/arm/plat-s5p/include/plat/usb-phy.h b/arch/arm/plat-s5p/include/plat/usb-phy.h new file mode 100644 index 00000000000..6dd6bcfca3c --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/usb-phy.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd + * Author: Joonyoung Shim <jy0922.shim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PLAT_S5P_USB_PHY_H +#define __PLAT_S5P_USB_PHY_H + +enum s5p_usb_phy_type { + S5P_USB_PHY_DEVICE, + S5P_USB_PHY_HOST, +}; + +extern int s5p_usb_phy_init(struct platform_device *pdev, int type); +extern int s5p_usb_phy_exit(struct platform_device *pdev, int type); + +#endif /* __PLAT_S5P_REGS_USB_PHY_H */ diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index 225aa25405d..b5bb774985b 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c @@ -205,15 +205,14 @@ int __init s5p_init_irq_eint(void) int irq; for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) - set_irq_chip(irq, &s5p_irq_vic_eint); + irq_set_chip(irq, &s5p_irq_vic_eint); for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { - set_irq_chip(irq, &s5p_irq_eint); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } - set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); + irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); return 0; } diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index cd87d3256e0..135abda31c9 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -41,72 +41,11 @@ struct s5p_gpioint_bank { LIST_HEAD(banks); -static int s5p_gpioint_get_offset(struct irq_data *data) +static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type) { - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); - return data->irq - chip->irq_base; -} - -static void s5p_gpioint_ack(struct irq_data *data) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); - int group, offset, pend_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - pend_offset = REG_OFFSET(group); - - value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset); - value |= BIT(offset); - __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset); -} - -static void s5p_gpioint_mask(struct irq_data *data) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); - int group, offset, mask_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - mask_offset = REG_OFFSET(group); - - value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset); - value |= BIT(offset); - __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset); -} - -static void s5p_gpioint_unmask(struct irq_data *data) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); - int group, offset, mask_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - mask_offset = REG_OFFSET(group); - - value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset); - value &= ~BIT(offset); - __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset); -} - -static void s5p_gpioint_mask_ack(struct irq_data *data) -{ - s5p_gpioint_mask(data); - s5p_gpioint_ack(data); -} - -static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) -{ - struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); - int group, offset, con_offset; - unsigned int value; - - group = chip->group; - offset = s5p_gpioint_get_offset(data); - con_offset = REG_OFFSET(group); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = gc->chip_types; + unsigned int shift = (d->irq - gc->irq_base) << 2; switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -130,26 +69,15 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) return -EINVAL; } - value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset); - value &= ~(0x7 << (offset * 0x4)); - value |= (type << (offset * 0x4)); - __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset); - + gc->type_cache &= ~(0x7 << shift); + gc->type_cache |= type << shift; + writel(gc->type_cache, gc->reg_base + ct->regs.type); return 0; } -static struct irq_chip s5p_gpioint = { - .name = "s5p_gpioint", - .irq_ack = s5p_gpioint_ack, - .irq_mask = s5p_gpioint_mask, - .irq_mask_ack = s5p_gpioint_mask_ack, - .irq_unmask = s5p_gpioint_unmask, - .irq_set_type = s5p_gpioint_set_type, -}; - static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) { - struct s5p_gpioint_bank *bank = get_irq_data(irq); + struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); int group, pend_offset, mask_offset; unsigned int pend, mask; @@ -179,9 +107,10 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) { static int used_gpioint_groups = 0; - int irq, group = chip->group; - int i; + int group = chip->group; struct s5p_gpioint_bank *bank = NULL; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) return -ENOMEM; @@ -200,30 +129,39 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) if (!bank->chips) return -ENOMEM; - set_irq_chained_handler(bank->irq, s5p_gpioint_handler); - set_irq_data(bank->irq, bank); + irq_set_chained_handler(bank->irq, s5p_gpioint_handler); + irq_set_handler_data(bank->irq, bank); bank->handler = s5p_gpioint_handler; printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", bank->irq); } /* - * chained GPIO irq has been sucessfully registered, allocate new gpio + * chained GPIO irq has been successfully registered, allocate new gpio * int group and assign irq nubmers */ - chip->irq_base = S5P_GPIOINT_BASE + used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE; used_gpioint_groups++; bank->chips[group - bank->start] = chip; - for (i = 0; i < chip->chip.ngpio; i++) { - irq = chip->irq_base + i; - set_irq_chip(irq, &s5p_gpioint); - set_irq_data(irq, chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + + gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base, + (void __iomem *)GPIO_BASE(chip), + handle_level_irq); + if (!gc) + return -ENOMEM; + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->chip.irq_set_type = s5p_gpioint_set_type, + ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group); + ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group); + ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group); + irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio), + IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); return 0; } diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c index 5259ad458bc..327acb3a446 100644 --- a/arch/arm/plat-s5p/irq-pm.c +++ b/arch/arm/plat-s5p/irq-pm.c @@ -16,7 +16,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> #include <plat/cpu.h> #include <plat/irqs.h> @@ -77,17 +76,15 @@ static struct sleep_save eint_save[] = { SAVE_ITEM(S5P_EINT_MASK(3)), }; -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) +int s3c24xx_irq_suspend(void) { s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save)); return 0; } -int s3c24xx_irq_resume(struct sys_device *dev) +void s3c24xx_irq_resume(void) { s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save)); - - return 0; } diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c index 5560b12035d..a97c08957f4 100644 --- a/arch/arm/plat-s5p/irq.c +++ b/arch/arm/plat-s5p/irq.c @@ -64,11 +64,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic) vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); #endif - s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); - s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); - s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); - s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); - s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); + s3c_init_vic_timer_irq(5, IRQ_TIMER0); s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c index d592b6304b4..d15dc47b0e3 100644 --- a/arch/arm/plat-s5p/pm.c +++ b/arch/arm/plat-s5p/pm.c @@ -19,17 +19,6 @@ #define PFX "s5p pm: " -/* s3c_pm_check_resume_pin - * - * check to see if the pin is configured correctly for sleep mode, and - * make any necessary adjustments if it is not -*/ - -static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) -{ - /* nothing here yet */ -} - /* s3c_pm_configure_extint * * configure all external interrupt pins diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c index 8090403eec0..899a8cc011f 100644 --- a/arch/arm/plat-s5p/s5p-time.c +++ b/arch/arm/plat-s5p/s5p-time.c @@ -290,7 +290,7 @@ static void __init s5p_clockevent_init(void) setup_irq(irq_number, &s5p_clock_event_irq); } -static cycle_t s5p_timer_read(struct clocksource *cs) +static void __iomem *s5p_timer_reg(void) { unsigned long offset = 0; @@ -308,10 +308,17 @@ static cycle_t s5p_timer_read(struct clocksource *cs) default: printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); - return 0; + return NULL; } - return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset)); + return S3C_TIMERREG(offset); +} + +static cycle_t s5p_timer_read(struct clocksource *cs) +{ + void __iomem *reg = s5p_timer_reg(); + + return (cycle_t) (reg ? ~__raw_readl(reg) : 0); } /* @@ -325,53 +332,22 @@ static DEFINE_CLOCK_DATA(cd); unsigned long long notrace sched_clock(void) { - u32 cyc; - unsigned long offset = 0; - - switch (timer_source.source_id) { - case S5P_PWM0: - case S5P_PWM1: - case S5P_PWM2: - case S5P_PWM3: - offset = (timer_source.source_id * 0x0c) + 0x14; - break; - - case S5P_PWM4: - offset = 0x40; - break; + void __iomem *reg = s5p_timer_reg(); - default: - printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); + if (!reg) return 0; - } - cyc = ~__raw_readl(S3C_TIMERREG(offset)); - return cyc_to_sched_clock(&cd, cyc, (u32)~0); + return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); } static void notrace s5p_update_sched_clock(void) { - u32 cyc; - unsigned long offset = 0; + void __iomem *reg = s5p_timer_reg(); - switch (timer_source.source_id) { - case S5P_PWM0: - case S5P_PWM1: - case S5P_PWM2: - case S5P_PWM3: - offset = (timer_source.source_id * 0x0c) + 0x14; - break; - - case S5P_PWM4: - offset = 0x40; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); - } + if (!reg) + return; - cyc = ~__raw_readl(S3C_TIMERREG(offset)); - update_sched_clock(&cd, cyc, (u32)~0); + update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); } struct clocksource time_clocksource = { diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index be72100b81b..4d79519d19a 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -8,6 +8,7 @@ config PLAT_SAMSUNG bool depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P select NO_IOPORT + select GENERIC_IRQ_CHIP default y help Base platform code for all Samsung SoC based systems diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 9a82b887491..983c578b827 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -21,7 +21,7 @@ struct clk; * @set_parent: set the clock's parent, see clk_set_parent(). * * Group the common clock implementations together so that we - * don't have to keep setting the same fiels again. We leave + * don't have to keep setting the same fields again. We leave * enable in struct clk. * * Adding an extra layer of indirection into the process should diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index cedfff51c82..3aedac0034b 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -68,6 +68,12 @@ extern void s3c24xx_init_uartdevs(char *name, struct sys_timer; extern struct sys_timer s3c24xx_timer; +extern struct syscore_ops s3c2410_pm_syscore_ops; +extern struct syscore_ops s3c2412_pm_syscore_ops; +extern struct syscore_ops s3c2416_pm_syscore_ops; +extern struct syscore_ops s3c244x_pm_syscore_ops; +extern struct syscore_ops s3c64xx_irq_syscore_ops; + /* system device classes */ extern struct sysdev_class s3c2410_sysclass; diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index f0da6b70fba..39818d8da42 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -88,6 +88,7 @@ extern struct platform_device s3c64xx_device_onenand1; extern struct platform_device s5p_device_onenand; extern struct platform_device s3c_device_usbgadget; +extern struct platform_device s3c_device_usb_hsudc; extern struct platform_device s3c_device_usb_hsotg; extern struct platform_device s5pv210_device_ac97; @@ -142,6 +143,8 @@ extern struct platform_device s5p_device_fimc3; extern struct platform_device s5p_device_mipi_csis0; extern struct platform_device s5p_device_mipi_csis1; +extern struct platform_device s5p_device_ehci; + extern struct platform_device exynos4_device_sysmmu; /* s3c2440 specific devices */ diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 5603db0b79b..3ad8386599c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -114,7 +114,7 @@ extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, * of control per GPIO, generally in the form of: * 0000 = Input * 0001 = Output - * others = Special functions (dependant on bank) + * others = Special functions (dependent on bank) * * Note, since the code to deal with the case where there are two control * registers instead of one, we do not have a separate set of functions for diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 5e04fa6eda7..1762dcb4cb9 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -125,7 +125,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * * These values control the state of the weak pull-{up,down} resistors * available on most pins on the S3C series. Not all chips support both - * up or down settings, and it may be dependant on the chip that is being + * up or down settings, and it may be dependent on the chip that is being * used to whether the particular mode is available. */ #define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) @@ -138,7 +138,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * @pull: The configuration for the pull resistor. * * This function sets the state of the pull-{up,down} resistor for the - * specified pin. It will return 0 if successfull, or a negative error + * specified pin. It will return 0 if successful, or a negative error * code if the pin cannot support the requested pull setting. * * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. @@ -202,7 +202,7 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin); * @drvstr: The new value of the driver strength * * This function sets the driver strength value for the specified pin. - * It will return 0 if successfull, or a negative error code if the pin + * It will return 0 if successful, or a negative error code if the pin * cannot support the requested setting. */ extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index dac35d0a711..8cad4cf19c3 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -108,7 +108,7 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); * of control per GPIO, generally in the form of: * 0000 = Input * 0001 = Output - * others = Special functions (dependant on bank) + * others = Special functions (dependent on bank) * * Note, since the code to deal with the case where there are two control * registers instead of one, we do not have a separate set of function diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h index a90b53431b5..5b9c42fd32d 100644 --- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h @@ -10,4 +10,4 @@ * published by the Free Software Foundation. */ -extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); +extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq); diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 937cc2ace51..7fb6f6be8c8 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -103,14 +103,16 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); #ifdef CONFIG_PM extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); -extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); -extern int s3c24xx_irq_resume(struct sys_device *dev); +extern int s3c24xx_irq_suspend(void); +extern void s3c24xx_irq_resume(void); #else #define s3c_irqext_wake NULL #define s3c24xx_irq_suspend NULL #define s3c24xx_irq_resume NULL #endif +extern struct syscore_ops s3c24xx_irq_syscore_ops; + /* PM debug functions */ #ifdef CONFIG_SAMSUNG_PM_DEBUG diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index b0bdf16549d..058e09654fe 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -57,7 +57,7 @@ enum clk_types { * @cfg_gpio: Configure the GPIO for a specific card bit-width * @cfg_card: Configure the interface for a specific card and speed. This * is necessary the controllers and/or GPIO blocks require the - * changing of driver-strength and other controls dependant on + * changing of driver-strength and other controls dependent on * the card and speed of operation. * * Initialisation data specific to either the machine or the platform @@ -108,7 +108,7 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata; -/* Helper function availablity */ +/* Helper function availability */ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 7d6ed7263d5..ee48e12a1e7 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -18,8 +18,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ /* uart setup */ -static unsigned int fifo_mask; -static unsigned int fifo_max; +unsigned int fifo_mask; +unsigned int fifo_max; /* forward declerations */ diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 6790edfaca6..79d10fca909 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -36,7 +36,7 @@ static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, unsigned int count) { for (; count != 0; count--, tab++) { - if ((idcode & tab->idmask) == tab->idcode) + if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) return tab; } diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4e770355ccb..32582c0958e 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -27,60 +27,6 @@ /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. */ - -static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) -{ - struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -static void s3c_irq_uart_mask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(struct irq_data *data) -{ - void __iomem *regs = s3c_irq_uart_base(data); - unsigned int bit = s3c_irq_uart_bit(data->irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) { struct s3c_uart_irq *uirq = desc->irq_data.handler_data; @@ -97,35 +43,28 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) generic_handle_irq(base + 3); } -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .irq_mask = s3c_irq_uart_mask, - .irq_unmask = s3c_irq_uart_unmask, - .irq_mask_ack = s3c_irq_uart_maskack, - .irq_ack = s3c_irq_uart_ack, -}; - static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) { - struct irq_desc *desc = irq_to_desc(uirq->parent_irq); void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; /* mask all interrupts at the start. */ __raw_writel(0xf, reg_base + S3C64XX_UINTM); - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - desc->irq_data.handler_data = uirq; - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); + gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->regs.ack = S3C64XX_UINTP; + ct->regs.mask = S3C64XX_UINTM; + irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + + irq_set_handler_data(uirq->parent_irq, uirq); + irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); } /** diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index dd8692ae5c4..a607546ddbd 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -28,63 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) } /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(struct irq_data *data) +static void s3c_irq_timer_ack(struct irq_data *d) { - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 mask = (1 << 5) << (d->irq - gc->irq_base); - reg &= 0x1f; /* mask out pending interrupts */ - reg |= mask; - __raw_writel(reg, S3C64XX_TINT_CSTAT); + irq_reg_writel(mask | gc->mask_cache, gc->reg_base); } -static void s3c_irq_timer_ack(struct irq_data *data) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - u32 mask = (u32)data->chip_data; - - reg &= 0x1f; - reg |= mask << 5; - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .irq_mask = s3c_irq_timer_mask, - .irq_unmask = s3c_irq_timer_unmask, - .irq_ack = s3c_irq_timer_ack, -}; - /** * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ - * @parent_irq: The parent IRQ on the VIC for the timer. - * @timer_irq: The IRQ to be used for the timer. + * @num: Number of timers to initialize + * @timer_irq: Base IRQ number to be used for the timers. * * Register the necessary IRQ chaining and support for the timer IRQs * chained of the VIC. */ -void __init s3c_init_vic_timer_irq(unsigned int parent_irq, - unsigned int timer_irq) +void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq) { - struct irq_desc *desc = irq_to_desc(parent_irq); - - set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); + unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, + IRQ_TIMER3_VIC, IRQ_TIMER4_VIC }; + struct irq_chip_generic *s3c_tgc; + struct irq_chip_type *ct; + unsigned int i; - set_irq_chip(timer_irq, &s3c_irq_timer); - set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); - set_irq_handler(timer_irq, handle_level_irq); - set_irq_flags(timer_irq, IRQF_VALID); + s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, + S3C64XX_TINT_CSTAT, handle_level_irq); + ct = s3c_tgc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_ack = s3c_irq_timer_ack; + irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); + /* Clear the upper bits of the mask_cache*/ + s3c_tgc->mask_cache &= 0x1f; - desc->irq_data.handler_data = (void *)timer_irq; + for (i = 0; i < num; i++, timer_irq++) { + irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer); + irq_set_handler_data(pirq[i], (void *)timer_irq); + } } diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c index e4baf76f374..6b733fafe7c 100644 --- a/arch/arm/plat-samsung/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c @@ -164,7 +164,6 @@ static inline int in_region(void *ptr, int size, void *what, size_t whatsz) */ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) { - void *save_at = phys_to_virt(s3c_sleep_save_phys); unsigned long addr; unsigned long left; void *stkpage; @@ -192,11 +191,6 @@ static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) goto skip_check; } - if (in_region(ptr, left, save_at, 32*4 )) { - S3C_PMDBG("skipping %08lx, has save block in\n", addr); - goto skip_check; - } - /* calculate and check the checksum */ calc = crc32_le(~0, ptr, left); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index d5b58d31903..5c0a440d6e1 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -214,8 +214,9 @@ void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) * * print any IRQs asserted at resume time (ie, we woke from) */ -static void s3c_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) +static void __maybe_unused s3c_pm_show_resume_irqs(int start, + unsigned long which, + unsigned long mask) { int i; diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c index b4ff8d74ac4..f85638c6f5a 100644 --- a/arch/arm/plat-samsung/s3c-pl330.c +++ b/arch/arm/plat-samsung/s3c-pl330.c @@ -68,7 +68,7 @@ struct s3c_pl330_xfer { * @req: Two requests to communicate with the PL330 engine. * @callback_fn: Callback function to the client. * @rqcfg: Channel configuration for the xfers. - * @xfer_head: Pointer to the xfer to be next excecuted. + * @xfer_head: Pointer to the xfer to be next executed. * @dmac: Pointer to the DMAC that manages this channel, NULL if the * channel is available to be acquired. * @client: Client of this channel. NULL if the diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c index 2e09b6ad84c..dc814037297 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/plat-samsung/wakeup-mask.c @@ -22,7 +22,7 @@ void samsung_sync_wakemask(void __iomem *reg, struct samsung_wakeup_mask *mask, int nr_mask) { - struct irq_desc *desc; + struct irq_data *data; u32 val; val = __raw_readl(reg); @@ -33,10 +33,10 @@ void samsung_sync_wakemask(void __iomem *reg, continue; } - desc = irq_to_desc(mask->irq); + data = irq_get_irq_data(mask->irq); - /* bit of a liberty to read this directly from irq_desc. */ - if (desc->wake_depth > 0) + /* bit of a liberty to read this directly from irq_data. */ + if (irqd_is_wakeup_set(data)) val &= ~mask->bit; else val |= mask->bit; diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c index bdbd7ec9cb6..6fa474cb398 100644 --- a/arch/arm/plat-spear/clock.c +++ b/arch/arm/plat-spear/clock.c @@ -903,6 +903,11 @@ void recalc_root_clocks(void) spin_unlock_irqrestore(&clocks_lock, flags); } +void __init clk_init(void) +{ + recalc_root_clocks(); +} + #ifdef CONFIG_DEBUG_FS /* * debugfs support to trace clock tree hierarchy and attributes diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h index 2ae6606930a..0062bafef12 100644 --- a/arch/arm/plat-spear/include/plat/clock.h +++ b/arch/arm/plat-spear/include/plat/clock.h @@ -89,7 +89,7 @@ struct rate_config { * @sibling: node for list of clocks having same parents * @private_data: clock specific private data * @node: list to maintain clocks linearly - * @cl: clocklook up assoicated with this clock + * @cl: clocklook up associated with this clock * @dent: object for debugfs */ struct clk { @@ -224,6 +224,7 @@ struct clcd_rate_tbl { }; /* platform specific clock functions */ +void __init clk_init(void); void clk_register(struct clk_lookup *cl); void recalc_root_clocks(void); diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c index 78189035e7f..961fb726124 100644 --- a/arch/arm/plat-spear/shirq.c +++ b/arch/arm/plat-spear/shirq.c @@ -68,7 +68,7 @@ static struct irq_chip shirq_chip = { static void shirq_handler(unsigned irq, struct irq_desc *desc) { u32 i, val, mask; - struct spear_shirq *shirq = get_irq_data(irq); + struct spear_shirq *shirq = irq_get_handler_data(irq); desc->irq_data.chip->irq_ack(&desc->irq_data); while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & @@ -105,14 +105,14 @@ int spear_shirq_register(struct spear_shirq *shirq) if (!shirq->dev_count) return -EINVAL; - set_irq_chained_handler(shirq->irq, shirq_handler); + irq_set_chained_handler(shirq->irq, shirq_handler); for (i = 0; i < shirq->dev_count; i++) { - set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); - set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); + irq_set_chip_and_handler(shirq->dev_config[i].virq, + &shirq_chip, handle_simple_irq); set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); - set_irq_chip_data(shirq->dev_config[i].virq, shirq); + irq_set_chip_data(shirq->dev_config[i].virq, shirq); } - set_irq_data(shirq->irq, shirq); + irq_set_handler_data(shirq->irq, shirq); return 0; } diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index dbb6e4fff79..0c77e429867 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -70,19 +70,6 @@ static void clockevent_set_mode(enum clock_event_mode mode, static int clockevent_next_event(unsigned long evt, struct clock_event_device *clk_event_dev); -static cycle_t clocksource_read_cycles(struct clocksource *cs) -{ - return (cycle_t) readw(gpt_base + COUNT(CLKSRC)); -} - -static struct clocksource clksrc = { - .name = "tmr1", - .rating = 200, /* its a pretty decent clock */ - .read = clocksource_read_cycles, - .mask = 0xFFFF, /* 16 bits */ - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static void spear_clocksource_init(void) { u32 tick_rate; @@ -103,7 +90,8 @@ static void spear_clocksource_init(void) writew(val, gpt_base + CR(CLKSRC)); /* register the clocksource */ - clocksource_register_hz(&clksrc, tick_rate); + clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, + 200, 16, clocksource_mmio_readw_up); } static struct clock_event_device clkevt = { diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig deleted file mode 100644 index 2cf37c35951..00000000000 --- a/arch/arm/plat-stmp3xxx/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -if ARCH_STMP3XXX - -menu "Freescale STMP3xxx implementations" - -choice - prompt "Select STMP3xxx chip family" - -config ARCH_STMP37XX - bool "Freescale SMTP37xx" - select CPU_ARM926T - ---help--- - STMP37xx refers to 3700 through 3769 chips - -config ARCH_STMP378X - bool "Freescale STMP378x" - select CPU_ARM926T - ---help--- - STMP378x refers to 3780 through 3789 chips - -endchoice - -choice - prompt "Select STMP3xxx board type" - -config MACH_STMP37XX - depends on ARCH_STMP37XX - bool "Freescale STMP37xx development board" - -config MACH_STMP378X - depends on ARCH_STMP378X - bool "Freescale STMP378x development board" - -endchoice - -endmenu - -endif diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile deleted file mode 100644 index 31dd518f37a..00000000000 --- a/arch/arm/plat-stmp3xxx/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the linux kernel. -# -# Object file lists. -obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c deleted file mode 100644 index 2e712e17ce7..00000000000 --- a/arch/arm/plat-stmp3xxx/clock.c +++ /dev/null @@ -1,1134 +0,0 @@ -/* - * Clock manipulation routines for Freescale STMP37XX/STMP378X - * - * Author: Vitaly Wool <vital@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define DEBUG -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <asm/mach-types.h> -#include <mach/platform.h> -#include <mach/regs-clkctrl.h> - -#include "clock.h" - -static DEFINE_SPINLOCK(clocks_lock); - -static struct clk osc_24M; -static struct clk pll_clk; -static struct clk cpu_clk; -static struct clk hclk; - -static int propagate_rate(struct clk *); - -static inline int clk_is_busy(struct clk *clk) -{ - return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit); -} - -static inline int clk_good(struct clk *clk) -{ - return clk && !IS_ERR(clk) && clk->ops; -} - -static int std_clk_enable(struct clk *clk) -{ - if (clk->enable_reg) { - u32 clk_reg = __raw_readl(clk->enable_reg); - if (clk->enable_negate) - clk_reg &= ~(1 << clk->enable_shift); - else - clk_reg |= (1 << clk->enable_shift); - __raw_writel(clk_reg, clk->enable_reg); - if (clk->enable_wait) - udelay(clk->enable_wait); - return 0; - } else - return -EINVAL; -} - -static int std_clk_disable(struct clk *clk) -{ - if (clk->enable_reg) { - u32 clk_reg = __raw_readl(clk->enable_reg); - if (clk->enable_negate) - clk_reg |= (1 << clk->enable_shift); - else - clk_reg &= ~(1 << clk->enable_shift); - __raw_writel(clk_reg, clk->enable_reg); - return 0; - } else - return -EINVAL; -} - -static int io_set_rate(struct clk *clk, u32 rate) -{ - u32 reg_frac, clkctrl_frac; - int i, ret = 0, mask = 0x1f; - - clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate; - - if (clkctrl_frac < 18 || clkctrl_frac > 35) { - ret = -EINVAL; - goto out; - } - - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_shift); - __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift), - clk->scale_reg); - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; - } -out: - return ret; -} - -static long io_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - int mask = 0x1f; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - clk->rate = rate; - - return rate; -} - -static long per_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - long div; - const int mask = 0xff; - - if (clk->enable_reg && - !(__raw_readl(clk->enable_reg) & clk->enable_shift)) - clk->rate = 0; - else { - div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - if (div) - rate /= div; - clk->rate = rate; - } - - return clk->rate; -} - -static int per_set_rate(struct clk *clk, u32 rate) -{ - int ret = -EINVAL; - int div = (clk->parent->rate + rate - 1) / rate; - u32 reg_frac; - const int mask = 0xff; - int try = 10; - int i = -1; - - if (div == 0 || div > mask) - goto out; - - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_shift); - - while (try--) { - __raw_writel(reg_frac | (div << clk->scale_shift), - clk->scale_reg); - - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - } - if (i) - break; - } - - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; - -out: - if (ret != 0) - printk(KERN_ERR "%s: error %d\n", __func__, ret); - return ret; -} - -static long lcdif_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - long div; - const int mask = 0xff; - - div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - if (div) { - rate /= div; - div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) & - BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC; - rate /= div; - } - clk->rate = rate; - - return rate; -} - -static int lcdif_set_rate(struct clk *clk, u32 rate) -{ - int ret = 0; - /* - * On 3700, we can get most timings exact by modifying ref_pix - * and the divider, but keeping the phase timings at 1 (2 - * phases per cycle). - * - * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz, - * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns. - * - * ns_cycle >= 2*18e3/(18*480) = 25/6 - * ns_cycle <= 2*35e3/(18*480) = 875/108 - * - * Multiply the ns_cycle by 'div' to lengthen it until it fits the - * bounds. This is the divider we'll use after ref_pix. - * - * 6 * ns_cycle >= 25 * div - * 108 * ns_cycle <= 875 * div - */ - u32 ns_cycle = 1000000 / rate; - u32 div, reg_val; - u32 lowest_result = (u32) -1; - u32 lowest_div = 0, lowest_fracdiv = 0; - - for (div = 1; div < 256; ++div) { - u32 fracdiv; - u32 ps_result; - int lower_bound = 6 * ns_cycle >= 25 * div; - int upper_bound = 108 * ns_cycle <= 875 * div; - if (!lower_bound) - break; - if (!upper_bound) - continue; - /* - * Found a matching div. Calculate fractional divider needed, - * rounded up. - */ - fracdiv = ((clk->parent->rate / 1000 * 18 / 2) * - ns_cycle + 1000 * div - 1) / - (1000 * div); - if (fracdiv < 18 || fracdiv > 35) { - ret = -EINVAL; - goto out; - } - /* Calculate the actual cycle time this results in */ - ps_result = 6250 * div * fracdiv / 27; - - /* Use the fastest result that doesn't break ns_cycle */ - if (ps_result <= lowest_result) { - lowest_result = ps_result; - lowest_div = div; - lowest_fracdiv = fracdiv; - } - } - - if (div >= 256 || lowest_result == (u32) -1) { - ret = -EINVAL; - goto out; - } - pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz " - "PIXCLK=%uMHz cycle=%u.%03uns\n", - lowest_fracdiv, lowest_div, - 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div, - lowest_result / 1000, lowest_result % 1000); - - /* Program ref_pix phase fractional divider */ - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC; - reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC); - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - - /* Ungate PFD */ - stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX, - REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - - /* Program pix divider */ - reg_val = __raw_readl(clk->scale_reg); - reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); - reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV); - __raw_writel(reg_val, clk->scale_reg); - - /* Wait for divider update */ - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - ret = -ETIMEDOUT; - goto out; - } - } - - /* Switch to ref_pix source */ - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); - reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX; - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); - -out: - return ret; -} - - -static int cpu_set_rate(struct clk *clk, u32 rate) -{ - u32 reg_val; - - if (rate < 24000) - return -EINVAL; - else if (rate == 24000) { - /* switch to the 24M source */ - clk_set_parent(clk, &osc_24M); - } else { - int i; - u32 clkctrl_cpu = 1; - u32 c = clkctrl_cpu; - u32 clkctrl_frac = 1; - u32 val; - for ( ; c < 0x40; c++) { - u32 f = (pll_clk.rate*18/c + rate/2) / rate; - int s1, s2; - - if (f < 18 || f > 35) - continue; - s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate; - s2 = pll_clk.rate*18/c/f - rate; - pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2); - if (abs(s1) > abs(s2)) { - clkctrl_cpu = c; - clkctrl_frac = f; - } - if (s2 == 0) - break; - }; - pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, - clkctrl_cpu, clkctrl_frac); - if (c == 0x40) { - int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - - rate; - if (abs(d) > 100 || - clkctrl_frac < 18 || clkctrl_frac > 35) - return -EINVAL; - } - - /* 4.6.2 */ - val = __raw_readl(clk->scale_reg); - val &= ~(0x3f << clk->scale_shift); - val |= clkctrl_frac; - clk_set_parent(clk, &osc_24M); - udelay(10); - __raw_writel(val, clk->scale_reg); - /* ungate */ - __raw_writel(1<<7, clk->scale_reg + 8); - /* write clkctrl_cpu */ - clk->saved_div = clkctrl_cpu; - - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - reg_val &= ~0x3F; - reg_val |= clkctrl_cpu; - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; - } - clk_set_parent(clk, &pll_clk); - clk->saved_div = 0; - udelay(10); - } - return 0; -} - -static long cpu_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f; - rate = ((rate + 9) / 10) * 10; - clk->rate = rate; - - return rate; -} - -static long cpu_round_rate(struct clk *clk, u32 rate) -{ - unsigned long r = 0; - - if (rate <= 24000) - r = 24000; - else { - u32 clkctrl_cpu = 1; - u32 clkctrl_frac; - do { - clkctrl_frac = - (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate; - if (clkctrl_frac > 35) - continue; - if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 == - rate / 10) - break; - } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate); - if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate) - clkctrl_cpu--; - pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, - clkctrl_cpu, clkctrl_frac); - if (clkctrl_frac < 18) - clkctrl_frac = 18; - if (clkctrl_frac > 35) - clkctrl_frac = 35; - - r = pll_clk.rate * 18; - r /= clkctrl_frac; - r /= clkctrl_cpu; - r = 10 * ((r + 9) / 10); - } - return r; -} - -static long emi_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f; - clk->rate = rate; - - return rate; -} - -static int clkseq_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -EINVAL; - int shift = 8; - - /* bypass? */ - if (parent == &osc_24M) - shift = 4; - - if (clk->bypass_reg) { -#ifdef CONFIG_ARCH_STMP378X - u32 hbus_val, cpu_val; - - if (clk == &cpu_clk && shift == 4) { - hbus_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_CPU); - - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - cpu_val |= 1; - - if (machine_is_stmp378x()) { - __raw_writel(hbus_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - hclk.rate = 0; - } - } else if (clk == &cpu_clk && shift == 8) { - hbus_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_CPU); - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - hbus_val |= 2; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - if (clk->saved_div) - cpu_val |= clk->saved_div; - else - cpu_val |= 2; - - if (machine_is_stmp378x()) { - __raw_writel(hbus_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - hclk.rate = 0; - } - } -#endif - __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift); - - ret = 0; - } - - return ret; -} - -static int hbus_set_rate(struct clk *clk, u32 rate) -{ - u8 div = 0; - int is_frac = 0; - u32 clkctrl_hbus; - struct clk *parent = clk->parent; - - pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, - parent->rate); - - if (rate > parent->rate) - return -EINVAL; - - if (((parent->rate + rate/2) / rate) * rate != parent->rate && - parent->rate / rate < 32) { - pr_debug("%s: switching to fractional mode\n", __func__); - is_frac = 1; - } - - if (is_frac) - div = (32 * rate + parent->rate / 2) / parent->rate; - else - div = (parent->rate + rate - 1) / rate; - pr_debug("%s: div calculated is %d\n", __func__, div); - if (!div || div > 0x1f) - return -EINVAL; - - clk_set_parent(&cpu_clk, &osc_24M); - udelay(10); - clkctrl_hbus = __raw_readl(clk->scale_reg); - clkctrl_hbus &= ~0x3f; - clkctrl_hbus |= div; - clkctrl_hbus |= (is_frac << 5); - - __raw_writel(clkctrl_hbus, clk->scale_reg); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; - } - } - clk_set_parent(&cpu_clk, &pll_clk); - __raw_writel(clkctrl_hbus, clk->scale_reg); - udelay(10); - return 0; -} - -static long hbus_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - - if (__raw_readl(clk->scale_reg) & 0x20) { - rate *= __raw_readl(clk->scale_reg) & 0x1f; - rate /= 32; - } else - rate /= __raw_readl(clk->scale_reg) & 0x1f; - clk->rate = rate; - - return rate; -} - -static int xbus_set_rate(struct clk *clk, u32 rate) -{ - u16 div = 0; - u32 clkctrl_xbus; - - pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, - clk->parent->rate); - - div = (clk->parent->rate + rate - 1) / rate; - pr_debug("%s: div calculated is %d\n", __func__, div); - if (!div || div > 0x3ff) - return -EINVAL; - - clkctrl_xbus = __raw_readl(clk->scale_reg); - clkctrl_xbus &= ~0x3ff; - clkctrl_xbus |= div; - __raw_writel(clkctrl_xbus, clk->scale_reg); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up xbus divisor\n"); - return -ETIMEDOUT; - } - } - return 0; -} - -static long xbus_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - - rate /= __raw_readl(clk->scale_reg) & 0x3ff; - clk->rate = rate; - - return rate; -} - - -/* Clock ops */ - -static struct clk_ops std_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = per_get_rate, - .set_rate = per_set_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops min_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, -}; - -static struct clk_ops cpu_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = cpu_get_rate, - .set_rate = cpu_set_rate, - .round_rate = cpu_round_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops io_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = io_get_rate, - .set_rate = io_set_rate, -}; - -static struct clk_ops hbus_ops = { - .get_rate = hbus_get_rate, - .set_rate = hbus_set_rate, -}; - -static struct clk_ops xbus_ops = { - .get_rate = xbus_get_rate, - .set_rate = xbus_set_rate, -}; - -static struct clk_ops lcdif_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = lcdif_get_rate, - .set_rate = lcdif_set_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops emi_ops = { - .get_rate = emi_get_rate, -}; - -/* List of on-chip clocks */ - -static struct clk osc_24M = { - .flags = FIXED_RATE | ENABLED, - .rate = 24000, -}; - -static struct clk pll_clk = { - .parent = &osc_24M, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, - .enable_shift = 16, - .enable_wait = 10, - .flags = FIXED_RATE | ENABLED, - .rate = 480000, - .ops = &min_ops, -}; - -static struct clk cpu_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 0, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 7, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU, - .busy_bit = 28, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &cpu_ops, -}; - -static struct clk io_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .enable_shift = 31, - .enable_negate = 1, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 24, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &io_ops, -}; - -static struct clk hclk = { - .parent = &cpu_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 7, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, - .busy_bit = 29, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &hbus_ops, -}; - -static struct clk xclk = { - .parent = &osc_24M, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, - .busy_bit = 31, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &xbus_ops, -}; - -static struct clk uart_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 31, - .enable_negate = 1, - .flags = ENABLED, - .ops = &min_ops, -}; - -static struct clk audio_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 30, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk pwm_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 29, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk dri_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 28, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk digctl_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 27, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk timer_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 26, - .enable_negate = 1, - .flags = ENABLED, - .ops = &min_ops, -}; - -static struct clk lcdif_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 1, - .flags = NEEDS_SET_PARENT, - .ops = &lcdif_ops, -}; - -static struct clk ssp_clk = { - .parent = &io_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .enable_shift = 31, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 5, - .enable_negate = 1, - .flags = NEEDS_SET_PARENT, - .ops = &std_ops, -}; - -static struct clk gpmi_clk = { - .parent = &io_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 4, - .flags = NEEDS_SET_PARENT, - .ops = &std_ops, -}; - -static struct clk spdif_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF, - .enable_shift = 31, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk emi_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, - .enable_shift = 31, - .enable_negate = 1, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 8, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, - .busy_bit = 28, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 6, - .flags = ENABLED, - .ops = &emi_ops, -}; - -static struct clk ir_clk = { - .parent = &io_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 3, - .ops = &min_ops, -}; - -static struct clk saif_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 0, - .ops = &std_ops, -}; - -static struct clk usb_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, - .enable_shift = 18, - .enable_negate = 1, - .ops = &min_ops, -}; - -/* list of all the clocks */ -static struct clk_lookup onchip_clks[] = { - { - .con_id = "osc_24M", - .clk = &osc_24M, - }, { - .con_id = "pll", - .clk = &pll_clk, - }, { - .con_id = "cpu", - .clk = &cpu_clk, - }, { - .con_id = "hclk", - .clk = &hclk, - }, { - .con_id = "xclk", - .clk = &xclk, - }, { - .con_id = "io", - .clk = &io_clk, - }, { - .con_id = "uart", - .clk = &uart_clk, - }, { - .con_id = "audio", - .clk = &audio_clk, - }, { - .con_id = "pwm", - .clk = &pwm_clk, - }, { - .con_id = "dri", - .clk = &dri_clk, - }, { - .con_id = "digctl", - .clk = &digctl_clk, - }, { - .con_id = "timer", - .clk = &timer_clk, - }, { - .con_id = "lcdif", - .clk = &lcdif_clk, - }, { - .con_id = "ssp", - .clk = &ssp_clk, - }, { - .con_id = "gpmi", - .clk = &gpmi_clk, - }, { - .con_id = "spdif", - .clk = &spdif_clk, - }, { - .con_id = "emi", - .clk = &emi_clk, - }, { - .con_id = "ir", - .clk = &ir_clk, - }, { - .con_id = "saif", - .clk = &saif_clk, - }, { - .con_id = "usb", - .clk = &usb_clk, - }, -}; - -static int __init propagate_rate(struct clk *clk) -{ - struct clk_lookup *cl; - - for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); - cl++) { - if (unlikely(!clk_good(cl->clk))) - continue; - if (cl->clk->parent == clk && cl->clk->ops->get_rate) { - cl->clk->ops->get_rate(cl->clk); - if (cl->clk->flags & RATE_PROPAGATES) - propagate_rate(cl->clk); - } - } - - return 0; -} - -/* Exported API */ -unsigned long clk_get_rate(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return 0; - - if (clk->rate != 0) - return clk->rate; - - if (clk->ops->get_rate != NULL) - return clk->ops->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(!clk_good(clk))) - return 0; - - if (clk->ops->round_rate) - return clk->ops->round_rate(clk, rate); - - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -static inline int close_enough(long rate1, long rate2) -{ - return rate1 && !((rate2 - rate1) * 1000 / rate1); -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (unlikely(!clk_good(clk))) - goto out; - - if (clk->flags & FIXED_RATE || !clk->ops->set_rate) - goto out; - - else if (!close_enough(clk->rate, rate)) { - ret = clk->ops->set_rate(clk, rate); - if (ret < 0) - goto out; - clk->rate = rate; - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); - } else - ret = 0; - -out: - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_enable(struct clk *clk) -{ - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - return -EINVAL; - - if (clk->parent) - clk_enable(clk->parent); - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - clk->usage++; - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void local_clk_disable(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return; - - if (clk->usage == 0 && clk->ops->disable) - clk->ops->disable(clk); - - if (clk->parent) - local_clk_disable(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - return; - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - if ((--clk->usage) == 0 && clk->ops->disable) - clk->ops->disable(clk); - - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - if (clk->parent) - clk_disable(clk->parent); -} -EXPORT_SYMBOL(clk_disable); - -/* Some additional API */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -ENODEV; - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - goto out; - - if (!clk->ops->set_parent) - goto out; - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - ret = clk->ops->set_parent(clk, parent); - if (!ret) { - /* disable if usage count is 0 */ - local_clk_disable(parent); - - parent->usage += clk->usage; - clk->parent->usage -= clk->usage; - - /* disable if new usage count is 0 */ - local_clk_disable(clk->parent); - - clk->parent = parent; - } - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - -out: - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return NULL; - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static int __init clk_init(void) -{ - struct clk_lookup *cl; - struct clk_ops *ops; - - spin_lock_init(&clocks_lock); - - for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); - cl++) { - if (cl->clk->flags & ENABLED) - clk_enable(cl->clk); - else - local_clk_disable(cl->clk); - - ops = cl->clk->ops; - - if ((cl->clk->flags & NEEDS_INITIALIZATION) && - ops && ops->set_rate) - ops->set_rate(cl->clk, cl->clk->rate); - - if (cl->clk->flags & FIXED_RATE) { - if (cl->clk->flags & RATE_PROPAGATES) - propagate_rate(cl->clk); - } else { - if (ops && ops->get_rate) - ops->get_rate(cl->clk); - } - - if (cl->clk->flags & NEEDS_SET_PARENT) { - if (ops && ops->set_parent) - ops->set_parent(cl->clk, cl->clk->parent); - } - } - clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); - return 0; -} - -arch_initcall(clk_init); diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h deleted file mode 100644 index a6611e1a351..00000000000 --- a/arch/arm/plat-stmp3xxx/clock.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Clock control driver for Freescale STMP37XX/STMP378X - internal header file - * - * Author: Vitaly Wool <vital@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__ -#define __ARCH_ARM_STMX3XXX_CLOCK_H__ - -#ifndef __ASSEMBLER__ - -struct clk_ops { - int (*enable) (struct clk *); - int (*disable) (struct clk *); - long (*get_rate) (struct clk *); - long (*round_rate) (struct clk *, u32); - int (*set_rate) (struct clk *, u32); - int (*set_parent) (struct clk *, struct clk *); -}; - -struct clk { - struct clk *parent; - u32 rate; - u32 flags; - u8 scale_shift; - u8 enable_shift; - u8 bypass_shift; - u8 busy_bit; - s8 usage; - int enable_wait; - int enable_negate; - u32 saved_div; - void __iomem *enable_reg; - void __iomem *scale_reg; - void __iomem *bypass_reg; - void __iomem *busy_reg; - struct clk_ops *ops; -}; - -#endif /* __ASSEMBLER__ */ - -/* Flags */ -#define RATE_PROPAGATES (1<<0) -#define NEEDS_INITIALIZATION (1<<1) -#define PARENT_SET_RATE (1<<2) -#define FIXED_RATE (1<<3) -#define ENABLED (1<<4) -#define NEEDS_SET_PARENT (1<<5) - -#endif diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c deleted file mode 100644 index 37b8a09148a..00000000000 --- a/arch/arm/plat-stmp3xxx/core.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X core routines - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <mach/stmp3xxx.h> -#include <mach/platform.h> -#include <mach/dma.h> -#include <mach/regs-clkctrl.h> - -static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) -{ - u32 c; - int timeout; - - /* the process of software reset of IP block is done - in several steps: - - - clear SFTRST and wait for block is enabled; - - clear clock gating (CLKGATE bit); - - set the SFTRST again and wait for block is in reset; - - clear SFTRST and wait for reset completion. - */ - c = __raw_readl(hwreg); - c &= ~(1<<31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when enabling\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - - if (!just_enable) { - c = __raw_readl(hwreg); - c |= (1<<31); /* now again set SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* poll until CLKGATE set */ - if (__raw_readl(hwreg) & (1<<30)) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when resetting\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when enabling " - "after reset\n", __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - } - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<30)) == 0) - break; - - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when unclockgating\n", - __func__, hwreg); - return -ETIME; - } - - return 0; -} - -int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) -{ - int try = 10; - int r; - - while (try--) { - r = __stmp3xxx_reset_block(hwreg, just_enable); - if (!r) - break; - pr_debug("%s: try %d failed\n", __func__, 10 - try); - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_reset_block); - -struct platform_device stmp3xxx_dbguart = { - .name = "stmp3xxx-dbguart", - .id = -1, -}; - -void __init stmp3xxx_init(void) -{ - /* Turn off auto-slow and other tricks */ - stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - - stmp3xxx_dma_init(); -} diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c deleted file mode 100644 index 68fed4b8746..00000000000 --- a/arch/arm/plat-stmp3xxx/devices.c +++ /dev/null @@ -1,389 +0,0 @@ -/* -* Freescale STMP37XX/STMP378X platform devices -* -* Embedded Alley Solutions, Inc <source@embeddedalley.com> -* -* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. -* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. -*/ - -/* -* The code contained herein is licensed under the GNU General Public -* License. You may obtain a copy of the GNU General Public License -* Version 2 or later at the following locations: -* -* http://www.opensource.org/licenses/gpl-license.html -* http://www.gnu.org/copyleft/gpl.html -*/ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> - -#include <mach/dma.h> -#include <mach/platform.h> -#include <mach/stmp3xxx.h> -#include <mach/regs-lcdif.h> -#include <mach/regs-uartapp.h> -#include <mach/regs-gpmi.h> -#include <mach/regs-usbctrl.h> -#include <mach/regs-ssp.h> -#include <mach/regs-rtc.h> - -static u64 common_dmamask = DMA_BIT_MASK(32); - -static struct resource appuart_resources[] = { - { - .start = IRQ_UARTAPP_INTERNAL, - .end = IRQ_UARTAPP_INTERNAL, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_UARTAPP_RX_DMA, - .end = IRQ_UARTAPP_RX_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_UARTAPP_TX_DMA, - .end = IRQ_UARTAPP_TX_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = REGS_UARTAPP1_PHYS, - .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE, - .flags = IORESOURCE_MEM, - }, { - /* Rx DMA channel */ - .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), - .flags = IORESOURCE_DMA, - }, { - /* Tx DMA channel */ - .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device stmp3xxx_appuart = { - .name = "stmp3xxx-appuart", - .id = 0, - .resource = appuart_resources, - .num_resources = ARRAY_SIZE(appuart_resources), - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device stmp3xxx_watchdog = { - .name = "stmp3xxx_wdt", - .id = -1, -}; - -static struct resource ts_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_TOUCH_DETECT, - .end = IRQ_TOUCH_DETECT, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_LRADC_CH5, - .end = IRQ_LRADC_CH5, - }, -}; - -struct platform_device stmp3xxx_touchscreen = { - .name = "stmp3xxx_ts", - .id = -1, - .resource = ts_resource, - .num_resources = ARRAY_SIZE(ts_resource), -}; - -/* -* Keypad device -*/ -struct platform_device stmp3xxx_keyboard = { - .name = "stmp3xxx-keyboard", - .id = -1, -}; - -static struct resource gpmi_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_GPMI_PHYS, - .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_GPMI_DMA, - .end = IRQ_GPMI_DMA, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH), - }, -}; - -struct platform_device stmp3xxx_gpmi = { - .name = "gpmi", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = gpmi_resources, - .num_resources = ARRAY_SIZE(gpmi_resources), -}; - -static struct resource mmc1_resource[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_SSP1_PHYS, - .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_SSP1_DMA, - .end = IRQ_SSP1_DMA, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_SSP_ERROR, - .end = IRQ_SSP_ERROR, - }, -}; - -struct platform_device stmp3xxx_mmc = { - .name = "stmp3xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = mmc1_resource, - .num_resources = ARRAY_SIZE(mmc1_resource), -}; - -static struct resource usb_resources[] = { - { - .start = REGS_USBCTRL_PHYS, - .end = REGS_USBCTRL_PHYS + SZ_4K, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_USB_CTRL, - .end = IRQ_USB_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_udc = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -struct platform_device stmp3xxx_ehci = { - .name = "fsl-ehci", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -static struct resource rtc_resources[] = { - { - .start = REGS_RTC_PHYS, - .end = REGS_RTC_PHYS + REGS_RTC_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_RTC_ALARM, - .end = IRQ_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_RTC_1MSEC, - .end = IRQ_RTC_1MSEC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_rtc = { - .name = "stmp3xxx-rtc", - .id = -1, - .resource = rtc_resources, - .num_resources = ARRAY_SIZE(rtc_resources), -}; - -static struct resource ssp1_resources[] = { - { - .start = REGS_SSP1_PHYS, - .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_SSP1_DMA, - .end = IRQ_SSP1_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource ssp2_resources[] = { - { - .start = REGS_SSP2_PHYS, - .end = REGS_SSP2_PHYS + REGS_SSP_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_SSP2_DMA, - .end = IRQ_SSP2_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device stmp3xxx_spi1 = { - .name = "stmp3xxx_ssp", - .id = 1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ssp1_resources, - .num_resources = ARRAY_SIZE(ssp1_resources), -}; - -struct platform_device stmp3xxx_spi2 = { - .name = "stmp3xxx_ssp", - .id = 2, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ssp2_resources, - .num_resources = ARRAY_SIZE(ssp2_resources), -}; - -static struct resource fb_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_LCDIF_DMA, - .end = IRQ_LCDIF_DMA, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_LCDIF_ERROR, - .end = IRQ_LCDIF_ERROR, - }, { - .flags = IORESOURCE_MEM, - .start = REGS_LCDIF_PHYS, - .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE, - }, -}; - -struct platform_device stmp3xxx_framebuffer = { - .name = "stmp3xxx-fb", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(fb_resource), - .resource = fb_resource, -}; - -#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \ - static char *cmdline_device_##name; \ - static int cmdline_device_##name##_setup(char *dev) \ - { \ - cmdline_device_##name = dev + 1; \ - return 0; \ - } \ - __setup(#name, cmdline_device_##name##_setup); \ - int stmp3xxx_##name##_device_register(void) \ - { \ - struct platform_device *d = NULL; \ - if (!cmdline_device_##name || \ - !strcmp(cmdline_device_##name, #dev1)) \ - d = &stmp3xxx_##dev1; \ - else if (!strcmp(cmdline_device_##name, #dev2)) \ - d = &stmp3xxx_##dev2; \ - else \ - printk(KERN_ERR"Unknown %s assignment '%s'.\n", \ - #name, cmdline_device_##name); \ - return d ? platform_device_register(d) : -ENOENT; \ - } - -CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1) -CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2) - -struct platform_device stmp3xxx_backlight = { - .name = "stmp3xxx-bl", - .id = -1, -}; - -struct platform_device stmp3xxx_rotdec = { - .name = "stmp3xxx-rotdec", - .id = -1, -}; - -struct platform_device stmp3xxx_persistent = { - .name = "stmp3xxx-persistent", - .id = -1, -}; - -struct platform_device stmp3xxx_dcp_bootstream = { - .name = "stmp3xxx-dcpboot", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dcp_resources[] = { - { - .start = IRQ_DCP_VMI, - .end = IRQ_DCP_VMI, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_DCP, - .end = IRQ_DCP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_dcp = { - .name = "stmp3xxx-dcp", - .id = -1, - .resource = dcp_resources, - .num_resources = ARRAY_SIZE(dcp_resources), - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource battery_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_VDD5V, - .end = IRQ_VDD5V, - }, -}; - -struct platform_device stmp3xxx_battery = { - .name = "stmp3xxx-battery", - .resource = battery_resource, - .num_resources = ARRAY_SIZE(battery_resource), -}; diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c deleted file mode 100644 index b4dcf8c0477..00000000000 --- a/arch/arm/plat-stmp3xxx/dma.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * DMA helper routines for Freescale STMP37XX/STMP378X - * - * Author: dmitry pervushin <dpervushin@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/dmapool.h> -#include <linux/sysdev.h> -#include <linux/cpufreq.h> - -#include <asm/page.h> - -#include <mach/platform.h> -#include <mach/dma.h> -#include <mach/regs-apbx.h> -#include <mach/regs-apbh.h> - -static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command); -static const size_t pool_alignment = 8; -static struct stmp3xxx_dma_user { - void *pool; - int inuse; - const char *name; -} channels[MAX_DMA_CHANNELS]; - -#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) -#define IS_USED(ch) (channels[ch].inuse) - -int stmp3xxx_dma_request(int ch, struct device *dev, const char *name) -{ - struct stmp3xxx_dma_user *user; - int err = 0; - - user = channels + ch; - if (!IS_VALID_CHANNEL(ch)) { - err = -ENODEV; - goto out; - } - if (IS_USED(ch)) { - err = -EBUSY; - goto out; - } - /* Create a pool to allocate dma commands from */ - user->pool = dma_pool_create(name, dev, pool_item_size, - pool_alignment, PAGE_SIZE); - if (user->pool == NULL) { - err = -ENOMEM; - goto out; - } - user->name = name; - user->inuse++; -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_request); - -int stmp3xxx_dma_release(int ch) -{ - struct stmp3xxx_dma_user *user = channels + ch; - int err = 0; - - if (!IS_VALID_CHANNEL(ch)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(ch)) { - err = -EBUSY; - goto out; - } - BUG_ON(user->pool == NULL); - dma_pool_destroy(user->pool); - user->inuse--; -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_release); - -int stmp3xxx_dma_read_semaphore(int channel) -{ - int sem = -1; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + - STMP3XXX_DMA_CHANNEL(channel) * 0x70); - sem &= BM_APBH_CHn_SEMA_PHORE; - sem >>= BP_APBH_CHn_SEMA_PHORE; - break; - - case STMP3XXX_BUS_APBX: - sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + - STMP3XXX_DMA_CHANNEL(channel) * 0x70); - sem &= BM_APBX_CHn_SEMA_PHORE; - sem >>= BP_APBX_CHn_SEMA_PHORE; - break; - default: - BUG(); - } - return sem; -} -EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore); - -int stmp3xxx_dma_allocate_command(int channel, - struct stmp3xxx_dma_descriptor *descriptor) -{ - struct stmp3xxx_dma_user *user = channels + channel; - int err = 0; - - if (!IS_VALID_CHANNEL(channel)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(channel)) { - err = -EBUSY; - goto out; - } - if (descriptor == NULL) { - err = -EINVAL; - goto out; - } - - /* Allocate memory for a command from the buffer */ - descriptor->command = - dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle); - - /* Check it worked */ - if (!descriptor->command) { - err = -ENOMEM; - goto out; - } - - memset(descriptor->command, 0, pool_item_size); -out: - WARN_ON(err); - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_allocate_command); - -int stmp3xxx_dma_free_command(int channel, - struct stmp3xxx_dma_descriptor *descriptor) -{ - int err = 0; - - if (!IS_VALID_CHANNEL(channel)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(channel)) { - err = -EBUSY; - goto out; - } - - /* Return the command memory to the pool */ - dma_pool_free(channels[channel].pool, descriptor->command, - descriptor->handle); - - /* Initialise descriptor so we're not tempted to use it */ - descriptor->command = NULL; - descriptor->handle = 0; - descriptor->virtual_buf_ptr = NULL; - descriptor->next_descr = NULL; - - WARN_ON(err); -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_free_command); - -void stmp3xxx_dma_go(int channel, - struct stmp3xxx_dma_descriptor *head, u32 semaphore) -{ - int ch = STMP3XXX_DMA_CHANNEL(channel); - void __iomem *c, *s; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch; - s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch; - break; - - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch; - s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch; - break; - - default: - return; - } - - /* Set next command */ - __raw_writel(head->handle, c); - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - __raw_writel(semaphore, s); -} -EXPORT_SYMBOL(stmp3xxx_dma_go); - -int stmp3xxx_dma_running(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + - 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & - BM_APBH_CHn_SEMA_PHORE; - - case STMP3XXX_BUS_APBX: - return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + - 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & - BM_APBX_CHn_SEMA_PHORE; - default: - BUG(); - return 0; - } -} -EXPORT_SYMBOL(stmp3xxx_dma_running); - -/* - * Circular dma chain management - */ -void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain) -{ - int i; - - for (i = 0; i < chain->total_count; i++) - stmp3xxx_dma_free_command( - STMP3XXX_DMA(chain->channel, chain->bus), - &chain->chain[i]); -} -EXPORT_SYMBOL(stmp3xxx_dma_free_chain); - -int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, - struct stmp3xxx_dma_descriptor descriptors[], - unsigned items) -{ - int i; - int err = 0; - - if (items == 0) - return err; - - for (i = 0; i < items; i++) { - err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]); - if (err) { - WARN_ON(err); - /* - * Couldn't allocate the whole chain. - * deallocate what has been allocated - */ - if (i) { - do { - stmp3xxx_dma_free_command(ch, - &descriptors - [i]); - } while (i-- > 0); - } - return err; - } - - /* link them! */ - if (i > 0) { - descriptors[i - 1].next_descr = &descriptors[i]; - descriptors[i - 1].command->next = - descriptors[i].handle; - } - } - - /* make list circular */ - descriptors[items - 1].next_descr = &descriptors[0]; - descriptors[items - 1].command->next = descriptors[0].handle; - - chain->total_count = items; - chain->chain = descriptors; - chain->free_index = 0; - chain->active_index = 0; - chain->cooked_index = 0; - chain->free_count = items; - chain->active_count = 0; - chain->cooked_count = 0; - chain->bus = STMP3XXX_DMA_BUS(ch); - chain->channel = STMP3XXX_DMA_CHANNEL(ch); - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_make_chain); - -void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) -{ - BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus))); - chain->free_index = 0; - chain->active_index = 0; - chain->cooked_index = 0; - chain->free_count = chain->total_count; - chain->active_count = 0; - chain->cooked_count = 0; -} -EXPORT_SYMBOL(stmp37xx_circ_clear_chain); - -void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, - unsigned count) -{ - BUG_ON(chain->cooked_count < count); - - chain->cooked_count -= count; - chain->cooked_index += count; - chain->cooked_index %= chain->total_count; - chain->free_count += count; -} -EXPORT_SYMBOL(stmp37xx_circ_advance_free); - -void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, - unsigned count) -{ - void __iomem *c; - u32 mask_clr, mask; - BUG_ON(chain->free_count < count); - - chain->free_count -= count; - chain->free_index += count; - chain->free_index %= chain->total_count; - chain->active_count += count; - - switch (chain->bus) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel; - mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA; - mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA); - break; - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel; - mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA; - mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA); - break; - default: - BUG(); - return; - } - - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - stmp3xxx_clearl(mask_clr, c); - stmp3xxx_setl(mask, c); -} -EXPORT_SYMBOL(stmp37xx_circ_advance_active); - -unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain) -{ - unsigned cooked; - - cooked = chain->active_count - - stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus)); - - chain->active_count -= cooked; - chain->active_index += cooked; - chain->active_index %= chain->total_count; - - chain->cooked_count += cooked; - - return cooked; -} -EXPORT_SYMBOL(stmp37xx_circ_advance_cooked); - -void stmp3xxx_dma_set_alt_target(int channel, int function) -{ -#if defined(CONFIG_ARCH_STMP37XX) - unsigned bits = 4; -#elif defined(CONFIG_ARCH_STMP378X) - unsigned bits = 2; -#else -#error wrong arch -#endif - int shift = STMP3XXX_DMA_CHANNEL(channel) * bits; - unsigned mask = (1<<bits) - 1; - void __iomem *c; - - BUG_ON(function < 0 || function >= (1<<bits)); - pr_debug("%s: channel = %d, using mask %x, " - "shift = %d\n", __func__, channel, mask, shift); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_DEVSEL; - break; - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_DEVSEL; - break; - default: - BUG(); - } - stmp3xxx_clearl(mask << shift, c); - stmp3xxx_setl(mask << shift, c); -} -EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target); - -void stmp3xxx_dma_suspend(void) -{ - stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0); - stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0); -} - -void stmp3xxx_dma_resume(void) -{ - stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST, - REGS_APBH_BASE + HW_APBH_CTRL0); - stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST, - REGS_APBX_BASE + HW_APBX_CTRL0); -} - -#ifdef CONFIG_CPU_FREQ - -struct dma_notifier_block { - struct notifier_block nb; - void *data; -}; - -static int dma_cpufreq_notifier(struct notifier_block *self, - unsigned long phase, void *p) -{ - switch (phase) { - case CPUFREQ_POSTCHANGE: - stmp3xxx_dma_resume(); - break; - - case CPUFREQ_PRECHANGE: - stmp3xxx_dma_suspend(); - break; - - default: - break; - } - - return NOTIFY_DONE; -} - -static struct dma_notifier_block dma_cpufreq_nb = { - .nb = { - .notifier_call = dma_cpufreq_notifier, - }, -}; -#endif /* CONFIG_CPU_FREQ */ - -void __init stmp3xxx_dma_init(void) -{ - stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST, - REGS_APBH_BASE + HW_APBH_CTRL0); - stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST, - REGS_APBX_BASE + HW_APBX_CTRL0); -#ifdef CONFIG_CPU_FREQ - cpufreq_register_notifier(&dma_cpufreq_nb.nb, - CPUFREQ_TRANSITION_NOTIFIER); -#endif /* CONFIG_CPU_FREQ */ -} diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h deleted file mode 100644 index f9c39772d7c..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_MACH_CLKDEV_H -#define __ASM_MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h deleted file mode 100644 index b4e205b95f2..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/cputype.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X CPU type detection - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_CPU_H -#define __ASM_PLAT_CPU_H - -#ifdef CONFIG_ARCH_STMP37XX -#define cpu_is_stmp37xx() (1) -#else -#define cpu_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_ARCH_STMP378X -#define cpu_is_stmp378x() (1) -#else -#define cpu_is_stmp378x() (0) -#endif - -#endif /* __ASM_PLAT_CPU_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S deleted file mode 100644 index d3a0985c968..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Debugging macro include header - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro addruart, rp, rv - mov \rp, #0x00070000 - add \rv, \rp, #0xf0000000 @ virtual base - add \rp, \rp, #0x80000000 @ physical base - .endm - - .macro senduart,rd,rx - strb \rd, [\rx, #0] @ data register at 0 - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h deleted file mode 100644 index 7c58557c676..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/dma.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X DMA helper interface - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_DMA_H -#define __ASM_PLAT_STMP3XXX_DMA_H - -#include <linux/platform_device.h> -#include <linux/dmapool.h> - -#if !defined(MAX_PIO_WORDS) -#define MAX_PIO_WORDS (15) -#endif - -#define STMP3XXX_BUS_APBH 0 -#define STMP3XXX_BUS_APBX 1 -#define STMP3XXX_DMA_MAX_CHANNEL 16 -#define STMP3XXX_DMA_BUS(dma) ((dma) / 16) -#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16) -#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel)) -#define MAX_DMA_ADDRESS 0xffffffff -#define MAX_DMA_CHANNELS 32 - -struct stmp3xxx_dma_command { - u32 next; - u32 cmd; - union { - u32 buf_ptr; - u32 alternate; - }; - u32 pio_words[MAX_PIO_WORDS]; -}; - -struct stmp3xxx_dma_descriptor { - struct stmp3xxx_dma_command *command; - dma_addr_t handle; - - /* The virtual address of the buffer pointer */ - void *virtual_buf_ptr; - /* The next descriptor in a the DMA chain (optional) */ - struct stmp3xxx_dma_descriptor *next_descr; -}; - -struct stmp37xx_circ_dma_chain { - unsigned total_count; - struct stmp3xxx_dma_descriptor *chain; - - unsigned free_index; - unsigned free_count; - unsigned active_index; - unsigned active_count; - unsigned cooked_index; - unsigned cooked_count; - - int bus; - unsigned channel; -}; - -static inline struct stmp3xxx_dma_descriptor - *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain) -{ - return &(chain->chain[chain->free_index]); -} - -static inline struct stmp3xxx_dma_descriptor - *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain) -{ - return &(chain->chain[chain->cooked_index]); -} - -int stmp3xxx_dma_request(int ch, struct device *dev, const char *name); -int stmp3xxx_dma_release(int ch); -int stmp3xxx_dma_allocate_command(int ch, - struct stmp3xxx_dma_descriptor *descriptor); -int stmp3xxx_dma_free_command(int ch, - struct stmp3xxx_dma_descriptor *descriptor); -void stmp3xxx_dma_continue(int channel, u32 semaphore); -void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head, - u32 semaphore); -int stmp3xxx_dma_running(int ch); -int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, - struct stmp3xxx_dma_descriptor descriptors[], - unsigned items); -void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain); -void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain); -void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, - unsigned count); -void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, - unsigned count); -unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain); -int stmp3xxx_dma_read_semaphore(int ch); -void stmp3xxx_dma_init(void); -void stmp3xxx_dma_set_alt_target(int ch, int target); -void stmp3xxx_dma_suspend(void); -void stmp3xxx_dma_resume(void); - -/* - * STMP37xx and STMP378x have different DMA control - * registers layout - */ - -void stmp3xxx_arch_dma_freeze(int ch); -void stmp3xxx_arch_dma_unfreeze(int ch); -void stmp3xxx_arch_dma_reset_channel(int ch); -void stmp3xxx_arch_dma_enable_interrupt(int ch); -void stmp3xxx_arch_dma_clear_interrupt(int ch); -int stmp3xxx_arch_dma_is_interrupt(int ch); - -static inline void stmp3xxx_dma_reset_channel(int ch) -{ - stmp3xxx_arch_dma_reset_channel(ch); -} - - -static inline void stmp3xxx_dma_freeze(int ch) -{ - stmp3xxx_arch_dma_freeze(ch); -} - -static inline void stmp3xxx_dma_unfreeze(int ch) -{ - stmp3xxx_arch_dma_unfreeze(ch); -} - -static inline void stmp3xxx_dma_enable_interrupt(int ch) -{ - stmp3xxx_arch_dma_enable_interrupt(ch); -} - -static inline void stmp3xxx_dma_clear_interrupt(int ch) -{ - stmp3xxx_arch_dma_clear_interrupt(ch); -} - -static inline int stmp3xxx_dma_is_interrupt(int ch) -{ - return stmp3xxx_arch_dma_is_interrupt(ch); -} - -#endif /* __ASM_PLAT_STMP3XXX_DMA_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h deleted file mode 100644 index a8b57925617..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X GPIO interface - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_GPIO_H -#define __ASM_PLAT_GPIO_H - -#define ARCH_NR_GPIOS (32 * 3) -#define gpio_to_irq(gpio) __gpio_to_irq(gpio) -#define gpio_get_value(gpio) __gpio_get_value(gpio) -#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value) - -#include <asm-generic/gpio.h> - -#endif /* __ASM_PLAT_GPIO_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h deleted file mode 100644 index e166432910a..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __MACH_GPMI_H - -#include <linux/mtd/partitions.h> -#include <mach/regs-gpmi.h> - -struct gpmi_platform_data { - void *pins; - int nr_parts; - struct mtd_partition *parts; - const char *part_types[]; -}; -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h deleted file mode 100644 index 47b8978405b..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file contains the hardware definitions of the Freescale STMP3XXX - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xF0000000 /* VA of IO */ -#define IO_SIZE 0x00100000 /* How much? */ -#define IO_START 0x80000000 /* PA of IO */ - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h deleted file mode 100644 index d08b1b7f3d1..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/io.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (a) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h deleted file mode 100644 index 61fa54882e1..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/memory.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0x40000000) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h deleted file mode 100644 index ba81e154376..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _MACH_MMC_H -#define _MACH_MMC_H - -#include <mach/regs-ssp.h> - -struct stmp3xxxmmc_platform_data { - int (*get_wp)(void); - unsigned long (*setclock)(void __iomem *base, unsigned long); - void (*cmd_pullup)(int); - int (*hw_init)(void); - void (*hw_release)(void); -}; - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h deleted file mode 100644 index cc5af82279a..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X Pin Multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __PINMUX_H -#define __PINMUX_H - -#include <linux/spinlock.h> -#include <linux/types.h> -#include <linux/gpio.h> -#include <asm-generic/gpio.h> - -/* Pin definitions */ -#include "pins.h" -#include <mach/pins.h> - -/* - * Each pin may be routed up to four different HW interfaces - * including GPIO - */ -enum pin_fun { - PIN_FUN1 = 0, - PIN_FUN2, - PIN_FUN3, - PIN_GPIO, -}; - -/* - * Each pin may have different output drive strength in range from - * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. - */ -enum pin_strength { - PIN_4MA = 0, - PIN_8MA, - PIN_12MA, - PIN_16MA, - PIN_20MA, -}; - -/* - * Each pin can be programmed for 1.8V or 3.3V - */ -enum pin_voltage { - PIN_1_8V = 0, - PIN_3_3V, -}; - -/* - * Structure to define a group of pins and their parameters - */ -struct pin_desc { - unsigned id; - enum pin_fun fun; - enum pin_strength strength; - enum pin_voltage voltage; - unsigned pullup:1; -}; - -struct pin_group { - struct pin_desc *pins; - int nr_pins; -}; - -/* Set pin drive strength */ -void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, - const char *label); - -/* Set pin voltage */ -void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, - const char *label); - -/* Enable pull-up resistor for a pin */ -void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label); - -/* - * Request a pin ownership, only one module (identified by @label) - * may own a pin. - */ -int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label); - -/* Release pin */ -void stmp3xxx_release_pin(unsigned id, const char *label); - -void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun); - -/* - * Each bank is associated with a number of registers to control - * pin function, drive strength, voltage and pull-up reigster. The - * number of registers of a given type depends on the number of bits - * describin particular pin. - */ -#define HW_MUXSEL_NUM 2 /* registers per bank */ -#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */ -#define HW_MUXSEL_PIN_NUM 16 /* pins per register */ -#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */ -#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */ - -#define HW_DRIVE_NUM 4 /* registers per bank */ -#define HW_DRIVE_PIN_LEN 4 /* bits per pin */ -#define HW_DRIVE_PIN_NUM 8 /* pins per register */ -#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */ -#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */ -#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */ - - -struct stmp3xxx_pinmux_bank { - struct gpio_chip chip; - - /* Pins allocation map */ - unsigned long pin_map; - - /* Pin owner names */ - const char *pin_labels[32]; - - /* Bank registers */ - void __iomem *hw_muxsel[HW_MUXSEL_NUM]; - void __iomem *hw_drive[HW_DRIVE_NUM]; - void __iomem *hw_pull; - - void __iomem *pin2irq, - *irqlevel, - *irqpolarity, - *irqen, - *irqstat; - - /* HW MUXSEL register function bit values */ - u8 functions[HW_MUXSEL_PINFUN_NUM]; - - /* - * HW DRIVE register strength bit values: - * 0xff - requested strength is not supported for this bank - */ - u8 strengths[HW_DRIVE_PINDRV_NUM]; - - /* GPIO things */ - void __iomem *hw_gpio_in, - *hw_gpio_out, - *hw_gpio_doe; - int irq, virq; -}; - -int __init stmp3xxx_pinmux_init(int virtual_irq_start); - -#endif /* __PINMUX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h deleted file mode 100644 index c573318e1ca..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_PINS_H -#define __ASM_PLAT_PINS_H - -#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin) -#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32) -#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32) - -/* - * Special invalid pin identificator to show a pin doesn't exist - */ -#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF) - -#endif /* __ASM_PLAT_PINS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h deleted file mode 100644 index 7007ddaa91e..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/platform.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_PLATFORM_H -#define __ASM_PLAT_PLATFORM_H - -#ifndef __ASSEMBLER__ -#include <linux/io.h> -#endif -#include <asm/sizes.h> - -/* Virtual address where registers are mapped */ -#define STMP3XXX_REGS_PHBASE 0x80000000 -#ifdef __ASSEMBLER__ -#define STMP3XXX_REGS_BASE 0xF0000000 -#else -#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000 -#endif -#define STMP3XXX_REGS_SIZE SZ_1M - -/* Virtual address where OCRAM is mapped */ -#define STMP3XXX_OCRAM_PHBASE 0x00000000 -#ifdef __ASSEMBLER__ -#define STMP3XXX_OCRAM_BASE 0xf1000000 -#else -#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000 -#endif -#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K) - -#ifdef CONFIG_ARCH_STMP37XX -#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD -#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR -#endif - -#ifdef CONFIG_ARCH_STMP378X -#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD -#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR -#endif - -#define HW_STMP3XXX_SET 0x04 -#define HW_STMP3XXX_CLR 0x08 -#define HW_STMP3XXX_TOG 0x0c - -#ifndef __ASSEMBLER__ -static inline void stmp3xxx_clearl(u32 v, void __iomem *r) -{ - __raw_writel(v, r + HW_STMP3XXX_CLR); -} - -static inline void stmp3xxx_setl(u32 v, void __iomem *r) -{ - __raw_writel(v, r + HW_STMP3XXX_SET); -} -#endif - -#define BF(value, field) (((value) << BP_##field) & BM_##field) - -#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h deleted file mode 100644 index 2e300feaa4c..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X core structure and function declarations - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_H -#define __ASM_PLAT_STMP3XXX_H - -#include <linux/irq.h> - -extern struct sys_timer stmp3xxx_timer; - -void stmp3xxx_init_irq(struct irq_chip *chip); -void stmp3xxx_init(void); -int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable); -extern struct platform_device stmp3xxx_dbguart, - stmp3xxx_appuart, - stmp3xxx_watchdog, - stmp3xxx_touchscreen, - stmp3xxx_keyboard, - stmp3xxx_gpmi, - stmp3xxx_mmc, - stmp3xxx_udc, - stmp3xxx_ehci, - stmp3xxx_rtc, - stmp3xxx_spi1, - stmp3xxx_spi2, - stmp3xxx_backlight, - stmp3xxx_rotdec, - stmp3xxx_dcp, - stmp3xxx_dcp_bootstream, - stmp3xxx_persistent, - stmp3xxx_framebuffer, - stmp3xxx_battery; -int stmp3xxx_ssp1_device_register(void); -int stmp3xxx_ssp2_device_register(void); - -struct pin_group; -void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label); -int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label); - -#endif /* __ASM_PLAT_STMP3XXX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h deleted file mode 100644 index 28a98888931..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/system.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <asm/proc-fns.h> -#include <mach/platform.h> -#include <mach/regs-clkctrl.h> -#include <mach/regs-power.h> - -static inline void arch_idle(void) -{ - /* - * This should do all the clock switching - * and wait for interrupt tricks - */ - - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - /* Set BATTCHRG to default value */ - __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE); - - /* Set MINPWR to default value */ - __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR); - - /* Reset digital side of chip (but not power or RTC) */ - __raw_writel(BM_CLKCTRL_RESET_DIG, - REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET); - - /* Should not return */ -} - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h deleted file mode 100644 index 3373985d7a8..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * System time clock is sourced from the 32k clock - */ -#define CLOCK_TICK_RATE (32768) diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h deleted file mode 100644 index f79f5ee56cd..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_UNCOMPRESS_H -#define __ASM_PLAT_UNCOMPRESS_H - -/* - * Register includes are for when the MMU enabled; we need to define our - * own stuff here for pre-MMU use - */ -#define UARTDBG_BASE 0x80070000 -#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c]) - -/* - * This does not append a newline - */ -static void putc(char c) -{ - /* Wait for TX fifo empty */ - while ((UART(6) & (1<<7)) == 0) - continue; - - /* Write byte */ - UART(0) = c; - - /* Wait for last bit to exit the UART */ - while (UART(6) & (1<<3)) - continue; -} - -static void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#define arch_decomp_wdog() - -#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h deleted file mode 100644 index 943c1a29d64..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define VMALLOC_END 0xf0000000UL diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c deleted file mode 100644 index aaa168683d4..00000000000 --- a/arch/arm/plat-stmp3xxx/irq.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X common interrupt handling code - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/sysdev.h> - -#include <mach/stmp3xxx.h> -#include <mach/platform.h> -#include <mach/regs-icoll.h> - -void __init stmp3xxx_init_irq(struct irq_chip *chip) -{ - unsigned int i, lv; - - /* Reset the interrupt controller */ - stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true); - - /* Disable all interrupts initially */ - for (i = 0; i < NR_REAL_IRQS; i++) { - chip->irq_mask(irq_get_irq_data(i)); - set_irq_chip(i, chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - - /* Ensure vector is cleared */ - for (lv = 0; lv < 4; lv++) - __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c deleted file mode 100644 index 66d5bac3ace..00000000000 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * Freescale STMP378X/STMP378X Pin Multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define DEBUG -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/sysdev.h> -#include <linux/string.h> -#include <linux/bitops.h> -#include <linux/irq.h> - -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/regs-pinctrl.h> -#include <mach/pins.h> -#include <mach/pinmux.h> - -#define NR_BANKS ARRAY_SIZE(pinmux_banks) -static struct stmp3xxx_pinmux_bank pinmux_banks[] = { - [0] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0, - .irq = IRQ_GPIO0, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0, - }, - [1] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1, - .irq = IRQ_GPIO1, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1, - }, - [2] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2, - .irq = IRQ_GPIO2, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2, - }, - [3] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14, - NULL, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3, - .functions = {0x0, 0x1, 0x2, 0x3}, - .strengths = {0x0, 0x1, 0x2, 0x3, 0xff}, - }, -}; - -static inline struct stmp3xxx_pinmux_bank * -stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin) -{ - unsigned b, p; - - b = STMP3XXX_PINID_TO_BANK(id); - p = STMP3XXX_PINID_TO_PINNUM(id); - BUG_ON(b >= NR_BANKS); - if (bank) - *bank = b; - if (pin) - *pin = p; - return &pinmux_banks[b]; -} - -/* Check if requested pin is owned by caller */ -static int stmp3xxx_check_pin(unsigned id, const char *label) -{ - unsigned pin; - struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin); - - if (!test_bit(pin, &pm->pin_map)) { - printk(KERN_WARNING - "%s: Accessing free pin %x, caller %s\n", - __func__, id, label); - - return -EINVAL; - } - - if (label && pm->pin_labels[pin] && - strcmp(label, pm->pin_labels[pin])) { - printk(KERN_WARNING - "%s: Wrong pin owner %x, caller %s owner %s\n", - __func__, id, label, pm->pin_labels[pin]); - - return -EINVAL; - } - return 0; -} - -void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, - const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwdrive; - u32 shift, val; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label, - bank, pin, strength); - - hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; - shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; - val = pbank->strengths[strength]; - if (val == 0xff) { - printk(KERN_WARNING - "%s: strength is not supported for bank %d, caller %s", - __func__, bank, label); - return; - } - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, - val << shift, hwdrive); - stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive); - stmp3xxx_setl(val << shift, hwdrive); -} - -void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, - const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwdrive; - u32 shift; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label, - bank, pin, voltage); - - hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; - shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: changing 0x%x bit in 0x%p register\n", - __func__, HW_DRIVE_PINV_MASK << shift, hwdrive); - if (voltage == PIN_1_8V) - stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive); - else - stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive); -} - -void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwpull; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label, - bank, pin, enable); - - hwpull = pbank->hw_pull; - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: changing 0x%x bit in 0x%p register\n", - __func__, 1 << pin, hwpull); - if (enable) - stmp3xxx_setl(1 << pin, hwpull); - else - stmp3xxx_clearl(1 << pin, hwpull); -} - -int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - u32 bank, pin; - int ret = 0; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label, - bank, pin, fun); - - if (test_bit(pin, &pbank->pin_map)) { - printk(KERN_WARNING - "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n", - __func__, bank, pin, label, pbank->pin_labels[pin]); - return -EBUSY; - } - - set_bit(pin, &pbank->pin_map); - pbank->pin_labels[pin] = label; - - stmp3xxx_set_pin_type(id, fun); - - return ret; -} - -void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwmux; - u32 shift, val; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - - hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM]; - shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; - - val = pbank->functions[fun]; - shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; - pr_debug("%s: writing 0x%x to 0x%p register\n", - __func__, val << shift, hwmux); - stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux); - stmp3xxx_setl(val << shift, hwmux); -} - -void stmp3xxx_release_pin(unsigned id, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin); - - if (stmp3xxx_check_pin(id, label)) - return; - - clear_bit(pin, &pbank->pin_map); - pbank->pin_labels[pin] = NULL; -} - -int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label) -{ - struct pin_desc *pin; - int p; - int err = 0; - - /* Allocate and configure pins */ - for (p = 0; p < pin_group->nr_pins; p++) { - pr_debug("%s: #%d\n", __func__, p); - pin = &pin_group->pins[p]; - - err = stmp3xxx_request_pin(pin->id, pin->fun, label); - if (err) - goto out_err; - - stmp3xxx_pin_strength(pin->id, pin->strength, label); - stmp3xxx_pin_voltage(pin->id, pin->voltage, label); - stmp3xxx_pin_pullup(pin->id, pin->pullup, label); - } - - return 0; - -out_err: - /* Release allocated pins in case of error */ - while (--p >= 0) { - pr_debug("%s: releasing #%d\n", __func__, p); - stmp3xxx_release_pin(pin_group->pins[p].id, label); - } - return err; -} -EXPORT_SYMBOL(stmp3xxx_request_pin_group); - -void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label) -{ - struct pin_desc *pin; - int p; - - for (p = 0; p < pin_group->nr_pins; p++) { - pin = &pin_group->pins[p]; - stmp3xxx_release_pin(pin->id, label); - } -} -EXPORT_SYMBOL(stmp3xxx_release_pin_group); - -static int stmp3xxx_irq_data_to_gpio(struct irq_data *d, - struct stmp3xxx_pinmux_bank **bank, unsigned *gpio) -{ - struct stmp3xxx_pinmux_bank *pm; - - for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++) - if (pm->virq <= d->irq && d->irq < pm->virq + 32) { - *bank = pm; - *gpio = d->irq - pm->virq; - return 0; - } - return -ENOENT; -} - -static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - int l, p; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - l = 0; p = 1; break; - case IRQ_TYPE_EDGE_FALLING: - l = 0; p = 0; break; - case IRQ_TYPE_LEVEL_HIGH: - l = 1; p = 1; break; - case IRQ_TYPE_LEVEL_LOW: - l = 1; p = 0; break; - default: - pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", - __func__, type); - return -ENXIO; - } - - if (l) - stmp3xxx_setl(1 << gpio, pm->irqlevel); - else - stmp3xxx_clearl(1 << gpio, pm->irqlevel); - if (p) - stmp3xxx_setl(1 << gpio, pm->irqpolarity); - else - stmp3xxx_clearl(1 << gpio, pm->irqpolarity); - return 0; -} - -static void stmp3xxx_pin_ack_irq(struct irq_data *d) -{ - u32 stat; - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stat = __raw_readl(pm->irqstat) & (1 << gpio); - stmp3xxx_clearl(stat, pm->irqstat); -} - -static void stmp3xxx_pin_mask_irq(struct irq_data *d) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stmp3xxx_clearl(1 << gpio, pm->irqen); - stmp3xxx_clearl(1 << gpio, pm->pin2irq); -} - -static void stmp3xxx_pin_unmask_irq(struct irq_data *d) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stmp3xxx_setl(1 << gpio, pm->irqen); - stmp3xxx_setl(1 << gpio, pm->pin2irq); -} - -static inline -struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip) -{ - return container_of(chip, struct stmp3xxx_pinmux_bank, chip); -} - -static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - return pm->virq + offset; -} - -static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - unsigned v; - - v = __raw_readl(pm->hw_gpio_in) & (1 << offset); - return v ? 1 : 0; -} - -static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - if (v) - stmp3xxx_setl(1 << offset, pm->hw_gpio_out); - else - stmp3xxx_clearl(1 << offset, pm->hw_gpio_out); -} - -static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - stmp3xxx_setl(1 << offset, pm->hw_gpio_doe); - stmp3xxx_gpio_set(chip, offset, v); - return 0; -} - -static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe); - return 0; -} - -static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio"); -} - -static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - stmp3xxx_release_pin(chip->base + offset, "gpio"); -} - -static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) -{ - struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq); - int gpio_irq = pm->virq; - u32 stat = __raw_readl(pm->irqstat); - - while (stat) { - if (stat & 1) - irq_desc[gpio_irq].handle_irq(gpio_irq, - &irq_desc[gpio_irq]); - gpio_irq++; - stat >>= 1; - } -} - -static struct irq_chip gpio_irq_chip = { - .irq_ack = stmp3xxx_pin_ack_irq, - .irq_mask = stmp3xxx_pin_mask_irq, - .irq_unmask = stmp3xxx_pin_unmask_irq, - .irq_set_type = stmp3xxx_set_irqtype, -}; - -int __init stmp3xxx_pinmux_init(int virtual_irq_start) -{ - int b, r = 0; - struct stmp3xxx_pinmux_bank *pm; - int virq; - - for (b = 0; b < 3; b++) { - /* only banks 0,1,2 are allowed to GPIO */ - pm = pinmux_banks + b; - pm->chip.base = 32 * b; - pm->chip.ngpio = 32; - pm->chip.owner = THIS_MODULE; - pm->chip.can_sleep = 1; - pm->chip.exported = 1; - pm->chip.to_irq = stmp3xxx_gpio_to_irq; - pm->chip.direction_input = stmp3xxx_gpio_input; - pm->chip.direction_output = stmp3xxx_gpio_output; - pm->chip.get = stmp3xxx_gpio_get; - pm->chip.set = stmp3xxx_gpio_set; - pm->chip.request = stmp3xxx_gpio_request; - pm->chip.free = stmp3xxx_gpio_free; - pm->virq = virtual_irq_start + b * 32; - - for (virq = pm->virq; virq < pm->virq; virq++) { - gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); - set_irq_chip(virq, &gpio_irq_chip); - set_irq_handler(virq, handle_level_irq); - set_irq_flags(virq, IRQF_VALID); - } - r = gpiochip_add(&pm->chip); - if (r < 0) - break; - set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq); - set_irq_data(pm->irq, pm); - } - return r; -} - -MODULE_AUTHOR("Vladislav Buzov"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c deleted file mode 100644 index c395630a6ed..00000000000 --- a/arch/arm/plat-stmp3xxx/timer.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * System timer for Freescale STMP37XX/STMP378X - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/interrupt.h> - -#include <asm/mach/time.h> -#include <mach/stmp3xxx.h> -#include <mach/platform.h> -#include <mach/regs-timrot.h> - -static irqreturn_t -stmp3xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *c = dev_id; - - /* timer 0 */ - if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) & - BM_TIMROT_TIMCTRLn_IRQ) { - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - c->event_handler(c); - } - - /* timer 1 */ - else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1) - & BM_TIMROT_TIMCTRLn_IRQ) { - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - } - - return IRQ_HANDLED; -} - -static cycle_t stmp3xxx_clock_read(struct clocksource *cs) -{ - return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1) - & 0xFFFF0000) >> 16); -} - -static int -stmp3xxx_timrot_set_next_event(unsigned long delta, - struct clock_event_device *dev) -{ - /* reload the timer */ - __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - return 0; -} - -static void -stmp3xxx_timrot_set_mode(enum clock_event_mode mode, - struct clock_event_device *dev) -{ -} - -static struct clock_event_device ckevt_timrot = { - .name = "timrot", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_next_event = stmp3xxx_timrot_set_next_event, - .set_mode = stmp3xxx_timrot_set_mode, -}; - -static struct clocksource cksrc_stmp3xxx = { - .name = "cksrc_stmp3xxx", - .rating = 250, - .read = stmp3xxx_clock_read, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static struct irqaction stmp3xxx_timer_irq = { - .name = "stmp3xxx_timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = stmp3xxx_timer_interrupt, - .dev_id = &ckevt_timrot, -}; - - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -static void __init stmp3xxx_init_timer(void) -{ - ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, - ckevt_timrot.shift); - ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); - ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); - ckevt_timrot.cpumask = cpumask_of(0); - - stmp3xxx_reset_block(REGS_TIMROT_BASE, false); - - /* clear two timers */ - __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - - /* configure them */ - __raw_writel( - (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - __raw_writel( - (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - - __raw_writel(CLOCK_TICK_RATE / HZ - 1, - REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - - setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); - - clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE); - clockevents_register_device(&ckevt_timrot); -} - -#ifdef CONFIG_PM - -void stmp3xxx_suspend_timer(void) -{ - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE, - REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); -} - -void stmp3xxx_resume_timer(void) -{ - stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, - REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); - __raw_writel( - 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - __raw_writel( - 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - __raw_writel(CLOCK_TICK_RATE / HZ - 1, - REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); -} - -#else - -#define stmp3xxx_suspend_timer NULL -#define stmp3xxx_resume_timer NULL - -#endif /* CONFIG_PM */ - -struct sys_timer stmp3xxx_timer = { - .init = stmp3xxx_init_timer, - .suspend = stmp3xxx_suspend_timer, - .resume = stmp3xxx_resume_timer, -}; diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index 31d945d37e4..f0cc8e19b09 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c @@ -30,7 +30,7 @@ static void fpga_irq_unmask(struct irq_data *d) static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) { - struct fpga_irq_data *f = get_irq_desc_data(desc); + struct fpga_irq_data *f = irq_desc_get_handler_data(desc); u32 status = readl(f->base + IRQ_STATUS); if (status == 0) { @@ -55,17 +55,17 @@ void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f) f->chip.irq_unmask = fpga_irq_unmask; if (parent_irq != -1) { - set_irq_data(parent_irq, f); - set_irq_chained_handler(parent_irq, fpga_irq_handle); + irq_set_handler_data(parent_irq, f); + irq_set_chained_handler(parent_irq, fpga_irq_handle); } for (i = 0; i < 32; i++) { if (valid & (1 << i)) { unsigned int irq = f->irq_start + i; - set_irq_chip_data(irq, f); - set_irq_chip(irq, &f->chip); - set_irq_handler(irq, handle_level_irq); + irq_set_chip_data(irq, f); + irq_set_chip_and_handler(irq, &f->chip, + handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index ba3d471d4bc..51ecfea09b2 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -16,6 +16,7 @@ #include <linux/smp.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> /* * control for which core is the next to come out of the secondary @@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 7ca41f0a09b..3b3776d0a1a 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -17,7 +17,7 @@ # XXX: the last 12 months. If your entry is missing please email rmk at # XXX: <linux@arm.linux.org.uk> # -# Last update: Sun Mar 20 18:06:11 2011 +# Last update: Sat May 7 08:48:24 2011 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -377,6 +377,8 @@ davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 +btmavb101 MACH_BTMAVB101 BTMAVB101 2172 +btmawb101 MACH_BTMAWB101 BTMAWB101 2173 omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 anw6410 MACH_ANW6410 ANW6410 2183 imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 @@ -400,6 +402,7 @@ d2net MACH_D2NET D2NET 2282 bigdisk MACH_BIGDISK BIGDISK 2283 at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 bcmring MACH_BCMRING BCMRING 2289 +dp6xx MACH_DP6XX DP6XX 2302 mahimahi MACH_MAHIMAHI MAHIMAHI 2304 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 @@ -424,6 +427,7 @@ smdkv210 MACH_SMDKV210 SMDKV210 2456 omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 smartq7 MACH_SMARTQ7 SMARTQ7 2479 +watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491 g4evm MACH_G4EVM G4EVM 2493 omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495 ts41x MACH_TS41X TS41X 2502 @@ -433,6 +437,8 @@ mx28evk MACH_MX28EVK MX28EVK 2531 smartq5 MACH_SMARTQ5 SMARTQ5 2534 davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 +riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 +riot_x37 MACH_RIOT_X37 RIOT_X37 2578 capc7117 MACH_CAPC7117 CAPC7117 2612 icontrol MACH_ICONTROL ICONTROL 2624 qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627 @@ -445,6 +451,7 @@ spear320 MACH_SPEAR320 SPEAR320 2661 aquila MACH_AQUILA AQUILA 2676 sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679 +ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683 terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703 msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704 @@ -463,75 +470,16 @@ wbd222 MACH_WBD222 WBD222 2753 msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755 msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756 tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758 -ap420 MACH_AP420 AP420 2765 -davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767 -msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768 -msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769 -esl_vamana MACH_ESL_VAMANA ESL_VAMANA 2770 -sbc35 MACH_SBC35 SBC35 2771 -mpx6446 MACH_MPX6446 MPX6446 2772 -oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773 -kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774 -ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775 +nanos MACH_NANOS NANOS 2759 +stamp9g45 MACH_STAMP9G45 STAMP9G45 2761 cns3420vb MACH_CNS3420VB CNS3420VB 2776 -olympus MACH_OLYMPUS OLYMPUS 2778 -vortex MACH_VORTEX VORTEX 2779 -s5pc200 MACH_S5PC200 S5PC200 2780 -ecucore_9263 MACH_ECUCORE_9263 ECUCORE_9263 2781 -smdkc200 MACH_SMDKC200 SMDKC200 2782 -emsiso_sx27 MACH_EMSISO_SX27 EMSISO_SX27 2783 -apx_som9g45_ek MACH_APX_SOM9G45_EK APX_SOM9G45_EK 2784 -songshan MACH_SONGSHAN SONGSHAN 2785 -tianshan MACH_TIANSHAN TIANSHAN 2786 -vpx500 MACH_VPX500 VPX500 2787 -am3517sam MACH_AM3517SAM AM3517SAM 2788 -skat91_sim508 MACH_SKAT91_SIM508 SKAT91_SIM508 2789 -skat91_s3e MACH_SKAT91_S3E SKAT91_S3E 2790 omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 -df7220 MACH_DF7220 DF7220 2792 -nemini MACH_NEMINI NEMINI 2793 -t8200 MACH_T8200 T8200 2794 -apf51 MACH_APF51 APF51 2795 -dr_rc_unit MACH_DR_RC_UNIT DR_RC_UNIT 2796 -bordeaux MACH_BORDEAUX BORDEAUX 2797 -catania_b MACH_CATANIA_B CATANIA_B 2798 -mx51_ocean MACH_MX51_OCEAN MX51_OCEAN 2799 ti8168evm MACH_TI8168EVM TI8168EVM 2800 -neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801 -withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802 -dbps MACH_DBPS DBPS 2803 -pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805 -speedy MACH_SPEEDY SPEEDY 2806 -chrysaor MACH_CHRYSAOR CHRYSAOR 2807 -tango MACH_TANGO TANGO 2808 -synology_dsx11 MACH_SYNOLOGY_DSX11 SYNOLOGY_DSX11 2809 -hanlin_v3ext MACH_HANLIN_V3EXT HANLIN_V3EXT 2810 -hanlin_v5 MACH_HANLIN_V5 HANLIN_V5 2811 -hanlin_v3plus MACH_HANLIN_V3PLUS HANLIN_V3PLUS 2812 -iriver_story MACH_IRIVER_STORY IRIVER_STORY 2813 -irex_iliad MACH_IREX_ILIAD IREX_ILIAD 2814 -irex_dr1000 MACH_IREX_DR1000 IREX_DR1000 2815 teton_bga MACH_TETON_BGA TETON_BGA 2816 -snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817 -tam3517 MACH_TAM3517 TAM3517 2818 -pdc100 MACH_PDC100 PDC100 2819 eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820 eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821 eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 -p565 MACH_P565 P565 2824 -acer_a4 MACH_ACER_A4 ACER_A4 2825 -davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826 -eshare MACH_ESHARE ESHARE 2827 -wlbargn MACH_WLBARGN WLBARGN 2829 -bm170 MACH_BM170 BM170 2830 -netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831 -netspace_plug_v2 MACH_NETSPACE_PLUG_V2 NETSPACE_PLUG_V2 2832 -siemens_l1 MACH_SIEMENS_L1 SIEMENS_L1 2833 -elv_lcu1 MACH_ELV_LCU1 ELV_LCU1 2834 -mcu1 MACH_MCU1 MCU1 2835 -omap3_tao3530 MACH_OMAP3_TAO3530 OMAP3_TAO3530 2836 -omap3_pcutouch MACH_OMAP3_PCUTOUCH OMAP3_PCUTOUCH 2837 smdkc210 MACH_SMDKC210 SMDKC210 2838 omap3_braillo MACH_OMAP3_BRAILLO OMAP3_BRAILLO 2839 spyplug MACH_SPYPLUG SPYPLUG 2840 @@ -973,9 +921,7 @@ isc3 MACH_ISC3 ISC3 3291 rascal MACH_RASCAL RASCAL 3292 hrefv60 MACH_HREFV60 HREFV60 3293 tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294 -pyramid_td MACH_PYRAMID_TD PYRAMID_TD 3295 splendor MACH_SPLENDOR SPLENDOR 3296 -guf_planet MACH_GUF_PLANET GUF_PLANET 3297 msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298 htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299 athene MACH_ATHENE ATHENE 3300 @@ -1099,3 +1045,71 @@ ecuv5 MACH_ECUV5 ECUV5 3421 hsgx6d MACH_HSGX6D HSGX6D 3422 dawad7 MACH_DAWAD7 DAWAD7 3423 sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424 +gt_i5700 MACH_GT_I5700 GT_I5700 3425 +ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426 +marvelct MACH_MARVELCT MARVELCT 3427 +ag11005 MACH_AG11005 AG11005 3428 +vangogh MACH_VANGOGH VANGOGH 3430 +matrix505 MACH_MATRIX505 MATRIX505 3431 +oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432 +t55 MACH_T55 T55 3433 +bio3k MACH_BIO3K BIO3K 3434 +expressct MACH_EXPRESSCT EXPRESSCT 3435 +cardhu MACH_CARDHU CARDHU 3436 +aruba MACH_ARUBA ARUBA 3437 +bonaire MACH_BONAIRE BONAIRE 3438 +nuc700evb MACH_NUC700EVB NUC700EVB 3439 +nuc710evb MACH_NUC710EVB NUC710EVB 3440 +nuc740evb MACH_NUC740EVB NUC740EVB 3441 +nuc745evb MACH_NUC745EVB NUC745EVB 3442 +transcede MACH_TRANSCEDE TRANSCEDE 3443 +mora MACH_MORA MORA 3444 +nda_evm MACH_NDA_EVM NDA_EVM 3445 +timu MACH_TIMU TIMU 3446 +expressh MACH_EXPRESSH EXPRESSH 3447 +veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448 +dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449 +omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450 +tritip MACH_TRITIP TRITIP 3451 +sm1k MACH_SM1K SM1K 3452 +monch MACH_MONCH MONCH 3453 +curacao MACH_CURACAO CURACAO 3454 +origen MACH_ORIGEN ORIGEN 3455 +epc10 MACH_EPC10 EPC10 3456 +sgh_i740 MACH_SGH_I740 SGH_I740 3457 +tuna MACH_TUNA TUNA 3458 +mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459 +mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460 +acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461 +elke MACH_ELKE ELKE 3462 +sbc6000x MACH_SBC6000X SBC6000X 3463 +r1801e MACH_R1801E R1801E 3464 +h1600 MACH_H1600 H1600 3465 +mini210 MACH_MINI210 MINI210 3466 +mini8168 MACH_MINI8168 MINI8168 3467 +pc7308 MACH_PC7308 PC7308 3468 +kmm2m01 MACH_KMM2M01 KMM2M01 3470 +mx51erebus MACH_MX51EREBUS MX51EREBUS 3471 +wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472 +tuxrail MACH_TUXRAIL TUXRAIL 3473 +arthur MACH_ARTHUR ARTHUR 3474 +doorboy MACH_DOORBOY DOORBOY 3475 +xarina MACH_XARINA XARINA 3476 +roverx7 MACH_ROVERX7 ROVERX7 3477 +sdvr MACH_SDVR SDVR 3478 +acer_maya MACH_ACER_MAYA ACER_MAYA 3479 +pico MACH_PICO PICO 3480 +cwmx233 MACH_CWMX233 CWMX233 3481 +cwam1808 MACH_CWAM1808 CWAM1808 3482 +cwdm365 MACH_CWDM365 CWDM365 3483 +mx51_moray MACH_MX51_MORAY MX51_MORAY 3484 +thales_cbc MACH_THALES_CBC THALES_CBC 3485 +bluepoint MACH_BLUEPOINT BLUEPOINT 3486 +dir665 MACH_DIR665 DIR665 3487 +acmerover1 MACH_ACMEROVER1 ACMEROVER1 3488 +shooter_ct MACH_SHOOTER_CT SHOOTER_CT 3489 +bliss MACH_BLISS BLISS 3490 +blissc MACH_BLISSC BLISSC 3491 +thales_adc MACH_THALES_ADC THALES_ADC 3492 +ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 +atdgp318 MACH_ATDGP318 ATDGP318 3494 diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index bbf3da012af..f25e7ec8941 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -78,6 +78,14 @@ static void vfp_thread_exit(struct thread_info *thread) put_cpu(); } +static void vfp_thread_copy(struct thread_info *thread) +{ + struct thread_info *parent = current_thread_info(); + + vfp_sync_hwstate(parent); + thread->vfpstate = parent->vfpstate; +} + /* * When this function is called with the following 'cmd's, the following * is true while this function is being run: @@ -104,12 +112,17 @@ static void vfp_thread_exit(struct thread_info *thread) static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) { struct thread_info *thread = v; + u32 fpexc; +#ifdef CONFIG_SMP + unsigned int cpu; +#endif - if (likely(cmd == THREAD_NOTIFY_SWITCH)) { - u32 fpexc = fmrx(FPEXC); + switch (cmd) { + case THREAD_NOTIFY_SWITCH: + fpexc = fmrx(FPEXC); #ifdef CONFIG_SMP - unsigned int cpu = thread->cpu; + cpu = thread->cpu; /* * On SMP, if VFP is enabled, save the old state in @@ -134,13 +147,20 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) * old state. */ fmxr(FPEXC, fpexc & ~FPEXC_EN); - return NOTIFY_DONE; - } + break; - if (cmd == THREAD_NOTIFY_FLUSH) + case THREAD_NOTIFY_FLUSH: vfp_thread_flush(thread); - else + break; + + case THREAD_NOTIFY_EXIT: vfp_thread_exit(thread); + break; + + case THREAD_NOTIFY_COPY: + vfp_thread_copy(thread); + break; + } return NOTIFY_DONE; } @@ -378,9 +398,9 @@ static void vfp_enable(void *unused) } #ifdef CONFIG_PM -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> -static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state) +static int vfp_pm_suspend(void) { struct thread_info *ti = current_thread_info(); u32 fpexc = fmrx(FPEXC); @@ -400,34 +420,25 @@ static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int vfp_pm_resume(struct sys_device *dev) +static void vfp_pm_resume(void) { /* ensure we have access to the vfp */ vfp_enable(NULL); /* and disable it to ensure the next usage restores the state */ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); - - return 0; } -static struct sysdev_class vfp_pm_sysclass = { - .name = "vfp", +static struct syscore_ops vfp_pm_syscore_ops = { .suspend = vfp_pm_suspend, .resume = vfp_pm_resume, }; -static struct sys_device vfp_pm_sysdev = { - .cls = &vfp_pm_sysclass, -}; - static void vfp_pm_init(void) { - sysdev_class_register(&vfp_pm_sysclass); - sysdev_register(&vfp_pm_sysdev); + register_syscore_ops(&vfp_pm_syscore_ops); } - #else static inline void vfp_pm_init(void) { } #endif /* CONFIG_PM */ |