diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/irqs.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/spi.h | 3 | ||||
| -rw-r--r-- | arch/arm/plat-s3c/include/plat/devs.h | 1 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/devs.c | 50 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/fiq.h | 13 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/irq.c | 36 | ||||
| -rw-r--r-- | arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c | 38 |
10 files changed, 157 insertions, 1 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 2a2384ffa7b..6c12c6312ad 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -164,6 +164,12 @@ #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 +#ifdef CONFIG_CPU_S3C2440 +#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 +#else +#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97 +#endif + /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ #define FIQ_START IRQ_EINT0 diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index b278d0c45cc..f6e8eec879c 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -328,13 +328,15 @@ #define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2400_GPD8_TOUT3 (0x02 << 16) +#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) #define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2400_GPD9_TCLK0 (0x02 << 18) -#define S3C2410_GPD9_MASK (0x03 << 18) +#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) #define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2400_GPD10_nWAIT (0x02 << 20) +#define S3C2440_GPD10_SPICLK1 (0x03 << 20) #define S3C2410_GPD11_VD19 (0x02 << 22) diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h index 1d300fb112b..193b39d654e 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ b/arch/arm/mach-s3c2410/include/mach/spi.h @@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, int enable); +extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, + int enable); + #endif /* __ASM_ARCH_SPI_H */ diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 1989ca1bb2b..0f540ea1e99 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -58,5 +58,6 @@ extern struct platform_device s3c_device_usb_hsotg; #ifdef CONFIG_CPU_S3C2440 extern struct platform_device s3c_device_camif; +extern struct platform_device s3c_device_ac97; #endif diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 5b0bc914f58..aaae456018b 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -105,6 +105,12 @@ config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7 SPI GPIO configuration code for BUS 1 when connected to GPG5, GPG6 and GPG7. +config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10 + bool + help + SPI GPIO configuration code for BUS 1 when connected to + GPD8, GPD9 and GPD10. + # common code for s3c24xx based machines, such as the SMDKs. config MACH_SMDK diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 579a165c282..59416796fb1 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o +obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10) += spi-bus1-gpd8_9_10.o # machine common support diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 3489019b537..656b375db46 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -26,6 +26,8 @@ #include <asm/mach/irq.h> #include <mach/fb.h> #include <mach/hardware.h> +#include <mach/dma.h> +#include <mach/irqs.h> #include <asm/irq.h> #include <plat/regs-serial.h> @@ -473,4 +475,52 @@ struct platform_device s3c_device_camif = { EXPORT_SYMBOL(s3c_device_camif); +/* AC97 */ + +static struct resource s3c_ac97_resource[] = { + [0] = { + .start = S3C2440_PA_AC97, + .end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3C244x_AC97, + .end = IRQ_S3C244x_AC97, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "PCM out", + .start = DMACH_PCM_OUT, + .end = DMACH_PCM_OUT, + .flags = IORESOURCE_DMA, + }, + [3] = { + .name = "PCM in", + .start = DMACH_PCM_IN, + .end = DMACH_PCM_IN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .name = "Mic in", + .start = DMACH_MIC_IN, + .end = DMACH_MIC_IN, + .flags = IORESOURCE_DMA, + }, +}; + +static u64 s3c_device_ac97_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_ac97 = { + .name = "s3c-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ac97_resource), + .resource = s3c_ac97_resource, + .dev = { + .dma_mask = &s3c_device_ac97_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_ac97); + #endif // CONFIG_CPU_S32440 diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-s3c24xx/include/plat/fiq.h new file mode 100644 index 00000000000..8521b8372c5 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/fiq.h @@ -0,0 +1,13 @@ +/* linux/include/asm-arm/plat-s3c24xx/fiq.h + * + * Copyright (c) 2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Header file for S3C24XX CPU FIQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern int s3c24xx_set_fiq(unsigned int irq, bool on); diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 958737775ad..d02f5f02045 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -493,6 +493,38 @@ s3c_irq_demux_extint4t7(unsigned int irq, } } +#ifdef CONFIG_FIQ +/** + * s3c24xx_set_fiq - set the FIQ routing + * @irq: IRQ number to route to FIQ on processor. + * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. + * + * Change the state of the IRQ to FIQ routing depending on @irq and @on. If + * @on is true, the @irq is checked to see if it can be routed and the + * interrupt controller updated to route the IRQ. If @on is false, the FIQ + * routing is cleared, regardless of which @irq is specified. + */ +int s3c24xx_set_fiq(unsigned int irq, bool on) +{ + u32 intmod; + unsigned offs; + + if (on) { + offs = irq - FIQ_START; + if (offs > 31) + return -EINVAL; + + intmod = 1 << offs; + } else { + intmod = 0; + } + + __raw_writel(intmod, S3C2410_INTMOD); + return 0; +} +#endif + + /* s3c24xx_init_irq * * Initialise S3C2410 IRQ system @@ -505,6 +537,10 @@ void __init s3c24xx_init_irq(void) int irqno; int i; +#ifdef CONFIG_FIQ + init_FIQ(); +#endif + irqdbf("s3c2410_init_irq: clearing interrupt status flags\n"); /* first, clear all interrupts pending... */ diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c new file mode 100644 index 00000000000..89fcf5308cf --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c @@ -0,0 +1,38 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> + +#include <mach/spi.h> +#include <mach/regs-gpio.h> + +void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, + int enable) +{ + + printk(KERN_INFO "%s(%d)\n", __func__, enable); + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); + s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); + s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); + s3c2410_gpio_pullup(S3C2410_GPD(10), 0); + s3c2410_gpio_pullup(S3C2410_GPD(9), 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPD(10), 1); + s3c2410_gpio_pullup(S3C2410_GPD(9), 1); + s3c2410_gpio_pullup(S3C2410_GPD(8), 1); + } +} |