diff options
Diffstat (limited to 'arch/arm')
941 files changed, 11375 insertions, 11820 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 19c97e5565a..482ba91e73a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -36,7 +36,6 @@ config ARM select HAVE_GENERIC_HARDIRQS select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) select HAVE_IDE if PCI || ISA || PCMCIA - select HAVE_IRQ_WORK select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZO @@ -261,7 +260,8 @@ config MMU # choice prompt "ARM system type" - default ARCH_MULTIPLATFORM + default ARCH_VERSATILE if !MMU + default ARCH_MULTIPLATFORM if MMU config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" @@ -344,10 +344,10 @@ config ARCH_BCM2835 select ARM_ERRATA_411920 select ARM_TIMER_SP804 select CLKDEV_LOOKUP + select CLKSRC_OF select COMMON_CLK select CPU_V6 select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select MULTI_IRQ_HANDLER select PINCTRL select PINCTRL_BCM2835 @@ -642,9 +642,9 @@ config ARCH_TEGRA select ARCH_HAS_CPUFREQ select CLKDEV_LOOKUP select CLKSRC_MMIO + select CLKSRC_OF select COMMON_CLK select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 @@ -745,7 +745,6 @@ config ARCH_S3C24XX select ARCH_HAS_CPUFREQ select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -788,7 +787,6 @@ config ARCH_S5P64X0 select CLKSRC_MMIO select CPU_V6 select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -803,7 +801,6 @@ config ARCH_S5PC100 select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP select CPU_V7 - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -821,7 +818,6 @@ config ARCH_S5PV210 select CLKSRC_MMIO select CPU_V7 select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -839,7 +835,6 @@ config ARCH_EXYNOS select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -874,7 +869,6 @@ config ARCH_U300 select COMMON_CLK select CPU_ARM926T select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_TCM select SPARSE_IRQ help @@ -958,7 +952,6 @@ config ARCH_VT8500_SINGLE select COMMON_CLK select CPU_ARM926T select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select MULTI_IRQ_HANDLER select SPARSE_IRQ @@ -1087,17 +1080,12 @@ source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" -source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig" source "arch/arm/plat-spear/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" -if ARCH_S3C24XX -source "arch/arm/mach-s3c2412/Kconfig" -source "arch/arm/mach-s3c2440/Kconfig" -endif if ARCH_S3C64XX source "arch/arm/mach-s3c64xx/Kconfig" @@ -1451,6 +1439,10 @@ config ISA_DMA bool select ISA_DMA_API +config ARCH_NO_VIRT_TO_BUS + def_bool y + depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK + # Select ISA DMA interface config ISA_DMA_API bool @@ -1532,7 +1524,6 @@ config SMP config SMP_ON_UP bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" - depends on EXPERIMENTAL depends on SMP && !XIP_KERNEL default y help @@ -1621,6 +1612,16 @@ config HOTPLUG_CPU Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. +config ARM_PSCI + bool "Support for the ARM Power State Coordination Interface (PSCI)" + depends on CPU_V7 + help + Say Y here if you want Linux to communicate with system firmware + implementing the PSCI specification for CPU-centric power + management operations described in ARM document number ARM DEN + 0022A ("Power State Coordination Interface System Software on + ARM processors"). + config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP @@ -1638,7 +1639,7 @@ config ARCH_NR_GPIO default 355 if ARCH_U8500 default 264 if MACH_H4700 default 512 if SOC_OMAP5 - default 288 if ARCH_VT8500 + default 288 if ARCH_VT8500 || ARCH_SUNXI default 0 help Maximum number of GPIOs in the system. @@ -1656,6 +1657,9 @@ config HZ default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE default 100 +config SCHED_HRTICK + def_bool HIGH_RES_TIMERS + config THUMB2_KERNEL bool "Compile the kernel in Thumb-2 mode" depends on CPU_V7 && !CPU_V6 && !CPU_V6K @@ -1720,7 +1724,7 @@ config AEABI config OABI_COMPAT bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" - depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL + depends on AEABI && !THUMB2_KERNEL default y help This option preserves the old syscall interface along with the @@ -1844,7 +1848,6 @@ config SECCOMP config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" - depends on EXPERIMENTAL help This option turns on the -fstack-protector GCC feature. This feature puts, at the beginning of functions, a canary value on @@ -1861,7 +1864,7 @@ config XEN_DOM0 config XEN bool "Xen guest support on ARM (EXPERIMENTAL)" - depends on EXPERIMENTAL && ARM && OF + depends on ARM && OF depends on CPU_V7 && !CPU_V6 help Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. @@ -1930,7 +1933,7 @@ config ZBOOT_ROM choice prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" - depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL + depends on ZBOOT_ROM && ARCH_SH7372 default ZBOOT_ROM_NONE help Include experimental SD/MMC loading code in the ROM-able zImage. @@ -1959,7 +1962,7 @@ endchoice config ARM_APPENDED_DTB bool "Use appended device tree blob to zImage (EXPERIMENTAL)" - depends on OF && !ZBOOT_ROM && EXPERIMENTAL + depends on OF && !ZBOOT_ROM help With this option, the boot code will look for a device tree binary (DTB) appended to zImage @@ -2077,7 +2080,7 @@ config XIP_PHYS_ADDR config KEXEC bool "Kexec system call (EXPERIMENTAL)" - depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) + depends on (!SMP || HOTPLUG_CPU) help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot @@ -2099,7 +2102,6 @@ config ATAGS_PROC config CRASH_DUMP bool "Build kdump crash kernel (EXPERIMENTAL)" - depends on EXPERIMENTAL help Generate crash dump after being started by kexec. This should be normally only set in special crash dump kernels which are @@ -2166,7 +2168,7 @@ config CPU_FREQ_S3C config CPU_FREQ_S3C24XX bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" - depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL + depends on ARCH_S3C24XX && CPU_FREQ select CPU_FREQ_S3C help This enables the CPUfreq driver for the Samsung S3C24XX family @@ -2178,7 +2180,7 @@ config CPU_FREQ_S3C24XX config CPU_FREQ_S3C24XX_PLL bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" - depends on CPU_FREQ_S3C24XX && EXPERIMENTAL + depends on CPU_FREQ_S3C24XX help Compile in support for changing the PLL frequency from the S3C24XX series CPUfreq driver. The PLL takes time to settle @@ -2241,7 +2243,7 @@ config FPE_NWFPE_XP config FPE_FASTFPE bool "FastFPE math emulation (EXPERIMENTAL)" - depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL + depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 ---help--- Say Y here to include the FAST floating point emulator in the kernel. This is an experimental much faster emulator which now also has full @@ -2323,3 +2325,5 @@ source "security/Kconfig" source "crypto/Kconfig" source "lib/Kconfig" + +source "arch/arm/kvm/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 661030d6bc6..ad375a51a7d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -32,7 +32,7 @@ config FRAME_POINTER config ARM_UNWIND bool "Enable stack unwinding support (EXPERIMENTAL)" - depends on AEABI && EXPERIMENTAL + depends on AEABI default y help This option enables stack unwinding support in the kernel @@ -219,12 +219,12 @@ choice Say Y here if you want kernel low-level debugging support on i.MX51. - config DEBUG_IMX50_IMX53_UART - bool "i.MX50 and i.MX53 Debug UART" - depends on SOC_IMX50 || SOC_IMX53 + config DEBUG_IMX53_UART + bool "i.MX53 Debug UART" + depends on SOC_IMX53 help Say Y here if you want kernel low-level debugging support - on i.MX50 or i.MX53. + on i.MX53. config DEBUG_IMX6Q_UART bool "i.MX6Q Debug UART" @@ -497,7 +497,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX21_IMX27_UART || \ DEBUG_IMX31_IMX35_UART || \ DEBUG_IMX51_UART || \ - DEBUG_IMX50_IMX53_UART ||\ + DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/mvebu.S" if DEBUG_MVEBU_UART diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 30c443c406f..1b7071681a5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_PRIMA2) += prima2 machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_RPC) += rpc -machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx s3c2412 s3c2440 +machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0 machine-$(CONFIG_ARCH_S5PC100) += s5pc100 @@ -204,7 +204,7 @@ plat-$(CONFIG_ARCH_S3C64XX) += samsung plat-$(CONFIG_PLAT_IOP) += iop plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa -plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung +plat-$(CONFIG_PLAT_S3C24XX) += samsung plat-$(CONFIG_PLAT_S5P) += samsung plat-$(CONFIG_PLAT_SPEAR) += spear plat-$(CONFIG_PLAT_VERSATILE) += versatile @@ -252,6 +252,7 @@ core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) core-$(CONFIG_VFP) += arch/arm/vfp/ core-$(CONFIG_XEN) += arch/arm/xen/ +core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/ # If we have a machine-specific directory, then include it in the build. core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index 9deb56a702c..24b0475cb8b 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -13,8 +13,6 @@ extern void error(char *); #define STATIC static #define STATIC_RW_DATA /* non-static please */ -#define ARCH_HAS_DECOMP_WDOG - /* Diagnostic functions */ #ifdef DEBUG # define Assert(cond,msg) {if(!(cond)) error(msg);} diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 80e29c605d4..4801717566d 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -324,8 +324,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x4000>; interrupts = <5 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -335,8 +333,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x4000>; interrupts = <6 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -346,8 +342,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x4000>; interrupts = <7 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; @@ -357,8 +351,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x4000>; interrupts = <8 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 8ecca6948d8..d112c3af8ce 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -197,9 +197,9 @@ }; usart3 { - pinctrl_uart3: usart3-0 { + pinctrl_usart3: usart3-0 { atmel,pins = - <2 23 0x2 0x1 /* PC22 periph B with pullup */ + <2 22 0x2 0x1 /* PC22 periph B with pullup */ 2 23 0x2 0x0>; /* PC23 periph B */ }; @@ -402,8 +402,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x200>; interrupts = <5 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; status = "disabled"; @@ -413,8 +411,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x200>; interrupts = <6 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; status = "disabled"; @@ -424,8 +420,6 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x200>; interrupts = <7 4 5>; - atmel,use-dma-rx; - atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; status = "disabled"; diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 63f2fbcfe81..69140ba99f4 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -170,10 +170,9 @@ gpio-bank = <8>; }; - pinctrl@80157000 { - // This is actually the PRCMU base address - reg = <0x80157000 0x2000>; - compatible = "stericsson,nmk_pinctrl"; + pinctrl { + compatible = "stericsson,nmk-pinctrl"; + prcm = <&prcmu>; }; usb@a03e0000 { @@ -190,9 +189,10 @@ interrupts = <0 25 0x4>; }; - prcmu@80157000 { + prcmu: prcmu@80157000 { compatible = "stericsson,db8500-prcmu"; reg = <0x80157000 0x1000>; + reg-names = "prcmu"; interrupts = <0 47 0x4>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 42eac1ff3cc..740630f9cd6 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -93,6 +93,7 @@ reg = <0xd0400 0x20>; ngpios = <32>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <12>, <13>, <14>, <60>; }; @@ -103,6 +104,7 @@ reg = <0xd0420 0x20>; ngpios = <32>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <61>; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index e31bfc4a6f0..2feffc70814 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -48,13 +48,13 @@ }; pinctrl_0: pinctrl@11400000 { - compatible = "samsung,pinctrl-exynos4210"; + compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; interrupts = <0 47 0>; }; pinctrl_1: pinctrl@11000000 { - compatible = "samsung,pinctrl-exynos4210"; + compatible = "samsung,exynos4210-pinctrl"; reg = <0x11000000 0x1000>; interrupts = <0 46 0>; @@ -66,7 +66,7 @@ }; pinctrl_2: pinctrl@03860000 { - compatible = "samsung,pinctrl-exynos4210"; + compatible = "samsung,exynos4210-pinctrl"; reg = <0x03860000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 8e6115adcd9..099cec79e2a 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -661,7 +661,7 @@ sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; + samsung,pin-function = <4>; samsung,pin-pud = <4>; samsung,pin-drv = <3>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 179a62e46c9..9a878069490 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -37,13 +37,13 @@ }; pinctrl_0: pinctrl@11400000 { - compatible = "samsung,pinctrl-exynos4x12"; + compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; interrupts = <0 47 0>; }; pinctrl_1: pinctrl@11000000 { - compatible = "samsung,pinctrl-exynos4x12"; + compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11000000 0x1000>; interrupts = <0 46 0>; @@ -55,14 +55,14 @@ }; pinctrl_2: pinctrl@03860000 { - compatible = "samsung,pinctrl-exynos4x12"; + compatible = "samsung,exynos4x12-pinctrl"; reg = <0x03860000 0x1000>; interrupt-parent = <&combiner>; interrupts = <10 0>; }; pinctrl_3: pinctrl@106E0000 { - compatible = "samsung,pinctrl-exynos4x12"; + compatible = "samsung,exynos4x12-pinctrl"; reg = <0x106E0000 0x1000>; interrupts = <0 72 0>; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index e05b18f3c33..4db9db0a844 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -49,6 +49,11 @@ compatible = "samsung,s524ad0xd1"; reg = <0x51>; }; + + wm8994: wm8994@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + }; }; i2c@121D0000 { @@ -204,4 +209,25 @@ samsung,mfc-r = <0x43000000 0x800000>; samsung,mfc-l = <0x51000000 0x800000>; }; + + i2s0: i2s@03830000 { + gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>, + <&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>, + <&gpz 6 2 0 0>; + }; + + i2s1: i2s@12D60000 { + status = "disabled"; + }; + + i2s2: i2s@12D70000 { + status = "disabled"; + }; + + sound { + compatible = "samsung,smdk-wm8994"; + + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&wm8994>; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 3acf594ea60..f50b4e85435 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -211,8 +211,9 @@ compatible = "samsung,exynos4210-spi"; reg = <0x12d20000 0x100>; interrupts = <0 66 0>; - tx-dma-channel = <&pdma0 5>; /* preliminary */ - rx-dma-channel = <&pdma0 4>; /* preliminary */ + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; }; @@ -221,8 +222,9 @@ compatible = "samsung,exynos4210-spi"; reg = <0x12d30000 0x100>; interrupts = <0 67 0>; - tx-dma-channel = <&pdma1 5>; /* preliminary */ - rx-dma-channel = <&pdma1 4>; /* preliminary */ + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; }; @@ -231,8 +233,9 @@ compatible = "samsung,exynos4210-spi"; reg = <0x12d40000 0x100>; interrupts = <0 68 0>; - tx-dma-channel = <&pdma0 7>; /* preliminary */ - rx-dma-channel = <&pdma0 6>; /* preliminary */ + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; }; @@ -269,6 +272,35 @@ #size-cells = <0>; }; + i2s0: i2s@03830000 { + compatible = "samsung,i2s-v5"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10 + &pdma0 9 + &pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + samsung,supports-6ch; + samsung,supports-rstclr; + samsung,supports-secdai; + samsung,idma-addr = <0x03000000>; + }; + + i2s1: i2s@12D60000 { + compatible = "samsung,i2s-v5"; + reg = <0x12D60000 0x100>; + dmas = <&pdma1 12 + &pdma1 11>; + dma-names = "tx", "rx"; + }; + + i2s2: i2s@12D70000 { + compatible = "samsung,i2s-v5"; + reg = <0x12D70000 0x100>; + dmas = <&pdma0 12 + &pdma0 11>; + dma-names = "tx", "rx"; + }; + amba { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 024269de8ee..5f3562ad674 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -86,7 +86,7 @@ }; pinctrl { - compatible = "samsung,pinctrl-exynos5440"; + compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; interrupt-controller; #interrupt-cells = <2>; @@ -154,6 +154,6 @@ rtc { compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; - interrupts = <0 16 0>, <0 17 0>; + interrupts = <0 17 0>, <0 16 0>; }; }; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 5927a8df562..6aad34ad951 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -37,6 +37,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; cpu@901 { diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 65415c598a5..56afcf41aae 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -391,7 +391,9 @@ }; lradc@80050000 { + compatible = "fsl,imx23-lradc"; reg = <0x80050000 0x2000>; + interrupts = <36 37 38 39 40 41 42 43 44>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d6265ca9711..ff1205ea571 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -866,7 +866,7 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <0 118 0x04 0 119 0x04>; - clocks = <&clks 117>, <&clks 117>, <&clks 177>; + clocks = <&clks 117>, <&clks 117>, <&clks 190>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 055fca54212..3329719a941 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -58,10 +58,11 @@ #size-cells = <1>; ranges = <0x88000000 0x88000000 0x40000>; - clock-controller@88000000 { + clks: clock-controller@88000000 { compatible = "sirf,prima2-clkc"; reg = <0x88000000 0x1000>; interrupts = <3>; + #clock-cells = <1>; }; reset-controller@88010000 { @@ -85,6 +86,7 @@ compatible = "sirf,prima2-memc"; reg = <0x90000000 0x10000>; interrupts = <27>; + clocks = <&clks 5>; }; }; @@ -104,6 +106,7 @@ compatible = "sirf,prima2-vpp"; reg = <0x90020000 0x10000>; interrupts = <31>; + clocks = <&clks 35>; }; }; @@ -117,6 +120,7 @@ compatible = "powervr,sgx531"; reg = <0x98000000 0x8000000>; interrupts = <6>; + clocks = <&clks 32>; }; }; @@ -130,6 +134,7 @@ compatible = "sirf,prima2-video-codec"; reg = <0xa0000000 0x8000000>; interrupts = <5>; + clocks = <&clks 33>; }; }; @@ -149,12 +154,14 @@ compatible = "sirf,prima2-gps"; reg = <0xa8010000 0x10000>; interrupts = <7>; + clocks = <&clks 9>; }; dsp@a9000000 { compatible = "sirf,prima2-dsp"; reg = <0xa9000000 0x1000000>; interrupts = <8>; + clocks = <&clks 8>; }; }; @@ -174,12 +181,14 @@ compatible = "sirf,prima2-nand"; reg = <0xb0030000 0x10000>; interrupts = <41>; + clocks = <&clks 26>; }; audio@b0040000 { compatible = "sirf,prima2-audio"; reg = <0xb0040000 0x10000>; interrupts = <35>; + clocks = <&clks 27>; }; uart0: uart@b0050000 { @@ -187,6 +196,7 @@ compatible = "sirf,prima2-uart"; reg = <0xb0050000 0x10000>; interrupts = <17>; + clocks = <&clks 13>; }; uart1: uart@b0060000 { @@ -194,6 +204,7 @@ compatible = "sirf,prima2-uart"; reg = <0xb0060000 0x10000>; interrupts = <18>; + clocks = <&clks 14>; }; uart2: uart@b0070000 { @@ -201,6 +212,7 @@ compatible = "sirf,prima2-uart"; reg = <0xb0070000 0x10000>; interrupts = <19>; + clocks = <&clks 15>; }; usp0: usp@b0080000 { @@ -208,6 +220,7 @@ compatible = "sirf,prima2-usp"; reg = <0xb0080000 0x10000>; interrupts = <20>; + clocks = <&clks 28>; }; usp1: usp@b0090000 { @@ -215,6 +228,7 @@ compatible = "sirf,prima2-usp"; reg = <0xb0090000 0x10000>; interrupts = <21>; + clocks = <&clks 29>; }; usp2: usp@b00a0000 { @@ -222,6 +236,7 @@ compatible = "sirf,prima2-usp"; reg = <0xb00a0000 0x10000>; interrupts = <22>; + clocks = <&clks 30>; }; dmac0: dma-controller@b00b0000 { @@ -229,6 +244,7 @@ compatible = "sirf,prima2-dmac"; reg = <0xb00b0000 0x10000>; interrupts = <12>; + clocks = <&clks 24>; }; dmac1: dma-controller@b0160000 { @@ -236,11 +252,13 @@ compatible = "sirf,prima2-dmac"; reg = <0xb0160000 0x10000>; interrupts = <13>; + clocks = <&clks 25>; }; vip@b00C0000 { compatible = "sirf,prima2-vip"; reg = <0xb00C0000 0x10000>; + clocks = <&clks 31>; }; spi0: spi@b00d0000 { @@ -248,6 +266,7 @@ compatible = "sirf,prima2-spi"; reg = <0xb00d0000 0x10000>; interrupts = <15>; + clocks = <&clks 19>; }; spi1: spi@b0170000 { @@ -255,6 +274,7 @@ compatible = "sirf,prima2-spi"; reg = <0xb0170000 0x10000>; interrupts = <16>; + clocks = <&clks 20>; }; i2c0: i2c@b00e0000 { @@ -262,6 +282,7 @@ compatible = "sirf,prima2-i2c"; reg = <0xb00e0000 0x10000>; interrupts = <24>; + clocks = <&clks 17>; }; i2c1: i2c@b00f0000 { @@ -269,12 +290,14 @@ compatible = "sirf,prima2-i2c"; reg = <0xb00f0000 0x10000>; interrupts = <25>; + clocks = <&clks 18>; }; tsc@b0110000 { compatible = "sirf,prima2-tsc"; reg = <0xb0110000 0x10000>; interrupts = <33>; + clocks = <&clks 16>; }; gpio: pinctrl@b0120000 { @@ -507,17 +530,20 @@ pwm@b0130000 { compatible = "sirf,prima2-pwm"; reg = <0xb0130000 0x10000>; + clocks = <&clks 21>; }; efusesys@b0140000 { compatible = "sirf,prima2-efuse"; reg = <0xb0140000 0x10000>; + clocks = <&clks 22>; }; pulsec@b0150000 { compatible = "sirf,prima2-pulsec"; reg = <0xb0150000 0x10000>; interrupts = <48>; + clocks = <&clks 23>; }; pci-iobg { @@ -616,12 +642,14 @@ compatible = "chipidea,ci13611a-prima2"; reg = <0xb8000000 0x10000>; interrupts = <10>; + clocks = <&clks 40>; }; usb1: usb@b00f0000 { compatible = "chipidea,ci13611a-prima2"; reg = <0xb8010000 0x10000>; interrupts = <11>; + clocks = <&clks 41>; }; sata@b00f0000 { @@ -634,6 +662,7 @@ compatible = "sirf,prima2-security"; reg = <0xb8030000 0x10000>; interrupts = <42>; + clocks = <&clks 7>; }; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index e61fdd47bd0..f99f60dadf5 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -16,4 +16,34 @@ memory { reg = <0x40000000 0x80000000>; }; + + soc { + pinctrl@01c20800 { + compatible = "allwinner,sun4i-a10-pinctrl"; + reg = <0x01c20800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PB22", "PB23"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart1_pins_a: uart1@0 { + allwinner,pins = "PA10", "PA11"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 498a091a4ea..4a1e45d4aac 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -24,6 +24,8 @@ soc { uart1: uart@01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 59a2d265a98..e1121890fb2 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -17,4 +17,27 @@ memory { reg = <0x40000000 0x20000000>; }; + + soc { + pinctrl@01c20800 { + compatible = "allwinner,sun5i-a13-pinctrl"; + reg = <0x01c20800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + uart1_pins_a: uart1@0 { + allwinner,pins = "PE10", "PE11"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart1_pins_b: uart1@1 { + allwinner,pins = "PG3", "PG4"; + allwinner,function = "uart1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index a3d37ec2655..73187173117 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -70,7 +70,7 @@ compatible = "arm,sp805", "arm,primecell"; status = "disabled"; reg = <0 0x2b060000 0 0x1000>; - interrupts = <98>; + interrupts = <0 98 4>; clocks = <&oscclk7>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index cf8071ad22d..dfe371ec274 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -72,7 +72,7 @@ wdt@2a490000 { compatible = "arm,sp805", "arm,primecell"; reg = <0 0x2a490000 0 0x1000>; - interrupts = <98>; + interrupts = <0 98 4>; clocks = <&oscclk6a>, <&oscclk6a>; clock-names = "wdogclk", "apb_pclk"; }; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index d8645e990b2..cf31ced4660 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -45,6 +45,38 @@ compatible = "fixed-clock"; clock-frequency = <24000000>; }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <1>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <2>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <3>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <4>; + }; }; }; @@ -83,28 +115,28 @@ compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; - clocks = <&ref24>; + clocks = <&clkuart0>; }; uart@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; - clocks = <&ref24>; + clocks = <&clkuart1>; }; uart@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; - clocks = <&ref24>; + clocks = <&clkuart2>; }; uart@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; - clocks = <&ref24>; + clocks = <&clkuart3>; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index 330f833ac3b..e74a1c0fb9a 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -59,6 +59,54 @@ compatible = "fixed-clock"; clock-frequency = <24000000>; }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <1>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <2>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <3>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <4>; + }; + + clkuart4: uart4 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <22>; + }; + + clkuart5: uart5 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <23>; + }; }; }; @@ -96,42 +144,42 @@ compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; - clocks = <&ref24>; + clocks = <&clkuart0>; }; uart@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; - clocks = <&ref24>; + clocks = <&clkuart1>; }; uart@d8210000 { compatible = "via,vt8500-uart"; reg = <0xd8210000 0x1040>; interrupts = <47>; - clocks = <&ref24>; + clocks = <&clkuart2>; }; uart@d82c0000 { compatible = "via,vt8500-uart"; reg = <0xd82c0000 0x1040>; interrupts = <50>; - clocks = <&ref24>; + clocks = <&clkuart3>; }; uart@d8370000 { compatible = "via,vt8500-uart"; reg = <0xd8370000 0x1040>; interrupts = <31>; - clocks = <&ref24>; + clocks = <&clkuart4>; }; uart@d8380000 { compatible = "via,vt8500-uart"; reg = <0xd8380000 0x1040>; interrupts = <30>; - clocks = <&ref24>; + clocks = <&clkuart5>; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index 83b9467559b..db3c0a12e05 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -75,6 +75,22 @@ reg = <0x204>; }; + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <1>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x250>; + enable-bit = <2>; + }; + arm: arm { #clock-cells = <0>; compatible = "via,vt8500-device-clock"; @@ -128,14 +144,14 @@ compatible = "via,vt8500-uart"; reg = <0xd8200000 0x1040>; interrupts = <32>; - clocks = <&ref24>; + clocks = <&clkuart0>; }; uart@d82b0000 { compatible = "via,vt8500-uart"; reg = <0xd82b0000 0x1040>; interrupts = <33>; - clocks = <&ref24>; + clocks = <&clkuart1>; }; rtc@d8100000 { diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 401c1262d4e..5914b565459 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -44,14 +44,14 @@ compatible = "xlnx,xuartps"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; - clock = <50000000>; + clocks = <&uart_clk 0>; }; uart1: uart@e0001000 { compatible = "xlnx,xuartps"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; - clock = <50000000>; + clocks = <&uart_clk 1>; }; slcr: slcr@f8000000 { diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 45ceeb0e93e..9353184d730 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,26 +1,3 @@ -config ARM_GIC - bool - select IRQ_DOMAIN - select MULTI_IRQ_HANDLER - -config GIC_NON_BANKED - bool - -config ARM_VIC - bool - select IRQ_DOMAIN - select MULTI_IRQ_HANDLER - -config ARM_VIC_NR - int - default 4 if ARCH_S5PV210 - default 3 if ARCH_S5PC100 - default 2 - depends on ARM_VIC - help - The maximum number of VICs available in the system, for - power management. - config ICST bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e8a4e58f1b8..dc8dd0de5c0 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -2,8 +2,6 @@ # Makefile for the linux kernel. # -obj-$(CONFIG_ARM_GIC) += gic.o -obj-$(CONFIG_ARM_VIC) += vic.o obj-$(CONFIG_ICST) += icst.o obj-$(CONFIG_SA1111) += sa1111.o obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c deleted file mode 100644 index 36ae03a3f5d..00000000000 --- a/arch/arm/common/gic.c +++ /dev/null @@ -1,811 +0,0 @@ -/* - * linux/arch/arm/common/gic.c - * - * Copyright (C) 2002 ARM Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Interrupt architecture for the GIC: - * - * o There is one Interrupt Distributor, which receives interrupts - * from system devices and sends them to the Interrupt Controllers. - * - * o There is one CPU Interface per CPU, which sends interrupts sent - * by the Distributor, and interrupts generated locally, to the - * associated CPU. The base address of the CPU interface is usually - * aliased so that the same address points to different chips depending - * on the CPU it is accessed from. - * - * Note that IRQs 0-31 are special - they are local to each CPU. - * As such, the enable set/clear, pending set/clear and active bit - * registers are banked per-cpu for these sources. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/smp.h> -#include <linux/cpu_pm.h> -#include <linux/cpumask.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/irqdomain.h> -#include <linux/interrupt.h> -#include <linux/percpu.h> -#include <linux/slab.h> - -#include <asm/irq.h> -#include <asm/exception.h> -#include <asm/smp_plat.h> -#include <asm/mach/irq.h> -#include <asm/hardware/gic.h> - -union gic_base { - void __iomem *common_base; - void __percpu __iomem **percpu_base; -}; - -struct gic_chip_data { - union gic_base dist_base; - union gic_base cpu_base; -#ifdef CONFIG_CPU_PM - u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; - u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; - u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; - u32 __percpu *saved_ppi_enable; - u32 __percpu *saved_ppi_conf; -#endif - struct irq_domain *domain; - unsigned int gic_irqs; -#ifdef CONFIG_GIC_NON_BANKED - void __iomem *(*get_base)(union gic_base *); -#endif -}; - -static DEFINE_RAW_SPINLOCK(irq_controller_lock); - -/* - * The GIC mapping of CPU interfaces does not necessarily match - * the logical CPU numbering. Let's use a mapping as returned - * by the GIC itself. - */ -#define NR_GIC_CPU_IF 8 -static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; - -/* - * Supported arch specific GIC irq extension. - * Default make them NULL. - */ -struct irq_chip gic_arch_extn = { - .irq_eoi = NULL, - .irq_mask = NULL, - .irq_unmask = NULL, - .irq_retrigger = NULL, - .irq_set_type = NULL, - .irq_set_wake = NULL, -}; - -#ifndef MAX_GIC_NR -#define MAX_GIC_NR 1 -#endif - -static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; - -#ifdef CONFIG_GIC_NON_BANKED -static void __iomem *gic_get_percpu_base(union gic_base *base) -{ - return *__this_cpu_ptr(base->percpu_base); -} - -static void __iomem *gic_get_common_base(union gic_base *base) -{ - return base->common_base; -} - -static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) -{ - return data->get_base(&data->dist_base); -} - -static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) -{ - return data->get_base(&data->cpu_base); -} - -static inline void gic_set_base_accessor(struct gic_chip_data *data, - void __iomem *(*f)(union gic_base *)) -{ - data->get_base = f; -} -#else -#define gic_data_dist_base(d) ((d)->dist_base.common_base) -#define gic_data_cpu_base(d) ((d)->cpu_base.common_base) -#define gic_set_base_accessor(d,f) -#endif - -static inline void __iomem *gic_dist_base(struct irq_data *d) -{ - struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); - return gic_data_dist_base(gic_data); -} - -static inline void __iomem *gic_cpu_base(struct irq_data *d) -{ - struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); - return gic_data_cpu_base(gic_data); -} - -static inline unsigned int gic_irq(struct irq_data *d) -{ - return d->hwirq; -} - -/* - * Routines to acknowledge, disable and enable interrupts - */ -static void gic_mask_irq(struct irq_data *d) -{ - u32 mask = 1 << (gic_irq(d) % 32); - - raw_spin_lock(&irq_controller_lock); - writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); - if (gic_arch_extn.irq_mask) - gic_arch_extn.irq_mask(d); - raw_spin_unlock(&irq_controller_lock); -} - -static void gic_unmask_irq(struct irq_data *d) -{ - u32 mask = 1 << (gic_irq(d) % 32); - - raw_spin_lock(&irq_controller_lock); - if (gic_arch_extn.irq_unmask) - gic_arch_extn.irq_unmask(d); - writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); - raw_spin_unlock(&irq_controller_lock); -} - -static void gic_eoi_irq(struct irq_data *d) -{ - if (gic_arch_extn.irq_eoi) { - raw_spin_lock(&irq_controller_lock); - gic_arch_extn.irq_eoi(d); - raw_spin_unlock(&irq_controller_lock); - } - - writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); -} - -static int gic_set_type(struct irq_data *d, unsigned int type) -{ - void __iomem *base = gic_dist_base(d); - unsigned int gicirq = gic_irq(d); - u32 enablemask = 1 << (gicirq % 32); - u32 enableoff = (gicirq / 32) * 4; - u32 confmask = 0x2 << ((gicirq % 16) * 2); - u32 confoff = (gicirq / 16) * 4; - bool enabled = false; - u32 val; - - /* Interrupt configuration for SGIs can't be changed */ - if (gicirq < 16) - return -EINVAL; - - if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) - return -EINVAL; - - raw_spin_lock(&irq_controller_lock); - - if (gic_arch_extn.irq_set_type) - gic_arch_extn.irq_set_type(d, type); - - val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); - if (type == IRQ_TYPE_LEVEL_HIGH) - val &= ~confmask; - else if (type == IRQ_TYPE_EDGE_RISING) - val |= confmask; - - /* - * As recommended by the spec, disable the interrupt before changing - * the configuration - */ - if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { - writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); - enabled = true; - } - - writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); - - if (enabled) - writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); - - raw_spin_unlock(&irq_controller_lock); - - return 0; -} - -static int gic_retrigger(struct irq_data *d) -{ - if (gic_arch_extn.irq_retrigger) - return gic_arch_extn.irq_retrigger(d); - - return -ENXIO; -} - -#ifdef CONFIG_SMP -static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, - bool force) -{ - void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); - unsigned int shift = (gic_irq(d) % 4) * 8; - unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); - u32 val, mask, bit; - - if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) - return -EINVAL; - - mask = 0xff << shift; - bit = gic_cpu_map[cpu] << shift; - - raw_spin_lock(&irq_controller_lock); - val = readl_relaxed(reg) & ~mask; - writel_relaxed(val | bit, reg); - raw_spin_unlock(&irq_controller_lock); - - return IRQ_SET_MASK_OK; -} -#endif - -#ifdef CONFIG_PM -static int gic_set_wake(struct irq_data *d, unsigned int on) -{ - int ret = -ENXIO; - - if (gic_arch_extn.irq_set_wake) - ret = gic_arch_extn.irq_set_wake(d, on); - - return ret; -} - -#else -#define gic_set_wake NULL -#endif - -asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) -{ - u32 irqstat, irqnr; - struct gic_chip_data *gic = &gic_data[0]; - void __iomem *cpu_base = gic_data_cpu_base(gic); - - do { - irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); - irqnr = irqstat & ~0x1c00; - - if (likely(irqnr > 15 && irqnr < 1021)) { - irqnr = irq_find_mapping(gic->domain, irqnr); - handle_IRQ(irqnr, regs); - continue; - } - if (irqnr < 16) { - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); -#ifdef CONFIG_SMP - handle_IPI(irqnr, regs); -#endif - continue; - } - break; - } while (1); -} - -static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) -{ - struct gic_chip_data *chip_data = irq_get_handler_data(irq); - struct irq_chip *chip = irq_get_chip(irq); - unsigned int cascade_irq, gic_irq; - unsigned long status; - - chained_irq_enter(chip, desc); - - raw_spin_lock(&irq_controller_lock); - status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); - raw_spin_unlock(&irq_controller_lock); - - gic_irq = (status & 0x3ff); - if (gic_irq == 1023) - goto out; - - cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); - if (unlikely(gic_irq < 32 || gic_irq > 1020)) - do_bad_IRQ(cascade_irq, desc); - else - generic_handle_irq(cascade_irq); - - out: - chained_irq_exit(chip, desc); -} - -static struct irq_chip gic_chip = { - .name = "GIC", - .irq_mask = gic_mask_irq, - .irq_unmask = gic_unmask_irq, - .irq_eoi = gic_eoi_irq, - .irq_set_type = gic_set_type, - .irq_retrigger = gic_retrigger, -#ifdef CONFIG_SMP - .irq_set_affinity = gic_set_affinity, -#endif - .irq_set_wake = gic_set_wake, -}; - -void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) -{ - if (gic_nr >= MAX_GIC_NR) - BUG(); - if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) - BUG(); - irq_set_chained_handler(irq, gic_handle_cascade_irq); -} - -static void __init gic_dist_init(struct gic_chip_data *gic) -{ - unsigned int i; - u32 cpumask; - unsigned int gic_irqs = gic->gic_irqs; - void __iomem *base = gic_data_dist_base(gic); - - writel_relaxed(0, base + GIC_DIST_CTRL); - - /* - * Set all global interrupts to be level triggered, active low. - */ - for (i = 32; i < gic_irqs; i += 16) - writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); - - /* - * Set all global interrupts to this CPU only. - */ - cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0); - for (i = 32; i < gic_irqs; i += 4) - writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); - - /* - * Set priority on all global interrupts. - */ - for (i = 32; i < gic_irqs; i += 4) - writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); - - /* - * Disable all interrupts. Leave the PPI and SGIs alone - * as these enables are banked registers. - */ - for (i = 32; i < gic_irqs; i += 32) - writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); - - writel_relaxed(1, base + GIC_DIST_CTRL); -} - -static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) -{ - void __iomem *dist_base = gic_data_dist_base(gic); - void __iomem *base = gic_data_cpu_base(gic); - unsigned int cpu_mask, cpu = smp_processor_id(); - int i; - - /* - * Get what the GIC says our CPU mask is. - */ - BUG_ON(cpu >= NR_GIC_CPU_IF); - cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0); - gic_cpu_map[cpu] = cpu_mask; - - /* - * Clear our mask from the other map entries in case they're - * still undefined. - */ - for (i = 0; i < NR_GIC_CPU_IF; i++) - if (i != cpu) - gic_cpu_map[i] &= ~cpu_mask; - - /* - * Deal with the banked PPI and SGI interrupts - disable all - * PPI interrupts, ensure all SGI interrupts are enabled. - */ - writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); - writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); - - /* - * Set priority on PPI and SGI interrupts - */ - for (i = 0; i < 32; i += 4) - writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); - - writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); - writel_relaxed(1, base + GIC_CPU_CTRL); -} - -#ifdef CONFIG_CPU_PM -/* - * Saves the GIC distributor registers during suspend or idle. Must be called - * with interrupts disabled but before powering down the GIC. After calling - * this function, no interrupts will be delivered by the GIC, and another - * platform-specific wakeup source must be enabled. - */ -static void gic_dist_save(unsigned int gic_nr) -{ - unsigned int gic_irqs; - void __iomem *dist_base; - int i; - - if (gic_nr >= MAX_GIC_NR) - BUG(); - - gic_irqs = gic_data[gic_nr].gic_irqs; - dist_base = gic_data_dist_base(&gic_data[gic_nr]); - - if (!dist_base) - return; - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) - gic_data[gic_nr].saved_spi_conf[i] = - readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) - gic_data[gic_nr].saved_spi_target[i] = - readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) - gic_data[gic_nr].saved_spi_enable[i] = - readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); -} - -/* - * Restores the GIC distributor registers during resume or when coming out of - * idle. Must be called before enabling interrupts. If a level interrupt - * that occured while the GIC was suspended is still present, it will be - * handled normally, but any edge interrupts that occured will not be seen by - * the GIC and need to be handled by the platform-specific wakeup source. - */ -static void gic_dist_restore(unsigned int gic_nr) -{ - unsigned int gic_irqs; - unsigned int i; - void __iomem *dist_base; - - if (gic_nr >= MAX_GIC_NR) - BUG(); - - gic_irqs = gic_data[gic_nr].gic_irqs; - dist_base = gic_data_dist_base(&gic_data[gic_nr]); - - if (!dist_base) - return; - - writel_relaxed(0, dist_base + GIC_DIST_CTRL); - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) - writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], - dist_base + GIC_DIST_CONFIG + i * 4); - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) - writel_relaxed(0xa0a0a0a0, - dist_base + GIC_DIST_PRI + i * 4); - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) - writel_relaxed(gic_data[gic_nr].saved_spi_target[i], - dist_base + GIC_DIST_TARGET + i * 4); - - for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) - writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], - dist_base + GIC_DIST_ENABLE_SET + i * 4); - - writel_relaxed(1, dist_base + GIC_DIST_CTRL); -} - -static void gic_cpu_save(unsigned int gic_nr) -{ - int i; - u32 *ptr; - void __iomem *dist_base; - void __iomem *cpu_base; - - if (gic_nr >= MAX_GIC_NR) - BUG(); - - dist_base = gic_data_dist_base(&gic_data[gic_nr]); - cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); - - if (!dist_base || !cpu_base) - return; - - ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); - for (i = 0; i < DIV_ROUND_UP(32, 32); i++) - ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); - - ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); - for (i = 0; i < DIV_ROUND_UP(32, 16); i++) - ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); - -} - -static void gic_cpu_restore(unsigned int gic_nr) -{ - int i; - u32 *ptr; - void __iomem *dist_base; - void __iomem *cpu_base; - - if (gic_nr >= MAX_GIC_NR) - BUG(); - - dist_base = gic_data_dist_base(&gic_data[gic_nr]); - cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); - - if (!dist_base || !cpu_base) - return; - - ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); - for (i = 0; i < DIV_ROUND_UP(32, 32); i++) - writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); - - ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); - for (i = 0; i < DIV_ROUND_UP(32, 16); i++) - writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); - - for (i = 0; i < DIV_ROUND_UP(32, 4); i++) - writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); - - writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); - writel_relaxed(1, cpu_base + GIC_CPU_CTRL); -} - -static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) -{ - int i; - - for (i = 0; i < MAX_GIC_NR; i++) { -#ifdef CONFIG_GIC_NON_BANKED - /* Skip over unused GICs */ - if (!gic_data[i].get_base) - continue; -#endif - switch (cmd) { - case CPU_PM_ENTER: - gic_cpu_save(i); - break; - case CPU_PM_ENTER_FAILED: - case CPU_PM_EXIT: - gic_cpu_restore(i); - break; - case CPU_CLUSTER_PM_ENTER: - gic_dist_save(i); - break; - case CPU_CLUSTER_PM_ENTER_FAILED: - case CPU_CLUSTER_PM_EXIT: - gic_dist_restore(i); - break; - } - } - - return NOTIFY_OK; -} - -static struct notifier_block gic_notifier_block = { - .notifier_call = gic_notifier, -}; - -static void __init gic_pm_init(struct gic_chip_data *gic) -{ - gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, - sizeof(u32)); - BUG_ON(!gic->saved_ppi_enable); - - gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, - sizeof(u32)); - BUG_ON(!gic->saved_ppi_conf); - - if (gic == &gic_data[0]) - cpu_pm_register_notifier(&gic_notifier_block); -} -#else -static void __init gic_pm_init(struct gic_chip_data *gic) -{ -} -#endif - -static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - if (hw < 32) { - irq_set_percpu_devid(irq); - irq_set_chip_and_handler(irq, &gic_chip, - handle_percpu_devid_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); - } else { - irq_set_chip_and_handler(irq, &gic_chip, - handle_fasteoi_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - irq_set_chip_data(irq, d->host_data); - return 0; -} - -static int gic_irq_domain_xlate(struct irq_domain *d, - struct device_node *controller, - const u32 *intspec, unsigned int intsize, - unsigned long *out_hwirq, unsigned int *out_type) -{ - if (d->of_node != controller) - return -EINVAL; - if (intsize < 3) - return -EINVAL; - - /* Get the interrupt number and add 16 to skip over SGIs */ - *out_hwirq = intspec[1] + 16; - - /* For SPIs, we need to add 16 more to get the GIC irq ID number */ - if (!intspec[0]) - *out_hwirq += 16; - - *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; - return 0; -} - -const struct irq_domain_ops gic_irq_domain_ops = { - .map = gic_irq_domain_map, - .xlate = gic_irq_domain_xlate, -}; - -void __init gic_init_bases(unsigned int gic_nr, int irq_start, - void __iomem *dist_base, void __iomem *cpu_base, - u32 percpu_offset, struct device_node *node) -{ - irq_hw_number_t hwirq_base; - struct gic_chip_data *gic; - int gic_irqs, irq_base, i; - - BUG_ON(gic_nr >= MAX_GIC_NR); - - gic = &gic_data[gic_nr]; -#ifdef CONFIG_GIC_NON_BANKED - if (percpu_offset) { /* Frankein-GIC without banked registers... */ - unsigned int cpu; - - gic->dist_base.percpu_base = alloc_percpu(void __iomem *); - gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); - if (WARN_ON(!gic->dist_base.percpu_base || - !gic->cpu_base.percpu_base)) { - free_percpu(gic->dist_base.percpu_base); - free_percpu(gic->cpu_base.percpu_base); - return; - } - - for_each_possible_cpu(cpu) { - unsigned long offset = percpu_offset * cpu_logical_map(cpu); - *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; - *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; - } - - gic_set_base_accessor(gic, gic_get_percpu_base); - } else -#endif - { /* Normal, sane GIC... */ - WARN(percpu_offset, - "GIC_NON_BANKED not enabled, ignoring %08x offset!", - percpu_offset); - gic->dist_base.common_base = dist_base; - gic->cpu_base.common_base = cpu_base; - gic_set_base_accessor(gic, gic_get_common_base); - } - - /* - * Initialize the CPU interface map to all CPUs. - * It will be refined as each CPU probes its ID. - */ - for (i = 0; i < NR_GIC_CPU_IF; i++) - gic_cpu_map[i] = 0xff; - - /* - * For primary GICs, skip over SGIs. - * For secondary GICs, skip over PPIs, too. - */ - if (gic_nr == 0 && (irq_start & 31) > 0) { - hwirq_base = 16; - if (irq_start != -1) - irq_start = (irq_start & ~31) + 16; - } else { - hwirq_base = 32; - } - - /* - * Find out how many interrupts are supported. - * The GIC only supports up to 1020 interrupt sources. - */ - gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; - gic_irqs = (gic_irqs + 1) * 32; - if (gic_irqs > 1020) - gic_irqs = 1020; - gic->gic_irqs = gic_irqs; - - gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ - irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id()); - if (IS_ERR_VALUE(irq_base)) { - WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", - irq_start); - irq_base = irq_start; - } - gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, - hwirq_base, &gic_irq_domain_ops, gic); - if (WARN_ON(!gic->domain)) - return; - - gic_chip.flags |= gic_arch_extn.flags; - gic_dist_init(gic); - gic_cpu_init(gic); - gic_pm_init(gic); -} - -void __cpuinit gic_secondary_init(unsigned int gic_nr) -{ - BUG_ON(gic_nr >= MAX_GIC_NR); - - gic_cpu_init(&gic_data[gic_nr]); -} - -#ifdef CONFIG_SMP -void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) -{ - int cpu; - unsigned long map = 0; - - /* Convert our logical CPU mask into a physical one. */ - for_each_cpu(cpu, mask) - map |= gic_cpu_map[cpu]; - - /* - * Ensure that stores to Normal memory are visible to the - * other CPUs before issuing the IPI. - */ - dsb(); - - /* this always happens on GIC0 */ - writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); -} -#endif - -#ifdef CONFIG_OF -static int gic_cnt __initdata = 0; - -int __init gic_of_init(struct device_node *node, struct device_node *parent) -{ - void __iomem *cpu_base; - void __iomem *dist_base; - u32 percpu_offset; - int irq; - - if (WARN_ON(!node)) - return -ENODEV; - - dist_base = of_iomap(node, 0); - WARN(!dist_base, "unable to map gic dist registers\n"); - - cpu_base = of_iomap(node, 1); - WARN(!cpu_base, "unable to map gic cpu registers\n"); - - if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) - percpu_offset = 0; - - gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); - - if (parent) { - irq = irq_of_parse_and_map(node, 0); - gic_cascade_irq(gic_cnt, irq); - } - gic_cnt++; - return 0; -} -#endif diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c deleted file mode 100644 index 8f324b99416..00000000000 --- a/arch/arm/common/vic.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * linux/arch/arm/common/vic.c - * - * Copyright (C) 1999 - 2003 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/export.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/io.h> -#include <linux/irqdomain.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/syscore_ops.h> -#include <linux/device.h> -#include <linux/amba/bus.h> - -#include <asm/exception.h> -#include <asm/mach/irq.h> -#include <asm/hardware/vic.h> - -/** - * struct vic_device - VIC PM device - * @irq: The IRQ number for the base of the VIC. - * @base: The register base for the VIC. - * @valid_sources: A bitmask of valid interrupts - * @resume_sources: A bitmask of interrupts for resume. - * @resume_irqs: The IRQs enabled for resume. - * @int_select: Save for VIC_INT_SELECT. - * @int_enable: Save for VIC_INT_ENABLE. - * @soft_int: Save for VIC_INT_SOFT. - * @protect: Save for VIC_PROTECT. - * @domain: The IRQ domain for the VIC. - */ -struct vic_device { - void __iomem *base; - int irq; - u32 valid_sources; - u32 resume_sources; - u32 resume_irqs; - u32 int_select; - u32 int_enable; - u32 soft_int; - u32 protect; - struct irq_domain *domain; -}; - -/* we cannot allocate memory when VICs are initially registered */ -static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; - -static int vic_id; - -/** - * vic_init2 - common initialisation code - * @base: Base of the VIC. - * - * Common initialisation code for registration - * and resume. -*/ -static void vic_init2(void __iomem *base) -{ - int i; - - for (i = 0; i < 16; i++) { - void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); - writel(VIC_VECT_CNTL_ENABLE | i, reg); - } - - writel(32, base + VIC_PL190_DEF_VECT_ADDR); -} - -#ifdef CONFIG_PM -static void resume_one_vic(struct vic_device *vic) -{ - void __iomem *base = vic->base; - - printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); - - /* re-initialise static settings */ - vic_init2(base); - - writel(vic->int_select, base + VIC_INT_SELECT); - writel(vic->protect, base + VIC_PROTECT); - - /* set the enabled ints and then clear the non-enabled */ - writel(vic->int_enable, base + VIC_INT_ENABLE); - writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); - - /* and the same for the soft-int register */ - - writel(vic->soft_int, base + VIC_INT_SOFT); - writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); -} - -static void vic_resume(void) -{ - int id; - - for (id = vic_id - 1; id >= 0; id--) - resume_one_vic(vic_devices + id); -} - -static void suspend_one_vic(struct vic_device *vic) -{ - void __iomem *base = vic->base; - - printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); - - vic->int_select = readl(base + VIC_INT_SELECT); - vic->int_enable = readl(base + VIC_INT_ENABLE); - vic->soft_int = readl(base + VIC_INT_SOFT); - vic->protect = readl(base + VIC_PROTECT); - - /* set the interrupts (if any) that are used for - * resuming the system */ - - writel(vic->resume_irqs, base + VIC_INT_ENABLE); - writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); -} - -static int vic_suspend(void) -{ - int id; - - for (id = 0; id < vic_id; id++) - suspend_one_vic(vic_devices + id); - - return 0; -} - -struct syscore_ops vic_syscore_ops = { - .suspend = vic_suspend, - .resume = vic_resume, -}; - -/** - * vic_pm_init - initicall to register VIC pm - * - * This is called via late_initcall() to register - * the resources for the VICs due to the early - * nature of the VIC's registration. -*/ -static int __init vic_pm_init(void) -{ - if (vic_id > 0) - register_syscore_ops(&vic_syscore_ops); - - return 0; -} -late_initcall(vic_pm_init); -#endif /* CONFIG_PM */ - -static struct irq_chip vic_chip; - -static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct vic_device *v = d->host_data; - - /* Skip invalid IRQs, only register handlers for the real ones */ - if (!(v->valid_sources & (1 << hwirq))) - return -ENOTSUPP; - irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq); - irq_set_chip_data(irq, v->base); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - return 0; -} - -static struct irq_domain_ops vic_irqdomain_ops = { - .map = vic_irqdomain_map, - .xlate = irq_domain_xlate_onetwocell, -}; - -/** - * vic_register() - Register a VIC. - * @base: The base address of the VIC. - * @irq: The base IRQ for the VIC. - * @valid_sources: bitmask of valid interrupts - * @resume_sources: bitmask of interrupts allowed for resume sources. - * @node: The device tree node associated with the VIC. - * - * Register the VIC with the system device tree so that it can be notified - * of suspend and resume requests and ensure that the correct actions are - * taken to re-instate the settings on resume. - * - * This also configures the IRQ domain for the VIC. - */ -static void __init vic_register(void __iomem *base, unsigned int irq, - u32 valid_sources, u32 resume_sources, - struct device_node *node) -{ - struct vic_device *v; - int i; - - if (vic_id >= ARRAY_SIZE(vic_devices)) { - printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); - return; - } - - v = &vic_devices[vic_id]; - v->base = base; - v->valid_sources = valid_sources; - v->resume_sources = resume_sources; - v->irq = irq; - vic_id++; - v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, - &vic_irqdomain_ops, v); - /* create an IRQ mapping for each valid IRQ */ - for (i = 0; i < fls(valid_sources); i++) - if (valid_sources & (1 << i)) - irq_create_mapping(v->domain, i); -} - -static void vic_ack_irq(struct irq_data *d) -{ - void __iomem *base = irq_data_get_irq_chip_data(d); - unsigned int irq = d->hwirq; - writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); - /* moreover, clear the soft-triggered, in case it was the reason */ - writel(1 << irq, base + VIC_INT_SOFT_CLEAR); -} - -static void vic_mask_irq(struct irq_data *d) -{ - void __iomem *base = irq_data_get_irq_chip_data(d); - unsigned int irq = d->hwirq; - writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); -} - -static void vic_unmask_irq(struct irq_data *d) -{ - void __iomem *base = irq_data_get_irq_chip_data(d); - unsigned int irq = d->hwirq; - writel(1 << irq, base + VIC_INT_ENABLE); -} - -#if defined(CONFIG_PM) -static struct vic_device *vic_from_irq(unsigned int irq) -{ - struct vic_device *v = vic_devices; - unsigned int base_irq = irq & ~31; - int id; - - for (id = 0; id < vic_id; id++, v++) { - if (v->irq == base_irq) - return v; - } - - return NULL; -} - -static int vic_set_wake(struct irq_data *d, unsigned int on) -{ - struct vic_device *v = vic_from_irq(d->irq); - unsigned int off = d->hwirq; - u32 bit = 1 << off; - - if (!v) - return -EINVAL; - - if (!(bit & v->resume_sources)) - return -EINVAL; - - if (on) - v->resume_irqs |= bit; - else - v->resume_irqs &= ~bit; - - return 0; -} -#else -#define vic_set_wake NULL -#endif /* CONFIG_PM */ - -static struct irq_chip vic_chip = { - .name = "VIC", - .irq_ack = vic_ack_irq, - .irq_mask = vic_mask_irq, - .irq_unmask = vic_unmask_irq, - .irq_set_wake = vic_set_wake, -}; - -static void __init vic_disable(void __iomem *base) -{ - writel(0, base + VIC_INT_SELECT); - writel(0, base + VIC_INT_ENABLE); - writel(~0, base + VIC_INT_ENABLE_CLEAR); - writel(0, base + VIC_ITCR); - writel(~0, base + VIC_INT_SOFT_CLEAR); -} - -static void __init vic_clear_interrupts(void __iomem *base) -{ - unsigned int i; - - writel(0, base + VIC_PL190_VECT_ADDR); - for (i = 0; i < 19; i++) { - unsigned int value; - - value = readl(base + VIC_PL190_VECT_ADDR); - writel(value, base + VIC_PL190_VECT_ADDR); - } -} - -/* - * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. - * The original cell has 32 interrupts, while the modified one has 64, - * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case - * the probe function is called twice, with base set to offset 000 - * and 020 within the page. We call this "second block". - */ -static void __init vic_init_st(void __iomem *base, unsigned int irq_start, - u32 vic_sources, struct device_node *node) -{ - unsigned int i; - int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; - - /* Disable all interrupts initially. */ - vic_disable(base); - - /* - * Make sure we clear all existing interrupts. The vector registers - * in this cell are after the second block of general registers, - * so we can address them using standard offsets, but only from - * the second base address, which is 0x20 in the page - */ - if (vic_2nd_block) { - vic_clear_interrupts(base); - - /* ST has 16 vectors as well, but we don't enable them by now */ - for (i = 0; i < 16; i++) { - void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); - writel(0, reg); - } - - writel(32, base + VIC_PL190_DEF_VECT_ADDR); - } - - vic_register(base, irq_start, vic_sources, 0, node); -} - -void __init __vic_init(void __iomem *base, int irq_start, - u32 vic_sources, u32 resume_sources, - struct device_node *node) -{ - unsigned int i; - u32 cellid = 0; - enum amba_vendor vendor; - - /* Identify which VIC cell this one is, by reading the ID */ - for (i = 0; i < 4; i++) { - void __iomem *addr; - addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); - cellid |= (readl(addr) & 0xff) << (8 * i); - } - vendor = (cellid >> 12) & 0xff; - printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n", - base, cellid, vendor); - - switch(vendor) { - case AMBA_VENDOR_ST: - vic_init_st(base, irq_start, vic_sources, node); - return; - default: - printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n"); - /* fall through */ - case AMBA_VENDOR_ARM: - break; - } - - /* Disable all interrupts initially. */ - vic_disable(base); - - /* Make sure we clear all existing interrupts */ - vic_clear_interrupts(base); - - vic_init2(base); - - vic_register(base, irq_start, vic_sources, resume_sources, node); -} - -/** - * vic_init() - initialise a vectored interrupt controller - * @base: iomem base address - * @irq_start: starting interrupt number, must be muliple of 32 - * @vic_sources: bitmask of interrupt sources to allow - * @resume_sources: bitmask of interrupt sources to allow for resume - */ -void __init vic_init(void __iomem *base, unsigned int irq_start, - u32 vic_sources, u32 resume_sources) -{ - __vic_init(base, irq_start, vic_sources, resume_sources, NULL); -} - -#ifdef CONFIG_OF -int __init vic_of_init(struct device_node *node, struct device_node *parent) -{ - void __iomem *regs; - - if (WARN(parent, "non-root VICs are not supported")) - return -EINVAL; - - regs = of_iomap(node, 0); - if (WARN_ON(!regs)) - return -EIO; - - /* - * Passing 0 as first IRQ makes the simple domain allocate descriptors - */ - __vic_init(regs, 0, ~0, ~0, node); - - return 0; -} -#endif /* CONFIG OF */ - -/* - * Handle each interrupt in a single VIC. Returns non-zero if we've - * handled at least one interrupt. This reads the status register - * before handling each interrupt, which is necessary given that - * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. - */ -static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) -{ - u32 stat, irq; - int handled = 0; - - while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { - irq = ffs(stat) - 1; - handle_IRQ(irq_find_mapping(vic->domain, irq), regs); - handled = 1; - } - - return handled; -} - -/* - * Keep iterating over all registered VIC's until there are no pending - * interrupts. - */ -asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs) -{ - int i, handled; - - do { - for (i = 0, handled = 0; i < vic_id; ++i) - handled |= handle_one_vic(&vic_devices[i], regs); - } while (handled); -} diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig index c5212f43eee..36fed66bd4b 100644 --- a/arch/arm/configs/at91sam9263_defconfig +++ b/arch/arm/configs/at91sam9263_defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9263=y CONFIG_MACH_AT91SAM9263EK=y CONFIG_MACH_USB_A9263=y -CONFIG_MACH_NEOCORE926=y CONFIG_MTD_AT91_DATAFLASH_CARD=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 69667133321..6dddbf877b0 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -32,7 +32,6 @@ CONFIG_MACH_PCM043=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_VPR200=y CONFIG_MACH_IMX51_DT=y -CONFIG_MACH_MX51_3DS=y CONFIG_MACH_EUKREA_CPUIMX51SD=y CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index 728a43c446f..afb17d630d4 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig @@ -83,7 +83,6 @@ CONFIG_USB=y CONFIG_USB_RCAR_PHY=y CONFIG_MMC=y CONFIG_MMC_SDHI=y -CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index b5bc96cb65a..cbd91bce1ca 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -33,6 +33,8 @@ CONFIG_MVNETA=y CONFIG_MARVELL_PHY=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_MV64XXX=y CONFIG_SERIAL_8250_DW=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig index caa07db90cf..e319b2c56f1 100644 --- a/arch/arm/configs/shark_defconfig +++ b/arch/arm/configs/shark_defconfig @@ -73,7 +73,6 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_ISO8859_1=m -# CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 231dca60473..426270fe080 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -66,9 +66,9 @@ CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_TC3589X=y -CONFIG_POWER_SUPPLY=y -CONFIG_AB8500_BM=y -CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y +# CONFIG_POWER_SUPPLY is not set +# CONFIG_AB8500_BM is not set +# CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL is not set CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_MFD_STMPE=y diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S index e59b1d505d6..19d6cd6f29f 100644 --- a/arch/arm/crypto/aes-armv4.S +++ b/arch/arm/crypto/aes-armv4.S @@ -34,8 +34,9 @@ @ A little glue here to select the correct code below for the ARM CPU @ that is being targetted. +#include <linux/linkage.h> + .text -.code 32 .type AES_Te,%object .align 5 @@ -145,10 +146,8 @@ AES_Te: @ void AES_encrypt(const unsigned char *in, unsigned char *out, @ const AES_KEY *key) { -.global AES_encrypt -.type AES_encrypt,%function .align 5 -AES_encrypt: +ENTRY(AES_encrypt) sub r3,pc,#8 @ AES_encrypt stmdb sp!,{r1,r4-r12,lr} mov r12,r0 @ inp @@ -239,15 +238,8 @@ AES_encrypt: strb r6,[r12,#14] strb r3,[r12,#15] #endif -#if __ARM_ARCH__>=5 ldmia sp!,{r4-r12,pc} -#else - ldmia sp!,{r4-r12,lr} - tst lr,#1 - moveq pc,lr @ be binary compatible with V4, yet - .word 0xe12fff1e @ interoperable with Thumb ISA:-) -#endif -.size AES_encrypt,.-AES_encrypt +ENDPROC(AES_encrypt) .type _armv4_AES_encrypt,%function .align 2 @@ -386,10 +378,8 @@ _armv4_AES_encrypt: ldr pc,[sp],#4 @ pop and return .size _armv4_AES_encrypt,.-_armv4_AES_encrypt -.global private_AES_set_encrypt_key -.type private_AES_set_encrypt_key,%function .align 5 -private_AES_set_encrypt_key: +ENTRY(private_AES_set_encrypt_key) _armv4_AES_set_encrypt_key: sub r3,pc,#8 @ AES_set_encrypt_key teq r0,#0 @@ -658,15 +648,11 @@ _armv4_AES_set_encrypt_key: .Ldone: mov r0,#0 ldmia sp!,{r4-r12,lr} -.Labrt: tst lr,#1 - moveq pc,lr @ be binary compatible with V4, yet - .word 0xe12fff1e @ interoperable with Thumb ISA:-) -.size private_AES_set_encrypt_key,.-private_AES_set_encrypt_key +.Labrt: mov pc,lr +ENDPROC(private_AES_set_encrypt_key) -.global private_AES_set_decrypt_key -.type private_AES_set_decrypt_key,%function .align 5 -private_AES_set_decrypt_key: +ENTRY(private_AES_set_decrypt_key) str lr,[sp,#-4]! @ push lr #if 0 @ kernel does both of these in setkey so optimise this bit out by @@ -748,15 +734,8 @@ private_AES_set_decrypt_key: bne .Lmix mov r0,#0 -#if __ARM_ARCH__>=5 ldmia sp!,{r4-r12,pc} -#else - ldmia sp!,{r4-r12,lr} - tst lr,#1 - moveq pc,lr @ be binary compatible with V4, yet - .word 0xe12fff1e @ interoperable with Thumb ISA:-) -#endif -.size private_AES_set_decrypt_key,.-private_AES_set_decrypt_key +ENDPROC(private_AES_set_decrypt_key) .type AES_Td,%object .align 5 @@ -862,10 +841,8 @@ AES_Td: @ void AES_decrypt(const unsigned char *in, unsigned char *out, @ const AES_KEY *key) { -.global AES_decrypt -.type AES_decrypt,%function .align 5 -AES_decrypt: +ENTRY(AES_decrypt) sub r3,pc,#8 @ AES_decrypt stmdb sp!,{r1,r4-r12,lr} mov r12,r0 @ inp @@ -956,15 +933,8 @@ AES_decrypt: strb r6,[r12,#14] strb r3,[r12,#15] #endif -#if __ARM_ARCH__>=5 ldmia sp!,{r4-r12,pc} -#else - ldmia sp!,{r4-r12,lr} - tst lr,#1 - moveq pc,lr @ be binary compatible with V4, yet - .word 0xe12fff1e @ interoperable with Thumb ISA:-) -#endif -.size AES_decrypt,.-AES_decrypt +ENDPROC(AES_decrypt) .type _armv4_AES_decrypt,%function .align 2 @@ -1064,7 +1034,9 @@ _armv4_AES_decrypt: and r9,lr,r1,lsr#8 ldrb r7,[r10,r7] @ Td4[s1>>0] - ldrb r1,[r10,r1,lsr#24] @ Td4[s1>>24] + ARM( ldrb r1,[r10,r1,lsr#24] ) @ Td4[s1>>24] + THUMB( add r1,r10,r1,lsr#24 ) @ Td4[s1>>24] + THUMB( ldrb r1,[r1] ) ldrb r8,[r10,r8] @ Td4[s1>>16] eor r0,r7,r0,lsl#24 ldrb r9,[r10,r9] @ Td4[s1>>8] @@ -1077,7 +1049,9 @@ _armv4_AES_decrypt: ldrb r8,[r10,r8] @ Td4[s2>>0] and r9,lr,r2,lsr#16 - ldrb r2,[r10,r2,lsr#24] @ Td4[s2>>24] + ARM( ldrb r2,[r10,r2,lsr#24] ) @ Td4[s2>>24] + THUMB( add r2,r10,r2,lsr#24 ) @ Td4[s2>>24] + THUMB( ldrb r2,[r2] ) eor r0,r0,r7,lsl#8 ldrb r9,[r10,r9] @ Td4[s2>>16] eor r1,r8,r1,lsl#16 @@ -1090,7 +1064,9 @@ _armv4_AES_decrypt: and r9,lr,r3 @ i2 ldrb r9,[r10,r9] @ Td4[s3>>0] - ldrb r3,[r10,r3,lsr#24] @ Td4[s3>>24] + ARM( ldrb r3,[r10,r3,lsr#24] ) @ Td4[s3>>24] + THUMB( add r3,r10,r3,lsr#24 ) @ Td4[s3>>24] + THUMB( ldrb r3,[r3] ) eor r0,r0,r7,lsl#16 ldr r7,[r11,#0] eor r1,r1,r8,lsl#8 diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S index 7050ab133b9..92c6eed7aac 100644 --- a/arch/arm/crypto/sha1-armv4-large.S +++ b/arch/arm/crypto/sha1-armv4-large.S @@ -51,13 +51,12 @@ @ Profiler-assisted and platform-specific optimization resulted in 10% @ improvement on Cortex A8 core and 12.2 cycles per byte. -.text +#include <linux/linkage.h> -.global sha1_block_data_order -.type sha1_block_data_order,%function +.text .align 2 -sha1_block_data_order: +ENTRY(sha1_block_data_order) stmdb sp!,{r4-r12,lr} add r2,r1,r2,lsl#6 @ r2 to point at the end of r1 ldmia r0,{r3,r4,r5,r6,r7} @@ -194,7 +193,7 @@ sha1_block_data_order: eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) str r9,[r14,#-4]! add r3,r3,r10 @ E+=F_00_19(B,C,D) - teq r14,sp + cmp r14,sp bne .L_00_15 @ [((11+4)*5+2)*3] #if __ARM_ARCH__<7 ldrb r10,[r1,#2] @@ -374,7 +373,9 @@ sha1_block_data_order: @ F_xx_xx add r3,r3,r9 @ E+=X[i] add r3,r3,r10 @ E+=F_20_39(B,C,D) - teq r14,sp @ preserve carry + ARM( teq r14,sp ) @ preserve carry + THUMB( mov r11,sp ) + THUMB( teq r14,r11 ) @ preserve carry bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4] bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes @@ -466,7 +467,7 @@ sha1_block_data_order: add r3,r3,r9 @ E+=X[i] add r3,r3,r10 @ E+=F_40_59(B,C,D) add r3,r3,r11,ror#2 - teq r14,sp + cmp r14,sp bne .L_40_59 @ [+((12+5)*5+2)*4] ldr r8,.LK_60_79 @@ -485,19 +486,12 @@ sha1_block_data_order: teq r1,r2 bne .Lloop @ [+18], total 1307 -#if __ARM_ARCH__>=5 ldmia sp!,{r4-r12,pc} -#else - ldmia sp!,{r4-r12,lr} - tst lr,#1 - moveq pc,lr @ be binary compatible with V4, yet - .word 0xe12fff1e @ interoperable with Thumb ISA:-) -#endif .align 2 .LK_00_19: .word 0x5a827999 .LK_20_39: .word 0x6ed9eba1 .LK_40_59: .word 0x8f1bbcdc .LK_60_79: .word 0xca62c1d6 -.size sha1_block_data_order,.-sha1_block_data_order +ENDPROC(sha1_block_data_order) .asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>" .align 2 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index eb87200aa4b..05ee9eebad6 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -246,18 +246,14 @@ * * This macro is intended for forcing the CPU into SVC mode at boot time. * you cannot return to the original mode. - * - * Beware, it also clobers LR. */ .macro safe_svcmode_maskall reg:req #if __LINUX_ARM_ARCH__ >= 6 mrs \reg , cpsr - mov lr , \reg - and lr , lr , #MODE_MASK - cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT + eor \reg, \reg, #HYP_MODE + tst \reg, #MODE_MASK bic \reg , \reg , #MODE_MASK - orr \reg , \reg , #SVC_MODE + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) bne 1f orr \reg, \reg, #PSR_A_BIT diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index a59dcb5ab5f..ad41ec2471e 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -64,6 +64,24 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_INTEL 0x69 + +#define ARM_CPU_PART_ARM1136 0xB360 +#define ARM_CPU_PART_ARM1156 0xB560 +#define ARM_CPU_PART_ARM1176 0xB760 +#define ARM_CPU_PART_ARM11MPCORE 0xB020 +#define ARM_CPU_PART_CORTEX_A8 0xC080 +#define ARM_CPU_PART_CORTEX_A9 0xC090 +#define ARM_CPU_PART_CORTEX_A5 0xC050 +#define ARM_CPU_PART_CORTEX_A15 0xC0F0 +#define ARM_CPU_PART_CORTEX_A7 0xC070 + +#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 +#define ARM_CPU_XSCALE_ARCH_V1 0x2000 +#define ARM_CPU_XSCALE_ARCH_V2 0x4000 +#define ARM_CPU_XSCALE_ARCH_V3 0x6000 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return read_cpuid_id() & 0xFFF0; +} + +static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) +{ + return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK; +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h index f2e5cad3f30..2381199acb7 100644 --- a/arch/arm/include/asm/cti.h +++ b/arch/arm/include/asm/cti.h @@ -2,6 +2,7 @@ #define __ASMARM_CTI_H #include <asm/io.h> +#include <asm/hardware/coresight.h> /* The registers' definition is from section 3.2 of * Embedded Cross Trigger Revision: r0p0 @@ -35,11 +36,6 @@ #define LOCKACCESS 0xFB0 #define LOCKSTATUS 0xFB4 -/* write this value to LOCKACCESS will unlock the module, and - * other value will lock the module - */ -#define LOCKCODE 0xC5ACCE55 - /** * struct cti - cross trigger interface struct * @base: mapped virtual address for the cti base @@ -146,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti) */ static inline void cti_unlock(struct cti *cti) { - __raw_writel(LOCKCODE, cti->base + LOCKACCESS); + __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); } /** @@ -158,6 +154,6 @@ static inline void cti_unlock(struct cti *cti) */ static inline void cti_lock(struct cti *cti) { - __raw_writel(~LOCKCODE, cti->base + LOCKACCESS); + __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); } #endif diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index 5694a0d6576..58b8c6a0ab1 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -105,7 +105,7 @@ extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg); */ extern void __set_dma_addr(unsigned int chan, void *addr); #define set_dma_addr(chan, addr) \ - __set_dma_addr(chan, bus_to_virt(addr)) + __set_dma_addr(chan, (void *)__bus_to_virt(addr)) /* Set the DMA byte count for this channel * diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index 7ecd793b8f5..0cf7a6b842f 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -36,7 +36,7 @@ /* CoreSight Component Registers */ #define CSCR_CLASS 0xff4 -#define UNLOCK_MAGIC 0xc5acce55 +#define CS_LAR_KEY 0xc5acce55 /* ETM control register, "ETM Architecture", 3.3.1 */ #define ETMR_CTRL 0 @@ -147,11 +147,11 @@ #define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) #define etm_unlock(t) \ - do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) + do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0) #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) #define etb_unlock(t) \ - do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) + do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0) #endif /* __ASM_HARDWARE_CORESIGHT_H */ diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h deleted file mode 100644 index 4b1ce6cd477..00000000000 --- a/arch/arm/include/asm/hardware/gic.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/include/asm/hardware/gic.h - * - * Copyright (C) 2002 ARM Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_ARM_HARDWARE_GIC_H -#define __ASM_ARM_HARDWARE_GIC_H - -#include <linux/compiler.h> - -#define GIC_CPU_CTRL 0x00 -#define GIC_CPU_PRIMASK 0x04 -#define GIC_CPU_BINPOINT 0x08 -#define GIC_CPU_INTACK 0x0c -#define GIC_CPU_EOI 0x10 -#define GIC_CPU_RUNNINGPRI 0x14 -#define GIC_CPU_HIGHPRI 0x18 - -#define GIC_DIST_CTRL 0x000 -#define GIC_DIST_CTR 0x004 -#define GIC_DIST_ENABLE_SET 0x100 -#define GIC_DIST_ENABLE_CLEAR 0x180 -#define GIC_DIST_PENDING_SET 0x200 -#define GIC_DIST_PENDING_CLEAR 0x280 -#define GIC_DIST_ACTIVE_BIT 0x300 -#define GIC_DIST_PRI 0x400 -#define GIC_DIST_TARGET 0x800 -#define GIC_DIST_CONFIG 0xc00 -#define GIC_DIST_SOFTINT 0xf00 - -#ifndef __ASSEMBLY__ -#include <linux/irqdomain.h> -struct device_node; - -extern struct irq_chip gic_arch_extn; - -void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, - u32 offset, struct device_node *); -int gic_of_init(struct device_node *node, struct device_node *parent); -void gic_secondary_init(unsigned int); -void gic_handle_irq(struct pt_regs *regs); -void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); -void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); - -static inline void gic_init(unsigned int nr, int start, - void __iomem *dist , void __iomem *cpu) -{ - gic_init_bases(nr, start, dist, cpu, 0, NULL); -} - -#endif - -#endif diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h deleted file mode 100644 index 2bebad36fc8..00000000000 --- a/arch/arm/include/asm/hardware/vic.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/include/asm/hardware/vic.h - * - * Copyright (c) ARM Limited 2003. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_HARDWARE_VIC_H -#define __ASM_ARM_HARDWARE_VIC_H - -#define VIC_IRQ_STATUS 0x00 -#define VIC_FIQ_STATUS 0x04 -#define VIC_RAW_STATUS 0x08 -#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ -#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */ -#define VIC_INT_ENABLE_CLEAR 0x14 -#define VIC_INT_SOFT 0x18 -#define VIC_INT_SOFT_CLEAR 0x1c -#define VIC_PROTECT 0x20 -#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ -#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ - -#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ -#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ -#define VIC_ITCR 0x300 /* VIC test control register */ - -#define VIC_VECT_CNTL_ENABLE (1 << 5) - -#define VIC_PL192_VECT_ADDR 0xF00 - -#ifndef __ASSEMBLY__ -#include <linux/compiler.h> -#include <linux/types.h> - -struct device_node; -struct pt_regs; - -void __vic_init(void __iomem *base, int irq_start, u32 vic_sources, - u32 resume_sources, struct device_node *node); -void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); -int vic_of_init(struct device_node *node, struct device_node *parent); -void vic_handle_irq(struct pt_regs *regs); - -#endif /* __ASSEMBLY__ */ -#endif diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h index 01169dd723f..eef55ea9ef0 100644 --- a/arch/arm/include/asm/hw_breakpoint.h +++ b/arch/arm/include/asm/hw_breakpoint.h @@ -85,6 +85,9 @@ static inline void decode_ctrl_reg(u32 reg, #define ARM_DSCR_HDBGEN (1 << 14) #define ARM_DSCR_MDBGEN (1 << 15) +/* OSLSR os lock model bits */ +#define ARM_OSLSR_OSLM0 (1 << 0) + /* opcode2 numbers for the co-processor instructions. */ #define ARM_OP2_BVR 4 #define ARM_OP2_BCR 5 diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h index bf863edb517..1a66f907e5c 100644 --- a/arch/arm/include/asm/idmap.h +++ b/arch/arm/include/asm/idmap.h @@ -8,6 +8,7 @@ #define __idmap __section(.idmap.text) noinline notrace extern pgd_t *idmap_pgd; +extern pgd_t *hyp_pgd; void setup_mm_for_reboot(void); diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h new file mode 100644 index 00000000000..7c3d813e15d --- /dev/null +++ b/arch/arm/include/asm/kvm_arm.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_ARM_H__ +#define __ARM_KVM_ARM_H__ + +#include <linux/types.h> + +/* Hyp Configuration Register (HCR) bits */ +#define HCR_TGE (1 << 27) +#define HCR_TVM (1 << 26) +#define HCR_TTLB (1 << 25) +#define HCR_TPU (1 << 24) +#define HCR_TPC (1 << 23) +#define HCR_TSW (1 << 22) +#define HCR_TAC (1 << 21) +#define HCR_TIDCP (1 << 20) +#define HCR_TSC (1 << 19) +#define HCR_TID3 (1 << 18) +#define HCR_TID2 (1 << 17) +#define HCR_TID1 (1 << 16) +#define HCR_TID0 (1 << 15) +#define HCR_TWE (1 << 14) +#define HCR_TWI (1 << 13) +#define HCR_DC (1 << 12) +#define HCR_BSU (3 << 10) +#define HCR_BSU_IS (1 << 10) +#define HCR_FB (1 << 9) +#define HCR_VA (1 << 8) +#define HCR_VI (1 << 7) +#define HCR_VF (1 << 6) +#define HCR_AMO (1 << 5) +#define HCR_IMO (1 << 4) +#define HCR_FMO (1 << 3) +#define HCR_PTW (1 << 2) +#define HCR_SWIO (1 << 1) +#define HCR_VM 1 + +/* + * The bits we set in HCR: + * TAC: Trap ACTLR + * TSC: Trap SMC + * TSW: Trap cache operations by set/way + * TWI: Trap WFI + * TIDCP: Trap L2CTLR/L2ECTLR + * BSU_IS: Upgrade barriers to the inner shareable domain + * FB: Force broadcast of all maintainance operations + * AMO: Override CPSR.A and enable signaling with VA + * IMO: Override CPSR.I and enable signaling with VI + * FMO: Override CPSR.F and enable signaling with VF + * SWIO: Turn set/way invalidates into set/way clean+invalidate + */ +#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ + HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ + HCR_SWIO | HCR_TIDCP) +#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) + +/* System Control Register (SCTLR) bits */ +#define SCTLR_TE (1 << 30) +#define SCTLR_EE (1 << 25) +#define SCTLR_V (1 << 13) + +/* Hyp System Control Register (HSCTLR) bits */ +#define HSCTLR_TE (1 << 30) +#define HSCTLR_EE (1 << 25) +#define HSCTLR_FI (1 << 21) +#define HSCTLR_WXN (1 << 19) +#define HSCTLR_I (1 << 12) +#define HSCTLR_C (1 << 2) +#define HSCTLR_A (1 << 1) +#define HSCTLR_M 1 +#define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \ + HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE) + +/* TTBCR and HTCR Registers bits */ +#define TTBCR_EAE (1 << 31) +#define TTBCR_IMP (1 << 30) +#define TTBCR_SH1 (3 << 28) +#define TTBCR_ORGN1 (3 << 26) +#define TTBCR_IRGN1 (3 << 24) +#define TTBCR_EPD1 (1 << 23) +#define TTBCR_A1 (1 << 22) +#define TTBCR_T1SZ (3 << 16) +#define TTBCR_SH0 (3 << 12) +#define TTBCR_ORGN0 (3 << 10) +#define TTBCR_IRGN0 (3 << 8) +#define TTBCR_EPD0 (1 << 7) +#define TTBCR_T0SZ 3 +#define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) + +/* Hyp System Trap Register */ +#define HSTR_T(x) (1 << x) +#define HSTR_TTEE (1 << 16) +#define HSTR_TJDBX (1 << 17) + +/* Hyp Coprocessor Trap Register */ +#define HCPTR_TCP(x) (1 << x) +#define HCPTR_TCP_MASK (0x3fff) +#define HCPTR_TASE (1 << 15) +#define HCPTR_TTA (1 << 20) +#define HCPTR_TCPAC (1 << 31) + +/* Hyp Debug Configuration Register bits */ +#define HDCR_TDRA (1 << 11) +#define HDCR_TDOSA (1 << 10) +#define HDCR_TDA (1 << 9) +#define HDCR_TDE (1 << 8) +#define HDCR_HPME (1 << 7) +#define HDCR_TPM (1 << 6) +#define HDCR_TPMCR (1 << 5) +#define HDCR_HPMN_MASK (0x1F) + +/* + * The architecture supports 40-bit IPA as input to the 2nd stage translations + * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address + * space. + */ +#define KVM_PHYS_SHIFT (40) +#define KVM_PHYS_SIZE (1ULL << KVM_PHYS_SHIFT) +#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL) +#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30)) +#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t)) +#define S2_PGD_SIZE (1 << S2_PGD_ORDER) + +/* Virtualization Translation Control Register (VTCR) bits */ +#define VTCR_SH0 (3 << 12) +#define VTCR_ORGN0 (3 << 10) +#define VTCR_IRGN0 (3 << 8) +#define VTCR_SL0 (3 << 6) +#define VTCR_S (1 << 4) +#define VTCR_T0SZ (0xf) +#define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \ + VTCR_S | VTCR_T0SZ) +#define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0) +#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */ +#define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */ +#define KVM_VTCR_SL0 VTCR_SL_L1 +/* stage-2 input address range defined as 2^(32-T0SZ) */ +#define KVM_T0SZ (32 - KVM_PHYS_SHIFT) +#define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ) +#define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S) + +/* Virtualization Translation Table Base Register (VTTBR) bits */ +#if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */ +#define VTTBR_X (14 - KVM_T0SZ) +#else +#define VTTBR_X (5 - KVM_T0SZ) +#endif +#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) +#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) +#define VTTBR_VMID_SHIFT (48LLU) +#define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT) + +/* Hyp Syndrome Register (HSR) bits */ +#define HSR_EC_SHIFT (26) +#define HSR_EC (0x3fU << HSR_EC_SHIFT) +#define HSR_IL (1U << 25) +#define HSR_ISS (HSR_IL - 1) +#define HSR_ISV_SHIFT (24) +#define HSR_ISV (1U << HSR_ISV_SHIFT) +#define HSR_SRT_SHIFT (16) +#define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT) +#define HSR_FSC (0x3f) +#define HSR_FSC_TYPE (0x3c) +#define HSR_SSE (1 << 21) +#define HSR_WNR (1 << 6) +#define HSR_CV_SHIFT (24) +#define HSR_CV (1U << HSR_CV_SHIFT) +#define HSR_COND_SHIFT (20) +#define HSR_COND (0xfU << HSR_COND_SHIFT) + +#define FSC_FAULT (0x04) +#define FSC_PERM (0x0c) + +/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ +#define HPFAR_MASK (~0xf) + +#define HSR_EC_UNKNOWN (0x00) +#define HSR_EC_WFI (0x01) +#define HSR_EC_CP15_32 (0x03) +#define HSR_EC_CP15_64 (0x04) +#define HSR_EC_CP14_MR (0x05) +#define HSR_EC_CP14_LS (0x06) +#define HSR_EC_CP_0_13 (0x07) +#define HSR_EC_CP10_ID (0x08) +#define HSR_EC_JAZELLE (0x09) +#define HSR_EC_BXJ (0x0A) +#define HSR_EC_CP14_64 (0x0C) +#define HSR_EC_SVC_HYP (0x11) +#define HSR_EC_HVC (0x12) +#define HSR_EC_SMC (0x13) +#define HSR_EC_IABT (0x20) +#define HSR_EC_IABT_HYP (0x21) +#define HSR_EC_DABT (0x24) +#define HSR_EC_DABT_HYP (0x25) + +#define HSR_HVC_IMM_MASK ((1UL << 16) - 1) + +#endif /* __ARM_KVM_ARM_H__ */ diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h new file mode 100644 index 00000000000..5e06e817778 --- /dev/null +++ b/arch/arm/include/asm/kvm_asm.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_ASM_H__ +#define __ARM_KVM_ASM_H__ + +/* 0 is reserved as an invalid value. */ +#define c0_MPIDR 1 /* MultiProcessor ID Register */ +#define c0_CSSELR 2 /* Cache Size Selection Register */ +#define c1_SCTLR 3 /* System Control Register */ +#define c1_ACTLR 4 /* Auxilliary Control Register */ +#define c1_CPACR 5 /* Coprocessor Access Control */ +#define c2_TTBR0 6 /* Translation Table Base Register 0 */ +#define c2_TTBR0_high 7 /* TTBR0 top 32 bits */ +#define c2_TTBR1 8 /* Translation Table Base Register 1 */ +#define c2_TTBR1_high 9 /* TTBR1 top 32 bits */ +#define c2_TTBCR 10 /* Translation Table Base Control R. */ +#define c3_DACR 11 /* Domain Access Control Register */ +#define c5_DFSR 12 /* Data Fault Status Register */ +#define c5_IFSR 13 /* Instruction Fault Status Register */ +#define c5_ADFSR 14 /* Auxilary Data Fault Status R */ +#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */ +#define c6_DFAR 16 /* Data Fault Address Register */ +#define c6_IFAR 17 /* Instruction Fault Address Register */ +#define c9_L2CTLR 18 /* Cortex A15 L2 Control Register */ +#define c10_PRRR 19 /* Primary Region Remap Register */ +#define c10_NMRR 20 /* Normal Memory Remap Register */ +#define c12_VBAR 21 /* Vector Base Address Register */ +#define c13_CID 22 /* Context ID Register */ +#define c13_TID_URW 23 /* Thread ID, User R/W */ +#define c13_TID_URO 24 /* Thread ID, User R/O */ +#define c13_TID_PRIV 25 /* Thread ID, Privileged */ +#define NR_CP15_REGS 26 /* Number of regs (incl. invalid) */ + +#define ARM_EXCEPTION_RESET 0 +#define ARM_EXCEPTION_UNDEFINED 1 +#define ARM_EXCEPTION_SOFTWARE 2 +#define ARM_EXCEPTION_PREF_ABORT 3 +#define ARM_EXCEPTION_DATA_ABORT 4 +#define ARM_EXCEPTION_IRQ 5 +#define ARM_EXCEPTION_FIQ 6 +#define ARM_EXCEPTION_HVC 7 + +#ifndef __ASSEMBLY__ +struct kvm; +struct kvm_vcpu; + +extern char __kvm_hyp_init[]; +extern char __kvm_hyp_init_end[]; + +extern char __kvm_hyp_exit[]; +extern char __kvm_hyp_exit_end[]; + +extern char __kvm_hyp_vector[]; + +extern char __kvm_hyp_code_start[]; +extern char __kvm_hyp_code_end[]; + +extern void __kvm_tlb_flush_vmid(struct kvm *kvm); + +extern void __kvm_flush_vm_context(void); +extern void __kvm_tlb_flush_vmid(struct kvm *kvm); + +extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); +#endif + +#endif /* __ARM_KVM_ASM_H__ */ diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h new file mode 100644 index 00000000000..4917c2f7e45 --- /dev/null +++ b/arch/arm/include/asm/kvm_coproc.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Rusty Russell IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_COPROC_H__ +#define __ARM_KVM_COPROC_H__ +#include <linux/kvm_host.h> + +void kvm_reset_coprocs(struct kvm_vcpu *vcpu); + +struct kvm_coproc_target_table { + unsigned target; + const struct coproc_reg *table; + size_t num; +}; +void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table); + +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run); + +unsigned long kvm_arm_num_guest_msrs(struct kvm_vcpu *vcpu); +int kvm_arm_copy_msrindices(struct kvm_vcpu *vcpu, u64 __user *uindices); +void kvm_coproc_table_init(void); + +struct kvm_one_reg; +int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); +int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); +int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); +unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu); +#endif /* __ARM_KVM_COPROC_H__ */ diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h new file mode 100644 index 00000000000..fd611996bfb --- /dev/null +++ b/arch/arm/include/asm/kvm_emulate.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_EMULATE_H__ +#define __ARM_KVM_EMULATE_H__ + +#include <linux/kvm_host.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_mmio.h> + +u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num); +u32 *vcpu_spsr(struct kvm_vcpu *vcpu); + +int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run); +void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr); +void kvm_inject_undefined(struct kvm_vcpu *vcpu); +void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); +void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); + +static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu) +{ + return 1; +} + +static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu) +{ + return (u32 *)&vcpu->arch.regs.usr_regs.ARM_pc; +} + +static inline u32 *vcpu_cpsr(struct kvm_vcpu *vcpu) +{ + return (u32 *)&vcpu->arch.regs.usr_regs.ARM_cpsr; +} + +static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) +{ + *vcpu_cpsr(vcpu) |= PSR_T_BIT; +} + +static inline bool mode_has_spsr(struct kvm_vcpu *vcpu) +{ + unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK; + return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE); +} + +static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu) +{ + unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK; + return cpsr_mode > USR_MODE;; +} + +static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg) +{ + return reg == 15; +} + +#endif /* __ARM_KVM_EMULATE_H__ */ diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h new file mode 100644 index 00000000000..98b4d1a7292 --- /dev/null +++ b/arch/arm/include/asm/kvm_host.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_HOST_H__ +#define __ARM_KVM_HOST_H__ + +#include <asm/kvm.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_mmio.h> +#include <asm/fpstate.h> + +#define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS +#define KVM_MEMORY_SLOTS 32 +#define KVM_PRIVATE_MEM_SLOTS 4 +#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 +#define KVM_HAVE_ONE_REG + +#define KVM_VCPU_MAX_FEATURES 1 + +/* We don't currently support large pages. */ +#define KVM_HPAGE_GFN_SHIFT(x) 0 +#define KVM_NR_PAGE_SIZES 1 +#define KVM_PAGES_PER_HPAGE(x) (1UL<<31) + +struct kvm_vcpu; +u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); +int kvm_target_cpu(void); +int kvm_reset_vcpu(struct kvm_vcpu *vcpu); +void kvm_reset_coprocs(struct kvm_vcpu *vcpu); + +struct kvm_arch { + /* VTTBR value associated with below pgd and vmid */ + u64 vttbr; + + /* + * Anything that is not used directly from assembly code goes + * here. + */ + + /* The VMID generation used for the virt. memory system */ + u64 vmid_gen; + u32 vmid; + + /* Stage-2 page table */ + pgd_t *pgd; +}; + +#define KVM_NR_MEM_OBJS 40 + +/* + * We don't want allocation failures within the mmu code, so we preallocate + * enough memory for a single page fault in a cache. + */ +struct kvm_mmu_memory_cache { + int nobjs; + void *objects[KVM_NR_MEM_OBJS]; +}; + +struct kvm_vcpu_arch { + struct kvm_regs regs; + + int target; /* Processor target */ + DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); + + /* System control coprocessor (cp15) */ + u32 cp15[NR_CP15_REGS]; + + /* The CPU type we expose to the VM */ + u32 midr; + + /* Exception Information */ + u32 hsr; /* Hyp Syndrome Register */ + u32 hxfar; /* Hyp Data/Inst Fault Address Register */ + u32 hpfar; /* Hyp IPA Fault Address Register */ + + /* Floating point registers (VFP and Advanced SIMD/NEON) */ + struct vfp_hard_struct vfp_guest; + struct vfp_hard_struct *vfp_host; + + /* + * Anything that is not used directly from assembly code goes + * here. + */ + /* dcache set/way operation pending */ + int last_pcpu; + cpumask_t require_dcache_flush; + + /* Don't run the guest on this vcpu */ + bool pause; + + /* IO related fields */ + struct kvm_decode mmio_decode; + + /* Interrupt related fields */ + u32 irq_lines; /* IRQ and FIQ levels */ + + /* Hyp exception information */ + u32 hyp_pc; /* PC when exception was taken from Hyp mode */ + + /* Cache some mmu pages needed inside spinlock regions */ + struct kvm_mmu_memory_cache mmu_page_cache; + + /* Detect first run of a vcpu */ + bool has_run_once; +}; + +struct kvm_vm_stat { + u32 remote_tlb_flush; +}; + +struct kvm_vcpu_stat { + u32 halt_wakeup; +}; + +struct kvm_vcpu_init; +int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, + const struct kvm_vcpu_init *init); +unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); +int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); +struct kvm_one_reg; +int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); +int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); +u64 kvm_call_hyp(void *hypfn, ...); +void force_vm_exit(const cpumask_t *mask); + +#define KVM_ARCH_WANT_MMU_NOTIFIER +struct kvm; +int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); +int kvm_unmap_hva_range(struct kvm *kvm, + unsigned long start, unsigned long end); +void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); + +unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); +int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); + +/* We do not have shadow page tables, hence the empty hooks */ +static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva) +{ + return 0; +} + +static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) +{ + return 0; +} +#endif /* __ARM_KVM_HOST_H__ */ diff --git a/arch/arm/include/asm/kvm_mmio.h b/arch/arm/include/asm/kvm_mmio.h new file mode 100644 index 00000000000..adcc0d7d317 --- /dev/null +++ b/arch/arm/include/asm/kvm_mmio.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_MMIO_H__ +#define __ARM_KVM_MMIO_H__ + +#include <linux/kvm_host.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_arm.h> + +struct kvm_decode { + unsigned long rt; + bool sign_extend; +}; + +/* + * The in-kernel MMIO emulation code wants to use a copy of run->mmio, + * which is an anonymous type. Use our own type instead. + */ +struct kvm_exit_mmio { + phys_addr_t phys_addr; + u8 data[8]; + u32 len; + bool is_write; +}; + +static inline void kvm_prepare_mmio(struct kvm_run *run, + struct kvm_exit_mmio *mmio) +{ + run->mmio.phys_addr = mmio->phys_addr; + run->mmio.len = mmio->len; + run->mmio.is_write = mmio->is_write; + memcpy(run->mmio.data, mmio->data, mmio->len); + run->exit_reason = KVM_EXIT_MMIO; +} + +int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); +int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, + phys_addr_t fault_ipa); + +#endif /* __ARM_KVM_MMIO_H__ */ diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h new file mode 100644 index 00000000000..421a20b3487 --- /dev/null +++ b/arch/arm/include/asm/kvm_mmu.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_MMU_H__ +#define __ARM_KVM_MMU_H__ + +int create_hyp_mappings(void *from, void *to); +int create_hyp_io_mappings(void *from, void *to, phys_addr_t); +void free_hyp_pmds(void); + +int kvm_alloc_stage2_pgd(struct kvm *kvm); +void kvm_free_stage2_pgd(struct kvm *kvm); +int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, + phys_addr_t pa, unsigned long size); + +int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run); + +void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); + +phys_addr_t kvm_mmu_get_httbr(void); +int kvm_mmu_init(void); +void kvm_clear_hyp_idmap(void); + +static inline bool kvm_is_write_fault(unsigned long hsr) +{ + unsigned long hsr_ec = hsr >> HSR_EC_SHIFT; + if (hsr_ec == HSR_EC_IABT) + return false; + else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR)) + return false; + else + return true; +} + +#endif /* __ARM_KVM_MMU_H__ */ diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h new file mode 100644 index 00000000000..9a83d98bf17 --- /dev/null +++ b/arch/arm/include/asm/kvm_psci.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2012 - ARM Ltd + * Author: Marc Zyngier <marc.zyngier@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ARM_KVM_PSCI_H__ +#define __ARM_KVM_PSCI_H__ + +bool kvm_psci_call(struct kvm_vcpu *vcpu); + +#endif /* __ARM_KVM_PSCI_H__ */ diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 917d4fcfd9b..308ad7d6f98 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -12,7 +12,6 @@ struct tag; struct meminfo; -struct sys_timer; struct pt_regs; struct smp_operations; #ifdef CONFIG_SMP @@ -48,7 +47,7 @@ struct machine_desc { void (*map_io)(void);/* IO mapping function */ void (*init_early)(void); void (*init_irq)(void); - struct sys_timer *timer; /* system tick timer */ + void (*init_time)(void); void (*init_machine)(void); void (*init_late)(void); #ifdef CONFIG_MULTI_IRQ_HANDLER diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 15cb035309f..18c88302333 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h @@ -22,6 +22,7 @@ extern int show_fiq_list(struct seq_file *, int); #ifdef CONFIG_MULTI_IRQ_HANDLER extern void (*handle_arch_irq)(struct pt_regs *); +extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); #endif /* diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index db9fedb57f2..5cf2e979b4b 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -23,6 +23,7 @@ struct hw_pci { #endif struct pci_ops *ops; int nr_controllers; + void **private_data; int (*setup)(int nr, struct pci_sys_data *); struct pci_bus *(*scan)(int nr, struct pci_sys_data *); void (*preinit)(void); diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index 6ca945f534a..90c12e1e695 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -10,36 +10,6 @@ #ifndef __ASM_ARM_MACH_TIME_H #define __ASM_ARM_MACH_TIME_H -/* - * This is our kernel timer structure. - * - * - init - * Initialise the kernels jiffy timer source, claim interrupt - * using setup_irq. This is called early on during initialisation - * while interrupts are still disabled on the local CPU. - * - suspend - * Suspend the kernel jiffy timer source, if necessary. This - * is called with interrupts disabled, after all normal devices - * have been suspended. If no action is required, set this to - * NULL. - * - resume - * Resume the kernel jiffy timer source, if necessary. This - * is called with interrupts disabled before any normal devices - * are resumed. If no action is required, set this to NULL. - * - offset - * Return the timer offset in microseconds since the last timer - * interrupt. Note: this must take account of any unprocessed - * timer interrupt which may be pending. - */ -struct sys_timer { - void (*init)(void); - void (*suspend)(void); - void (*resume)(void); -#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET - unsigned long (*offset)(void); -#endif -}; - extern void timer_tick(void); struct timespec; diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 73cf03aa981..57870ab313c 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -36,23 +36,23 @@ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area */ #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) -#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000)) -#define TASK_UNMAPPED_BASE (UL(CONFIG_PAGE_OFFSET) / 3) +#define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M)) +#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M) /* * The maximum size of a 26-bit user space task. */ -#define TASK_SIZE_26 UL(0x04000000) +#define TASK_SIZE_26 (UL(1) << 26) /* * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 32MB of the kernel text. */ #ifndef CONFIG_THUMB2_KERNEL -#define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) +#define MODULES_VADDR (PAGE_OFFSET - SZ_16M) #else /* smaller range for Thumb-2 symbols relocation (2^24)*/ -#define MODULES_VADDR (PAGE_OFFSET - 8*1024*1024) +#define MODULES_VADDR (PAGE_OFFSET - SZ_8M) #endif #if TASK_SIZE > MODULES_VADDR @@ -245,6 +245,7 @@ static inline void *phys_to_virt(phys_addr_t x) #define __bus_to_pfn(x) __phys_to_pfn(x) #endif +#ifdef CONFIG_VIRT_TO_BUS static inline __deprecated unsigned long virt_to_bus(void *x) { return __virt_to_bus((unsigned long)x); @@ -254,6 +255,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x) { return (void *)__bus_to_virt(x); } +#endif /* * Conversion between a struct page and a physical address. diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h new file mode 100644 index 00000000000..bc3a9174417 --- /dev/null +++ b/arch/arm/include/asm/opcodes-sec.h @@ -0,0 +1,24 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2012 ARM Limited + */ + +#ifndef __ASM_ARM_OPCODES_SEC_H +#define __ASM_ARM_OPCODES_SEC_H + +#include <asm/opcodes.h> + +#define __SMC(imm4) __inst_arm_thumb32( \ + 0xE1600070 | (((imm4) & 0xF) << 0), \ + 0xF7F08000 | (((imm4) & 0xF) << 16) \ +) + +#endif /* __ASM_ARM_OPCODES_SEC_H */ diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h index 74e211a6fb2..e796c598513 100644 --- a/arch/arm/include/asm/opcodes.h +++ b/arch/arm/include/asm/opcodes.h @@ -10,6 +10,7 @@ #define __ASM_ARM_OPCODES_H #ifndef __ASSEMBLY__ +#include <linux/linkage.h> extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #endif diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index 53426c66352..12f71a19042 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -92,6 +92,7 @@ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) static inline void outer_flush_all(void) { } static inline void outer_inv_all(void) { } static inline void outer_disable(void) { } +static inline void outer_resume(void) { } #endif diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h index d7952824c5c..18f5cef82ad 100644 --- a/arch/arm/include/asm/pgtable-3level-hwdef.h +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h @@ -32,6 +32,9 @@ #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) #define PMD_BIT4 (_AT(pmdval_t, 0)) #define PMD_DOMAIN(x) (_AT(pmdval_t, 0)) +#define PMD_APTABLE_SHIFT (61) +#define PMD_APTABLE (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT) +#define PMD_PXNTABLE (_AT(pgdval_t, 1) << 59) /* * - section @@ -41,9 +44,11 @@ #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) +#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 0)) #define PMD_SECT_AP_READ (_AT(pmdval_t, 0)) +#define PMD_SECT_AP1 (_AT(pmdval_t, 1) << 6) #define PMD_SECT_TEX(x) (_AT(pmdval_t, 0)) /* diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index a3f37929940..6ef8afd1b64 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -104,11 +104,29 @@ */ #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ +/* + * 2nd stage PTE definitions for LPAE. + */ +#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */ +#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */ +#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */ +#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ +#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */ + +/* + * Hyp-mode PL2 PTE definitions for LPAE. + */ +#define L_PTE_HYP L_PTE_USER + #ifndef __ASSEMBLY__ #define pud_none(pud) (!pud_val(pud)) #define pud_bad(pud) (!(pud_val(pud) & 2)) #define pud_present(pud) (pud_val(pud)) +#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ + PMD_TYPE_TABLE) +#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ + PMD_TYPE_SECT) #define pud_clear(pudp) \ do { \ diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 9c82f988c0e..f30ac3b55ba 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t); extern pgprot_t pgprot_user; extern pgprot_t pgprot_kernel; +extern pgprot_t pgprot_hyp_device; +extern pgprot_t pgprot_s2; +extern pgprot_t pgprot_s2_device; #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b)) @@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel; #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY) #define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN) #define PAGE_KERNEL_EXEC pgprot_kernel +#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP) +#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP) +#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY) +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY) #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE) #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN) diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h new file mode 100644 index 00000000000..ce0dbe7c162 --- /dev/null +++ b/arch/arm/include/asm/psci.h @@ -0,0 +1,36 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2012 ARM Limited + */ + +#ifndef __ASM_ARM_PSCI_H +#define __ASM_ARM_PSCI_H + +#define PSCI_POWER_STATE_TYPE_STANDBY 0 +#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1 + +struct psci_power_state { + u16 id; + u8 type; + u8 affinity_level; +}; + +struct psci_operations { + int (*cpu_suspend)(struct psci_power_state state, + unsigned long entry_point); + int (*cpu_off)(struct psci_power_state state); + int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); + int (*migrate)(unsigned long cpuid); +}; + +extern struct psci_operations psci_ops; + +#endif /* __ASM_ARM_PSCI_H */ diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 4eb6d005ffa..86dff32a073 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -7,8 +7,14 @@ #ifndef __ASSEMBLER__ unsigned int scu_get_core_count(void __iomem *); -void scu_enable(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); + +#ifdef CONFIG_SMP +void scu_enable(void __iomem *scu_base); +#else +static inline void scu_enable(void __iomem *scu_base) {} +#endif + #endif #endif diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index b4ca707d0a6..6220e9fdf4c 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -119,22 +119,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock) static inline void arch_spin_unlock(arch_spinlock_t *lock) { - unsigned long tmp; - u32 slock; - smp_mb(); - - __asm__ __volatile__( -" mov %1, #1\n" -"1: ldrex %0, [%2]\n" -" uadd16 %0, %0, %1\n" -" strex %1, %0, [%2]\n" -" teq %1, #0\n" -" bne 1b" - : "=&r" (slock), "=&r" (tmp) - : "r" (&lock->slock) - : "cc"); - + lock->tickets.owner++; dsb_sev(); } diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h index 86164df86cb..50af92bac73 100644 --- a/arch/arm/include/asm/virt.h +++ b/arch/arm/include/asm/virt.h @@ -24,9 +24,9 @@ /* * Flag indicating that the kernel was not entered in the same mode on every * CPU. The zImage loader stashes this value in an SPSR, so we need an - * architecturally defined flag bit here (the N flag, as it happens) + * architecturally defined flag bit here. */ -#define BOOT_CPU_MODE_MISMATCH (1<<31) +#define BOOT_CPU_MODE_MISMATCH PSR_N_BIT #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S index 0c4e17d4d35..c6f294cf18f 100644 --- a/arch/arm/include/debug/imx.S +++ b/arch/arm/include/debug/imx.S @@ -34,7 +34,7 @@ #define UART_PADDR 0x43f90000 #elif defined (CONFIG_DEBUG_IMX51_UART) #define UART_PADDR 0x73fbc000 -#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) +#elif defined (CONFIG_DEBUG_IMX53_UART) #define UART_PADDR 0x53fbc000 #elif defined (CONFIG_DEBUG_IMX6Q_UART) #define UART_PADDR IMX6Q_DEBUG_UART_BASE diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h new file mode 100644 index 00000000000..3303ff5adbf --- /dev/null +++ b/arch/arm/include/uapi/asm/kvm.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_H__ +#define __ARM_KVM_H__ + +#include <linux/types.h> +#include <asm/ptrace.h> + +#define __KVM_HAVE_GUEST_DEBUG +#define __KVM_HAVE_IRQ_LINE + +#define KVM_REG_SIZE(id) \ + (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) + +/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */ +#define KVM_ARM_SVC_sp svc_regs[0] +#define KVM_ARM_SVC_lr svc_regs[1] +#define KVM_ARM_SVC_spsr svc_regs[2] +#define KVM_ARM_ABT_sp abt_regs[0] +#define KVM_ARM_ABT_lr abt_regs[1] +#define KVM_ARM_ABT_spsr abt_regs[2] +#define KVM_ARM_UND_sp und_regs[0] +#define KVM_ARM_UND_lr und_regs[1] +#define KVM_ARM_UND_spsr und_regs[2] +#define KVM_ARM_IRQ_sp irq_regs[0] +#define KVM_ARM_IRQ_lr irq_regs[1] +#define KVM_ARM_IRQ_spsr irq_regs[2] + +/* Valid only for fiq_regs in struct kvm_regs */ +#define KVM_ARM_FIQ_r8 fiq_regs[0] +#define KVM_ARM_FIQ_r9 fiq_regs[1] +#define KVM_ARM_FIQ_r10 fiq_regs[2] +#define KVM_ARM_FIQ_fp fiq_regs[3] +#define KVM_ARM_FIQ_ip fiq_regs[4] +#define KVM_ARM_FIQ_sp fiq_regs[5] +#define KVM_ARM_FIQ_lr fiq_regs[6] +#define KVM_ARM_FIQ_spsr fiq_regs[7] + +struct kvm_regs { + struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */ + __u32 svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */ + __u32 abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */ + __u32 und_regs[3]; /* SP_und, LR_und, SPSR_und */ + __u32 irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */ + __u32 fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */ +}; + +/* Supported Processor Types */ +#define KVM_ARM_TARGET_CORTEX_A15 0 +#define KVM_ARM_NUM_TARGETS 1 + +#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ + +struct kvm_vcpu_init { + __u32 target; + __u32 features[7]; +}; + +struct kvm_sregs { +}; + +struct kvm_fpu { +}; + +struct kvm_guest_debug_arch { +}; + +struct kvm_debug_exit_arch { +}; + +struct kvm_sync_regs { +}; + +struct kvm_arch_memory_slot { +}; + +/* If you need to interpret the index values, here is the key: */ +#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 +#define KVM_REG_ARM_COPROC_SHIFT 16 +#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007 +#define KVM_REG_ARM_32_OPC2_SHIFT 0 +#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078 +#define KVM_REG_ARM_OPC1_SHIFT 3 +#define KVM_REG_ARM_CRM_MASK 0x0000000000000780 +#define KVM_REG_ARM_CRM_SHIFT 7 +#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800 +#define KVM_REG_ARM_32_CRN_SHIFT 11 + +/* Normal registers are mapped as coprocessor 16. */ +#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) +#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4) + +/* Some registers need more space to represent values. */ +#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) +#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 +#define KVM_REG_ARM_DEMUX_ID_SHIFT 8 +#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) +#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF +#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 + +/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */ +#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT) +#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF +#define KVM_REG_ARM_VFP_BASE_REG 0x0 +#define KVM_REG_ARM_VFP_FPSID 0x1000 +#define KVM_REG_ARM_VFP_FPSCR 0x1001 +#define KVM_REG_ARM_VFP_MVFR1 0x1006 +#define KVM_REG_ARM_VFP_MVFR0 0x1007 +#define KVM_REG_ARM_VFP_FPEXC 0x1008 +#define KVM_REG_ARM_VFP_FPINST 0x1009 +#define KVM_REG_ARM_VFP_FPINST2 0x100A + + +/* KVM_IRQ_LINE irq field index values */ +#define KVM_ARM_IRQ_TYPE_SHIFT 24 +#define KVM_ARM_IRQ_TYPE_MASK 0xff +#define KVM_ARM_IRQ_VCPU_SHIFT 16 +#define KVM_ARM_IRQ_VCPU_MASK 0xff +#define KVM_ARM_IRQ_NUM_SHIFT 0 +#define KVM_ARM_IRQ_NUM_MASK 0xffff + +/* irq_type field */ +#define KVM_ARM_IRQ_TYPE_CPU 0 +#define KVM_ARM_IRQ_TYPE_SPI 1 +#define KVM_ARM_IRQ_TYPE_PPI 2 + +/* out-of-kernel GIC cpu interrupt injection irq_number field */ +#define KVM_ARM_IRQ_CPU_IRQ 0 +#define KVM_ARM_IRQ_CPU_FIQ 1 + +/* Highest supported SPI, from VGIC_NR_IRQS */ +#define KVM_ARM_IRQ_GIC_MAX 127 + +/* PSCI interface */ +#define KVM_PSCI_FN_BASE 0x95c1ba5e +#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) + +#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) +#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) +#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) +#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) + +#define KVM_PSCI_RET_SUCCESS 0 +#define KVM_PSCI_RET_NI ((unsigned long)-1) +#define KVM_PSCI_RET_INVAL ((unsigned long)-2) +#define KVM_PSCI_RET_DENIED ((unsigned long)-3) + +#endif /* __ARM_KVM_H__ */ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5bbec7b8183..5f3338eacad 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -82,5 +82,6 @@ obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o +obj-$(CONFIG_ARM_PSCI) += psci.o extra-y := $(head-y) vmlinux.lds diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index c985b481192..c8b3272dfed 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -13,6 +13,9 @@ #include <linux/sched.h> #include <linux/mm.h> #include <linux/dma-mapping.h> +#ifdef CONFIG_KVM_ARM_HOST +#include <linux/kvm_host.h> +#endif #include <asm/cacheflush.h> #include <asm/glue-df.h> #include <asm/glue-pf.h> @@ -146,5 +149,27 @@ int main(void) DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL); DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE); DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE); +#ifdef CONFIG_KVM_ARM_HOST + DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); + DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr)); + DEFINE(VCPU_CP15, offsetof(struct kvm_vcpu, arch.cp15)); + DEFINE(VCPU_VFP_GUEST, offsetof(struct kvm_vcpu, arch.vfp_guest)); + DEFINE(VCPU_VFP_HOST, offsetof(struct kvm_vcpu, arch.vfp_host)); + DEFINE(VCPU_REGS, offsetof(struct kvm_vcpu, arch.regs)); + DEFINE(VCPU_USR_REGS, offsetof(struct kvm_vcpu, arch.regs.usr_regs)); + DEFINE(VCPU_SVC_REGS, offsetof(struct kvm_vcpu, arch.regs.svc_regs)); + DEFINE(VCPU_ABT_REGS, offsetof(struct kvm_vcpu, arch.regs.abt_regs)); + DEFINE(VCPU_UND_REGS, offsetof(struct kvm_vcpu, arch.regs.und_regs)); + DEFINE(VCPU_IRQ_REGS, offsetof(struct kvm_vcpu, arch.regs.irq_regs)); + DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs)); + DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc)); + DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr)); + DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines)); + DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.hsr)); + DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.hxfar)); + DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.hpfar)); + DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.hyp_pc)); + DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr)); +#endif return 0; } diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 379cf329239..a1f73b502ef 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -413,7 +413,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) +static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) { int ret; struct pci_host_bridge_window *window; @@ -445,7 +445,7 @@ static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) return 0; } -static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) +static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; int ret; @@ -464,6 +464,9 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) sys->map_irq = hw->map_irq; INIT_LIST_HEAD(&sys->resources); + if (hw->private_data) + sys->private_data = hw->private_data[nr]; + ret = hw->setup(nr, sys); if (ret > 0) { @@ -493,7 +496,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) } } -void __init pci_common_init(struct hw_pci *hw) +void pci_common_init(struct hw_pci *hw) { struct pci_sys_data *sys; LIST_HEAD(head); diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 5ff2e77782b..5eae53e7a2e 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -28,6 +28,7 @@ #include <linux/perf_event.h> #include <linux/hw_breakpoint.h> #include <linux/smp.h> +#include <linux/cpu_pm.h> #include <asm/cacheflush.h> #include <asm/cputype.h> @@ -35,6 +36,7 @@ #include <asm/hw_breakpoint.h> #include <asm/kdebug.h> #include <asm/traps.h> +#include <asm/hardware/coresight.h> /* Breakpoint currently in use for each BRP. */ static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); @@ -49,6 +51,9 @@ static int core_num_wrps; /* Debug architecture version. */ static u8 debug_arch; +/* Does debug architecture support OS Save and Restore? */ +static bool has_ossr; + /* Maximum supported watchpoint length. */ static u8 max_watchpoint_len; @@ -903,6 +908,23 @@ static struct undef_hook debug_reg_hook = { .fn = debug_reg_trap, }; +/* Does this core support OS Save and Restore? */ +static bool core_has_os_save_restore(void) +{ + u32 oslsr; + + switch (get_debug_arch()) { + case ARM_DEBUG_ARCH_V7_1: + return true; + case ARM_DEBUG_ARCH_V7_ECP14: + ARM_DBG_READ(c1, c1, 4, oslsr); + if (oslsr & ARM_OSLSR_OSLM0) + return true; + default: + return false; + } +} + static void reset_ctrl_regs(void *unused) { int i, raw_num_brps, err = 0, cpu = smp_processor_id(); @@ -930,11 +952,7 @@ static void reset_ctrl_regs(void *unused) if ((val & 0x1) == 0) err = -EPERM; - /* - * Check whether we implement OS save and restore. - */ - ARM_DBG_READ(c1, c1, 4, val); - if ((val & 0x9) == 0) + if (!has_ossr) goto clear_vcr; break; case ARM_DEBUG_ARCH_V7_1: @@ -955,9 +973,9 @@ static void reset_ctrl_regs(void *unused) /* * Unconditionally clear the OS lock by writing a value - * other than 0xC5ACCE55 to the access register. + * other than CS_LAR_KEY to the access register. */ - ARM_DBG_WRITE(c1, c0, 4, 0); + ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY); isb(); /* @@ -1015,6 +1033,30 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = { .notifier_call = dbg_reset_notify, }; +#ifdef CONFIG_CPU_PM +static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action, + void *v) +{ + if (action == CPU_PM_EXIT) + reset_ctrl_regs(NULL); + + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata dbg_cpu_pm_nb = { + .notifier_call = dbg_cpu_pm_notify, +}; + +static void __init pm_init(void) +{ + cpu_pm_register_notifier(&dbg_cpu_pm_nb); +} +#else +static inline void pm_init(void) +{ +} +#endif + static int __init arch_hw_breakpoint_init(void) { debug_arch = get_debug_arch(); @@ -1024,6 +1066,8 @@ static int __init arch_hw_breakpoint_init(void) return 0; } + has_ossr = core_has_os_save_restore(); + /* Determine how many BRPs/WRPs are available. */ core_num_brps = get_num_brps(); core_num_wrps = get_num_wrps(); @@ -1062,8 +1106,9 @@ static int __init arch_hw_breakpoint_init(void) hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, "breakpoint debug exception"); - /* Register hotplug notifier. */ + /* Register hotplug and PM notifiers. */ register_cpu_notifier(&dbg_reset_nb); + pm_init(); return 0; } arch_initcall(arch_hw_breakpoint_init); diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 896165096d6..8e4ef4c83a7 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -117,6 +117,16 @@ void __init init_IRQ(void) machine_desc->init_irq(); } +#ifdef CONFIG_MULTI_IRQ_HANDLER +void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) +{ + if (handle_arch_irq) + return; + + handle_arch_irq = handle_irq; +} +#endif + #ifdef CONFIG_SPARSE_IRQ int __init arch_probe_nr_irqs(void) { diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index f9e8657dd24..31e0eb353cd 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -149,12 +149,6 @@ again: static void armpmu_read(struct perf_event *event) { - struct hw_perf_event *hwc = &event->hw; - - /* Don't read disabled counters! */ - if (hwc->idx < 0) - return; - armpmu_event_update(event); } @@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags) struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; - WARN_ON(idx < 0); - armpmu_stop(event, PERF_EF_UPDATE); hw_events->events[idx] = NULL; clear_bit(idx, hw_events->used_mask); @@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event) { struct arm_pmu *armpmu = to_arm_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; - int mapping, err; + int mapping; mapping = armpmu->map_event(event); @@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event) local64_set(&hwc->period_left, hwc->sample_period); } - err = 0; if (event->group_leader != event) { - err = validate_group(event); - if (err) + if (validate_group(event) != 0); return -EINVAL; } - return err; + return 0; } static int armpmu_event_init(struct perf_event *event) diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 5f6620684e2..1f2740e3dbc 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->free_irq = cpu_pmu_free_irq; /* Ensure the PMU has sane values out of reset. */ - if (cpu_pmu && cpu_pmu->reset) + if (cpu_pmu->reset) on_each_cpu(cpu_pmu->reset, cpu_pmu, 1); } @@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = { static int probe_current_pmu(struct arm_pmu *pmu) { int cpu = get_cpu(); - unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); int ret = -ENODEV; pr_info("probing PMU on CPU %d\n", cpu); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == ARM_CPU_IMP_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case ARM_CPU_PART_ARM1136: + case ARM_CPU_PART_ARM1156: + case ARM_CPU_PART_ARM1176: ret = armv6pmu_init(pmu); break; - case 0xB020: /* ARM11mpcore */ + case ARM_CPU_PART_ARM11MPCORE: ret = armv6mpcore_pmu_init(pmu); break; - case 0xC080: /* Cortex-A8 */ + case ARM_CPU_PART_CORTEX_A8: ret = armv7_a8_pmu_init(pmu); break; - case 0xC090: /* Cortex-A9 */ + case ARM_CPU_PART_CORTEX_A9: ret = armv7_a9_pmu_init(pmu); break; - case 0xC050: /* Cortex-A5 */ + case ARM_CPU_PART_CORTEX_A5: ret = armv7_a5_pmu_init(pmu); break; - case 0xC0F0: /* Cortex-A15 */ + case ARM_CPU_PART_CORTEX_A15: ret = armv7_a15_pmu_init(pmu); break; - case 0xC070: /* Cortex-A7 */ + case ARM_CPU_PART_CORTEX_A7: ret = armv7_a7_pmu_init(pmu); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; - switch (part_number) { - case 1: + } else if (implementor == ARM_CPU_IMP_INTEL) { + switch (xscale_cpu_arch_version()) { + case ARM_CPU_XSCALE_ARCH_V1: ret = xscale1pmu_init(pmu); break; - case 2: + case ARM_CPU_XSCALE_ARCH_V2: ret = xscale2pmu_init(pmu); break; } @@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev) } if (ret) { - pr_info("failed to register PMU devices!"); - kfree(pmu); - return ret; + pr_info("failed to probe PMU!"); + goto out_free; } cpu_pmu = pmu; cpu_pmu->plat_device = pdev; cpu_pmu_init(cpu_pmu); - armpmu_register(cpu_pmu, PERF_TYPE_RAW); + ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW); - return 0; + if (!ret) + return 0; + +out_free: + pr_info("failed to register PMU devices!"); + kfree(pmu); + return ret; } static struct platform_driver cpu_pmu_driver = { diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 041d0526a28..03664b0e8fa 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 4fbc757d9cf..8c79a9e70b8 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, /* * The prefetch counters don't differentiate between the I @@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 2b0fe30ec12..63990c42fac 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index c6dec5fc20a..047d3e40e47 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -172,14 +172,9 @@ static void default_idle(void) local_irq_enable(); } -void (*pm_idle)(void) = default_idle; -EXPORT_SYMBOL(pm_idle); - /* - * The idle thread, has rather strange semantics for calling pm_idle, - * but this is what x86 does and we need to do the same, so that - * things like cpuidle get called in the same way. The only difference - * is that we always respect 'hlt_counter' to prevent low power idle. + * The idle thread. + * We always respect 'hlt_counter' to prevent low power idle. */ void cpu_idle(void) { @@ -210,10 +205,10 @@ void cpu_idle(void) } else if (!need_resched()) { stop_critical_timings(); if (cpuidle_idle_call()) - pm_idle(); + default_idle(); start_critical_timings(); /* - * pm_idle functions must always + * default_idle functions must always * return with IRQs enabled. */ WARN_ON(irqs_disabled()); diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c new file mode 100644 index 00000000000..36531643cc2 --- /dev/null +++ b/arch/arm/kernel/psci.c @@ -0,0 +1,211 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2012 ARM Limited + * + * Author: Will Deacon <will.deacon@arm.com> + */ + +#define pr_fmt(fmt) "psci: " fmt + +#include <linux/init.h> +#include <linux/of.h> + +#include <asm/compiler.h> +#include <asm/errno.h> +#include <asm/opcodes-sec.h> +#include <asm/opcodes-virt.h> +#include <asm/psci.h> + +struct psci_operations psci_ops; + +static int (*invoke_psci_fn)(u32, u32, u32, u32); + +enum psci_function { + PSCI_FN_CPU_SUSPEND, + PSCI_FN_CPU_ON, + PSCI_FN_CPU_OFF, + PSCI_FN_MIGRATE, + PSCI_FN_MAX, +}; + +static u32 psci_function_id[PSCI_FN_MAX]; + +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_EOPNOTSUPP -1 +#define PSCI_RET_EINVAL -2 +#define PSCI_RET_EPERM -3 + +static int psci_to_linux_errno(int errno) +{ + switch (errno) { + case PSCI_RET_SUCCESS: + return 0; + case PSCI_RET_EOPNOTSUPP: + return -EOPNOTSUPP; + case PSCI_RET_EINVAL: + return -EINVAL; + case PSCI_RET_EPERM: + return -EPERM; + }; + + return -EINVAL; +} + +#define PSCI_POWER_STATE_ID_MASK 0xffff +#define PSCI_POWER_STATE_ID_SHIFT 0 +#define PSCI_POWER_STATE_TYPE_MASK 0x1 +#define PSCI_POWER_STATE_TYPE_SHIFT 16 +#define PSCI_POWER_STATE_AFFL_MASK 0x3 +#define PSCI_POWER_STATE_AFFL_SHIFT 24 + +static u32 psci_power_state_pack(struct psci_power_state state) +{ + return ((state.id & PSCI_POWER_STATE_ID_MASK) + << PSCI_POWER_STATE_ID_SHIFT) | + ((state.type & PSCI_POWER_STATE_TYPE_MASK) + << PSCI_POWER_STATE_TYPE_SHIFT) | + ((state.affinity_level & PSCI_POWER_STATE_AFFL_MASK) + << PSCI_POWER_STATE_AFFL_SHIFT); +} + +/* + * The following two functions are invoked via the invoke_psci_fn pointer + * and will not be inlined, allowing us to piggyback on the AAPCS. + */ +static noinline int __invoke_psci_fn_hvc(u32 function_id, u32 arg0, u32 arg1, + u32 arg2) +{ + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r1") + __asmeq("%2", "r2") + __asmeq("%3", "r3") + __HVC(0) + : "+r" (function_id) + : "r" (arg0), "r" (arg1), "r" (arg2)); + + return function_id; +} + +static noinline int __invoke_psci_fn_smc(u32 function_id, u32 arg0, u32 arg1, + u32 arg2) +{ + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r1") + __asmeq("%2", "r2") + __asmeq("%3", "r3") + __SMC(0) + : "+r" (function_id) + : "r" (arg0), "r" (arg1), "r" (arg2)); + + return function_id; +} + +static int psci_cpu_suspend(struct psci_power_state state, + unsigned long entry_point) +{ + int err; + u32 fn, power_state; + + fn = psci_function_id[PSCI_FN_CPU_SUSPEND]; + power_state = psci_power_state_pack(state); + err = invoke_psci_fn(fn, power_state, entry_point, 0); + return psci_to_linux_errno(err); +} + +static int psci_cpu_off(struct psci_power_state state) +{ + int err; + u32 fn, power_state; + + fn = psci_function_id[PSCI_FN_CPU_OFF]; + power_state = psci_power_state_pack(state); + err = invoke_psci_fn(fn, power_state, 0, 0); + return psci_to_linux_errno(err); +} + +static int psci_cpu_on(unsigned long cpuid, unsigned long entry_point) +{ + int err; + u32 fn; + + fn = psci_function_id[PSCI_FN_CPU_ON]; + err = invoke_psci_fn(fn, cpuid, entry_point, 0); + return psci_to_linux_errno(err); +} + +static int psci_migrate(unsigned long cpuid) +{ + int err; + u32 fn; + + fn = psci_function_id[PSCI_FN_MIGRATE]; + err = invoke_psci_fn(fn, cpuid, 0, 0); + return psci_to_linux_errno(err); +} + +static const struct of_device_id psci_of_match[] __initconst = { + { .compatible = "arm,psci", }, + {}, +}; + +static int __init psci_init(void) +{ + struct device_node *np; + const char *method; + u32 id; + + np = of_find_matching_node(NULL, psci_of_match); + if (!np) + return 0; + + pr_info("probing function IDs from device-tree\n"); + + if (of_property_read_string(np, "method", &method)) { + pr_warning("missing \"method\" property\n"); + goto out_put_node; + } + + if (!strcmp("hvc", method)) { + invoke_psci_fn = __invoke_psci_fn_hvc; + } else if (!strcmp("smc", method)) { + invoke_psci_fn = __invoke_psci_fn_smc; + } else { + pr_warning("invalid \"method\" property: %s\n", method); + goto out_put_node; + } + + if (!of_property_read_u32(np, "cpu_suspend", &id)) { + psci_function_id[PSCI_FN_CPU_SUSPEND] = id; + psci_ops.cpu_suspend = psci_cpu_suspend; + } + + if (!of_property_read_u32(np, "cpu_off", &id)) { + psci_function_id[PSCI_FN_CPU_OFF] = id; + psci_ops.cpu_off = psci_cpu_off; + } + + if (!of_property_read_u32(np, "cpu_on", &id)) { + psci_function_id[PSCI_FN_CPU_ON] = id; + psci_ops.cpu_on = psci_cpu_on; + } + + if (!of_property_read_u32(np, "migrate", &id)) { + psci_function_id[PSCI_FN_MIGRATE] = id; + psci_ops.migrate = psci_migrate; + } + +out_put_node: + of_node_put(np); + return 0; +} +early_initcall(psci_init); diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c index fc6692e2b60..bd6f56b9ec2 100644 --- a/arch/arm/kernel/sched_clock.c +++ b/arch/arm/kernel/sched_clock.c @@ -93,11 +93,11 @@ static void notrace update_sched_clock(void) * detectable in cyc_to_fixed_sched_clock(). */ raw_local_irq_save(flags); - cd.epoch_cyc = cyc; + cd.epoch_cyc_copy = cyc; smp_wmb(); cd.epoch_ns = ns; smp_wmb(); - cd.epoch_cyc_copy = cyc; + cd.epoch_cyc = cyc; raw_local_irq_restore(flags); } diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 84f4cbf652e..60340fa561d 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -125,18 +125,6 @@ void __init smp_init_cpus(void) smp_ops.smp_init_cpus(); } -static void __init platform_smp_prepare_cpus(unsigned int max_cpus) -{ - if (smp_ops.smp_prepare_cpus) - smp_ops.smp_prepare_cpus(max_cpus); -} - -static void __cpuinit platform_secondary_init(unsigned int cpu) -{ - if (smp_ops.smp_secondary_init) - smp_ops.smp_secondary_init(cpu); -} - int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { if (smp_ops.smp_boot_secondary) @@ -154,12 +142,6 @@ static int platform_cpu_kill(unsigned int cpu) return 1; } -static void platform_cpu_die(unsigned int cpu) -{ - if (smp_ops.cpu_die) - smp_ops.cpu_die(cpu); -} - static int platform_cpu_disable(unsigned int cpu) { if (smp_ops.cpu_disable) @@ -257,7 +239,8 @@ void __ref cpu_die(void) * actual CPU shutdown procedure is at least platform (if not * CPU) specific. */ - platform_cpu_die(cpu); + if (smp_ops.cpu_die) + smp_ops.cpu_die(cpu); /* * Do not return to the idle loop - jump back to the secondary @@ -324,7 +307,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) /* * Give the platform a chance to do its own initialisation. */ - platform_secondary_init(cpu); + if (smp_ops.smp_secondary_init) + smp_ops.smp_secondary_init(cpu); notify_cpu_starting(cpu); @@ -399,8 +383,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) /* * Initialise the present map, which describes the set of CPUs * actually populated at the present time. A platform should - * re-initialize the map in platform_smp_prepare_cpus() if - * present != possible (e.g. physical hotplug). + * re-initialize the map in the platforms smp_prepare_cpus() + * if present != possible (e.g. physical hotplug). */ init_cpu_present(cpu_possible_mask); @@ -408,7 +392,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * Initialise the SCU if there are more than one CPU * and let them know where to start. */ - platform_smp_prepare_cpus(max_cpus); + if (smp_ops.smp_prepare_cpus) + smp_ops.smp_prepare_cpus(max_cpus); } } @@ -416,7 +401,8 @@ static void (*smp_cross_call)(const struct cpumask *, unsigned int); void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) { - smp_cross_call = fn; + if (!smp_cross_call) + smp_cross_call = fn; } void arch_send_call_function_ipi_mask(const struct cpumask *mask) diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index b9f015e843d..45eac87ed66 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base) int scu_power_mode(void __iomem *scu_base, unsigned int mode) { unsigned int val; - int cpu = cpu_logical_map(smp_processor_id()); + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 49f335d301b..c092115d903 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -24,14 +24,12 @@ #include <asm/smp_twd.h> #include <asm/localtimer.h> -#include <asm/hardware/gic.h> /* set up by the platform code */ static void __iomem *twd_base; static struct clk *twd_clk; static unsigned long twd_timer_rate; -static bool common_setup_called; static DEFINE_PER_CPU(bool, percpu_setup_called); static struct clock_event_device __percpu **twd_evt; @@ -239,25 +237,28 @@ static irqreturn_t twd_handler(int irq, void *dev_id) return IRQ_NONE; } -static struct clk *twd_get_clock(void) +static void twd_get_clock(struct device_node *np) { - struct clk *clk; int err; - clk = clk_get_sys("smp_twd", NULL); - if (IS_ERR(clk)) { - pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk)); - return clk; + if (np) + twd_clk = of_clk_get(np, 0); + else + twd_clk = clk_get_sys("smp_twd", NULL); + + if (IS_ERR(twd_clk)) { + pr_err("smp_twd: clock not found %d\n", (int) PTR_ERR(twd_clk)); + return; } - err = clk_prepare_enable(clk); + err = clk_prepare_enable(twd_clk); if (err) { pr_err("smp_twd: clock failed to prepare+enable: %d\n", err); - clk_put(clk); - return ERR_PTR(err); + clk_put(twd_clk); + return; } - return clk; + twd_timer_rate = clk_get_rate(twd_clk); } /* @@ -280,26 +281,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk) } per_cpu(percpu_setup_called, cpu) = true; - /* - * This stuff only need to be done once for the entire TWD cluster - * during the runtime of the system. - */ - if (!common_setup_called) { - twd_clk = twd_get_clock(); - - /* - * We use IS_ERR_OR_NULL() here, because if the clock stubs - * are active we will get a valid clk reference which is - * however NULL and will return the rate 0. In that case we - * need to calibrate the rate instead. - */ - if (!IS_ERR_OR_NULL(twd_clk)) - twd_timer_rate = clk_get_rate(twd_clk); - else - twd_calibrate_rate(); - - common_setup_called = true; - } + twd_calibrate_rate(); /* * The following is done once per CPU the first time .setup() is @@ -330,7 +312,7 @@ static struct local_timer_ops twd_lt_ops __cpuinitdata = { .stop = twd_timer_stop, }; -static int __init twd_local_timer_common_register(void) +static int __init twd_local_timer_common_register(struct device_node *np) { int err; @@ -350,6 +332,8 @@ static int __init twd_local_timer_common_register(void) if (err) goto out_irq; + twd_get_clock(np); + return 0; out_irq: @@ -373,7 +357,7 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) if (!twd_base) return -ENOMEM; - return twd_local_timer_common_register(); + return twd_local_timer_common_register(NULL); } #ifdef CONFIG_OF @@ -405,7 +389,7 @@ void __init twd_local_timer_of_register(void) goto out; } - err = twd_local_timer_common_register(); + err = twd_local_timer_common_register(np); out: WARN(err, "twd_local_timer_of_register failed (%d)\n", err); diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 09be0c3c906..955d92d265e 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -21,7 +21,6 @@ #include <linux/timex.h> #include <linux/errno.h> #include <linux/profile.h> -#include <linux/syscore_ops.h> #include <linux/timer.h> #include <linux/irq.h> @@ -31,11 +30,6 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> -/* - * Our system timer. - */ -static struct sys_timer *system_timer; - #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \ defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE) /* this needs a better home */ @@ -69,16 +63,6 @@ unsigned long profile_pc(struct pt_regs *regs) EXPORT_SYMBOL(profile_pc); #endif -#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET -u32 arch_gettimeoffset(void) -{ - if (system_timer->offset != NULL) - return system_timer->offset() * 1000; - - return 0; -} -#endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */ - #ifndef CONFIG_GENERIC_CLOCKEVENTS /* * Kernel system timer support. @@ -129,43 +113,8 @@ int __init register_persistent_clock(clock_access_fn read_boot, return -EINVAL; } -#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS) -static int timer_suspend(void) -{ - if (system_timer->suspend) - system_timer->suspend(); - - return 0; -} - -static void timer_resume(void) -{ - if (system_timer->resume) - system_timer->resume(); -} -#else -#define timer_suspend NULL -#define timer_resume NULL -#endif - -static struct syscore_ops timer_syscore_ops = { - .suspend = timer_suspend, - .resume = timer_resume, -}; - -static int __init timer_init_syscore_ops(void) -{ - register_syscore_ops(&timer_syscore_ops); - - return 0; -} - -device_initcall(timer_init_syscore_ops); - void __init time_init(void) { - system_timer = machine_desc->timer; - system_timer->init(); + machine_desc->init_time(); sched_clock_postinit(); } - diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 11c1785bf63..b571484e9f0 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -19,7 +19,11 @@ ALIGN_FUNCTION(); \ VMLINUX_SYMBOL(__idmap_text_start) = .; \ *(.idmap.text) \ - VMLINUX_SYMBOL(__idmap_text_end) = .; + VMLINUX_SYMBOL(__idmap_text_end) = .; \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \ + *(.hyp.idmap.text) \ + VMLINUX_SYMBOL(__hyp_idmap_text_end) = .; #ifdef CONFIG_HOTPLUG_CPU #define ARM_CPU_DISCARD(x) diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig new file mode 100644 index 00000000000..05227cb57a7 --- /dev/null +++ b/arch/arm/kvm/Kconfig @@ -0,0 +1,56 @@ +# +# KVM configuration +# + +source "virt/kvm/Kconfig" + +menuconfig VIRTUALIZATION + bool "Virtualization" + ---help--- + Say Y here to get to see options for using your Linux host to run + other operating systems inside virtual machines (guests). + This option alone does not add any kernel code. + + If you say N, all options in this submenu will be skipped and + disabled. + +if VIRTUALIZATION + +config KVM + bool "Kernel-based Virtual Machine (KVM) support" + select PREEMPT_NOTIFIERS + select ANON_INODES + select KVM_MMIO + select KVM_ARM_HOST + depends on ARM_VIRT_EXT && ARM_LPAE + ---help--- + Support hosting virtualized guest machines. You will also + need to select one or more of the processor modules below. + + This module provides access to the hardware capabilities through + a character device node named /dev/kvm. + + If unsure, say N. + +config KVM_ARM_HOST + bool "KVM host support for ARM cpus." + depends on KVM + depends on MMU + select MMU_NOTIFIER + ---help--- + Provides host support for ARM processors. + +config KVM_ARM_MAX_VCPUS + int "Number maximum supported virtual CPUs per VM" + depends on KVM_ARM_HOST + default 4 + help + Static number of max supported virtual CPUs per VM. + + If you choose a high number, the vcpu structures will be quite + large, so only choose a reasonable number that you expect to + actually use. + +source drivers/virtio/Kconfig + +endif # VIRTUALIZATION diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile new file mode 100644 index 00000000000..ea27987bd07 --- /dev/null +++ b/arch/arm/kvm/Makefile @@ -0,0 +1,21 @@ +# +# Makefile for Kernel-based Virtual Machine module +# + +plus_virt := $(call as-instr,.arch_extension virt,+virt) +ifeq ($(plus_virt),+virt) + plus_virt_def := -DREQUIRES_VIRT=1 +endif + +ccflags-y += -Ivirt/kvm -Iarch/arm/kvm +CFLAGS_arm.o := -I. $(plus_virt_def) +CFLAGS_mmu.o := -I. + +AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt) +AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt) + +kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o) + +obj-y += kvm-arm.o init.o interrupts.o +obj-y += arm.o guest.o mmu.o emulate.o reset.o +obj-y += coproc.o coproc_a15.o mmio.o psci.o diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c new file mode 100644 index 00000000000..2d30e3afdaf --- /dev/null +++ b/arch/arm/kvm/arm.c @@ -0,0 +1,1015 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/kvm_host.h> +#include <linux/module.h> +#include <linux/vmalloc.h> +#include <linux/fs.h> +#include <linux/mman.h> +#include <linux/sched.h> +#include <linux/kvm.h> +#include <trace/events/kvm.h> + +#define CREATE_TRACE_POINTS +#include "trace.h" + +#include <asm/unified.h> +#include <asm/uaccess.h> +#include <asm/ptrace.h> +#include <asm/mman.h> +#include <asm/cputype.h> +#include <asm/tlbflush.h> +#include <asm/cacheflush.h> +#include <asm/virt.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_mmu.h> +#include <asm/kvm_emulate.h> +#include <asm/kvm_coproc.h> +#include <asm/kvm_psci.h> +#include <asm/opcodes.h> + +#ifdef REQUIRES_VIRT +__asm__(".arch_extension virt"); +#endif + +static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page); +static struct vfp_hard_struct __percpu *kvm_host_vfp_state; +static unsigned long hyp_default_vectors; + +/* The VMID used in the VTTBR */ +static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1); +static u8 kvm_next_vmid; +static DEFINE_SPINLOCK(kvm_vmid_lock); + +int kvm_arch_hardware_enable(void *garbage) +{ + return 0; +} + +int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) +{ + return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; +} + +void kvm_arch_hardware_disable(void *garbage) +{ +} + +int kvm_arch_hardware_setup(void) +{ + return 0; +} + +void kvm_arch_hardware_unsetup(void) +{ +} + +void kvm_arch_check_processor_compat(void *rtn) +{ + *(int *)rtn = 0; +} + +void kvm_arch_sync_events(struct kvm *kvm) +{ +} + +/** + * kvm_arch_init_vm - initializes a VM data structure + * @kvm: pointer to the KVM struct + */ +int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) +{ + int ret = 0; + + if (type) + return -EINVAL; + + ret = kvm_alloc_stage2_pgd(kvm); + if (ret) + goto out_fail_alloc; + + ret = create_hyp_mappings(kvm, kvm + 1); + if (ret) + goto out_free_stage2_pgd; + + /* Mark the initial VMID generation invalid */ + kvm->arch.vmid_gen = 0; + + return ret; +out_free_stage2_pgd: + kvm_free_stage2_pgd(kvm); +out_fail_alloc: + return ret; +} + +int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) +{ + return VM_FAULT_SIGBUS; +} + +void kvm_arch_free_memslot(struct kvm_memory_slot *free, + struct kvm_memory_slot *dont) +{ +} + +int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages) +{ + return 0; +} + +/** + * kvm_arch_destroy_vm - destroy the VM data structure + * @kvm: pointer to the KVM struct + */ +void kvm_arch_destroy_vm(struct kvm *kvm) +{ + int i; + + kvm_free_stage2_pgd(kvm); + + for (i = 0; i < KVM_MAX_VCPUS; ++i) { + if (kvm->vcpus[i]) { + kvm_arch_vcpu_free(kvm->vcpus[i]); + kvm->vcpus[i] = NULL; + } + } +} + +int kvm_dev_ioctl_check_extension(long ext) +{ + int r; + switch (ext) { + case KVM_CAP_USER_MEMORY: + case KVM_CAP_SYNC_MMU: + case KVM_CAP_DESTROY_MEMORY_REGION_WORKS: + case KVM_CAP_ONE_REG: + case KVM_CAP_ARM_PSCI: + r = 1; + break; + case KVM_CAP_COALESCED_MMIO: + r = KVM_COALESCED_MMIO_PAGE_OFFSET; + break; + case KVM_CAP_NR_VCPUS: + r = num_online_cpus(); + break; + case KVM_CAP_MAX_VCPUS: + r = KVM_MAX_VCPUS; + break; + default: + r = 0; + break; + } + return r; +} + +long kvm_arch_dev_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + return -EINVAL; +} + +int kvm_arch_set_memory_region(struct kvm *kvm, + struct kvm_userspace_memory_region *mem, + struct kvm_memory_slot old, + int user_alloc) +{ + return 0; +} + +int kvm_arch_prepare_memory_region(struct kvm *kvm, + struct kvm_memory_slot *memslot, + struct kvm_memory_slot old, + struct kvm_userspace_memory_region *mem, + int user_alloc) +{ + return 0; +} + +void kvm_arch_commit_memory_region(struct kvm *kvm, + struct kvm_userspace_memory_region *mem, + struct kvm_memory_slot old, + int user_alloc) +{ +} + +void kvm_arch_flush_shadow_all(struct kvm *kvm) +{ +} + +void kvm_arch_flush_shadow_memslot(struct kvm *kvm, + struct kvm_memory_slot *slot) +{ +} + +struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) +{ + int err; + struct kvm_vcpu *vcpu; + + vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); + if (!vcpu) { + err = -ENOMEM; + goto out; + } + + err = kvm_vcpu_init(vcpu, kvm, id); + if (err) + goto free_vcpu; + + err = create_hyp_mappings(vcpu, vcpu + 1); + if (err) + goto vcpu_uninit; + + return vcpu; +vcpu_uninit: + kvm_vcpu_uninit(vcpu); +free_vcpu: + kmem_cache_free(kvm_vcpu_cache, vcpu); +out: + return ERR_PTR(err); +} + +int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) +{ + return 0; +} + +void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) +{ + kvm_mmu_free_memory_caches(vcpu); + kmem_cache_free(kvm_vcpu_cache, vcpu); +} + +void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) +{ + kvm_arch_vcpu_free(vcpu); +} + +int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) +{ + return 0; +} + +int __attribute_const__ kvm_target_cpu(void) +{ + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); + + if (implementor != ARM_CPU_IMP_ARM) + return -EINVAL; + + switch (part_number) { + case ARM_CPU_PART_CORTEX_A15: + return KVM_ARM_TARGET_CORTEX_A15; + default: + return -EINVAL; + } +} + +int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) +{ + /* Force users to call KVM_ARM_VCPU_INIT */ + vcpu->arch.target = -1; + return 0; +} + +void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) +{ +} + +void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + vcpu->cpu = cpu; + vcpu->arch.vfp_host = this_cpu_ptr(kvm_host_vfp_state); + + /* + * Check whether this vcpu requires the cache to be flushed on + * this physical CPU. This is a consequence of doing dcache + * operations by set/way on this vcpu. We do it here to be in + * a non-preemptible section. + */ + if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush)) + flush_cache_all(); /* We'd really want v7_flush_dcache_all() */ +} + +void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) +{ +} + +int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, + struct kvm_guest_debug *dbg) +{ + return -EINVAL; +} + + +int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, + struct kvm_mp_state *mp_state) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, + struct kvm_mp_state *mp_state) +{ + return -EINVAL; +} + +/** + * kvm_arch_vcpu_runnable - determine if the vcpu can be scheduled + * @v: The VCPU pointer + * + * If the guest CPU is not waiting for interrupts or an interrupt line is + * asserted, the CPU is by definition runnable. + */ +int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) +{ + return !!v->arch.irq_lines; +} + +/* Just ensure a guest exit from a particular CPU */ +static void exit_vm_noop(void *info) +{ +} + +void force_vm_exit(const cpumask_t *mask) +{ + smp_call_function_many(mask, exit_vm_noop, NULL, true); +} + +/** + * need_new_vmid_gen - check that the VMID is still valid + * @kvm: The VM's VMID to checkt + * + * return true if there is a new generation of VMIDs being used + * + * The hardware supports only 256 values with the value zero reserved for the + * host, so we check if an assigned value belongs to a previous generation, + * which which requires us to assign a new value. If we're the first to use a + * VMID for the new generation, we must flush necessary caches and TLBs on all + * CPUs. + */ +static bool need_new_vmid_gen(struct kvm *kvm) +{ + return unlikely(kvm->arch.vmid_gen != atomic64_read(&kvm_vmid_gen)); +} + +/** + * update_vttbr - Update the VTTBR with a valid VMID before the guest runs + * @kvm The guest that we are about to run + * + * Called from kvm_arch_vcpu_ioctl_run before entering the guest to ensure the + * VM has a valid VMID, otherwise assigns a new one and flushes corresponding + * caches and TLBs. + */ +static void update_vttbr(struct kvm *kvm) +{ + phys_addr_t pgd_phys; + u64 vmid; + + if (!need_new_vmid_gen(kvm)) + return; + + spin_lock(&kvm_vmid_lock); + + /* + * We need to re-check the vmid_gen here to ensure that if another vcpu + * already allocated a valid vmid for this vm, then this vcpu should + * use the same vmid. + */ + if (!need_new_vmid_gen(kvm)) { + spin_unlock(&kvm_vmid_lock); + return; + } + + /* First user of a new VMID generation? */ + if (unlikely(kvm_next_vmid == 0)) { + atomic64_inc(&kvm_vmid_gen); + kvm_next_vmid = 1; + + /* + * On SMP we know no other CPUs can use this CPU's or each + * other's VMID after force_vm_exit returns since the + * kvm_vmid_lock blocks them from reentry to the guest. + */ + force_vm_exit(cpu_all_mask); + /* + * Now broadcast TLB + ICACHE invalidation over the inner + * shareable domain to make sure all data structures are + * clean. + */ + kvm_call_hyp(__kvm_flush_vm_context); + } + + kvm->arch.vmid_gen = atomic64_read(&kvm_vmid_gen); + kvm->arch.vmid = kvm_next_vmid; + kvm_next_vmid++; + + /* update vttbr to be used with the new vmid */ + pgd_phys = virt_to_phys(kvm->arch.pgd); + vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK; + kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK; + kvm->arch.vttbr |= vmid; + + spin_unlock(&kvm_vmid_lock); +} + +static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + /* SVC called from Hyp mode should never get here */ + kvm_debug("SVC called from Hyp mode shouldn't go here\n"); + BUG(); + return -EINVAL; /* Squash warning */ +} + +static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0), + vcpu->arch.hsr & HSR_HVC_IMM_MASK); + + if (kvm_psci_call(vcpu)) + return 1; + + kvm_inject_undefined(vcpu); + return 1; +} + +static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + if (kvm_psci_call(vcpu)) + return 1; + + kvm_inject_undefined(vcpu); + return 1; +} + +static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + /* The hypervisor should never cause aborts */ + kvm_err("Prefetch Abort taken from Hyp mode at %#08x (HSR: %#08x)\n", + vcpu->arch.hxfar, vcpu->arch.hsr); + return -EFAULT; +} + +static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + /* This is either an error in the ws. code or an external abort */ + kvm_err("Data Abort taken from Hyp mode at %#08x (HSR: %#08x)\n", + vcpu->arch.hxfar, vcpu->arch.hsr); + return -EFAULT; +} + +typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *); +static exit_handle_fn arm_exit_handlers[] = { + [HSR_EC_WFI] = kvm_handle_wfi, + [HSR_EC_CP15_32] = kvm_handle_cp15_32, + [HSR_EC_CP15_64] = kvm_handle_cp15_64, + [HSR_EC_CP14_MR] = kvm_handle_cp14_access, + [HSR_EC_CP14_LS] = kvm_handle_cp14_load_store, + [HSR_EC_CP14_64] = kvm_handle_cp14_access, + [HSR_EC_CP_0_13] = kvm_handle_cp_0_13_access, + [HSR_EC_CP10_ID] = kvm_handle_cp10_id, + [HSR_EC_SVC_HYP] = handle_svc_hyp, + [HSR_EC_HVC] = handle_hvc, + [HSR_EC_SMC] = handle_smc, + [HSR_EC_IABT] = kvm_handle_guest_abort, + [HSR_EC_IABT_HYP] = handle_pabt_hyp, + [HSR_EC_DABT] = kvm_handle_guest_abort, + [HSR_EC_DABT_HYP] = handle_dabt_hyp, +}; + +/* + * A conditional instruction is allowed to trap, even though it + * wouldn't be executed. So let's re-implement the hardware, in + * software! + */ +static bool kvm_condition_valid(struct kvm_vcpu *vcpu) +{ + unsigned long cpsr, cond, insn; + + /* + * Exception Code 0 can only happen if we set HCR.TGE to 1, to + * catch undefined instructions, and then we won't get past + * the arm_exit_handlers test anyway. + */ + BUG_ON(((vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT) == 0); + + /* Top two bits non-zero? Unconditional. */ + if (vcpu->arch.hsr >> 30) + return true; + + cpsr = *vcpu_cpsr(vcpu); + + /* Is condition field valid? */ + if ((vcpu->arch.hsr & HSR_CV) >> HSR_CV_SHIFT) + cond = (vcpu->arch.hsr & HSR_COND) >> HSR_COND_SHIFT; + else { + /* This can happen in Thumb mode: examine IT state. */ + unsigned long it; + + it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3); + + /* it == 0 => unconditional. */ + if (it == 0) + return true; + + /* The cond for this insn works out as the top 4 bits. */ + cond = (it >> 4); + } + + /* Shift makes it look like an ARM-mode instruction */ + insn = cond << 28; + return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL; +} + +/* + * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on + * proper exit to QEMU. + */ +static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, + int exception_index) +{ + unsigned long hsr_ec; + + switch (exception_index) { + case ARM_EXCEPTION_IRQ: + return 1; + case ARM_EXCEPTION_UNDEFINED: + kvm_err("Undefined exception in Hyp mode at: %#08x\n", + vcpu->arch.hyp_pc); + BUG(); + panic("KVM: Hypervisor undefined exception!\n"); + case ARM_EXCEPTION_DATA_ABORT: + case ARM_EXCEPTION_PREF_ABORT: + case ARM_EXCEPTION_HVC: + hsr_ec = (vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT; + + if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) + || !arm_exit_handlers[hsr_ec]) { + kvm_err("Unkown exception class: %#08lx, " + "hsr: %#08x\n", hsr_ec, + (unsigned int)vcpu->arch.hsr); + BUG(); + } + + /* + * See ARM ARM B1.14.1: "Hyp traps on instructions + * that fail their condition code check" + */ + if (!kvm_condition_valid(vcpu)) { + bool is_wide = vcpu->arch.hsr & HSR_IL; + kvm_skip_instr(vcpu, is_wide); + return 1; + } + + return arm_exit_handlers[hsr_ec](vcpu, run); + default: + kvm_pr_unimpl("Unsupported exception type: %d", + exception_index); + run->exit_reason = KVM_EXIT_INTERNAL_ERROR; + return 0; + } +} + +static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu) +{ + if (likely(vcpu->arch.has_run_once)) + return 0; + + vcpu->arch.has_run_once = true; + + /* + * Handle the "start in power-off" case by calling into the + * PSCI code. + */ + if (test_and_clear_bit(KVM_ARM_VCPU_POWER_OFF, vcpu->arch.features)) { + *vcpu_reg(vcpu, 0) = KVM_PSCI_FN_CPU_OFF; + kvm_psci_call(vcpu); + } + + return 0; +} + +static void vcpu_pause(struct kvm_vcpu *vcpu) +{ + wait_queue_head_t *wq = kvm_arch_vcpu_wq(vcpu); + + wait_event_interruptible(*wq, !vcpu->arch.pause); +} + +/** + * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code + * @vcpu: The VCPU pointer + * @run: The kvm_run structure pointer used for userspace state exchange + * + * This function is called through the VCPU_RUN ioctl called from user space. It + * will execute VM code in a loop until the time slice for the process is used + * or some emulation is needed from user space in which case the function will + * return with return value 0 and with the kvm_run structure filled in with the + * required data for the requested emulation. + */ +int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + int ret; + sigset_t sigsaved; + + /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */ + if (unlikely(vcpu->arch.target < 0)) + return -ENOEXEC; + + ret = kvm_vcpu_first_run_init(vcpu); + if (ret) + return ret; + + if (run->exit_reason == KVM_EXIT_MMIO) { + ret = kvm_handle_mmio_return(vcpu, vcpu->run); + if (ret) + return ret; + } + + if (vcpu->sigset_active) + sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); + + ret = 1; + run->exit_reason = KVM_EXIT_UNKNOWN; + while (ret > 0) { + /* + * Check conditions before entering the guest + */ + cond_resched(); + + update_vttbr(vcpu->kvm); + + if (vcpu->arch.pause) + vcpu_pause(vcpu); + + local_irq_disable(); + + /* + * Re-check atomic conditions + */ + if (signal_pending(current)) { + ret = -EINTR; + run->exit_reason = KVM_EXIT_INTR; + } + + if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) { + local_irq_enable(); + continue; + } + + /************************************************************** + * Enter the guest + */ + trace_kvm_entry(*vcpu_pc(vcpu)); + kvm_guest_enter(); + vcpu->mode = IN_GUEST_MODE; + + ret = kvm_call_hyp(__kvm_vcpu_run, vcpu); + + vcpu->mode = OUTSIDE_GUEST_MODE; + vcpu->arch.last_pcpu = smp_processor_id(); + kvm_guest_exit(); + trace_kvm_exit(*vcpu_pc(vcpu)); + /* + * We may have taken a host interrupt in HYP mode (ie + * while executing the guest). This interrupt is still + * pending, as we haven't serviced it yet! + * + * We're now back in SVC mode, with interrupts + * disabled. Enabling the interrupts now will have + * the effect of taking the interrupt again, in SVC + * mode this time. + */ + local_irq_enable(); + + /* + * Back from guest + *************************************************************/ + + ret = handle_exit(vcpu, run, ret); + } + + if (vcpu->sigset_active) + sigprocmask(SIG_SETMASK, &sigsaved, NULL); + return ret; +} + +static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level) +{ + int bit_index; + bool set; + unsigned long *ptr; + + if (number == KVM_ARM_IRQ_CPU_IRQ) + bit_index = __ffs(HCR_VI); + else /* KVM_ARM_IRQ_CPU_FIQ */ + bit_index = __ffs(HCR_VF); + + ptr = (unsigned long *)&vcpu->arch.irq_lines; + if (level) + set = test_and_set_bit(bit_index, ptr); + else + set = test_and_clear_bit(bit_index, ptr); + + /* + * If we didn't change anything, no need to wake up or kick other CPUs + */ + if (set == level) + return 0; + + /* + * The vcpu irq_lines field was updated, wake up sleeping VCPUs and + * trigger a world-switch round on the running physical CPU to set the + * virtual IRQ/FIQ fields in the HCR appropriately. + */ + kvm_vcpu_kick(vcpu); + + return 0; +} + +int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level) +{ + u32 irq = irq_level->irq; + unsigned int irq_type, vcpu_idx, irq_num; + int nrcpus = atomic_read(&kvm->online_vcpus); + struct kvm_vcpu *vcpu = NULL; + bool level = irq_level->level; + + irq_type = (irq >> KVM_ARM_IRQ_TYPE_SHIFT) & KVM_ARM_IRQ_TYPE_MASK; + vcpu_idx = (irq >> KVM_ARM_IRQ_VCPU_SHIFT) & KVM_ARM_IRQ_VCPU_MASK; + irq_num = (irq >> KVM_ARM_IRQ_NUM_SHIFT) & KVM_ARM_IRQ_NUM_MASK; + + trace_kvm_irq_line(irq_type, vcpu_idx, irq_num, irq_level->level); + + if (irq_type != KVM_ARM_IRQ_TYPE_CPU) + return -EINVAL; + + if (vcpu_idx >= nrcpus) + return -EINVAL; + + vcpu = kvm_get_vcpu(kvm, vcpu_idx); + if (!vcpu) + return -EINVAL; + + if (irq_num > KVM_ARM_IRQ_CPU_FIQ) + return -EINVAL; + + return vcpu_interrupt_line(vcpu, irq_num, level); +} + +long kvm_arch_vcpu_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + struct kvm_vcpu *vcpu = filp->private_data; + void __user *argp = (void __user *)arg; + + switch (ioctl) { + case KVM_ARM_VCPU_INIT: { + struct kvm_vcpu_init init; + + if (copy_from_user(&init, argp, sizeof(init))) + return -EFAULT; + + return kvm_vcpu_set_target(vcpu, &init); + + } + case KVM_SET_ONE_REG: + case KVM_GET_ONE_REG: { + struct kvm_one_reg reg; + if (copy_from_user(®, argp, sizeof(reg))) + return -EFAULT; + if (ioctl == KVM_SET_ONE_REG) + return kvm_arm_set_reg(vcpu, ®); + else + return kvm_arm_get_reg(vcpu, ®); + } + case KVM_GET_REG_LIST: { + struct kvm_reg_list __user *user_list = argp; + struct kvm_reg_list reg_list; + unsigned n; + + if (copy_from_user(®_list, user_list, sizeof(reg_list))) + return -EFAULT; + n = reg_list.n; + reg_list.n = kvm_arm_num_regs(vcpu); + if (copy_to_user(user_list, ®_list, sizeof(reg_list))) + return -EFAULT; + if (n < reg_list.n) + return -E2BIG; + return kvm_arm_copy_reg_indices(vcpu, user_list->reg); + } + default: + return -EINVAL; + } +} + +int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) +{ + return -EINVAL; +} + +long kvm_arch_vm_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + return -EINVAL; +} + +static void cpu_init_hyp_mode(void *vector) +{ + unsigned long long pgd_ptr; + unsigned long pgd_low, pgd_high; + unsigned long hyp_stack_ptr; + unsigned long stack_page; + unsigned long vector_ptr; + + /* Switch from the HYP stub to our own HYP init vector */ + __hyp_set_vectors((unsigned long)vector); + + pgd_ptr = (unsigned long long)kvm_mmu_get_httbr(); + pgd_low = (pgd_ptr & ((1ULL << 32) - 1)); + pgd_high = (pgd_ptr >> 32ULL); + stack_page = __get_cpu_var(kvm_arm_hyp_stack_page); + hyp_stack_ptr = stack_page + PAGE_SIZE; + vector_ptr = (unsigned long)__kvm_hyp_vector; + + /* + * Call initialization code, and switch to the full blown + * HYP code. The init code doesn't need to preserve these registers as + * r1-r3 and r12 are already callee save according to the AAPCS. + * Note that we slightly misuse the prototype by casing the pgd_low to + * a void *. + */ + kvm_call_hyp((void *)pgd_low, pgd_high, hyp_stack_ptr, vector_ptr); +} + +/** + * Inits Hyp-mode on all online CPUs + */ +static int init_hyp_mode(void) +{ + phys_addr_t init_phys_addr; + int cpu; + int err = 0; + + /* + * Allocate Hyp PGD and setup Hyp identity mapping + */ + err = kvm_mmu_init(); + if (err) + goto out_err; + + /* + * It is probably enough to obtain the default on one + * CPU. It's unlikely to be different on the others. + */ + hyp_default_vectors = __hyp_get_vectors(); + + /* + * Allocate stack pages for Hypervisor-mode + */ + for_each_possible_cpu(cpu) { + unsigned long stack_page; + + stack_page = __get_free_page(GFP_KERNEL); + if (!stack_page) { + err = -ENOMEM; + goto out_free_stack_pages; + } + + per_cpu(kvm_arm_hyp_stack_page, cpu) = stack_page; + } + + /* + * Execute the init code on each CPU. + * + * Note: The stack is not mapped yet, so don't do anything else than + * initializing the hypervisor mode on each CPU using a local stack + * space for temporary storage. + */ + init_phys_addr = virt_to_phys(__kvm_hyp_init); + for_each_online_cpu(cpu) { + smp_call_function_single(cpu, cpu_init_hyp_mode, + (void *)(long)init_phys_addr, 1); + } + + /* + * Unmap the identity mapping + */ + kvm_clear_hyp_idmap(); + + /* + * Map the Hyp-code called directly from the host + */ + err = create_hyp_mappings(__kvm_hyp_code_start, __kvm_hyp_code_end); + if (err) { + kvm_err("Cannot map world-switch code\n"); + goto out_free_mappings; + } + + /* + * Map the Hyp stack pages + */ + for_each_possible_cpu(cpu) { + char *stack_page = (char *)per_cpu(kvm_arm_hyp_stack_page, cpu); + err = create_hyp_mappings(stack_page, stack_page + PAGE_SIZE); + + if (err) { + kvm_err("Cannot map hyp stack\n"); + goto out_free_mappings; + } + } + + /* + * Map the host VFP structures + */ + kvm_host_vfp_state = alloc_percpu(struct vfp_hard_struct); + if (!kvm_host_vfp_state) { + err = -ENOMEM; + kvm_err("Cannot allocate host VFP state\n"); + goto out_free_mappings; + } + + for_each_possible_cpu(cpu) { + struct vfp_hard_struct *vfp; + + vfp = per_cpu_ptr(kvm_host_vfp_state, cpu); + err = create_hyp_mappings(vfp, vfp + 1); + + if (err) { + kvm_err("Cannot map host VFP state: %d\n", err); + goto out_free_vfp; + } + } + + kvm_info("Hyp mode initialized successfully\n"); + return 0; +out_free_vfp: + free_percpu(kvm_host_vfp_state); +out_free_mappings: + free_hyp_pmds(); +out_free_stack_pages: + for_each_possible_cpu(cpu) + free_page(per_cpu(kvm_arm_hyp_stack_page, cpu)); +out_err: + kvm_err("error initializing Hyp mode: %d\n", err); + return err; +} + +/** + * Initialize Hyp-mode and memory mappings on all CPUs. + */ +int kvm_arch_init(void *opaque) +{ + int err; + + if (!is_hyp_mode_available()) { + kvm_err("HYP mode not available\n"); + return -ENODEV; + } + + if (kvm_target_cpu() < 0) { + kvm_err("Target CPU not supported!\n"); + return -ENODEV; + } + + err = init_hyp_mode(); + if (err) + goto out_err; + + kvm_coproc_table_init(); + return 0; +out_err: + return err; +} + +/* NOP: Compiling as a module not supported */ +void kvm_arch_exit(void) +{ +} + +static int arm_init(void) +{ + int rc = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); + return rc; +} + +module_init(arm_init); diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c new file mode 100644 index 00000000000..d782638c7ec --- /dev/null +++ b/arch/arm/kvm/coproc.c @@ -0,0 +1,1046 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Authors: Rusty Russell <rusty@rustcorp.com.au> + * Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#include <linux/mm.h> +#include <linux/kvm_host.h> +#include <linux/uaccess.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_host.h> +#include <asm/kvm_emulate.h> +#include <asm/kvm_coproc.h> +#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <trace/events/kvm.h> +#include <asm/vfp.h> +#include "../vfp/vfpinstr.h" + +#include "trace.h" +#include "coproc.h" + + +/****************************************************************************** + * Co-processor emulation + *****************************************************************************/ + +/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ +static u32 cache_levels; + +/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ +#define CSSELR_MAX 12 + +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + kvm_inject_undefined(vcpu); + return 1; +} + +int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + /* + * We can get here, if the host has been built without VFPv3 support, + * but the guest attempted a floating point operation. + */ + kvm_inject_undefined(vcpu); + return 1; +} + +int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + kvm_inject_undefined(vcpu); + return 1; +} + +int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + kvm_inject_undefined(vcpu); + return 1; +} + +/* See note at ARM ARM B1.14.4 */ +static bool access_dcsw(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + u32 val; + int cpu; + + cpu = get_cpu(); + + if (!p->is_write) + return read_from_write_only(vcpu, p); + + cpumask_setall(&vcpu->arch.require_dcache_flush); + cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush); + + /* If we were already preempted, take the long way around */ + if (cpu != vcpu->arch.last_pcpu) { + flush_cache_all(); + goto done; + } + + val = *vcpu_reg(vcpu, p->Rt1); + + switch (p->CRm) { + case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */ + case 14: /* DCCISW */ + asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val)); + break; + + case 10: /* DCCSW */ + asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val)); + break; + } + +done: + put_cpu(); + + return true; +} + +/* + * We could trap ID_DFR0 and tell the guest we don't support performance + * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was + * NAKed, so it will read the PMCR anyway. + * + * Therefore we tell the guest we have 0 counters. Unfortunately, we + * must always support PMCCNTR (the cycle counter): we just RAZ/WI for + * all PM registers, which doesn't crash the guest kernel at least. + */ +static bool pm_fake(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + else + return read_zero(vcpu, p); +} + +#define access_pmcr pm_fake +#define access_pmcntenset pm_fake +#define access_pmcntenclr pm_fake +#define access_pmovsr pm_fake +#define access_pmselr pm_fake +#define access_pmceid0 pm_fake +#define access_pmceid1 pm_fake +#define access_pmccntr pm_fake +#define access_pmxevtyper pm_fake +#define access_pmxevcntr pm_fake +#define access_pmuserenr pm_fake +#define access_pmintenset pm_fake +#define access_pmintenclr pm_fake + +/* Architected CP15 registers. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 + */ +static const struct coproc_reg cp15_regs[] = { + /* CSSELR: swapped by interrupt.S. */ + { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32, + NULL, reset_unknown, c0_CSSELR }, + + /* TTBR0/TTBR1: swapped by interrupt.S. */ + { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, + { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, + + /* TTBCR: swapped by interrupt.S. */ + { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, + NULL, reset_val, c2_TTBCR, 0x00000000 }, + + /* DACR: swapped by interrupt.S. */ + { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32, + NULL, reset_unknown, c3_DACR }, + + /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */ + { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32, + NULL, reset_unknown, c5_DFSR }, + { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32, + NULL, reset_unknown, c5_IFSR }, + { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32, + NULL, reset_unknown, c5_ADFSR }, + { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32, + NULL, reset_unknown, c5_AIFSR }, + + /* DFAR/IFAR: swapped by interrupt.S. */ + { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32, + NULL, reset_unknown, c6_DFAR }, + { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32, + NULL, reset_unknown, c6_IFAR }, + /* + * DC{C,I,CI}SW operations: + */ + { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw}, + { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw}, + { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw}, + /* + * Dummy performance monitor implementation. + */ + { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset}, + { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr}, + { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0}, + { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1}, + { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr}, + { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper}, + { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr}, + { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr}, + { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset}, + { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr}, + + /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */ + { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32, + NULL, reset_unknown, c10_PRRR}, + { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32, + NULL, reset_unknown, c10_NMRR}, + + /* VBAR: swapped by interrupt.S. */ + { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, + NULL, reset_val, c12_VBAR, 0x00000000 }, + + /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */ + { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32, + NULL, reset_val, c13_CID, 0x00000000 }, + { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32, + NULL, reset_unknown, c13_TID_URW }, + { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32, + NULL, reset_unknown, c13_TID_URO }, + { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32, + NULL, reset_unknown, c13_TID_PRIV }, +}; + +/* Target specific emulation tables */ +static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS]; + +void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table) +{ + target_tables[table->target] = table; +} + +/* Get specific register table for this target. */ +static const struct coproc_reg *get_target_table(unsigned target, size_t *num) +{ + struct kvm_coproc_target_table *table; + + table = target_tables[target]; + *num = table->num; + return table->table; +} + +static const struct coproc_reg *find_reg(const struct coproc_params *params, + const struct coproc_reg table[], + unsigned int num) +{ + unsigned int i; + + for (i = 0; i < num; i++) { + const struct coproc_reg *r = &table[i]; + + if (params->is_64bit != r->is_64) + continue; + if (params->CRn != r->CRn) + continue; + if (params->CRm != r->CRm) + continue; + if (params->Op1 != r->Op1) + continue; + if (params->Op2 != r->Op2) + continue; + + return r; + } + return NULL; +} + +static int emulate_cp15(struct kvm_vcpu *vcpu, + const struct coproc_params *params) +{ + size_t num; + const struct coproc_reg *table, *r; + + trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn, + params->CRm, params->Op2, params->is_write); + + table = get_target_table(vcpu->arch.target, &num); + + /* Search target-specific then generic table. */ + r = find_reg(params, table, num); + if (!r) + r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs)); + + if (likely(r)) { + /* If we don't have an accessor, we should never get here! */ + BUG_ON(!r->access); + + if (likely(r->access(vcpu, params, r))) { + /* Skip instruction, since it was emulated */ + kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1); + return 1; + } + /* If access function fails, it should complain. */ + } else { + kvm_err("Unsupported guest CP15 access at: %08x\n", + *vcpu_pc(vcpu)); + print_cp_instr(params); + } + kvm_inject_undefined(vcpu); + return 1; +} + +/** + * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access + * @vcpu: The VCPU pointer + * @run: The kvm_run struct + */ +int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct coproc_params params; + + params.CRm = (vcpu->arch.hsr >> 1) & 0xf; + params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf; + params.is_write = ((vcpu->arch.hsr & 1) == 0); + params.is_64bit = true; + + params.Op1 = (vcpu->arch.hsr >> 16) & 0xf; + params.Op2 = 0; + params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf; + params.CRn = 0; + + return emulate_cp15(vcpu, ¶ms); +} + +static void reset_coproc_regs(struct kvm_vcpu *vcpu, + const struct coproc_reg *table, size_t num) +{ + unsigned long i; + + for (i = 0; i < num; i++) + if (table[i].reset) + table[i].reset(vcpu, &table[i]); +} + +/** + * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access + * @vcpu: The VCPU pointer + * @run: The kvm_run struct + */ +int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + struct coproc_params params; + + params.CRm = (vcpu->arch.hsr >> 1) & 0xf; + params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf; + params.is_write = ((vcpu->arch.hsr & 1) == 0); + params.is_64bit = false; + + params.CRn = (vcpu->arch.hsr >> 10) & 0xf; + params.Op1 = (vcpu->arch.hsr >> 14) & 0x7; + params.Op2 = (vcpu->arch.hsr >> 17) & 0x7; + params.Rt2 = 0; + + return emulate_cp15(vcpu, ¶ms); +} + +/****************************************************************************** + * Userspace API + *****************************************************************************/ + +static bool index_to_params(u64 id, struct coproc_params *params) +{ + switch (id & KVM_REG_SIZE_MASK) { + case KVM_REG_SIZE_U32: + /* Any unused index bits means it's not valid. */ + if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK + | KVM_REG_ARM_COPROC_MASK + | KVM_REG_ARM_32_CRN_MASK + | KVM_REG_ARM_CRM_MASK + | KVM_REG_ARM_OPC1_MASK + | KVM_REG_ARM_32_OPC2_MASK)) + return false; + + params->is_64bit = false; + params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK) + >> KVM_REG_ARM_32_CRN_SHIFT); + params->CRm = ((id & KVM_REG_ARM_CRM_MASK) + >> KVM_REG_ARM_CRM_SHIFT); + params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) + >> KVM_REG_ARM_OPC1_SHIFT); + params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK) + >> KVM_REG_ARM_32_OPC2_SHIFT); + return true; + case KVM_REG_SIZE_U64: + /* Any unused index bits means it's not valid. */ + if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK + | KVM_REG_ARM_COPROC_MASK + | KVM_REG_ARM_CRM_MASK + | KVM_REG_ARM_OPC1_MASK)) + return false; + params->is_64bit = true; + params->CRm = ((id & KVM_REG_ARM_CRM_MASK) + >> KVM_REG_ARM_CRM_SHIFT); + params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) + >> KVM_REG_ARM_OPC1_SHIFT); + params->Op2 = 0; + params->CRn = 0; + return true; + default: + return false; + } +} + +/* Decode an index value, and find the cp15 coproc_reg entry. */ +static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu, + u64 id) +{ + size_t num; + const struct coproc_reg *table, *r; + struct coproc_params params; + + /* We only do cp15 for now. */ + if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15) + return NULL; + + if (!index_to_params(id, ¶ms)) + return NULL; + + table = get_target_table(vcpu->arch.target, &num); + r = find_reg(¶ms, table, num); + if (!r) + r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); + + /* Not saved in the cp15 array? */ + if (r && !r->reg) + r = NULL; + + return r; +} + +/* + * These are the invariant cp15 registers: we let the guest see the host + * versions of these, so they're part of the guest state. + * + * A future CPU may provide a mechanism to present different values to + * the guest, or a future kvm may trap them. + */ +/* Unfortunately, there's no register-argument for mrc, so generate. */ +#define FUNCTION_FOR32(crn, crm, op1, op2, name) \ + static void get_##name(struct kvm_vcpu *v, \ + const struct coproc_reg *r) \ + { \ + u32 val; \ + \ + asm volatile("mrc p15, " __stringify(op1) \ + ", %0, c" __stringify(crn) \ + ", c" __stringify(crm) \ + ", " __stringify(op2) "\n" : "=r" (val)); \ + ((struct coproc_reg *)r)->val = val; \ + } + +FUNCTION_FOR32(0, 0, 0, 0, MIDR) +FUNCTION_FOR32(0, 0, 0, 1, CTR) +FUNCTION_FOR32(0, 0, 0, 2, TCMTR) +FUNCTION_FOR32(0, 0, 0, 3, TLBTR) +FUNCTION_FOR32(0, 0, 0, 6, REVIDR) +FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0) +FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1) +FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0) +FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0) +FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0) +FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1) +FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2) +FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3) +FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0) +FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1) +FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2) +FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3) +FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4) +FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5) +FUNCTION_FOR32(0, 0, 1, 1, CLIDR) +FUNCTION_FOR32(0, 0, 1, 7, AIDR) + +/* ->val is filled in by kvm_invariant_coproc_table_init() */ +static struct coproc_reg invariant_cp15[] = { + { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR }, + { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR }, + { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR }, + { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR }, + { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR }, + + { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 }, + { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 }, + + { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 }, + { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 }, + { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 }, + { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 }, + { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 }, + { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 }, + + { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR }, + { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR }, +}; + +static int reg_from_user(void *val, const void __user *uaddr, u64 id) +{ + /* This Just Works because we are little endian. */ + if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) + return -EFAULT; + return 0; +} + +static int reg_to_user(void __user *uaddr, const void *val, u64 id) +{ + /* This Just Works because we are little endian. */ + if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) + return -EFAULT; + return 0; +} + +static int get_invariant_cp15(u64 id, void __user *uaddr) +{ + struct coproc_params params; + const struct coproc_reg *r; + + if (!index_to_params(id, ¶ms)) + return -ENOENT; + + r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15)); + if (!r) + return -ENOENT; + + return reg_to_user(uaddr, &r->val, id); +} + +static int set_invariant_cp15(u64 id, void __user *uaddr) +{ + struct coproc_params params; + const struct coproc_reg *r; + int err; + u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ + + if (!index_to_params(id, ¶ms)) + return -ENOENT; + r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15)); + if (!r) + return -ENOENT; + + err = reg_from_user(&val, uaddr, id); + if (err) + return err; + + /* This is what we mean by invariant: you can't change it. */ + if (r->val != val) + return -EINVAL; + + return 0; +} + +static bool is_valid_cache(u32 val) +{ + u32 level, ctype; + + if (val >= CSSELR_MAX) + return -ENOENT; + + /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ + level = (val >> 1); + ctype = (cache_levels >> (level * 3)) & 7; + + switch (ctype) { + case 0: /* No cache */ + return false; + case 1: /* Instruction cache only */ + return (val & 1); + case 2: /* Data cache only */ + case 4: /* Unified cache */ + return !(val & 1); + case 3: /* Separate instruction and data caches */ + return true; + default: /* Reserved: we can't know instruction or data. */ + return false; + } +} + +/* Which cache CCSIDR represents depends on CSSELR value. */ +static u32 get_ccsidr(u32 csselr) +{ + u32 ccsidr; + + /* Make sure noone else changes CSSELR during this! */ + local_irq_disable(); + /* Put value into CSSELR */ + asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); + isb(); + /* Read result out of CCSIDR */ + asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); + local_irq_enable(); + + return ccsidr; +} + +static int demux_c15_get(u64 id, void __user *uaddr) +{ + u32 val; + u32 __user *uval = uaddr; + + /* Fail if we have unknown bits set. */ + if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK + | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) + return -ENOENT; + + switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { + case KVM_REG_ARM_DEMUX_ID_CCSIDR: + if (KVM_REG_SIZE(id) != 4) + return -ENOENT; + val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) + >> KVM_REG_ARM_DEMUX_VAL_SHIFT; + if (!is_valid_cache(val)) + return -ENOENT; + + return put_user(get_ccsidr(val), uval); + default: + return -ENOENT; + } +} + +static int demux_c15_set(u64 id, void __user *uaddr) +{ + u32 val, newval; + u32 __user *uval = uaddr; + + /* Fail if we have unknown bits set. */ + if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK + | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) + return -ENOENT; + + switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { + case KVM_REG_ARM_DEMUX_ID_CCSIDR: + if (KVM_REG_SIZE(id) != 4) + return -ENOENT; + val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) + >> KVM_REG_ARM_DEMUX_VAL_SHIFT; + if (!is_valid_cache(val)) + return -ENOENT; + + if (get_user(newval, uval)) + return -EFAULT; + + /* This is also invariant: you can't change it. */ + if (newval != get_ccsidr(val)) + return -EINVAL; + return 0; + default: + return -ENOENT; + } +} + +#ifdef CONFIG_VFPv3 +static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC, + KVM_REG_ARM_VFP_FPSCR, + KVM_REG_ARM_VFP_FPINST, + KVM_REG_ARM_VFP_FPINST2, + KVM_REG_ARM_VFP_MVFR0, + KVM_REG_ARM_VFP_MVFR1, + KVM_REG_ARM_VFP_FPSID }; + +static unsigned int num_fp_regs(void) +{ + if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2) + return 32; + else + return 16; +} + +static unsigned int num_vfp_regs(void) +{ + /* Normal FP regs + control regs. */ + return num_fp_regs() + ARRAY_SIZE(vfp_sysregs); +} + +static int copy_vfp_regids(u64 __user *uindices) +{ + unsigned int i; + const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP; + const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + + for (i = 0; i < num_fp_regs(); i++) { + if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i, + uindices)) + return -EFAULT; + uindices++; + } + + for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) { + if (put_user(u32reg | vfp_sysregs[i], uindices)) + return -EFAULT; + uindices++; + } + + return num_vfp_regs(); +} + +static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) +{ + u32 vfpid = (id & KVM_REG_ARM_VFP_MASK); + u32 val; + + /* Fail if we have unknown bits set. */ + if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK + | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) + return -ENOENT; + + if (vfpid < num_fp_regs()) { + if (KVM_REG_SIZE(id) != 8) + return -ENOENT; + return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid], + id); + } + + /* FP control registers are all 32 bit. */ + if (KVM_REG_SIZE(id) != 4) + return -ENOENT; + + switch (vfpid) { + case KVM_REG_ARM_VFP_FPEXC: + return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id); + case KVM_REG_ARM_VFP_FPSCR: + return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id); + case KVM_REG_ARM_VFP_FPINST: + return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id); + case KVM_REG_ARM_VFP_FPINST2: + return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id); + case KVM_REG_ARM_VFP_MVFR0: + val = fmrx(MVFR0); + return reg_to_user(uaddr, &val, id); + case KVM_REG_ARM_VFP_MVFR1: + val = fmrx(MVFR1); + return reg_to_user(uaddr, &val, id); + case KVM_REG_ARM_VFP_FPSID: + val = fmrx(FPSID); + return reg_to_user(uaddr, &val, id); + default: + return -ENOENT; + } +} + +static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr) +{ + u32 vfpid = (id & KVM_REG_ARM_VFP_MASK); + u32 val; + + /* Fail if we have unknown bits set. */ + if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK + | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) + return -ENOENT; + + if (vfpid < num_fp_regs()) { + if (KVM_REG_SIZE(id) != 8) + return -ENOENT; + return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid], + uaddr, id); + } + + /* FP control registers are all 32 bit. */ + if (KVM_REG_SIZE(id) != 4) + return -ENOENT; + + switch (vfpid) { + case KVM_REG_ARM_VFP_FPEXC: + return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id); + case KVM_REG_ARM_VFP_FPSCR: + return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id); + case KVM_REG_ARM_VFP_FPINST: + return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id); + case KVM_REG_ARM_VFP_FPINST2: + return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id); + /* These are invariant. */ + case KVM_REG_ARM_VFP_MVFR0: + if (reg_from_user(&val, uaddr, id)) + return -EFAULT; + if (val != fmrx(MVFR0)) + return -EINVAL; + return 0; + case KVM_REG_ARM_VFP_MVFR1: + if (reg_from_user(&val, uaddr, id)) + return -EFAULT; + if (val != fmrx(MVFR1)) + return -EINVAL; + return 0; + case KVM_REG_ARM_VFP_FPSID: + if (reg_from_user(&val, uaddr, id)) + return -EFAULT; + if (val != fmrx(FPSID)) + return -EINVAL; + return 0; + default: + return -ENOENT; + } +} +#else /* !CONFIG_VFPv3 */ +static unsigned int num_vfp_regs(void) +{ + return 0; +} + +static int copy_vfp_regids(u64 __user *uindices) +{ + return 0; +} + +static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) +{ + return -ENOENT; +} + +static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr) +{ + return -ENOENT; +} +#endif /* !CONFIG_VFPv3 */ + +int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + const struct coproc_reg *r; + void __user *uaddr = (void __user *)(long)reg->addr; + + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) + return demux_c15_get(reg->id, uaddr); + + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP) + return vfp_get_reg(vcpu, reg->id, uaddr); + + r = index_to_coproc_reg(vcpu, reg->id); + if (!r) + return get_invariant_cp15(reg->id, uaddr); + + /* Note: copies two regs if size is 64 bit. */ + return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id); +} + +int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + const struct coproc_reg *r; + void __user *uaddr = (void __user *)(long)reg->addr; + + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) + return demux_c15_set(reg->id, uaddr); + + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP) + return vfp_set_reg(vcpu, reg->id, uaddr); + + r = index_to_coproc_reg(vcpu, reg->id); + if (!r) + return set_invariant_cp15(reg->id, uaddr); + + /* Note: copies two regs if size is 64 bit */ + return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id); +} + +static unsigned int num_demux_regs(void) +{ + unsigned int i, count = 0; + + for (i = 0; i < CSSELR_MAX; i++) + if (is_valid_cache(i)) + count++; + + return count; +} + +static int write_demux_regids(u64 __user *uindices) +{ + u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; + unsigned int i; + + val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; + for (i = 0; i < CSSELR_MAX; i++) { + if (!is_valid_cache(i)) + continue; + if (put_user(val | i, uindices)) + return -EFAULT; + uindices++; + } + return 0; +} + +static u64 cp15_to_index(const struct coproc_reg *reg) +{ + u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT); + if (reg->is_64) { + val |= KVM_REG_SIZE_U64; + val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); + val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); + } else { + val |= KVM_REG_SIZE_U32; + val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); + val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT); + val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); + val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT); + } + return val; +} + +static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind) +{ + if (!*uind) + return true; + + if (put_user(cp15_to_index(reg), *uind)) + return false; + + (*uind)++; + return true; +} + +/* Assumed ordered tables, see kvm_coproc_table_init. */ +static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind) +{ + const struct coproc_reg *i1, *i2, *end1, *end2; + unsigned int total = 0; + size_t num; + + /* We check for duplicates here, to allow arch-specific overrides. */ + i1 = get_target_table(vcpu->arch.target, &num); + end1 = i1 + num; + i2 = cp15_regs; + end2 = cp15_regs + ARRAY_SIZE(cp15_regs); + + BUG_ON(i1 == end1 || i2 == end2); + + /* Walk carefully, as both tables may refer to the same register. */ + while (i1 || i2) { + int cmp = cmp_reg(i1, i2); + /* target-specific overrides generic entry. */ + if (cmp <= 0) { + /* Ignore registers we trap but don't save. */ + if (i1->reg) { + if (!copy_reg_to_user(i1, &uind)) + return -EFAULT; + total++; + } + } else { + /* Ignore registers we trap but don't save. */ + if (i2->reg) { + if (!copy_reg_to_user(i2, &uind)) + return -EFAULT; + total++; + } + } + + if (cmp <= 0 && ++i1 == end1) + i1 = NULL; + if (cmp >= 0 && ++i2 == end2) + i2 = NULL; + } + return total; +} + +unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu) +{ + return ARRAY_SIZE(invariant_cp15) + + num_demux_regs() + + num_vfp_regs() + + walk_cp15(vcpu, (u64 __user *)NULL); +} + +int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) +{ + unsigned int i; + int err; + + /* Then give them all the invariant registers' indices. */ + for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) { + if (put_user(cp15_to_index(&invariant_cp15[i]), uindices)) + return -EFAULT; + uindices++; + } + + err = walk_cp15(vcpu, uindices); + if (err < 0) + return err; + uindices += err; + + err = copy_vfp_regids(uindices); + if (err < 0) + return err; + uindices += err; + + return write_demux_regids(uindices); +} + +void kvm_coproc_table_init(void) +{ + unsigned int i; + + /* Make sure tables are unique and in order. */ + for (i = 1; i < ARRAY_SIZE(cp15_regs); i++) + BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0); + + /* We abuse the reset function to overwrite the table itself. */ + for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) + invariant_cp15[i].reset(NULL, &invariant_cp15[i]); + + /* + * CLIDR format is awkward, so clean it up. See ARM B4.1.20: + * + * If software reads the Cache Type fields from Ctype1 + * upwards, once it has seen a value of 0b000, no caches + * exist at further-out levels of the hierarchy. So, for + * example, if Ctype3 is the first Cache Type field with a + * value of 0b000, the values of Ctype4 to Ctype7 must be + * ignored. + */ + asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels)); + for (i = 0; i < 7; i++) + if (((cache_levels >> (i*3)) & 7) == 0) + break; + /* Clear all higher bits. */ + cache_levels &= (1 << (i*3))-1; +} + +/** + * kvm_reset_coprocs - sets cp15 registers to reset value + * @vcpu: The VCPU pointer + * + * This function finds the right table above and sets the registers on the + * virtual CPU struct to their architecturally defined reset values. + */ +void kvm_reset_coprocs(struct kvm_vcpu *vcpu) +{ + size_t num; + const struct coproc_reg *table; + + /* Catch someone adding a register without putting in reset entry. */ + memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15)); + + /* Generic chip reset first (so target could override). */ + reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); + + table = get_target_table(vcpu->arch.target, &num); + reset_coproc_regs(vcpu, table, num); + + for (num = 1; num < NR_CP15_REGS; num++) + if (vcpu->arch.cp15[num] == 0x42424242) + panic("Didn't reset vcpu->arch.cp15[%zi]", num); +} diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h new file mode 100644 index 00000000000..992adfafa2f --- /dev/null +++ b/arch/arm/kvm/coproc.h @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Authors: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ARM_KVM_COPROC_LOCAL_H__ +#define __ARM_KVM_COPROC_LOCAL_H__ + +struct coproc_params { + unsigned long CRn; + unsigned long CRm; + unsigned long Op1; + unsigned long Op2; + unsigned long Rt1; + unsigned long Rt2; + bool is_64bit; + bool is_write; +}; + +struct coproc_reg { + /* MRC/MCR/MRRC/MCRR instruction which accesses it. */ + unsigned long CRn; + unsigned long CRm; + unsigned long Op1; + unsigned long Op2; + + bool is_64; + + /* Trapped access from guest, if non-NULL. */ + bool (*access)(struct kvm_vcpu *, + const struct coproc_params *, + const struct coproc_reg *); + + /* Initialization for vcpu. */ + void (*reset)(struct kvm_vcpu *, const struct coproc_reg *); + + /* Index into vcpu->arch.cp15[], or 0 if we don't need to save it. */ + unsigned long reg; + + /* Value (usually reset value) */ + u64 val; +}; + +static inline void print_cp_instr(const struct coproc_params *p) +{ + /* Look, we even formatted it for you to paste into the table! */ + if (p->is_64bit) { + kvm_pr_unimpl(" { CRm(%2lu), Op1(%2lu), is64, func_%s },\n", + p->CRm, p->Op1, p->is_write ? "write" : "read"); + } else { + kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32," + " func_%s },\n", + p->CRn, p->CRm, p->Op1, p->Op2, + p->is_write ? "write" : "read"); + } +} + +static inline bool ignore_write(struct kvm_vcpu *vcpu, + const struct coproc_params *p) +{ + return true; +} + +static inline bool read_zero(struct kvm_vcpu *vcpu, + const struct coproc_params *p) +{ + *vcpu_reg(vcpu, p->Rt1) = 0; + return true; +} + +static inline bool write_to_read_only(struct kvm_vcpu *vcpu, + const struct coproc_params *params) +{ + kvm_debug("CP15 write to read-only register at: %08x\n", + *vcpu_pc(vcpu)); + print_cp_instr(params); + return false; +} + +static inline bool read_from_write_only(struct kvm_vcpu *vcpu, + const struct coproc_params *params) +{ + kvm_debug("CP15 read to write-only register at: %08x\n", + *vcpu_pc(vcpu)); + print_cp_instr(params); + return false; +} + +/* Reset functions */ +static inline void reset_unknown(struct kvm_vcpu *vcpu, + const struct coproc_reg *r) +{ + BUG_ON(!r->reg); + BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.cp15)); + vcpu->arch.cp15[r->reg] = 0xdecafbad; +} + +static inline void reset_val(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + BUG_ON(!r->reg); + BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.cp15)); + vcpu->arch.cp15[r->reg] = r->val; +} + +static inline void reset_unknown64(struct kvm_vcpu *vcpu, + const struct coproc_reg *r) +{ + BUG_ON(!r->reg); + BUG_ON(r->reg + 1 >= ARRAY_SIZE(vcpu->arch.cp15)); + + vcpu->arch.cp15[r->reg] = 0xdecafbad; + vcpu->arch.cp15[r->reg+1] = 0xd0c0ffee; +} + +static inline int cmp_reg(const struct coproc_reg *i1, + const struct coproc_reg *i2) +{ + BUG_ON(i1 == i2); + if (!i1) + return 1; + else if (!i2) + return -1; + if (i1->CRn != i2->CRn) + return i1->CRn - i2->CRn; + if (i1->CRm != i2->CRm) + return i1->CRm - i2->CRm; + if (i1->Op1 != i2->Op1) + return i1->Op1 - i2->Op1; + return i1->Op2 - i2->Op2; +} + + +#define CRn(_x) .CRn = _x +#define CRm(_x) .CRm = _x +#define Op1(_x) .Op1 = _x +#define Op2(_x) .Op2 = _x +#define is64 .is_64 = true +#define is32 .is_64 = false + +#endif /* __ARM_KVM_COPROC_LOCAL_H__ */ diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c new file mode 100644 index 00000000000..685063a6d0c --- /dev/null +++ b/arch/arm/kvm/coproc_a15.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Authors: Rusty Russell <rusty@rustcorp.au> + * Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#include <linux/kvm_host.h> +#include <asm/cputype.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_host.h> +#include <asm/kvm_emulate.h> +#include <asm/kvm_coproc.h> +#include <linux/init.h> + +static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + /* + * Compute guest MPIDR: + * (Even if we present only one VCPU to the guest on an SMP + * host we don't set the U bit in the MPIDR, or vice versa, as + * revealing the underlying hardware properties is likely to + * be the best choice). + */ + vcpu->arch.cp15[c0_MPIDR] = (read_cpuid_mpidr() & ~MPIDR_LEVEL_MASK) + | (vcpu->vcpu_id & MPIDR_LEVEL_MASK); +} + +#include "coproc.h" + +/* A15 TRM 4.3.28: RO WI */ +static bool access_actlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR]; + return true; +} + +/* A15 TRM 4.3.60: R/O. */ +static bool access_cbar(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return write_to_read_only(vcpu, p); + return read_zero(vcpu, p); +} + +/* A15 TRM 4.3.48: R/O WI. */ +static bool access_l2ctlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR]; + return true; +} + +static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + u32 l2ctlr, ncores; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); + l2ctlr &= ~(3 << 24); + ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1; + l2ctlr |= (ncores & 3) << 24; + + vcpu->arch.cp15[c9_L2CTLR] = l2ctlr; +} + +static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r) +{ + u32 actlr; + + /* ACTLR contains SMP bit: make sure you create all cpus first! */ + asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); + /* Make the SMP bit consistent with the guest configuration */ + if (atomic_read(&vcpu->kvm->online_vcpus) > 1) + actlr |= 1U << 6; + else + actlr &= ~(1U << 6); + + vcpu->arch.cp15[c1_ACTLR] = actlr; +} + +/* A15 TRM 4.3.49: R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). */ +static bool access_l2ectlr(struct kvm_vcpu *vcpu, + const struct coproc_params *p, + const struct coproc_reg *r) +{ + if (p->is_write) + return ignore_write(vcpu, p); + + *vcpu_reg(vcpu, p->Rt1) = 0; + return true; +} + +/* + * A15-specific CP15 registers. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 + */ +static const struct coproc_reg a15_regs[] = { + /* MPIDR: we use VMPIDR for guest access. */ + { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32, + NULL, reset_mpidr, c0_MPIDR }, + + /* SCTLR: swapped by interrupt.S. */ + { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, + NULL, reset_val, c1_SCTLR, 0x00C50078 }, + /* ACTLR: trapped by HCR.TAC bit. */ + { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32, + access_actlr, reset_actlr, c1_ACTLR }, + /* CPACR: swapped by interrupt.S. */ + { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, + NULL, reset_val, c1_CPACR, 0x00000000 }, + + /* + * L2CTLR access (guest wants to know #CPUs). + */ + { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, + access_l2ctlr, reset_l2ctlr, c9_L2CTLR }, + { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr}, + + /* The Configuration Base Address Register. */ + { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, +}; + +static struct kvm_coproc_target_table a15_target_table = { + .target = KVM_ARM_TARGET_CORTEX_A15, + .table = a15_regs, + .num = ARRAY_SIZE(a15_regs), +}; + +static int __init coproc_a15_init(void) +{ + unsigned int i; + + for (i = 1; i < ARRAY_SIZE(a15_regs); i++) + BUG_ON(cmp_reg(&a15_regs[i-1], + &a15_regs[i]) >= 0); + + kvm_register_target_coproc_table(&a15_target_table); + return 0; +} +late_initcall(coproc_a15_init); diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c new file mode 100644 index 00000000000..d61450ac666 --- /dev/null +++ b/arch/arm/kvm/emulate.c @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/mm.h> +#include <linux/kvm_host.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_emulate.h> +#include <trace/events/kvm.h> + +#include "trace.h" + +#define VCPU_NR_MODES 6 +#define VCPU_REG_OFFSET_USR 0 +#define VCPU_REG_OFFSET_FIQ 1 +#define VCPU_REG_OFFSET_IRQ 2 +#define VCPU_REG_OFFSET_SVC 3 +#define VCPU_REG_OFFSET_ABT 4 +#define VCPU_REG_OFFSET_UND 5 +#define REG_OFFSET(_reg) \ + (offsetof(struct kvm_regs, _reg) / sizeof(u32)) + +#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num]) + +static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = { + /* USR/SYS Registers */ + [VCPU_REG_OFFSET_USR] = { + USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), + USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), + USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), + USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), + USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14), + }, + + /* FIQ Registers */ + [VCPU_REG_OFFSET_FIQ] = { + USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), + USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), + USR_REG_OFFSET(6), USR_REG_OFFSET(7), + REG_OFFSET(fiq_regs[0]), /* r8 */ + REG_OFFSET(fiq_regs[1]), /* r9 */ + REG_OFFSET(fiq_regs[2]), /* r10 */ + REG_OFFSET(fiq_regs[3]), /* r11 */ + REG_OFFSET(fiq_regs[4]), /* r12 */ + REG_OFFSET(fiq_regs[5]), /* r13 */ + REG_OFFSET(fiq_regs[6]), /* r14 */ + }, + + /* IRQ Registers */ + [VCPU_REG_OFFSET_IRQ] = { + USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), + USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), + USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), + USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), + USR_REG_OFFSET(12), + REG_OFFSET(irq_regs[0]), /* r13 */ + REG_OFFSET(irq_regs[1]), /* r14 */ + }, + + /* SVC Registers */ + [VCPU_REG_OFFSET_SVC] = { + USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), + USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), + USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), + USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), + USR_REG_OFFSET(12), + REG_OFFSET(svc_regs[0]), /* r13 */ + REG_OFFSET(svc_regs[1]), /* r14 */ + }, + + /* ABT Registers */ + [VCPU_REG_OFFSET_ABT] = { + USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), + USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), + USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), + USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), + USR_REG_OFFSET(12), + REG_OFFSET(abt_regs[0]), /* r13 */ + REG_OFFSET(abt_regs[1]), /* r14 */ + }, + + /* UND Registers */ + [VCPU_REG_OFFSET_UND] = { + USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), + USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), + USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), + USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), + USR_REG_OFFSET(12), + REG_OFFSET(und_regs[0]), /* r13 */ + REG_OFFSET(und_regs[1]), /* r14 */ + }, +}; + +/* + * Return a pointer to the register number valid in the current mode of + * the virtual CPU. + */ +u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num) +{ + u32 *reg_array = (u32 *)&vcpu->arch.regs; + u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK; + + switch (mode) { + case USR_MODE...SVC_MODE: + mode &= ~MODE32_BIT; /* 0 ... 3 */ + break; + + case ABT_MODE: + mode = VCPU_REG_OFFSET_ABT; + break; + + case UND_MODE: + mode = VCPU_REG_OFFSET_UND; + break; + + case SYSTEM_MODE: + mode = VCPU_REG_OFFSET_USR; + break; + + default: + BUG(); + } + + return reg_array + vcpu_reg_offsets[mode][reg_num]; +} + +/* + * Return the SPSR for the current mode of the virtual CPU. + */ +u32 *vcpu_spsr(struct kvm_vcpu *vcpu) +{ + u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK; + switch (mode) { + case SVC_MODE: + return &vcpu->arch.regs.KVM_ARM_SVC_spsr; + case ABT_MODE: + return &vcpu->arch.regs.KVM_ARM_ABT_spsr; + case UND_MODE: + return &vcpu->arch.regs.KVM_ARM_UND_spsr; + case IRQ_MODE: + return &vcpu->arch.regs.KVM_ARM_IRQ_spsr; + case FIQ_MODE: + return &vcpu->arch.regs.KVM_ARM_FIQ_spsr; + default: + BUG(); + } +} + +/** + * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest + * @vcpu: the vcpu pointer + * @run: the kvm_run structure pointer + * + * Simply sets the wait_for_interrupts flag on the vcpu structure, which will + * halt execution of world-switches and schedule other host processes until + * there is an incoming IRQ or FIQ to the VM. + */ +int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + trace_kvm_wfi(*vcpu_pc(vcpu)); + kvm_vcpu_block(vcpu); + return 1; +} + +/** + * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block + * @vcpu: The VCPU pointer + * + * When exceptions occur while instructions are executed in Thumb IF-THEN + * blocks, the ITSTATE field of the CPSR is not advanved (updated), so we have + * to do this little bit of work manually. The fields map like this: + * + * IT[7:0] -> CPSR[26:25],CPSR[15:10] + */ +static void kvm_adjust_itstate(struct kvm_vcpu *vcpu) +{ + unsigned long itbits, cond; + unsigned long cpsr = *vcpu_cpsr(vcpu); + bool is_arm = !(cpsr & PSR_T_BIT); + + BUG_ON(is_arm && (cpsr & PSR_IT_MASK)); + + if (!(cpsr & PSR_IT_MASK)) + return; + + cond = (cpsr & 0xe000) >> 13; + itbits = (cpsr & 0x1c00) >> (10 - 2); + itbits |= (cpsr & (0x3 << 25)) >> 25; + + /* Perform ITAdvance (see page A-52 in ARM DDI 0406C) */ + if ((itbits & 0x7) == 0) + itbits = cond = 0; + else + itbits = (itbits << 1) & 0x1f; + + cpsr &= ~PSR_IT_MASK; + cpsr |= cond << 13; + cpsr |= (itbits & 0x1c) << (10 - 2); + cpsr |= (itbits & 0x3) << 25; + *vcpu_cpsr(vcpu) = cpsr; +} + +/** + * kvm_skip_instr - skip a trapped instruction and proceed to the next + * @vcpu: The vcpu pointer + */ +void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr) +{ + bool is_thumb; + + is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_T_BIT); + if (is_thumb && !is_wide_instr) + *vcpu_pc(vcpu) += 2; + else + *vcpu_pc(vcpu) += 4; + kvm_adjust_itstate(vcpu); +} + + +/****************************************************************************** + * Inject exceptions into the guest + */ + +static u32 exc_vector_base(struct kvm_vcpu *vcpu) +{ + u32 sctlr = vcpu->arch.cp15[c1_SCTLR]; + u32 vbar = vcpu->arch.cp15[c12_VBAR]; + + if (sctlr & SCTLR_V) + return 0xffff0000; + else /* always have security exceptions */ + return vbar; +} + +/** + * kvm_inject_undefined - inject an undefined exception into the guest + * @vcpu: The VCPU to receive the undefined exception + * + * It is assumed that this code is called from the VCPU thread and that the + * VCPU therefore is not currently executing guest code. + * + * Modelled after TakeUndefInstrException() pseudocode. + */ +void kvm_inject_undefined(struct kvm_vcpu *vcpu) +{ + u32 new_lr_value; + u32 new_spsr_value; + u32 cpsr = *vcpu_cpsr(vcpu); + u32 sctlr = vcpu->arch.cp15[c1_SCTLR]; + bool is_thumb = (cpsr & PSR_T_BIT); + u32 vect_offset = 4; + u32 return_offset = (is_thumb) ? 2 : 4; + + new_spsr_value = cpsr; + new_lr_value = *vcpu_pc(vcpu) - return_offset; + + *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | UND_MODE; + *vcpu_cpsr(vcpu) |= PSR_I_BIT; + *vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT); + + if (sctlr & SCTLR_TE) + *vcpu_cpsr(vcpu) |= PSR_T_BIT; + if (sctlr & SCTLR_EE) + *vcpu_cpsr(vcpu) |= PSR_E_BIT; + + /* Note: These now point to UND banked copies */ + *vcpu_spsr(vcpu) = cpsr; + *vcpu_reg(vcpu, 14) = new_lr_value; + + /* Branch to exception vector */ + *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset; +} + +/* + * Modelled after TakeDataAbortException() and TakePrefetchAbortException + * pseudocode. + */ +static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr) +{ + u32 new_lr_value; + u32 new_spsr_value; + u32 cpsr = *vcpu_cpsr(vcpu); + u32 sctlr = vcpu->arch.cp15[c1_SCTLR]; + bool is_thumb = (cpsr & PSR_T_BIT); + u32 vect_offset; + u32 return_offset = (is_thumb) ? 4 : 0; + bool is_lpae; + + new_spsr_value = cpsr; + new_lr_value = *vcpu_pc(vcpu) + return_offset; + + *vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | ABT_MODE; + *vcpu_cpsr(vcpu) |= PSR_I_BIT | PSR_A_BIT; + *vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT); + + if (sctlr & SCTLR_TE) + *vcpu_cpsr(vcpu) |= PSR_T_BIT; + if (sctlr & SCTLR_EE) + *vcpu_cpsr(vcpu) |= PSR_E_BIT; + + /* Note: These now point to ABT banked copies */ + *vcpu_spsr(vcpu) = cpsr; + *vcpu_reg(vcpu, 14) = new_lr_value; + + if (is_pabt) + vect_offset = 12; + else + vect_offset = 16; + + /* Branch to exception vector */ + *vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset; + + if (is_pabt) { + /* Set DFAR and DFSR */ + vcpu->arch.cp15[c6_IFAR] = addr; + is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31); + /* Always give debug fault for now - should give guest a clue */ + if (is_lpae) + vcpu->arch.cp15[c5_IFSR] = 1 << 9 | 0x22; + else + vcpu->arch.cp15[c5_IFSR] = 2; + } else { /* !iabt */ + /* Set DFAR and DFSR */ + vcpu->arch.cp15[c6_DFAR] = addr; + is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31); + /* Always give debug fault for now - should give guest a clue */ + if (is_lpae) + vcpu->arch.cp15[c5_DFSR] = 1 << 9 | 0x22; + else + vcpu->arch.cp15[c5_DFSR] = 2; + } + +} + +/** + * kvm_inject_dabt - inject a data abort into the guest + * @vcpu: The VCPU to receive the undefined exception + * @addr: The address to report in the DFAR + * + * It is assumed that this code is called from the VCPU thread and that the + * VCPU therefore is not currently executing guest code. + */ +void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr) +{ + inject_abt(vcpu, false, addr); +} + +/** + * kvm_inject_pabt - inject a prefetch abort into the guest + * @vcpu: The VCPU to receive the undefined exception + * @addr: The address to report in the DFAR + * + * It is assumed that this code is called from the VCPU thread and that the + * VCPU therefore is not currently executing guest code. + */ +void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr) +{ + inject_abt(vcpu, true, addr); +} diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c new file mode 100644 index 00000000000..2339d9609d3 --- /dev/null +++ b/arch/arm/kvm/guest.c @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/kvm_host.h> +#include <linux/module.h> +#include <linux/vmalloc.h> +#include <linux/fs.h> +#include <asm/uaccess.h> +#include <asm/kvm.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_emulate.h> +#include <asm/kvm_coproc.h> + +#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM } +#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU } + +struct kvm_stats_debugfs_item debugfs_entries[] = { + { NULL } +}; + +int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) +{ + return 0; +} + +static u64 core_reg_offset_from_id(u64 id) +{ + return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); +} + +static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + u32 __user *uaddr = (u32 __user *)(long)reg->addr; + struct kvm_regs *regs = &vcpu->arch.regs; + u64 off; + + if (KVM_REG_SIZE(reg->id) != 4) + return -ENOENT; + + /* Our ID is an index into the kvm_regs struct. */ + off = core_reg_offset_from_id(reg->id); + if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id)) + return -ENOENT; + + return put_user(((u32 *)regs)[off], uaddr); +} + +static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + u32 __user *uaddr = (u32 __user *)(long)reg->addr; + struct kvm_regs *regs = &vcpu->arch.regs; + u64 off, val; + + if (KVM_REG_SIZE(reg->id) != 4) + return -ENOENT; + + /* Our ID is an index into the kvm_regs struct. */ + off = core_reg_offset_from_id(reg->id); + if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id)) + return -ENOENT; + + if (get_user(val, uaddr) != 0) + return -EFAULT; + + if (off == KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr)) { + unsigned long mode = val & MODE_MASK; + switch (mode) { + case USR_MODE: + case FIQ_MODE: + case IRQ_MODE: + case SVC_MODE: + case ABT_MODE: + case UND_MODE: + break; + default: + return -EINVAL; + } + } + + ((u32 *)regs)[off] = val; + return 0; +} + +int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + return -EINVAL; +} + +static unsigned long num_core_regs(void) +{ + return sizeof(struct kvm_regs) / sizeof(u32); +} + +/** + * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG + * + * This is for all registers. + */ +unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) +{ + return num_core_regs() + kvm_arm_num_coproc_regs(vcpu); +} + +/** + * kvm_arm_copy_reg_indices - get indices of all registers. + * + * We do core registers right here, then we apppend coproc regs. + */ +int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) +{ + unsigned int i; + const u64 core_reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE; + + for (i = 0; i < sizeof(struct kvm_regs)/sizeof(u32); i++) { + if (put_user(core_reg | i, uindices)) + return -EFAULT; + uindices++; + } + + return kvm_arm_copy_coproc_indices(vcpu, uindices); +} + +int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + /* We currently use nothing arch-specific in upper 32 bits */ + if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32) + return -EINVAL; + + /* Register group 16 means we want a core register. */ + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) + return get_core_reg(vcpu, reg); + + return kvm_arm_coproc_get_reg(vcpu, reg); +} + +int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + /* We currently use nothing arch-specific in upper 32 bits */ + if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32) + return -EINVAL; + + /* Register group 16 means we set a core register. */ + if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) + return set_core_reg(vcpu, reg); + + return kvm_arm_coproc_set_reg(vcpu, reg); +} + +int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, + struct kvm_sregs *sregs) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, + struct kvm_sregs *sregs) +{ + return -EINVAL; +} + +int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, + const struct kvm_vcpu_init *init) +{ + unsigned int i; + + /* We can only do a cortex A15 for now. */ + if (init->target != kvm_target_cpu()) + return -EINVAL; + + vcpu->arch.target = init->target; + bitmap_zero(vcpu->arch.features, KVM_VCPU_MAX_FEATURES); + + /* -ENOENT for unknown features, -EINVAL for invalid combinations. */ + for (i = 0; i < sizeof(init->features) * 8; i++) { + if (test_bit(i, (void *)init->features)) { + if (i >= KVM_VCPU_MAX_FEATURES) + return -ENOENT; + set_bit(i, vcpu->arch.features); + } + } + + /* Now we know what it is, we can reset it. */ + return kvm_reset_vcpu(vcpu); +} + +int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) +{ + return -EINVAL; +} + +int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, + struct kvm_translation *tr) +{ + return -EINVAL; +} diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S new file mode 100644 index 00000000000..9f37a79b880 --- /dev/null +++ b/arch/arm/kvm/init.S @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/linkage.h> +#include <asm/unified.h> +#include <asm/asm-offsets.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_arm.h> + +/******************************************************************** + * Hypervisor initialization + * - should be called with: + * r0,r1 = Hypervisor pgd pointer + * r2 = top of Hyp stack (kernel VA) + * r3 = pointer to hyp vectors + */ + + .text + .pushsection .hyp.idmap.text,"ax" + .align 5 +__kvm_hyp_init: + .globl __kvm_hyp_init + + @ Hyp-mode exception vector + W(b) . + W(b) . + W(b) . + W(b) . + W(b) . + W(b) __do_hyp_init + W(b) . + W(b) . + +__do_hyp_init: + @ Set the HTTBR to point to the hypervisor PGD pointer passed + mcrr p15, 4, r0, r1, c2 + + @ Set the HTCR and VTCR to the same shareability and cacheability + @ settings as the non-secure TTBCR and with T0SZ == 0. + mrc p15, 4, r0, c2, c0, 2 @ HTCR + ldr r12, =HTCR_MASK + bic r0, r0, r12 + mrc p15, 0, r1, c2, c0, 2 @ TTBCR + and r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ) + orr r0, r0, r1 + mcr p15, 4, r0, c2, c0, 2 @ HTCR + + mrc p15, 4, r1, c2, c1, 2 @ VTCR + ldr r12, =VTCR_MASK + bic r1, r1, r12 + bic r0, r0, #(~VTCR_HTCR_SH) @ clear non-reusable HTCR bits + orr r1, r0, r1 + orr r1, r1, #(KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S) + mcr p15, 4, r1, c2, c1, 2 @ VTCR + + @ Use the same memory attributes for hyp. accesses as the kernel + @ (copy MAIRx ro HMAIRx). + mrc p15, 0, r0, c10, c2, 0 + mcr p15, 4, r0, c10, c2, 0 + mrc p15, 0, r0, c10, c2, 1 + mcr p15, 4, r0, c10, c2, 1 + + @ Set the HSCTLR to: + @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel) + @ - Endianness: Kernel config + @ - Fast Interrupt Features: Kernel config + @ - Write permission implies XN: disabled + @ - Instruction cache: enabled + @ - Data/Unified cache: enabled + @ - Memory alignment checks: enabled + @ - MMU: enabled (this code must be run from an identity mapping) + mrc p15, 4, r0, c1, c0, 0 @ HSCR + ldr r12, =HSCTLR_MASK + bic r0, r0, r12 + mrc p15, 0, r1, c1, c0, 0 @ SCTLR + ldr r12, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C) + and r1, r1, r12 + ARM( ldr r12, =(HSCTLR_M | HSCTLR_A) ) + THUMB( ldr r12, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) ) + orr r1, r1, r12 + orr r0, r0, r1 + isb + mcr p15, 4, r0, c1, c0, 0 @ HSCR + isb + + @ Set stack pointer and return to the kernel + mov sp, r2 + + @ Set HVBAR to point to the HYP vectors + mcr p15, 4, r3, c12, c0, 0 @ HVBAR + + eret + + .ltorg + + .globl __kvm_hyp_init_end +__kvm_hyp_init_end: + + .popsection diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S new file mode 100644 index 00000000000..c5400d2e97c --- /dev/null +++ b/arch/arm/kvm/interrupts.S @@ -0,0 +1,478 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/linkage.h> +#include <linux/const.h> +#include <asm/unified.h> +#include <asm/page.h> +#include <asm/ptrace.h> +#include <asm/asm-offsets.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_arm.h> +#include <asm/vfpmacros.h> +#include "interrupts_head.S" + + .text + +__kvm_hyp_code_start: + .globl __kvm_hyp_code_start + +/******************************************************************** + * Flush per-VMID TLBs + * + * void __kvm_tlb_flush_vmid(struct kvm *kvm); + * + * We rely on the hardware to broadcast the TLB invalidation to all CPUs + * inside the inner-shareable domain (which is the case for all v7 + * implementations). If we come across a non-IS SMP implementation, we'll + * have to use an IPI based mechanism. Until then, we stick to the simple + * hardware assisted version. + */ +ENTRY(__kvm_tlb_flush_vmid) + push {r2, r3} + + add r0, r0, #KVM_VTTBR + ldrd r2, r3, [r0] + mcrr p15, 6, r2, r3, c2 @ Write VTTBR + isb + mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored) + dsb + isb + mov r2, #0 + mov r3, #0 + mcrr p15, 6, r2, r3, c2 @ Back to VMID #0 + isb @ Not necessary if followed by eret + + pop {r2, r3} + bx lr +ENDPROC(__kvm_tlb_flush_vmid) + +/******************************************************************** + * Flush TLBs and instruction caches of all CPUs inside the inner-shareable + * domain, for all VMIDs + * + * void __kvm_flush_vm_context(void); + */ +ENTRY(__kvm_flush_vm_context) + mov r0, #0 @ rn parameter for c15 flushes is SBZ + + /* Invalidate NS Non-Hyp TLB Inner Shareable (TLBIALLNSNHIS) */ + mcr p15, 4, r0, c8, c3, 4 + /* Invalidate instruction caches Inner Shareable (ICIALLUIS) */ + mcr p15, 0, r0, c7, c1, 0 + dsb + isb @ Not necessary if followed by eret + + bx lr +ENDPROC(__kvm_flush_vm_context) + + +/******************************************************************** + * Hypervisor world-switch code + * + * + * int __kvm_vcpu_run(struct kvm_vcpu *vcpu) + */ +ENTRY(__kvm_vcpu_run) + @ Save the vcpu pointer + mcr p15, 4, vcpu, c13, c0, 2 @ HTPIDR + + save_host_regs + + @ Store hardware CP15 state and load guest state + read_cp15_state store_to_vcpu = 0 + write_cp15_state read_from_vcpu = 1 + + @ If the host kernel has not been configured with VFPv3 support, + @ then it is safer if we deny guests from using it as well. +#ifdef CONFIG_VFPv3 + @ Set FPEXC_EN so the guest doesn't trap floating point instructions + VFPFMRX r2, FPEXC @ VMRS + push {r2} + orr r2, r2, #FPEXC_EN + VFPFMXR FPEXC, r2 @ VMSR +#endif + + @ Configure Hyp-role + configure_hyp_role vmentry + + @ Trap coprocessor CRx accesses + set_hstr vmentry + set_hcptr vmentry, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11)) + set_hdcr vmentry + + @ Write configured ID register into MIDR alias + ldr r1, [vcpu, #VCPU_MIDR] + mcr p15, 4, r1, c0, c0, 0 + + @ Write guest view of MPIDR into VMPIDR + ldr r1, [vcpu, #CP15_OFFSET(c0_MPIDR)] + mcr p15, 4, r1, c0, c0, 5 + + @ Set up guest memory translation + ldr r1, [vcpu, #VCPU_KVM] + add r1, r1, #KVM_VTTBR + ldrd r2, r3, [r1] + mcrr p15, 6, r2, r3, c2 @ Write VTTBR + + @ We're all done, just restore the GPRs and go to the guest + restore_guest_regs + clrex @ Clear exclusive monitor + eret + +__kvm_vcpu_return: + /* + * return convention: + * guest r0, r1, r2 saved on the stack + * r0: vcpu pointer + * r1: exception code + */ + save_guest_regs + + @ Set VMID == 0 + mov r2, #0 + mov r3, #0 + mcrr p15, 6, r2, r3, c2 @ Write VTTBR + + @ Don't trap coprocessor accesses for host kernel + set_hstr vmexit + set_hdcr vmexit + set_hcptr vmexit, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11)) + +#ifdef CONFIG_VFPv3 + @ Save floating point registers we if let guest use them. + tst r2, #(HCPTR_TCP(10) | HCPTR_TCP(11)) + bne after_vfp_restore + + @ Switch VFP/NEON hardware state to the host's + add r7, vcpu, #VCPU_VFP_GUEST + store_vfp_state r7 + add r7, vcpu, #VCPU_VFP_HOST + ldr r7, [r7] + restore_vfp_state r7 + +after_vfp_restore: + @ Restore FPEXC_EN which we clobbered on entry + pop {r2} + VFPFMXR FPEXC, r2 +#endif + + @ Reset Hyp-role + configure_hyp_role vmexit + + @ Let host read hardware MIDR + mrc p15, 0, r2, c0, c0, 0 + mcr p15, 4, r2, c0, c0, 0 + + @ Back to hardware MPIDR + mrc p15, 0, r2, c0, c0, 5 + mcr p15, 4, r2, c0, c0, 5 + + @ Store guest CP15 state and restore host state + read_cp15_state store_to_vcpu = 1 + write_cp15_state read_from_vcpu = 0 + + restore_host_regs + clrex @ Clear exclusive monitor + mov r0, r1 @ Return the return code + mov r1, #0 @ Clear upper bits in return value + bx lr @ return to IOCTL + +/******************************************************************** + * Call function in Hyp mode + * + * + * u64 kvm_call_hyp(void *hypfn, ...); + * + * This is not really a variadic function in the classic C-way and care must + * be taken when calling this to ensure parameters are passed in registers + * only, since the stack will change between the caller and the callee. + * + * Call the function with the first argument containing a pointer to the + * function you wish to call in Hyp mode, and subsequent arguments will be + * passed as r0, r1, and r2 (a maximum of 3 arguments in addition to the + * function pointer can be passed). The function being called must be mapped + * in Hyp mode (see init_hyp_mode in arch/arm/kvm/arm.c). Return values are + * passed in r0 and r1. + * + * The calling convention follows the standard AAPCS: + * r0 - r3: caller save + * r12: caller save + * rest: callee save + */ +ENTRY(kvm_call_hyp) + hvc #0 + bx lr + +/******************************************************************** + * Hypervisor exception vector and handlers + * + * + * The KVM/ARM Hypervisor ABI is defined as follows: + * + * Entry to Hyp mode from the host kernel will happen _only_ when an HVC + * instruction is issued since all traps are disabled when running the host + * kernel as per the Hyp-mode initialization at boot time. + * + * HVC instructions cause a trap to the vector page + offset 0x18 (see hyp_hvc + * below) when the HVC instruction is called from SVC mode (i.e. a guest or the + * host kernel) and they cause a trap to the vector page + offset 0xc when HVC + * instructions are called from within Hyp-mode. + * + * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode): + * Switching to Hyp mode is done through a simple HVC #0 instruction. The + * exception vector code will check that the HVC comes from VMID==0 and if + * so will push the necessary state (SPSR, lr_usr) on the Hyp stack. + * - r0 contains a pointer to a HYP function + * - r1, r2, and r3 contain arguments to the above function. + * - The HYP function will be called with its arguments in r0, r1 and r2. + * On HYP function return, we return directly to SVC. + * + * Note that the above is used to execute code in Hyp-mode from a host-kernel + * point of view, and is a different concept from performing a world-switch and + * executing guest code SVC mode (with a VMID != 0). + */ + +/* Handle undef, svc, pabt, or dabt by crashing with a user notice */ +.macro bad_exception exception_code, panic_str + push {r0-r2} + mrrc p15, 6, r0, r1, c2 @ Read VTTBR + lsr r1, r1, #16 + ands r1, r1, #0xff + beq 99f + + load_vcpu @ Load VCPU pointer + .if \exception_code == ARM_EXCEPTION_DATA_ABORT + mrc p15, 4, r2, c5, c2, 0 @ HSR + mrc p15, 4, r1, c6, c0, 0 @ HDFAR + str r2, [vcpu, #VCPU_HSR] + str r1, [vcpu, #VCPU_HxFAR] + .endif + .if \exception_code == ARM_EXCEPTION_PREF_ABORT + mrc p15, 4, r2, c5, c2, 0 @ HSR + mrc p15, 4, r1, c6, c0, 2 @ HIFAR + str r2, [vcpu, #VCPU_HSR] + str r1, [vcpu, #VCPU_HxFAR] + .endif + mov r1, #\exception_code + b __kvm_vcpu_return + + @ We were in the host already. Let's craft a panic-ing return to SVC. +99: mrs r2, cpsr + bic r2, r2, #MODE_MASK + orr r2, r2, #SVC_MODE +THUMB( orr r2, r2, #PSR_T_BIT ) + msr spsr_cxsf, r2 + mrs r1, ELR_hyp + ldr r2, =BSYM(panic) + msr ELR_hyp, r2 + ldr r0, =\panic_str + eret +.endm + + .text + + .align 5 +__kvm_hyp_vector: + .globl __kvm_hyp_vector + + @ Hyp-mode exception vector + W(b) hyp_reset + W(b) hyp_undef + W(b) hyp_svc + W(b) hyp_pabt + W(b) hyp_dabt + W(b) hyp_hvc + W(b) hyp_irq + W(b) hyp_fiq + + .align +hyp_reset: + b hyp_reset + + .align +hyp_undef: + bad_exception ARM_EXCEPTION_UNDEFINED, und_die_str + + .align +hyp_svc: + bad_exception ARM_EXCEPTION_HVC, svc_die_str + + .align +hyp_pabt: + bad_exception ARM_EXCEPTION_PREF_ABORT, pabt_die_str + + .align +hyp_dabt: + bad_exception ARM_EXCEPTION_DATA_ABORT, dabt_die_str + + .align +hyp_hvc: + /* + * Getting here is either becuase of a trap from a guest or from calling + * HVC from the host kernel, which means "switch to Hyp mode". + */ + push {r0, r1, r2} + + @ Check syndrome register + mrc p15, 4, r1, c5, c2, 0 @ HSR + lsr r0, r1, #HSR_EC_SHIFT +#ifdef CONFIG_VFPv3 + cmp r0, #HSR_EC_CP_0_13 + beq switch_to_guest_vfp +#endif + cmp r0, #HSR_EC_HVC + bne guest_trap @ Not HVC instr. + + /* + * Let's check if the HVC came from VMID 0 and allow simple + * switch to Hyp mode + */ + mrrc p15, 6, r0, r2, c2 + lsr r2, r2, #16 + and r2, r2, #0xff + cmp r2, #0 + bne guest_trap @ Guest called HVC + +host_switch_to_hyp: + pop {r0, r1, r2} + + push {lr} + mrs lr, SPSR + push {lr} + + mov lr, r0 + mov r0, r1 + mov r1, r2 + mov r2, r3 + +THUMB( orr lr, #1) + blx lr @ Call the HYP function + + pop {lr} + msr SPSR_csxf, lr + pop {lr} + eret + +guest_trap: + load_vcpu @ Load VCPU pointer to r0 + str r1, [vcpu, #VCPU_HSR] + + @ Check if we need the fault information + lsr r1, r1, #HSR_EC_SHIFT + cmp r1, #HSR_EC_IABT + mrceq p15, 4, r2, c6, c0, 2 @ HIFAR + beq 2f + cmp r1, #HSR_EC_DABT + bne 1f + mrc p15, 4, r2, c6, c0, 0 @ HDFAR + +2: str r2, [vcpu, #VCPU_HxFAR] + + /* + * B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode: + * + * Abort on the stage 2 translation for a memory access from a + * Non-secure PL1 or PL0 mode: + * + * For any Access flag fault or Translation fault, and also for any + * Permission fault on the stage 2 translation of a memory access + * made as part of a translation table walk for a stage 1 translation, + * the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR + * is UNKNOWN. + */ + + /* Check for permission fault, and S1PTW */ + mrc p15, 4, r1, c5, c2, 0 @ HSR + and r0, r1, #HSR_FSC_TYPE + cmp r0, #FSC_PERM + tsteq r1, #(1 << 7) @ S1PTW + mrcne p15, 4, r2, c6, c0, 4 @ HPFAR + bne 3f + + /* Resolve IPA using the xFAR */ + mcr p15, 0, r2, c7, c8, 0 @ ATS1CPR + isb + mrrc p15, 0, r0, r1, c7 @ PAR + tst r0, #1 + bne 4f @ Failed translation + ubfx r2, r0, #12, #20 + lsl r2, r2, #4 + orr r2, r2, r1, lsl #24 + +3: load_vcpu @ Load VCPU pointer to r0 + str r2, [r0, #VCPU_HPFAR] + +1: mov r1, #ARM_EXCEPTION_HVC + b __kvm_vcpu_return + +4: pop {r0, r1, r2} @ Failed translation, return to guest + eret + +/* + * If VFPv3 support is not available, then we will not switch the VFP + * registers; however cp10 and cp11 accesses will still trap and fallback + * to the regular coprocessor emulation code, which currently will + * inject an undefined exception to the guest. + */ +#ifdef CONFIG_VFPv3 +switch_to_guest_vfp: + load_vcpu @ Load VCPU pointer to r0 + push {r3-r7} + + @ NEON/VFP used. Turn on VFP access. + set_hcptr vmexit, (HCPTR_TCP(10) | HCPTR_TCP(11)) + + @ Switch VFP/NEON hardware state to the guest's + add r7, r0, #VCPU_VFP_HOST + ldr r7, [r7] + store_vfp_state r7 + add r7, r0, #VCPU_VFP_GUEST + restore_vfp_state r7 + + pop {r3-r7} + pop {r0-r2} + eret +#endif + + .align +hyp_irq: + push {r0, r1, r2} + mov r1, #ARM_EXCEPTION_IRQ + load_vcpu @ Load VCPU pointer to r0 + b __kvm_vcpu_return + + .align +hyp_fiq: + b hyp_fiq + + .ltorg + +__kvm_hyp_code_end: + .globl __kvm_hyp_code_end + + .section ".rodata" + +und_die_str: + .ascii "unexpected undefined exception in Hyp mode at: %#08x" +pabt_die_str: + .ascii "unexpected prefetch abort in Hyp mode at: %#08x" +dabt_die_str: + .ascii "unexpected data abort in Hyp mode at: %#08x" +svc_die_str: + .ascii "unexpected HVC/SVC trap in Hyp mode at: %#08x" diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S new file mode 100644 index 00000000000..6a95d341e9c --- /dev/null +++ b/arch/arm/kvm/interrupts_head.S @@ -0,0 +1,441 @@ +#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4)) +#define VCPU_USR_SP (VCPU_USR_REG(13)) +#define VCPU_USR_LR (VCPU_USR_REG(14)) +#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4)) + +/* + * Many of these macros need to access the VCPU structure, which is always + * held in r0. These macros should never clobber r1, as it is used to hold the + * exception code on the return path (except of course the macro that switches + * all the registers before the final jump to the VM). + */ +vcpu .req r0 @ vcpu pointer always in r0 + +/* Clobbers {r2-r6} */ +.macro store_vfp_state vfp_base + @ The VFPFMRX and VFPFMXR macros are the VMRS and VMSR instructions + VFPFMRX r2, FPEXC + @ Make sure VFP is enabled so we can touch the registers. + orr r6, r2, #FPEXC_EN + VFPFMXR FPEXC, r6 + + VFPFMRX r3, FPSCR + tst r2, #FPEXC_EX @ Check for VFP Subarchitecture + beq 1f + @ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so + @ we only need to save them if FPEXC_EX is set. + VFPFMRX r4, FPINST + tst r2, #FPEXC_FP2V + VFPFMRX r5, FPINST2, ne @ vmrsne + bic r6, r2, #FPEXC_EX @ FPEXC_EX disable + VFPFMXR FPEXC, r6 +1: + VFPFSTMIA \vfp_base, r6 @ Save VFP registers + stm \vfp_base, {r2-r5} @ Save FPEXC, FPSCR, FPINST, FPINST2 +.endm + +/* Assume FPEXC_EN is on and FPEXC_EX is off, clobbers {r2-r6} */ +.macro restore_vfp_state vfp_base + VFPFLDMIA \vfp_base, r6 @ Load VFP registers + ldm \vfp_base, {r2-r5} @ Load FPEXC, FPSCR, FPINST, FPINST2 + + VFPFMXR FPSCR, r3 + tst r2, #FPEXC_EX @ Check for VFP Subarchitecture + beq 1f + VFPFMXR FPINST, r4 + tst r2, #FPEXC_FP2V + VFPFMXR FPINST2, r5, ne +1: + VFPFMXR FPEXC, r2 @ FPEXC (last, in case !EN) +.endm + +/* These are simply for the macros to work - value don't have meaning */ +.equ usr, 0 +.equ svc, 1 +.equ abt, 2 +.equ und, 3 +.equ irq, 4 +.equ fiq, 5 + +.macro push_host_regs_mode mode + mrs r2, SP_\mode + mrs r3, LR_\mode + mrs r4, SPSR_\mode + push {r2, r3, r4} +.endm + +/* + * Store all host persistent registers on the stack. + * Clobbers all registers, in all modes, except r0 and r1. + */ +.macro save_host_regs + /* Hyp regs. Only ELR_hyp (SPSR_hyp already saved) */ + mrs r2, ELR_hyp + push {r2} + + /* usr regs */ + push {r4-r12} @ r0-r3 are always clobbered + mrs r2, SP_usr + mov r3, lr + push {r2, r3} + + push_host_regs_mode svc + push_host_regs_mode abt + push_host_regs_mode und + push_host_regs_mode irq + + /* fiq regs */ + mrs r2, r8_fiq + mrs r3, r9_fiq + mrs r4, r10_fiq + mrs r5, r11_fiq + mrs r6, r12_fiq + mrs r7, SP_fiq + mrs r8, LR_fiq + mrs r9, SPSR_fiq + push {r2-r9} +.endm + +.macro pop_host_regs_mode mode + pop {r2, r3, r4} + msr SP_\mode, r2 + msr LR_\mode, r3 + msr SPSR_\mode, r4 +.endm + +/* + * Restore all host registers from the stack. + * Clobbers all registers, in all modes, except r0 and r1. + */ +.macro restore_host_regs + pop {r2-r9} + msr r8_fiq, r2 + msr r9_fiq, r3 + msr r10_fiq, r4 + msr r11_fiq, r5 + msr r12_fiq, r6 + msr SP_fiq, r7 + msr LR_fiq, r8 + msr SPSR_fiq, r9 + + pop_host_regs_mode irq + pop_host_regs_mode und + pop_host_regs_mode abt + pop_host_regs_mode svc + + pop {r2, r3} + msr SP_usr, r2 + mov lr, r3 + pop {r4-r12} + + pop {r2} + msr ELR_hyp, r2 +.endm + +/* + * Restore SP, LR and SPSR for a given mode. offset is the offset of + * this mode's registers from the VCPU base. + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r1, r2, r3, r4. + */ +.macro restore_guest_regs_mode mode, offset + add r1, vcpu, \offset + ldm r1, {r2, r3, r4} + msr SP_\mode, r2 + msr LR_\mode, r3 + msr SPSR_\mode, r4 +.endm + +/* + * Restore all guest registers from the vcpu struct. + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers *all* registers. + */ +.macro restore_guest_regs + restore_guest_regs_mode svc, #VCPU_SVC_REGS + restore_guest_regs_mode abt, #VCPU_ABT_REGS + restore_guest_regs_mode und, #VCPU_UND_REGS + restore_guest_regs_mode irq, #VCPU_IRQ_REGS + + add r1, vcpu, #VCPU_FIQ_REGS + ldm r1, {r2-r9} + msr r8_fiq, r2 + msr r9_fiq, r3 + msr r10_fiq, r4 + msr r11_fiq, r5 + msr r12_fiq, r6 + msr SP_fiq, r7 + msr LR_fiq, r8 + msr SPSR_fiq, r9 + + @ Load return state + ldr r2, [vcpu, #VCPU_PC] + ldr r3, [vcpu, #VCPU_CPSR] + msr ELR_hyp, r2 + msr SPSR_cxsf, r3 + + @ Load user registers + ldr r2, [vcpu, #VCPU_USR_SP] + ldr r3, [vcpu, #VCPU_USR_LR] + msr SP_usr, r2 + mov lr, r3 + add vcpu, vcpu, #(VCPU_USR_REGS) + ldm vcpu, {r0-r12} +.endm + +/* + * Save SP, LR and SPSR for a given mode. offset is the offset of + * this mode's registers from the VCPU base. + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2, r3, r4, r5. + */ +.macro save_guest_regs_mode mode, offset + add r2, vcpu, \offset + mrs r3, SP_\mode + mrs r4, LR_\mode + mrs r5, SPSR_\mode + stm r2, {r3, r4, r5} +.endm + +/* + * Save all guest registers to the vcpu struct + * Expects guest's r0, r1, r2 on the stack. + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2, r3, r4, r5. + */ +.macro save_guest_regs + @ Store usr registers + add r2, vcpu, #VCPU_USR_REG(3) + stm r2, {r3-r12} + add r2, vcpu, #VCPU_USR_REG(0) + pop {r3, r4, r5} @ r0, r1, r2 + stm r2, {r3, r4, r5} + mrs r2, SP_usr + mov r3, lr + str r2, [vcpu, #VCPU_USR_SP] + str r3, [vcpu, #VCPU_USR_LR] + + @ Store return state + mrs r2, ELR_hyp + mrs r3, spsr + str r2, [vcpu, #VCPU_PC] + str r3, [vcpu, #VCPU_CPSR] + + @ Store other guest registers + save_guest_regs_mode svc, #VCPU_SVC_REGS + save_guest_regs_mode abt, #VCPU_ABT_REGS + save_guest_regs_mode und, #VCPU_UND_REGS + save_guest_regs_mode irq, #VCPU_IRQ_REGS +.endm + +/* Reads cp15 registers from hardware and stores them in memory + * @store_to_vcpu: If 0, registers are written in-order to the stack, + * otherwise to the VCPU struct pointed to by vcpup + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2 - r12 + */ +.macro read_cp15_state store_to_vcpu + mrc p15, 0, r2, c1, c0, 0 @ SCTLR + mrc p15, 0, r3, c1, c0, 2 @ CPACR + mrc p15, 0, r4, c2, c0, 2 @ TTBCR + mrc p15, 0, r5, c3, c0, 0 @ DACR + mrrc p15, 0, r6, r7, c2 @ TTBR 0 + mrrc p15, 1, r8, r9, c2 @ TTBR 1 + mrc p15, 0, r10, c10, c2, 0 @ PRRR + mrc p15, 0, r11, c10, c2, 1 @ NMRR + mrc p15, 2, r12, c0, c0, 0 @ CSSELR + + .if \store_to_vcpu == 0 + push {r2-r12} @ Push CP15 registers + .else + str r2, [vcpu, #CP15_OFFSET(c1_SCTLR)] + str r3, [vcpu, #CP15_OFFSET(c1_CPACR)] + str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)] + str r5, [vcpu, #CP15_OFFSET(c3_DACR)] + add r2, vcpu, #CP15_OFFSET(c2_TTBR0) + strd r6, r7, [r2] + add r2, vcpu, #CP15_OFFSET(c2_TTBR1) + strd r8, r9, [r2] + str r10, [vcpu, #CP15_OFFSET(c10_PRRR)] + str r11, [vcpu, #CP15_OFFSET(c10_NMRR)] + str r12, [vcpu, #CP15_OFFSET(c0_CSSELR)] + .endif + + mrc p15, 0, r2, c13, c0, 1 @ CID + mrc p15, 0, r3, c13, c0, 2 @ TID_URW + mrc p15, 0, r4, c13, c0, 3 @ TID_URO + mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV + mrc p15, 0, r6, c5, c0, 0 @ DFSR + mrc p15, 0, r7, c5, c0, 1 @ IFSR + mrc p15, 0, r8, c5, c1, 0 @ ADFSR + mrc p15, 0, r9, c5, c1, 1 @ AIFSR + mrc p15, 0, r10, c6, c0, 0 @ DFAR + mrc p15, 0, r11, c6, c0, 2 @ IFAR + mrc p15, 0, r12, c12, c0, 0 @ VBAR + + .if \store_to_vcpu == 0 + push {r2-r12} @ Push CP15 registers + .else + str r2, [vcpu, #CP15_OFFSET(c13_CID)] + str r3, [vcpu, #CP15_OFFSET(c13_TID_URW)] + str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)] + str r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)] + str r6, [vcpu, #CP15_OFFSET(c5_DFSR)] + str r7, [vcpu, #CP15_OFFSET(c5_IFSR)] + str r8, [vcpu, #CP15_OFFSET(c5_ADFSR)] + str r9, [vcpu, #CP15_OFFSET(c5_AIFSR)] + str r10, [vcpu, #CP15_OFFSET(c6_DFAR)] + str r11, [vcpu, #CP15_OFFSET(c6_IFAR)] + str r12, [vcpu, #CP15_OFFSET(c12_VBAR)] + .endif +.endm + +/* + * Reads cp15 registers from memory and writes them to hardware + * @read_from_vcpu: If 0, registers are read in-order from the stack, + * otherwise from the VCPU struct pointed to by vcpup + * + * Assumes vcpu pointer in vcpu reg + */ +.macro write_cp15_state read_from_vcpu + .if \read_from_vcpu == 0 + pop {r2-r12} + .else + ldr r2, [vcpu, #CP15_OFFSET(c13_CID)] + ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)] + ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)] + ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)] + ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)] + ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)] + ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)] + ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)] + ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)] + ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)] + ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)] + .endif + + mcr p15, 0, r2, c13, c0, 1 @ CID + mcr p15, 0, r3, c13, c0, 2 @ TID_URW + mcr p15, 0, r4, c13, c0, 3 @ TID_URO + mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV + mcr p15, 0, r6, c5, c0, 0 @ DFSR + mcr p15, 0, r7, c5, c0, 1 @ IFSR + mcr p15, 0, r8, c5, c1, 0 @ ADFSR + mcr p15, 0, r9, c5, c1, 1 @ AIFSR + mcr p15, 0, r10, c6, c0, 0 @ DFAR + mcr p15, 0, r11, c6, c0, 2 @ IFAR + mcr p15, 0, r12, c12, c0, 0 @ VBAR + + .if \read_from_vcpu == 0 + pop {r2-r12} + .else + ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)] + ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)] + ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)] + ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)] + add r12, vcpu, #CP15_OFFSET(c2_TTBR0) + ldrd r6, r7, [r12] + add r12, vcpu, #CP15_OFFSET(c2_TTBR1) + ldrd r8, r9, [r12] + ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)] + ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)] + ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)] + .endif + + mcr p15, 0, r2, c1, c0, 0 @ SCTLR + mcr p15, 0, r3, c1, c0, 2 @ CPACR + mcr p15, 0, r4, c2, c0, 2 @ TTBCR + mcr p15, 0, r5, c3, c0, 0 @ DACR + mcrr p15, 0, r6, r7, c2 @ TTBR 0 + mcrr p15, 1, r8, r9, c2 @ TTBR 1 + mcr p15, 0, r10, c10, c2, 0 @ PRRR + mcr p15, 0, r11, c10, c2, 1 @ NMRR + mcr p15, 2, r12, c0, c0, 0 @ CSSELR +.endm + +/* + * Save the VGIC CPU state into memory + * + * Assumes vcpu pointer in vcpu reg + */ +.macro save_vgic_state +.endm + +/* + * Restore the VGIC CPU state from memory + * + * Assumes vcpu pointer in vcpu reg + */ +.macro restore_vgic_state +.endm + +.equ vmentry, 0 +.equ vmexit, 1 + +/* Configures the HSTR (Hyp System Trap Register) on entry/return + * (hardware reset value is 0) */ +.macro set_hstr operation + mrc p15, 4, r2, c1, c1, 3 + ldr r3, =HSTR_T(15) + .if \operation == vmentry + orr r2, r2, r3 @ Trap CR{15} + .else + bic r2, r2, r3 @ Don't trap any CRx accesses + .endif + mcr p15, 4, r2, c1, c1, 3 +.endm + +/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return + * (hardware reset value is 0). Keep previous value in r2. */ +.macro set_hcptr operation, mask + mrc p15, 4, r2, c1, c1, 2 + ldr r3, =\mask + .if \operation == vmentry + orr r3, r2, r3 @ Trap coproc-accesses defined in mask + .else + bic r3, r2, r3 @ Don't trap defined coproc-accesses + .endif + mcr p15, 4, r3, c1, c1, 2 +.endm + +/* Configures the HDCR (Hyp Debug Configuration Register) on entry/return + * (hardware reset value is 0) */ +.macro set_hdcr operation + mrc p15, 4, r2, c1, c1, 1 + ldr r3, =(HDCR_TPM|HDCR_TPMCR) + .if \operation == vmentry + orr r2, r2, r3 @ Trap some perfmon accesses + .else + bic r2, r2, r3 @ Don't trap any perfmon accesses + .endif + mcr p15, 4, r2, c1, c1, 1 +.endm + +/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */ +.macro configure_hyp_role operation + mrc p15, 4, r2, c1, c1, 0 @ HCR + bic r2, r2, #HCR_VIRT_EXCP_MASK + ldr r3, =HCR_GUEST_MASK + .if \operation == vmentry + orr r2, r2, r3 + ldr r3, [vcpu, #VCPU_IRQ_LINES] + orr r2, r2, r3 + .else + bic r2, r2, r3 + .endif + mcr p15, 4, r2, c1, c1, 0 +.endm + +.macro load_vcpu + mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR +.endm diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c new file mode 100644 index 00000000000..0144baf8290 --- /dev/null +++ b/arch/arm/kvm/mmio.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kvm_host.h> +#include <asm/kvm_mmio.h> +#include <asm/kvm_emulate.h> +#include <trace/events/kvm.h> + +#include "trace.h" + +/** + * kvm_handle_mmio_return -- Handle MMIO loads after user space emulation + * @vcpu: The VCPU pointer + * @run: The VCPU run struct containing the mmio data + * + * This should only be called after returning from userspace for MMIO load + * emulation. + */ +int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + __u32 *dest; + unsigned int len; + int mask; + + if (!run->mmio.is_write) { + dest = vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt); + memset(dest, 0, sizeof(int)); + + len = run->mmio.len; + if (len > 4) + return -EINVAL; + + memcpy(dest, run->mmio.data, len); + + trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, + *((u64 *)run->mmio.data)); + + if (vcpu->arch.mmio_decode.sign_extend && len < 4) { + mask = 1U << ((len * 8) - 1); + *dest = (*dest ^ mask) - mask; + } + } + + return 0; +} + +static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, + struct kvm_exit_mmio *mmio) +{ + unsigned long rt, len; + bool is_write, sign_extend; + + if ((vcpu->arch.hsr >> 8) & 1) { + /* cache operation on I/O addr, tell guest unsupported */ + kvm_inject_dabt(vcpu, vcpu->arch.hxfar); + return 1; + } + + if ((vcpu->arch.hsr >> 7) & 1) { + /* page table accesses IO mem: tell guest to fix its TTBR */ + kvm_inject_dabt(vcpu, vcpu->arch.hxfar); + return 1; + } + + switch ((vcpu->arch.hsr >> 22) & 0x3) { + case 0: + len = 1; + break; + case 1: + len = 2; + break; + case 2: + len = 4; + break; + default: + kvm_err("Hardware is weird: SAS 0b11 is reserved\n"); + return -EFAULT; + } + + is_write = vcpu->arch.hsr & HSR_WNR; + sign_extend = vcpu->arch.hsr & HSR_SSE; + rt = (vcpu->arch.hsr & HSR_SRT_MASK) >> HSR_SRT_SHIFT; + + if (kvm_vcpu_reg_is_pc(vcpu, rt)) { + /* IO memory trying to read/write pc */ + kvm_inject_pabt(vcpu, vcpu->arch.hxfar); + return 1; + } + + mmio->is_write = is_write; + mmio->phys_addr = fault_ipa; + mmio->len = len; + vcpu->arch.mmio_decode.sign_extend = sign_extend; + vcpu->arch.mmio_decode.rt = rt; + + /* + * The MMIO instruction is emulated and should not be re-executed + * in the guest. + */ + kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1); + return 0; +} + +int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, + phys_addr_t fault_ipa) +{ + struct kvm_exit_mmio mmio; + unsigned long rt; + int ret; + + /* + * Prepare MMIO operation. First stash it in a private + * structure that we can use for in-kernel emulation. If the + * kernel can't handle it, copy it into run->mmio and let user + * space do its magic. + */ + + if (vcpu->arch.hsr & HSR_ISV) { + ret = decode_hsr(vcpu, fault_ipa, &mmio); + if (ret) + return ret; + } else { + kvm_err("load/store instruction decoding not implemented\n"); + return -ENOSYS; + } + + rt = vcpu->arch.mmio_decode.rt; + trace_kvm_mmio((mmio.is_write) ? KVM_TRACE_MMIO_WRITE : + KVM_TRACE_MMIO_READ_UNSATISFIED, + mmio.len, fault_ipa, + (mmio.is_write) ? *vcpu_reg(vcpu, rt) : 0); + + if (mmio.is_write) + memcpy(mmio.data, vcpu_reg(vcpu, rt), mmio.len); + + kvm_prepare_mmio(run, &mmio); + return 0; +} diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c new file mode 100644 index 00000000000..f30e13163a9 --- /dev/null +++ b/arch/arm/kvm/mmu.c @@ -0,0 +1,787 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/mman.h> +#include <linux/kvm_host.h> +#include <linux/io.h> +#include <trace/events/kvm.h> +#include <asm/idmap.h> +#include <asm/pgalloc.h> +#include <asm/cacheflush.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_mmu.h> +#include <asm/kvm_mmio.h> +#include <asm/kvm_asm.h> +#include <asm/kvm_emulate.h> +#include <asm/mach/map.h> +#include <trace/events/kvm.h> + +#include "trace.h" + +extern char __hyp_idmap_text_start[], __hyp_idmap_text_end[]; + +static DEFINE_MUTEX(kvm_hyp_pgd_mutex); + +static void kvm_tlb_flush_vmid(struct kvm *kvm) +{ + kvm_call_hyp(__kvm_tlb_flush_vmid, kvm); +} + +static void kvm_set_pte(pte_t *pte, pte_t new_pte) +{ + pte_val(*pte) = new_pte; + /* + * flush_pmd_entry just takes a void pointer and cleans the necessary + * cache entries, so we can reuse the function for ptes. + */ + flush_pmd_entry(pte); +} + +static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, + int min, int max) +{ + void *page; + + BUG_ON(max > KVM_NR_MEM_OBJS); + if (cache->nobjs >= min) + return 0; + while (cache->nobjs < max) { + page = (void *)__get_free_page(PGALLOC_GFP); + if (!page) + return -ENOMEM; + cache->objects[cache->nobjs++] = page; + } + return 0; +} + +static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc) +{ + while (mc->nobjs) + free_page((unsigned long)mc->objects[--mc->nobjs]); +} + +static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) +{ + void *p; + + BUG_ON(!mc || !mc->nobjs); + p = mc->objects[--mc->nobjs]; + return p; +} + +static void free_ptes(pmd_t *pmd, unsigned long addr) +{ + pte_t *pte; + unsigned int i; + + for (i = 0; i < PTRS_PER_PMD; i++, addr += PMD_SIZE) { + if (!pmd_none(*pmd) && pmd_table(*pmd)) { + pte = pte_offset_kernel(pmd, addr); + pte_free_kernel(NULL, pte); + } + pmd++; + } +} + +/** + * free_hyp_pmds - free a Hyp-mode level-2 tables and child level-3 tables + * + * Assumes this is a page table used strictly in Hyp-mode and therefore contains + * only mappings in the kernel memory area, which is above PAGE_OFFSET. + */ +void free_hyp_pmds(void) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + unsigned long addr; + + mutex_lock(&kvm_hyp_pgd_mutex); + for (addr = PAGE_OFFSET; addr != 0; addr += PGDIR_SIZE) { + pgd = hyp_pgd + pgd_index(addr); + pud = pud_offset(pgd, addr); + + if (pud_none(*pud)) + continue; + BUG_ON(pud_bad(*pud)); + + pmd = pmd_offset(pud, addr); + free_ptes(pmd, addr); + pmd_free(NULL, pmd); + pud_clear(pud); + } + mutex_unlock(&kvm_hyp_pgd_mutex); +} + +static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start, + unsigned long end) +{ + pte_t *pte; + unsigned long addr; + struct page *page; + + for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) { + pte = pte_offset_kernel(pmd, addr); + BUG_ON(!virt_addr_valid(addr)); + page = virt_to_page(addr); + kvm_set_pte(pte, mk_pte(page, PAGE_HYP)); + } +} + +static void create_hyp_io_pte_mappings(pmd_t *pmd, unsigned long start, + unsigned long end, + unsigned long *pfn_base) +{ + pte_t *pte; + unsigned long addr; + + for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) { + pte = pte_offset_kernel(pmd, addr); + BUG_ON(pfn_valid(*pfn_base)); + kvm_set_pte(pte, pfn_pte(*pfn_base, PAGE_HYP_DEVICE)); + (*pfn_base)++; + } +} + +static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start, + unsigned long end, unsigned long *pfn_base) +{ + pmd_t *pmd; + pte_t *pte; + unsigned long addr, next; + + for (addr = start; addr < end; addr = next) { + pmd = pmd_offset(pud, addr); + + BUG_ON(pmd_sect(*pmd)); + + if (pmd_none(*pmd)) { + pte = pte_alloc_one_kernel(NULL, addr); + if (!pte) { + kvm_err("Cannot allocate Hyp pte\n"); + return -ENOMEM; + } + pmd_populate_kernel(NULL, pmd, pte); + } + + next = pmd_addr_end(addr, end); + + /* + * If pfn_base is NULL, we map kernel pages into HYP with the + * virtual address. Otherwise, this is considered an I/O + * mapping and we map the physical region starting at + * *pfn_base to [start, end[. + */ + if (!pfn_base) + create_hyp_pte_mappings(pmd, addr, next); + else + create_hyp_io_pte_mappings(pmd, addr, next, pfn_base); + } + + return 0; +} + +static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base) +{ + unsigned long start = (unsigned long)from; + unsigned long end = (unsigned long)to; + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + unsigned long addr, next; + int err = 0; + + BUG_ON(start > end); + if (start < PAGE_OFFSET) + return -EINVAL; + + mutex_lock(&kvm_hyp_pgd_mutex); + for (addr = start; addr < end; addr = next) { + pgd = hyp_pgd + pgd_index(addr); + pud = pud_offset(pgd, addr); + + if (pud_none_or_clear_bad(pud)) { + pmd = pmd_alloc_one(NULL, addr); + if (!pmd) { + kvm_err("Cannot allocate Hyp pmd\n"); + err = -ENOMEM; + goto out; + } + pud_populate(NULL, pud, pmd); + } + + next = pgd_addr_end(addr, end); + err = create_hyp_pmd_mappings(pud, addr, next, pfn_base); + if (err) + goto out; + } +out: + mutex_unlock(&kvm_hyp_pgd_mutex); + return err; +} + +/** + * create_hyp_mappings - map a kernel virtual address range in Hyp mode + * @from: The virtual kernel start address of the range + * @to: The virtual kernel end address of the range (exclusive) + * + * The same virtual address as the kernel virtual address is also used in + * Hyp-mode mapping to the same underlying physical pages. + * + * Note: Wrapping around zero in the "to" address is not supported. + */ +int create_hyp_mappings(void *from, void *to) +{ + return __create_hyp_mappings(from, to, NULL); +} + +/** + * create_hyp_io_mappings - map a physical IO range in Hyp mode + * @from: The virtual HYP start address of the range + * @to: The virtual HYP end address of the range (exclusive) + * @addr: The physical start address which gets mapped + */ +int create_hyp_io_mappings(void *from, void *to, phys_addr_t addr) +{ + unsigned long pfn = __phys_to_pfn(addr); + return __create_hyp_mappings(from, to, &pfn); +} + +/** + * kvm_alloc_stage2_pgd - allocate level-1 table for stage-2 translation. + * @kvm: The KVM struct pointer for the VM. + * + * Allocates the 1st level table only of size defined by S2_PGD_ORDER (can + * support either full 40-bit input addresses or limited to 32-bit input + * addresses). Clears the allocated pages. + * + * Note we don't need locking here as this is only called when the VM is + * created, which can only be done once. + */ +int kvm_alloc_stage2_pgd(struct kvm *kvm) +{ + pgd_t *pgd; + + if (kvm->arch.pgd != NULL) { + kvm_err("kvm_arch already initialized?\n"); + return -EINVAL; + } + + pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, S2_PGD_ORDER); + if (!pgd) + return -ENOMEM; + + /* stage-2 pgd must be aligned to its size */ + VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1)); + + memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t)); + clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t)); + kvm->arch.pgd = pgd; + + return 0; +} + +static void clear_pud_entry(pud_t *pud) +{ + pmd_t *pmd_table = pmd_offset(pud, 0); + pud_clear(pud); + pmd_free(NULL, pmd_table); + put_page(virt_to_page(pud)); +} + +static void clear_pmd_entry(pmd_t *pmd) +{ + pte_t *pte_table = pte_offset_kernel(pmd, 0); + pmd_clear(pmd); + pte_free_kernel(NULL, pte_table); + put_page(virt_to_page(pmd)); +} + +static bool pmd_empty(pmd_t *pmd) +{ + struct page *pmd_page = virt_to_page(pmd); + return page_count(pmd_page) == 1; +} + +static void clear_pte_entry(pte_t *pte) +{ + if (pte_present(*pte)) { + kvm_set_pte(pte, __pte(0)); + put_page(virt_to_page(pte)); + } +} + +static bool pte_empty(pte_t *pte) +{ + struct page *pte_page = virt_to_page(pte); + return page_count(pte_page) == 1; +} + +/** + * unmap_stage2_range -- Clear stage2 page table entries to unmap a range + * @kvm: The VM pointer + * @start: The intermediate physical base address of the range to unmap + * @size: The size of the area to unmap + * + * Clear a range of stage-2 mappings, lowering the various ref-counts. Must + * be called while holding mmu_lock (unless for freeing the stage2 pgd before + * destroying the VM), otherwise another faulting VCPU may come in and mess + * with things behind our backs. + */ +static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + phys_addr_t addr = start, end = start + size; + u64 range; + + while (addr < end) { + pgd = kvm->arch.pgd + pgd_index(addr); + pud = pud_offset(pgd, addr); + if (pud_none(*pud)) { + addr += PUD_SIZE; + continue; + } + + pmd = pmd_offset(pud, addr); + if (pmd_none(*pmd)) { + addr += PMD_SIZE; + continue; + } + + pte = pte_offset_kernel(pmd, addr); + clear_pte_entry(pte); + range = PAGE_SIZE; + + /* If we emptied the pte, walk back up the ladder */ + if (pte_empty(pte)) { + clear_pmd_entry(pmd); + range = PMD_SIZE; + if (pmd_empty(pmd)) { + clear_pud_entry(pud); + range = PUD_SIZE; + } + } + + addr += range; + } +} + +/** + * kvm_free_stage2_pgd - free all stage-2 tables + * @kvm: The KVM struct pointer for the VM. + * + * Walks the level-1 page table pointed to by kvm->arch.pgd and frees all + * underlying level-2 and level-3 tables before freeing the actual level-1 table + * and setting the struct pointer to NULL. + * + * Note we don't need locking here as this is only called when the VM is + * destroyed, which can only be done once. + */ +void kvm_free_stage2_pgd(struct kvm *kvm) +{ + if (kvm->arch.pgd == NULL) + return; + + unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE); + free_pages((unsigned long)kvm->arch.pgd, S2_PGD_ORDER); + kvm->arch.pgd = NULL; +} + + +static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, + phys_addr_t addr, const pte_t *new_pte, bool iomap) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte, old_pte; + + /* Create 2nd stage page table mapping - Level 1 */ + pgd = kvm->arch.pgd + pgd_index(addr); + pud = pud_offset(pgd, addr); + if (pud_none(*pud)) { + if (!cache) + return 0; /* ignore calls from kvm_set_spte_hva */ + pmd = mmu_memory_cache_alloc(cache); + pud_populate(NULL, pud, pmd); + pmd += pmd_index(addr); + get_page(virt_to_page(pud)); + } else + pmd = pmd_offset(pud, addr); + + /* Create 2nd stage page table mapping - Level 2 */ + if (pmd_none(*pmd)) { + if (!cache) + return 0; /* ignore calls from kvm_set_spte_hva */ + pte = mmu_memory_cache_alloc(cache); + clean_pte_table(pte); + pmd_populate_kernel(NULL, pmd, pte); + pte += pte_index(addr); + get_page(virt_to_page(pmd)); + } else + pte = pte_offset_kernel(pmd, addr); + + if (iomap && pte_present(*pte)) + return -EFAULT; + + /* Create 2nd stage page table mapping - Level 3 */ + old_pte = *pte; + kvm_set_pte(pte, *new_pte); + if (pte_present(old_pte)) + kvm_tlb_flush_vmid(kvm); + else + get_page(virt_to_page(pte)); + + return 0; +} + +/** + * kvm_phys_addr_ioremap - map a device range to guest IPA + * + * @kvm: The KVM pointer + * @guest_ipa: The IPA at which to insert the mapping + * @pa: The physical address of the device + * @size: The size of the mapping + */ +int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, + phys_addr_t pa, unsigned long size) +{ + phys_addr_t addr, end; + int ret = 0; + unsigned long pfn; + struct kvm_mmu_memory_cache cache = { 0, }; + + end = (guest_ipa + size + PAGE_SIZE - 1) & PAGE_MASK; + pfn = __phys_to_pfn(pa); + + for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) { + pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE | L_PTE_S2_RDWR); + + ret = mmu_topup_memory_cache(&cache, 2, 2); + if (ret) + goto out; + spin_lock(&kvm->mmu_lock); + ret = stage2_set_pte(kvm, &cache, addr, &pte, true); + spin_unlock(&kvm->mmu_lock); + if (ret) + goto out; + + pfn++; + } + +out: + mmu_free_memory_cache(&cache); + return ret; +} + +static void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn) +{ + /* + * If we are going to insert an instruction page and the icache is + * either VIPT or PIPT, there is a potential problem where the host + * (or another VM) may have used the same page as this guest, and we + * read incorrect data from the icache. If we're using a PIPT cache, + * we can invalidate just that page, but if we are using a VIPT cache + * we need to invalidate the entire icache - damn shame - as written + * in the ARM ARM (DDI 0406C.b - Page B3-1393). + * + * VIVT caches are tagged using both the ASID and the VMID and doesn't + * need any kind of flushing (DDI 0406C.b - Page B3-1392). + */ + if (icache_is_pipt()) { + unsigned long hva = gfn_to_hva(kvm, gfn); + __cpuc_coherent_user_range(hva, hva + PAGE_SIZE); + } else if (!icache_is_vivt_asid_tagged()) { + /* any kind of VIPT cache */ + __flush_icache_all(); + } +} + +static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, + gfn_t gfn, struct kvm_memory_slot *memslot, + unsigned long fault_status) +{ + pte_t new_pte; + pfn_t pfn; + int ret; + bool write_fault, writable; + unsigned long mmu_seq; + struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache; + + write_fault = kvm_is_write_fault(vcpu->arch.hsr); + if (fault_status == FSC_PERM && !write_fault) { + kvm_err("Unexpected L2 read permission error\n"); + return -EFAULT; + } + + /* We need minimum second+third level pages */ + ret = mmu_topup_memory_cache(memcache, 2, KVM_NR_MEM_OBJS); + if (ret) + return ret; + + mmu_seq = vcpu->kvm->mmu_notifier_seq; + /* + * Ensure the read of mmu_notifier_seq happens before we call + * gfn_to_pfn_prot (which calls get_user_pages), so that we don't risk + * the page we just got a reference to gets unmapped before we have a + * chance to grab the mmu_lock, which ensure that if the page gets + * unmapped afterwards, the call to kvm_unmap_hva will take it away + * from us again properly. This smp_rmb() interacts with the smp_wmb() + * in kvm_mmu_notifier_invalidate_<page|range_end>. + */ + smp_rmb(); + + pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write_fault, &writable); + if (is_error_pfn(pfn)) + return -EFAULT; + + new_pte = pfn_pte(pfn, PAGE_S2); + coherent_icache_guest_page(vcpu->kvm, gfn); + + spin_lock(&vcpu->kvm->mmu_lock); + if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) + goto out_unlock; + if (writable) { + pte_val(new_pte) |= L_PTE_S2_RDWR; + kvm_set_pfn_dirty(pfn); + } + stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false); + +out_unlock: + spin_unlock(&vcpu->kvm->mmu_lock); + kvm_release_pfn_clean(pfn); + return 0; +} + +/** + * kvm_handle_guest_abort - handles all 2nd stage aborts + * @vcpu: the VCPU pointer + * @run: the kvm_run structure + * + * Any abort that gets to the host is almost guaranteed to be caused by a + * missing second stage translation table entry, which can mean that either the + * guest simply needs more memory and we must allocate an appropriate page or it + * can mean that the guest tried to access I/O memory, which is emulated by user + * space. The distinction is based on the IPA causing the fault and whether this + * memory region has been registered as standard RAM by user space. + */ +int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + unsigned long hsr_ec; + unsigned long fault_status; + phys_addr_t fault_ipa; + struct kvm_memory_slot *memslot; + bool is_iabt; + gfn_t gfn; + int ret, idx; + + hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT; + is_iabt = (hsr_ec == HSR_EC_IABT); + fault_ipa = ((phys_addr_t)vcpu->arch.hpfar & HPFAR_MASK) << 8; + + trace_kvm_guest_fault(*vcpu_pc(vcpu), vcpu->arch.hsr, + vcpu->arch.hxfar, fault_ipa); + + /* Check the stage-2 fault is trans. fault or write fault */ + fault_status = (vcpu->arch.hsr & HSR_FSC_TYPE); + if (fault_status != FSC_FAULT && fault_status != FSC_PERM) { + kvm_err("Unsupported fault status: EC=%#lx DFCS=%#lx\n", + hsr_ec, fault_status); + return -EFAULT; + } + + idx = srcu_read_lock(&vcpu->kvm->srcu); + + gfn = fault_ipa >> PAGE_SHIFT; + if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) { + if (is_iabt) { + /* Prefetch Abort on I/O address */ + kvm_inject_pabt(vcpu, vcpu->arch.hxfar); + ret = 1; + goto out_unlock; + } + + if (fault_status != FSC_FAULT) { + kvm_err("Unsupported fault status on io memory: %#lx\n", + fault_status); + ret = -EFAULT; + goto out_unlock; + } + + /* Adjust page offset */ + fault_ipa |= vcpu->arch.hxfar & ~PAGE_MASK; + ret = io_mem_abort(vcpu, run, fault_ipa); + goto out_unlock; + } + + memslot = gfn_to_memslot(vcpu->kvm, gfn); + if (!memslot->user_alloc) { + kvm_err("non user-alloc memslots not supported\n"); + ret = -EINVAL; + goto out_unlock; + } + + ret = user_mem_abort(vcpu, fault_ipa, gfn, memslot, fault_status); + if (ret == 0) + ret = 1; +out_unlock: + srcu_read_unlock(&vcpu->kvm->srcu, idx); + return ret; +} + +static void handle_hva_to_gpa(struct kvm *kvm, + unsigned long start, + unsigned long end, + void (*handler)(struct kvm *kvm, + gpa_t gpa, void *data), + void *data) +{ + struct kvm_memslots *slots; + struct kvm_memory_slot *memslot; + + slots = kvm_memslots(kvm); + + /* we only care about the pages that the guest sees */ + kvm_for_each_memslot(memslot, slots) { + unsigned long hva_start, hva_end; + gfn_t gfn, gfn_end; + + hva_start = max(start, memslot->userspace_addr); + hva_end = min(end, memslot->userspace_addr + + (memslot->npages << PAGE_SHIFT)); + if (hva_start >= hva_end) + continue; + + /* + * {gfn(page) | page intersects with [hva_start, hva_end)} = + * {gfn_start, gfn_start+1, ..., gfn_end-1}. + */ + gfn = hva_to_gfn_memslot(hva_start, memslot); + gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); + + for (; gfn < gfn_end; ++gfn) { + gpa_t gpa = gfn << PAGE_SHIFT; + handler(kvm, gpa, data); + } + } +} + +static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data) +{ + unmap_stage2_range(kvm, gpa, PAGE_SIZE); + kvm_tlb_flush_vmid(kvm); +} + +int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) +{ + unsigned long end = hva + PAGE_SIZE; + + if (!kvm->arch.pgd) + return 0; + + trace_kvm_unmap_hva(hva); + handle_hva_to_gpa(kvm, hva, end, &kvm_unmap_hva_handler, NULL); + return 0; +} + +int kvm_unmap_hva_range(struct kvm *kvm, + unsigned long start, unsigned long end) +{ + if (!kvm->arch.pgd) + return 0; + + trace_kvm_unmap_hva_range(start, end); + handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL); + return 0; +} + +static void kvm_set_spte_handler(struct kvm *kvm, gpa_t gpa, void *data) +{ + pte_t *pte = (pte_t *)data; + + stage2_set_pte(kvm, NULL, gpa, pte, false); +} + + +void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) +{ + unsigned long end = hva + PAGE_SIZE; + pte_t stage2_pte; + + if (!kvm->arch.pgd) + return; + + trace_kvm_set_spte_hva(hva); + stage2_pte = pfn_pte(pte_pfn(pte), PAGE_S2); + handle_hva_to_gpa(kvm, hva, end, &kvm_set_spte_handler, &stage2_pte); +} + +void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu) +{ + mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); +} + +phys_addr_t kvm_mmu_get_httbr(void) +{ + VM_BUG_ON(!virt_addr_valid(hyp_pgd)); + return virt_to_phys(hyp_pgd); +} + +int kvm_mmu_init(void) +{ + if (!hyp_pgd) { + kvm_err("Hyp mode PGD not allocated\n"); + return -ENOMEM; + } + + return 0; +} + +/** + * kvm_clear_idmap - remove all idmaps from the hyp pgd + * + * Free the underlying pmds for all pgds in range and clear the pgds (but + * don't free them) afterwards. + */ +void kvm_clear_hyp_idmap(void) +{ + unsigned long addr, end; + unsigned long next; + pgd_t *pgd = hyp_pgd; + pud_t *pud; + pmd_t *pmd; + + addr = virt_to_phys(__hyp_idmap_text_start); + end = virt_to_phys(__hyp_idmap_text_end); + + pgd += pgd_index(addr); + do { + next = pgd_addr_end(addr, end); + if (pgd_none_or_clear_bad(pgd)) + continue; + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); + + pud_clear(pud); + clean_pmd_entry(pmd); + pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK)); + } while (pgd++, addr = next, addr < end); +} diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c new file mode 100644 index 00000000000..7ee5bb7a366 --- /dev/null +++ b/arch/arm/kvm/psci.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2012 - ARM Ltd + * Author: Marc Zyngier <marc.zyngier@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/kvm_host.h> +#include <linux/wait.h> + +#include <asm/kvm_emulate.h> +#include <asm/kvm_psci.h> + +/* + * This is an implementation of the Power State Coordination Interface + * as described in ARM document number ARM DEN 0022A. + */ + +static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu) +{ + vcpu->arch.pause = true; +} + +static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) +{ + struct kvm *kvm = source_vcpu->kvm; + struct kvm_vcpu *vcpu; + wait_queue_head_t *wq; + unsigned long cpu_id; + phys_addr_t target_pc; + + cpu_id = *vcpu_reg(source_vcpu, 1); + if (vcpu_mode_is_32bit(source_vcpu)) + cpu_id &= ~((u32) 0); + + if (cpu_id >= atomic_read(&kvm->online_vcpus)) + return KVM_PSCI_RET_INVAL; + + target_pc = *vcpu_reg(source_vcpu, 2); + + vcpu = kvm_get_vcpu(kvm, cpu_id); + + wq = kvm_arch_vcpu_wq(vcpu); + if (!waitqueue_active(wq)) + return KVM_PSCI_RET_INVAL; + + kvm_reset_vcpu(vcpu); + + /* Gracefully handle Thumb2 entry point */ + if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { + target_pc &= ~((phys_addr_t) 1); + vcpu_set_thumb(vcpu); + } + + *vcpu_pc(vcpu) = target_pc; + vcpu->arch.pause = false; + smp_mb(); /* Make sure the above is visible */ + + wake_up_interruptible(wq); + + return KVM_PSCI_RET_SUCCESS; +} + +/** + * kvm_psci_call - handle PSCI call if r0 value is in range + * @vcpu: Pointer to the VCPU struct + * + * Handle PSCI calls from guests through traps from HVC or SMC instructions. + * The calling convention is similar to SMC calls to the secure world where + * the function number is placed in r0 and this function returns true if the + * function number specified in r0 is withing the PSCI range, and false + * otherwise. + */ +bool kvm_psci_call(struct kvm_vcpu *vcpu) +{ + unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0); + unsigned long val; + + switch (psci_fn) { + case KVM_PSCI_FN_CPU_OFF: + kvm_psci_vcpu_off(vcpu); + val = KVM_PSCI_RET_SUCCESS; + break; + case KVM_PSCI_FN_CPU_ON: + val = kvm_psci_vcpu_on(vcpu); + break; + case KVM_PSCI_FN_CPU_SUSPEND: + case KVM_PSCI_FN_MIGRATE: + val = KVM_PSCI_RET_NI; + break; + + default: + return false; + } + + *vcpu_reg(vcpu, 0) = val; + return true; +} diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c new file mode 100644 index 00000000000..b80256b554c --- /dev/null +++ b/arch/arm/kvm/reset.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2012 - Virtual Open Systems and Columbia University + * Author: Christoffer Dall <c.dall@virtualopensystems.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#include <linux/compiler.h> +#include <linux/errno.h> +#include <linux/sched.h> +#include <linux/kvm_host.h> +#include <linux/kvm.h> + +#include <asm/unified.h> +#include <asm/ptrace.h> +#include <asm/cputype.h> +#include <asm/kvm_arm.h> +#include <asm/kvm_coproc.h> + +/****************************************************************************** + * Cortex-A15 Reset Values + */ + +static const int a15_max_cpu_idx = 3; + +static struct kvm_regs a15_regs_reset = { + .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT, +}; + + +/******************************************************************************* + * Exported reset function + */ + +/** + * kvm_reset_vcpu - sets core registers and cp15 registers to reset value + * @vcpu: The VCPU pointer + * + * This function finds the right table above and sets the registers on the + * virtual CPU struct to their architectually defined reset values. + */ +int kvm_reset_vcpu(struct kvm_vcpu *vcpu) +{ + struct kvm_regs *cpu_reset; + + switch (vcpu->arch.target) { + case KVM_ARM_TARGET_CORTEX_A15: + if (vcpu->vcpu_id > a15_max_cpu_idx) + return -EINVAL; + cpu_reset = &a15_regs_reset; + vcpu->arch.midr = read_cpuid_id(); + break; + default: + return -ENODEV; + } + + /* Reset core registers */ + memcpy(&vcpu->arch.regs, cpu_reset, sizeof(vcpu->arch.regs)); + + /* Reset CP15 registers */ + kvm_reset_coprocs(vcpu); + + return 0; +} diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h new file mode 100644 index 00000000000..a8e73ed5ad5 --- /dev/null +++ b/arch/arm/kvm/trace.h @@ -0,0 +1,235 @@ +#if !defined(_TRACE_KVM_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_KVM_H + +#include <linux/tracepoint.h> + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM kvm + +/* + * Tracepoints for entry/exit to guest + */ +TRACE_EVENT(kvm_entry, + TP_PROTO(unsigned long vcpu_pc), + TP_ARGS(vcpu_pc), + + TP_STRUCT__entry( + __field( unsigned long, vcpu_pc ) + ), + + TP_fast_assign( + __entry->vcpu_pc = vcpu_pc; + ), + + TP_printk("PC: 0x%08lx", __entry->vcpu_pc) +); + +TRACE_EVENT(kvm_exit, + TP_PROTO(unsigned long vcpu_pc), + TP_ARGS(vcpu_pc), + + TP_STRUCT__entry( + __field( unsigned long, vcpu_pc ) + ), + + TP_fast_assign( + __entry->vcpu_pc = vcpu_pc; + ), + + TP_printk("PC: 0x%08lx", __entry->vcpu_pc) +); + +TRACE_EVENT(kvm_guest_fault, + TP_PROTO(unsigned long vcpu_pc, unsigned long hsr, + unsigned long hxfar, + unsigned long long ipa), + TP_ARGS(vcpu_pc, hsr, hxfar, ipa), + + TP_STRUCT__entry( + __field( unsigned long, vcpu_pc ) + __field( unsigned long, hsr ) + __field( unsigned long, hxfar ) + __field( unsigned long long, ipa ) + ), + + TP_fast_assign( + __entry->vcpu_pc = vcpu_pc; + __entry->hsr = hsr; + __entry->hxfar = hxfar; + __entry->ipa = ipa; + ), + + TP_printk("guest fault at PC %#08lx (hxfar %#08lx, " + "ipa %#16llx, hsr %#08lx", + __entry->vcpu_pc, __entry->hxfar, + __entry->ipa, __entry->hsr) +); + +TRACE_EVENT(kvm_irq_line, + TP_PROTO(unsigned int type, int vcpu_idx, int irq_num, int level), + TP_ARGS(type, vcpu_idx, irq_num, level), + + TP_STRUCT__entry( + __field( unsigned int, type ) + __field( int, vcpu_idx ) + __field( int, irq_num ) + __field( int, level ) + ), + + TP_fast_assign( + __entry->type = type; + __entry->vcpu_idx = vcpu_idx; + __entry->irq_num = irq_num; + __entry->level = level; + ), + + TP_printk("Inject %s interrupt (%d), vcpu->idx: %d, num: %d, level: %d", + (__entry->type == KVM_ARM_IRQ_TYPE_CPU) ? "CPU" : + (__entry->type == KVM_ARM_IRQ_TYPE_PPI) ? "VGIC PPI" : + (__entry->type == KVM_ARM_IRQ_TYPE_SPI) ? "VGIC SPI" : "UNKNOWN", + __entry->type, __entry->vcpu_idx, __entry->irq_num, __entry->level) +); + +TRACE_EVENT(kvm_mmio_emulate, + TP_PROTO(unsigned long vcpu_pc, unsigned long instr, + unsigned long cpsr), + TP_ARGS(vcpu_pc, instr, cpsr), + + TP_STRUCT__entry( + __field( unsigned long, vcpu_pc ) + __field( unsigned long, instr ) + __field( unsigned long, cpsr ) + ), + + TP_fast_assign( + __entry->vcpu_pc = vcpu_pc; + __entry->instr = instr; + __entry->cpsr = cpsr; + ), + + TP_printk("Emulate MMIO at: 0x%08lx (instr: %08lx, cpsr: %08lx)", + __entry->vcpu_pc, __entry->instr, __entry->cpsr) +); + +/* Architecturally implementation defined CP15 register access */ +TRACE_EVENT(kvm_emulate_cp15_imp, + TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn, + unsigned long CRm, unsigned long Op2, bool is_write), + TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write), + + TP_STRUCT__entry( + __field( unsigned int, Op1 ) + __field( unsigned int, Rt1 ) + __field( unsigned int, CRn ) + __field( unsigned int, CRm ) + __field( unsigned int, Op2 ) + __field( bool, is_write ) + ), + + TP_fast_assign( + __entry->is_write = is_write; + __entry->Op1 = Op1; + __entry->Rt1 = Rt1; + __entry->CRn = CRn; + __entry->CRm = CRm; + __entry->Op2 = Op2; + ), + + TP_printk("Implementation defined CP15: %s\tp15, %u, r%u, c%u, c%u, %u", + (__entry->is_write) ? "mcr" : "mrc", + __entry->Op1, __entry->Rt1, __entry->CRn, + __entry->CRm, __entry->Op2) +); + +TRACE_EVENT(kvm_wfi, + TP_PROTO(unsigned long vcpu_pc), + TP_ARGS(vcpu_pc), + + TP_STRUCT__entry( + __field( unsigned long, vcpu_pc ) + ), + + TP_fast_assign( + __entry->vcpu_pc = vcpu_pc; + ), + + TP_printk("guest executed wfi at: 0x%08lx", __entry->vcpu_pc) +); + +TRACE_EVENT(kvm_unmap_hva, + TP_PROTO(unsigned long hva), + TP_ARGS(hva), + + TP_STRUCT__entry( + __field( unsigned long, hva ) + ), + + TP_fast_assign( + __entry->hva = hva; + ), + + TP_printk("mmu notifier unmap hva: %#08lx", __entry->hva) +); + +TRACE_EVENT(kvm_unmap_hva_range, + TP_PROTO(unsigned long start, unsigned long end), + TP_ARGS(start, end), + + TP_STRUCT__entry( + __field( unsigned long, start ) + __field( unsigned long, end ) + ), + + TP_fast_assign( + __entry->start = start; + __entry->end = end; + ), + + TP_printk("mmu notifier unmap range: %#08lx -- %#08lx", + __entry->start, __entry->end) +); + +TRACE_EVENT(kvm_set_spte_hva, + TP_PROTO(unsigned long hva), + TP_ARGS(hva), + + TP_STRUCT__entry( + __field( unsigned long, hva ) + ), + + TP_fast_assign( + __entry->hva = hva; + ), + + TP_printk("mmu notifier set pte hva: %#08lx", __entry->hva) +); + +TRACE_EVENT(kvm_hvc, + TP_PROTO(unsigned long vcpu_pc, unsigned long r0, unsigned long imm), + TP_ARGS(vcpu_pc, r0, imm), + + TP_STRUCT__entry( + __field( unsigned long, vcpu_pc ) + __field( unsigned long, r0 ) + __field( unsigned long, imm ) + ), + + TP_fast_assign( + __entry->vcpu_pc = vcpu_pc; + __entry->r0 = r0; + __entry->imm = imm; + ), + + TP_printk("HVC at 0x%08lx (r0: 0x%08lx, imm: 0x%lx", + __entry->vcpu_pc, __entry->r0, __entry->imm) +); + +#endif /* _TRACE_KVM_H */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH arch/arm/kvm +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 958358c91af..6071f4c3d65 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -352,12 +352,6 @@ config MACH_USB_A9263 Select this if you are using a Calao Systems USB-A9263. <http://www.calao-systems.com> -config MACH_NEOCORE926 - bool "Adeneo NEOCORE926" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using the Adeneo Neocore 926 board. - endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index b38a1dcb79b..39218ca6d8e 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -66,7 +66,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o # AT91SAM9263 board-specific support obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o obj-$(CONFIG_MACH_USB_A9263) += board-usb-a926x.o -obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o # AT91SAM9RL board-specific support obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index cafe98836c8..2acdff4c1df 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) static struct clock_event_device clkevt = { .name = "at91_tick", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 150, .set_next_event = clkevt32k_next_event, .set_mode = clkevt32k_mode, @@ -265,17 +264,10 @@ void __init at91rm9200_timer_init(void) at91_st_write(AT91_ST_RTMR, 1); /* Setup timer clockevent, with minimum of two ticks (important!!) */ - clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); - clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); - clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&clkevt); + clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, + 2, AT91_ST_ALMV); /* register clocksource */ clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); } - -struct sys_timer at91rm9200_timer = { - .init = at91rm9200_timer_init, -}; - diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 358412f1f5f..3a4bc2e1a65 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -104,12 +104,38 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) } } +static void at91sam926x_pit_suspend(struct clock_event_device *cedev) +{ + /* Disable timer */ + pit_write(AT91_PIT_MR, 0); +} + +static void at91sam926x_pit_reset(void) +{ + /* Disable timer and irqs */ + pit_write(AT91_PIT_MR, 0); + + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0) + cpu_relax(); + + /* Start PIT but don't enable IRQ */ + pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); +} + +static void at91sam926x_pit_resume(struct clock_event_device *cedev) +{ + at91sam926x_pit_reset(); +} + static struct clock_event_device pit_clkevt = { .name = "pit", .features = CLOCK_EVT_FEAT_PERIODIC, .shift = 32, .rating = 100, .set_mode = pit_clkevt_mode, + .suspend = at91sam926x_pit_suspend, + .resume = at91sam926x_pit_resume, }; @@ -150,19 +176,6 @@ static struct irqaction at91sam926x_pit_irq = { .irq = NR_IRQS_LEGACY + AT91_ID_SYS, }; -static void at91sam926x_pit_reset(void) -{ - /* Disable timer and irqs */ - pit_write(AT91_PIT_MR, 0); - - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0) - cpu_relax(); - - /* Start PIT but don't enable IRQ */ - pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); -} - #ifdef CONFIG_OF static struct of_device_id pit_timer_ids[] = { { .compatible = "atmel,at91sam9260-pit" }, @@ -211,7 +224,7 @@ static int __init of_at91sam926x_pit_init(void) /* * Set up both clocksource and clockevent support. */ -static void __init at91sam926x_pit_init(void) +void __init at91sam926x_pit_init(void) { unsigned long pit_rate; unsigned bits; @@ -250,12 +263,6 @@ static void __init at91sam926x_pit_init(void) clockevents_register_device(&pit_clkevt); } -static void at91sam926x_pit_suspend(void) -{ - /* Disable timer */ - pit_write(AT91_PIT_MR, 0); -} - void __init at91sam926x_ioremap_pit(u32 addr) { #if defined(CONFIG_OF) @@ -272,9 +279,3 @@ void __init at91sam926x_ioremap_pit(u32 addr) if (!pit_base_addr) panic("Impossible to ioremap PIT\n"); } - -struct sys_timer at91sam926x_timer = { - .init = at91sam926x_pit_init, - .suspend = at91sam926x_pit_suspend, - .resume = at91sam926x_pit_reset, -}; diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c index 0e57e440c06..0c07a4459cb 100644 --- a/arch/arm/mach-at91/at91x40_time.c +++ b/arch/arm/mach-at91/at91x40_time.c @@ -42,9 +42,10 @@ #define AT91_TC_CLK1BASE 0x40 #define AT91_TC_CLK2BASE 0x80 -static unsigned long at91x40_gettimeoffset(void) +static u32 at91x40_gettimeoffset(void) { - return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128)); + return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / + (AT91X40_MASTER_CLOCK / 128)) * 1000; } static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) @@ -64,6 +65,8 @@ void __init at91x40_timer_init(void) { unsigned int v; + arch_gettimeoffset = at91x40_gettimeoffset; + at91_tc_write(AT91_TC_BCR, 0); v = at91_tc_read(AT91_TC_BMR); v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE; @@ -79,9 +82,3 @@ void __init at91x40_timer_init(void) at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN)); } - -struct sys_timer at91x40_timer = { - .init = at91x40_timer_init, - .offset = at91x40_gettimeoffset, -}; - diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index b99b5752cc1..35ab632bbf6 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c @@ -90,7 +90,7 @@ static void __init onearm_board_init(void) MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = onearm_init_early, diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 854b9797428..f95e31cda4b 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -210,7 +210,7 @@ static void __init afeb9260_board_init(void) MACHINE_START(AFEB9260, "Custom afeb9260 board") /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = afeb9260_init_early, diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 28a18ce6d91..ade948b8266 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -187,7 +187,7 @@ static void __init cam60_board_init(void) MACHINE_START(CAM60, "KwikByte CAM60") /* Maintainer: KwikByte */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = cam60_init_early, diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index c17bb533a94..92983050a9b 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -157,7 +157,7 @@ static void __init carmeva_board_init(void) MACHINE_START(CARMEVA, "Carmeva") /* Maintainer: Conitec Datasystems */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = carmeva_init_early, diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 847432441ec..008527efdbc 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c @@ -374,7 +374,7 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260") MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") #endif /* Maintainer: Eric Benard - EUKREA Electromatique */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = cpu9krea_init_early, diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index 2a7af786874..42f1353a4ba 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c @@ -178,7 +178,7 @@ static void __init cpuat91_board_init(void) MACHINE_START(CPUAT91, "Eukrea") /* Maintainer: Eric Benard - EUKREA Electromatique */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = cpuat91_init_early, diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index 48a531e05be..e5fde215225 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -251,7 +251,7 @@ static void __init csb337_board_init(void) MACHINE_START(CSB337, "Cogent CSB337") /* Maintainer: Bill Gatliff */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = csb337_init_early, diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index ec0f3abd504..fdf11061c57 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c @@ -132,7 +132,7 @@ static void __init csb637_board_init(void) MACHINE_START(CSB637, "Cogent CSB637") /* Maintainer: Bill Gatliff */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = csb637_init_early, diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c index 881170ce61d..8db30132abe 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt.c @@ -49,7 +49,7 @@ static const char *at91_dt_board_compat[] __initdata = { DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = at91_dt_initialize, diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c index b489388a6f8..becf0a6a289 100644 --- a/arch/arm/mach-at91/board-eb01.c +++ b/arch/arm/mach-at91/board-eb01.c @@ -44,7 +44,7 @@ static void __init at91eb01_init_early(void) MACHINE_START(AT91EB01, "Atmel AT91 EB01") /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ - .timer = &at91x40_timer, + .init_time = at91x40_timer_init, .handle_irq = at91_aic_handle_irq, .init_early = at91eb01_init_early, .init_irq = at91eb01_init_irq, diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index 9f5e71c95f0..f9be8161bbf 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c @@ -116,7 +116,7 @@ static void __init eb9200_board_init(void) } MACHINE_START(ATEB9200, "Embest ATEB9200") - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = eb9200_init_early, diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index ef69e0ebe94..b2fcd71262b 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c @@ -181,7 +181,7 @@ static void __init ecb_at91board_init(void) MACHINE_START(ECBAT91, "emQbit's ECB_AT91") /* Maintainer: emQbit.com */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ecb_at91init_early, diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index 50f3d3795c0..77de410efc9 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c @@ -149,7 +149,7 @@ static void __init eco920_board_init(void) MACHINE_START(ECO920, "eco920") /* Maintainer: Sascha Hauer */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = eco920_init_early, diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 5d44eba0f20..737c0856362 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c @@ -159,7 +159,7 @@ static void __init flexibity_board_init(void) MACHINE_START(FLEXIBITY, "Flexibity Connect") /* Maintainer: Maxim Osipov */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = flexibity_init_early, diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index 191d37c16ba..2ea7059b840 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c @@ -261,7 +261,7 @@ static void __init foxg20_board_init(void) MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20") /* Maintainer: Sergio Tanzilli */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = foxg20_init_early, diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 23a2fa17ab2..c1d61d24779 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -574,7 +574,7 @@ static void __init gsia18s_board_init(void) } MACHINE_START(GSIA18S, "GS_IA18_S") - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = gsia18s_init_early, diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index 9a43d1e1a03..88e2f5d2d16 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c @@ -103,7 +103,7 @@ static void __init kafa_board_init(void) MACHINE_START(KAFA, "Sperry-Sun KAFA") /* Maintainer: Sergei Sharonov */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = kafa_init_early, diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index f168bec2369..0c519d9ebff 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -149,7 +149,7 @@ static void __init kb9202_board_init(void) MACHINE_START(KB9200, "KB920x") /* Maintainer: KwikByte, Inc. */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = kb9202_init_early, diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c deleted file mode 100644 index bc7a1c4a1f6..00000000000 --- a/arch/arm/mach-at91/board-neocore926.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-neocore926.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2007 Atmel Corporation - * Copyright (C) 2008 ADENEO. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/types.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/spi/ads7846.h> -#include <linux/fb.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> - -#include <video/atmel_lcdc.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/irq.h> -#include <asm/sizes.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/at91sam9_smc.h> - -#include "at91_aic.h" -#include "board.h" -#include "sam9_smc.h" -#include "generic.h" - - -static void __init neocore926_init_early(void) -{ - /* Initialize processor: 20 MHz crystal */ - at91_initialize(20000000); -} - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata neocore926_usbh_data = { - .ports = 2, - .vbus_pin = { AT91_PIN_PA24, AT91_PIN_PA21 }, - .overcurrent_pin= {-EINVAL, -EINVAL}, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata neocore926_udc_data = { - .vbus_pin = AT91_PIN_PA25, - .pullup_pin = -EINVAL, /* pull-up driven by UDC */ -}; - - -/* - * ADS7846 Touchscreen - */ -#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -static int ads7843_pendown_state(void) -{ - return !at91_get_gpio_value(AT91_PIN_PA15); /* Touchscreen PENIRQ */ -} - -static struct ads7846_platform_data ads_info = { - .model = 7843, - .x_min = 150, - .x_max = 3830, - .y_min = 190, - .y_max = 3830, - .vref_delay_usecs = 100, - .x_plate_ohms = 450, - .y_plate_ohms = 250, - .pressure_max = 15000, - .debounce_max = 1, - .debounce_rep = 0, - .debounce_tol = (~0), - .get_pendown_state = ads7843_pendown_state, -}; - -static void __init neocore926_add_device_ts(void) -{ - at91_set_B_periph(AT91_PIN_PA15, 1); /* External IRQ1, with pullup */ - at91_set_gpio_input(AT91_PIN_PC13, 1); /* Touchscreen BUSY signal */ -} -#else -static void __init neocore926_add_device_ts(void) {} -#endif - -/* - * SPI devices. - */ -static struct spi_board_info neocore926_spi_devices[] = { -#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) - { /* DataFlash card */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#endif -#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) - { - .modalias = "ads7846", - .chip_select = 1, - .max_speed_hz = 125000 * 16, - .bus_num = 0, - .platform_data = &ads_info, - .irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1, - }, -#endif -}; - - -/* - * MCI (SD/MMC) - */ -static struct mci_platform_data __initdata neocore926_mci0_data = { - .slot[0] = { - .bus_width = 4, - .detect_pin = AT91_PIN_PE18, - .wp_pin = AT91_PIN_PE19, - }, -}; - - -/* - * MACB Ethernet device - */ -static struct macb_platform_data __initdata neocore926_macb_data = { - .phy_irq_pin = AT91_PIN_PE31, - .is_rmii = 1, -}; - - -/* - * NAND flash - */ -static struct mtd_partition __initdata neocore926_nand_partition[] = { - { - .name = "Linux Kernel", /* "Partition 1", */ - .offset = 0, - .size = SZ_8M, - }, - { - .name = "Filesystem", /* "Partition 2", */ - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_32M, - }, - { - .name = "Free", /* "Partition 3", */ - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct atmel_nand_data __initdata neocore926_nand_data = { - .ale = 21, - .cle = 22, - .rdy_pin = AT91_PIN_PB19, - .rdy_pin_active_low = 1, - .enable_pin = AT91_PIN_PD15, - .ecc_mode = NAND_ECC_SOFT, - .parts = neocore926_nand_partition, - .num_parts = ARRAY_SIZE(neocore926_nand_partition), - .det_pin = -EINVAL, -}; - -static struct sam9_smc_config __initdata neocore926_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, - - .ncs_read_pulse = 4, - .nrd_pulse = 4, - .ncs_write_pulse = 4, - .nwe_pulse = 4, - - .read_cycle = 6, - .write_cycle = 6, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, - .tdf_cycles = 2, -}; - -static void __init neocore926_add_device_nand(void) -{ - /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &neocore926_nand_smc_config); - - at91_add_device_nand(&neocore926_nand_data); -} - - -/* - * LCD Controller - */ -#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) -static struct fb_videomode at91_tft_vga_modes[] = { - { - .name = "TX09D50VM1CCA @ 60", - .refresh = 60, - .xres = 240, .yres = 320, - .pixclock = KHZ2PICOS(5000), - - .left_margin = 1, .right_margin = 33, - .upper_margin = 1, .lower_margin = 0, - .hsync_len = 5, .vsync_len = 1, - - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - }, -}; - -static struct fb_monspecs at91fb_default_monspecs = { - .manufacturer = "HIT", - .monitor = "TX09D70VM1CCA", - - .modedb = at91_tft_vga_modes, - .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), - .hfmin = 15000, - .hfmax = 64000, - .vfmin = 50, - .vfmax = 150, -}; - -#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ - | ATMEL_LCDC_DISTYPE_TFT \ - | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) - -static void at91_lcdc_power_control(int on) -{ - at91_set_gpio_value(AT91_PIN_PA30, on); -} - -/* Driver datas */ -static struct atmel_lcdfb_info __initdata neocore926_lcdc_data = { - .lcdcon_is_backlight = true, - .default_bpp = 16, - .default_dmacon = ATMEL_LCDC_DMAEN, - .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, - .default_monspecs = &at91fb_default_monspecs, - .atmel_lcdfb_power_control = at91_lcdc_power_control, - .guard_time = 1, - .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB555, -}; - -#else -static struct atmel_lcdfb_info __initdata neocore926_lcdc_data; -#endif - - -/* - * GPIO Buttons - */ -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -static struct gpio_keys_button neocore926_buttons[] = { - { /* BP1, "leftclic" */ - .code = BTN_LEFT, - .gpio = AT91_PIN_PC5, - .active_low = 1, - .desc = "left_click", - .wakeup = 1, - }, - { /* BP2, "rightclic" */ - .code = BTN_RIGHT, - .gpio = AT91_PIN_PC4, - .active_low = 1, - .desc = "right_click", - .wakeup = 1, - }, -}; - -static struct gpio_keys_platform_data neocore926_button_data = { - .buttons = neocore926_buttons, - .nbuttons = ARRAY_SIZE(neocore926_buttons), -}; - -static struct platform_device neocore926_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &neocore926_button_data, - } -}; - -static void __init neocore926_add_device_buttons(void) -{ - at91_set_GPIO_periph(AT91_PIN_PC5, 0); /* left button */ - at91_set_deglitch(AT91_PIN_PC5, 1); - at91_set_GPIO_periph(AT91_PIN_PC4, 0); /* right button */ - at91_set_deglitch(AT91_PIN_PC4, 1); - - platform_device_register(&neocore926_button_device); -} -#else -static void __init neocore926_add_device_buttons(void) {} -#endif - - -/* - * AC97 - */ -static struct ac97c_platform_data neocore926_ac97_data = { - .reset_pin = AT91_PIN_PA13, -}; - - -static void __init neocore926_board_init(void) -{ - /* Serial */ - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_add_device_serial(); - - /* USB Host */ - at91_add_device_usbh(&neocore926_usbh_data); - - /* USB Device */ - at91_add_device_udc(&neocore926_udc_data); - - /* SPI */ - at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ - at91_add_device_spi(neocore926_spi_devices, ARRAY_SIZE(neocore926_spi_devices)); - - /* Touchscreen */ - neocore926_add_device_ts(); - - /* MMC */ - at91_add_device_mci(0, &neocore926_mci0_data); - - /* Ethernet */ - at91_add_device_eth(&neocore926_macb_data); - - /* NAND */ - neocore926_add_device_nand(); - - /* I2C */ - at91_add_device_i2c(NULL, 0); - - /* LCD Controller */ - at91_add_device_lcdc(&neocore926_lcdc_data); - - /* Push Buttons */ - neocore926_add_device_buttons(); - - /* AC97 */ - at91_add_device_ac97(&neocore926_ac97_data); -} - -MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") - /* Maintainer: ADENEO */ - .timer = &at91sam926x_timer, - .map_io = at91_map_io, - .handle_irq = at91_aic_handle_irq, - .init_early = neocore926_init_early, - .init_irq = at91_init_irq_default, - .init_machine = neocore926_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 0299554495d..65c0d6b5ecb 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -217,7 +217,7 @@ static void __init pcontrol_g20_board_init(void) MACHINE_START(PCONTROL_G20, "PControl G20") /* Maintainer: pgsellmann@portner-elektronik.at */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = pcontrol_g20_init_early, diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index 4938f1cd5e1..ab2b2ec36c1 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c @@ -119,7 +119,7 @@ static void __init picotux200_board_init(void) MACHINE_START(PICOTUX2XX, "picotux 200") /* Maintainer: Kleinhenz Elektronik GmbH */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = picotux200_init_early, diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index 33b1628467e..aa3bc9b0f15 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c @@ -257,7 +257,7 @@ static void __init ek_board_init(void) MACHINE_START(QIL_A9260, "CALAO QIL_A9260") /* Maintainer: calao-systems */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-rm9200-dt.c index 5f9ce3da3fd..3fcb6623a33 100644 --- a/arch/arm/mach-at91/board-rm9200-dt.c +++ b/arch/arm/mach-at91/board-rm9200-dt.c @@ -47,7 +47,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = { }; DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = at91rm9200_dt_initialize, diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index 9e5061bef0d..690541b18cb 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c @@ -219,7 +219,7 @@ static void __init dk_board_init(void) MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") /* Maintainer: SAN People/Atmel */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = dk_init_early, diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 58277dbc718..8b17dadc1ab 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -186,7 +186,7 @@ static void __init ek_board_init(void) MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") /* Maintainer: SAN People/Atmel */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index 2e8b8339a20..f6d7f1958c7 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c @@ -222,7 +222,7 @@ static void __init rsi_ews_board_init(void) MACHINE_START(RSI_EWS, "RSI EWS") /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = rsi_ews_init_early, diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index b75fbf6003a..43ee4dc43b5 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -218,7 +218,7 @@ static void __init ek_board_init(void) MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") /* Maintainer: Olimex */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index f0135cd1d85..0b153c87521 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -343,7 +343,7 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 13ebaa8e410..b446645c772 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -612,7 +612,7 @@ MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") #endif /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 89b9608742a..3284df05df1 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -443,7 +443,7 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 1b7dd9f688d..f9cd1f2c714 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -409,7 +409,7 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, @@ -419,7 +419,7 @@ MACHINE_END MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index e4cc375e3a3..2a94896a137 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -502,7 +502,7 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index 377a1097afa..aa265dcf212 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -320,7 +320,7 @@ static void __init ek_board_init(void) MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") /* Maintainer: Atmel */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 98771500ddb..3aaa9784cf0 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -177,7 +177,7 @@ static void __init snapper9260_board_init(void) } MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = snapper9260_init_early, diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index 48a962b61fa..a033b8df9fb 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -272,7 +272,7 @@ static void __init stamp9g20evb_board_init(void) MACHINE_START(PORTUXG20, "taskit PortuxG20") /* Maintainer: taskit GmbH */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = stamp9g20_init_early, @@ -282,7 +282,7 @@ MACHINE_END MACHINE_START(STAMP9G20, "taskit Stamp9G20") /* Maintainer: taskit GmbH */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = stamp9g20_init_early, diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index c1060f96e58..2487d944a1b 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c @@ -355,7 +355,7 @@ static void __init ek_board_init(void) MACHINE_START(USB_A9263, "CALAO USB_A9263") /* Maintainer: calao-systems */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, @@ -365,7 +365,7 @@ MACHINE_END MACHINE_START(USB_A9260, "CALAO USB_A9260") /* Maintainer: calao-systems */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, @@ -375,7 +375,7 @@ MACHINE_END MACHINE_START(USB_A9G20, "CALAO USB_A92G0") /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ - .timer = &at91sam926x_timer, + .init_time = at91sam926x_pit_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = ek_init_early, diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index 8673aebcb85..be083771df2 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -587,7 +587,7 @@ static void __init yl9200_board_init(void) MACHINE_START(YL9200, "uCdragon YL-9200") /* Maintainer: S.Birtles */ - .timer = &at91rm9200_timer, + .init_time = at91rm9200_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic_handle_irq, .init_early = yl9200_init_early, diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index fc593d615e7..78ab0654865 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -36,12 +36,11 @@ extern int __init at91_aic5_of_init(struct device_node *node, /* Timer */ -struct sys_timer; extern void at91rm9200_ioremap_st(u32 addr); -extern struct sys_timer at91rm9200_timer; +extern void at91rm9200_timer_init(void); extern void at91sam926x_ioremap_pit(u32 addr); -extern struct sys_timer at91sam926x_timer; -extern struct sys_timer at91x40_timer; +extern void at91sam926x_pit_init(void); +extern void at91x40_timer_init(void); /* Clocks */ #ifdef CONFIG_AT91_PMC_UNIT diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index 97ad68a826f..5659f7c7212 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h @@ -196,6 +196,4 @@ static inline void flush(void) barrier(); } -#define arch_decomp_wdog() - #endif diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 48705c10a0f..bf02471d7e7 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -7,7 +7,6 @@ config ARCH_BCM select ARM_GIC select CPU_V7 select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select GENERIC_TIME select GPIO_BCM select SPARSE_IRQ diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c index 3a62f1b1cab..f0f9abafad2 100644 --- a/arch/arm/mach-bcm/board_bcm.c +++ b/arch/arm/mach-bcm/board_bcm.c @@ -11,34 +11,19 @@ * GNU General Public License for more details. */ -#include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/init.h> #include <linux/device.h> #include <linux/platform_device.h> +#include <linux/irqchip.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> - #include <asm/mach/time.h> -static const struct of_device_id irq_match[] = { - {.compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {} -}; - static void timer_init(void) { } -static struct sys_timer timer = { - .init = timer_init, -}; - -static void __init init_irq(void) -{ - of_irq_init(irq_match); -} static void __init board_init(void) { @@ -49,9 +34,8 @@ static void __init board_init(void) static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, }; DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") - .init_irq = init_irq, - .timer = &timer, + .init_irq = irqchip_init, + .init_time = timer_init, .init_machine = board_init, .dt_compat = bcm11351_dt_compat, - .handle_irq = gic_handle_irq, MACHINE_END diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c index f0d739f4b7a..d615a61e902 100644 --- a/arch/arm/mach-bcm2835/bcm2835.c +++ b/arch/arm/mach-bcm2835/bcm2835.c @@ -17,8 +17,8 @@ #include <linux/irqchip/bcm2835.h> #include <linux/of_address.h> #include <linux/of_platform.h> -#include <linux/bcm2835_timer.h> #include <linux/clk/bcm2835.h> +#include <linux/clocksource.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -104,7 +104,7 @@ DT_MACHINE_START(BCM2835, "BCM2835") .init_irq = bcm2835_init_irq, .handle_irq = bcm2835_handle_irq, .init_machine = bcm2835_init, - .timer = &bcm2835_timer, + .init_time = clocksource_of_init, .restart = bcm2835_restart, .dt_compat = bcm2835_compat MACHINE_END diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h index cc46dcc7237..bf86dca3bf7 100644 --- a/arch/arm/mach-bcm2835/include/mach/uncompress.h +++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h @@ -42,4 +42,3 @@ static inline void flush(void) } #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index 3fbf43f7258..f38584709df 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -170,7 +170,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12") .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, + .init_time = clps711x_timer_init, .init_machine = autcpu12_init, .init_late = autcpu12_init_late, .handle_irq = clps711x_handle_irq, diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c index 60900ddf97c..baab7da33c9 100644 --- a/arch/arm/mach-clps711x/board-cdb89712.c +++ b/arch/arm/mach-clps711x/board-cdb89712.c @@ -140,7 +140,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712") .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, + .init_time = clps711x_timer_init, .init_machine = cdb89712_init, .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c index 0b32a487183..014aa3c19a0 100644 --- a/arch/arm/mach-clps711x/board-clep7312.c +++ b/arch/arm/mach-clps711x/board-clep7312.c @@ -40,7 +40,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") .fixup = fixup_clep7312, .map_io = clps711x_map_io, .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, + .init_time = clps711x_timer_init, .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c index 71aa5cf2c0d..5f928e9ed2e 100644 --- a/arch/arm/mach-clps711x/board-edb7211.c +++ b/arch/arm/mach-clps711x/board-edb7211.c @@ -173,7 +173,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .reserve = edb7211_reserve, .map_io = edb7211_map_io, .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, + .init_time = clps711x_timer_init, .init_machine = edb7211_init, .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c index 7d012558036..c5675efc8c6 100644 --- a/arch/arm/mach-clps711x/board-fortunet.c +++ b/arch/arm/mach-clps711x/board-fortunet.c @@ -78,7 +78,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet") .fixup = fortunet_fixup, .map_io = clps711x_map_io, .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, + .init_time = clps711x_timer_init, .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c index 1518fc83bab..8d3ee677113 100644 --- a/arch/arm/mach-clps711x/board-p720t.c +++ b/arch/arm/mach-clps711x/board-p720t.c @@ -224,7 +224,7 @@ MACHINE_START(P720T, "ARM-Prospector720T") .map_io = p720t_map_io, .init_early = p720t_init_early, .init_irq = clps711x_init_irq, - .timer = &clps711x_timer, + .init_time = clps711x_timer_init, .init_machine = p720t_init, .init_late = p720t_init_late, .handle_irq = clps711x_handle_irq, diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index e046439573e..20ff50f3ccf 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -282,7 +282,7 @@ static void add_fixed_clk(struct clk *clk, const char *name, int rate) clk_register_clkdev(clk, name, NULL); } -static void __init clps711x_timer_init(void) +void __init clps711x_timer_init(void) { int osc, ext, pll, cpu, bus, timl, timh, uart, spi; u32 tmp; @@ -345,10 +345,6 @@ static void __init clps711x_timer_init(void) setup_irq(IRQ_TC2OI, &clps711x_timer_irq); } -struct sys_timer clps711x_timer = { - .init = clps711x_timer_init, -}; - void clps711x_restart(char mode, const char *cmd) { soft_restart(0); diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h index b7c0c75c90c..f84a7292c70 100644 --- a/arch/arm/mach-clps711x/common.h +++ b/arch/arm/mach-clps711x/common.h @@ -8,10 +8,8 @@ #define CLPS711X_NR_GPIO (4 * 8 + 3) #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit)) -struct sys_timer; - extern void clps711x_map_io(void); extern void clps711x_init_irq(void); +extern void clps711x_timer_init(void); extern void clps711x_handle_irq(struct pt_regs *regs); extern void clps711x_restart(char mode, const char *cmd); -extern struct sys_timer clps711x_timer; diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h index 7b28d6a4769..5f02d06dc65 100644 --- a/arch/arm/mach-clps711x/include/mach/uncompress.h +++ b/arch/arm/mach-clps711x/include/mach/uncompress.h @@ -53,5 +53,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index ae305397003..a71867e1d8d 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -28,7 +28,6 @@ #include <linux/usb/ohci_pdriver.h> #include <asm/setup.h> #include <asm/mach-types.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -250,8 +249,7 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, - .timer = &cns3xxx_timer, - .handle_irq = gic_handle_irq, + .init_time = cns3xxx_timer_init, .init_machine = cns3420_init, .restart = cns3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 031805b1428..e698f26cc0c 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -12,10 +12,10 @@ #include <linux/interrupt.h> #include <linux/clockchips.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <mach/cns3xxx.h> #include "core.h" @@ -134,7 +134,6 @@ static int cns3xxx_timer_set_next_event(unsigned long evt, static struct clock_event_device cns3xxx_tmr1_clockevent = { .name = "cns3xxx timer1", - .shift = 8, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = cns3xxx_timer_set_mode, .set_next_event = cns3xxx_timer_set_next_event, @@ -145,15 +144,9 @@ static struct clock_event_device cns3xxx_tmr1_clockevent = { static void __init cns3xxx_clockevents_init(unsigned int timer_irq) { cns3xxx_tmr1_clockevent.irq = timer_irq; - cns3xxx_tmr1_clockevent.mult = - div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC, - cns3xxx_tmr1_clockevent.shift); - cns3xxx_tmr1_clockevent.max_delta_ns = - clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent); - cns3xxx_tmr1_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent); - - clockevents_register_device(&cns3xxx_tmr1_clockevent); + clockevents_config_and_register(&cns3xxx_tmr1_clockevent, + (cns3xxx_cpu_clock() >> 3) * 1000000, + 0xf, 0xffffffff); } /* @@ -235,17 +228,13 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq) cns3xxx_clockevents_init(timer_irq); } -static void __init cns3xxx_timer_init(void) +void __init cns3xxx_timer_init(void) { cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); } -struct sys_timer cns3xxx_timer = { - .init = cns3xxx_timer_init, -}; - #ifdef CONFIG_CACHE_L2X0 void __init cns3xxx_l2x0_init(void) diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index 4894b8c1715..b23b17b4da1 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h @@ -11,7 +11,7 @@ #ifndef __CNS3XXX_CORE_H #define __CNS3XXX_CORE_H -extern struct sys_timer cns3xxx_timer; +extern void cns3xxx_timer_init(void); #ifdef CONFIG_CACHE_L2X0 void __init cns3xxx_l2x0_init(void); diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h index a91b6058ab4..7a030b99df8 100644 --- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h +++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h @@ -51,4 +51,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 95b5e102ceb..e3742716cba 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -679,7 +679,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .atag_offset = 0x100, .map_io = da830_evm_map_io, .init_irq = cp_intc_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = da830_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 0299915575a..3b3356097bb 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1599,7 +1599,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .atag_offset = 0x100, .map_io = da850_evm_map_io, .init_irq = cp_intc_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = da850_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index cdf8d0746e7..147b8e1a440 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -355,7 +355,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") .atag_offset = 0x100, .map_io = dm355_evm_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = dm355_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index d41954507fc..dff4ddc5ef8 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -274,7 +274,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") .atag_offset = 0x100, .map_io = dm355_leopard_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = dm355_leopard_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 5d49c75388c..c2d4958a0cb 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -616,7 +616,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") .atag_offset = 0x100, .map_io = dm365_evm_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = dm365_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index f5e018de7fa..e4a16f98e6a 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -825,7 +825,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") .atag_offset = 0x100, .map_io = davinci_evm_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = davinci_evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6e2f1631df5..de7adff324d 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -818,7 +818,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") .atag_offset = 0x100, .map_io = davinci_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, @@ -829,7 +829,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") .atag_offset = 0x100, .map_io = davinci_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = evm_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 43e4a0d663f..b0df578bf74 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -570,7 +570,7 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") .atag_offset = 0x100, .map_io = mityomapl138_map_io, .init_irq = cp_intc_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = mityomapl138_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 3e3e3afebf8..1c98107527f 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -237,7 +237,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2") .atag_offset = 0x100, .map_io = davinci_ntosd2_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = davinci_ntosd2_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index dc1208e9e66..deb3922612b 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -341,7 +341,7 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") .atag_offset = 0x100, .map_io = omapl138_hawk_map_io, .init_irq = cp_intc_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = omapl138_hawk_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 6957787fa7f..739be7e738f 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -155,7 +155,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR") .atag_offset = 0x100, .map_io = davinci_sffsdr_map_io, .init_irq = davinci_irq_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = davinci_sffsdr_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index be3099733b1..4f416023d4e 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -280,7 +280,7 @@ MACHINE_START(TNETV107X, "TNETV107X EVM") .atag_offset = 0x100, .map_io = tnetv107x_init, .init_irq = cp_intc_init, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = tnetv107x_evm_board_init, .init_late = davinci_init_late, .dma_zone_size = SZ_128M, diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index 9107691adbd..5ac9e9384b1 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -25,35 +25,44 @@ #define DAVINCI_CPUIDLE_MAX_STATES 2 -struct davinci_ops { - void (*enter) (u32 flags); - void (*exit) (u32 flags); - u32 flags; -}; +static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); +static void __iomem *ddr2_reg_base; +static bool ddr2_pdown; + +static void davinci_save_ddr_power(int enter, bool pdown) +{ + u32 val; + + val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); + + if (enter) { + if (pdown) + val |= DDR2_SRPD_BIT; + else + val &= ~DDR2_SRPD_BIT; + val |= DDR2_LPMODEN_BIT; + } else { + val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); + } + + __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); +} /* Actual code that puts the SoC in different idle states */ static int davinci_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; - struct davinci_ops *ops = cpuidle_get_statedata(state_usage); - - if (ops && ops->enter) - ops->enter(ops->flags); + davinci_save_ddr_power(1, ddr2_pdown); index = cpuidle_wrap_enter(dev, drv, index, arm_cpuidle_simple_enter); - if (ops && ops->exit) - ops->exit(ops->flags); + davinci_save_ddr_power(0, ddr2_pdown); return index; } -/* fields in davinci_ops.flags */ -#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0) - static struct cpuidle_driver davinci_idle_driver = { .name = "cpuidle-davinci", .owner = THIS_MODULE, @@ -70,45 +79,6 @@ static struct cpuidle_driver davinci_idle_driver = { .state_count = DAVINCI_CPUIDLE_MAX_STATES, }; -static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); -static void __iomem *ddr2_reg_base; - -static void davinci_save_ddr_power(int enter, bool pdown) -{ - u32 val; - - val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); - - if (enter) { - if (pdown) - val |= DDR2_SRPD_BIT; - else - val &= ~DDR2_SRPD_BIT; - val |= DDR2_LPMODEN_BIT; - } else { - val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT); - } - - __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET); -} - -static void davinci_c2state_enter(u32 flags) -{ - davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN)); -} - -static void davinci_c2state_exit(u32 flags) -{ - davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN)); -} - -static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = { - [1] = { - .enter = davinci_c2state_enter, - .exit = davinci_c2state_exit, - }, -}; - static int __init davinci_cpuidle_probe(struct platform_device *pdev) { int ret; @@ -124,11 +94,7 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev) ddr2_reg_base = pdata->ddr2_ctlr_base; - if (pdata->ddr2_pdown) - davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN; - cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]); - - device->state_count = DAVINCI_CPUIDLE_MAX_STATES; + ddr2_pdown = pdata->ddr2_pdown; ret = cpuidle_register_driver(&davinci_idle_driver); if (ret) { diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 37c27af18fa..9a7c76efc8f 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -56,7 +56,7 @@ static const char *da850_boards_compat[] __initdata = { DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x") .map_io = da850_init, .init_irq = da8xx_init_irq, - .timer = &davinci_timer, + .init_time = davinci_timer_init, .init_machine = da850_init_machine, .dt_compat = da850_boards_compat, .init_late = davinci_init_late, diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 046c7238a3d..b124b77c90c 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -15,9 +15,7 @@ #include <linux/compiler.h> #include <linux/types.h> -struct sys_timer; - -extern struct sys_timer davinci_timer; +extern void davinci_timer_init(void); extern void davinci_irq_init(void); extern void __iomem *davinci_intc_base; diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 3a0ff905a69..f49c2916aa3 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -101,4 +101,3 @@ static inline void __arch_decomp_setup(unsigned long arch_id) } #define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 9847938785c..bad361ec166 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -337,7 +337,7 @@ static struct clock_event_device clockevent_davinci = { }; -static void __init davinci_timer_init(void) +void __init davinci_timer_init(void) { struct clk *timer_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; @@ -410,11 +410,6 @@ static void __init davinci_timer_init(void) timer32_config(&timers[i]); } -struct sys_timer davinci_timer = { - .init = davinci_timer_init, -}; - - /* reset board using watchdog timer */ void davinci_watchdog_reset(struct platform_device *pdev) { diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c index 792b4e2e24f..0dc39cf30fd 100644 --- a/arch/arm/mach-dove/cm-a510.c +++ b/arch/arm/mach-dove/cm-a510.c @@ -92,6 +92,6 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board") .map_io = dove_map_io, .init_early = dove_init_early, .init_irq = dove_init_irq, - .timer = &dove_timer, + .init_time = dove_timer_init, .restart = dove_restart, MACHINE_END diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 89f4f993cd0..ea84c535a11 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -8,35 +8,24 @@ * warranty of any kind, whether express or implied. */ -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/pci.h> #include <linux/clk-provider.h> #include <linux/clk/mvebu.h> -#include <linux/ata_platform.h> -#include <linux/gpio.h> +#include <linux/dma-mapping.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/of_platform.h> -#include <asm/page.h> -#include <asm/setup.h> -#include <asm/timex.h> +#include <linux/platform_data/dma-mv_xor.h> +#include <linux/platform_data/usb-ehci-orion.h> +#include <linux/platform_device.h> #include <asm/hardware/cache-tauros2.h> +#include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/mach/pci.h> -#include <mach/dove.h> -#include <mach/pm.h> #include <mach/bridge-regs.h> -#include <asm/mach/arch.h> -#include <linux/irq.h> -#include <plat/time.h> -#include <linux/platform_data/usb-ehci-orion.h> -#include <linux/platform_data/dma-mv_xor.h> -#include <plat/irq.h> +#include <mach/pm.h> #include <plat/common.h> -#include <plat/addr-map.h> +#include <plat/irq.h> +#include <plat/time.h> #include "common.h" /***************************************************************************** @@ -242,17 +231,13 @@ static int __init dove_find_tclk(void) return 166666667; } -static void __init dove_timer_init(void) +void __init dove_timer_init(void) { dove_tclk = dove_find_tclk(); orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_DOVE_BRIDGE, dove_tclk); } -struct sys_timer dove_timer = { - .init = dove_timer_init, -}; - /***************************************************************************** * Cryptographic Engines and Security Accelerator (CESA) ****************************************************************************/ @@ -454,7 +439,7 @@ DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") .map_io = dove_map_io, .init_early = dove_init_early, .init_irq = orion_dt_init_irq, - .timer = &dove_timer, + .init_time = dove_timer_init, .init_machine = dove_dt_init, .restart = dove_restart, .dt_compat = dove_dt_board_compat, diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index 1a233404b73..ee59fba4c6d 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -14,7 +14,7 @@ struct mv643xx_eth_platform_data; struct mv_sata_platform_data; -extern struct sys_timer dove_timer; +extern void dove_timer_init(void); /* * Basic Dove init functions used early by machine-setup. diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c index bc2867f1134..76e26f949c2 100644 --- a/arch/arm/mach-dove/dove-db-setup.c +++ b/arch/arm/mach-dove/dove-db-setup.c @@ -98,6 +98,6 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") .map_io = dove_map_io, .init_early = dove_init_early, .init_irq = dove_init_irq, - .timer = &dove_timer, + .init_time = dove_timer_init, .restart = dove_restart, MACHINE_END diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h index 2c5cdd7a3ee..5c8ae9b9d39 100644 --- a/arch/arm/mach-dove/include/mach/uncompress.h +++ b/arch/arm/mach-dove/include/mach/uncompress.h @@ -34,4 +34,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index f0fe6b5350e..b13cc74114d 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c @@ -158,7 +158,7 @@ static void __init ebsa110_init_early(void) * interrupt, then the PIT counter will roll over (ie, be negative). * This actually works out to be convenient. */ -static unsigned long ebsa110_gettimeoffset(void) +static u32 ebsa110_gettimeoffset(void) { unsigned long offset, count; @@ -181,7 +181,7 @@ static unsigned long ebsa110_gettimeoffset(void) */ offset = offset * (1000000 / HZ) / COUNT; - return offset; + return offset * 1000; } static irqreturn_t @@ -213,8 +213,10 @@ static struct irqaction ebsa110_timer_irq = { /* * Set up timer interrupt. */ -static void __init ebsa110_timer_init(void) +void __init ebsa110_timer_init(void) { + arch_gettimeoffset = ebsa110_gettimeoffset; + /* * Timer 1, mode 2, LSB/MSB */ @@ -225,11 +227,6 @@ static void __init ebsa110_timer_init(void) setup_irq(IRQ_EBSA110_TIMER0, &ebsa110_timer_irq); } -static struct sys_timer ebsa110_timer = { - .init = ebsa110_timer_init, - .offset = ebsa110_gettimeoffset, -}; - static struct plat_serial8250_port serial_platform_data[] = { { .iobase = 0x3f8, @@ -328,6 +325,6 @@ MACHINE_START(EBSA110, "EBSA110") .map_io = ebsa110_map_io, .init_early = ebsa110_init_early, .init_irq = ebsa110_init_irq, - .timer = &ebsa110_timer, + .init_time = ebsa110_timer_init, .restart = ebsa110_restart, MACHINE_END diff --git a/arch/arm/mach-ebsa110/include/mach/uncompress.h b/arch/arm/mach-ebsa110/include/mach/uncompress.h index 32041509fbf..ab64bea69c7 100644 --- a/arch/arm/mach-ebsa110/include/mach/uncompress.h +++ b/arch/arm/mach-ebsa110/include/mach/uncompress.h @@ -42,4 +42,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 41383bf03d4..bda6c3a5c92 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -17,7 +17,6 @@ #include <mach/hardware.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -39,8 +38,7 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = adssphere_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index e85bf17f2d2..c49ed3dc1ae 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -34,6 +34,7 @@ #include <linux/i2c-gpio.h> #include <linux/spi/spi.h> #include <linux/export.h> +#include <linux/irqchip/arm-vic.h> #include <mach/hardware.h> #include <linux/platform_data/video-ep93xx.h> @@ -44,8 +45,6 @@ #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/hardware/vic.h> - #include "soc.h" /************************************************************************* @@ -140,11 +139,29 @@ static struct irqaction ep93xx_timer_irq = { .handler = ep93xx_timer_interrupt, }; -static void __init ep93xx_timer_init(void) +static u32 ep93xx_gettimeoffset(void) +{ + int offset; + + offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; + + /* + * Timer 4 is based on a 983.04 kHz reference clock, + * so dividing by 983040 gives the fraction of a second, + * so dividing by 0.983040 converts to uS. + * Refactor the calculation to avoid overflow. + * Finally, multiply by 1000 to give nS. + */ + return (offset + (53 * offset / 3072)) * 1000; +} + +void __init ep93xx_timer_init(void) { u32 tmode = EP93XX_TIMER123_CONTROL_MODE | EP93XX_TIMER123_CONTROL_CLKSEL; + arch_gettimeoffset = ep93xx_gettimeoffset; + /* Enable periodic HZ timer. */ __raw_writel(tmode, EP93XX_TIMER1_CONTROL); __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); @@ -158,21 +175,6 @@ static void __init ep93xx_timer_init(void) setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq); } -static unsigned long ep93xx_gettimeoffset(void) -{ - int offset; - - offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time; - - /* Calculate (1000000 / 983040) * offset. */ - return offset + (53 * offset / 3072); -} - -struct sys_timer ep93xx_timer = { - .init = ep93xx_timer_init, - .offset = ep93xx_gettimeoffset, -}; - /************************************************************************* * EP93xx IRQ handling diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index b8f53d57a29..27b14ae92c7 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -39,7 +39,6 @@ #include <linux/platform_data/spi-ep93xx.h> #include <mach/gpio-ep93xx.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -276,8 +275,7 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -290,8 +288,7 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -304,8 +301,7 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -318,8 +314,7 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -332,8 +327,7 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -346,8 +340,7 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -360,8 +353,7 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -374,8 +366,7 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = edb93xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index 7fd705b5efe..0cca5b18330 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -17,7 +17,6 @@ #include <mach/hardware.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -39,8 +38,7 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = gesbc9312_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 33a5122c6dc..a14e1b37bef 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -53,7 +53,7 @@ int ep93xx_ide_acquire_gpio(struct platform_device *pdev); void ep93xx_ide_release_gpio(struct platform_device *pdev); void ep93xx_init_devices(void); -extern struct sys_timer ep93xx_timer; +extern void ep93xx_timer_init(void); void ep93xx_restart(char, const char *); void ep93xx_init_late(void); diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h index d64274fc576..d2afb4dd82a 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -86,5 +86,3 @@ static void arch_decomp_setup(void) { ethernet_reset(); } - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index 3d7cdab725b..373583c2982 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -18,7 +18,6 @@ #include <mach/hardware.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -82,8 +81,7 @@ MACHINE_START(MICRO9, "Contec Micro9-High") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -96,8 +94,7 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -110,8 +107,7 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, @@ -124,8 +120,7 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = micro9_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 0eb3f17a6fa..36f22c1a31f 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -25,7 +25,6 @@ #include <linux/platform_data/video-ep93xx.h> #include <mach/gpio-ep93xx.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -83,8 +82,7 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = simone_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c index 50043eef1cf..aa86f86638d 100644 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ b/arch/arm/mach-ep93xx/snappercl15.c @@ -31,7 +31,6 @@ #include <linux/platform_data/video-ep93xx.h> #include <mach/gpio-ep93xx.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -176,8 +175,7 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") .atag_offset = 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = snappercl15_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 3c4c233391d..61f4b5dc4d7 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -22,7 +22,6 @@ #include <mach/hardware.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/map.h> #include <asm/mach/arch.h> @@ -246,8 +245,7 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") .atag_offset = 0x100, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = ts72xx_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c index ba92e25e301..605956fd07a 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -34,7 +34,6 @@ #include <linux/platform_data/spi-ep93xx.h> #include <mach/gpio-ep93xx.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/map.h> #include <asm/mach/arch.h> @@ -364,8 +363,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") .atag_offset = 0x100, .map_io = vision_map_io, .init_irq = ep93xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &ep93xx_timer, + .init_time = ep93xx_timer_init, .init_machine = vision_init_machine, .init_late = ep93xx_init_late, .restart = ep93xx_restart, diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index e103c290bc9..85afb031b67 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -414,7 +414,7 @@ config MACH_EXYNOS4_DT select CPU_EXYNOS4210 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select PINCTRL - select PINCTRL_EXYNOS4 + select PINCTRL_EXYNOS select USE_OF help Machine support for Samsung Exynos4 machine with device tree enabled. diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 1a89824a5f7..d63d399c7ba 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -12,6 +12,7 @@ #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/io.h> #include <linux/device.h> #include <linux/gpio.h> @@ -22,12 +23,13 @@ #include <linux/of_irq.h> #include <linux/export.h> #include <linux/irqdomain.h> +#include <linux/irqchip.h> #include <linux/of_address.h> +#include <linux/irqchip/arm-gic.h> #include <asm/proc-fns.h> #include <asm/exception.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> #include <asm/cacheflush.h> @@ -35,7 +37,6 @@ #include <mach/regs-irq.h> #include <mach/regs-pmu.h> #include <mach/regs-gpio.h> -#include <mach/pmu.h> #include <plat/cpu.h> #include <plat/clock.h> @@ -299,6 +300,7 @@ void exynos4_restart(char mode, const char *cmd) void exynos5_restart(char mode, const char *cmd) { + struct device_node *np; u32 val; void __iomem *addr; @@ -306,8 +308,9 @@ void exynos5_restart(char mode, const char *cmd) val = 0x1; addr = EXYNOS_SWRESET; } else if (of_machine_is_compatible("samsung,exynos5440")) { - val = (0x10 << 20) | (0x1 << 16); - addr = EXYNOS5440_SWRESET; + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); + addr = of_iomap(np, 0) + 0xcc; + val = (0xfff << 20) | (0x1 << 16); } else { pr_err("%s: cannot support non-DT\n", __func__); return; @@ -438,220 +441,6 @@ static void __init exynos5_init_clocks(int xtal) #endif } -#define COMBINER_ENABLE_SET 0x0 -#define COMBINER_ENABLE_CLEAR 0x4 -#define COMBINER_INT_STATUS 0xC - -static DEFINE_SPINLOCK(irq_controller_lock); - -struct combiner_chip_data { - unsigned int irq_offset; - unsigned int irq_mask; - void __iomem *base; -}; - -static struct irq_domain *combiner_irq_domain; -static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; - -static inline void __iomem *combiner_base(struct irq_data *data) -{ - struct combiner_chip_data *combiner_data = - irq_data_get_irq_chip_data(data); - - return combiner_data->base; -} - -static void combiner_mask_irq(struct irq_data *data) -{ - u32 mask = 1 << (data->hwirq % 32); - - __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); -} - -static void combiner_unmask_irq(struct irq_data *data) -{ - u32 mask = 1 << (data->hwirq % 32); - - __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); -} - -static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) -{ - struct combiner_chip_data *chip_data = irq_get_handler_data(irq); - struct irq_chip *chip = irq_get_chip(irq); - unsigned int cascade_irq, combiner_irq; - unsigned long status; - - chained_irq_enter(chip, desc); - - spin_lock(&irq_controller_lock); - status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); - spin_unlock(&irq_controller_lock); - status &= chip_data->irq_mask; - - if (status == 0) - goto out; - - combiner_irq = __ffs(status); - - cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); - if (unlikely(cascade_irq >= NR_IRQS)) - do_bad_IRQ(cascade_irq, desc); - else - generic_handle_irq(cascade_irq); - - out: - chained_irq_exit(chip, desc); -} - -static struct irq_chip combiner_chip = { - .name = "COMBINER", - .irq_mask = combiner_mask_irq, - .irq_unmask = combiner_unmask_irq, -}; - -static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) -{ - unsigned int max_nr; - - if (soc_is_exynos5250()) - max_nr = EXYNOS5_MAX_COMBINER_NR; - else - max_nr = EXYNOS4_MAX_COMBINER_NR; - - if (combiner_nr >= max_nr) - BUG(); - if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) - BUG(); - irq_set_chained_handler(irq, combiner_handle_cascade_irq); -} - -static void __init combiner_init_one(unsigned int combiner_nr, - void __iomem *base) -{ - combiner_data[combiner_nr].base = base; - combiner_data[combiner_nr].irq_offset = irq_find_mapping( - combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); - combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); - - /* Disable all interrupts */ - __raw_writel(combiner_data[combiner_nr].irq_mask, - base + COMBINER_ENABLE_CLEAR); -} - -#ifdef CONFIG_OF -static int combiner_irq_domain_xlate(struct irq_domain *d, - struct device_node *controller, - const u32 *intspec, unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - if (d->of_node != controller) - return -EINVAL; - - if (intsize < 2) - return -EINVAL; - - *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1]; - *out_type = 0; - - return 0; -} -#else -static int combiner_irq_domain_xlate(struct irq_domain *d, - struct device_node *controller, - const u32 *intspec, unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - return -EINVAL; -} -#endif - -static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq); - irq_set_chip_data(irq, &combiner_data[hw >> 3]); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - - return 0; -} - -static struct irq_domain_ops combiner_irq_domain_ops = { - .xlate = combiner_irq_domain_xlate, - .map = combiner_irq_domain_map, -}; - -static void __init combiner_init(void __iomem *combiner_base, - struct device_node *np) -{ - int i, irq, irq_base; - unsigned int max_nr, nr_irq; - - if (np) { - if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { - pr_warning("%s: number of combiners not specified, " - "setting default as %d.\n", - __func__, EXYNOS4_MAX_COMBINER_NR); - max_nr = EXYNOS4_MAX_COMBINER_NR; - } - } else { - max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR : - EXYNOS4_MAX_COMBINER_NR; - } - nr_irq = max_nr * MAX_IRQ_IN_COMBINER; - - irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); - if (IS_ERR_VALUE(irq_base)) { - irq_base = COMBINER_IRQ(0, 0); - pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base); - } - - combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0, - &combiner_irq_domain_ops, &combiner_data); - if (WARN_ON(!combiner_irq_domain)) { - pr_warning("%s: irq domain init failed\n", __func__); - return; - } - - for (i = 0; i < max_nr; i++) { - combiner_init_one(i, combiner_base + (i >> 2) * 0x10); - irq = IRQ_SPI(i); -#ifdef CONFIG_OF - if (np) - irq = irq_of_parse_and_map(np, i); -#endif - combiner_cascade_irq(i, irq); - } -} - -#ifdef CONFIG_OF -static int __init combiner_of_init(struct device_node *np, - struct device_node *parent) -{ - void __iomem *combiner_base; - - combiner_base = of_iomap(np, 0); - if (!combiner_base) { - pr_err("%s: failed to map combiner registers\n", __func__); - return -ENXIO; - } - - combiner_init(combiner_base, np); - - return 0; -} - -static const struct of_device_id exynos_dt_irq_match[] = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, }, - { .compatible = "samsung,exynos4210-combiner", - .data = combiner_of_init, }, - {}, -}; -#endif - void __init exynos4_init_irq(void) { unsigned int gic_bank_offset; @@ -662,7 +451,7 @@ void __init exynos4_init_irq(void) gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); #ifdef CONFIG_OF else - of_irq_init(exynos_dt_irq_match); + irqchip_init(); #endif if (!of_have_populated_dt()) @@ -679,7 +468,7 @@ void __init exynos4_init_irq(void) void __init exynos5_init_irq(void) { #ifdef CONFIG_OF - of_irq_init(exynos_dt_irq_match); + irqchip_init(); #endif /* * The parameters of s5p_init_irq() are for VIC init. @@ -1031,8 +820,8 @@ static int __init exynos_init_irq_eint(void) * interrupt support code here can be completely removed. */ static const struct of_device_id exynos_pinctrl_ids[] = { - { .compatible = "samsung,pinctrl-exynos4210", }, - { .compatible = "samsung,pinctrl-exynos4x12", }, + { .compatible = "samsung,exynos4210-pinctrl", }, + { .compatible = "samsung,exynos4x12-pinctrl", }, }; struct device_node *pctrl_np, *wkup_np; const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 04744f9c120..9339bb8954b 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -12,7 +12,7 @@ #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H -extern struct sys_timer exynos4_timer; +extern void exynos4_timer_init(void); struct map_desc; void exynos_init_io(struct map_desc *mach_desc, int size); @@ -60,8 +60,31 @@ void exynos4212_register_clocks(void); #define exynos4212_register_clocks() #endif +struct device_node; +void combiner_init(void __iomem *combiner_base, struct device_node *np); + extern struct smp_operations exynos_smp_ops; extern void exynos_cpu_die(unsigned int cpu); +/* PMU(Power Management Unit) support */ + +#define PMU_TABLE_END NULL + +enum sys_powerdown { + SYS_AFTR, + SYS_LPA, + SYS_SLEEP, + NUM_SYS_POWERDOWN, +}; + +extern unsigned long l2x0_regs_phys; +struct exynos_pmu_conf { + void __iomem *reg; + unsigned int val[NUM_SYS_POWERDOWN]; +}; + +extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void s3c_cpu_resume(void); + #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 05092415277..fcfe0251aa3 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -23,10 +23,11 @@ #include <asm/cpuidle.h> #include <mach/regs-clock.h> #include <mach/regs-pmu.h> -#include <mach/pmu.h> #include <plat/cpu.h> +#include "common.h" + #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c index 9d1a60951d7..c662c89794b 100644 --- a/arch/arm/mach-exynos/dev-audio.c +++ b/arch/arm/mach-exynos/dev-audio.c @@ -21,7 +21,8 @@ #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> -#include <mach/regs-audss.h> + +#define EXYNOS4_AUDSS_INT_MEM (0x03000000) static int exynos4_cfg_i2s(struct platform_device *pdev) { diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h deleted file mode 100644 index 7517c3f417a..00000000000 --- a/arch/arm/mach-exynos/include/mach/cpufreq.h +++ /dev/null @@ -1,36 +0,0 @@ -/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - CPUFreq support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -enum cpufreq_level_index { - L0, L1, L2, L3, L4, - L5, L6, L7, L8, L9, - L10, L11, L12, L13, L14, - L15, L16, L17, L18, L19, - L20, -}; - -struct exynos_dvfs_info { - unsigned long mpll_freq_khz; - unsigned int pll_safe_idx; - unsigned int pm_lock_idx; - unsigned int max_support_idx; - unsigned int min_support_idx; - struct clk *cpu_clk; - unsigned int *volt_table; - struct cpufreq_frequency_table *freq_table; - void (*set_freq)(unsigned int, unsigned int); - bool (*need_apll_change)(unsigned int, unsigned int); -}; - -extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *); -extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *); -extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *); diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h deleted file mode 100644 index 7c27c2d4bf4..00000000000 --- a/arch/arm/mach-exynos/include/mach/pmu.h +++ /dev/null @@ -1,34 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/pmu.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS4210 - PMU(Power Management Unit) support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_PMU_H -#define __ASM_ARCH_PMU_H __FILE__ - -#define PMU_TABLE_END NULL - -enum sys_powerdown { - SYS_AFTR, - SYS_LPA, - SYS_SLEEP, - NUM_SYS_POWERDOWN, -}; - -extern unsigned long l2x0_regs_phys; -struct exynos_pmu_conf { - void __iomem *reg; - unsigned int val[NUM_SYS_POWERDOWN]; -}; - -extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); -extern void s3c_cpu_resume(void); - -#endif /* __ASM_ARCH_PMU_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-audss.h b/arch/arm/mach-exynos/include/mach/regs-audss.h deleted file mode 100644 index ca5a8b64218..00000000000 --- a/arch/arm/mach-exynos/include/mach/regs-audss.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-exynos4/include/mach/regs-audss.h - * - * Copyright (c) 2011 Samsung Electronics - * http://www.samsung.com - * - * Exynos4 Audio SubSystem clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_AUDSS_H -#define __PLAT_REGS_AUDSS_H __FILE__ - -#define EXYNOS4_AUDSS_INT_MEM (0x03000000) - -#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h index 9c7b4bfd546..f2b50506b9f 100644 --- a/arch/arm/mach-exynos/include/mach/regs-irq.h +++ b/arch/arm/mach-exynos/include/mach/regs-irq.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_REGS_IRQ_H #define __ASM_ARCH_REGS_IRQ_H __FILE__ -#include <asm/hardware/gic.h> +#include <linux/irqchip/arm-gic.h> #include <mach/map.h> #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c index b938f9fc1dd..685f29173af 100644 --- a/arch/arm/mach-exynos/mach-armlex4210.c +++ b/arch/arm/mach-exynos/mach-armlex4210.c @@ -16,7 +16,6 @@ #include <linux/smsc911x.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <plat/cpu.h> @@ -201,9 +200,8 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = armlex4210_map_io, - .handle_irq = gic_handle_irq, .init_machine = armlex4210_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index 92757ff817a..112d10e53d2 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -15,7 +15,6 @@ #include <linux/serial_core.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <mach/map.h> #include <plat/cpu.h> @@ -107,10 +106,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = exynos4_dt_map_io, - .handle_irq = gic_handle_irq, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index e99d3d8f2bc..973a0663757 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -16,7 +16,6 @@ #include <linux/io.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <mach/map.h> #include <mach/regs-pmu.h> @@ -104,6 +103,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL), OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000, "exynos-tmu", NULL), + OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000, + "samsung-i2s.0", NULL), + OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000, + "samsung-i2s.1", NULL), + OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000, + "samsung-i2s.2", NULL), {}, }; @@ -179,10 +184,9 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .init_irq = exynos5_init_irq, .smp = smp_ops(exynos_smp_ops), .map_io = exynos5_dt_map_io, - .handle_irq = gic_handle_irq, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 27d4ed8b116..b8b3fbf0bae 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -39,7 +39,6 @@ #include <media/v4l2-mediabus.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <plat/adc.h> @@ -1379,10 +1378,9 @@ MACHINE_START(NURI, "NURI") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = nuri_map_io, - .handle_irq = gic_handle_irq, .init_machine = nuri_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .reserve = &nuri_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index 5e34b9c1619..579d2d171da 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -29,7 +29,6 @@ #include <linux/platform_data/usb-exynos.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <video/platform_lcd.h> @@ -814,10 +813,9 @@ MACHINE_START(ORIGEN, "ORIGEN") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = origen_map_io, - .handle_irq = gic_handle_irq, .init_machine = origen_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .reserve = &origen_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index ae6da40c2aa..fe6149624b8 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -25,7 +25,6 @@ #include <linux/platform_data/s3c-hsotg.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <video/samsung_fimd.h> @@ -376,9 +375,8 @@ MACHINE_START(SMDK4212, "SMDK4212") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, - .handle_irq = gic_handle_irq, .init_machine = smdk4x12_machine_init, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END @@ -390,10 +388,9 @@ MACHINE_START(SMDK4412, "SMDK4412") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, - .handle_irq = gic_handle_irq, .init_machine = smdk4x12_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 35548e3c097..d71672922b1 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c @@ -26,7 +26,6 @@ #include <linux/platform_data/usb-exynos.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <video/platform_lcd.h> @@ -423,9 +422,8 @@ MACHINE_START(SMDKV310, "SMDKV310") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, - .handle_irq = gic_handle_irq, .init_machine = smdkv310_machine_init, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END @@ -436,10 +434,9 @@ MACHINE_START(SMDKC210, "SMDKC210") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, - .handle_irq = gic_handle_irq, .init_machine = smdkv310_machine_init, .init_late = exynos_init_late, - .timer = &exynos4_timer, + .init_time = exynos4_timer_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 9e3340f1895..c9d33a43103 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -29,7 +29,6 @@ #include <drm/exynos_drm.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <video/samsung_fimd.h> @@ -1151,10 +1150,9 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .smp = smp_ops(exynos_smp_ops), .init_irq = exynos4_init_irq, .map_io = universal_map_io, - .handle_irq = gic_handle_irq, .init_machine = universal_machine_init, .init_late = exynos_init_late, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index 57668eb68e7..c9d6650f9b5 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -22,7 +22,6 @@ #include <linux/of.h> #include <asm/arch_timer.h> -#include <asm/hardware/gic.h> #include <asm/localtimer.h> #include <plat/cpu.h> @@ -255,13 +254,9 @@ static struct irqaction mct_comp_event_irq = { static void exynos4_clockevent_init(void) { - clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5); - mct_comp_device.max_delta_ns = - clockevent_delta2ns(0xffffffff, &mct_comp_device); - mct_comp_device.min_delta_ns = - clockevent_delta2ns(0xf, &mct_comp_device); mct_comp_device.cpumask = cpumask_of(0); - clockevents_register_device(&mct_comp_device); + clockevents_config_and_register(&mct_comp_device, clk_rate, + 0xf, 0xffffffff); if (soc_is_exynos5250()) setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); @@ -404,14 +399,8 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) evt->set_mode = exynos4_tick_set_mode; evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; evt->rating = 450; - - clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5); - evt->max_delta_ns = - clockevent_delta2ns(0x7fffffff, evt); - evt->min_delta_ns = - clockevent_delta2ns(0xf, evt); - - clockevents_register_device(evt); + clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), + 0xf, 0x7fffffff); exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); @@ -478,7 +467,7 @@ static void __init exynos4_timer_resources(void) #endif /* CONFIG_LOCAL_TIMERS */ } -static void __init exynos_timer_init(void) +void __init exynos4_timer_init(void) { if (soc_is_exynos5440()) { arch_timer_of_register(); @@ -494,7 +483,3 @@ static void __init exynos_timer_init(void) exynos4_clocksource_init(); exynos4_clockevent_init(); } - -struct sys_timer exynos4_timer = { - .init = exynos_timer_init, -}; diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index c5c840e947b..60f7c5be057 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -20,9 +20,9 @@ #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> -#include <asm/hardware/gic.h> #include <asm/smp_plat.h> #include <asm/smp_scu.h> @@ -149,7 +149,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct __raw_writel(virt_to_phys(exynos4_secondary_startup), cpu_boot_reg(phys_cpu)); - gic_raise_softirq(cpumask_of(cpu), 0); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); if (pen_release == -1) break; @@ -190,8 +190,6 @@ static void __init exynos_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index b9b539cac81..e3faaa81201 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -34,7 +34,8 @@ #include <mach/regs-clock.h> #include <mach/regs-pmu.h> #include <mach/pm-core.h> -#include <mach/pmu.h> + +#include "common.h" static struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, @@ -91,8 +92,8 @@ static int exynos_cpu_suspend(unsigned long arg) /* issue the standby signal into the pm unit. */ cpu_do_idle(); - /* we should never get past here */ - panic("sleep resumed to originator?"); + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ } static void exynos_pm_prepare(void) @@ -282,6 +283,8 @@ static void exynos_pm_resume(void) if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + /* clear the wakeup state register */ + __raw_writel(0x0, S5P_WAKEUP_STAT); /* No need to perform below restore code */ goto early_wakeup; } diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 3a48c852be6..daebc1abc96 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -14,7 +14,8 @@ #include <linux/bug.h> #include <mach/regs-clock.h> -#include <mach/pmu.h> + +#include "common.h" static struct exynos_pmu_conf *exynos_pmu_config; diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c index 25b453601ac..6987a09ec21 100644 --- a/arch/arm/mach-footbridge/cats-hw.c +++ b/arch/arm/mach-footbridge/cats-hw.c @@ -90,6 +90,6 @@ MACHINE_START(CATS, "Chalice-CATS") .fixup = fixup_cats, .map_io = footbridge_map_io, .init_irq = footbridge_init_irq, - .timer = &isa_timer, + .init_time = isa_timer_init, .restart = footbridge_restart, MACHINE_END diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h index c9767b892cb..a846e50a07b 100644 --- a/arch/arm/mach-footbridge/common.h +++ b/arch/arm/mach-footbridge/common.h @@ -1,6 +1,6 @@ -extern struct sys_timer footbridge_timer; -extern struct sys_timer isa_timer; +extern void footbridge_timer_init(void); +extern void isa_timer_init(void); extern void isa_rtc_init(void); diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 3b54196447c..9ee78f7b499 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -93,7 +93,7 @@ static struct irqaction footbridge_timer_irq = { /* * Set up timer interrupt. */ -static void __init footbridge_timer_init(void) +void __init footbridge_timer_init(void) { struct clock_event_device *ce = &ckevt_dc21285; @@ -101,14 +101,6 @@ static void __init footbridge_timer_init(void) setup_irq(ce->irq, &footbridge_timer_irq); - clockevents_calc_mult_shift(ce, mem_fclk_21285, 5); - ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce); - ce->min_delta_ns = clockevent_delta2ns(0x000004, ce); ce->cpumask = cpumask_of(smp_processor_id()); - - clockevents_register_device(ce); + clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff); } - -struct sys_timer footbridge_timer = { - .init = footbridge_timer_init, -}; diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c index b09551ef89c..b08243500e2 100644 --- a/arch/arm/mach-footbridge/ebsa285.c +++ b/arch/arm/mach-footbridge/ebsa285.c @@ -101,7 +101,7 @@ MACHINE_START(EBSA285, "EBSA285") .video_end = 0x000bffff, .map_io = footbridge_map_io, .init_irq = footbridge_init_irq, - .timer = &footbridge_timer, + .init_time = footbridge_timer_init, .restart = footbridge_restart, MACHINE_END diff --git a/arch/arm/mach-footbridge/include/mach/uncompress.h b/arch/arm/mach-footbridge/include/mach/uncompress.h index 5dfa4428734..a69398c05a5 100644 --- a/arch/arm/mach-footbridge/include/mach/uncompress.h +++ b/arch/arm/mach-footbridge/include/mach/uncompress.h @@ -35,4 +35,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c index c40bb415f4b..d9301dd5635 100644 --- a/arch/arm/mach-footbridge/isa-timer.c +++ b/arch/arm/mach-footbridge/isa-timer.c @@ -31,14 +31,10 @@ static struct irqaction pit_timer_irq = { .dev_id = &i8253_clockevent, }; -static void __init isa_timer_init(void) +void __init isa_timer_init(void) { clocksource_i8253_init(); setup_irq(i8253_clockevent.irq, &pit_timer_irq); clockevent_i8253_init(false); } - -struct sys_timer isa_timer = { - .init = isa_timer_init, -}; diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c index d2d14339c6c..90ea23fdce4 100644 --- a/arch/arm/mach-footbridge/netwinder-hw.c +++ b/arch/arm/mach-footbridge/netwinder-hw.c @@ -766,6 +766,6 @@ MACHINE_START(NETWINDER, "Rebel-NetWinder") .fixup = fixup_netwinder, .map_io = footbridge_map_io, .init_irq = footbridge_init_irq, - .timer = &isa_timer, + .init_time = isa_timer_init, .restart = netwinder_restart, MACHINE_END diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c index e1e9990fa95..7bdeabdcd4d 100644 --- a/arch/arm/mach-footbridge/personal.c +++ b/arch/arm/mach-footbridge/personal.c @@ -18,7 +18,7 @@ MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer") .atag_offset = 0x100, .map_io = footbridge_map_io, .init_irq = footbridge_init_irq, - .timer = &footbridge_timer, + .init_time = footbridge_timer_init, .restart = footbridge_restart, MACHINE_END diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c index 5927d3c253a..08bd650c42f 100644 --- a/arch/arm/mach-gemini/board-nas4220b.c +++ b/arch/arm/mach-gemini/board-nas4220b.c @@ -31,10 +31,6 @@ #include "common.h" -static struct sys_timer ib4220b_timer = { - .init = gemini_timer_init, -}; - static struct gpio_led ib4220b_leds[] = { { .name = "nas4220b:orange:hdd", @@ -105,6 +101,6 @@ MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") .atag_offset = 0x100, .map_io = gemini_map_io, .init_irq = gemini_init_irq, - .timer = &ib4220b_timer, + .init_time = gemini_timer_init, .init_machine = ib4220b_init, MACHINE_END diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c index cd7437a1cea..fa0a36337f4 100644 --- a/arch/arm/mach-gemini/board-rut1xx.c +++ b/arch/arm/mach-gemini/board-rut1xx.c @@ -71,10 +71,6 @@ static struct platform_device rut1xx_leds = { }, }; -static struct sys_timer rut1xx_timer = { - .init = gemini_timer_init, -}; - static void __init rut1xx_init(void) { gemini_gpio_init(); @@ -89,6 +85,6 @@ MACHINE_START(RUT100, "Teltonika RUT100") .atag_offset = 0x100, .map_io = gemini_map_io, .init_irq = gemini_init_irq, - .timer = &rut1xx_timer, + .init_time = gemini_timer_init, .init_machine = rut1xx_init, MACHINE_END diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c index a367880368f..3321cd6cc1f 100644 --- a/arch/arm/mach-gemini/board-wbd111.c +++ b/arch/arm/mach-gemini/board-wbd111.c @@ -80,10 +80,6 @@ static struct platform_device wbd111_leds_device = { }, }; -static struct sys_timer wbd111_timer = { - .init = gemini_timer_init, -}; - static struct mtd_partition wbd111_partitions[] = { { .name = "RedBoot", @@ -132,6 +128,6 @@ MACHINE_START(WBD111, "Wiliboard WBD-111") .atag_offset = 0x100, .map_io = gemini_map_io, .init_irq = gemini_init_irq, - .timer = &wbd111_timer, + .init_time = gemini_timer_init, .init_machine = wbd111_init, MACHINE_END diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c index f382811c131..fe33c825fda 100644 --- a/arch/arm/mach-gemini/board-wbd222.c +++ b/arch/arm/mach-gemini/board-wbd222.c @@ -80,10 +80,6 @@ static struct platform_device wbd222_leds_device = { }, }; -static struct sys_timer wbd222_timer = { - .init = gemini_timer_init, -}; - static struct mtd_partition wbd222_partitions[] = { { .name = "RedBoot", @@ -132,6 +128,6 @@ MACHINE_START(WBD222, "Wiliboard WBD-222") .atag_offset = 0x100, .map_io = gemini_map_io, .init_irq = gemini_init_irq, - .timer = &wbd222_timer, + .init_time = gemini_timer_init, .init_machine = wbd222_init, MACHINE_END diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h index 0efa2624723..02e225673ac 100644 --- a/arch/arm/mach-gemini/include/mach/uncompress.h +++ b/arch/arm/mach-gemini/include/mach/uncompress.h @@ -39,6 +39,4 @@ static inline void flush(void) */ #define arch_decomp_setup() -#define arch_decomp_wdog() - #endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index aa1331e86bc..17ef91fa3d5 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c @@ -42,12 +42,12 @@ void __init arch_dma_init(dma_t *dma) } /* - * Return usecs since last timer reload + * Return nsecs since last timer reload * (timercount * (usecs perjiffie)) / (ticks per jiffie) */ -unsigned long h720x_gettimeoffset(void) +u32 h720x_gettimeoffset(void) { - return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH; + return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000; } /* diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h index 2489537d33d..7e738410ca9 100644 --- a/arch/arm/mach-h720x/common.h +++ b/arch/arm/mach-h720x/common.h @@ -13,18 +13,18 @@ * */ -extern unsigned long h720x_gettimeoffset(void); +extern u32 h720x_gettimeoffset(void); extern void __init h720x_init_irq(void); extern void __init h720x_map_io(void); extern void h720x_restart(char, const char *); #ifdef CONFIG_ARCH_H7202 -extern struct sys_timer h7202_timer; +extern void h7202_timer_init(void); extern void __init init_hw_h7202(void); extern void __init h7202_init_irq(void); extern void __init h7202_init_time(void); #endif #ifdef CONFIG_ARCH_H7201 -extern struct sys_timer h7201_timer; +extern void h7201_timer_init(void); #endif diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c index 24df2a349a9..13c74121538 100644 --- a/arch/arm/mach-h720x/cpu-h7201.c +++ b/arch/arm/mach-h720x/cpu-h7201.c @@ -44,8 +44,10 @@ static struct irqaction h7201_timer_irq = { /* * Setup TIMER0 as system timer */ -void __init h7201_init_time(void) +void __init h7201_timer_init(void) { + arch_gettimeoffset = h720x_gettimeoffset; + CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; @@ -53,8 +55,3 @@ void __init h7201_init_time(void) setup_irq(IRQ_TIMER0, &h7201_timer_irq); } - -struct sys_timer h7201_timer = { - .init = h7201_init_time, - .offset = h720x_gettimeoffset, -}; diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index c37d570b852..e2ae7e898f9 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c @@ -178,8 +178,10 @@ static struct irqaction h7202_timer_irq = { /* * Setup TIMER0 as system timer */ -void __init h7202_init_time(void) +void __init h7202_timer_init(void) { + arch_gettimeoffset = h720x_gettimeoffset; + CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; @@ -188,11 +190,6 @@ void __init h7202_init_time(void) setup_irq(IRQ_TIMER0, &h7202_timer_irq); } -struct sys_timer h7202_timer = { - .init = h7202_init_time, - .offset = h720x_gettimeoffset, -}; - void __init h7202_init_irq (void) { int irq; diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c index 5fdb20c855e..4fdeb686c0a 100644 --- a/arch/arm/mach-h720x/h7201-eval.c +++ b/arch/arm/mach-h720x/h7201-eval.c @@ -32,7 +32,7 @@ MACHINE_START(H7201, "Hynix GMS30C7201") .atag_offset = 0x1000, .map_io = h720x_map_io, .init_irq = h720x_init_irq, - .timer = &h7201_timer, + .init_time = h7201_timer_init, .dma_zone_size = SZ_256M, .restart = h720x_restart, MACHINE_END diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c index 169673036c5..f68e967a206 100644 --- a/arch/arm/mach-h720x/h7202-eval.c +++ b/arch/arm/mach-h720x/h7202-eval.c @@ -74,7 +74,7 @@ MACHINE_START(H7202, "Hynix HMS30C7202") .atag_offset = 0x100, .map_io = h720x_map_io, .init_irq = h7202_init_irq, - .timer = &h7202_timer, + .init_time = h7202_timer_init, .init_machine = init_eval_h7202, .dma_zone_size = SZ_256M, .restart = h720x_restart, diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h index d6623234f61..43e343c4b50 100644 --- a/arch/arm/mach-h720x/include/mach/uncompress.h +++ b/arch/arm/mach-h720x/include/mach/uncompress.h @@ -32,6 +32,5 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() #endif diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 551c97e87a7..44b12f9c158 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -1,5 +1,7 @@ config ARCH_HIGHBANK bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7 + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_GIC @@ -11,5 +13,7 @@ config ARCH_HIGHBANK select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select HAVE_SMP + select MAILBOX + select PL320_MBOX select SPARSE_IRQ select USE_OF diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h index 80235b46cb5..3f65206a9b9 100644 --- a/arch/arm/mach-highbank/core.h +++ b/arch/arm/mach-highbank/core.h @@ -2,7 +2,6 @@ #define __HIGHBANK_CORE_H extern void highbank_set_cpu_jump(int cpu, void *jump_addr); -extern void highbank_clocks_init(void); extern void highbank_restart(char, const char *); extern void __iomem *scu_base_addr; diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 981dc1e1da5..a4f9f50247d 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -18,6 +18,7 @@ #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/irqdomain.h> #include <linux/of.h> #include <linux/of_irq.h> @@ -25,14 +26,15 @@ #include <linux/of_address.h> #include <linux/smp.h> #include <linux/amba/bus.h> +#include <linux/clk-provider.h> #include <asm/arch_timer.h> #include <asm/cacheflush.h> +#include <asm/cputype.h> #include <asm/smp_plat.h> #include <asm/smp_twd.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/timer-sp.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -59,19 +61,13 @@ static void __init highbank_scu_map_io(void) void highbank_set_cpu_jump(int cpu, void *jump_addr) { - cpu = cpu_logical_map(cpu); + cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu)); __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), HB_JUMP_TABLE_PHYS(cpu) + 15); } -const static struct of_device_id irq_match[] = { - { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, }, - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {} -}; - #ifdef CONFIG_CACHE_L2X0 static void highbank_l2x0_disable(void) { @@ -82,7 +78,7 @@ static void highbank_l2x0_disable(void) static void __init highbank_init_irq(void) { - of_irq_init(irq_match); + irqchip_init(); if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) highbank_scu_map_io(); @@ -116,7 +112,7 @@ static void __init highbank_timer_init(void) WARN_ON(!timer_base); irq = irq_of_parse_and_map(np, 0); - highbank_clocks_init(); + of_clk_init(NULL); lookup.clk = of_clk_get(np, 0); clkdev_add(&lookup); @@ -129,10 +125,6 @@ static void __init highbank_timer_init(void) arch_timer_sched_clock_init(); } -static struct sys_timer highbank_timer = { - .init = highbank_timer_init, -}; - static void highbank_power_off(void) { highbank_set_pwr_shutdown(); @@ -209,8 +201,7 @@ DT_MACHINE_START(HIGHBANK, "Highbank") .smp = smp_ops(highbank_smp_ops), .map_io = debug_ll_io_init, .init_irq = highbank_init_irq, - .timer = &highbank_timer, - .handle_irq = gic_handle_irq, + .init_time = highbank_timer_init, .init_machine = highbank_init, .dt_compat = highbank_match, .restart = highbank_restart, diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c index 4ecc864ac8b..8797a700172 100644 --- a/arch/arm/mach-highbank/platsmp.c +++ b/arch/arm/mach-highbank/platsmp.c @@ -17,9 +17,9 @@ #include <linux/init.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <asm/smp_scu.h> -#include <asm/hardware/gic.h> #include "core.h" @@ -33,7 +33,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu) static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) { highbank_set_cpu_jump(cpu, secondary_startup); - gic_raise_softirq(cpumask_of(cpu), 0); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); return 0; } @@ -56,8 +56,6 @@ static void __init highbank_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h index 70af9d13fce..5995df7f262 100644 --- a/arch/arm/mach-highbank/sysregs.h +++ b/arch/arm/mach-highbank/sysregs.h @@ -37,7 +37,7 @@ extern void __iomem *sregs_base; static inline void highbank_set_core_pwr(void) { - int cpu = cpu_logical_map(smp_processor_id()); + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); if (scu_base_addr) scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); else @@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void) static inline void highbank_clear_core_pwr(void) { - int cpu = cpu_logical_map(smp_processor_id()); + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); if (scu_base_addr) scu_power_mode(scu_base_addr, SCU_PM_NORMAL); else diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0a2349dc701..4c9c6f9d2c5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -95,9 +95,6 @@ config MACH_MX27 config ARCH_MX5 bool -config ARCH_MX50 - bool - config ARCH_MX51 bool @@ -164,11 +161,6 @@ config SOC_IMX5 select CPU_V7 select MXC_TZIC -config SOC_IMX50 - bool - select ARCH_MX50 - select SOC_IMX5 - config SOC_IMX51 bool select ARCH_MX5 @@ -488,7 +480,7 @@ config MACH_MX31ADS_WM1133_EV1 bool "Support Wolfson Microelectronics 1133-EV1 module" depends on MACH_MX31ADS depends on MFD_WM8350_I2C - depends on REGULATOR_WM8350 + depends on REGULATOR_WM8350 = y select MFD_WM8350_CONFIG_MODE_0 select MFD_WM8352_CONFIG_MODE_0 help @@ -738,25 +730,10 @@ endif if ARCH_MULTI_V7 -comment "i.MX5 platforms:" - -config MACH_MX50_RDP - bool "Support MX50 reference design platform" - depends on BROKEN - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select SOC_IMX50 - help - Include support for MX50 reference design platform (RDP) board. This - includes specific configurations for the board and its peripherals. - comment "i.MX51 machines:" config MACH_IMX51_DT bool "Support i.MX51 platforms from device tree" - select MACH_MX51_BABBAGE select SOC_IMX51 help Include support for Freescale i.MX51 based platforms @@ -777,19 +754,6 @@ config MACH_MX51_BABBAGE u-boot. This includes specific configurations for the board and its peripherals. -config MACH_MX51_3DS - bool "Support MX51PDK (3DS)" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select SOC_IMX51 - help - Include support for MX51PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. - config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" select IMX_HAVE_PLATFORM_FSL_USB2_UDC diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0634b3152c2..240e0294c37 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -88,7 +88,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o -obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o @@ -103,10 +102,8 @@ endif # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o -obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o -obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index b27815de847..41ba1bb0437 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -22,10 +22,6 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000 params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 -zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000 -params_phys-$(CONFIG_SOC_IMX50) := 0x70000100 -initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000 - zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 2c570cdaae7..69858c78f40 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -224,6 +224,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) clk_prepare_enable(clk[emi_ahb]); + /* Clock source for gpt must be derived from AHB */ + clk_set_parent(clk[per5_sel], clk[ahb]); + clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 1ffe3b534e5..e30369a58e4 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -228,9 +228,12 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1"); clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2"); clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2"); - clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0"); - clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1"); - clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2"); + clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0"); + clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0"); + clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1"); + clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1"); + clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2"); + clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2"); clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0"); clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index c0c4e723b7f..19644f6524d 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -56,8 +56,6 @@ static void __iomem *ccm_base; -void __init imx6q_clock_map_io(void) { } - int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { u32 val = readl_relaxed(ccm_base + CLPCR); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index fa36fb84ab1..76c42004328 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -21,7 +21,6 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); -extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); extern void imx1_init_early(void); @@ -30,7 +29,6 @@ extern void imx25_init_early(void); extern void imx27_init_early(void); extern void imx31_init_early(void); extern void imx35_init_early(void); -extern void imx50_init_early(void); extern void imx51_init_early(void); extern void imx53_init_early(void); extern void mxc_init_irq(void __iomem *); @@ -41,7 +39,6 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); -extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); extern void imx1_soc_init(void); @@ -50,7 +47,6 @@ extern void imx25_soc_init(void); extern void imx27_soc_init(void); extern void imx31_soc_init(void); extern void imx35_soc_init(void); -extern void imx50_soc_init(void); extern void imx51_soc_init(void); extern void imx51_init_late(void); extern void imx53_init_late(void); @@ -109,18 +105,11 @@ void tzic_handle_irq(struct pt_regs *); #define imx27_handle_irq avic_handle_irq #define imx31_handle_irq avic_handle_irq #define imx35_handle_irq avic_handle_irq -#define imx50_handle_irq tzic_handle_irq #define imx51_handle_irq tzic_handle_irq #define imx53_handle_irq tzic_handle_irq -#define imx6q_handle_irq gic_handle_irq extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); -#ifdef CONFIG_DEBUG_LL -extern void imx_lluart_map_io(void); -#else -static inline void imx_lluart_map_io(void) {} -#endif extern void v7_cpu_resume(void); extern u32 *pl310_get_save_ptr(void); #ifdef CONFIG_SMP @@ -139,7 +128,6 @@ extern void imx_gpc_init(void); extern void imx_gpc_pre_suspend(void); extern void imx_gpc_post_resume(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_clock_map_io(void); extern void imx_cpu_die(unsigned int cpu); extern int imx_cpu_kill(unsigned int cpu); diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index d88760014ff..d7ce72252a4 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -22,7 +22,6 @@ static int mx5_cpu_rev = -1; #define IIM_SREV 0x24 -#define MX50_HW_ADADIG_DIGPROG 0xB0 static int get_mx51_srev(void) { @@ -108,41 +107,3 @@ int mx53_revision(void) return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); - -static int get_mx50_srev(void) -{ - void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K); - u32 rev; - - if (!anatop) { - mx5_cpu_rev = -EINVAL; - return 0; - } - - rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); - rev &= 0xff; - - iounmap(anatop); - if (rev == 0x0) - return IMX_CHIP_REVISION_1_0; - else if (rev == 0x1) - return IMX_CHIP_REVISION_1_1; - return 0; -} - -/* - * Returns: - * the silicon revision of the cpu - * -EINVAL - not a mx50 - */ -int mx50_revision(void) -{ - if (!cpu_is_mx50()) - return -EINVAL; - - if (mx5_cpu_rev == -1) - mx5_cpu_rev = get_mx50_srev(); - - return mx5_cpu_rev; -} -EXPORT_SYMBOL(mx50_revision); diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h deleted file mode 100644 index 2c290391f29..00000000000 --- a/arch/arm/mach-imx/devices-imx50.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include "devices/devices-common.h" - -extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[]; -#define imx50_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) - -extern const struct imx_fec_data imx50_fec_data; -#define imx50_add_fec(pdata) \ - imx_add_fec(&imx50_fec_data, pdata) - -extern const struct imx_imx_i2c_data imx50_imx_i2c_data[]; -#define imx50_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata) diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig index 9a8f1ca7bcb..9b9ba1f4ffe 100644 --- a/arch/arm/mach-imx/devices/Kconfig +++ b/arch/arm/mach-imx/devices/Kconfig @@ -1,6 +1,6 @@ config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 config IMX_HAVE_PLATFORM_FLEXCAN bool diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c index 2cb188ad9a0..63eba08f87b 100644 --- a/arch/arm/mach-imx/devices/platform-fec.c +++ b/arch/arm/mach-imx/devices/platform-fec.c @@ -35,12 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35, "imx27-fec"); #endif -#ifdef CONFIG_SOC_IMX50 -/* i.mx50 has the i.mx25 type fec */ -const struct imx_fec_data imx50_fec_data __initconst = - imx_fec_data_entry_single(MX50, "imx25-fec"); -#endif - #ifdef CONFIG_SOC_IMX51 /* i.mx51 has the i.mx27 type fec */ const struct imx_fec_data imx51_fec_data __initconst = diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c index 8e30e5703cd..57d342e85c2 100644 --- a/arch/arm/mach-imx/devices/platform-imx-i2c.c +++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c @@ -70,16 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_SOC_IMX50 -const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = { -#define imx50_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K) - imx50_imx_i2c_data_entry(0, 1), - imx50_imx_i2c_data_entry(1, 2), - imx50_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - #ifdef CONFIG_SOC_IMX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { #define imx51_imx_i2c_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c index 67bf866a2cb..faac4aa6ca6 100644 --- a/arch/arm/mach-imx/devices/platform-imx-uart.c +++ b/arch/arm/mach-imx/devices/platform-imx-uart.c @@ -94,18 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_SOC_IMX50 -const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = { -#define imx50_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K) - imx50_imx_uart_data_entry(0, 1), - imx50_imx_uart_data_entry(1, 2), - imx50_imx_uart_data_entry(2, 3), - imx50_imx_uart_data_entry(3, 4), - imx50_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX50 */ - #ifdef CONFIG_SOC_IMX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { #define imx51_imx_uart_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c index 04a5961beea..e02de188ae8 100644 --- a/arch/arm/mach-imx/epit.c +++ b/arch/arm/mach-imx/epit.c @@ -178,7 +178,6 @@ static struct irqaction epit_timer_irq = { static struct clock_event_device clockevent_epit = { .name = "epit", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_mode = epit_set_mode, .set_next_event = epit_set_next_event, .rating = 200, @@ -186,18 +185,10 @@ static struct clock_event_device clockevent_epit = { static int __init epit_clockevent_init(struct clk *timer_clk) { - unsigned int c = clk_get_rate(timer_clk); - - clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, - clockevent_epit.shift); - clockevent_epit.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_epit); - clockevent_epit.min_delta_ns = - clockevent_delta2ns(0x800, &clockevent_epit); - clockevent_epit.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_epit); + clockevents_config_and_register(&clockevent_epit, + clk_get_rate(timer_clk), + 0x800, 0xfffffffe); return 0; } diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index e1537f9e45b..ff24920699e 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -15,7 +15,7 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> -#include <asm/hardware/gic.h> +#include <linux/irqchip/arm-gic.h> #define GPC_IMR1 0x008 #define GPC_PGC_CPU_PDN 0x2a0 diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 3ce7fa3bd43..911e9b31b03 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -72,11 +72,6 @@ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * mx50: - * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 - * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 @@ -108,7 +103,6 @@ #include "mxc.h" #include "mx6q.h" -#include "mx50.h" #include "mx51.h" #include "mx53.h" #include "mx3x.h" diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c index e17dfbc4219..03b65e5ea54 100644 --- a/arch/arm/mach-imx/imx25-dt.c +++ b/arch/arm/mach-imx/imx25-dt.c @@ -22,15 +22,6 @@ static void __init imx25_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static void __init imx25_timer_init(void) -{ - mx25_clocks_init_dt(); -} - -static struct sys_timer imx25_timer = { - .init = imx25_timer_init, -}; - static const char * const imx25_dt_board_compat[] __initconst = { "fsl,imx25", NULL @@ -41,7 +32,7 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") .init_early = imx25_init_early, .init_irq = mx25_init_irq, .handle_irq = imx25_handle_irq, - .timer = &imx25_timer, + .init_time = imx25_timer_init, .init_machine = imx25_dt_init, .dt_compat = imx25_dt_board_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index ebfae96543c..c915a490a11 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c @@ -39,26 +39,22 @@ static void __init imx27_dt_init(void) imx27_auxdata_lookup, NULL); } -static void __init imx27_timer_init(void) -{ - mx27_clocks_init_dt(); -} - -static struct sys_timer imx27_timer = { - .init = imx27_timer_init, -}; - static const char * const imx27_dt_board_compat[] __initconst = { "fsl,imx27", NULL }; +static void __init imx27_timer_init(void) +{ + mx27_clocks_init_dt(); +} + DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") .map_io = mx27_map_io, .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &imx27_timer, + .init_time = imx27_timer_init, .init_machine = imx27_dt_init, .dt_compat = imx27_dt_board_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index af476de2570..b5c04eece78 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -38,26 +38,22 @@ static void __init imx31_dt_init(void) imx31_auxdata_lookup, NULL); } -static void __init imx31_timer_init(void) -{ - mx31_clocks_init_dt(); -} - -static struct sys_timer imx31_timer = { - .init = imx31_timer_init, -}; - static const char *imx31_dt_board_compat[] __initdata = { "fsl,imx31", NULL }; +static void __init imx31_dt_timer_init(void) +{ + mx31_clocks_init_dt(); +} + DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &imx31_timer, + .init_time = imx31_dt_timer_init, .init_machine = imx31_dt_init, .dt_compat = imx31_dt_board_compat, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index 5ffa40c673f..e2926a8863f 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -24,26 +24,22 @@ static void __init imx51_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static void __init imx51_timer_init(void) -{ - mx51_clocks_init_dt(); -} - -static struct sys_timer imx51_timer = { - .init = imx51_timer_init, -}; - static const char *imx51_dt_board_compat[] __initdata = { "fsl,imx51", NULL }; +static void __init imx51_timer_init(void) +{ + mx51_clocks_init_dt(); +} + DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") .map_io = mx51_map_io, .init_early = imx51_init_early, .init_irq = mx51_init_irq, .handle_irq = imx51_handle_irq, - .timer = &imx51_timer, + .init_time = imx51_timer_init, .init_machine = imx51_dt_init, .init_late = imx51_init_late, .dt_compat = imx51_dt_board_compat, diff --git a/arch/arm/mach-imx/iomux-mx50.h b/arch/arm/mach-imx/iomux-mx50.h deleted file mode 100644 index 00f56e0e800..00000000000 --- a/arch/arm/mach-imx/iomux-mx50.h +++ /dev/null @@ -1,977 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_IOMUX_MX50_H__ -#define __MACH_IOMUX_MX50_H__ - -#include "iomux-v3.h" - -#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) - -#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) - -#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) - -#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) - -#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) - -#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH) - -#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) - -#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) - -#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \ - PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL) - -#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL) - -#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL) - -#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL) - -#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL) - -#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \ - PAD_CTL_PKE | PAD_CTL_DSE_HIGH) - -#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL) -#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ - PAD_CTL_PKE | PAD_CTL_DSE_HIGH) -#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL) -#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL) -#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ - PAD_CTL_PKE | PAD_CTL_DSE_HIGH) -#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD) - -#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) - -#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE) - -#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL) - - -#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \ - PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH) -#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c deleted file mode 100644 index 2fdc9bf2fb5..00000000000 --- a/arch/arm/mach-imx/lluart.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <asm/page.h> -#include <asm/sizes.h> -#include <asm/mach/map.h> - -#include "hardware.h" - -#define IMX6Q_UART1_BASE_ADDR 0x02020000 -#define IMX6Q_UART2_BASE_ADDR 0x021e8000 -#define IMX6Q_UART3_BASE_ADDR 0x021ec000 -#define IMX6Q_UART4_BASE_ADDR 0x021f0000 -#define IMX6Q_UART5_BASE_ADDR 0x021f4000 - -/* - * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion - * of IMX6Q_UART##n##_BASE_ADDR. - */ -#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR -#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) -#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT) - -static struct map_desc imx_lluart_desc = { -#ifdef CONFIG_DEBUG_IMX6Q_UART - .virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE), - .pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE), - .length = 0x4000, - .type = MT_DEVICE, -#endif -}; - -void __init imx_lluart_map_io(void) -{ - if (imx_lluart_desc.virtual) - iotable_init(&imx_lluart_desc, 1); -} diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c index 5c9bd2c66e6..067580b2969 100644 --- a/arch/arm/mach-imx/mach-apf9328.c +++ b/arch/arm/mach-imx/mach-apf9328.c @@ -137,17 +137,13 @@ static void __init apf9328_timer_init(void) mx1_clocks_init(32768); } -static struct sys_timer apf9328_timer = { - .init = apf9328_timer_init, -}; - MACHINE_START(APF9328, "Armadeus APF9328") /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */ .map_io = mx1_map_io, .init_early = imx1_init_early, .init_irq = mx1_init_irq, .handle_irq = imx1_handle_irq, - .timer = &apf9328_timer, + .init_time = apf9328_timer_init, .init_machine = apf9328_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index 59bd6b06a6b..368a6e3f592 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c @@ -557,10 +557,6 @@ static void __init armadillo5x0_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer armadillo5x0_timer = { - .init = armadillo5x0_timer_init, -}; - MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ .atag_offset = 0x100, @@ -568,7 +564,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &armadillo5x0_timer, + .init_time = armadillo5x0_timer_init, .init_machine = armadillo5x0_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c index 3a39d5aec07..2d00476f7d2 100644 --- a/arch/arm/mach-imx/mach-bug.c +++ b/arch/arm/mach-imx/mach-bug.c @@ -53,16 +53,12 @@ static void __init bug_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer bug_timer = { - .init = bug_timer_init, -}; - MACHINE_START(BUG, "BugLabs BUGBase") .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &bug_timer, + .init_time = bug_timer_init, .init_machine = bug_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 12a370646b4..146559311bd 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -309,17 +309,13 @@ static void __init eukrea_cpuimx27_timer_init(void) mx27_clocks_init(26000000); } -static struct sys_timer eukrea_cpuimx27_timer = { - .init = eukrea_cpuimx27_timer_init, -}; - MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27") .atag_offset = 0x100, .map_io = mx27_map_io, .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &eukrea_cpuimx27_timer, + .init_time = eukrea_cpuimx27_timer_init, .init_machine = eukrea_cpuimx27_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 5a31bf8c8f4..771362d1fbe 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c @@ -193,10 +193,6 @@ static void __init eukrea_cpuimx35_timer_init(void) mx35_clocks_init(); } -static struct sys_timer eukrea_cpuimx35_timer = { - .init = eukrea_cpuimx35_timer_init, -}; - MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") /* Maintainer: Eukrea Electromatique */ .atag_offset = 0x100, @@ -204,7 +200,7 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") .init_early = imx35_init_early, .init_irq = mx35_init_irq, .handle_irq = imx35_handle_irq, - .timer = &eukrea_cpuimx35_timer, + .init_time = eukrea_cpuimx35_timer_init, .init_machine = eukrea_cpuimx35_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c index b727de029c8..9b7393234f6 100644 --- a/arch/arm/mach-imx/mach-cpuimx51sd.c +++ b/arch/arm/mach-imx/mach-cpuimx51sd.c @@ -355,10 +355,6 @@ static void __init eukrea_cpuimx51sd_timer_init(void) mx51_clocks_init(32768, 24000000, 22579200, 0); } -static struct sys_timer mxc_timer = { - .init = eukrea_cpuimx51sd_timer_init, -}; - MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") /* Maintainer: Eric Bénard <eric@eukrea.com> */ .atag_offset = 0x100, @@ -366,7 +362,7 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") .init_early = imx51_init_early, .init_irq = mx51_init_irq, .handle_irq = imx51_handle_irq, - .timer = &mxc_timer, + .init_time = eukrea_cpuimx51sd_timer_init, .init_machine = eukrea_cpuimx51sd_init, .init_late = imx51_init_late, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index 75027a5ad8b..4bf45442424 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -159,10 +159,6 @@ static void __init eukrea_cpuimx25_timer_init(void) mx25_clocks_init(); } -static struct sys_timer eukrea_cpuimx25_timer = { - .init = eukrea_cpuimx25_timer_init, -}; - MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") /* Maintainer: Eukrea Electromatique */ .atag_offset = 0x100, @@ -170,7 +166,7 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") .init_early = imx25_init_early, .init_irq = mx25_init_irq, .handle_irq = imx25_handle_irq, - .timer = &eukrea_cpuimx25_timer, + .init_time = eukrea_cpuimx25_timer_init, .init_machine = eukrea_cpuimx25_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 318bd8df7fc..29ac8ee651d 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -598,10 +598,6 @@ static void __init visstrim_m10_timer_init(void) mx27_clocks_init((unsigned long)25000000); } -static struct sys_timer visstrim_m10_timer = { - .init = visstrim_m10_timer_init, -}; - MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") .atag_offset = 0x100, .reserve = visstrim_reserve, @@ -609,7 +605,7 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &visstrim_m10_timer, + .init_time = visstrim_m10_timer_init, .init_machine = visstrim_m10_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c index 53a86011293..1a851aea683 100644 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ b/arch/arm/mach-imx/mach-imx27ipcam.c @@ -65,10 +65,6 @@ static void __init mx27ipcam_timer_init(void) mx27_clocks_init(25000000); } -static struct sys_timer mx27ipcam_timer = { - .init = mx27ipcam_timer_init, -}; - MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") /* maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, @@ -76,7 +72,7 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &mx27ipcam_timer, + .init_time = mx27ipcam_timer_init, .init_machine = mx27ipcam_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index fc8dce93137..3da2e3e44ce 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -72,17 +72,13 @@ static void __init mx27lite_timer_init(void) mx27_clocks_init(26000000); } -static struct sys_timer mx27lite_timer = { - .init = mx27lite_timer_init, -}; - MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") .atag_offset = 0x100, .map_io = mx27_map_io, .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &mx27lite_timer, + .init_time = mx27lite_timer_init, .init_machine = mx27lite_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 860284dea0e..f579c616fee 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -44,26 +44,22 @@ static void __init imx53_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static void __init imx53_timer_init(void) -{ - mx53_clocks_init_dt(); -} - -static struct sys_timer imx53_timer = { - .init = imx53_timer_init, -}; - static const char *imx53_dt_board_compat[] __initdata = { "fsl,imx53", NULL }; +static void __init imx53_timer_init(void) +{ + mx53_clocks_init_dt(); +} + DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") .map_io = mx53_map_io, .init_early = imx53_init_early, .init_irq = mx53_init_irq, .handle_irq = imx53_handle_irq, - .timer = &imx53_timer, + .init_time = imx53_timer_init, .init_machine = imx53_dt_init, .init_late = imx53_init_late, .dt_compat = imx53_dt_board_compat, diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 4eb1b3ac794..5a18e7e5c56 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -18,6 +18,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> @@ -29,8 +30,8 @@ #include <asm/cpuidle.h> #include <asm/smp_twd.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> +#include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/system_misc.h> @@ -216,22 +217,16 @@ static void __init imx6q_init_late(void) static void __init imx6q_map_io(void) { - imx_lluart_map_io(); + debug_ll_io_init(); imx_scu_map_io(); - imx6q_clock_map_io(); } -static const struct of_device_id imx6q_irq_match[] __initconst = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - { /* sentinel */ } -}; - static void __init imx6q_init_irq(void) { l2x0_of_init(0, ~0UL); imx_src_init(); imx_gpc_init(); - of_irq_init(imx6q_irq_match); + irqchip_init(); } static void __init imx6q_timer_init(void) @@ -241,10 +236,6 @@ static void __init imx6q_timer_init(void) imx_print_silicon_rev("i.MX6Q", imx6q_revision()); } -static struct sys_timer imx6q_timer = { - .init = imx6q_timer_init, -}; - static const char *imx6q_dt_compat[] __initdata = { "fsl,imx6q", NULL, @@ -254,8 +245,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)") .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, - .handle_irq = imx6q_handle_irq, - .timer = &imx6q_timer, + .init_time = imx6q_timer_init, .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c index 2e536ea5344..c7bc41d6b46 100644 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -284,17 +284,13 @@ static void __init kzm_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer kzm_timer = { - .init = kzm_timer_init, -}; - MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") .atag_offset = 0x100, .map_io = kzm_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &kzm_timer, + .init_time = kzm_timer_init, .init_machine = kzm_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 06b483783e6..9f883e4d6fc 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -132,10 +132,6 @@ static void __init mx1ads_timer_init(void) mx1_clocks_init(32000); } -static struct sys_timer mx1ads_timer = { - .init = mx1ads_timer_init, -}; - MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ .atag_offset = 0x100, @@ -143,7 +139,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") .init_early = imx1_init_early, .init_irq = mx1_init_irq, .handle_irq = imx1_handle_irq, - .timer = &mx1ads_timer, + .init_time = mx1ads_timer_init, .init_machine = mx1ads_init, .restart = mxc_restart, MACHINE_END @@ -154,7 +150,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS") .init_early = imx1_init_early, .init_irq = mx1_init_irq, .handle_irq = imx1_handle_irq, - .timer = &mx1ads_timer, + .init_time = mx1ads_timer_init, .init_machine = mx1ads_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 6adb3136bb0..a06aa4dc37f 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -318,10 +318,6 @@ static void __init mx21ads_timer_init(void) mx21_clocks_init(32768, 26000000); } -static struct sys_timer mx21ads_timer = { - .init = mx21ads_timer_init, -}; - MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, @@ -329,7 +325,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS") .init_early = imx21_init_early, .init_irq = mx21_init_irq, .handle_irq = imx21_handle_irq, - .timer = &mx21ads_timer, + .init_time = mx21ads_timer_init, .init_machine = mx21ads_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index b1b03aa55bb..8bcda688a00 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -257,10 +257,6 @@ static void __init mx25pdk_timer_init(void) mx25_clocks_init(); } -static struct sys_timer mx25pdk_timer = { - .init = mx25pdk_timer_init, -}; - MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, @@ -268,7 +264,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") .init_early = imx25_init_early, .init_irq = mx25_init_irq, .handle_irq = imx25_handle_irq, - .timer = &mx25pdk_timer, + .init_time = mx25pdk_timer_init, .init_machine = mx25pdk_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index d0e547fa925..25b3e4c9bc0 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -538,10 +538,6 @@ static void __init mx27pdk_timer_init(void) mx27_clocks_init(26000000); } -static struct sys_timer mx27pdk_timer = { - .init = mx27pdk_timer_init, -}; - MACHINE_START(MX27_3DS, "Freescale MX27PDK") /* maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, @@ -549,7 +545,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK") .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &mx27pdk_timer, + .init_time = mx27pdk_timer_init, .init_machine = mx27pdk_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 3d036f57f0e..9821b824dca 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -323,10 +323,6 @@ static void __init mx27ads_timer_init(void) mx27_clocks_init(fref); } -static struct sys_timer mx27ads_timer = { - .init = mx27ads_timer_init, -}; - static struct map_desc mx27ads_io_desc[] __initdata = { { .virtual = PBC_BASE_ADDRESS, @@ -349,7 +345,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &mx27ads_timer, + .init_time = mx27ads_timer_init, .init_machine = mx27ads_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index bc301befdd0..1ed916175d4 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -762,10 +762,6 @@ static void __init mx31_3ds_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer mx31_3ds_timer = { - .init = mx31_3ds_timer_init, -}; - static void __init mx31_3ds_reserve(void) { /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ @@ -780,7 +776,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &mx31_3ds_timer, + .init_time = mx31_3ds_timer_init, .init_machine = mx31_3ds_init, .reserve = mx31_3ds_reserve, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c index 8b56f8883f3..daf8889125c 100644 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ b/arch/arm/mach-imx/mach-mx31ads.c @@ -576,10 +576,6 @@ static void __init mx31ads_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer mx31ads_timer = { - .init = mx31ads_timer_init, -}; - MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, @@ -587,7 +583,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS") .init_early = imx31_init_early, .init_irq = mx31ads_init_irq, .handle_irq = imx31_handle_irq, - .timer = &mx31ads_timer, + .init_time = mx31ads_timer_init, .init_machine = mx31ads_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c index 08b9965c8b3..832b1e2f964 100644 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ b/arch/arm/mach-imx/mach-mx31lilly.c @@ -303,17 +303,13 @@ static void __init mx31lilly_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer mx31lilly_timer = { - .init = mx31lilly_timer_init, -}; - MACHINE_START(LILLY1131, "INCO startec LILLY-1131") .atag_offset = 0x100, .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &mx31lilly_timer, + .init_time = mx31lilly_timer_init, .init_machine = mx31lilly_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index bdcd92e5951..bea07299b61 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -285,10 +285,6 @@ static void __init mx31lite_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer mx31lite_timer = { - .init = mx31lite_timer_init, -}; - MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, @@ -296,7 +292,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &mx31lite_timer, + .init_time = mx31lite_timer_init, .init_machine = mx31lite_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index 2517cfa9f26..dae4cd7be04 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -596,10 +596,6 @@ static void __init mx31moboard_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer mx31moboard_timer = { - .init = mx31moboard_timer_init, -}; - static void __init mx31moboard_reserve(void) { /* reserve 4 MiB for mx3-camera */ @@ -615,7 +611,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &mx31moboard_timer, + .init_time = mx31moboard_timer_init, .init_machine = mx31moboard_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 5277da45d60..a42f4f07051 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c @@ -602,10 +602,6 @@ static void __init mx35pdk_timer_init(void) mx35_clocks_init(); } -static struct sys_timer mx35pdk_timer = { - .init = mx35pdk_timer_init, -}; - static void __init mx35_3ds_reserve(void) { /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ @@ -620,7 +616,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK") .init_early = imx35_init_early, .init_irq = mx35_init_irq, .handle_irq = imx35_handle_irq, - .timer = &mx35pdk_timer, + .init_time = mx35pdk_timer_init, .init_machine = mx35_3ds_init, .reserve = mx35_3ds_reserve, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c deleted file mode 100644 index 0c1f88a80bd..00000000000 --- a/arch/arm/mach-imx/mach-mx50_rdp.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx50.h" -#include "hardware.h" -#include "iomux-mx50.h" - -#define FEC_EN IMX_GPIO_NR(6, 23) -#define FEC_RESET_B IMX_GPIO_NR(4, 12) - -static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { - /* SD1 */ - MX50_PAD_ECSPI2_SS0__GPIO_4_19, - MX50_PAD_EIM_CRE__GPIO_1_27, - MX50_PAD_SD1_CMD__SD1_CMD, - - MX50_PAD_SD1_CLK__SD1_CLK, - MX50_PAD_SD1_D0__SD1_D0, - MX50_PAD_SD1_D1__SD1_D1, - MX50_PAD_SD1_D2__SD1_D2, - MX50_PAD_SD1_D3__SD1_D3, - - /* SD2 */ - MX50_PAD_SD2_CD__GPIO_5_17, - MX50_PAD_SD2_WP__GPIO_5_16, - MX50_PAD_SD2_CMD__SD2_CMD, - MX50_PAD_SD2_CLK__SD2_CLK, - MX50_PAD_SD2_D0__SD2_D0, - MX50_PAD_SD2_D1__SD2_D1, - MX50_PAD_SD2_D2__SD2_D2, - MX50_PAD_SD2_D3__SD2_D3, - MX50_PAD_SD2_D4__SD2_D4, - MX50_PAD_SD2_D5__SD2_D5, - MX50_PAD_SD2_D6__SD2_D6, - MX50_PAD_SD2_D7__SD2_D7, - - /* SD3 */ - MX50_PAD_SD3_CMD__SD3_CMD, - MX50_PAD_SD3_CLK__SD3_CLK, - MX50_PAD_SD3_D0__SD3_D0, - MX50_PAD_SD3_D1__SD3_D1, - MX50_PAD_SD3_D2__SD3_D2, - MX50_PAD_SD3_D3__SD3_D3, - MX50_PAD_SD3_D4__SD3_D4, - MX50_PAD_SD3_D5__SD3_D5, - MX50_PAD_SD3_D6__SD3_D6, - MX50_PAD_SD3_D7__SD3_D7, - - /* PWR_INT */ - MX50_PAD_ECSPI2_MISO__GPIO_4_18, - - /* UART pad setting */ - MX50_PAD_UART1_TXD__UART1_TXD, - MX50_PAD_UART1_RXD__UART1_RXD, - MX50_PAD_UART1_RTS__UART1_RTS, - MX50_PAD_UART2_TXD__UART2_TXD, - MX50_PAD_UART2_RXD__UART2_RXD, - MX50_PAD_UART2_CTS__UART2_CTS, - MX50_PAD_UART2_RTS__UART2_RTS, - - MX50_PAD_I2C1_SCL__I2C1_SCL, - MX50_PAD_I2C1_SDA__I2C1_SDA, - MX50_PAD_I2C2_SCL__I2C2_SCL, - MX50_PAD_I2C2_SDA__I2C2_SDA, - - MX50_PAD_EPITO__USBH1_PWR, - /* Need to comment below line if - * one needs to debug owire. - */ - MX50_PAD_OWIRE__USBH1_OC, - /* using gpio to control otg pwr */ - MX50_PAD_PWM2__GPIO_6_25, - MX50_PAD_I2C3_SCL__USBOTG_OC, - - MX50_PAD_SSI_RXC__FEC_MDIO, - MX50_PAD_SSI_RXFS__FEC_MDC, - MX50_PAD_DISP_D0__FEC_TXCLK, - MX50_PAD_DISP_D1__FEC_RX_ER, - MX50_PAD_DISP_D2__FEC_RX_DV, - MX50_PAD_DISP_D3__FEC_RXD1, - MX50_PAD_DISP_D4__FEC_RXD0, - MX50_PAD_DISP_D5__FEC_TX_EN, - MX50_PAD_DISP_D6__FEC_TXD1, - MX50_PAD_DISP_D7__FEC_TXD0, - MX50_PAD_I2C3_SDA__GPIO_6_23, - MX50_PAD_ECSPI1_SCLK__GPIO_4_12, - - MX50_PAD_CSPI_SS0__CSPI_SS0, - MX50_PAD_ECSPI1_MOSI__CSPI_SS1, - MX50_PAD_CSPI_MOSI__CSPI_MOSI, - MX50_PAD_CSPI_MISO__CSPI_MISO, - - /* SGTL500_OSC_EN */ - MX50_PAD_UART1_CTS__GPIO_6_8, - - /* SGTL_AMP_SHDN */ - MX50_PAD_UART3_RXD__GPIO_6_15, - - /* Keypad */ - MX50_PAD_KEY_COL0__KEY_COL0, - MX50_PAD_KEY_ROW0__KEY_ROW0, - MX50_PAD_KEY_COL1__KEY_COL1, - MX50_PAD_KEY_ROW1__KEY_ROW1, - MX50_PAD_KEY_COL2__KEY_COL2, - MX50_PAD_KEY_ROW2__KEY_ROW2, - MX50_PAD_KEY_COL3__KEY_COL3, - MX50_PAD_KEY_ROW3__KEY_ROW3, - MX50_PAD_EIM_DA0__KEY_COL4, - MX50_PAD_EIM_DA1__KEY_ROW4, - MX50_PAD_EIM_DA2__KEY_COL5, - MX50_PAD_EIM_DA3__KEY_ROW5, - MX50_PAD_EIM_DA4__KEY_COL6, - MX50_PAD_EIM_DA5__KEY_ROW6, - MX50_PAD_EIM_DA6__KEY_COL7, - MX50_PAD_EIM_DA7__KEY_ROW7, - /*EIM pads */ - MX50_PAD_EIM_DA8__GPIO_1_8, - MX50_PAD_EIM_DA9__GPIO_1_9, - MX50_PAD_EIM_DA10__GPIO_1_10, - MX50_PAD_EIM_DA11__GPIO_1_11, - MX50_PAD_EIM_DA12__GPIO_1_12, - MX50_PAD_EIM_DA13__GPIO_1_13, - MX50_PAD_EIM_DA14__GPIO_1_14, - MX50_PAD_EIM_DA15__GPIO_1_15, - MX50_PAD_EIM_CS2__GPIO_1_16, - MX50_PAD_EIM_CS1__GPIO_1_17, - MX50_PAD_EIM_CS0__GPIO_1_18, - MX50_PAD_EIM_EB0__GPIO_1_19, - MX50_PAD_EIM_EB1__GPIO_1_20, - MX50_PAD_EIM_WAIT__GPIO_1_21, - MX50_PAD_EIM_BCLK__GPIO_1_22, - MX50_PAD_EIM_RDY__GPIO_1_23, - MX50_PAD_EIM_OE__GPIO_1_24, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct fec_platform_data fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static inline void mx50_rdp_fec_reset(void) -{ - gpio_request(FEC_EN, "fec-en"); - gpio_direction_output(FEC_EN, 0); - gpio_request(FEC_RESET_B, "fec-reset_b"); - gpio_direction_output(FEC_RESET_B, 0); - msleep(1); - gpio_set_value(FEC_RESET_B, 1); -} - -static const struct imxi2c_platform_data i2c_data __initconst = { - .bitrate = 100000, -}; - -/* - * Board specific initialization. - */ -static void __init mx50_rdp_board_init(void) -{ - imx50_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads, - ARRAY_SIZE(mx50_rdp_pads)); - - imx50_add_imx_uart(0, &uart_pdata); - imx50_add_imx_uart(1, &uart_pdata); - mx50_rdp_fec_reset(); - imx50_add_fec(&fec_data); - imx50_add_imx_i2c(0, &i2c_data); - imx50_add_imx_i2c(1, &i2c_data); - imx50_add_imx_i2c(2, &i2c_data); -} - -static void __init mx50_rdp_timer_init(void) -{ - mx50_clocks_init(32768, 24000000, 22579200); -} - -static struct sys_timer mx50_rdp_timer = { - .init = mx50_rdp_timer_init, -}; - -MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") - .map_io = mx50_map_io, - .init_early = imx50_init_early, - .init_irq = mx50_init_irq, - .handle_irq = imx50_handle_irq, - .timer = &mx50_rdp_timer, - .init_machine = mx50_rdp_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c deleted file mode 100644 index abc25bd1107..00000000000 --- a/arch/arm/mach-imx/mach-mx51_3ds.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx51.h" -#include "hardware.h" -#include "iomux-mx51.h" - -#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) - -static iomux_v3_cfg_t mx51_3ds_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - MX51_PAD_EIM_D25__UART2_CTS, - MX51_PAD_EIM_D26__UART2_RTS, - - /* UART3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - MX51_PAD_EIM_D24__UART3_CTS, - MX51_PAD_EIM_D27__UART3_RTS, - - /* CPLD PARENT IRQ PIN */ - MX51_PAD_GPIO1_6__GPIO1_6, - - /* KPP */ - MX51_PAD_KEY_ROW0__KEY_ROW0, - MX51_PAD_KEY_ROW1__KEY_ROW1, - MX51_PAD_KEY_ROW2__KEY_ROW2, - MX51_PAD_KEY_ROW3__KEY_ROW3, - MX51_PAD_KEY_COL0__KEY_COL0, - MX51_PAD_KEY_COL1__KEY_COL1, - MX51_PAD_KEY_COL2__KEY_COL2, - MX51_PAD_KEY_COL3__KEY_COL3, - MX51_PAD_KEY_COL4__KEY_COL4, - MX51_PAD_KEY_COL5__KEY_COL5, - - /* eCSPI2 */ - MX51_PAD_NANDF_RB2__ECSPI2_SCLK, - MX51_PAD_NANDF_RB3__ECSPI2_MISO, - MX51_PAD_NANDF_D15__ECSPI2_MOSI, - MX51_PAD_NANDF_D12__GPIO3_28, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int mx51_3ds_board_keymap[] = { - KEY(0, 0, KEY_1), - KEY(0, 1, KEY_2), - KEY(0, 2, KEY_3), - KEY(0, 3, KEY_F1), - KEY(0, 4, KEY_UP), - KEY(0, 5, KEY_F2), - - KEY(1, 0, KEY_4), - KEY(1, 1, KEY_5), - KEY(1, 2, KEY_6), - KEY(1, 3, KEY_LEFT), - KEY(1, 4, KEY_SELECT), - KEY(1, 5, KEY_RIGHT), - - KEY(2, 0, KEY_7), - KEY(2, 1, KEY_8), - KEY(2, 2, KEY_9), - KEY(2, 3, KEY_F3), - KEY(2, 4, KEY_DOWN), - KEY(2, 5, KEY_F4), - - KEY(3, 0, KEY_0), - KEY(3, 1, KEY_OK), - KEY(3, 2, KEY_ESC), - KEY(3, 3, KEY_ENTER), - KEY(3, 4, KEY_MENU), - KEY(3, 5, KEY_BACK) -}; - -static const struct matrix_keymap_data mx51_3ds_map_data __initconst = { - .keymap = mx51_3ds_board_keymap, - .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), -}; - -static int mx51_3ds_spi2_cs[] = { - MXC_SPI_CS(0), - MX51_3DS_ECSPI2_CS, -}; - -static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = { - .chipselect = mx51_3ds_spi2_cs, - .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs), -}; - -static struct spi_board_info mx51_3ds_spi_nor_device[] = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL,}, -}; - -/* - * Board specific initialization. - */ -static void __init mx51_3ds_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, - ARRAY_SIZE(mx51_3ds_pads)); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); - - imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); - spi_register_board_info(mx51_3ds_spi_nor_device, - ARRAY_SIZE(mx51_3ds_spi_nor_device)); - - if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6))) - printk(KERN_WARNING "Init of the debugboard failed, all " - "devices on the board are unusable.\n"); - - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_imx_keypad(&mx51_3ds_map_data); - imx51_add_imx2_wdt(0); -} - -static void __init mx51_3ds_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -static struct sys_timer mx51_3ds_timer = { - .init = mx51_3ds_timer_init, -}; - -MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .timer = &mx51_3ds_timer, - .init_machine = mx51_3ds_init, - .init_late = imx51_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c index d9a84ca2199..6c4d7feb452 100644 --- a/arch/arm/mach-imx/mach-mx51_babbage.c +++ b/arch/arm/mach-imx/mach-mx51_babbage.c @@ -418,10 +418,6 @@ static void __init mx51_babbage_timer_init(void) mx51_clocks_init(32768, 24000000, 22579200, 0); } -static struct sys_timer mx51_babbage_timer = { - .init = mx51_babbage_timer_init, -}; - MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ .atag_offset = 0x100, @@ -429,7 +425,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") .init_early = imx51_init_early, .init_irq = mx51_init_irq, .handle_irq = imx51_handle_irq, - .timer = &mx51_babbage_timer, + .init_time = mx51_babbage_timer_init, .init_machine = mx51_babbage_init, .init_late = imx51_init_late, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index f4a8c7e108e..a27faaba98e 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -261,10 +261,6 @@ static void __init mxt_td60_timer_init(void) mx27_clocks_init(26000000); } -static struct sys_timer mxt_td60_timer = { - .init = mxt_td60_timer_init, -}; - MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") /* maintainer: Maxtrack Industrial */ .atag_offset = 0x100, @@ -272,7 +268,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &mxt_td60_timer, + .init_time = mxt_td60_timer_init, .init_machine = mxt_td60_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index eee369fa94a..b8b15bb1ffd 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -416,10 +416,6 @@ static void __init pca100_timer_init(void) mx27_clocks_init(26000000); } -static struct sys_timer pca100_timer = { - .init = pca100_timer_init, -}; - MACHINE_START(PCA100, "phyCARD-i.MX27") .atag_offset = 0x100, .map_io = mx27_map_io, @@ -427,6 +423,6 @@ MACHINE_START(PCA100, "phyCARD-i.MX27") .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, .init_machine = pca100_init, - .timer = &pca100_timer, + .init_time = pca100_timer_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 547fef133f6..bc0261e99d3 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -685,10 +685,6 @@ static void __init pcm037_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer pcm037_timer = { - .init = pcm037_timer_init, -}; - static void __init pcm037_reserve(void) { /* reserve 4 MiB for mx3-camera */ @@ -709,7 +705,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &pcm037_timer, + .init_time = pcm037_timer_init, .init_machine = pcm037_init, .init_late = pcm037_init_late, .restart = mxc_restart, diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 4aa0d079860..e805ac273e9 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -346,17 +346,13 @@ static void __init pcm038_timer_init(void) mx27_clocks_init(26000000); } -static struct sys_timer pcm038_timer = { - .init = pcm038_timer_init, -}; - MACHINE_START(PCM038, "phyCORE-i.MX27") .atag_offset = 0x100, .map_io = mx27_map_io, .init_early = imx27_init_early, .init_irq = mx27_init_irq, .handle_irq = imx27_handle_irq, - .timer = &pcm038_timer, + .init_time = pcm038_timer_init, .init_machine = pcm038_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 92445440221..8ed533f0f8c 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -394,10 +394,6 @@ static void __init pcm043_timer_init(void) mx35_clocks_init(); } -static struct sys_timer pcm043_timer = { - .init = pcm043_timer_init, -}; - MACHINE_START(PCM043, "Phytec Phycore pcm043") /* Maintainer: Pengutronix */ .atag_offset = 0x100, @@ -405,7 +401,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043") .init_early = imx35_init_early, .init_irq = mx35_init_irq, .handle_irq = imx35_handle_irq, - .timer = &pcm043_timer, + .init_time = pcm043_timer_init, .init_machine = pcm043_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index 96d9a91f8a3..22af27ed457 100644 --- a/arch/arm/mach-imx/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c @@ -260,10 +260,6 @@ static void __init qong_timer_init(void) mx31_clocks_init(26000000); } -static struct sys_timer qong_timer = { - .init = qong_timer_init, -}; - MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ .atag_offset = 0x100, @@ -271,7 +267,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") .init_early = imx31_init_early, .init_irq = mx31_init_irq, .handle_irq = imx31_handle_irq, - .timer = &qong_timer, + .init_time = qong_timer_init, .init_machine = qong_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index fc970409dba..b0fa10dd79f 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -131,10 +131,6 @@ static void __init scb9328_timer_init(void) mx1_clocks_init(32000); } -static struct sys_timer scb9328_timer = { - .init = scb9328_timer_init, -}; - MACHINE_START(SCB9328, "Synertronixx scb9328") /* Sascha Hauer */ .atag_offset = 100, @@ -142,7 +138,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328") .init_early = imx1_init_early, .init_irq = mx1_init_irq, .handle_irq = imx1_handle_irq, - .timer = &scb9328_timer, + .init_time = scb9328_timer_init, .init_machine = scb9328_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 3aecf91e428..0910761e828 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -305,17 +305,13 @@ static void __init vpr200_timer_init(void) mx35_clocks_init(); } -static struct sys_timer vpr200_timer = { - .init = vpr200_timer_init, -}; - MACHINE_START(VPR200, "VPR200") /* Maintainer: Creative Product Design */ .map_io = mx35_map_io, .init_early = imx35_init_early, .init_irq = mx35_init_irq, .handle_irq = imx35_handle_irq, - .timer = &vpr200_timer, + .init_time = vpr200_timer_init, .init_machine = vpr200_board_init, .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 79d71cf23a1..cf34994cfe2 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -24,16 +24,6 @@ #include "iomux-v3.h" /* - * Define the MX50 memory map. - */ -static struct map_desc mx50_io_desc[] __initdata = { - imx_map_entry(MX50, TZIC, MT_DEVICE), - imx_map_entry(MX50, SPBA0, MT_DEVICE), - imx_map_entry(MX50, AIPS1, MT_DEVICE), - imx_map_entry(MX50, AIPS2, MT_DEVICE), -}; - -/* * Define the MX51 memory map. */ static struct map_desc mx51_io_desc[] __initdata = { @@ -59,11 +49,6 @@ static struct map_desc mx53_io_desc[] __initdata = { * system startup to create static physical to virtual memory mappings * for the IO modules. */ -void __init mx50_map_io(void) -{ - iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); -} - void __init mx51_map_io(void) { iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); @@ -74,13 +59,6 @@ void __init mx53_map_io(void) iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); } -void __init imx50_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX50); - mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); -} - /* * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by * the Freescale marketing division. However this did not remove the @@ -115,11 +93,6 @@ void __init imx53_init_early(void) mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); } -void __init mx50_init_irq(void) -{ - tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); -} - void __init mx51_init_irq(void) { tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); @@ -148,31 +121,10 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = { .script_addrs = &imx51_sdma_script, }; -static const struct resource imx50_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), -}; - static const struct resource imx51_audmux_res[] __initconst = { DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), }; -void __init imx50_soc_init(void) -{ - mxc_device_init(); - - /* i.mx50 has the i.mx35 type gpio */ - mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); - mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); - mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); - mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); - mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); - mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); - - /* i.mx50 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res, - ARRAY_SIZE(imx50_audmux_res)); -} - void __init imx51_soc_init(void) { mxc_device_init(); diff --git a/arch/arm/mach-imx/mx50.h b/arch/arm/mach-imx/mx50.h deleted file mode 100644 index 09ac19c1570..00000000000 --- a/arch/arm/mach-imx/mx50.h +++ /dev/null @@ -1,290 +0,0 @@ -#ifndef __MACH_MX50_H__ -#define __MACH_MX50_H__ - -/* - * IROM - */ -#define MX50_IROM_BASE_ADDR 0x0 -#define MX50_IROM_SIZE SZ_64K - -/* TZIC */ -#define MX50_TZIC_BASE_ADDR 0x0fffc000 -#define MX50_TZIC_SIZE SZ_16K - -/* - * IRAM - */ -#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ -#define MX50_IRAM_PARTITIONS 16 -#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -/* - * Databahn - */ -#define MX50_DATABAHN_BASE_ADDR 0x14000000 - -/* - * Graphics Memory of GPU - */ -#define MX50_GPU2D_BASE_ADDR 0x20000000 - -#define MX50_DEBUG_BASE_ADDR 0x40000000 -#define MX50_DEBUG_SIZE SZ_1M -#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) -#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) -#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) -#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) -#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) -#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) -#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) -#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) - -#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) -#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) -#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) -#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) -#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) -#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) -#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) -#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) -#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) -#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) -#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) -#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) -#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) -#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) - -/* - * SPBA global module enabled #0 - */ -#define MX50_SPBA0_BASE_ADDR 0x50000000 -#define MX50_SPBA0_SIZE SZ_1M - -#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) -#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) -#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) -#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) -#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) -#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) -#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) - -/* - * AIPS 1 - */ -#define MX50_AIPS1_BASE_ADDR 0x53f00000 -#define MX50_AIPS1_SIZE SZ_1M - -#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) -#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) -#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) -#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) -#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) -#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) -#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) -#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) -#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) -#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) -#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) -#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) -#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) -#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) -#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) -#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) -#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) -#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) -#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) -#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) -#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) -#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) - -#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) -#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) - -/* - * AIPS 2 - */ -#define MX50_AIPS2_BASE_ADDR 0x63f00000 -#define MX50_AIPS2_SIZE SZ_1M - -#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) -#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) -#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) -#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) -#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) -#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) -#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) -#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) -#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) -#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) -#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) -#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) -#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) -#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) -#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) -#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) -#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) - -/* - * Memory regions and CS - */ -#define MX50_CSD0_BASE_ADDR 0x70000000 -#define MX50_CSD1_BASE_ADDR 0xb0000000 -#define MX50_CS0_BASE_ADDR 0xf0000000 - -#define MX50_IO_P2V(x) IMX_IO_P2V(x) -#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX50_SPBA_SDHC1 0x04 -#define MX50_SPBA_SDHC2 0x08 -#define MX50_SPBA_UART3 0x0c -#define MX50_SPBA_CSPI1 0x10 -#define MX50_SPBA_SSI2 0x14 -#define MX50_SPBA_SDHC3 0x20 -#define MX50_SPBA_SDHC4 0x24 -#define MX50_SPBA_SPDIF 0x28 -#define MX50_SPBA_ATA 0x30 -#define MX50_SPBA_SLIM 0x34 -#define MX50_SPBA_HSI2C 0x38 -#define MX50_SPBA_CTRL 0x3c - -/* - * DMA request assignments - */ -#define MX50_DMA_REQ_GPC 1 -#define MX50_DMA_REQ_ATA_UART4_RX 2 -#define MX50_DMA_REQ_ATA_UART4_TX 3 -#define MX50_DMA_REQ_CSPI1_RX 6 -#define MX50_DMA_REQ_CSPI1_TX 7 -#define MX50_DMA_REQ_CSPI2_RX 8 -#define MX50_DMA_REQ_CSPI2_TX 9 -#define MX50_DMA_REQ_I2C3_SDHC3 10 -#define MX50_DMA_REQ_SDHC4 11 -#define MX50_DMA_REQ_UART2_FIRI_RX 12 -#define MX50_DMA_REQ_UART2_FIRI_TX 13 -#define MX50_DMA_REQ_EXT0 14 -#define MX50_DMA_REQ_EXT1 15 -#define MX50_DMA_REQ_UART5_RX 16 -#define MX50_DMA_REQ_UART5_TX 17 -#define MX50_DMA_REQ_UART1_RX 18 -#define MX50_DMA_REQ_UART1_TX 19 -#define MX50_DMA_REQ_I2C1_SDHC1 20 -#define MX50_DMA_REQ_I2C2_SDHC2 21 -#define MX50_DMA_REQ_SSI2_RX2 22 -#define MX50_DMA_REQ_SSI2_TX2 23 -#define MX50_DMA_REQ_SSI2_RX1 24 -#define MX50_DMA_REQ_SSI2_TX1 25 -#define MX50_DMA_REQ_SSI1_RX2 26 -#define MX50_DMA_REQ_SSI1_TX2 27 -#define MX50_DMA_REQ_SSI1_RX1 28 -#define MX50_DMA_REQ_SSI1_TX1 29 -#define MX50_DMA_REQ_CSPI_RX 38 -#define MX50_DMA_REQ_CSPI_TX 39 -#define MX50_DMA_REQ_UART3_RX 42 -#define MX50_DMA_REQ_UART3_TX 43 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1) -#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2) -#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3) -#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4) -#define MX50_INT_DAP (NR_IRQS_LEGACY + 5) -#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13) -#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14) -#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19) -#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20) -#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21) -#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27) -#define MX50_INT_NIC (NR_IRQS_LEGACY + 28) -#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34) -#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35) -#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36) -#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37) -#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX50_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX50_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64) -#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65) -#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66) -#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67) -#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68) -#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69) -#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX50_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX50_INT_NM (NR_IRQS_LEGACY + 76) -#define MX50_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86) -#define MX50_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX50_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91) -#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92) -#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97) -#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100) -#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102) -#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) -#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) -#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) -#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) -#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109) -#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110) -#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111) -#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112) -#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113) -#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114) -#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115) -#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116) -#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117) - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx50_revision(void); -#endif - -#endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index d78298366a9..7dce17a9fe6 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -32,7 +32,6 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 -#define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 @@ -126,18 +125,6 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_SOC_IMX50 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX50 -# endif -# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) -#else -# define cpu_is_mx50() (0) -#endif - #ifdef CONFIG_SOC_IMX51 # ifdef mxc_cpu_type # undef mxc_cpu_type diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 66fae885c84..b2872ec614a 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -12,9 +12,9 @@ #include <linux/init.h> #include <linux/smp.h> +#include <linux/irqchip/arm-gic.h> #include <asm/page.h> #include <asm/smp_scu.h> -#include <asm/hardware/gic.h> #include <asm/mach/map.h> #include "common.h" @@ -71,8 +71,6 @@ static void __init imx_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } void imx_smp_prepare(void) diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 2e063c2deb9..f67fd7ee812 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -34,7 +34,7 @@ /* * set cpu low power mode before WFI instruction. This function is called - * mx5 because it can be used for mx50, mx51, and mx53. + * mx5 because it can be used for mx51, and mx53. */ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { @@ -85,10 +85,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); - - /* Enable NEON SRPG for all but MX50TO1.0. */ - if (mx50_revision() != IMX_CHIP_REVISION_1_0) - __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); if (stop_mode) { empgc0 |= MXC_SRPGCR_PCR; diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index f017302f6d0..62769df36db 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -256,7 +256,6 @@ static struct irqaction mxc_timer_irq = { static struct clock_event_device clockevent_mxc = { .name = "mxc_timer1", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_mode = mxc_set_mode, .set_next_event = mx1_2_set_next_event, .rating = 200, @@ -264,21 +263,13 @@ static struct clock_event_device clockevent_mxc = { static int __init mxc_clockevent_init(struct clk *timer_clk) { - unsigned int c = clk_get_rate(timer_clk); - if (timer_is_v2()) clockevent_mxc.set_next_event = v2_set_next_event; - clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, - clockevent_mxc.shift); - clockevent_mxc.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_mxc); - clockevent_mxc.min_delta_ns = - clockevent_delta2ns(0xff, &clockevent_mxc); - clockevent_mxc.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_mxc); + clockevents_config_and_register(&clockevent_mxc, + clk_get_rate(timer_clk), + 0xff, 0xfffffffe); return 0; } diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h index 79197d8b34a..72516658be1 100644 --- a/arch/arm/mach-integrator/common.h +++ b/arch/arm/mach-integrator/common.h @@ -1,10 +1,5 @@ #include <linux/amba/serial.h> -#ifdef CONFIG_ARCH_INTEGRATOR_AP extern struct amba_pl010_data ap_uart_data; -#else -/* Not used without Integrator/AP support anyway */ -struct amba_pl010_data ap_uart_data {}; -#endif void integrator_init_early(void); int integrator_init(bool is_cp); void integrator_reserve(void); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 39c060f75e4..81461d21871 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -71,7 +71,7 @@ int __init integrator_init(bool is_cp) * hard-code them. The Integator/CP and forward have proper cell IDs. * Else we leave them undefined to the bus driver can autoprobe them. */ - if (!is_cp) { + if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) { rtc_device.periphid = 0x00041030; uart0_device.periphid = 0x00041010; uart1_device.periphid = 0x00041010; diff --git a/arch/arm/mach-integrator/include/mach/uncompress.h b/arch/arm/mach-integrator/include/mach/uncompress.h index 30452f00a16..8f3cc9954c1 100644 --- a/arch/arm/mach-integrator/include/mach/uncompress.h +++ b/arch/arm/mach-integrator/include/mach/uncompress.h @@ -46,5 +46,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 11e2a414580..ea961445e0e 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -94,7 +94,7 @@ void __iomem *ap_syscon_base; * f1b00000 1b000000 GPIO */ -static struct map_desc ap_io_desc[] __initdata = { +static struct map_desc ap_io_desc[] __initdata __maybe_unused = { { .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), @@ -425,7 +425,7 @@ void __init ap_init_early(void) #ifdef CONFIG_OF -static void __init ap_init_timer_of(void) +static void __init ap_of_timer_init(void) { struct device_node *node; const char *path; @@ -464,10 +464,6 @@ static void __init ap_init_timer_of(void) integrator_clockevent_init(rate, base, irq); } -static struct sys_timer ap_of_timer = { - .init = ap_init_timer_of, -}; - static const struct of_device_id fpga_irq_of_match[] __initconst = { { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, { /* Sentinel */ } @@ -586,7 +582,7 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") .init_early = ap_init_early, .init_irq = ap_init_irq_of, .handle_irq = fpga_handle_irq, - .timer = &ap_of_timer, + .init_time = ap_of_timer_init, .init_machine = ap_init_of, .restart = integrator_restart, .dt_compat = ap_dt_board_compat, @@ -613,7 +609,6 @@ static struct map_desc ap_io_desc_atag[] __initdata = { static void __init ap_map_io_atag(void) { iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag)); - ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); ap_map_io(); } @@ -638,7 +633,7 @@ static struct platform_device cfi_flash_device = { .resource = &cfi_flash_resource, }; -static void __init ap_init_timer(void) +static void __init ap_timer_init(void) { struct clk *clk; unsigned long rate; @@ -657,10 +652,6 @@ static void __init ap_init_timer(void) IRQ_TIMERINT1); } -static struct sys_timer ap_timer = { - .init = ap_init_timer, -}; - #define INTEGRATOR_SC_VALID_INT 0x003fffff static void __init ap_init_irq(void) @@ -685,6 +676,7 @@ static void __init ap_init(void) platform_device_register(&cfi_flash_device); + ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); for (i = 0; i < 4; i++) { struct lm_device *lmdev; @@ -716,7 +708,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator") .init_early = ap_init_early, .init_irq = ap_init_irq, .handle_irq = fpga_handle_irq, - .timer = &ap_timer, + .init_time = ap_timer_init, .init_machine = ap_init, .restart = integrator_restart, MACHINE_END diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 7322838c044..2b0db82a538 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -78,7 +78,7 @@ static void __iomem *intcp_con_base; * fcb00000 cb000000 CP system control */ -static struct map_desc intcp_io_desc[] __initdata = { +static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { { .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), @@ -251,7 +251,7 @@ static void __init intcp_init_early(void) #ifdef CONFIG_OF -static void __init intcp_timer_init_of(void) +static void __init cp_of_timer_init(void) { struct device_node *node; const char *path; @@ -283,10 +283,6 @@ static void __init intcp_timer_init_of(void) sp804_clockevents_init(base, irq, node->name); } -static struct sys_timer cp_of_timer = { - .init = intcp_timer_init_of, -}; - static const struct of_device_id fpga_irq_of_match[] __initconst = { { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, { /* Sentinel */ } @@ -390,7 +386,7 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") .init_early = intcp_init_early, .init_irq = intcp_init_irq_of, .handle_irq = fpga_handle_irq, - .timer = &cp_of_timer, + .init_time = cp_of_timer_init, .init_machine = intcp_init_of, .restart = integrator_restart, .dt_compat = intcp_dt_board_compat, @@ -512,7 +508,7 @@ static void __init intcp_init_irq(void) #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) -static void __init intcp_timer_init(void) +static void __init cp_timer_init(void) { writel(0, TIMER0_VA_BASE + TIMER_CTRL); writel(0, TIMER1_VA_BASE + TIMER_CTRL); @@ -522,10 +518,6 @@ static void __init intcp_timer_init(void) sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); } -static struct sys_timer cp_timer = { - .init = intcp_timer_init, -}; - #define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } @@ -565,7 +557,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") .init_early = intcp_init_early, .init_irq = intcp_init_irq, .handle_irq = fpga_handle_irq, - .timer = &cp_timer, + .init_time = cp_timer_init, .init_machine = intcp_init, .restart = integrator_restart, MACHINE_END diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h index fa4f80522fa..d3791ece277 100644 --- a/arch/arm/mach-iop13xx/include/mach/uncompress.h +++ b/arch/arm/mach-iop13xx/include/mach/uncompress.h @@ -20,4 +20,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index e3f3e7daa79..02a8228ac2d 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -84,17 +84,13 @@ static void __init iq81340mc_timer_init(void) iop_init_time(bus_freq); } -static struct sys_timer iq81340mc_timer = { - .init = iq81340mc_timer_init, -}; - MACHINE_START(IQ81340MC, "Intel IQ81340MC") /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ .atag_offset = 0x100, .init_early = iop13xx_init_early, .map_io = iop13xx_map_io, .init_irq = iop13xx_init_irq, - .timer = &iq81340mc_timer, + .init_time = iq81340mc_timer_init, .init_machine = iq81340mc_init, .restart = iop13xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index e9474411163..1b80f10722b 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -86,17 +86,13 @@ static void __init iq81340sc_timer_init(void) iop_init_time(bus_freq); } -static struct sys_timer iq81340sc_timer = { - .init = iq81340sc_timer_init, -}; - MACHINE_START(IQ81340SC, "Intel IQ81340SC") /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ .atag_offset = 0x100, .init_early = iop13xx_init_early, .map_io = iop13xx_map_io, .init_irq = iop13xx_init_irq, - .timer = &iq81340sc_timer, + .init_time = iq81340sc_timer_init, .init_machine = iq81340sc_init, .restart = iop13xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 9f369f09c29..31fbb6c61b2 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -40,10 +40,6 @@ static void __init em7210_timer_init(void) iop_init_time(200000000); } -static struct sys_timer em7210_timer = { - .init = em7210_timer_init, -}; - /* * EM7210 RTC */ @@ -205,7 +201,7 @@ MACHINE_START(EM7210, "Lanner EM7210") .atag_offset = 0x100, .map_io = em7210_map_io, .init_irq = iop32x_init_irq, - .timer = &em7210_timer, + .init_time = em7210_timer_init, .init_machine = em7210_init_machine, .restart = iop3xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index 02e20c3912b..ac304705fe6 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -44,10 +44,6 @@ static void __init glantank_timer_init(void) iop_init_time(200000000); } -static struct sys_timer glantank_timer = { - .init = glantank_timer_init, -}; - /* * GLAN Tank I/O. @@ -209,7 +205,7 @@ MACHINE_START(GLANTANK, "GLAN Tank") .atag_offset = 0x100, .map_io = glantank_map_io, .init_irq = iop32x_init_irq, - .timer = &glantank_timer, + .init_time = glantank_timer_init, .init_machine = glantank_init_machine, .restart = iop3xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h index 4fd715496f4..b3d45fd365e 100644 --- a/arch/arm/mach-iop32x/include/mach/uncompress.h +++ b/arch/arm/mach-iop32x/include/mach/uncompress.h @@ -36,4 +36,3 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) * nothing to do */ #define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index ddd1c7ecfe5..f2cd2966212 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -75,10 +75,6 @@ static void __init iq31244_timer_init(void) } } -static struct sys_timer iq31244_timer = { - .init = iq31244_timer_init, -}; - /* * IQ31244 I/O. @@ -314,7 +310,7 @@ MACHINE_START(IQ31244, "Intel IQ31244") .atag_offset = 0x100, .map_io = iq31244_map_io, .init_irq = iop32x_init_irq, - .timer = &iq31244_timer, + .init_time = iq31244_timer_init, .init_machine = iq31244_init_machine, .restart = iop3xx_restart, MACHINE_END @@ -329,7 +325,7 @@ MACHINE_START(EP80219, "Intel EP80219") .atag_offset = 0x100, .map_io = iq31244_map_io, .init_irq = iop32x_init_irq, - .timer = &iq31244_timer, + .init_time = iq31244_timer_init, .init_machine = iq31244_init_machine, .restart = iop3xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index bf155e6a3b4..015435de90d 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -43,10 +43,6 @@ static void __init iq80321_timer_init(void) iop_init_time(200000000); } -static struct sys_timer iq80321_timer = { - .init = iq80321_timer_init, -}; - /* * IQ80321 I/O. @@ -188,7 +184,7 @@ MACHINE_START(IQ80321, "Intel IQ80321") .atag_offset = 0x100, .map_io = iq80321_map_io, .init_irq = iop32x_init_irq, - .timer = &iq80321_timer, + .init_time = iq80321_timer_init, .init_machine = iq80321_init_machine, .restart = iop3xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 5a7ae91e884..ea0984a7449 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -50,10 +50,6 @@ static void __init n2100_timer_init(void) iop_init_time(198000000); } -static struct sys_timer n2100_timer = { - .init = n2100_timer_init, -}; - /* * N2100 I/O. @@ -337,7 +333,7 @@ MACHINE_START(N2100, "Thecus N2100") .atag_offset = 0x100, .map_io = n2100_map_io, .init_irq = iop32x_init_irq, - .timer = &n2100_timer, + .init_time = n2100_timer_init, .init_machine = n2100_init_machine, .restart = n2100_restart, MACHINE_END diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h index f99bb848c5a..ed282e14176 100644 --- a/arch/arm/mach-iop33x/include/mach/uncompress.h +++ b/arch/arm/mach-iop33x/include/mach/uncompress.h @@ -34,4 +34,3 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) * nothing to do */ #define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index e74a7debe79..c43304a10fa 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -45,10 +45,6 @@ static void __init iq80331_timer_init(void) iop_init_time(266000000); } -static struct sys_timer iq80331_timer = { - .init = iq80331_timer_init, -}; - /* * IQ80331 PCI. @@ -143,7 +139,7 @@ MACHINE_START(IQ80331, "Intel IQ80331") .atag_offset = 0x100, .map_io = iop3xx_map_io, .init_irq = iop33x_init_irq, - .timer = &iq80331_timer, + .init_time = iq80331_timer_init, .init_machine = iq80331_init_machine, .restart = iop3xx_restart, MACHINE_END diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index e2f5beece6e..8192987e78e 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -45,10 +45,6 @@ static void __init iq80332_timer_init(void) iop_init_time(266000000); } -static struct sys_timer iq80332_timer = { - .init = iq80332_timer_init, -}; - /* * IQ80332 PCI. @@ -143,7 +139,7 @@ MACHINE_START(IQ80332, "Intel IQ80332") .atag_offset = 0x100, .map_io = iop3xx_map_io, .init_irq = iop33x_init_irq, - .timer = &iq80332_timer, + .init_time = iq80332_timer_init, .init_machine = iq80332_init_machine, .restart = iop3xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c index 90e42e9982c..6beec150c06 100644 --- a/arch/arm/mach-ixp4xx/avila-setup.c +++ b/arch/arm/mach-ixp4xx/avila-setup.c @@ -167,7 +167,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = avila_init, #if defined(CONFIG_PCI) @@ -187,7 +187,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc Loft board") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = avila_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 8c0c0e2d072..1dbeb7c99d5 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -307,10 +307,6 @@ void __init ixp4xx_timer_init(void) ixp4xx_clockevent_init(); } -struct sys_timer ixp4xx_timer = { - .init = ixp4xx_timer_init, -}; - static struct pxa2xx_udc_mach_info ixp4xx_udc_info; void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info) @@ -523,22 +519,15 @@ static struct clock_event_device clockevent_ixp4xx = { .name = "ixp4xx timer1", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .rating = 200, - .shift = 24, .set_mode = ixp4xx_set_mode, .set_next_event = ixp4xx_set_next_event, }; static void __init ixp4xx_clockevent_init(void) { - clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC, - clockevent_ixp4xx.shift); - clockevent_ixp4xx.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx); - clockevent_ixp4xx.min_delta_ns = - clockevent_delta2ns(0xf, &clockevent_ixp4xx); clockevent_ixp4xx.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_ixp4xx); + clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ, + 0xf, 0xfffffffe); } void ixp4xx_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c index 1b83110028d..820cae8608f 100644 --- a/arch/arm/mach-ixp4xx/coyote-setup.c +++ b/arch/arm/mach-ixp4xx/coyote-setup.c @@ -112,7 +112,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = coyote_init, #if defined(CONFIG_PCI) @@ -132,7 +132,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = coyote_init, .restart = ixp4xx_restart, diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index 97a0af8f195..5d413f8c570 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -226,10 +226,6 @@ static void __init dsmg600_timer_init(void) ixp4xx_timer_init(); } -static struct sys_timer dsmg600_timer = { - .init = dsmg600_timer_init, -}; - static void __init dsmg600_init(void) { ixp4xx_sys_init(); @@ -282,7 +278,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &dsmg600_timer, + .init_time = dsmg600_timer_init, .init_machine = dsmg600_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c index 9175a25a751..429966b756e 100644 --- a/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/arch/arm/mach-ixp4xx/fsg-setup.c @@ -272,7 +272,7 @@ MACHINE_START(FSG, "Freecom FSG-3") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = fsg_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c index 033c7175895..3d24b3fcee8 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-setup.c +++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c @@ -99,7 +99,7 @@ MACHINE_START(GATEWAY7001, "Gateway 7001 AP") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = gateway7001_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index 53b8348dfcc..e54ff491c10 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -498,7 +498,7 @@ MACHINE_START(GORAMO_MLR, "MultiLink") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = gmlr_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 18ebc6be796..16a12994fb5 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c @@ -167,7 +167,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = gtwx5715_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h index 5bce94aacca..db5afb69c12 100644 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h @@ -89,8 +89,6 @@ struct ixp4xx_pata_data { void __iomem *cs1; }; -struct sys_timer; - #define IXP4XX_ETH_NPEA 0x00 #define IXP4XX_ETH_NPEB 0x10 #define IXP4XX_ETH_NPEC 0x20 @@ -125,7 +123,6 @@ extern void ixp4xx_init_early(void); extern void ixp4xx_init_irq(void); extern void ixp4xx_sys_init(void); extern void ixp4xx_timer_init(void); -extern struct sys_timer ixp4xx_timer; extern void ixp4xx_restart(char, const char *); extern void ixp4xx_pci_preinit(void); struct pci_sys_data; diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h index eb945a926d0..7b25c0225e4 100644 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -53,6 +53,4 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) */ #define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() - #endif diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 108a9d3f382..22d688b7d51 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -252,7 +252,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) @@ -268,7 +268,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) @@ -283,7 +283,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) @@ -298,7 +298,7 @@ MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = ixdp425_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 33cb0955b6b..ed667ce9f57 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -317,7 +317,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .init_machine = nas100d_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index e2903faaebb..7e55236c26e 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -232,10 +232,6 @@ static void __init nslu2_timer_init(void) ixp4xx_timer_init(); } -static struct sys_timer nslu2_timer = { - .init = nslu2_timer_init, -}; - static void __init nslu2_init(void) { uint8_t __iomem *f; @@ -303,7 +299,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &nslu2_timer, + .init_time = nslu2_timer_init, .init_machine = nslu2_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c index 158ddb79821..46a89f5e826 100644 --- a/arch/arm/mach-ixp4xx/omixp-setup.c +++ b/arch/arm/mach-ixp4xx/omixp-setup.c @@ -245,7 +245,7 @@ MACHINE_START(DEVIXP, "Omicron DEVIXP") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .init_machine = omixp_init, .restart = ixp4xx_restart, MACHINE_END @@ -257,7 +257,7 @@ MACHINE_START(MICCPT, "Omicron MICCPT") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .init_machine = omixp_init, #if defined(CONFIG_PCI) .dma_zone_size = SZ_64M, @@ -272,7 +272,7 @@ MACHINE_START(MIC256, "Omicron MIC256") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .init_machine = omixp_init, .restart = ixp4xx_restart, MACHINE_END diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c index 2798f435aaf..d42730a1d4a 100644 --- a/arch/arm/mach-ixp4xx/vulcan-setup.c +++ b/arch/arm/mach-ixp4xx/vulcan-setup.c @@ -239,7 +239,7 @@ MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = vulcan_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c index a785175b115..8f9ea2f3a9a 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-setup.c +++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c @@ -100,7 +100,7 @@ MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2") .map_io = ixp4xx_map_io, .init_early = ixp4xx_init_early, .init_irq = ixp4xx_init_irq, - .timer = &ixp4xx_timer, + .init_time = ixp4xx_timer_init, .atag_offset = 0x100, .init_machine = wg302v2_init, #if defined(CONFIG_PCI) diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index de4fd2bb1e2..d4af5c191c2 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -183,7 +183,7 @@ DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = orion_dt_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .init_machine = kirkwood_dt_init, .restart = kirkwood_restart, .dt_compat = kirkwood_dt_board_compat, diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c index 9f6f496380d..9a857ae8398 100644 --- a/arch/arm/mach-kirkwood/board-ib62x0.c +++ b/arch/arm/mach-kirkwood/board-ib62x0.c @@ -14,7 +14,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/mv643xx_eth.h> -#include <linux/input.h> #include "common.h" static struct mv643xx_eth_platform_data ib62x0_ge00_data = { diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c index 56bfe5a1605..3264925b831 100644 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ b/arch/arm/mach-kirkwood/board-mplcec4.c @@ -14,7 +14,6 @@ #include <linux/mv643xx_eth.h> #include <linux/platform_data/mmc-mvsdio.h> #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data mplcec4_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(1), diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c index f58d2e1a404..970174ad4a7 100644 --- a/arch/arm/mach-kirkwood/board-nsa310.c +++ b/arch/arm/mach-kirkwood/board-nsa310.c @@ -10,12 +10,10 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/i2c.h> #include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> +#include <linux/i2c.h> #include <mach/kirkwood.h> +#include <linux/of.h> #include "common.h" #include "mpp.h" @@ -79,14 +77,10 @@ static void __init nsa310_gpio_init(void) void __init nsa310_init(void) { - u32 dev, rev; - kirkwood_mpp_conf(nsa310_mpp_config); nsa310_gpio_init(); - kirkwood_pcie_id(&dev, &rev); - i2c_register_board_info(0, ARRAY_AND_SIZE(nsa310_i2c_info)); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index bac21a554c9..b5ad4dff6b1 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -530,7 +530,7 @@ static int __init kirkwood_find_tclk(void) return 166666667; } -static void __init kirkwood_timer_init(void) +void __init kirkwood_timer_init(void) { kirkwood_tclk = kirkwood_find_tclk(); @@ -538,10 +538,6 @@ static void __init kirkwood_timer_init(void) IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); } -struct sys_timer kirkwood_timer = { - .init = kirkwood_timer_init, -}; - /***************************************************************************** * Audio ****************************************************************************/ diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 5ffa57f08c8..283ab611e8d 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -156,7 +156,7 @@ void kirkwood_xor1_init(void); void kirkwood_crypto_init(void); extern int kirkwood_tclk; -extern struct sys_timer kirkwood_timer; +extern void kirkwood_timer_init(void); #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c index 2c1a453df20..453418063c1 100644 --- a/arch/arm/mach-kirkwood/d2net_v2-setup.c +++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c @@ -226,6 +226,6 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index c49b177c152..5a369fe7475 100644 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -103,6 +103,6 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c index 791a98fafa2..060ccf9cb63 100644 --- a/arch/arm/mach-kirkwood/dockstar-setup.c +++ b/arch/arm/mach-kirkwood/dockstar-setup.c @@ -19,7 +19,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/kirkwood.h> -#include <linux/platform_data/mmc-mvsdio.h> #include "common.h" #include "mpp.h" @@ -107,6 +106,6 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c index 7cb55f98224..1c6e736cbbf 100644 --- a/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/arch/arm/mach-kirkwood/guruplug-setup.c @@ -126,6 +126,6 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/include/mach/uncompress.h b/arch/arm/mach-kirkwood/include/mach/uncompress.h index 75d5497df3a..5bca5534021 100644 --- a/arch/arm/mach-kirkwood/include/mach/uncompress.h +++ b/arch/arm/mach-kirkwood/include/mach/uncompress.h @@ -44,4 +44,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c index 6d8364a9781..ba384b992be 100644 --- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c +++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c @@ -167,6 +167,6 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index 728e86d33f0..3b706611da8 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -263,7 +263,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif @@ -275,7 +275,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif @@ -287,7 +287,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c index a3b091470b8..913d032cdb1 100644 --- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c +++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -404,7 +404,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif @@ -416,7 +416,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index 7e81e9b586b..8ddd69fdc93 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -221,7 +221,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif @@ -234,7 +234,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif @@ -247,7 +247,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index 19072c84008..e4fd3129d36 100644 --- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -84,6 +84,6 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index 9717101a743..c7d93b48926 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -120,6 +120,6 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index 8a175948b28..55b68fa39f4 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -143,7 +143,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif @@ -155,7 +155,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END #endif diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c index f2daf711e72..8736f8c9751 100644 --- a/arch/arm/mach-kirkwood/t5325-setup.c +++ b/arch/arm/mach-kirkwood/t5325-setup.c @@ -211,6 +211,6 @@ MACHINE_START(T5325, "HP t5325 Thin Client") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index 73e2b6ca956..283abff9022 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -137,6 +137,6 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index e4c61279ea8..81d585806b2 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -181,6 +181,6 @@ MACHINE_START(TS41X, "QNAP TS-41x") .map_io = kirkwood_map_io, .init_early = kirkwood_init_early, .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, + .init_time = kirkwood_timer_init, .restart = kirkwood_restart, MACHINE_END diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c index b0c306ccbc6..456d6386edf 100644 --- a/arch/arm/mach-ks8695/board-acs5k.c +++ b/arch/arm/mach-ks8695/board-acs5k.c @@ -227,6 +227,6 @@ MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = acs5k_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c index e0d36cef2c5..d37c218c358 100644 --- a/arch/arm/mach-ks8695/board-dsm320.c +++ b/arch/arm/mach-ks8695/board-dsm320.c @@ -125,6 +125,6 @@ MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = dsm320_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c index a8270725b76..3acbdfd3139 100644 --- a/arch/arm/mach-ks8695/board-micrel.c +++ b/arch/arm/mach-ks8695/board-micrel.c @@ -57,6 +57,6 @@ MACHINE_START(KS8695, "KS8695 Centaur Development Board") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = micrel_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END diff --git a/arch/arm/mach-ks8695/board-og.c b/arch/arm/mach-ks8695/board-og.c index 1623ba461e4..002bc619bb6 100644 --- a/arch/arm/mach-ks8695/board-og.c +++ b/arch/arm/mach-ks8695/board-og.c @@ -145,7 +145,7 @@ MACHINE_START(CM4002, "OpenGear/CM4002") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = og_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif @@ -157,7 +157,7 @@ MACHINE_START(CM4008, "OpenGear/CM4008") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = og_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif @@ -169,7 +169,7 @@ MACHINE_START(CM41XX, "OpenGear/CM41xx") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = og_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif @@ -181,7 +181,7 @@ MACHINE_START(IM4004, "OpenGear/IM4004") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = og_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif @@ -193,7 +193,7 @@ MACHINE_START(IM42XX, "OpenGear/IM42xx") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = og_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ks8695/board-sg.c b/arch/arm/mach-ks8695/board-sg.c index f35b98b5bf3..fdf2352d2cf 100644 --- a/arch/arm/mach-ks8695/board-sg.c +++ b/arch/arm/mach-ks8695/board-sg.c @@ -91,7 +91,7 @@ MACHINE_START(LITE300, "SecureComputing/SG300") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = sg_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif @@ -103,7 +103,7 @@ MACHINE_START(SG310, "McAfee/SG310") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = sg_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif @@ -115,7 +115,7 @@ MACHINE_START(SE4200, "SecureComputing/SE4200") .map_io = ks8695_map_io, .init_irq = ks8695_init_irq, .init_machine = sg_init, - .timer = &ks8695_timer, + .init_time = ks8695_timer_init, .restart = ks8695_restart, MACHINE_END #endif diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h index f8bdb11a9c3..6e97ce462d7 100644 --- a/arch/arm/mach-ks8695/generic.h +++ b/arch/arm/mach-ks8695/generic.h @@ -13,4 +13,4 @@ extern __init void ks8695_map_io(void); extern __init void ks8695_init_irq(void); extern void ks8695_restart(char, const char *); -extern struct sys_timer ks8695_timer; +extern void ks8695_timer_init(void); diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h index 8879d610308..c089a1aea67 100644 --- a/arch/arm/mach-ks8695/include/mach/uncompress.h +++ b/arch/arm/mach-ks8695/include/mach/uncompress.h @@ -32,6 +32,5 @@ static inline void flush(void) } #define arch_decomp_setup() -#define arch_decomp_wdog() #endif diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c index 46c84bc7792..c272a3863d5 100644 --- a/arch/arm/mach-ks8695/time.c +++ b/arch/arm/mach-ks8695/time.c @@ -146,7 +146,7 @@ static void ks8695_timer_setup(void) 0xFFFFFFFFU); } -static void __init ks8695_timer_init (void) +void __init ks8695_timer_init(void) { ks8695_timer_setup(); @@ -154,10 +154,6 @@ static void __init ks8695_timer_init (void) setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq); } -struct sys_timer ks8695_timer = { - .init = ks8695_timer_init, -}; - void ks8695_restart(char mode, const char *cmd) { unsigned int reg; diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index afeac3b1fae..e0b26062a27 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -25,7 +25,7 @@ /* * Other arch specific structures and functions */ -extern struct sys_timer lpc32xx_timer; +extern void lpc32xx_timer_init(void); extern void __init lpc32xx_init_irq(void); extern void __init lpc32xx_map_io(void); extern void __init lpc32xx_serial_init(void); diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h index c142487d299..1198a89183c 100644 --- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h +++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h @@ -55,6 +55,5 @@ static inline void flush(void) /* NULL functions; we don't presently need them */ #define arch_decomp_setup() -#define arch_decomp_wdog() #endif diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index e8ff4c3f056..c1cd5a943ab 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -263,7 +263,7 @@ DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)") .atag_offset = 0x100, .map_io = lpc32xx_map_io, .init_irq = lpc32xx_init_irq, - .timer = &lpc32xx_timer, + .init_time = lpc32xx_timer_init, .init_machine = lpc3250_machine_init, .dt_compat = lpc32xx_dt_compat, .restart = lpc23xx_restart, diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index c40667c3316..20eab63d10b 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -70,7 +70,6 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode, static struct clock_event_device lpc32xx_clkevt = { .name = "lpc32xx_clkevt", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 300, .set_next_event = lpc32xx_clkevt_next_event, .set_mode = lpc32xx_clkevt_mode, @@ -100,7 +99,7 @@ static struct irqaction lpc32xx_timer_irq = { * clocks need to be enabled here manually and then tagged as used in * the clock driver initialization */ -static void __init lpc32xx_timer_init(void) +void __init lpc32xx_timer_init(void) { u32 clkrate, pllreg; @@ -141,14 +140,8 @@ static void __init lpc32xx_timer_init(void) setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); /* Setup the clockevent structure. */ - lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC, - lpc32xx_clkevt.shift); - lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1, - &lpc32xx_clkevt); - lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1, - &lpc32xx_clkevt) + 1; lpc32xx_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&lpc32xx_clkevt); + clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1); /* Use timer1 as clock source. */ __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, @@ -161,8 +154,3 @@ static void __init lpc32xx_timer_init(void) clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE), "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up); } - -struct sys_timer lpc32xx_timer = { - .init = &lpc32xx_timer_init, -}; - diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index e5dba9c5dc5..9f64d5632e0 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -262,7 +262,7 @@ MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") .map_io = mmp_map_io, .nr_irqs = MMP_NR_IRQS, .init_irq = pxa168_init_irq, - .timer = &pxa168_timer, + .init_time = pxa168_timer_init, .init_machine = common_init, .restart = pxa168_restart, MACHINE_END @@ -271,7 +271,7 @@ MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") .map_io = mmp_map_io, .nr_irqs = MMP_NR_IRQS, .init_irq = pxa168_init_irq, - .timer = &pxa168_timer, + .init_time = pxa168_timer_init, .init_machine = common_init, .restart = pxa168_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c index 603542ae6fb..1f94957b56a 100644 --- a/arch/arm/mach-mmp/avengers_lite.c +++ b/arch/arm/mach-mmp/avengers_lite.c @@ -45,7 +45,7 @@ MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") .map_io = mmp_map_io, .nr_irqs = MMP_NR_IRQS, .init_irq = pxa168_init_irq, - .timer = &pxa168_timer, + .init_time = pxa168_timer_init, .init_machine = avengers_lite_init, .restart = pxa168_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c index 5cb769cd26d..2358011c7d8 100644 --- a/arch/arm/mach-mmp/brownstone.c +++ b/arch/arm/mach-mmp/brownstone.c @@ -218,7 +218,7 @@ MACHINE_START(BROWNSTONE, "Brownstone Development Platform") .map_io = mmp_map_io, .nr_irqs = BROWNSTONE_NR_IRQS, .init_irq = mmp2_init_irq, - .timer = &mmp2_timer, + .init_time = mmp2_timer_init, .init_machine = brownstone_init, .restart = mmp_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index bd453274fca..0bdc50b134c 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -1,7 +1,5 @@ #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) -struct sys_timer; - extern void timer_init(int irq); extern void __init icu_init_irq(void); diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c index 8059cc0905c..754c352dd02 100644 --- a/arch/arm/mach-mmp/flint.c +++ b/arch/arm/mach-mmp/flint.c @@ -121,7 +121,7 @@ MACHINE_START(FLINT, "Flint Development Platform") .map_io = mmp_map_io, .nr_irqs = FLINT_NR_IRQS, .init_irq = mmp2_init_irq, - .timer = &mmp2_timer, + .init_time = mmp2_timer_init, .init_machine = flint_init, .restart = mmp_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c index 5c3d61ee729..d1e2d595e79 100644 --- a/arch/arm/mach-mmp/gplugd.c +++ b/arch/arm/mach-mmp/gplugd.c @@ -194,7 +194,7 @@ MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform") .map_io = mmp_map_io, .nr_irqs = MMP_NR_IRQS, .init_irq = pxa168_init_irq, - .timer = &pxa168_timer, + .init_time = pxa168_timer_init, .init_machine = gplugd_init, .restart = pxa168_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index c4ca4d17194..0764f4ecec8 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -3,9 +3,7 @@ #include <linux/platform_data/pxa_sdhci.h> -struct sys_timer; - -extern struct sys_timer mmp2_timer; +extern void mmp2_timer_init(void); extern void __init mmp2_init_icu(void); extern void __init mmp2_init_irq(void); extern void mmp2_clear_pmic_int(void); diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 37632d964d5..7ed1df21ea1 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -1,9 +1,7 @@ #ifndef __ASM_MACH_PXA168_H #define __ASM_MACH_PXA168_H -struct sys_timer; - -extern struct sys_timer pxa168_timer; +extern void pxa168_timer_init(void); extern void __init pxa168_init_irq(void); extern void pxa168_restart(char, const char *); extern void pxa168_clear_keypad_wakeup(void); diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index 3b58a3b2d7d..eff31ab6dc3 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -1,9 +1,7 @@ #ifndef __ASM_MACH_PXA910_H #define __ASM_MACH_PXA910_H -struct sys_timer; - -extern struct sys_timer pxa910_timer; +extern void pxa910_timer_init(void); extern void __init pxa910_init_irq(void); #include <linux/i2c.h> diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h index d6daeb7e4ef..8890fa8fa77 100644 --- a/arch/arm/mach-mmp/include/mach/uncompress.h +++ b/arch/arm/mach-mmp/include/mach/uncompress.h @@ -43,9 +43,3 @@ static inline void arch_decomp_setup(void) if (machine_is_avengers_lite()) UART = (unsigned long *)UART3_BASE; } - -/* - * nothing to do - */ - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c index ff73249884d..66634fd0ecb 100644 --- a/arch/arm/mach-mmp/jasper.c +++ b/arch/arm/mach-mmp/jasper.c @@ -174,7 +174,7 @@ MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") .map_io = mmp_map_io, .nr_irqs = JASPER_NR_IRQS, .init_irq = mmp2_init_irq, - .timer = &mmp2_timer, + .init_time = mmp2_timer_init, .init_machine = jasper_init, .restart = mmp_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c index 033cc31b3c7..d063efa0a4f 100644 --- a/arch/arm/mach-mmp/mmp-dt.c +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -22,10 +22,6 @@ extern void __init mmp_dt_irq_init(void); extern void __init mmp_dt_init_timer(void); -static struct sys_timer mmp_dt_timer = { - .init = mmp_dt_init_timer, -}; - static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL), OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL), @@ -69,7 +65,7 @@ static const char *mmp_dt_board_compat[] __initdata = { DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") .map_io = mmp_map_io, .init_irq = mmp_dt_irq_init, - .timer = &mmp_dt_timer, + .init_time = mmp_dt_init_timer, .init_machine = pxa168_dt_init, .dt_compat = mmp_dt_board_compat, MACHINE_END @@ -77,7 +73,7 @@ MACHINE_END DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") .map_io = mmp_map_io, .init_irq = mmp_dt_irq_init, - .timer = &mmp_dt_timer, + .init_time = mmp_dt_init_timer, .init_machine = pxa910_dt_init, .dt_compat = mmp_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c index 535a5ed5977..fad431aa6e0 100644 --- a/arch/arm/mach-mmp/mmp2-dt.c +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -24,10 +24,6 @@ extern void __init mmp_dt_irq_init(void); extern void __init mmp_dt_init_timer(void); -static struct sys_timer mmp_dt_timer = { - .init = mmp_dt_init_timer, -}; - static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL), OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL), @@ -54,7 +50,7 @@ static const char *mmp2_dt_board_compat[] __initdata = { DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") .map_io = mmp_map_io, .init_irq = mmp_dt_irq_init, - .timer = &mmp_dt_timer, + .init_time = mmp_dt_init_timer, .init_machine = mmp2_dt_init, .dt_compat = mmp2_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 3a3768c7a19..d94d114eef7 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -114,7 +114,7 @@ postcore_initcall(mmp2_init); #define APBC_TIMERS APBC_REG(0x024) -static void __init mmp2_timer_init(void) +void __init mmp2_timer_init(void) { unsigned long clk_rst; @@ -130,10 +130,6 @@ static void __init mmp2_timer_init(void) timer_init(IRQ_MMP2_TIMER1); } -struct sys_timer mmp2_timer = { - .init = mmp2_timer_init, -}; - /* on-chip devices */ MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index b7f074f1549..9bc7b86a86a 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -67,7 +67,7 @@ postcore_initcall(pxa168_init); #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) #define APBC_TIMERS APBC_REG(0x34) -static void __init pxa168_timer_init(void) +void __init pxa168_timer_init(void) { /* this is early, we have to initialize the CCU registers by * ourselves instead of using clk_* API. Clock rate is defined @@ -81,10 +81,6 @@ static void __init pxa168_timer_init(void) timer_init(IRQ_PXA168_TIMER1); } -struct sys_timer pxa168_timer = { - .init = pxa168_timer_init, -}; - void pxa168_clear_keypad_wakeup(void) { uint32_t val; diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 8b1e16fbb7a..c6a89f1eca4 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -101,7 +101,7 @@ postcore_initcall(pxa910_init); #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) #define APBC_TIMERS APBC_REG(0x34) -static void __init pxa910_timer_init(void) +void __init pxa910_timer_init(void) { /* reset and configure */ __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); @@ -110,10 +110,6 @@ static void __init pxa910_timer_init(void) timer_init(IRQ_PXA910_AP1_TIMER1); } -struct sys_timer pxa910_timer = { - .init = pxa910_timer_init, -}; - /* on-chip devices */ /* NOTE: there are totally 3 UARTs on PXA910: diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c index b28f9084dff..4c127d23955 100644 --- a/arch/arm/mach-mmp/tavorevb.c +++ b/arch/arm/mach-mmp/tavorevb.c @@ -103,7 +103,7 @@ MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)") .map_io = mmp_map_io, .nr_irqs = MMP_NR_IRQS, .init_irq = pxa910_init_irq, - .timer = &pxa910_timer, + .init_time = pxa910_timer_init, .init_machine = tavorevb_init, .restart = mmp_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c index dd30ea74785..8609967975e 100644 --- a/arch/arm/mach-mmp/teton_bga.c +++ b/arch/arm/mach-mmp/teton_bga.c @@ -86,7 +86,7 @@ MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform") .map_io = mmp_map_io, .nr_irqs = MMP_NR_IRQS, .init_irq = pxa168_init_irq, - .timer = &pxa168_timer, + .init_time = pxa168_timer_init, .init_machine = teton_bga_init, .restart = pxa168_restart, MACHINE_END diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 936447c7097..86a18b3d252 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -141,7 +141,6 @@ static void timer_set_mode(enum clock_event_mode mode, static struct clock_event_device ckevt = { .name = "clockevent", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_next_event = timer_set_next_event, .set_mode = timer_set_mode, @@ -198,15 +197,13 @@ void __init timer_init(int irq) setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); - ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); - ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); - ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); ckevt.cpumask = cpumask_of(0); setup_irq(irq, &timer_irq); clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); - clockevents_register_device(&ckevt); + clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE, + MIN_DELTA, MAX_DELTA); } #ifdef CONFIG_OF diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index ce55fd8821c..6e474900b13 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -218,7 +218,7 @@ MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") .map_io = mmp_map_io, .nr_irqs = TTCDKB_NR_IRQS, .init_irq = pxa910_init_irq, - .timer = &pxa910_timer, + .init_time = pxa910_timer_init, .init_machine = ttc_dkb_init, .restart = mmp_restart, MACHINE_END diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c index b5b4de2cdf9..7dcfc5300bb 100644 --- a/arch/arm/mach-msm/board-dt-8660.c +++ b/arch/arm/mach-msm/board-dt-8660.c @@ -11,26 +11,15 @@ */ #include <linux/init.h> +#include <linux/irqchip.h> #include <linux/of.h> -#include <linux/of_irq.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <mach/board.h> #include "common.h" -static const struct of_device_id msm_dt_gic_match[] __initconst = { - { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, - {} -}; - -static void __init msm8x60_init_irq(void) -{ - of_irq_init(msm_dt_gic_match); -} - static void __init msm8x60_init_late(void) { smd_debugfs_init(); @@ -55,10 +44,9 @@ static const char *msm8x60_fluid_match[] __initdata = { DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8x60_io, - .init_irq = msm8x60_init_irq, - .handle_irq = gic_handle_irq, + .init_irq = irqchip_init, .init_machine = msm8x60_dt_init, .init_late = msm8x60_init_late, - .timer = &msm_dt_timer, + .init_time = msm_dt_timer_init, .dt_compat = msm8x60_fluid_match, MACHINE_END diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c index 4490edb71c1..73019363ffa 100644 --- a/arch/arm/mach-msm/board-dt-8960.c +++ b/arch/arm/mach-msm/board-dt-8960.c @@ -11,24 +11,13 @@ */ #include <linux/init.h> -#include <linux/of_irq.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include "common.h" -static const struct of_device_id msm_dt_gic_match[] __initconst = { - { .compatible = "qcom,msm-qgic2", .data = gic_of_init }, - { } -}; - -static void __init msm_dt_init_irq(void) -{ - of_irq_init(msm_dt_gic_match); -} - static void __init msm_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -42,9 +31,8 @@ static const char * const msm8960_dt_match[] __initconst = { DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8960_io, - .init_irq = msm_dt_init_irq, - .timer = &msm_dt_timer, + .init_irq = irqchip_init, + .init_time = msm_dt_timer_init, .init_machine = msm_dt_init, .dt_compat = msm8960_dt_match, - .handle_irq = gic_handle_irq, MACHINE_END diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 6ce542e2e21..84d720af34a 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -106,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") .init_irq = halibut_init_irq, .init_machine = halibut_init, .init_late = halibut_init_late, - .timer = &msm7x01_timer, + .init_time = msm7x01_timer_init, MACHINE_END diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c index df00bc03ce7..30c3496db59 100644 --- a/arch/arm/mach-msm/board-mahimahi.c +++ b/arch/arm/mach-msm/board-mahimahi.c @@ -75,7 +75,7 @@ static void __init mahimahi_init_late(void) smd_debugfs_init(); } -extern struct sys_timer msm_timer; +void msm_timer_init(void); MACHINE_START(MAHIMAHI, "mahimahi") .atag_offset = 0x100, @@ -84,5 +84,5 @@ MACHINE_START(MAHIMAHI, "mahimahi") .init_irq = msm_init_irq, .init_machine = mahimahi_init, .init_late = mahimahi_init_late, - .timer = &msm_timer, + .init_time = msm_timer_init, MACHINE_END diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index effa6f4336c..7bc3f82e3ec 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -131,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm7x30_timer, + .init_time = msm7x30_timer_init, MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") @@ -142,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm7x30_timer, + .init_time = msm7x30_timer_init, MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") @@ -153,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, .init_late = msm7x30_init_late, - .timer = &msm7x30_timer, + .init_time = msm7x30_timer_init, MACHINE_END diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 2448fcf09eb..686e7949a73 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -200,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, .init_late = qsd8x50_init_late, - .timer = &qsd8x50_timer, + .init_time = qsd8x50_timer_init, MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") @@ -209,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, .init_late = qsd8x50_init_late, - .timer = &qsd8x50_timer, + .init_time = qsd8x50_timer_init, MACHINE_END diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index b7b0fc7e327..70730111b37 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -53,7 +53,7 @@ static struct platform_device *devices[] __initdata = { &msm_device_uart3, }; -extern struct sys_timer msm_timer; +void msm_timer_init(void); static void __init sapphire_init_irq(void) { @@ -113,5 +113,5 @@ MACHINE_START(SAPPHIRE, "sapphire") .init_irq = sapphire_init_irq, .init_machine = sapphire_init, .init_late = sapphire_init_late, - .timer = &msm_timer, + .init_time = msm_timer_init, MACHINE_END diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 4ba0800e243..919bfa32871 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -110,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream") .init_irq = trout_init_irq, .init_machine = trout_init, .init_late = trout_init_late, - .timer = &msm7x01_timer, + .init_time = msm7x01_timer_init, MACHINE_END diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h index 633a7159d5f..ce8215a269e 100644 --- a/arch/arm/mach-msm/common.h +++ b/arch/arm/mach-msm/common.h @@ -12,10 +12,10 @@ #ifndef __MACH_COMMON_H #define __MACH_COMMON_H -extern struct sys_timer msm7x01_timer; -extern struct sys_timer msm7x30_timer; -extern struct sys_timer msm_dt_timer; -extern struct sys_timer qsd8x50_timer; +extern void msm7x01_timer_init(void); +extern void msm7x30_timer_init(void); +extern void msm_dt_timer_init(void); +extern void qsd8x50_timer_init(void); extern void msm_map_common_io(void); extern void msm_map_msm7x30_io(void); diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h index c14011fe832..fa97a10d869 100644 --- a/arch/arm/mach-msm/include/mach/uncompress.h +++ b/arch/arm/mach-msm/include/mach/uncompress.h @@ -60,8 +60,4 @@ static inline void arch_decomp_setup(void) { } -static inline void arch_decomp_wdog(void) -{ -} - #endif diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 7ed69b69c87..42932865416 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -15,8 +15,8 @@ #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> -#include <asm/hardware/gic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> #include <asm/mach-types.h> @@ -115,7 +115,7 @@ static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *id * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - gic_raise_softirq(cpumask_of(cpu), 0); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -153,8 +153,6 @@ static void __init msm_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init msm_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-msm/proc_comm.h b/arch/arm/mach-msm/proc_comm.h index 12da4cacd4a..e8d043a0e99 100644 --- a/arch/arm/mach-msm/proc_comm.h +++ b/arch/arm/mach-msm/proc_comm.h @@ -253,6 +253,6 @@ enum { (((drvstr) & 0xF) << 17)) int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2); -void __init proc_comm_boot_wait(void); +void proc_comm_boot_wait(void); #endif diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 476549a8a70..2969027f02f 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -25,7 +25,6 @@ #include <linux/of_irq.h> #include <asm/mach/time.h> -#include <asm/hardware/gic.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> @@ -144,13 +143,9 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) evt->rating = msm_clockevent.rating; evt->set_mode = msm_timer_set_mode; evt->set_next_event = msm_timer_set_next_event; - evt->shift = msm_clockevent.shift; - evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt); - evt->min_delta_ns = clockevent_delta2ns(4, evt); *__this_cpu_ptr(msm_evt.percpu_evt) = evt; - clockevents_register_device(evt); + clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000); enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); return 0; } @@ -229,7 +224,7 @@ static const struct of_device_id msm_gpt_match[] __initconst = { { }, }; -static void __init msm_dt_timer_init(void) +void __init msm_dt_timer_init(void) { struct device_node *np; u32 freq; @@ -296,10 +291,6 @@ static void __init msm_dt_timer_init(void) msm_timer_init(freq, 32, irq, !!percpu_offset); } - -struct sys_timer msm_dt_timer = { - .init = msm_dt_timer_init -}; #endif static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) @@ -317,7 +308,7 @@ static int __init msm_timer_map(phys_addr_t event, phys_addr_t source) return 0; } -static void __init msm7x01_timer_init(void) +void __init msm7x01_timer_init(void) { struct clocksource *cs = &msm_clocksource; @@ -330,28 +321,16 @@ static void __init msm7x01_timer_init(void) false); } -struct sys_timer msm7x01_timer = { - .init = msm7x01_timer_init -}; - -static void __init msm7x30_timer_init(void) +void __init msm7x30_timer_init(void) { if (msm_timer_map(0xc0100004, 0xc0100024)) return; msm_timer_init(24576000 / 4, 32, 1, false); } -struct sys_timer msm7x30_timer = { - .init = msm7x30_timer_init -}; - -static void __init qsd8x50_timer_init(void) +void __init qsd8x50_timer_init(void) { if (msm_timer_map(0xAC100000, 0xAC100010)) return; msm_timer_init(19200000 / 4, 32, 7, false); } - -struct sys_timer qsd8x50_timer = { - .init = qsd8x50_timer_init -}; diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c index ee74ec97c14..1f2ef98b37c 100644 --- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -150,6 +150,6 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, + .init_time = mv78xx0_timer_init, .restart = mv78xx0_restart, MACHINE_END diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index d0cb4857b4b..0efa14498eb 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -336,16 +336,12 @@ void __init mv78xx0_init_early(void) orion_time_set_base(TIMER_VIRT_BASE); } -static void __init_refok mv78xx0_timer_init(void) +void __init_refok mv78xx0_timer_init(void) { orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } -struct sys_timer mv78xx0_timer = { - .init = mv78xx0_timer_init, -}; - /***************************************************************************** * General diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 507c767d49e..5e9485bad0a 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h @@ -47,7 +47,7 @@ void mv78xx0_uart3_init(void); void mv78xx0_i2c_init(void); void mv78xx0_restart(char, const char *); -extern struct sys_timer mv78xx0_timer; +extern void mv78xx0_timer_init(void); #endif diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 4d6d48bf51e..4e0f22b30bc 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c @@ -98,6 +98,6 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, + .init_time = mv78xx0_timer_init, .restart = mv78xx0_restart, MACHINE_END diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h index 365264298e7..6a761c44a29 100644 --- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h +++ b/arch/arm/mach-mv78xx0/include/mach/uncompress.h @@ -44,4 +44,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c index 9a882706e13..d2d06f3957f 100644 --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c @@ -83,6 +83,6 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, + .init_time = mv78xx0_timer_init, .restart = mv78xx0_restart, MACHINE_END diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 99df4df680f..da93bcbc74c 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -3,7 +3,8 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a -obj-y += system-controller.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o +obj-y += system-controller.o +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o +obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 7434b5e3619..a5ea616d6d1 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -56,10 +56,6 @@ void __init armada_370_xp_init_early(void) init_dma_coherent_pool_size(SZ_1M); } -struct sys_timer armada_370_xp_timer = { - .init = armada_370_xp_timer_and_clk_init, -}; - static void __init armada_370_xp_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -78,7 +74,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .init_early = armada_370_xp_init_early, .init_irq = armada_370_xp_init_irq, .handle_irq = armada_370_xp_handle_irq, - .timer = &armada_370_xp_timer, + .init_time = armada_370_xp_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, MACHINE_END diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h index ef281149544..533f5186e20 100644 --- a/arch/arm/mach-mxs/include/mach/uncompress.h +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -72,6 +72,5 @@ static inline void __arch_decomp_setup(unsigned long arch_id) } #define arch_decomp_setup() __arch_decomp_setup(arch_id) -#define arch_decomp_wdog() #endif /* __MACH_MXS_UNCOMPRESS_H__ */ diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index c66129b5dd1..5fad7cefe8a 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -163,19 +163,11 @@ static void __init imx23_timer_init(void) mx23_clocks_init(); } -static struct sys_timer imx23_timer = { - .init = imx23_timer_init, -}; - static void __init imx28_timer_init(void) { mx28_clocks_init(); } -static struct sys_timer imx28_timer = { - .init = imx28_timer_init, -}; - enum mac_oui { OUI_FSL, OUI_DENX, @@ -446,7 +438,7 @@ DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)") .map_io = mx23_map_io, .init_irq = icoll_init_irq, .handle_irq = icoll_handle_irq, - .timer = &imx23_timer, + .init_time = imx23_timer_init, .init_machine = mxs_machine_init, .dt_compat = imx23_dt_compat, .restart = mxs_restart, @@ -456,7 +448,7 @@ DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)") .map_io = mx28_map_io, .init_irq = icoll_init_irq, .handle_irq = icoll_handle_irq, - .timer = &imx28_timer, + .init_time = imx28_timer_init, .init_machine = mxs_machine_init, .dt_compat = imx28_dt_compat, .restart = mxs_restart, diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 856f4c79606..27451b1ba3f 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -195,7 +195,6 @@ static void mxs_set_mode(enum clock_event_mode mode, static struct clock_event_device mxs_clockevent_device = { .name = "mxs_timrot", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_mode = mxs_set_mode, .set_next_event = timrotv2_set_next_event, .rating = 200, @@ -203,25 +202,12 @@ static struct clock_event_device mxs_clockevent_device = { static int __init mxs_clockevent_init(struct clk *timer_clk) { - unsigned int c = clk_get_rate(timer_clk); - - mxs_clockevent_device.mult = - div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift); - mxs_clockevent_device.cpumask = cpumask_of(0); - if (timrot_is_v1()) { + if (timrot_is_v1()) mxs_clockevent_device.set_next_event = timrotv1_set_next_event; - mxs_clockevent_device.max_delta_ns = - clockevent_delta2ns(0xfffe, &mxs_clockevent_device); - mxs_clockevent_device.min_delta_ns = - clockevent_delta2ns(0xf, &mxs_clockevent_device); - } else { - mxs_clockevent_device.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device); - mxs_clockevent_device.min_delta_ns = - clockevent_delta2ns(0xf, &mxs_clockevent_device); - } - - clockevents_register_device(&mxs_clockevent_device); + mxs_clockevent_device.cpumask = cpumask_of(0); + clockevents_config_and_register(&mxs_clockevent_device, + clk_get_rate(timer_clk), 0xf, + timrot_is_v1() ? 0xfffe : 0xfffffffe); return 0; } diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index aa627465d91..27c2cb7ab81 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -23,9 +23,9 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/irqchip/arm-vic.h> #include <mach/hardware.h> #include <asm/mach/map.h> -#include <asm/hardware/vic.h> #include <mach/netx-regs.h> #include <asm/mach/irq.h> diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h index 9b915119b8d..768b26bbb42 100644 --- a/arch/arm/mach-netx/generic.h +++ b/arch/arm/mach-netx/generic.h @@ -21,5 +21,4 @@ extern void __init netx_map_io(void); extern void __init netx_init_irq(void); extern void netx_restart(char, const char *); -struct sys_timer; -extern struct sys_timer netx_timer; +extern void netx_timer_init(void); diff --git a/arch/arm/mach-netx/include/mach/uncompress.h b/arch/arm/mach-netx/include/mach/uncompress.h index 84f91284f61..5cb1051b583 100644 --- a/arch/arm/mach-netx/include/mach/uncompress.h +++ b/arch/arm/mach-netx/include/mach/uncompress.h @@ -73,4 +73,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c index 8b781ff7c9e..9b558eb3070 100644 --- a/arch/arm/mach-netx/nxdb500.c +++ b/arch/arm/mach-netx/nxdb500.c @@ -28,7 +28,6 @@ #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/vic.h> #include <mach/netx-regs.h> #include <linux/platform_data/eth-netx.h> @@ -204,8 +203,7 @@ MACHINE_START(NXDB500, "Hilscher nxdb500") .atag_offset = 0x100, .map_io = netx_map_io, .init_irq = netx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &netx_timer, + .init_time = netx_timer_init, .init_machine = nxdb500_init, .restart = netx_restart, MACHINE_END diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c index b26dbce334f..a5e86cd365e 100644 --- a/arch/arm/mach-netx/nxdkn.c +++ b/arch/arm/mach-netx/nxdkn.c @@ -28,7 +28,6 @@ #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/vic.h> #include <mach/netx-regs.h> #include <linux/platform_data/eth-netx.h> @@ -97,8 +96,7 @@ MACHINE_START(NXDKN, "Hilscher nxdkn") .atag_offset = 0x100, .map_io = netx_map_io, .init_irq = netx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &netx_timer, + .init_time = netx_timer_init, .init_machine = nxdkn_init, .restart = netx_restart, MACHINE_END diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c index 257382efafa..ad17885d015 100644 --- a/arch/arm/mach-netx/nxeb500hmi.c +++ b/arch/arm/mach-netx/nxeb500hmi.c @@ -28,7 +28,6 @@ #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/vic.h> #include <mach/netx-regs.h> #include <linux/platform_data/eth-netx.h> @@ -181,8 +180,7 @@ MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi") .atag_offset = 0x100, .map_io = netx_map_io, .init_irq = netx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &netx_timer, + .init_time = netx_timer_init, .init_machine = nxeb500hmi_init, .restart = netx_restart, MACHINE_END diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index e24c141ba48..6df42e64303 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c @@ -76,7 +76,6 @@ static int netx_set_next_event(unsigned long evt, static struct clock_event_device netx_clockevent = { .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), - .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = netx_set_next_event, .set_mode = netx_set_mode, @@ -107,7 +106,7 @@ static struct irqaction netx_timer_irq = { /* * Set up timer interrupt */ -static void __init netx_timer_init(void) +void __init netx_timer_init(void) { /* disable timer initially */ writel(0, NETX_GPIO_COUNTER_CTRL(0)); @@ -140,18 +139,9 @@ static void __init netx_timer_init(void) clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); - netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, - netx_clockevent.shift); - netx_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &netx_clockevent); /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. * Adding some safety ... */ - netx_clockevent.min_delta_ns = - clockevent_delta2ns(0xa00, &netx_clockevent); netx_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&netx_clockevent); + clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE, + 0xa00, 0xfffffffe); } - -struct sys_timer netx_timer = { - .init = netx_timer_init, -}; diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index 9f19069248d..aaed48d9437 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -27,7 +27,6 @@ #include <linux/pinctrl/machine.h> #include <linux/platform_data/pinctrl-nomadik.h> #include <linux/platform_data/clocksource-nomadik-mtu.h> -#include <asm/hardware/vic.h> #include <asm/sizes.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -267,10 +266,6 @@ static void __init nomadik_timer_init(void) nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE), IRQ_MTU0); } -static struct sys_timer nomadik_timer = { - .init = nomadik_timer_init, -}; - static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = { { I2C_BOARD_INFO("stw4811", 0x2d), @@ -352,8 +347,7 @@ MACHINE_START(NOMADIK, "NHK8815") .atag_offset = 0x100, .map_io = cpu8815_map_io, .init_irq = cpu8815_init_irq, - .handle_irq = vic_handle_irq, - .timer = &nomadik_timer, + .init_time = nomadik_timer_init, .init_machine = nhk8815_platform_init, .restart = cpu8815_restart, MACHINE_END diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 1273931303f..351404673f6 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -25,13 +25,13 @@ #include <linux/slab.h> #include <linux/irq.h> #include <linux/dma-mapping.h> +#include <linux/irqchip/arm-vic.h> #include <linux/platform_data/clk-nomadik.h> #include <linux/platform_data/pinctrl-nomadik.h> #include <mach/hardware.h> #include <mach/irqs.h> #include <asm/mach/map.h> -#include <asm/hardware/vic.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h index 7d4687e9cbd..f527af6527c 100644 --- a/arch/arm/mach-nomadik/include/mach/uncompress.h +++ b/arch/arm/mach-nomadik/include/mach/uncompress.h @@ -58,6 +58,4 @@ static inline void arch_decomp_setup(void) { } -#define arch_decomp_wdog() /* nothing to do here */ - #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 2e98a3ac7c5..2aab761ee68 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -628,6 +628,6 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") .init_irq = omap1_init_irq, .init_machine = ams_delta_init, .init_late = ams_delta_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 560a7dcf0a5..702d58039cc 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -364,6 +364,6 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") .init_irq = omap1_init_irq, .init_machine = omap_fsample_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 608e7d2a277..e1d9171774b 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -84,6 +84,6 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") .init_irq = omap1_init_irq, .init_machine = omap_generic_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 2274bd677ef..0dac3d239e3 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -461,6 +461,6 @@ MACHINE_START(OMAP_H2, "TI-H2") .init_irq = omap1_init_irq, .init_machine = h2_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 1051935f0aa..816ecd13f81 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -454,6 +454,6 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") .init_irq = omap1_init_irq, .init_machine = h3_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 356f816c84a..35a2379b986 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -603,6 +603,6 @@ MACHINE_START(HERALD, "HTC Herald") .init_irq = omap1_init_irq, .init_machine = htcherald_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index f8033fab0f8..bd5f02e9c35 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -458,6 +458,6 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") .init_irq = omap1_init_irq, .init_machine = innovator_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 24d2f2df11a..4695ca71770 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -242,6 +242,6 @@ MACHINE_START(NOKIA770, "Nokia 770") .init_irq = omap1_init_irq, .init_machine = omap_nokia770_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 872ea47cd28..a7ce6928668 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -609,6 +609,6 @@ MACHINE_START(OMAP_OSK, "TI-OSK") .init_irq = omap1_init_irq, .init_machine = osk_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index c33dceb4660..845a1a7aef9 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -268,6 +268,6 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") .init_irq = omap1_init_irq, .init_machine = omap_palmte_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 2948b0ee4be..65a4a3e357f 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -314,6 +314,6 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") .init_irq = omap1_init_irq, .init_machine = omap_palmtt_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 7a05895c0be..01c970071fd 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -330,6 +330,6 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") .init_irq = omap1_init_irq, .init_machine = omap_palmz71_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 27f8d12ec22..8b2f7127f71 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -326,6 +326,6 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") .init_irq = omap1_init_irq, .init_machine = omap_perseus2_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 20ed52ae171..9732a98f3e0 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -407,6 +407,6 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1") .init_irq = omap1_init_irq, .init_machine = omap_sx1_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = omap1_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index abf705f49b1..6c116e1a4b0 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -289,6 +289,6 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") .init_irq = omap1_init_irq, .init_machine = voiceblue_init, .init_late = omap1_init_late, - .timer = &omap1_timer, + .init_time = omap1_timer_init, .restart = voiceblue_restart, MACHINE_END diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index b53e0854422..fb18831e88a 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -75,7 +75,7 @@ extern void __init omap_check_revision(void); extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl); -extern struct sys_timer omap1_timer; +extern void omap1_timer_init(void); #ifdef CONFIG_OMAP_32K_TIMER extern int omap_32k_timer_init(void); #else diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h index ad6fbe7d83f..4869633de8c 100644 --- a/arch/arm/mach-omap1/include/mach/uncompress.h +++ b/arch/arm/mach-omap1/include/mach/uncompress.h @@ -115,8 +115,3 @@ static inline void arch_decomp_setup(void) DEBUG_LL_OMAP1(3, sx1); } while (0); } - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 4d4816fd6fc..726ec23d29c 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -145,7 +145,6 @@ static void omap_mpu_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_mpu_timer1 = { .name = "mpu_timer1", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_next_event = omap_mpu_set_next_event, .set_mode = omap_mpu_set_mode, }; @@ -170,15 +169,9 @@ static __init void omap_init_mpu_timer(unsigned long rate) setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); omap_mpu_timer_start(0, (rate / HZ) - 1, 1); - clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC, - clockevent_mpu_timer1.shift); - clockevent_mpu_timer1.max_delta_ns = - clockevent_delta2ns(-1, &clockevent_mpu_timer1); - clockevent_mpu_timer1.min_delta_ns = - clockevent_delta2ns(1, &clockevent_mpu_timer1); - clockevent_mpu_timer1.cpumask = cpumask_of(0); - clockevents_register_device(&clockevent_mpu_timer1); + clockevents_config_and_register(&clockevent_mpu_timer1, rate, + 1, -1); } @@ -236,12 +229,8 @@ static inline void omap_mpu_timer_init(void) * Timer initialization * --------------------------------------------------------------------------- */ -static void __init omap1_timer_init(void) +void __init omap1_timer_init(void) { if (omap_32k_timer_init() != 0) omap_mpu_timer_init(); } - -struct sys_timer omap1_timer = { - .init = omap1_timer_init, -}; diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 41152fadd4c..0b74246ba62 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -140,7 +140,6 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_32k_timer = { .name = "32k-timer", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_next_event = omap_32k_timer_set_next_event, .set_mode = omap_32k_timer_set_mode, }; @@ -165,16 +164,9 @@ static __init void omap_init_32k_timer(void) { setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); - clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, - NSEC_PER_SEC, - clockevent_32k_timer.shift); - clockevent_32k_timer.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer); - clockevent_32k_timer.min_delta_ns = - clockevent_delta2ns(1, &clockevent_32k_timer); - clockevent_32k_timer.cpumask = cpumask_of(0); - clockevents_register_device(&clockevent_32k_timer); + clockevents_config_and_register(&clockevent_32k_timer, + OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe); } /* diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 4815ea6f8f5..a3e0aaa4886 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -27,6 +27,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/gpio.h> +#include <linux/usb/phy.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -263,6 +264,7 @@ static void __init omap_2430sdp_init(void) omap_hsmmc_init(mmc); omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); board_smc91x_init(); @@ -284,6 +286,6 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") .handle_irq = omap2_intc_handle_irq, .init_machine = omap_2430sdp_init, .init_late = omap2430_init_late, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index bb73afc9ac1..e71ebdefc67 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -25,6 +25,7 @@ #include <linux/gpio.h> #include <linux/mmc/host.h> #include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/usb/phy.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -579,6 +580,7 @@ static void __init omap_3430sdp_init(void) omap_ads7846_init(1, gpio_pendown, 310, NULL); omap_serial_init(); omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); @@ -597,6 +599,6 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap_3430sdp_init, .init_late = omap3430_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 050aaa77125..33846274bb8 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -211,6 +211,6 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap_sdp_init, .init_late = omap3630_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1cc6696594f..508e2752b7d 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -26,10 +26,11 @@ #include <linux/regulator/fixed.h> #include <linux/leds.h> #include <linux/leds_pwm.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/omap4-keypad.h> #include <linux/usb/musb.h> +#include <linux/usb/phy.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -696,6 +697,7 @@ static void __init omap_4430sdp_init(void) omap4_sdp4430_wifi_init(); omap4_twl6030_hsmmc_init(mmc); + usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto"); usb_musb_init(&musb_board_data); status = omap_ethernet_init(); @@ -722,9 +724,8 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") .map_io = omap4_map_io, .init_early = omap4430_init_early, .init_irq = gic_init_irq, - .handle_irq = gic_handle_irq, .init_machine = omap_4430sdp_init, .init_late = omap4430_init_late, - .timer = &omap4_timer, + .init_time = omap4_local_timer_init, .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 51b96a1206d..07f0be24a5d 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -92,6 +92,6 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") .handle_irq = omap3_intc_handle_irq, .init_machine = am3517_crane_init, .init_late = am35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index f81a303b87f..6f5b2a05f4b 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -393,6 +393,6 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .handle_irq = omap3_intc_handle_irq, .init_machine = am3517_evm_init, .init_late = am35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 5d0a61f5416..3a6ca74709a 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -337,6 +337,6 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") .handle_irq = omap2_intc_handle_irq, .init_machine = omap_apollon_init, .init_late = omap2420_init_late, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index b3102c2f4a3..231a7d825f9 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -30,6 +30,7 @@ #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <linux/spi/spi.h> #include <linux/spi/tdo24m.h> @@ -724,6 +725,7 @@ static void __init cm_t3x_common_init(void) cm_t35_init_display(); omap_twl4030_audio_init("cm-t3x"); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); cm_t35_init_usbh(); cm_t35_init_camera(); @@ -751,7 +753,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t35_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END @@ -764,6 +766,6 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730") .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3730_init, .init_late = omap3630_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index ebbc2adb499..6a9529ab95c 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3517_init, .init_late = am35xx_init_late, - .timer = &omap3_gp_timer, + .init_time = omap3_gp_gptimer_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 12865af25d3..a37514ecc38 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -29,6 +29,7 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> @@ -622,6 +623,7 @@ static void __init devkit8000_init(void) omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); board_nand_init(devkit8000_nand_partitions, @@ -643,6 +645,6 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .handle_irq = omap3_intc_handle_irq, .init_machine = devkit8000_init, .init_late = omap35xx_init_late, - .timer = &omap3_secure_timer, + .init_time = omap3_secure_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 53cb380b787..2590463e4b5 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -16,7 +16,6 @@ #include <linux/of_platform.h> #include <linux/irqdomain.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include "common.h" @@ -65,7 +64,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap2_intc_handle_irq, .init_machine = omap_generic_init, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .dt_compat = omap242x_boards_compat, .restart = omap2xxx_restart, MACHINE_END @@ -84,7 +83,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap2_intc_handle_irq, .init_machine = omap_generic_init, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .dt_compat = omap243x_boards_compat, .restart = omap2xxx_restart, MACHINE_END @@ -103,7 +102,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .dt_compat = omap3_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -120,7 +119,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .timer = &omap3_secure_timer, + .init_time = omap3_secure_sync32k_timer_init, .dt_compat = omap3_gp_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -139,7 +138,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .timer = &omap3_am33xx_timer, + .init_time = omap3_am33xx_gptimer_timer_init, .dt_compat = am33xx_boards_compat, MACHINE_END #endif @@ -156,10 +155,9 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .map_io = omap4_map_io, .init_early = omap4430_init_early, .init_irq = omap_gic_of_init, - .handle_irq = gic_handle_irq, .init_machine = omap_generic_init, .init_late = omap4430_init_late, - .timer = &omap4_timer, + .init_time = omap4_local_timer_init, .dt_compat = omap4_boards_compat, .restart = omap44xx_restart, MACHINE_END @@ -177,9 +175,8 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .map_io = omap5_map_io, .init_early = omap5_init_early, .init_irq = omap_gic_of_init, - .handle_irq = gic_handle_irq, .init_machine = omap_generic_init, - .timer = &omap5_timer, + .init_time = omap5_realtime_timer_init, .dt_compat = omap5_boards_compat, .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 3be1311f9e3..812c829fa46 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -342,6 +342,6 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board") .handle_irq = omap2_intc_handle_irq, .init_machine = omap_h4_init, .init_late = omap2420_init_late, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 0f24cb84ba5..3f97f30d788 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -18,6 +18,7 @@ #include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/input.h> +#include <linux/usb/phy.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -625,6 +626,7 @@ static void __init igep_init(void) omap_serial_init(); omap_sdrc_init(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); igep_flash_init(); @@ -655,7 +657,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board") .handle_irq = omap3_intc_handle_irq, .init_machine = igep_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END @@ -668,6 +670,6 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module") .handle_irq = omap3_intc_handle_irq, .init_machine = igep_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 0869f4f3d3e..b12fe966a7b 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -28,6 +28,7 @@ #include <linux/io.h> #include <linux/smsc911x.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <asm/mach-types.h> @@ -418,6 +419,7 @@ static void __init omap_ldp_init(void) omap_ads7846_init(1, 54, 310, NULL); omap_serial_init(); omap_sdrc_init(NULL, NULL); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0, nand_default_timings); @@ -435,6 +437,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap_ldp_init, .init_late = omap3430_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 0abb30fe399..f6eeb87e4e9 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -731,7 +731,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800") .handle_irq = omap2_intc_handle_irq, .init_machine = n8x0_init_machine, .init_late = omap2420_init_late, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .restart = omap2xxx_restart, MACHINE_END @@ -744,7 +744,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810") .handle_irq = omap2_intc_handle_irq, .init_machine = n8x0_init_machine, .init_late = omap2420_init_late, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .restart = omap2xxx_restart, MACHINE_END @@ -757,6 +757,6 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") .handle_irq = omap2_intc_handle_irq, .init_machine = n8x0_init_machine, .init_late = omap2420_init_late, - .timer = &omap2_timer, + .init_time = omap2_sync32k_timer_init, .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 22c483d5dfa..d07058b9c28 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -30,6 +30,7 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> @@ -519,6 +520,7 @@ static void __init omap3_beagle_init(void) omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); board_nand_init(omap3beagle_nand_partitions, @@ -544,6 +546,6 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_beagle_init, .init_late = omap3_init_late, - .timer = &omap3_secure_timer, + .init_time = omap3_secure_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 3985f35aee0..f43763647d5 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -41,6 +41,7 @@ #include <linux/regulator/machine.h> #include <linux/mmc/host.h> #include <linux/export.h> +#include <linux/usb/phy.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -309,7 +310,7 @@ static struct omap2_hsmmc_info mmc[] = { .gpio_wp = 63, .deferred = true, }, -#ifdef CONFIG_WL12XX_PLATFORM_DATA +#ifdef CONFIG_WILINK_PLATFORM_DATA { .name = "wl1271", .mmc = 2, @@ -450,7 +451,7 @@ static struct regulator_init_data omap3evm_vio = { .consumer_supplies = omap3evm_vio_supply, }; -#ifdef CONFIG_WL12XX_PLATFORM_DATA +#ifdef CONFIG_WILINK_PLATFORM_DATA #define OMAP3EVM_WLAN_PMENA_GPIO (150) #define OMAP3EVM_WLAN_IRQ_GPIO (149) @@ -563,7 +564,7 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = { OMAP_PIN_OFF_NONE), OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_NONE), -#ifdef CONFIG_WL12XX_PLATFORM_DATA +#ifdef CONFIG_WILINK_PLATFORM_DATA /* WLAN IRQ - GPIO 149 */ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), @@ -601,7 +602,7 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = { OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -#ifdef CONFIG_WL12XX_PLATFORM_DATA +#ifdef CONFIG_WILINK_PLATFORM_DATA /* WLAN IRQ - GPIO 149 */ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), @@ -637,7 +638,7 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = { static void __init omap3_evm_wl12xx_init(void) { -#ifdef CONFIG_WL12XX_PLATFORM_DATA +#ifdef CONFIG_WILINK_PLATFORM_DATA int ret; /* WL12xx WLAN Init */ @@ -734,6 +735,7 @@ static void __init omap3_evm_init(void) omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); usbhs_bdata.reset_gpio_port[1] = 135; } + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(&musb_board_data); usbhs_init(&usbhs_bdata); board_nand_init(omap3evm_nand_partitions, @@ -757,6 +759,6 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_evm_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 2a065ba6eb5..bab51e64c4b 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -29,6 +29,7 @@ #include <linux/i2c/twl.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -215,6 +216,7 @@ static void __init omap3logic_init(void) board_mmc_init(); board_smsc911x_init(); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); /* Ensure SDRC pins are mux'd for self-refresh */ @@ -231,7 +233,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3logic_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END @@ -244,6 +246,6 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3logic_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index a53a6683c1b..07cc0884e76 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -35,6 +35,7 @@ #include <linux/mmc/host.h> #include <linux/mmc/card.h> #include <linux/regulator/fixed.h> +#include <linux/usb/phy.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <asm/mach-types.h> @@ -601,6 +602,7 @@ static void __init omap3pandora_init(void) ARRAY_SIZE(omap3pandora_spi_board_info)); omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); usbhs_init(&usbhs_bdata); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); gpmc_nand_init(&pandora_nand_data, NULL); @@ -618,6 +620,6 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3pandora_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 53a6cbcf974..0490acbc433 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -33,6 +33,7 @@ #include <linux/interrupt.h> #include <linux/smsc911x.h> #include <linux/i2c/at24.h> +#include <linux/usb/phy.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -404,6 +405,7 @@ static void __init omap3_stalker_init(void) omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL); @@ -427,6 +429,6 @@ MACHINE_START(SBC3530, "OMAP3 STALKER") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_stalker_init, .init_late = omap35xx_init_late, - .timer = &omap3_secure_timer, + .init_time = omap3_secure_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 263cb9cfbf3..91daf71190c 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -28,6 +28,7 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/nand.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/spi/spi.h> @@ -365,6 +366,7 @@ static void __init omap3_touchbook_init(void) /* Touchscreen and accelerometer */ omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); board_nand_init(omap3touchbook_nand_partitions, @@ -386,6 +388,6 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_touchbook_init, .init_late = omap3430_init_late, - .timer = &omap3_secure_timer, + .init_time = omap3_secure_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 769c1feee1c..7b152d04a60 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -30,10 +30,11 @@ #include <linux/regulator/fixed.h> #include <linux/ti_wilink_st.h> #include <linux/usb/musb.h> +#include <linux/usb/phy.h> #include <linux/wl12xx.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/omap-abe-twl6040.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -447,6 +448,7 @@ static void __init omap4_panda_init(void) omap_sdrc_init(NULL, NULL); omap4_twl6030_hsmmc_init(mmc); omap4_ehci_init(); + usb_bind_phy("musb-hdrc.0.auto", 0, "omap-usb2.1.auto"); usb_musb_init(&musb_board_data); omap4_panda_display_init(); } @@ -459,9 +461,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") .map_io = omap4_map_io, .init_early = omap4430_init_early, .init_irq = gic_init_irq, - .handle_irq = gic_handle_irq, .init_machine = omap4_panda_init, .init_late = omap4430_init_late, - .timer = &omap4_timer, + .init_time = omap4_local_timer_init, .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index c8fde3e5644..6975a8585da 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -36,6 +36,7 @@ #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/mmc/host.h> +#include <linux/usb/phy.h> #include <linux/platform_data/mtd-nand-omap2.h> #include <linux/platform_data/spi-omap2-mcspi.h> @@ -499,6 +500,7 @@ static void __init overo_init(void) mt46h32m32lf6_sdrc_params); board_nand_init(overo_nand_partitions, ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); overo_spi_init(); @@ -551,6 +553,6 @@ MACHINE_START(OVERO, "Gumstix Overo") .handle_irq = omap3_intc_handle_irq, .init_machine = overo_init, .init_late = omap35xx_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 0c777b75e48..345e8c4b873 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -18,6 +18,7 @@ #include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> #include <linux/platform_data/mtd-onenand-omap2.h> +#include <linux/usb/phy.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -134,6 +135,7 @@ static void __init rm680_init(void) sdrc_params = nokia_get_sdram_timings(); omap_sdrc_init(sdrc_params, sdrc_params); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); rm680_peripherals_init(); } @@ -147,7 +149,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") .handle_irq = omap3_intc_handle_irq, .init_machine = rm680_init, .init_late = omap3630_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END @@ -160,6 +162,6 @@ MACHINE_START(NOKIA_RM696, "Nokia RM-696 board") .handle_irq = omap3_intc_handle_irq, .init_machine = rm680_init, .init_late = omap3630_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index cf07e289b4e..f3d075baebb 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -42,7 +42,7 @@ #include <media/si4713.h> #include <linux/leds-lp5523.h> -#include <../drivers/staging/iio/light/tsl2563.h> +#include <linux/platform_data/tsl2563.h> #include <linux/lis3lv02d.h> #if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE) diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index d0374ea2dfb..f7c4616cbb6 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -123,6 +123,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") .handle_irq = omap3_intc_handle_irq, .init_machine = rx51_init, .init_late = omap3430_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index 1a3e056d63a..6273c286e1d 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -43,7 +43,7 @@ MACHINE_START(TI8168EVM, "ti8168evm") .map_io = ti81xx_map_io, .init_early = ti81xx_init_early, .init_irq = ti81xx_init_irq, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .init_machine = ti81xx_evm_init, .init_late = ti81xx_init_late, .restart = omap44xx_restart, @@ -55,7 +55,7 @@ MACHINE_START(TI8148EVM, "ti8148evm") .map_io = ti81xx_map_io, .init_early = ti81xx_init_early, .init_irq = ti81xx_init_irq, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .init_machine = ti81xx_evm_init, .init_late = ti81xx_init_late, .restart = omap44xx_restart, diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 26e07addc9d..dc5498b1b3a 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -20,6 +20,7 @@ #include <linux/wl12xx.h> #include <linux/mmc/host.h> #include <linux/platform_data/gpio-omap.h> +#include <linux/usb/phy.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -298,6 +299,7 @@ void __init zoom_peripherals_init(void) omap_hsmmc_init(mmc); omap_i2c_init(); platform_device_register(&omap_vwlan_device); + usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); enable_board_wakeup_source(); omap_serial_init(); diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index d7fa31e6723..d257cf1e0ab 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -137,7 +137,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap_zoom_init, .init_late = omap3430_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END @@ -150,6 +150,6 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .handle_irq = omap3_intc_handle_irq, .init_machine = omap_zoom_init, .init_late = omap3630_init_late, - .timer = &omap3_timer, + .init_time = omap3_sync32k_timer_init, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 948bcaa82eb..b4350274361 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -79,13 +79,13 @@ static inline int omap_mux_late_init(void) extern void omap2_init_common_infrastructure(void); -extern struct sys_timer omap2_timer; -extern struct sys_timer omap3_timer; -extern struct sys_timer omap3_secure_timer; -extern struct sys_timer omap3_gp_timer; -extern struct sys_timer omap3_am33xx_timer; -extern struct sys_timer omap4_timer; -extern struct sys_timer omap5_timer; +extern void omap2_sync32k_timer_init(void); +extern void omap3_sync32k_timer_init(void); +extern void omap3_secure_sync32k_timer_init(void); +extern void omap3_gp_gptimer_timer_init(void); +extern void omap3_am33xx_gptimer_timer_init(void); +extern void omap4_local_timer_init(void); +extern void omap5_realtime_timer_init(void); void omap2420_init_early(void); void omap2430_init_early(void); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 626f3ea3142..b6cc233214d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -20,6 +20,7 @@ #include <linux/pinctrl/machine.h> #include <linux/platform_data/omap4-keypad.h> #include <linux/platform_data/omap_ocp2scp.h> +#include <linux/usb/omap_control_usb.h> #include <asm/mach-types.h> #include <asm/mach/map.h> @@ -254,6 +255,49 @@ static inline void omap_init_camera(void) #endif } +#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB) +static struct omap_control_usb_platform_data omap4_control_usb_pdata = { + .type = 1, +}; + +struct resource omap4_control_usb_res[] = { + { + .name = "control_dev_conf", + .start = 0x4a002300, + .end = 0x4a002303, + .flags = IORESOURCE_MEM, + }, + { + .name = "otghs_control", + .start = 0x4a00233c, + .end = 0x4a00233f, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap4_control_usb = { + .name = "omap-control-usb", + .id = -1, + .dev = { + .platform_data = &omap4_control_usb_pdata, + }, + .num_resources = 2, + .resource = omap4_control_usb_res, +}; + +static inline void __init omap_init_control_usb(void) +{ + if (!cpu_is_omap44xx()) + return; + + if (platform_device_register(&omap4_control_usb)) + pr_err("Error registering omap_control_usb device\n"); +} + +#else +static inline void omap_init_control_usb(void) { } +#endif /* CONFIG_OMAP_CONTROL_USB */ + int __init omap4_keyboard_init(struct omap4_keypad_platform_data *sdp4430_keypad_data, struct omap_board_data *bdata) { @@ -721,6 +765,7 @@ static int __init omap2_init_devices(void) omap_init_mbox(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { + omap_init_control_usb(); omap_init_dmic(); omap_init_mcpdm(); omap_init_mcspi(); diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 8033cb747c8..64bac53da0e 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1134,11 +1134,9 @@ static int gpmc_probe(struct platform_device *pdev) phys_base = res->start; mem_size = resource_size(res); - gpmc_base = devm_request_and_ioremap(&pdev->dev, res); - if (!gpmc_base) { - dev_err(&pdev->dev, "error: request memory / ioremap\n"); - return -EADDRNOTAVAIL; - } + gpmc_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpmc_base)) + return PTR_ERR(gpmc_base); res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (res == NULL) diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h index 8e3546d3e04..7b360acd19c 100644 --- a/arch/arm/mach-omap2/include/mach/uncompress.h +++ b/arch/arm/mach-omap2/include/mach/uncompress.h @@ -169,8 +169,3 @@ static inline void arch_decomp_setup(void) DEBUG_LL_AM33XX(1, am335xevm); } while (0); } - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index cd42d921940..361677983af 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -19,9 +19,9 @@ #include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> -#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include "omap-secure.h" @@ -157,7 +157,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * booted = true; } - gic_raise_softirq(cpumask_of(cpu), 0); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); /* * Now the secondary core is starting up let it run its @@ -231,8 +231,6 @@ static void __init omap4_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 5d3b4f4f81a..f8bb3b9b6a7 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -24,8 +24,7 @@ #include <linux/cpu.h> #include <linux/notifier.h> #include <linux/cpu_pm.h> - -#include <asm/hardware/gic.h> +#include <linux/irqchip/arm-gic.h> #include "omap-wakeupgen.h" #include "omap-secure.h" @@ -46,7 +45,7 @@ static void __iomem *wakeupgen_base; static void __iomem *sar_base; -static DEFINE_SPINLOCK(wakeupgen_lock); +static DEFINE_RAW_SPINLOCK(wakeupgen_lock); static unsigned int irq_target_cpu[MAX_IRQS]; static unsigned int irq_banks = MAX_NR_REG_BANKS; static unsigned int max_irqs = MAX_IRQS; @@ -134,9 +133,9 @@ static void wakeupgen_mask(struct irq_data *d) { unsigned long flags; - spin_lock_irqsave(&wakeupgen_lock, flags); + raw_spin_lock_irqsave(&wakeupgen_lock, flags); _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]); - spin_unlock_irqrestore(&wakeupgen_lock, flags); + raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } /* @@ -146,9 +145,9 @@ static void wakeupgen_unmask(struct irq_data *d) { unsigned long flags; - spin_lock_irqsave(&wakeupgen_lock, flags); + raw_spin_lock_irqsave(&wakeupgen_lock, flags); _wakeupgen_set(d->irq, irq_target_cpu[d->irq]); - spin_unlock_irqrestore(&wakeupgen_lock, flags); + raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } #ifdef CONFIG_HOTPLUG_CPU @@ -189,7 +188,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set) { unsigned long flags; - spin_lock_irqsave(&wakeupgen_lock, flags); + raw_spin_lock_irqsave(&wakeupgen_lock, flags); if (set) { _wakeupgen_save_masks(cpu); _wakeupgen_set_all(cpu, WKG_MASK_ALL); @@ -197,7 +196,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set) _wakeupgen_set_all(cpu, WKG_UNMASK_ALL); _wakeupgen_restore_masks(cpu); } - spin_unlock_irqrestore(&wakeupgen_lock, flags); + raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); } #endif diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 6897ae21bb8..54709488360 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -15,13 +15,14 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/platform_device.h> #include <linux/memblock.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/export.h> +#include <linux/irqchip/arm-gic.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> #include <asm/memblock.h> @@ -255,16 +256,10 @@ static int __init omap4_sar_ram_init(void) } early_initcall(omap4_sar_ram_init); -static struct of_device_id irq_match[] __initdata = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, }, - { } -}; - void __init omap_gic_of_init(void) { omap_wakeupgen_init(); - of_irq_init(irq_match); + irqchip_init(); } #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 793f54ac7d1..624a7e84a68 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2702,13 +2702,6 @@ static struct resource omap44xx_usb_phy_and_pll_addrs[] = { .end = 0x4a0ae000, .flags = IORESOURCE_MEM, }, - { - /* XXX: Remove this once control module driver is in place */ - .name = "ctrl_dev", - .start = 0x4a002300, - .end = 0x4a002303, - .flags = IORESOURCE_MEM, - }, { } }; @@ -6156,12 +6149,6 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { .pa_end = 0x4a0ab7ff, .flags = ADDR_TYPE_RT }, - { - /* XXX: Remove this once control module driver is in place */ - .pa_start = 0x4a00233c, - .pa_end = 0x4a00233f, - .flags = ADDR_TYPE_RT - }, { } }; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7be3622cfc8..2d93d8b2383 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -351,12 +351,10 @@ static void omap3_pm_idle(void) if (omap_irq_pending()) goto out; - trace_power_start(POWER_CSTATE, 1, smp_processor_id()); trace_cpu_idle(1, smp_processor_id()); omap_sram_idle(); - trace_power_end(smp_processor_id()); trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); out: diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b8ad6e632bb..71729888ff0 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -131,7 +131,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_gpt = { .name = "gp_timer", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 300, .set_next_event = omap2_gp_timer_set_next_event, .set_mode = omap2_gp_timer_set_mode, @@ -228,7 +227,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, int r = 0; if (of_have_populated_dt()) { - np = omap_get_timer_dt(omap_timer_match, NULL); + np = omap_get_timer_dt(omap_timer_match, property); if (!np) return -ENODEV; @@ -336,17 +335,11 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); - clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, - clockevent_gpt.shift); - clockevent_gpt.max_delta_ns = - clockevent_delta2ns(0xffffffff, &clockevent_gpt); - clockevent_gpt.min_delta_ns = - clockevent_delta2ns(3, &clockevent_gpt); - /* Timer internal resynch latency. */ - clockevent_gpt.cpumask = cpu_possible_mask; clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); - clockevents_register_device(&clockevent_gpt); + clockevents_config_and_register(&clockevent_gpt, clkev.rate, + 3, /* Timer internal resynch latency */ + 0xffffffff); pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", gptimer_id, clkev.rate); @@ -552,7 +545,7 @@ static inline void __init realtime_counter_init(void) #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ clksrc_nr, clksrc_src) \ -static void __init omap##name##_gptimer_timer_init(void) \ +void __init omap##name##_gptimer_timer_init(void) \ { \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ @@ -561,7 +554,7 @@ static void __init omap##name##_gptimer_timer_init(void) \ #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ clksrc_nr, clksrc_src) \ -static void __init omap##name##_sync32k_timer_init(void) \ +void __init omap##name##_sync32k_timer_init(void) \ { \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ @@ -572,33 +565,23 @@ static void __init omap##name##_sync32k_timer_init(void) \ omap2_sync32k_clocksource_init(); \ } -#define OMAP_SYS_TIMER(name, clksrc) \ -struct sys_timer omap##name##_timer = { \ - .init = omap##name##_##clksrc##_timer_init, \ -}; - #ifdef CONFIG_ARCH_OMAP2 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon", 2, OMAP2_MPU_SOURCE); -OMAP_SYS_TIMER(2, sync32k); #endif /* CONFIG_ARCH_OMAP2 */ #ifdef CONFIG_ARCH_OMAP3 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon", 2, OMAP3_MPU_SOURCE); -OMAP_SYS_TIMER(3, sync32k); OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", 2, OMAP3_MPU_SOURCE); -OMAP_SYS_TIMER(3_secure, sync32k); OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon", 2, OMAP3_MPU_SOURCE); -OMAP_SYS_TIMER(3_gp, gptimer); #endif /* CONFIG_ARCH_OMAP3 */ #ifdef CONFIG_SOC_AM33XX OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", 2, OMAP4_MPU_SOURCE); -OMAP_SYS_TIMER(3_am33xx, gptimer); #endif /* CONFIG_SOC_AM33XX */ #ifdef CONFIG_ARCH_OMAP4 @@ -606,7 +589,7 @@ OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", 2, OMAP4_MPU_SOURCE); #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); -static void __init omap4_local_timer_init(void) +void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); /* Local timers are not supprted on OMAP4430 ES1.0 */ @@ -624,18 +607,17 @@ static void __init omap4_local_timer_init(void) } } #else /* CONFIG_LOCAL_TIMERS */ -static void __init omap4_local_timer_init(void) +void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); } #endif /* CONFIG_LOCAL_TIMERS */ -OMAP_SYS_TIMER(4, local); #endif /* CONFIG_ARCH_OMAP4 */ #ifdef CONFIG_SOC_OMAP5 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", 2, OMAP4_MPU_SOURCE); -static void __init omap5_realtime_timer_init(void) +void __init omap5_realtime_timer_init(void) { int err; @@ -646,7 +628,6 @@ static void __init omap5_realtime_timer_init(void) if (err) pr_err("%s: arch_timer_register failed %d\n", __func__, err); } -OMAP_SYS_TIMER(5, realtime); #endif /* CONFIG_SOC_OMAP5 */ /** diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index e49b40b4c90..6a7aec6d117 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -23,6 +23,7 @@ #include <linux/i2c.h> #include <linux/i2c/twl.h> #include <linux/gpio.h> +#include <linux/string.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -56,7 +57,7 @@ void __init omap_pmic_init(int bus, u32 clkrate, struct twl4030_platform_data *pmic_data) { omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE); - strncpy(pmic_i2c_board_info.type, pmic_type, + strlcpy(pmic_i2c_board_info.type, pmic_type, sizeof(pmic_i2c_board_info.type)); pmic_i2c_board_info.irq = pmic_irq; pmic_i2c_board_info.platform_data = pmic_data; diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 7b33b375fe7..9d27e3f8a09 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -85,6 +85,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) musb_plat.mode = board_data->mode; musb_plat.extvbus = board_data->extvbus; + if (cpu_is_omap44xx()) + musb_plat.has_mailbox = true; + if (soc_is_am35xx()) { oh_name = "am35x_otg_hs"; name = "musb-am35x"; diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 32e5c211a89..35a8014529c 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -72,7 +72,7 @@ DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion_dt_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .init_machine = orion5x_dt_init, .restart = orion5x_restart, .dt_compat = orion5x_dt_compat, diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 550f92320af..d068f1431c4 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -217,7 +217,7 @@ int __init orion5x_find_tclk(void) return 166666667; } -static void __init orion5x_timer_init(void) +void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); @@ -225,10 +225,6 @@ static void __init orion5x_timer_init(void) IRQ_ORION5X_BRIDGE, orion5x_tclk); } -struct sys_timer orion5x_timer = { - .init = orion5x_timer_init, -}; - /***************************************************************************** * General diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 7db5cdd9c4b..e6034576028 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -15,7 +15,7 @@ void orion5x_init(void); void orion5x_id(u32 *dev, u32 *rev, char **dev_name); void clk_init(void); extern int orion5x_tclk; -extern struct sys_timer orion5x_timer; +extern void orion5x_timer_init(void); /* * Enumerations and functions for Orion windows mapping. Used by Orion core diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index e3629c063df..57d0af74874 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -342,7 +342,7 @@ MACHINE_START(D2NET, "LaCie d2 Network") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END @@ -355,7 +355,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 41fe2b1ff47..76665640087 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -362,6 +362,6 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index e533588880f..6eb1732757f 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -714,7 +714,7 @@ MACHINE_START(DNS323, "D-Link DNS-323") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h index 4322dba468a..abd26b542c3 100644 --- a/arch/arm/mach-orion5x/include/mach/uncompress.h +++ b/arch/arm/mach-orion5x/include/mach/uncompress.h @@ -46,4 +46,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index f1ae10ae5bd..b9840352621 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -383,7 +383,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END @@ -397,7 +397,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 0c9e413b580..044da5b6a6a 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -322,7 +322,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index c1b5d8a5803..d49f93423f5 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -269,7 +269,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index 949eaa8f12e..8e3965c6c0f 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -271,7 +271,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 1c16d045333..0ec94a1f2b1 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -265,7 +265,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index c87fde4deec..18143f2a909 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -233,7 +233,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 3506f16c0bf..282e503b003 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -425,7 +425,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 9b1c9531029..d6e72f672af 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -171,7 +171,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index 51ba2b81a10..c8b7913310e 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -183,7 +183,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 0a56b9444f1..f9e156725d7 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -281,6 +281,6 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index ed50910b08a..78a1e6ab1b9 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -123,7 +123,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 90e571dc4de..acc0877ec1c 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -361,7 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index b184f680e0d..9c17f0c2b48 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -326,7 +326,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index a5c2e64c4ec..8cc5ab6c503 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -315,7 +315,7 @@ MACHINE_START(TS409, "QNAP TS-409") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index b0727dcd1ef..e960855d32a 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -619,6 +619,6 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") .map_io = ts78xx_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 754c12b6abf..66552ca7e05 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -176,7 +176,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 45c21251eb1..2c5408e2e68 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -264,7 +264,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") .map_io = orion5x_map_io, .init_early = orion5x_init_early, .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .init_time = orion5x_timer_init, .fixup = tag_fixup_mem32, .restart = orion5x_restart, MACHINE_END diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig index 868796f8085..13bae78b215 100644 --- a/arch/arm/mach-picoxcell/Kconfig +++ b/arch/arm/mach-picoxcell/Kconfig @@ -7,7 +7,6 @@ config ARCH_PICOXCELL select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_TCM select NO_IOPORT select SPARSE_IRQ diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index f6c0849af5e..70b441ad1d1 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -9,6 +9,7 @@ */ #include <linux/delay.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/irqdomain.h> #include <linux/of.h> #include <linux/of_address.h> @@ -17,7 +18,6 @@ #include <linux/dw_apb_timer.h> #include <asm/mach/arch.h> -#include <asm/hardware/vic.h> #include <asm/mach/map.h> #include "common.h" @@ -70,16 +70,6 @@ static const char *picoxcell_dt_match[] = { NULL }; -static const struct of_device_id vic_of_match[] __initconst = { - { .compatible = "arm,pl192-vic", .data = vic_of_init, }, - { /* Sentinel */ } -}; - -static void __init picoxcell_init_irq(void) -{ - of_irq_init(vic_of_match); -} - static void picoxcell_wdt_restart(char mode, const char *cmd) { /* @@ -97,9 +87,8 @@ static void picoxcell_wdt_restart(char mode, const char *cmd) DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .map_io = picoxcell_map_io, .nr_irqs = NR_IRQS_LEGACY, - .init_irq = picoxcell_init_irq, - .handle_irq = vic_handle_irq, - .timer = &dw_apb_timer, + .init_irq = irqchip_init, + .init_time = dw_apb_timer_init, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, .restart = picoxcell_wdt_restart, diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h index a65cb02f84c..481b42a4ef1 100644 --- a/arch/arm/mach-picoxcell/common.h +++ b/arch/arm/mach-picoxcell/common.h @@ -12,6 +12,6 @@ #include <asm/mach/time.h> -extern struct sys_timer dw_apb_timer; +extern void dw_apb_timer_init(void); #endif /* __PICOXCELL_COMMON_H__ */ diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index f25a5419463..ed3570e5eb8 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -40,7 +40,7 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .map_io = sirfsoc_map_lluart, .init_irq = sirfsoc_of_irq_init, - .timer = &sirfsoc_timer, + .init_time = sirfsoc_timer_init, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 60d826fc218..9c75f124e3c 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -12,7 +12,7 @@ #include <linux/init.h> #include <asm/mach/time.h> -extern struct sys_timer sirfsoc_timer; +extern void sirfsoc_timer_init(void); extern void __init sirfsoc_of_irq_init(void); extern void __init sirfsoc_of_clk_init(void); diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h index 0c898fcf909..f72ca26ab4f 100644 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ b/arch/arm/mach-prima2/include/mach/uncompress.h @@ -17,8 +17,6 @@ void arch_decomp_setup(void) { } -#define arch_decomp_wdog() - static __inline__ void putc(char c) { /* diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c index d95bf252f69..a7a2c199c3e 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer.c @@ -175,19 +175,13 @@ static u32 notrace sirfsoc_read_sched_clock(void) static void __init sirfsoc_clockevent_init(void) { - clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); - - sirfsoc_clockevent.max_delta_ns = - clockevent_delta2ns(-2, &sirfsoc_clockevent); - sirfsoc_clockevent.min_delta_ns = - clockevent_delta2ns(2, &sirfsoc_clockevent); - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&sirfsoc_clockevent); + clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, + 2, -2); } /* initialize the kernel jiffy timer source */ -static void __init sirfsoc_timer_init(void) +void __init sirfsoc_timer_init(void) { unsigned long rate; struct clk *clk; @@ -226,7 +220,7 @@ static struct of_device_id timer_ids[] = { {}, }; -static void __init sirfsoc_of_timer_map(void) +void __init sirfsoc_of_timer_map(void) { struct device_node *np; const unsigned int *intspec; @@ -245,7 +239,3 @@ static void __init sirfsoc_of_timer_map(void) of_node_put(np); } - -struct sys_timer sirfsoc_timer = { - .init = sirfsoc_timer_init, -}; diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 20822934251..2f71b3fbd31 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -822,7 +822,7 @@ MACHINE_START(BALLOON3, "Balloon3") .nr_irqs = BALLOON3_NR_IRQS, .init_irq = balloon3_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = balloon3_init, .atag_offset = 0x100, .restart = pxa_restart, diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c index 9a8760b7291..c092730749b 100644 --- a/arch/arm/mach-pxa/capc7117.c +++ b/arch/arm/mach-pxa/capc7117.c @@ -153,7 +153,7 @@ MACHINE_START(CAPC7117, .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = capc7117_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index a103c8ffea9..bb99f59a36d 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -520,7 +520,7 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX") .init_irq = cmx2xx_init_irq, /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */ .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = cmx2xx_init, #ifdef CONFIG_PCI .dma_zone_size = SZ_64M, diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index cc2b23afcaa..8091aac89ed 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -854,7 +854,7 @@ MACHINE_START(CM_X300, "CM-X300 module") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = cm_x300_init, .fixup = cm_x300_fixup, .restart = pxa_restart, diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index b2f227d3612..5f9d9303b34 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -313,7 +313,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END @@ -324,7 +324,7 @@ MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index a9c9c163dd9..f1a1ac1fbd8 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -189,7 +189,7 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index 25515cd7e68..f6cc8b0ab82 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -259,7 +259,7 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 7c83f52c549..a5b8fead7d6 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -733,7 +733,7 @@ MACHINE_START(CORGI, "SHARP Corgi") .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, .init_machine = corgi_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = corgi_restart, MACHINE_END #endif @@ -746,7 +746,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd") .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, .init_machine = corgi_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = corgi_restart, MACHINE_END #endif @@ -759,7 +759,7 @@ MACHINE_START(HUSKY, "SHARP Husky") .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, .init_machine = corgi_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = corgi_restart, MACHINE_END #endif diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 7039f44b364..fadfff8feae 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -278,6 +278,6 @@ MACHINE_START(CSB726, "Cogent CSB726") .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, .init_machine = csb726_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 1b6411439ec..446563a7d1a 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -1298,7 +1298,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = em_x270_init, .restart = pxa_restart, MACHINE_END @@ -1309,7 +1309,7 @@ MACHINE_START(EXEDA, "Compulab eXeda") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = em_x270_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index be2ee9bf5c6..8280ebcaab9 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -195,7 +195,7 @@ MACHINE_START(E330, "Toshiba e330") .handle_irq = pxa25x_handle_irq, .fixup = eseries_fixup, .init_machine = e330_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -246,7 +246,7 @@ MACHINE_START(E350, "Toshiba e350") .handle_irq = pxa25x_handle_irq, .fixup = eseries_fixup, .init_machine = e350_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -370,7 +370,7 @@ MACHINE_START(E400, "Toshiba e400") .handle_irq = pxa25x_handle_irq, .fixup = eseries_fixup, .init_machine = e400_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -566,7 +566,7 @@ MACHINE_START(E740, "Toshiba e740") .handle_irq = pxa25x_handle_irq, .fixup = eseries_fixup, .init_machine = e740_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -765,7 +765,7 @@ MACHINE_START(E750, "Toshiba e750") .handle_irq = pxa25x_handle_irq, .fixup = eseries_fixup, .init_machine = e750_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -977,7 +977,7 @@ MACHINE_START(E800, "Toshiba e800") .handle_irq = pxa25x_handle_irq, .fixup = eseries_fixup, .init_machine = e800_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index dc58fa0edb6..dca10709be8 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -802,7 +802,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780") .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = a780_init, .restart = pxa_restart, MACHINE_END @@ -869,7 +869,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680") .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = e680_init, .restart = pxa_restart, MACHINE_END @@ -936,7 +936,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200") .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = a1200_init, .restart = pxa_restart, MACHINE_END @@ -1128,7 +1128,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910") .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = a910_init, .restart = pxa_restart, MACHINE_END @@ -1195,7 +1195,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6") .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = e6_init, .restart = pxa_restart, MACHINE_END @@ -1236,7 +1236,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2") .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = e2_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 42d5cca6625..fd7ea39b78c 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -10,9 +10,8 @@ */ struct irq_data; -struct sys_timer; -extern struct sys_timer pxa_timer; +extern void pxa_timer_init(void); extern void __init pxa_map_io(void); diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 60755a6bb1c..00b92dad7b8 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -238,7 +238,7 @@ MACHINE_START(GUMSTIX, "Gumstix") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = gumstix_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index e7dec589f01..875ec335149 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c @@ -208,7 +208,7 @@ MACHINE_START(H5400, "HP iPAQ H5000") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = h5000_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index 2962de898da..7a8d749a07b 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c @@ -164,6 +164,6 @@ MACHINE_START(HIMALAYA, "HTC Himalaya") .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, .init_machine = himalaya_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index e2c6391863f..133109ec733 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -900,6 +900,6 @@ MACHINE_START(H4700, "HP iPAQ HX4700") .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, .init_machine = hx4700_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index 1d02eabc9c6..fe31bfcbb8d 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -196,7 +196,7 @@ MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = icontrol_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 64507cdd2e8..343c4e3a7c5 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -279,7 +279,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = idp_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h index 2d3f14e3be2..714b6574393 100644 --- a/arch/arm/mach-pxa/include/mach/palmtreo.h +++ b/arch/arm/mach-pxa/include/mach/palmtreo.h @@ -38,13 +38,14 @@ #define GPIO_NR_TREO_LCD_POWER 25 /* Treo680 specific GPIOs */ -#ifdef CONFIG_MACH_TREO680 #define GPIO_NR_TREO680_SD_READONLY 33 #define GPIO_NR_TREO680_SD_POWER 42 #define GPIO_NR_TREO680_VIBRATE_EN 44 #define GPIO_NR_TREO680_KEYB_BL 24 #define GPIO_NR_TREO680_BT_EN 43 -#endif /* CONFIG_MACH_TREO680 */ +#define GPIO_NR_TREO680_LCD_POWER 77 +#define GPIO_NR_TREO680_LCD_EN 86 +#define GPIO_NR_TREO680_LCD_EN_N 25 /* Centro685 specific GPIOs */ #define GPIO_NR_CENTRO_SD_POWER 21 diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h index b7de471b273..b802f285fe0 100644 --- a/arch/arm/mach-pxa/include/mach/smemc.h +++ b/arch/arm/mach-pxa/include/mach/smemc.h @@ -37,6 +37,7 @@ #define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ #define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ #define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ +#define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */ /* * More handy macros for PCMCIA diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 5519a34b667..8c27757e68f 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -72,8 +72,3 @@ static inline void arch_decomp_setup(void) uart_is_pxa = 0; } } - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 402874f9021..e848c4607ba 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -443,7 +443,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto .nr_irqs = LITTLETON_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = littleton_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 1a63eaa8986..1255ee00f3d 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -503,7 +503,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") .nr_irqs = LPD270_NR_IRQS, .init_irq = lpd270_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = lpd270_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 553056d9a3c..d8a1be619f2 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -650,7 +650,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)") .nr_irqs = LUBBOCK_NR_IRQS, .init_irq = lubbock_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = lubbock_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index f7922404d94..f44532fc648 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -774,6 +774,6 @@ MACHINE_START(MAGICIAN, "HTC Magician") .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, .init_machine = magician_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f27a61ee7ac..7a12c1ba90f 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -714,7 +714,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") .nr_irqs = MAINSTONE_NR_IRQS, .init_irq = mainstone_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = mainstone_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 2831308dba6..f8979b943cb 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -762,6 +762,6 @@ MACHINE_START(MIOA701, "MIO A701") .init_irq = &pxa27x_init_irq, .handle_irq = &pxa27x_handle_irq, .init_machine = mioa701_machine_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = mioa701_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 152efbf093f..854f1f562d6 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c @@ -93,7 +93,7 @@ static void __init mp900c_init(void) /* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */ MACHINE_START(NEC_MP900, "MobilePro900/C") .atag_offset = 0x220100, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .map_io = pxa25x_map_io, .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 8bcc96e3b0d..909b713e578 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -347,7 +347,7 @@ MACHINE_START(PALMLD, "Palm LifeDrive") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = palmld_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 5ca7b904a30..5033fd07968 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -208,7 +208,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = palmt5_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index ca924cfedfc..100b176f7e8 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -542,7 +542,7 @@ MACHINE_START(PALMTC, "Palm Tungsten|C") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = palmtc_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 32e0d799835..0742721ced2 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -363,7 +363,7 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = palmte2_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 3f3c48f2f7c..a29849d181c 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -98,9 +98,6 @@ static unsigned long treo_pin_config[] __initdata = { GPIO96_KP_MKOUT_6, GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ - /* LCD */ - GPIOxx_LCD_TFT_16BPP, - /* Quick Capture Interface */ GPIO84_CIF_FV, GPIO85_CIF_LV, @@ -140,6 +137,12 @@ static unsigned long treo680_pin_config[] __initdata = { /* MATRIX KEYPAD - different wake up source */ GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, GPIO99_KP_MKIN_5, + + /* LCD... L_BIAS alt fn not configured on Treo680; is GPIO instead */ + GPIOxx_LCD_16BPP, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, }; #endif /* CONFIG_MACH_TREO680 */ @@ -155,6 +158,9 @@ static unsigned long centro685_pin_config[] __initdata = { /* MATRIX KEYPAD - different wake up source */ GPIO100_KP_MKIN_0, GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, + + /* LCD */ + GPIOxx_LCD_TFT_16BPP, }; #endif /* CONFIG_MACH_CENTRO */ @@ -328,7 +334,6 @@ static inline void palmtreo_uhc_init(void) {} /****************************************************************************** * Vibra and LEDs ******************************************************************************/ -#ifdef CONFIG_MACH_TREO680 static struct gpio_led treo680_gpio_leds[] = { { .name = "treo680:vibra:vibra", @@ -379,21 +384,17 @@ static struct gpio_led_platform_data centro_gpio_led_info = { static struct platform_device palmtreo_leds = { .name = "leds-gpio", .id = -1, - .dev = { - .platform_data = &treo680_gpio_led_info, - } }; static void __init palmtreo_leds_init(void) { if (machine_is_centro()) palmtreo_leds.dev.platform_data = ¢ro_gpio_led_info; + else if (machine_is_treo680()) + palmtreo_leds.dev.platform_data = &treo680_gpio_led_info; platform_device_register(&palmtreo_leds); } -#else -static inline void palmtreo_leds_init(void) {} -#endif /****************************************************************************** * Machine init @@ -424,10 +425,59 @@ static void __init palmphone_common_init(void) } #ifdef CONFIG_MACH_TREO680 +void __init treo680_gpio_init(void) +{ + unsigned int gpio; + + /* drive all three lcd gpios high initially */ + const unsigned long lcd_flags = GPIOF_INIT_HIGH | GPIOF_DIR_OUT; + + /* + * LCD GPIO initialization... + */ + + /* + * This is likely the power to the lcd. Toggling it low/high appears to + * turn the lcd off/on. Can be toggled after lcd is initialized without + * any apparent adverse effects to the lcd operation. Note that this + * gpio line is used by the lcd controller as the L_BIAS signal, but + * treo680 configures it as gpio. + */ + gpio = GPIO_NR_TREO680_LCD_POWER; + if (gpio_request_one(gpio, lcd_flags, "LCD power") < 0) + goto fail; + + /* + * These two are called "enables", for lack of a better understanding. + * If either of these are toggled after the lcd is initialized, the + * image becomes degraded. N.B. The IPL shipped with the treo + * configures GPIO_NR_TREO680_LCD_EN_N as output and drives it high. If + * the IPL is ever reprogrammed, this initialization may be need to be + * revisited. + */ + gpio = GPIO_NR_TREO680_LCD_EN; + if (gpio_request_one(gpio, lcd_flags, "LCD enable") < 0) + goto fail; + gpio = GPIO_NR_TREO680_LCD_EN_N; + if (gpio_request_one(gpio, lcd_flags, "LCD enable_n") < 0) + goto fail; + + /* driving this low turns LCD on */ + gpio_set_value(GPIO_NR_TREO680_LCD_EN_N, 0); + + return; + fail: + pr_err("gpio %d initialization failed\n", gpio); + gpio_free(GPIO_NR_TREO680_LCD_POWER); + gpio_free(GPIO_NR_TREO680_LCD_EN); + gpio_free(GPIO_NR_TREO680_LCD_EN_N); +} + static void __init treo680_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); palmphone_common_init(); + treo680_gpio_init(); palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY, GPIO_NR_TREO680_SD_POWER, 0); } @@ -451,7 +501,7 @@ MACHINE_START(TREO680, "Palm Treo 680") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = treo680_init, .restart = pxa_restart, MACHINE_END @@ -465,7 +515,7 @@ MACHINE_START(CENTRO, "Palm Centro 685") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = centro_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 8b4366628a1..627c93a7364 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -366,7 +366,7 @@ MACHINE_START(PALMTX, "Palm T|X") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = palmtx_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 8cdd4f58e25..18b7fcd9859 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -404,7 +404,7 @@ MACHINE_START(PALMZ72, "Palm Zire72") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = palmz72_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index fe9054435b6..69918c7e3f1 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -263,7 +263,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270") .nr_irqs = PCM027_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = pcm027_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 2910bb935c7..50ccd5f1d56 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -469,7 +469,7 @@ MACHINE_START(POODLE, "SHARP Poodle") .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = poodle_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c index c9192cea003..3835979a0dd 100644 --- a/arch/arm/mach-pxa/pxa-dt.c +++ b/arch/arm/mach-pxa/pxa-dt.c @@ -55,7 +55,7 @@ DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)") .map_io = pxa3xx_map_io, .init_irq = pxa3xx_dt_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, .init_machine = pxa3xx_dt_init, .dt_compat = pxa3xx_dt_board_compat, diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 616cb87b617..69985b06c0d 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -53,17 +53,25 @@ static unsigned long ac97_reset_config[] = { GPIO95_AC97_nRESET, }; -void pxa27x_assert_ac97reset(int reset_gpio, int on) +void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio) { + /* + * This helper function is used to work around a bug in the pxa27x's + * ac97 controller during a warm reset. The configuration of the + * reset_gpio is changed as follows: + * to_gpio == true: configured to generic output gpio and driven high + * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET + */ + if (reset_gpio == 113) - pxa2xx_mfp_config(on ? &ac97_reset_config[0] : - &ac97_reset_config[1], 1); + pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] : + &ac97_reset_config[1], 1); if (reset_gpio == 95) - pxa2xx_mfp_config(on ? &ac97_reset_config[2] : - &ac97_reset_config[3], 1); + pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] : + &ac97_reset_config[3], 1); } -EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset); +EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 25b08bfa997..af41888acbd 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -1095,7 +1095,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -1108,7 +1108,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif @@ -1121,7 +1121,7 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END #endif diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 08d87a5d263..710c493eac8 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -601,7 +601,7 @@ MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = saar_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index 79923058d10..f38aa890b2c 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -40,6 +40,8 @@ static void pxa3xx_smemc_resume(void) __raw_writel(csadrcfg[1], CSADRCFG1); __raw_writel(csadrcfg[2], CSADRCFG2); __raw_writel(csadrcfg[3], CSADRCFG3); + /* CSMSADRCFG wakes up in its default state (0), so we need to set it */ + __raw_writel(0x2, CSMSADRCFG); } static struct syscore_ops smemc_syscore_ops = { @@ -49,8 +51,19 @@ static struct syscore_ops smemc_syscore_ops = { static int __init smemc_init(void) { - if (cpu_is_pxa3xx()) + if (cpu_is_pxa3xx()) { + /* + * The only documentation we have on the + * Chip Select Configuration Register (CSMSADRCFG) is that + * it must be programmed to 0x2. + * Moreover, in the bit definitions, the second bit + * (CSMSADRCFG[1]) is called "SETALWAYS". + * Other bits are reserved in this register. + */ + __raw_writel(0x2, CSMSADRCFG); + register_syscore_ops(&smemc_syscore_ops); + } return 0; } diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 2073f0e6db0..362726c49c7 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -732,7 +732,7 @@ static inline void spitz_lcd_init(void) {} #endif /****************************************************************************** - * Framebuffer + * NAND Flash ******************************************************************************/ #if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE) static struct mtd_partition spitz_nand_partitions[] = { @@ -858,7 +858,7 @@ static inline void spitz_nor_init(void) {} #endif /****************************************************************************** - * GPIO expander + * I2C devices ******************************************************************************/ #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) static struct pca953x_platform_data akita_pca953x_pdata = { @@ -986,7 +986,7 @@ MACHINE_START(SPITZ, "SHARP Spitz") .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, .init_machine = spitz_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = spitz_restart, MACHINE_END #endif @@ -1000,7 +1000,7 @@ MACHINE_START(BORZOI, "SHARP Borzoi") .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, .init_machine = spitz_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = spitz_restart, MACHINE_END #endif @@ -1014,7 +1014,7 @@ MACHINE_START(AKITA, "SHARP Akita") .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, .init_machine = spitz_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = spitz_restart, MACHINE_END #endif diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 456560b5aad..88fde43c948 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -1006,7 +1006,7 @@ MACHINE_START(INTELMOTE2, "IMOTE 2") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = imote2_init, .atag_offset = 0x100, .restart = pxa_restart, @@ -1019,7 +1019,7 @@ MACHINE_START(STARGATE2, "Stargate 2") .nr_irqs = STARGATE_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = stargate2_init, .atag_offset = 0x100, .restart = pxa_restart, diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 1a25f8a7b0c..f55979c09a5 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -494,7 +494,7 @@ MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = tavorevb_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 4bc47d63698..8f1ee92aea3 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -89,48 +89,10 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) } } -static struct clock_event_device ckevt_pxa_osmr0 = { - .name = "osmr0", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = pxa_osmr0_set_next_event, - .set_mode = pxa_osmr0_set_mode, -}; - -static struct irqaction pxa_ost0_irq = { - .name = "ost0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = pxa_ost0_interrupt, - .dev_id = &ckevt_pxa_osmr0, -}; - -static void __init pxa_timer_init(void) -{ - unsigned long clock_tick_rate = get_clock_tick_rate(); - - writel_relaxed(0, OIER); - writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); - - setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); - - clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); - ckevt_pxa_osmr0.max_delta_ns = - clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); - ckevt_pxa_osmr0.min_delta_ns = - clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; - ckevt_pxa_osmr0.cpumask = cpumask_of(0); - - setup_irq(IRQ_OST0, &pxa_ost0_irq); - - clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32, - clocksource_mmio_readl_up); - clockevents_register_device(&ckevt_pxa_osmr0); -} - #ifdef CONFIG_PM static unsigned long osmr[4], oier, oscr; -static void pxa_timer_suspend(void) +static void pxa_timer_suspend(struct clock_event_device *cedev) { osmr[0] = readl_relaxed(OSMR0); osmr[1] = readl_relaxed(OSMR1); @@ -140,7 +102,7 @@ static void pxa_timer_suspend(void) oscr = readl_relaxed(OSCR); } -static void pxa_timer_resume(void) +static void pxa_timer_resume(struct clock_event_device *cedev) { /* * Ensure that we have at least MIN_OSCR_DELTA between match @@ -163,8 +125,38 @@ static void pxa_timer_resume(void) #define pxa_timer_resume NULL #endif -struct sys_timer pxa_timer = { - .init = pxa_timer_init, +static struct clock_event_device ckevt_pxa_osmr0 = { + .name = "osmr0", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = pxa_osmr0_set_next_event, + .set_mode = pxa_osmr0_set_mode, .suspend = pxa_timer_suspend, .resume = pxa_timer_resume, }; + +static struct irqaction pxa_ost0_irq = { + .name = "ost0", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = pxa_ost0_interrupt, + .dev_id = &ckevt_pxa_osmr0, +}; + +void __init pxa_timer_init(void) +{ + unsigned long clock_tick_rate = get_clock_tick_rate(); + + writel_relaxed(0, OIER); + writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); + + setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); + + ckevt_pxa_osmr0.cpumask = cpumask_of(0); + + setup_irq(IRQ_OST0, &pxa_ost0_irq); + + clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32, + clocksource_mmio_readl_up); + clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate, + MIN_OSCR_DELTA * 2, 0x7fffffff); +} diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 233629edf7e..9e7998d3635 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -982,6 +982,6 @@ MACHINE_START(TOSA, "SHARP Tosa") .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, .init_machine = tosa_init, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = tosa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index fbbcbed4d1d..c58043462ac 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -561,7 +561,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END @@ -573,6 +573,6 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index c773e4dded6..9c363c081d3 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -997,7 +997,7 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC") .nr_irqs = PXA_NR_IRQS, .init_irq = viper_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = viper_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index 491b6c9a2a9..aa89488f961 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -719,7 +719,7 @@ MACHINE_START(VPAC270, "Voipac PXA270") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = vpac270_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 4275713ccd1..13b1d4586d7 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -185,7 +185,7 @@ MACHINE_START(XCEP, "Iskratel XCEP") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa25x_init_irq, .handle_irq = pxa25x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index 97529face7a..989903a7e46 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -722,7 +722,7 @@ MACHINE_START(ZIPIT2, "Zipit Z2") .nr_irqs = PXA_NR_IRQS, .init_irq = pxa27x_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = z2_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index abd3aa14508..f5d43643456 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -910,7 +910,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") .nr_irqs = ZEUS_NR_IRQS, .init_irq = zeus_init_irq, .handle_irq = pxa27x_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = zeus_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 226279fac9d..1f00d650ac2 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -428,7 +428,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") .nr_irqs = ZYLONITE_NR_IRQS, .init_irq = pxa3xx_init_irq, .handle_irq = pxa3xx_handle_irq, - .timer = &pxa_timer, + .init_time = pxa_timer_init, .init_machine = zylonite_init, .restart = pxa_restart, MACHINE_END diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 68246748058..1d5ee5c9a1d 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -42,7 +42,6 @@ #include <asm/mach/irq.h> #include <asm/mach/map.h> -#include <asm/hardware/gic.h> #include <mach/platform.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h index d6b5073692d..44754230fdc 100644 --- a/arch/arm/mach-realview/include/mach/irqs-eb.h +++ b/arch/arm/mach-realview/include/mach/irqs-eb.h @@ -115,7 +115,7 @@ /* * Only define NR_IRQS if less than NR_IRQS_EB */ -#define NR_IRQS_EB (IRQ_EB_GIC_START + 96) +#define NR_IRQS_EB (IRQ_EB_GIC_START + 128) #if defined(CONFIG_MACH_REALVIEW_EB) \ && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h index 83050378ffd..cfa30d21783 100644 --- a/arch/arm/mach-realview/include/mach/uncompress.h +++ b/arch/arm/mach-realview/include/mach/uncompress.h @@ -75,4 +75,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 300f7064465..98e3052b793 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -14,7 +14,6 @@ #include <linux/io.h> #include <mach/hardware.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> @@ -59,8 +58,6 @@ static void __init realview_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init realview_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 28511d43637..5b1c8bfe6fa 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -27,13 +27,13 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-realview.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <asm/pgtable.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/smp_twd.h> @@ -418,10 +418,6 @@ static void __init realview_eb_timer_init(void) realview_eb_twd_init(); } -static struct sys_timer realview_eb_timer = { - .init = realview_eb_timer_init, -}; - static void realview_eb_restart(char mode, const char *cmd) { void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); @@ -472,8 +468,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB") .map_io = realview_eb_map_io, .init_early = realview_init_early, .init_irq = gic_init_irq, - .timer = &realview_eb_timer, - .handle_irq = gic_handle_irq, + .init_time = realview_eb_timer_init, .init_machine = realview_eb_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 07d6672ddae..d5e83a1f698 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -29,13 +29,13 @@ #include <linux/mtd/physmap.h> #include <linux/mtd/partitions.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-realview.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <asm/pgtable.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> @@ -329,10 +329,6 @@ static void __init realview_pb1176_timer_init(void) realview_timer_init(IRQ_DC1176_TIMER0); } -static struct sys_timer realview_pb1176_timer = { - .init = realview_pb1176_timer_init, -}; - static void realview_pb1176_restart(char mode, const char *cmd) { void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); @@ -384,8 +380,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") .map_io = realview_pb1176_map_io, .init_early = realview_init_early, .init_irq = gic_init_irq, - .timer = &realview_pb1176_timer, - .handle_irq = gic_handle_irq, + .init_time = realview_pb1176_timer_init, .init_machine = realview_pb1176_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 7ed53d75350..c3cfe213b5e 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -27,13 +27,13 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-realview.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <asm/pgtable.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/smp_twd.h> @@ -316,10 +316,6 @@ static void __init realview_pb11mp_timer_init(void) realview_pb11mp_twd_init(); } -static struct sys_timer realview_pb11mp_timer = { - .init = realview_pb11mp_timer_init, -}; - static void realview_pb11mp_restart(char mode, const char *cmd) { void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); @@ -367,8 +363,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") .map_io = realview_pb11mp_map_io, .init_early = realview_init_early, .init_irq = gic_init_irq, - .timer = &realview_pb11mp_timer, - .handle_irq = gic_handle_irq, + .init_time = realview_pb11mp_timer_init, .init_machine = realview_pb11mp_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 9992431b8a1..dde652a5962 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -27,12 +27,12 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-realview.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <asm/pgtable.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -264,10 +264,6 @@ static void __init realview_pba8_timer_init(void) realview_timer_init(IRQ_PBA8_TIMER0_1); } -static struct sys_timer realview_pba8_timer = { - .init = realview_pba8_timer_init, -}; - static void realview_pba8_restart(char mode, const char *cmd) { void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL); @@ -308,8 +304,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") .map_io = realview_pba8_map_io, .init_early = realview_init_early, .init_irq = gic_init_irq, - .timer = &realview_pba8_timer, - .handle_irq = gic_handle_irq, + .init_time = realview_pba8_timer_init, .init_machine = realview_pba8_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M, diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 4f486f05108..54f0185b01e 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -26,13 +26,13 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-realview.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <asm/smp_twd.h> #include <asm/pgtable.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> @@ -324,10 +324,6 @@ static void __init realview_pbx_timer_init(void) realview_pbx_twd_init(); } -static struct sys_timer realview_pbx_timer = { - .init = realview_pbx_timer_init, -}; - static void realview_pbx_fixup(struct tag *tags, char **from, struct meminfo *meminfo) { @@ -404,8 +400,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") .map_io = realview_pbx_map_io, .init_early = realview_init_early, .init_irq = gic_init_irq, - .timer = &realview_pbx_timer, - .handle_irq = gic_handle_irq, + .init_time = realview_pbx_timer_init, .init_machine = realview_pbx_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M, diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h index 9cd9bcdad6c..0fd4b0b8ef2 100644 --- a/arch/arm/mach-rpc/include/mach/uncompress.h +++ b/arch/arm/mach-rpc/include/mach/uncompress.h @@ -189,8 +189,3 @@ static void arch_decomp_setup(void) if (nr_pages * page_size < 4096*1024) error("<4M of mem\n"); } #endif - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c index f3fa259ce01..a302cf5e0fc 100644 --- a/arch/arm/mach-rpc/riscpc.c +++ b/arch/arm/mach-rpc/riscpc.c @@ -211,7 +211,7 @@ static void rpc_restart(char mode, const char *cmd) soft_restart(0); } -extern struct sys_timer ioc_timer; +void ioc_timer_init(void); MACHINE_START(RISCPC, "Acorn-RiscPC") /* Maintainer: Russell King */ @@ -220,6 +220,6 @@ MACHINE_START(RISCPC, "Acorn-RiscPC") .reserve_lp1 = 1, .map_io = rpc_map_io, .init_irq = rpc_init_irq, - .timer = &ioc_timer, + .init_time = ioc_timer_init, .restart = rpc_restart, MACHINE_END diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c index 581fca934bb..9a6def14df0 100644 --- a/arch/arm/mach-rpc/time.c +++ b/arch/arm/mach-rpc/time.c @@ -24,7 +24,7 @@ #include <asm/mach/time.h> -unsigned long ioc_timer_gettimeoffset(void) +static u32 ioc_timer_gettimeoffset(void) { unsigned int count1, count2, status; long offset; @@ -56,7 +56,7 @@ unsigned long ioc_timer_gettimeoffset(void) } offset = (LATCH - offset) * (tick_nsec / 1000); - return (offset + LATCH/2) / LATCH; + return ((offset + LATCH/2) / LATCH) * 1000; } void __init ioctime_init(void) @@ -82,14 +82,9 @@ static struct irqaction ioc_timer_irq = { /* * Set up timer interrupt. */ -static void __init ioc_timer_init(void) +void __init ioc_timer_init(void) { + arch_gettimeoffset = ioc_timer_gettimeoffset; ioctime_init(); setup_irq(IRQ_TIMER0, &ioc_timer_irq); } - -struct sys_timer ioc_timer = { - .init = ioc_timer_init, - .offset = ioc_timer_gettimeoffset, -}; - diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig deleted file mode 100644 index 68d89cb96af..00000000000 --- a/arch/arm/mach-s3c2410/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -# cpu frequency scaling support - -config S3C2410_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX && CPU_S3C2410 - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2410 - -config S3C2410_PLLTABLE - bool - depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL - default y - help - Select the PLL table for the S3C2410 - diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile deleted file mode 100644 index 6b9a316e004..00000000000 --- a/arch/arm/mach-s3c2410/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# arch/arm/mach-s3c2410/Makefile -# -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o -obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o - diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig deleted file mode 100644 index 495f6928cba..00000000000 --- a/arch/arm/mach-s3c2412/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -# Note, the S3C2412 IOtiming support is in plat-s3c24xx - -config S3C2412_CPUFREQ - bool - depends on CPU_FREQ_S3C24XX && CPU_S3C2412 - default y - select S3C2412_IOTIMING - help - CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile deleted file mode 100644 index 41a6c279fb2..00000000000 --- a/arch/arm/mach-s3c2412/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# arch/arm/mach-s3c2412/Makefile -# -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c deleted file mode 100644 index 4526f6ba31a..00000000000 --- a/arch/arm/mach-s3c2412/gpio.c +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/mach-s3c2412/gpio.c - * - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://armlinux.simtec.co.uk/. - * - * S3C2412/S3C2413 specific GPIO support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/gpio.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include <mach/regs-gpio.h> -#include <mach/hardware.h> - -#include <plat/gpio-core.h> - -int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) -{ - struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); - unsigned long offs = pin - chip->chip.base; - unsigned long flags; - unsigned long slpcon; - - offs *= 2; - - if (pin < S3C2410_GPB(0)) - return -EINVAL; - - if (pin >= S3C2410_GPF(0) && - pin <= S3C2410_GPG(16)) - return -EINVAL; - - if (pin > S3C2410_GPH(16)) - return -EINVAL; - - local_irq_save(flags); - - slpcon = __raw_readl(chip->base + 0x0C); - - slpcon &= ~(3 << offs); - slpcon |= state << offs; - - __raw_writel(slpcon, chip->base + 0x0C); - - local_irq_restore(flags); - - return 0; -} - -EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg); diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig deleted file mode 100644 index a4d7fd27bec..00000000000 --- a/arch/arm/mach-s3c2440/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -config S3C2440_CPUFREQ - bool "S3C2440/S3C2442 CPU Frequency scaling support" - depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) - default y - select S3C2410_CPUFREQ_UTILS - help - CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. - -config S3C2440_XTAL_12000000 - bool - help - Indicate that the build needs to support 12MHz system - crystal. - -config S3C2440_XTAL_16934400 - bool - help - Indicate that the build needs to support 16.9344MHz system - crystal. - -config S3C2440_PLL_12000000 - bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 - default y if CPU_FREQ_S3C24XX_PLL - help - PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. - -config S3C2440_PLL_16934400 - bool - depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 - default y if CPU_FREQ_S3C24XX_PLL - help - PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile deleted file mode 100644 index c4609243981..00000000000 --- a/arch/arm/mach-s3c2440/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# arch/arm/mach-s3c2440/Makefile -# -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_CPU_S3C2440) += dsc.o - -obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o - -obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o -obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c deleted file mode 100644 index 9ea66e31f62..00000000000 --- a/arch/arm/mach-s3c2440/dsc.c +++ /dev/null @@ -1,54 +0,0 @@ -/* linux/arch/arm/mach-s3c2440/dsc.c - * - * Copyright (c) 2004-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Samsung S3C2440 Drive Strength Control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <mach/regs-gpio.h> -#include <mach/regs-dsc.h> - -#include <plat/cpu.h> -#include <plat/s3c244x.h> - -int s3c2440_set_dsc(unsigned int pin, unsigned int value) -{ - void __iomem *base; - unsigned long val; - unsigned long flags; - unsigned long mask; - - base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0; - mask = 3 << S3C2440_DSC_GETSHIFT(pin); - - local_irq_save(flags); - - val = __raw_readl(base); - val &= ~mask; - val |= value & mask; - __raw_writel(val, base); - - local_irq_restore(flags); - return 0; -} - -EXPORT_SYMBOL(s3c2440_set_dsc); diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 25df14a9e26..37f513d1588 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -9,6 +9,15 @@ if ARCH_S3C24XX +config PLAT_S3C24XX + def_bool y + select ARCH_REQUIRE_GPIOLIB + select NO_IOPORT + select S3C_DEV_NAND + select IRQ_DOMAIN + help + Base platform code for any Samsung S3C24XX device + menu "SAMSUNG S3C24XX SoCs Support" comment "S3C24XX SoCs" @@ -83,6 +92,17 @@ config CPU_S3C2443 # common code +config S3C2410_CLOCK + bool + help + Clock code for the S3C2410, and similar processors which + is currently includes the S3C2410, S3C2440, S3C2442. + +config S3C24XX_DCLK + bool + help + Clock code for supporting DCLK/CLKOUT on S3C24XX architectures + config S3C24XX_SMDK bool help @@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS help Compile in platform device definition for Samsung TouchScreen. +config S3C24XX_DMA + bool "S3C2410 DMA support" + depends on ARCH_S3C24XX + select S3C_DMA + help + S3C2410 DMA support. This is needed for drivers like sound which + use the S3C2410's DMA system to move data to and from the + peripheral blocks. + +config S3C2410_DMA_DEBUG + bool "S3C2410 DMA support debug" + depends on ARCH_S3C24XX && S3C2410_DMA + help + Enable debugging output for the DMA code. This option sends info + to the kernel log, at priority KERN_DEBUG. + config S3C2410_DMA bool depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) @@ -123,10 +159,92 @@ config S3C2410_PM help Power Management code common to S3C2410 and better +# low-level serial option nodes + +config CPU_LLSERIAL_S3C2410_ONLY + bool + default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 + +config CPU_LLSERIAL_S3C2440_ONLY + bool + default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 + +config CPU_LLSERIAL_S3C2410 + bool + help + Selected if there is an S3C2410 (or register compatible) serial + low-level implementation needed + +config CPU_LLSERIAL_S3C2440 + bool + help + Selected if there is an S3C2440 (or register compatible) serial + low-level implementation needed + +# gpio configurations + +config S3C24XX_GPIO_EXTRA + int + default 128 if S3C24XX_GPIO_EXTRA128 + default 64 if S3C24XX_GPIO_EXTRA64 + default 16 if ARCH_H1940 + default 0 + +config S3C24XX_GPIO_EXTRA64 + bool + help + Add an extra 64 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + +config S3C24XX_GPIO_EXTRA128 + bool + help + Add an extra 128 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + +# cpu frequency items common between s3c2410 and s3c2440/s3c2442 + +config S3C2410_IOTIMING + bool + depends on CPU_FREQ_S3C24XX + help + Internal node to select io timing code that is common to the s3c2410 + and s3c2440/s3c2442 cpu frequency support. + +config S3C2410_CPUFREQ_UTILS + bool + depends on CPU_FREQ_S3C24XX + help + Internal node to select timing code that is common to the s3c2410 + and s3c2440/s3c244 cpu frequency support. + +# cpu frequency support common to s3c2412, s3c2413 and s3c2442 + +config S3C2412_IOTIMING + bool + depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) + help + Intel node to select io timing code that is common to the s3c2412 + and the s3c2443. + # cpu-specific sections if CPU_S3C2410 +config S3C2410_CPUFREQ + bool + depends on CPU_FREQ_S3C24XX && CPU_S3C2410 + select S3C2410_CPUFREQ_UTILS + help + CPU Frequency scaling support for S3C2410 + +config S3C2410_PLL + bool + depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL + default y + help + Select the PLL table for the S3C2410 + config S3C24XX_SIMTEC_NOR bool help @@ -226,6 +344,7 @@ config MACH_QT2410 config ARCH_SMDK2410 bool "SMDK2410/A9M2410" select S3C24XX_SMDK + select S3C_DEV_USB_HOST help Say Y here if you are using the SMDK2410 or the derived module A9M2410 <http://www.fsforth.de> @@ -266,6 +385,14 @@ config CPU_S3C2412_ONLY !CPU_S3C2443 && CPU_S3C2412 default y +config S3C2412_CPUFREQ + bool + depends on CPU_FREQ_S3C24XX && CPU_S3C2412 + default y + select S3C2412_IOTIMING + help + CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs. + config S3C2412_DMA bool help @@ -273,6 +400,7 @@ config S3C2412_DMA config S3C2412_PM bool + select S3C2412_PM_SLEEP help Internal config node to apply S3C2412 power management @@ -291,8 +419,8 @@ config MACH_JIVE Say Y here if you are using the Logitech Jive. config MACH_JIVE_SHOW_BOOTLOADER - bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)" - depends on MACH_JIVE && EXPERIMENTAL + bool "Allow access to bootloader partitions in MTD" + depends on MACH_JIVE config MACH_S3C2413 bool @@ -365,11 +493,45 @@ endif # CPU_S3C2416 if CPU_S3C2440 +config S3C2440_CPUFREQ + bool "S3C2440/S3C2442 CPU Frequency scaling support" + depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442) + default y + select S3C2410_CPUFREQ_UTILS + help + CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs. + config S3C2440_DMA bool help Support for S3C2440 specific DMA code5A +config S3C2440_XTAL_12000000 + bool + help + Indicate that the build needs to support 12MHz system + crystal. + +config S3C2440_XTAL_16934400 + bool + help + Indicate that the build needs to support 16.9344MHz system + crystal. + +config S3C2440_PLL_12000000 + bool + depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 + default y if CPU_FREQ_S3C24XX_PLL + help + PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. + +config S3C2440_PLL_16934400 + bool + depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 + default y if CPU_FREQ_S3C24XX_PLL + help + PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. + comment "S3C2440 Boards" # diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 0ab6ab15da4..af53d27d5c3 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -14,26 +14,32 @@ obj- := # core -obj-y += common.o +obj-y += common.o irq.o obj-$(CONFIG_CPU_S3C2410) += s3c2410.o +obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o +obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o obj-$(CONFIG_CPU_S3C2412) += s3c2412.o irq-s3c2412.o clock-s3c2412.o +obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o -obj-$(CONFIG_CPU_S3C2416) += s3c2416.o irq-s3c2416.o clock-s3c2416.o +obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o obj-$(CONFIG_CPU_S3C2442) += s3c2442.o obj-$(CONFIG_CPU_S3C244X) += s3c244x.o irq-s3c244x.o clock-s3c244x.o +obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o +obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o +obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o -obj-$(CONFIG_CPU_S3C2443) += s3c2443.o irq-s3c2443.o clock-s3c2443.o +obj-$(CONFIG_CPU_S3C2443) += s3c2443.o clock-s3c2443.o # PM @@ -41,9 +47,21 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o # common code +obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o +obj-$(CONFIG_S3C24XX_DMA) += dma.o + +obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o +obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o + +obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o +obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o + obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o +obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o +obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o + # # machine support # following is ordered alphabetically by option text. diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c24xx/anubis.h new file mode 100644 index 00000000000..2691665f27d --- /dev/null +++ b/arch/arm/mach-s3c24xx/anubis.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2005 Simtec Electronics + * http://www.simtec.co.uk/products/ + * Ben Dooks <ben@simtec.co.uk> + * + * ANUBIS - CPLD control constants + * ANUBIS - IRQ Number definitions + * ANUBIS - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __MACH_S3C24XX_ANUBIS_H +#define __MACH_S3C24XX_ANUBIS_H __FILE__ + +/* CTRL2 - NAND WP control, IDE Reset assert/check */ + +#define ANUBIS_CTRL1_NANDSEL (0x3) + +/* IDREG - revision */ + +#define ANUBIS_IDREG_REVMASK (0x7) + +/* irq */ + +#define ANUBIS_IRQ_IDE0 IRQ_EINT2 +#define ANUBIS_IRQ_IDE1 IRQ_EINT3 +#define ANUBIS_IRQ_ASIX IRQ_EINT1 + +/* map */ + +/* start peripherals off after the S3C2410 */ + +#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) + +#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) + +/* we put the CPLD registers next, to get them out of the way */ + +#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) +#define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD + +#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) +#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23)) + +#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) +#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) +#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) +#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) + +#endif /* __MACH_S3C24XX_ANUBIS_H */ diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c index ba02cf8d80a..3f0288f2f54 100644 --- a/arch/arm/mach-s3c24xx/bast-ide.c +++ b/arch/arm/mach-s3c24xx/bast-ide.c @@ -25,8 +25,8 @@ #include <asm/mach/irq.h> #include <mach/map.h> -#include <mach/bast-map.h> -#include <mach/bast-irq.h> + +#include "bast.h" /* IDE ports */ @@ -34,12 +34,10 @@ static struct pata_platform_info bast_ide_platdata = { .ioport_shift = 5, }; -#define IDE_CS S3C2410_CS5 - static struct resource bast_ide0_resource[] = { - [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20), - [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20), - [2] = DEFINE_RES_IRQ(IRQ_IDE0), + [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20), + [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20), + [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0), }; static struct platform_device bast_device_ide0 = { @@ -55,9 +53,9 @@ static struct platform_device bast_device_ide0 = { }; static struct resource bast_ide1_resource[] = { - [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20), - [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20), - [2] = DEFINE_RES_IRQ(IRQ_IDE1), + [0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20), + [1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20), + [2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1), }; static struct platform_device bast_device_ide1 = { diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c index ac7b2ad5c40..c0daa9590b4 100644 --- a/arch/arm/mach-s3c24xx/bast-irq.c +++ b/arch/arm/mach-s3c24xx/bast-irq.c @@ -27,27 +27,20 @@ #include <linux/device.h> #include <linux/io.h> -#include <asm/mach-types.h> - -#include <mach/hardware.h> #include <asm/irq.h> - +#include <asm/mach-types.h> #include <asm/mach/irq.h> +#include <mach/hardware.h> #include <mach/regs-irq.h> -#include <mach/bast-map.h> -#include <mach/bast-irq.h> #include <plat/irq.h> -#if 0 -#include <asm/debug-ll.h> -#endif +#include "bast.h" #define irqdbf(x...) #define irqdbf2(x...) - /* handle PC104 ISA interrupts from the system CPLD */ /* table of ISA irq nos to the relevant mask... zero means @@ -87,7 +80,7 @@ bast_pc104_mask(struct irq_data *data) static void bast_pc104_maskack(struct irq_data *data) { - struct irq_desc *desc = irq_desc + IRQ_ISA; + struct irq_desc *desc = irq_desc + BAST_IRQ_ISA; bast_pc104_mask(data); desc->irq_data.chip->irq_ack(&desc->irq_data); @@ -122,7 +115,7 @@ bast_irq_pc104_demux(unsigned int irq, if (unlikely(stat == 0)) { /* ack if we get an irq with nothing (ie, startup) */ - desc = irq_desc + IRQ_ISA; + desc = irq_desc + BAST_IRQ_ISA; desc->irq_data.chip->irq_ack(&desc->irq_data); } else { /* handle the IRQ */ @@ -147,7 +140,7 @@ static __init int bast_irq_init(void) __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); - irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); + irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux); /* register our IRQs */ diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c24xx/bast.h new file mode 100644 index 00000000000..5c7534bae92 --- /dev/null +++ b/arch/arm/mach-s3c24xx/bast.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2003-2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * BAST - CPLD control constants + * BAST - IRQ Number definitions + * BAST - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __MACH_S3C24XX_BAST_H +#define __MACH_S3C24XX_BAST_H __FILE__ + +/* CTRL1 - Audio LR routing */ + +#define BAST_CPLD_CTRL1_LRCOFF (0x00) +#define BAST_CPLD_CTRL1_LRCADC (0x01) +#define BAST_CPLD_CTRL1_LRCDAC (0x02) +#define BAST_CPLD_CTRL1_LRCARM (0x03) +#define BAST_CPLD_CTRL1_LRMASK (0x03) + +/* CTRL2 - NAND WP control, IDE Reset assert/check */ + +#define BAST_CPLD_CTRL2_WNAND (0x04) +#define BAST_CPLD_CTLR2_IDERST (0x08) + +/* CTRL3 - rom write control, CPLD identity */ + +#define BAST_CPLD_CTRL3_IDMASK (0x0e) +#define BAST_CPLD_CTRL3_ROMWEN (0x01) + +/* CTRL4 - 8bit LCD interface control/status */ + +#define BAST_CPLD_CTRL4_LLAT (0x01) +#define BAST_CPLD_CTRL4_LCDRW (0x02) +#define BAST_CPLD_CTRL4_LCDCMD (0x04) +#define BAST_CPLD_CTRL4_LCDE2 (0x01) + +/* CTRL5 - DMA routing */ + +#define BAST_CPLD_DMA0_PRIIDE (0) +#define BAST_CPLD_DMA0_SECIDE (1) +#define BAST_CPLD_DMA0_ISA15 (2) +#define BAST_CPLD_DMA0_ISA36 (3) + +#define BAST_CPLD_DMA1_PRIIDE (0 << 2) +#define BAST_CPLD_DMA1_SECIDE (1 << 2) +#define BAST_CPLD_DMA1_ISA15 (2 << 2) +#define BAST_CPLD_DMA1_ISA36 (3 << 2) + +/* irq numbers to onboard peripherals */ + +#define BAST_IRQ_USBOC IRQ_EINT18 +#define BAST_IRQ_IDE0 IRQ_EINT16 +#define BAST_IRQ_IDE1 IRQ_EINT17 +#define BAST_IRQ_PCSERIAL1 IRQ_EINT15 +#define BAST_IRQ_PCSERIAL2 IRQ_EINT14 +#define BAST_IRQ_PCPARALLEL IRQ_EINT13 +#define BAST_IRQ_ASIX IRQ_EINT11 +#define BAST_IRQ_DM9000 IRQ_EINT10 +#define BAST_IRQ_ISA IRQ_EINT9 +#define BAST_IRQ_SMALERT IRQ_EINT8 + +/* map */ + +/* + * ok, we've used up to 0x13000000, now we need to find space for the + * peripherals that live in the nGCS[x] areas, which are quite numerous + * in their space. We also have the board's CPLD to find register space + * for. + */ + +#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) + +/* we put the CPLD registers next, to get them out of the way */ + +#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) +#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) + +#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) +#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) + +#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) +#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) + +#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) +#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) + +/* next, we have the PC104 ISA interrupt registers */ + +#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) +#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) + +#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) +#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) + +#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) +#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) + +#define BAST_PA_LCD_RCMD1 (0x8800000) +#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) + +#define BAST_PA_LCD_WCMD1 (0x8000000) +#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) + +#define BAST_PA_LCD_RDATA1 (0x9800000) +#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) + +#define BAST_PA_LCD_WDATA1 (0x9000000) +#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) + +#define BAST_PA_LCD_RCMD2 (0xA800000) +#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) + +#define BAST_PA_LCD_WCMD2 (0xA000000) +#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) + +#define BAST_PA_LCD_RDATA2 (0xB800000) +#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) + +#define BAST_PA_LCD_WDATA2 (0xB000000) +#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) + + +/* + * 0xE0000000 contains the IO space that is split by speed and + * whether the access is for 8 or 16bit IO... this ensures that + * the correct access is made + * + * 0x10000000 of space, partitioned as so: + * + * 0x00000000 to 0x04000000 8bit, slow + * 0x04000000 to 0x08000000 16bit, slow + * 0x08000000 to 0x0C000000 16bit, net + * 0x0C000000 to 0x10000000 16bit, fast + * + * each of these spaces has the following in: + * + * 0x00000000 to 0x01000000 16MB ISA IO space + * 0x01000000 to 0x02000000 16MB ISA memory space + * 0x02000000 to 0x02100000 1MB IDE primary channel + * 0x02100000 to 0x02200000 1MB IDE primary channel aux + * 0x02200000 to 0x02400000 1MB IDE secondary channel + * 0x02300000 to 0x02400000 1MB IDE secondary channel aux + * 0x02400000 to 0x02500000 1MB ASIX ethernet controller + * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller + * 0x02600000 to 0x02700000 1MB PC SuperIO controller + * + * the phyiscal layout of the zones are: + * nGCS2 - 8bit, slow + * nGCS3 - 16bit, slow + * nGCS4 - 16bit, net + * nGCS5 - 16bit, fast + */ + +#define BAST_VA_MULTISPACE (0xE0000000) + +#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) +#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) +#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) +#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) +#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) +#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) +#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) +#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) +#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) + +#define BAST_VAM_CS2 (0x00000000) +#define BAST_VAM_CS3 (0x04000000) +#define BAST_VAM_CS4 (0x08000000) +#define BAST_VAM_CS5 (0x0C000000) + +/* physical offset addresses for the peripherals */ + +#define BAST_PA_ISAIO (0x00000000) +#define BAST_PA_ASIXNET (0x01000000) +#define BAST_PA_SUPERIO (0x01800000) +#define BAST_PA_IDEPRI (0x02000000) +#define BAST_PA_IDEPRIAUX (0x02800000) +#define BAST_PA_IDESEC (0x03000000) +#define BAST_PA_IDESECAUX (0x03800000) +#define BAST_PA_ISAMEM (0x04000000) +#define BAST_PA_DM9000 (0x05000000) + +/* some configurations for the peripherals */ + +#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) + +#define BAST_ASIXNET_CS BAST_VAM_CS5 +#define BAST_DM9000_CS BAST_VAM_CS4 + +#define BAST_IDE_CS S3C2410_CS5 + +#endif /* __MACH_S3C24XX_BAST_H */ diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c index f95d3268ae1..1edd9b2369c 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/mach-s3c24xx/clock-dclk.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/clock-dclk.c - * +/* * Copyright (c) 2004-2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c index 25dc4d4397b..641266f3d15 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-clock.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/clock.c - * +/* * Copyright (c) 2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c index aeb4a24ff3e..f6b9f2ef01b 100644 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/arch/arm/mach-s3c24xx/common-s3c2443.c @@ -132,7 +132,7 @@ static struct clk *clk_msysclk_sources[] = { [3] = &clk_mpllref, }; -struct clksrc_clk clk_msysclk = { +static struct clksrc_clk clk_msysclk = { .clk = { .name = "msysclk", .parent = &clk_xtal, diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 0c9e9a785ef..6bcf87f65f9 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -197,7 +197,7 @@ static unsigned long s3c24xx_read_idcode_v4(void) static void s3c24xx_default_idle(void) { - unsigned long tmp; + unsigned long tmp = 0; int i; /* idle the system by using the idle mode which will wait for an diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index c2f596e7bc2..ed6276fcaa3 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h @@ -15,4 +15,6 @@ void s3c2410_restart(char mode, const char *cmd); void s3c244x_restart(char mode, const char *cmd); +extern struct syscore_ops s3c24xx_irq_syscore_ops; + #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c index c7adad0e8de..9b7b4289d66 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c +++ b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c - * +/* * Copyright (c) 2009 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c index 5404535da1a..cfa0dd8723e 100644 --- a/arch/arm/mach-s3c2410/cpu-freq.c +++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/cpu-freq.c - * +/* * Copyright (c) 2006-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -81,7 +80,7 @@ static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) cfg->divs.p_divisor = pdiv; cfg->divs.h_divisor = hdiv; - return 0 ; + return 0; } static struct s3c_cpufreq_info s3c2410_cpufreq_info = { @@ -131,7 +130,6 @@ static int __init s3c2410_cpufreq_init(void) { return subsys_interface_register(&s3c2410_cpufreq_interface); } - arch_initcall(s3c2410_cpufreq_init); static int s3c2410a_cpufreq_add(struct device *dev, @@ -159,5 +157,4 @@ static int __init s3c2410a_cpufreq_init(void) { return subsys_interface_register(&s3c2410a_cpufreq_interface); } - arch_initcall(s3c2410a_cpufreq_init); diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c index 125be7d5fa6..8bf0f3a7747 100644 --- a/arch/arm/mach-s3c2412/cpu-freq.c +++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2412/cpu-freq.c - * +/* * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -26,12 +25,13 @@ #include <asm/mach/map.h> #include <mach/regs-clock.h> -#include <mach/regs-s3c2412-mem.h> #include <plat/cpu.h> #include <plat/clock.h> #include <plat/cpu-freq-core.h> +#include "s3c2412.h" + /* our clock resources. */ static struct clk *xtal; static struct clk *fclk; @@ -111,7 +111,7 @@ static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) return 0; - invalid: +invalid: return -EINVAL; } @@ -255,5 +255,4 @@ static int s3c2412_cpufreq_init(void) { return subsys_interface_register(&s3c2412_cpufreq_interface); } - arch_initcall(s3c2412_cpufreq_init); diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c index 61776764d9f..72b2cc8a5a8 100644 --- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c +++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c - * +/* * Copyright (c) 2006-2009 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -310,5 +309,4 @@ static int s3c2442_cpufreq_init(void) { return subsys_interface_register(&s3c2442_cpufreq_interface); } - subsys_initcall(s3c2442_cpufreq_init); diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c index 43ea80190d8..ddd8280e387 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c +++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c - * +/* * Copyright (c) 2009 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -17,11 +16,12 @@ #include <linux/io.h> #include <mach/map.h> -#include <mach/regs-mem.h> #include <mach/regs-clock.h> #include <plat/cpu-freq-core.h> +#include "regs-mem.h" + /** * s3c2410_cpufreq_setrefresh - set SDRAM refresh value * @cfg: The frequency configuration diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq.c index 46807993888..5f181e733ee 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/mach-s3c24xx/cpufreq.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/cpu-freq.c - * +/* * Copyright (c) 2006-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c index 4803338cf56..25d085adc93 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2410.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c @@ -27,7 +27,6 @@ #include <mach/regs-gpio.h> #include <plat/regs-ac97.h> #include <plat/regs-dma.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <plat/regs-iis.h> diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c index 38472ac920f..d2408ba372c 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -27,7 +27,6 @@ #include <mach/regs-gpio.h> #include <plat/regs-ac97.h> #include <plat/regs-dma.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <plat/regs-iis.h> diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c index 5f0a0c8ef84..0b86e74d104 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2440.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c @@ -27,7 +27,6 @@ #include <mach/regs-gpio.h> #include <plat/regs-ac97.h> #include <plat/regs-dma.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <plat/regs-iis.h> diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index 2d94228d286..05536254a3f 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -27,7 +27,6 @@ #include <mach/regs-gpio.h> #include <plat/regs-ac97.h> #include <plat/regs-dma.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <plat/regs-iis.h> diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c index ba3e76c9550..aab64909e9a 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/mach-s3c24xx/dma.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/dma.c - * +/* * Copyright 2003-2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/gta02.h index 21739348215..9430a71e918 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gta02.h +++ b/arch/arm/mach-s3c24xx/gta02.h @@ -1,5 +1,13 @@ -#ifndef _GTA02_H -#define _GTA02_H +/* + * GTA02 header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __MACH_S3C24XX_GTA02_H +#define __MACH_S3C24XX_GTA02_H __FILE__ #include <mach/regs-gpio.h> @@ -12,4 +20,4 @@ #define GTA02_IRQ_PCF50633 IRQ_EINT9 -#endif /* _GTA02_H */ +#endif /* __MACH_S3C24XX_GTA02_H */ diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c index 3f40c61b6e0..5b98bfd1df4 100644 --- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c +++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c @@ -19,10 +19,10 @@ #include <linux/gpio.h> #include <linux/rfkill.h> -#include <mach/regs-gpio.h> #include <mach/hardware.h> -#include <mach/h1940-latch.h> -#include <mach/h1940.h> +#include <mach/regs-gpio.h> + +#include "h1940.h" #define DRV_NAME "h1940-bt" diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/h1940.h index fc897d3a056..2950cc46684 100644 --- a/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h +++ b/arch/arm/mach-s3c24xx/h1940.h @@ -1,20 +1,30 @@ -/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h +/* + * Copyright 2006 Ben Dooks <ben-linux@fluff.org> * * Copyright (c) 2005 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * - * iPAQ H1940 series - latch definitions + * iPAQ H1940 series definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_H1940_LATCH_H -#define __ASM_ARCH_H1940_LATCH_H +#ifndef __MACH_S3C24XX_H1940_H +#define __MACH_S3C24XX_H1940_H __FILE__ -#include <asm/gpio.h> +#define H1940_SUSPEND_CHECKSUM (0x30003ff8) +#define H1940_SUSPEND_RESUMEAT (0x30081000) +#define H1940_SUSPEND_CHECK (0x30080000) + +extern void h1940_pm_return(void); +extern int h1940_led_blink_set(unsigned gpio, int state, + unsigned long *delay_on, + unsigned long *delay_off); + +#include <linux/gpio.h> #define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x)) @@ -40,4 +50,4 @@ #define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14) #define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15) -#endif /* __ASM_ARCH_H1940_LATCH_H */ +#endif /* __MACH_S3C24XX_H1940_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h deleted file mode 100644 index 1b614d5a81f..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_ANUBISCPLD_H -#define __ASM_ARCH_ANUBISCPLD_H - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define ANUBIS_CTRL1_NANDSEL (0x3) - -/* IDREG - revision */ - -#define ANUBIS_IDREG_REVMASK (0x7) - -#endif /* __ASM_ARCH_ANUBISCPLD_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h deleted file mode 100644 index a2a328134e3..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_ANUBISIRQ_H -#define __ASM_ARCH_ANUBISIRQ_H - -#define IRQ_IDE0 IRQ_EINT2 -#define IRQ_IDE1 IRQ_EINT3 -#define IRQ_ASIX IRQ_EINT1 - -#endif /* __ASM_ARCH_ANUBISIRQ_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h deleted file mode 100644 index c9deb3a5b2c..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/anubis-map.h +++ /dev/null @@ -1,38 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/anubis-map.h - * - * Copyright (c) 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * ANUBIS - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -#ifndef __ASM_ARCH_ANUBISMAP_H -#define __ASM_ARCH_ANUBISMAP_H - -/* start peripherals off after the S3C2410 */ - -#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) - -#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ -#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) - -#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ -#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23)) - -#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) -#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) -#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) -#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) - -#endif /* __ASM_ARCH_ANUBISMAP_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h deleted file mode 100644 index bee2a7a932a..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * BAST - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTCPLD_H -#define __ASM_ARCH_BASTCPLD_H - -/* CTRL1 - Audio LR routing */ - -#define BAST_CPLD_CTRL1_LRCOFF (0x00) -#define BAST_CPLD_CTRL1_LRCADC (0x01) -#define BAST_CPLD_CTRL1_LRCDAC (0x02) -#define BAST_CPLD_CTRL1_LRCARM (0x03) -#define BAST_CPLD_CTRL1_LRMASK (0x03) - -/* CTRL2 - NAND WP control, IDE Reset assert/check */ - -#define BAST_CPLD_CTRL2_WNAND (0x04) -#define BAST_CPLD_CTLR2_IDERST (0x08) - -/* CTRL3 - rom write control, CPLD identity */ - -#define BAST_CPLD_CTRL3_IDMASK (0x0e) -#define BAST_CPLD_CTRL3_ROMWEN (0x01) - -/* CTRL4 - 8bit LCD interface control/status */ - -#define BAST_CPLD_CTRL4_LLAT (0x01) -#define BAST_CPLD_CTRL4_LCDRW (0x02) -#define BAST_CPLD_CTRL4_LCDCMD (0x04) -#define BAST_CPLD_CTRL4_LCDE2 (0x01) - -/* CTRL5 - DMA routing */ - -#define BAST_CPLD_DMA0_PRIIDE (0<<0) -#define BAST_CPLD_DMA0_SECIDE (1<<0) -#define BAST_CPLD_DMA0_ISA15 (2<<0) -#define BAST_CPLD_DMA0_ISA36 (3<<0) - -#define BAST_CPLD_DMA1_PRIIDE (0<<2) -#define BAST_CPLD_DMA1_SECIDE (1<<2) -#define BAST_CPLD_DMA1_ISA15 (2<<2) -#define BAST_CPLD_DMA1_ISA36 (3<<2) - -#endif /* __ASM_ARCH_BASTCPLD_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h deleted file mode 100644 index cac428c42e7..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/bast-irq.h +++ /dev/null @@ -1,29 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-irq.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine BAST - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BASTIRQ_H -#define __ASM_ARCH_BASTIRQ_H - -/* irq numbers to onboard peripherals */ - -#define IRQ_USBOC IRQ_EINT18 -#define IRQ_IDE0 IRQ_EINT16 -#define IRQ_IDE1 IRQ_EINT17 -#define IRQ_PCSERIAL1 IRQ_EINT15 -#define IRQ_PCSERIAL2 IRQ_EINT14 -#define IRQ_PCPARALLEL IRQ_EINT13 -#define IRQ_ASIX IRQ_EINT11 -#define IRQ_DM9000 IRQ_EINT10 -#define IRQ_ISA IRQ_EINT9 -#define IRQ_SMALERT IRQ_EINT8 - -#endif /* __ASM_ARCH_BASTIRQ_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h deleted file mode 100644 index eecea2a50f8..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/bast-map.h +++ /dev/null @@ -1,146 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/bast-map.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine BAST - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#ifndef __ASM_ARCH_BASTMAP_H -#define __ASM_ARCH_BASTMAP_H - -#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) - -/* we put the CPLD registers next, to get them out of the way */ - -#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */ -#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */ -#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */ -#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */ -#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ -#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) - -#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ -#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) - -#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ -#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) - -#define BAST_PA_LCD_RCMD1 (0x8800000) -#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) - -#define BAST_PA_LCD_WCMD1 (0x8000000) -#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) - -#define BAST_PA_LCD_RDATA1 (0x9800000) -#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) - -#define BAST_PA_LCD_WDATA1 (0x9000000) -#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) - -#define BAST_PA_LCD_RCMD2 (0xA800000) -#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) - -#define BAST_PA_LCD_WCMD2 (0xA000000) -#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) - -#define BAST_PA_LCD_RDATA2 (0xB800000) -#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) - -#define BAST_PA_LCD_WDATA2 (0xB000000) -#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) - - -/* 0xE0000000 contains the IO space that is split by speed and - * whether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x00000000 to 0x01000000 16MB ISA IO space - * 0x01000000 to 0x02000000 16MB ISA memory space - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02400000 to 0x02500000 1MB ASIX ethernet controller - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller - * 0x02600000 to 0x02700000 1MB PC SuperIO controller - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) -#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) -#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) -#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) -#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) -#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) -#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) -#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) -#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) - -#define BAST_VA_MULTISPACE (0xE0000000) - -#define BAST_VAM_CS2 (0x00000000) -#define BAST_VAM_CS3 (0x04000000) -#define BAST_VAM_CS4 (0x08000000) -#define BAST_VAM_CS5 (0x0C000000) - -/* physical offset addresses for the peripherals */ - -#define BAST_PA_ISAIO (0x00000000) -#define BAST_PA_ASIXNET (0x01000000) -#define BAST_PA_SUPERIO (0x01800000) -#define BAST_PA_IDEPRI (0x02000000) -#define BAST_PA_IDEPRIAUX (0x02800000) -#define BAST_PA_IDESEC (0x03000000) -#define BAST_PA_IDESECAUX (0x03800000) -#define BAST_PA_ISAMEM (0x04000000) -#define BAST_PA_DM9000 (0x05000000) - -/* some configurations for the peripherals */ - -#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) -/* */ - -#define BAST_ASIXNET_CS BAST_VAM_CS5 -#define BAST_IDE_CS BAST_VAM_CS5 -#define BAST_DM9000_CS BAST_VAM_CS4 - -#endif /* __ASM_ARCH_BASTMAP_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S index 4135de87d1f..13ed33c6911 100644 --- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S +++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S @@ -40,17 +40,17 @@ addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) bic \rd, \rd, #0xff000 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] + ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] and \rd, \rd, #0x00ff0000 teq \rd, #0x00440000 @ is it 2440? 1004: - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] moveq \rd, \rd, lsr #SHIFT_2440TXF tst \rd, #S3C2410_UFSTAT_TXFULL .endm .macro fifo_full_s3c2410 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] tst \rd, #S3C2410_UFSTAT_TXFULL .endm @@ -68,18 +68,18 @@ addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) bic \rd, \rd, #0xff000 - ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] + ldr \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)] and \rd, \rd, #0x00ff0000 teq \rd, #0x00440000 @ is it 2440? 10000: - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] andne \rd, \rd, #S3C2410_UFSTAT_TXMASK andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK .endm .macro fifo_level_s3c2410 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] and \rd, \rd, #S3C2410_UFSTAT_TXMASK .endm diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S index 7615a14773f..6a21beeba1d 100644 --- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S +++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S @@ -31,10 +31,10 @@ @@ try the interrupt offset register, since it is there - ldr \irqstat, [ \base, #INTPND ] + ldr \irqstat, [\base, #INTPND ] teq \irqstat, #0 beq 1002f - ldr \irqnr, [ \base, #INTOFFSET ] + ldr \irqnr, [\base, #INTOFFSET ] mov \tmp, #1 tst \irqstat, \tmp, lsl \irqnr bne 1001f diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h deleted file mode 100644 index c53ad34c657..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h +++ /dev/null @@ -1 +0,0 @@ -#include <plat/gpio-fns.h> diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h deleted file mode 100644 index 3890a05948f..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - GPIO bank numbering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __MACH_GPIONRS_H -#define __MACH_GPIONRS_H - -#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) - -#define S3C2410_GPIO_BANKG (32*6) -#define S3C2410_GPIO_BANKH (32*7) - -/* GPIO sizes for various SoCs: - * - * 2442 - * 2410 2412 2440 2443 2416 - * ---- ---- ---- ---- ---- - * A 23 22 25 16 25 - * B 11 11 11 11 9 - * C 16 15 16 16 16 - * D 16 16 16 16 16 - * E 16 16 16 16 16 - * F 8 8 8 8 8 - * G 16 16 16 16 8 - * H 11 11 9 15 15 - * J -- -- 13 16 -- - * K -- -- -- -- 16 - * L -- -- -- 15 7 - * M -- -- -- 2 2 - */ - -/* GPIO bank sizes */ -#define S3C2410_GPIO_A_NR (32) -#define S3C2410_GPIO_B_NR (32) -#define S3C2410_GPIO_C_NR (32) -#define S3C2410_GPIO_D_NR (32) -#define S3C2410_GPIO_E_NR (32) -#define S3C2410_GPIO_F_NR (32) -#define S3C2410_GPIO_G_NR (32) -#define S3C2410_GPIO_H_NR (32) -#define S3C2410_GPIO_J_NR (32) /* technically 16. */ -#define S3C2410_GPIO_K_NR (32) /* technically 16. */ -#define S3C2410_GPIO_L_NR (32) /* technically 15. */ -#define S3C2410_GPIO_M_NR (32) /* technically 2. */ - -#if CONFIG_S3C_GPIO_SPACE != 0 -#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment -#endif - -#define S3C2410_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) - -#ifndef __ASSEMBLY__ - -enum s3c_gpio_number { - S3C2410_GPIO_A_START = 0, - S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), - S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), - S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), - S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), - S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), - S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), - S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), - S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), - S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), - S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), - S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), -}; - -#endif /* __ASSEMBLY__ */ - -/* S3C2410 GPIO number definitions. */ - -#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) -#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) -#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) -#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) -#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) -#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) -#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) -#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) -#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) -#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) -#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) -#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) - -#endif /* __MACH_GPIONRS_H */ - diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h deleted file mode 100644 index c410a078622..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-track.h +++ /dev/null @@ -1,33 +0,0 @@ -/* arch/arm/mach-s3c24100/include/mach/gpio-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C2410 - GPIO core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -#include <mach/regs-gpio.h> - -extern struct samsung_gpio_chip s3c24xx_gpios[]; - -static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) -{ - struct samsung_gpio_chip *chip; - - if (pin > S3C_GPIO_END) - return NULL; - - chip = &s3c24xx_gpios[pin/32]; - return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; -} - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h index 6fac70f3484..14591563ca7 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio.h - * +/* * Copyright (c) 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -15,6 +14,9 @@ * devices that need GPIO. */ +#ifndef __MACH_GPIO_H +#define __MACH_GPIO_H __FILE__ + #ifdef CONFIG_CPU_S3C244X #define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA) #elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) @@ -23,8 +25,83 @@ #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) #endif -#include <mach/gpio-nrs.h> -#include <mach/gpio-fns.h> +/* + * GPIO sizes for various SoCs: + * + * 2410 2412 2440 2443 2416 + * 2442 + * ---- ---- ---- ---- ---- + * A 23 22 25 16 25 + * B 11 11 11 11 9 + * C 16 15 16 16 16 + * D 16 16 16 16 16 + * E 16 16 16 16 16 + * F 8 8 8 8 8 + * G 16 16 16 16 8 + * H 11 11 9 15 15 + * J -- -- 13 16 -- + * K -- -- -- -- 16 + * L -- -- -- 15 7 + * M -- -- -- 2 2 + */ + +/* GPIO bank sizes */ + +#define S3C2410_GPIO_A_NR (32) +#define S3C2410_GPIO_B_NR (32) +#define S3C2410_GPIO_C_NR (32) +#define S3C2410_GPIO_D_NR (32) +#define S3C2410_GPIO_E_NR (32) +#define S3C2410_GPIO_F_NR (32) +#define S3C2410_GPIO_G_NR (32) +#define S3C2410_GPIO_H_NR (32) +#define S3C2410_GPIO_J_NR (32) /* technically 16. */ +#define S3C2410_GPIO_K_NR (32) /* technically 16. */ +#define S3C2410_GPIO_L_NR (32) /* technically 15. */ +#define S3C2410_GPIO_M_NR (32) /* technically 2. */ + +#if CONFIG_S3C_GPIO_SPACE != 0 +#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment +#endif + +#define S3C2410_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) + +#ifndef __ASSEMBLY__ + +enum s3c_gpio_number { + S3C2410_GPIO_A_START = 0, + S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), + S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), + S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), + S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), + S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), + S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), + S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), + S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H), + S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J), + S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K), + S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L), +}; + +#endif /* __ASSEMBLY__ */ + +/* S3C2410 GPIO number definitions. */ + +#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) +#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) +#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) +#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) +#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) +#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) +#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) +#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) +#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr)) +#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr)) +#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) +#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) + +#include <plat/gpio-cfg.h> #ifdef CONFIG_CPU_S3C244X #define S3C_GPIO_END (S3C2410_GPJ(0) + 32) @@ -33,3 +110,5 @@ #else #define S3C_GPIO_END (S3C2410_GPH(0) + 32) #endif + +#endif /* __MACH_GPIO_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h deleted file mode 100644 index 2aa683c8d3d..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/h1940.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/h1940.h - * - * Copyright 2006 Ben Dooks <ben-linux@fluff.org> - * - * H1940 definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_H1940_H -#define __ASM_ARCH_H1940_H - -#define H1940_SUSPEND_CHECKSUM (0x30003ff8) -#define H1940_SUSPEND_RESUMEAT (0x30081000) -#define H1940_SUSPEND_CHECK (0x30080000) - -extern void h1940_pm_return(void); -extern int h1940_led_blink_set(unsigned gpio, int state, - unsigned long *delay_on, unsigned long *delay_off); - - -#endif /* __ASM_ARCH_H1940_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h index aef5631eac5..a6cc14a092f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/hardware.h +++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h @@ -23,12 +23,6 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); #endif /* CONFIG_CPU_S3C2440 */ -#ifdef CONFIG_CPU_S3C2412 - -extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state); - -#endif /* CONFIG_CPU_S3C2412 */ - #endif /* __ASSEMBLY__ */ #include <asm/sizes.h> diff --git a/arch/arm/mach-s3c24xx/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h deleted file mode 100644 index e9ddd706b16..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/idle.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/idle.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 CPU Idle controls -*/ - -#ifndef __ASM_ARCH_IDLE_H -#define __ASM_ARCH_IDLE_H __FILE__ - -/* This allows the over-ride of the default idle code, in case there - * is any other things to be done over idle (like DVS) -*/ - -extern void (*s3c24xx_idle)(void); - -extern void s3c24xx_default_idle(void); - -#endif /* __ASM_ARCH_IDLE_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h deleted file mode 100644 index e9e36b0abba..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h - * - * Copyright 2005 Simtec Electronics - * http://www.simtec.co.uk/products/ - * Ben Dooks <ben@simtec.co.uk> - * - * OSIRIS - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_OSIRISCPLD_H -#define __ASM_ARCH_OSIRISCPLD_H - -/* CTRL0 - NAND WP control */ - -#define OSIRIS_CTRL0_NANDSEL (0x3) -#define OSIRIS_CTRL0_BOOT_INT (1<<3) -#define OSIRIS_CTRL0_PCMCIA (1<<4) -#define OSIRIS_CTRL0_FIX8 (1<<5) -#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) -#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) - -#define OSIRIS_CTRL1_FIX8 (1<<0) - -#define OSIRIS_ID_REVMASK (0x7) - -#endif /* __ASM_ARCH_OSIRISCPLD_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h index a11a638bd59..c2ef016032a 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h @@ -14,8 +14,6 @@ #ifndef __ASM_ARCH_REGS_GPIO_H #define __ASM_ARCH_REGS_GPIO_H -#include <mach/gpio-nrs.h> - #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) /* general configuration options */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h deleted file mode 100644 index e0c67b0163d..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h +++ /dev/null @@ -1,202 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-mem.h - * - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Memory Control register definitions -*/ - -#ifndef __ASM_ARM_MEMREGS_H -#define __ASM_ARM_MEMREGS_H - -#ifndef S3C2410_MEMREG -#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif - -/* bus width, and wait state control */ -#define S3C2410_BWSCON S3C2410_MEMREG(0x0000) - -/* bank zero config - note, pinstrapped from OM pins! */ -#define S3C2410_BWSCON_DW0_16 (1<<1) -#define S3C2410_BWSCON_DW0_32 (2<<1) - -/* bank one configs */ -#define S3C2410_BWSCON_DW1_8 (0<<4) -#define S3C2410_BWSCON_DW1_16 (1<<4) -#define S3C2410_BWSCON_DW1_32 (2<<4) -#define S3C2410_BWSCON_WS1 (1<<6) -#define S3C2410_BWSCON_ST1 (1<<7) - -/* bank 2 configurations */ -#define S3C2410_BWSCON_DW2_8 (0<<8) -#define S3C2410_BWSCON_DW2_16 (1<<8) -#define S3C2410_BWSCON_DW2_32 (2<<8) -#define S3C2410_BWSCON_WS2 (1<<10) -#define S3C2410_BWSCON_ST2 (1<<11) - -/* bank 3 configurations */ -#define S3C2410_BWSCON_DW3_8 (0<<12) -#define S3C2410_BWSCON_DW3_16 (1<<12) -#define S3C2410_BWSCON_DW3_32 (2<<12) -#define S3C2410_BWSCON_WS3 (1<<14) -#define S3C2410_BWSCON_ST3 (1<<15) - -/* bank 4 configurations */ -#define S3C2410_BWSCON_DW4_8 (0<<16) -#define S3C2410_BWSCON_DW4_16 (1<<16) -#define S3C2410_BWSCON_DW4_32 (2<<16) -#define S3C2410_BWSCON_WS4 (1<<18) -#define S3C2410_BWSCON_ST4 (1<<19) - -/* bank 5 configurations */ -#define S3C2410_BWSCON_DW5_8 (0<<20) -#define S3C2410_BWSCON_DW5_16 (1<<20) -#define S3C2410_BWSCON_DW5_32 (2<<20) -#define S3C2410_BWSCON_WS5 (1<<22) -#define S3C2410_BWSCON_ST5 (1<<23) - -/* bank 6 configurations */ -#define S3C2410_BWSCON_DW6_8 (0<<24) -#define S3C2410_BWSCON_DW6_16 (1<<24) -#define S3C2410_BWSCON_DW6_32 (2<<24) -#define S3C2410_BWSCON_WS6 (1<<26) -#define S3C2410_BWSCON_ST6 (1<<27) - -/* bank 7 configurations */ -#define S3C2410_BWSCON_DW7_8 (0<<28) -#define S3C2410_BWSCON_DW7_16 (1<<28) -#define S3C2410_BWSCON_DW7_32 (2<<28) -#define S3C2410_BWSCON_WS7 (1<<30) -#define S3C2410_BWSCON_ST7 (1<<31) - -/* accesor functions for getting BANK(n) configuration. (n != 0) */ - -#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) - -#define S3C2410_BWSCON_DW8 (0) -#define S3C2410_BWSCON_DW16 (1) -#define S3C2410_BWSCON_DW32 (2) -#define S3C2410_BWSCON_WS (1 << 2) -#define S3C2410_BWSCON_ST (1 << 3) - -/* memory set (rom, ram) */ -#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) -#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) -#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C) -#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010) -#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014) -#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018) -#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C) -#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020) - -/* bank configuration registers */ - -#define S3C2410_BANKCON_PMCnorm (0x00) -#define S3C2410_BANKCON_PMC4 (0x01) -#define S3C2410_BANKCON_PMC8 (0x02) -#define S3C2410_BANKCON_PMC16 (0x03) - -/* bank configurations for banks 0..7, note banks - * 6 and 7 have different configurations depending on - * the memory type bits */ - -#define S3C2410_BANKCON_Tacp2 (0x0 << 2) -#define S3C2410_BANKCON_Tacp3 (0x1 << 2) -#define S3C2410_BANKCON_Tacp4 (0x2 << 2) -#define S3C2410_BANKCON_Tacp6 (0x3 << 2) -#define S3C2410_BANKCON_Tacp_SHIFT (2) - -#define S3C2410_BANKCON_Tcah0 (0x0 << 4) -#define S3C2410_BANKCON_Tcah1 (0x1 << 4) -#define S3C2410_BANKCON_Tcah2 (0x2 << 4) -#define S3C2410_BANKCON_Tcah4 (0x3 << 4) -#define S3C2410_BANKCON_Tcah_SHIFT (4) - -#define S3C2410_BANKCON_Tcoh0 (0x0 << 6) -#define S3C2410_BANKCON_Tcoh1 (0x1 << 6) -#define S3C2410_BANKCON_Tcoh2 (0x2 << 6) -#define S3C2410_BANKCON_Tcoh4 (0x3 << 6) -#define S3C2410_BANKCON_Tcoh_SHIFT (6) - -#define S3C2410_BANKCON_Tacc1 (0x0 << 8) -#define S3C2410_BANKCON_Tacc2 (0x1 << 8) -#define S3C2410_BANKCON_Tacc3 (0x2 << 8) -#define S3C2410_BANKCON_Tacc4 (0x3 << 8) -#define S3C2410_BANKCON_Tacc6 (0x4 << 8) -#define S3C2410_BANKCON_Tacc8 (0x5 << 8) -#define S3C2410_BANKCON_Tacc10 (0x6 << 8) -#define S3C2410_BANKCON_Tacc14 (0x7 << 8) -#define S3C2410_BANKCON_Tacc_SHIFT (8) - -#define S3C2410_BANKCON_Tcos0 (0x0 << 11) -#define S3C2410_BANKCON_Tcos1 (0x1 << 11) -#define S3C2410_BANKCON_Tcos2 (0x2 << 11) -#define S3C2410_BANKCON_Tcos4 (0x3 << 11) -#define S3C2410_BANKCON_Tcos_SHIFT (11) - -#define S3C2410_BANKCON_Tacs0 (0x0 << 13) -#define S3C2410_BANKCON_Tacs1 (0x1 << 13) -#define S3C2410_BANKCON_Tacs2 (0x2 << 13) -#define S3C2410_BANKCON_Tacs4 (0x3 << 13) -#define S3C2410_BANKCON_Tacs_SHIFT (13) - -#define S3C2410_BANKCON_SRAM (0x0 << 15) -#define S3C2410_BANKCON_SDRAM (0x3 << 15) - -/* next bits only for SDRAM in 6,7 */ -#define S3C2410_BANKCON_Trcd2 (0x00 << 2) -#define S3C2410_BANKCON_Trcd3 (0x01 << 2) -#define S3C2410_BANKCON_Trcd4 (0x02 << 2) - -/* control column address select */ -#define S3C2410_BANKCON_SCANb8 (0x00 << 0) -#define S3C2410_BANKCON_SCANb9 (0x01 << 0) -#define S3C2410_BANKCON_SCANb10 (0x02 << 0) - -#define S3C2410_REFRESH S3C2410_MEMREG(0x0024) -#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028) -#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C) -#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030) - -/* refresh control */ - -#define S3C2410_REFRESH_REFEN (1<<23) -#define S3C2410_REFRESH_SELF (1<<22) -#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1) - -#define S3C2410_REFRESH_TRP_MASK (3<<20) -#define S3C2410_REFRESH_TRP_2clk (0<<20) -#define S3C2410_REFRESH_TRP_3clk (1<<20) -#define S3C2410_REFRESH_TRP_4clk (2<<20) - -#define S3C2410_REFRESH_TSRC_MASK (3<<18) -#define S3C2410_REFRESH_TSRC_4clk (0<<18) -#define S3C2410_REFRESH_TSRC_5clk (1<<18) -#define S3C2410_REFRESH_TSRC_6clk (2<<18) -#define S3C2410_REFRESH_TSRC_7clk (3<<18) - - -/* mode select register(s) */ - -#define S3C2410_MRSRB_CL1 (0x00 << 4) -#define S3C2410_MRSRB_CL2 (0x02 << 4) -#define S3C2410_MRSRB_CL3 (0x03 << 4) - -/* bank size register */ -#define S3C2410_BANKSIZE_128M (0x2 << 0) -#define S3C2410_BANKSIZE_64M (0x1 << 0) -#define S3C2410_BANKSIZE_32M (0x0 << 0) -#define S3C2410_BANKSIZE_16M (0x7 << 0) -#define S3C2410_BANKSIZE_8M (0x6 << 0) -#define S3C2410_BANKSIZE_4M (0x5 << 0) -#define S3C2410_BANKSIZE_2M (0x4 << 0) -#define S3C2410_BANKSIZE_MASK (0x7 << 0) -#define S3C2410_BANKSIZE_SCLK_EN (1<<4) -#define S3C2410_BANKSIZE_SCKE_EN (1<<5) -#define S3C2410_BANKSIZE_BURST (1<<7) - -#endif /* __ASM_ARM_MEMREGS_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h deleted file mode 100644 index 4932b87bdf3..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-power.h +++ /dev/null @@ -1,40 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-power.h - * - * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C24XX power control register definitions -*/ - -#ifndef __ASM_ARM_REGS_PWR -#define __ASM_ARM_REGS_PWR __FILE__ - -#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) - -#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) -#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) - -#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) -#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) -#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) -#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) - -#define S3C2412_PWRCFG_BATF_IRQ (1<<0) -#define S3C2412_PWRCFG_BATF_IGNORE (2<<0) -#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) -#define S3C2412_PWRCFG_BATF_MASK (3<<0) - -#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) -#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) -#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) -#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) -#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) - -#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) -#define S3C2412_PWRCFG_NAND_NORST (1<<9) - -#endif /* __ASM_ARM_REGS_PWR */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h deleted file mode 100644 index fb635251509..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h +++ /dev/null @@ -1,48 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2412_MEM -#define __ASM_ARM_REGS_S3C2412_MEM - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_BANKCFG S3C2412_MEMREG(0x00) -#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) -#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) -#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) -#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) - -/* EBI control registers */ - -#define S3C2412_EBI_PR S3C2412_EBIREG(0x00) -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) - -/* SSMC control registers */ - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) -#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) -#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) -#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) -#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) -#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) -#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) - -#endif /* __ASM_ARM_REGS_S3C2412_MEM */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h deleted file mode 100644 index aa69dc79bc3..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h +++ /dev/null @@ -1,23 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h - * - * Copyright 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 specific register definitions -*/ - -#ifndef __ASM_ARCH_REGS_S3C2412_H -#define __ASM_ARCH_REGS_S3C2412_H "s3c2412" - -#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) -#define S3C2412_SWRST_RESET (0x533C2412) - -/* see regs-power.h for the other registers in the power block. */ - -#endif /* __ASM_ARCH_REGS_S3C2412_H */ - diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h deleted file mode 100644 index 2f31b74974a..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h +++ /dev/null @@ -1,30 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2416 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2416_MEM -#define __ASM_ARM_REGS_S3C2416_MEM - -#ifndef S3C2416_MEMREG -#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#endif - -#define S3C2416_BANKCFG S3C2416_MEMREG(0x00) -#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04) -#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08) -#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C) - -#define S3C2416_REFRESH S3C2416_MEMREG(0x10) -#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14) - -#endif /* __ASM_ARM_REGS_S3C2416_MEM */ diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h deleted file mode 100644 index e443167efb8..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h +++ /dev/null @@ -1,24 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2416 specific register definitions -*/ - -#ifndef __ASM_ARCH_REGS_S3C2416_H -#define __ASM_ARCH_REGS_S3C2416_H "s3c2416" - -#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44) -#define S3C2416_SWRST_RESET (0x533C2416) - -/* see regs-power.h for the other registers in the power block. */ - -#endif /* __ASM_ARCH_REGS_S3C2416_H */ - diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h deleted file mode 100644 index e4119913d7c..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h - * - * Copyright (c) 2003 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * VR1000 - CPLD control constants - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VR1000CPLD_H -#define __ASM_ARCH_VR1000CPLD_H - -#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ - -#endif /* __ASM_ARCH_VR1000CPLD_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h deleted file mode 100644 index 47add133b8e..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h +++ /dev/null @@ -1,26 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine VR1000 - IRQ Number definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_VR1000IRQ_H -#define __ASM_ARCH_VR1000IRQ_H - -/* irq numbers to onboard peripherals */ - -#define IRQ_USBOC IRQ_EINT19 -#define IRQ_IDE0 IRQ_EINT16 -#define IRQ_IDE1 IRQ_EINT17 -#define IRQ_VR1000_SERIAL IRQ_EINT12 -#define IRQ_VR1000_DM9000A IRQ_EINT10 -#define IRQ_VR1000_DM9000N IRQ_EINT9 -#define IRQ_SMALERT IRQ_EINT8 - -#endif /* __ASM_ARCH_VR1000IRQ_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h deleted file mode 100644 index 28376e56dd3..00000000000 --- a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h +++ /dev/null @@ -1,110 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h - * - * Copyright (c) 2003-2005 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Machine VR1000 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x13000000, now we need to find space for the - * peripherals that live in the nGCS[x] areas, which are quite numerous - * in their space. We also have the board's CPLD to find register space - * for. - */ - -#ifndef __ASM_ARCH_VR1000MAP_H -#define __ASM_ARCH_VR1000MAP_H - -#include <mach/bast-map.h> - -#define VR1000_IOADDR(x) BAST_IOADDR(x) - -/* we put the CPLD registers next, to get them out of the way */ - -#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ -#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) - -#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ -#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) - -#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ -#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) - -#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ -#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) - -/* next, we have the PC104 ISA interrupt registers */ - -#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ -#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) - -#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ -#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) - -#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ -#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) - -/* 0xE0000000 contains the IO space that is split by speed and - * whether the access is for 8 or 16bit IO... this ensures that - * the correct access is made - * - * 0x10000000 of space, partitioned as so: - * - * 0x00000000 to 0x04000000 8bit, slow - * 0x04000000 to 0x08000000 16bit, slow - * 0x08000000 to 0x0C000000 16bit, net - * 0x0C000000 to 0x10000000 16bit, fast - * - * each of these spaces has the following in: - * - * 0x02000000 to 0x02100000 1MB IDE primary channel - * 0x02100000 to 0x02200000 1MB IDE primary channel aux - * 0x02200000 to 0x02400000 1MB IDE secondary channel - * 0x02300000 to 0x02400000 1MB IDE secondary channel aux - * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers - * 0x02600000 to 0x02700000 1MB - * - * the phyiscal layout of the zones are: - * nGCS2 - 8bit, slow - * nGCS3 - 16bit, slow - * nGCS4 - 16bit, net - * nGCS5 - 16bit, fast - */ - -#define VR1000_VA_MULTISPACE (0xE0000000) - -#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) -#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) -#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) -#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) -#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) -#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) -#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) -#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) -#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) - -/* physical offset addresses for the peripherals */ - -#define VR1000_PA_IDEPRI (0x02000000) -#define VR1000_PA_IDEPRIAUX (0x02800000) -#define VR1000_PA_IDESEC (0x03000000) -#define VR1000_PA_IDESECAUX (0x03800000) -#define VR1000_PA_DM9000 (0x05000000) - -#define VR1000_PA_SERIAL (0x11800000) -#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) - -/* VR1000 ram is in CS1, with A26..A24 = 2_101 */ -#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) - -/* some configurations for the peripherals */ - -#define VR1000_DM9000_CS VR1000_VAM_CS4 - -#endif /* __ASM_ARCH_VR1000MAP_H */ diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c index b1908e56da1..4cd13ab6496 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c - * +/* * Copyright (c) 2006-2009 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -20,11 +19,12 @@ #include <linux/slab.h> #include <mach/map.h> -#include <mach/regs-mem.h> #include <mach/regs-clock.h> #include <plat/cpu-freq-core.h> +#include "regs-mem.h" + #define print_ns(x) ((x) / 10), ((x) % 10) /** diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c index 48eee39ab36..663436d9db0 100644 --- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c - * +/* * Copyright (c) 2006-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -28,12 +27,12 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/regs-s3c2412-mem.h> - #include <plat/cpu.h> #include <plat/cpu-freq-core.h> #include <plat/clock.h> +#include "s3c2412.h" + #define print_ns(x) ((x) / 10), ((x) % 10) /** diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c index 0efb2e2848c..e1199599873 100644 --- a/arch/arm/mach-s3c24xx/irq-pm.c +++ b/arch/arm/mach-s3c24xx/irq-pm.c @@ -15,6 +15,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/syscore_ops.h> #include <plat/cpu.h> #include <plat/pm.h> @@ -29,18 +30,18 @@ * set bit to 1 in allow bitfield to enable the wakeup settings on it */ -unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; +unsigned long s3c_irqwake_intallow = 1L << 30 | 0xfL; unsigned long s3c_irqwake_eintallow = 0x0000fff0L; int s3c_irq_wake(struct irq_data *data, unsigned int state) { - unsigned long irqbit = 1 << (data->irq - IRQ_EINT0); + unsigned long irqbit = 1 << data->hwirq; if (!(s3c_irqwake_intallow & irqbit)) return -ENOENT; - printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", data->irq); + pr_info("wake %s for hwirq %lu\n", + state ? "enabled" : "disabled", data->hwirq); if (!state) s3c_irqwake_intmask |= irqbit; @@ -64,7 +65,7 @@ static unsigned long save_extint[3]; static unsigned long save_eintflt[4]; static unsigned long save_eintmask; -int s3c24xx_irq_suspend(void) +static int s3c24xx_irq_suspend(void) { unsigned int i; @@ -80,7 +81,7 @@ int s3c24xx_irq_suspend(void) return 0; } -void s3c24xx_irq_resume(void) +static void s3c24xx_irq_resume(void) { unsigned int i; @@ -93,3 +94,31 @@ void s3c24xx_irq_resume(void) s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); __raw_writel(save_eintmask, S3C24XX_EINTMASK); } + +struct syscore_ops s3c24xx_irq_syscore_ops = { + .suspend = s3c24xx_irq_suspend, + .resume = s3c24xx_irq_resume, +}; + +#ifdef CONFIG_CPU_S3C2416 +static struct sleep_save s3c2416_irq_save[] = { + SAVE_ITEM(S3C2416_INTMSK2), +}; + +static int s3c2416_irq_suspend(void) +{ + s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save)); + + return 0; +} + +static void s3c2416_irq_resume(void) +{ + s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save)); +} + +struct syscore_ops s3c2416_irq_syscore_ops = { + .suspend = s3c2416_irq_suspend, + .resume = s3c2416_irq_resume, +}; +#endif diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c index e65619ddbcc..67d763178d3 100644 --- a/arch/arm/mach-s3c24xx/irq-s3c2412.c +++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c @@ -33,12 +33,13 @@ #include <mach/regs-irq.h> #include <mach/regs-gpio.h> -#include <mach/regs-power.h> #include <plat/cpu.h> #include <plat/irq.h> #include <plat/pm.h> +#include "s3c2412-power.h" + #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c deleted file mode 100644 index ff141b0af26..00000000000 --- a/arch/arm/mach-s3c24xx/irq-s3c2416.c +++ /dev/null @@ -1,348 +0,0 @@ -/* linux/arch/arm/mach-s3c2416/irq.c - * - * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>, - * as part of OpenInkpot project - * Copyright (c) 2009 Promwad Innovation Company - * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/device.h> -#include <linux/io.h> -#include <linux/syscore_ops.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/irq.h> - -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> - -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/irq.h> - -#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) - -static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len) -{ - unsigned int subsrc, submsk; - unsigned int end; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - subsrc &= ~submsk; - subsrc >>= (irq - S3C2410_IRQSUB(0)); - subsrc &= (1 << len)-1; - - end = len + irq; - - for (; irq < end && subsrc; irq++) { - if (subsrc & 1) - generic_handle_irq(irq); - - subsrc >>= 1; - } -} - -/* WDT/AC97 sub interrupts */ - -static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) -{ - s3c2416_irq_demux(IRQ_S3C2443_WDT, 4); -} - -#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) -#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) - -static void s3c2416_irq_wdtac97_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); -} - -static void s3c2416_irq_wdtac97_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); -} - -static void s3c2416_irq_wdtac97_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); -} - -static struct irq_chip s3c2416_irq_wdtac97 = { - .irq_mask = s3c2416_irq_wdtac97_mask, - .irq_unmask = s3c2416_irq_wdtac97_unmask, - .irq_ack = s3c2416_irq_wdtac97_ack, -}; - -/* LCD sub interrupts */ - -static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) -{ - s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4); -} - -#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) -#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) - -static void s3c2416_irq_lcd_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); -} - -static void s3c2416_irq_lcd_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_LCD); -} - -static void s3c2416_irq_lcd_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); -} - -static struct irq_chip s3c2416_irq_lcd = { - .irq_mask = s3c2416_irq_lcd_mask, - .irq_unmask = s3c2416_irq_lcd_unmask, - .irq_ack = s3c2416_irq_lcd_ack, -}; - -/* DMA sub interrupts */ - -static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc) -{ - s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6); -} - -#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) -#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) - - -static void s3c2416_irq_dma_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); -} - -static void s3c2416_irq_dma_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_DMA); -} - -static void s3c2416_irq_dma_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); -} - -static struct irq_chip s3c2416_irq_dma = { - .irq_mask = s3c2416_irq_dma_mask, - .irq_unmask = s3c2416_irq_dma_unmask, - .irq_ack = s3c2416_irq_dma_ack, -}; - -/* UART3 sub interrupts */ - -static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) -{ - s3c2416_irq_demux(IRQ_S3C2443_RX3, 3); -} - -#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) -#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) - -static void s3c2416_irq_uart3_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); -} - -static void s3c2416_irq_uart3_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_UART3); -} - -static void s3c2416_irq_uart3_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); -} - -static struct irq_chip s3c2416_irq_uart3 = { - .irq_mask = s3c2416_irq_uart3_mask, - .irq_unmask = s3c2416_irq_uart3_unmask, - .irq_ack = s3c2416_irq_uart3_ack, -}; - -/* second interrupt register */ - -static inline void s3c2416_irq_ack_second(struct irq_data *data) -{ - unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D); - - __raw_writel(bitval, S3C2416_SRCPND2); - __raw_writel(bitval, S3C2416_INTPND2); -} - -static void s3c2416_irq_mask_second(struct irq_data *data) -{ - unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D); - unsigned long mask; - - mask = __raw_readl(S3C2416_INTMSK2); - mask |= bitval; - __raw_writel(mask, S3C2416_INTMSK2); -} - -static void s3c2416_irq_unmask_second(struct irq_data *data) -{ - unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D); - unsigned long mask; - - mask = __raw_readl(S3C2416_INTMSK2); - mask &= ~bitval; - __raw_writel(mask, S3C2416_INTMSK2); -} - -struct irq_chip s3c2416_irq_second = { - .irq_ack = s3c2416_irq_ack_second, - .irq_mask = s3c2416_irq_mask_second, - .irq_unmask = s3c2416_irq_unmask_second, -}; - - -/* IRQ initialisation code */ - -static int s3c2416_add_sub(unsigned int base, - void (*demux)(unsigned int, - struct irq_desc *), - struct irq_chip *chip, - unsigned int start, unsigned int end) -{ - unsigned int irqno; - - irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); - irq_set_chained_handler(base, demux); - - for (irqno = start; irqno <= end; irqno++) { - irq_set_chip_and_handler(irqno, chip, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - return 0; -} - -static void s3c2416_irq_add_second(void) -{ - unsigned long pend; - unsigned long last; - int irqno; - int i; - - /* first, clear all interrupts pending... */ - last = 0; - for (i = 0; i < 4; i++) { - pend = __raw_readl(S3C2416_INTPND2); - - if (pend == 0 || pend == last) - break; - - __raw_writel(pend, S3C2416_SRCPND2); - __raw_writel(pend, S3C2416_INTPND2); - printk(KERN_INFO "irq: clearing pending status %08x\n", - (int)pend); - last = pend; - } - - for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) { - switch (irqno) { - case IRQ_S3C2416_RESERVED2: - case IRQ_S3C2416_RESERVED3: - /* no IRQ here */ - break; - default: - irq_set_chip_and_handler(irqno, &s3c2416_irq_second, - handle_edge_irq); - set_irq_flags(irqno, IRQF_VALID); - } - } -} - -static int s3c2416_irq_add(struct device *dev, - struct subsys_interface *sif) -{ - printk(KERN_INFO "S3C2416: IRQ Support\n"); - - s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd, - IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4); - - s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma, - &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5); - - s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3, - &s3c2416_irq_uart3, - IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3); - - s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97, - &s3c2416_irq_wdtac97, - IRQ_S3C2443_WDT, IRQ_S3C2443_AC97); - - s3c2416_irq_add_second(); - - return 0; -} - -static struct subsys_interface s3c2416_irq_interface = { - .name = "s3c2416_irq", - .subsys = &s3c2416_subsys, - .add_dev = s3c2416_irq_add, -}; - -static int __init s3c2416_irq_init(void) -{ - return subsys_interface_register(&s3c2416_irq_interface); -} - -arch_initcall(s3c2416_irq_init); - -#ifdef CONFIG_PM -static struct sleep_save irq_save[] = { - SAVE_ITEM(S3C2416_INTMSK2), -}; - -int s3c2416_irq_suspend(void) -{ - s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); - - return 0; -} - -void s3c2416_irq_resume(void) -{ - s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); -} - -struct syscore_ops s3c2416_irq_syscore_ops = { - .suspend = s3c2416_irq_suspend, - .resume = s3c2416_irq_resume, -}; -#endif diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c deleted file mode 100644 index 5e69109c092..00000000000 --- a/arch/arm/mach-s3c24xx/irq-s3c2443.c +++ /dev/null @@ -1,281 +0,0 @@ -/* linux/arch/arm/mach-s3c2443/irq.c - * - * Copyright (c) 2007 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/device.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/irq.h> - -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> - -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/irq.h> - -#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) - -static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len) -{ - unsigned int subsrc, submsk; - unsigned int end; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - subsrc &= ~submsk; - subsrc >>= (irq - S3C2410_IRQSUB(0)); - subsrc &= (1 << len)-1; - - end = len + irq; - - for (; irq < end && subsrc; irq++) { - if (subsrc & 1) - generic_handle_irq(irq); - - subsrc >>= 1; - } -} - -/* WDT/AC97 sub interrupts */ - -static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) -{ - s3c2443_irq_demux(IRQ_S3C2443_WDT, 4); -} - -#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) -#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) - -static void s3c2443_irq_wdtac97_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); -} - -static void s3c2443_irq_wdtac97_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); -} - -static void s3c2443_irq_wdtac97_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); -} - -static struct irq_chip s3c2443_irq_wdtac97 = { - .irq_mask = s3c2443_irq_wdtac97_mask, - .irq_unmask = s3c2443_irq_wdtac97_unmask, - .irq_ack = s3c2443_irq_wdtac97_ack, -}; - -/* LCD sub interrupts */ - -static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) -{ - s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4); -} - -#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) -#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) - -static void s3c2443_irq_lcd_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); -} - -static void s3c2443_irq_lcd_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_LCD); -} - -static void s3c2443_irq_lcd_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); -} - -static struct irq_chip s3c2443_irq_lcd = { - .irq_mask = s3c2443_irq_lcd_mask, - .irq_unmask = s3c2443_irq_lcd_unmask, - .irq_ack = s3c2443_irq_lcd_ack, -}; - -/* DMA sub interrupts */ - -static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) -{ - s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6); -} - -#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) -#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) - -static void s3c2443_irq_dma_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); -} - -static void s3c2443_irq_dma_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_DMA); -} - -static void s3c2443_irq_dma_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); -} - -static struct irq_chip s3c2443_irq_dma = { - .irq_mask = s3c2443_irq_dma_mask, - .irq_unmask = s3c2443_irq_dma_unmask, - .irq_ack = s3c2443_irq_dma_ack, -}; - -/* UART3 sub interrupts */ - -static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) -{ - s3c2443_irq_demux(IRQ_S3C2443_RX3, 3); -} - -#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) -#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) - -static void s3c2443_irq_uart3_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); -} - -static void s3c2443_irq_uart3_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_UART3); -} - -static void s3c2443_irq_uart3_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); -} - -static struct irq_chip s3c2443_irq_uart3 = { - .irq_mask = s3c2443_irq_uart3_mask, - .irq_unmask = s3c2443_irq_uart3_unmask, - .irq_ack = s3c2443_irq_uart3_ack, -}; - -/* CAM sub interrupts */ - -static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) -{ - s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4); -} - -#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) -#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P) - -static void s3c2443_irq_cam_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM); -} - -static void s3c2443_irq_cam_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_CAM); -} - -static void s3c2443_irq_cam_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM); -} - -static struct irq_chip s3c2443_irq_cam = { - .irq_mask = s3c2443_irq_cam_mask, - .irq_unmask = s3c2443_irq_cam_unmask, - .irq_ack = s3c2443_irq_cam_ack, -}; - -/* IRQ initialisation code */ - -static int s3c2443_add_sub(unsigned int base, - void (*demux)(unsigned int, - struct irq_desc *), - struct irq_chip *chip, - unsigned int start, unsigned int end) -{ - unsigned int irqno; - - irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); - irq_set_chained_handler(base, demux); - - for (irqno = start; irqno <= end; irqno++) { - irq_set_chip_and_handler(irqno, chip, handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - return 0; -} - -static int s3c2443_irq_add(struct device *dev, - struct subsys_interface *sif) -{ - printk("S3C2443: IRQ Support\n"); - - s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam, - IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P); - - s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd, - IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4); - - s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma, - &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5); - - s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3, - &s3c2443_irq_uart3, - IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3); - - s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97, - &s3c2443_irq_wdtac97, - IRQ_S3C2443_WDT, IRQ_S3C2443_AC97); - - return 0; -} - -static struct subsys_interface s3c2443_irq_interface = { - .name = "s3c2443_irq", - .subsys = &s3c2443_subsys, - .add_dev = s3c2443_irq_add, -}; - -static int __init s3c2443_irq_init(void) -{ - return subsys_interface_register(&s3c2443_irq_interface); -} - -arch_initcall(s3c2443_irq_init); - diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c new file mode 100644 index 00000000000..cb9f5e011e7 --- /dev/null +++ b/arch/arm/mach-s3c24xx/irq.c @@ -0,0 +1,822 @@ +/* + * S3C24XX IRQ handling + * + * Copyright (c) 2003-2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/device.h> +#include <linux/irqdomain.h> + +#include <asm/mach/irq.h> + +#include <mach/regs-irq.h> +#include <mach/regs-gpio.h> + +#include <plat/cpu.h> +#include <plat/regs-irqtype.h> +#include <plat/pm.h> +#include <plat/irq.h> + +#define S3C_IRQTYPE_NONE 0 +#define S3C_IRQTYPE_EINT 1 +#define S3C_IRQTYPE_EDGE 2 +#define S3C_IRQTYPE_LEVEL 3 + +struct s3c_irq_data { + unsigned int type; + unsigned long parent_irq; + + /* data gets filled during init */ + struct s3c_irq_intc *intc; + unsigned long sub_bits; + struct s3c_irq_intc *sub_intc; +}; + +/* + * Sructure holding the controller data + * @reg_pending register holding pending irqs + * @reg_intpnd special register intpnd in main intc + * @reg_mask mask register + * @domain irq_domain of the controller + * @parent parent controller for ext and sub irqs + * @irqs irq-data, always s3c_irq_data[32] + */ +struct s3c_irq_intc { + void __iomem *reg_pending; + void __iomem *reg_intpnd; + void __iomem *reg_mask; + struct irq_domain *domain; + struct s3c_irq_intc *parent; + struct s3c_irq_data *irqs; +}; + +static void s3c_irq_mask(struct irq_data *data) +{ + struct s3c_irq_intc *intc = data->domain->host_data; + struct s3c_irq_intc *parent_intc = intc->parent; + struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; + struct s3c_irq_data *parent_data; + unsigned long mask; + unsigned int irqno; + + mask = __raw_readl(intc->reg_mask); + mask |= (1UL << data->hwirq); + __raw_writel(mask, intc->reg_mask); + + if (parent_intc && irq_data->parent_irq) { + parent_data = &parent_intc->irqs[irq_data->parent_irq]; + + /* check to see if we need to mask the parent IRQ */ + if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { + irqno = irq_find_mapping(parent_intc->domain, + irq_data->parent_irq); + s3c_irq_mask(irq_get_irq_data(irqno)); + } + } +} + +static void s3c_irq_unmask(struct irq_data *data) +{ + struct s3c_irq_intc *intc = data->domain->host_data; + struct s3c_irq_intc *parent_intc = intc->parent; + struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; + unsigned long mask; + unsigned int irqno; + + mask = __raw_readl(intc->reg_mask); + mask &= ~(1UL << data->hwirq); + __raw_writel(mask, intc->reg_mask); + + if (parent_intc && irq_data->parent_irq) { + irqno = irq_find_mapping(parent_intc->domain, + irq_data->parent_irq); + s3c_irq_unmask(irq_get_irq_data(irqno)); + } +} + +static inline void s3c_irq_ack(struct irq_data *data) +{ + struct s3c_irq_intc *intc = data->domain->host_data; + unsigned long bitval = 1UL << data->hwirq; + + __raw_writel(bitval, intc->reg_pending); + if (intc->reg_intpnd) + __raw_writel(bitval, intc->reg_intpnd); +} + +static int s3c_irqext_type_set(void __iomem *gpcon_reg, + void __iomem *extint_reg, + unsigned long gpcon_offset, + unsigned long extint_offset, + unsigned int type) +{ + unsigned long newvalue = 0, value; + + /* Set the GPIO to external interrupt mode */ + value = __raw_readl(gpcon_reg); + value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); + __raw_writel(value, gpcon_reg); + + /* Set the external interrupt to pointed trigger type */ + switch (type) + { + case IRQ_TYPE_NONE: + pr_warn("No edge setting!\n"); + break; + + case IRQ_TYPE_EDGE_RISING: + newvalue = S3C2410_EXTINT_RISEEDGE; + break; + + case IRQ_TYPE_EDGE_FALLING: + newvalue = S3C2410_EXTINT_FALLEDGE; + break; + + case IRQ_TYPE_EDGE_BOTH: + newvalue = S3C2410_EXTINT_BOTHEDGE; + break; + + case IRQ_TYPE_LEVEL_LOW: + newvalue = S3C2410_EXTINT_LOWLEV; + break; + + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S3C2410_EXTINT_HILEV; + break; + + default: + pr_err("No such irq type %d", type); + return -EINVAL; + } + + value = __raw_readl(extint_reg); + value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); + __raw_writel(value, extint_reg); + + return 0; +} + +/* FIXME: make static when it's out of plat-samsung/irq.h */ +int s3c_irqext_type(struct irq_data *data, unsigned int type) +{ + void __iomem *extint_reg; + void __iomem *gpcon_reg; + unsigned long gpcon_offset, extint_offset; + + if ((data->hwirq >= 4) && (data->hwirq <= 7)) { + gpcon_reg = S3C2410_GPFCON; + extint_reg = S3C24XX_EXTINT0; + gpcon_offset = (data->hwirq) * 2; + extint_offset = (data->hwirq) * 4; + } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { + gpcon_reg = S3C2410_GPGCON; + extint_reg = S3C24XX_EXTINT1; + gpcon_offset = (data->hwirq - 8) * 2; + extint_offset = (data->hwirq - 8) * 4; + } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { + gpcon_reg = S3C2410_GPGCON; + extint_reg = S3C24XX_EXTINT2; + gpcon_offset = (data->hwirq - 8) * 2; + extint_offset = (data->hwirq - 16) * 4; + } else { + return -EINVAL; + } + + return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, + extint_offset, type); +} + +static int s3c_irqext0_type(struct irq_data *data, unsigned int type) +{ + void __iomem *extint_reg; + void __iomem *gpcon_reg; + unsigned long gpcon_offset, extint_offset; + + if ((data->hwirq >= 0) && (data->hwirq <= 3)) { + gpcon_reg = S3C2410_GPFCON; + extint_reg = S3C24XX_EXTINT0; + gpcon_offset = (data->hwirq) * 2; + extint_offset = (data->hwirq) * 4; + } else { + return -EINVAL; + } + + return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, + extint_offset, type); +} + +struct irq_chip s3c_irq_chip = { + .name = "s3c", + .irq_ack = s3c_irq_ack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_wake = s3c_irq_wake +}; + +struct irq_chip s3c_irq_level_chip = { + .name = "s3c-level", + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_ack = s3c_irq_ack, +}; + +static struct irq_chip s3c_irqext_chip = { + .name = "s3c-ext", + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_ack = s3c_irq_ack, + .irq_set_type = s3c_irqext_type, + .irq_set_wake = s3c_irqext_wake +}; + +static struct irq_chip s3c_irq_eint0t4 = { + .name = "s3c-ext0", + .irq_ack = s3c_irq_ack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_wake = s3c_irq_wake, + .irq_set_type = s3c_irqext0_type, +}; + +static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct s3c_irq_intc *intc = desc->irq_data.domain->host_data; + struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq]; + struct s3c_irq_intc *sub_intc = irq_data->sub_intc; + unsigned long src; + unsigned long msk; + unsigned int n; + + chained_irq_enter(chip, desc); + + src = __raw_readl(sub_intc->reg_pending); + msk = __raw_readl(sub_intc->reg_mask); + + src &= ~msk; + src &= irq_data->sub_bits; + + while (src) { + n = __ffs(src); + src &= ~(1 << n); + generic_handle_irq(irq_find_mapping(sub_intc->domain, n)); + } + + chained_irq_exit(chip, desc); +} + +#ifdef CONFIG_FIQ +/** + * s3c24xx_set_fiq - set the FIQ routing + * @irq: IRQ number to route to FIQ on processor. + * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. + * + * Change the state of the IRQ to FIQ routing depending on @irq and @on. If + * @on is true, the @irq is checked to see if it can be routed and the + * interrupt controller updated to route the IRQ. If @on is false, the FIQ + * routing is cleared, regardless of which @irq is specified. + */ +int s3c24xx_set_fiq(unsigned int irq, bool on) +{ + u32 intmod; + unsigned offs; + + if (on) { + offs = irq - FIQ_START; + if (offs > 31) + return -EINVAL; + + intmod = 1 << offs; + } else { + intmod = 0; + } + + __raw_writel(intmod, S3C2410_INTMOD); + return 0; +} + +EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); +#endif + +static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c_irq_intc *intc = h->host_data; + struct s3c_irq_data *irq_data = &intc->irqs[hw]; + struct s3c_irq_intc *parent_intc; + struct s3c_irq_data *parent_irq_data; + unsigned int irqno; + + if (!intc) { + pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw); + return -EINVAL; + } + + if (!irq_data) { + pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw); + return -EINVAL; + } + + /* attach controller pointer to irq_data */ + irq_data->intc = intc; + + /* set handler and flags */ + switch (irq_data->type) { + case S3C_IRQTYPE_NONE: + return 0; + case S3C_IRQTYPE_EINT: + if (irq_data->parent_irq) + irq_set_chip_and_handler(virq, &s3c_irqext_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, + handle_edge_irq); + break; + case S3C_IRQTYPE_EDGE: + if (irq_data->parent_irq || + intc->reg_pending == S3C2416_SRCPND2) + irq_set_chip_and_handler(virq, &s3c_irq_level_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_chip, + handle_edge_irq); + break; + case S3C_IRQTYPE_LEVEL: + if (irq_data->parent_irq) + irq_set_chip_and_handler(virq, &s3c_irq_level_chip, + handle_level_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_chip, + handle_level_irq); + break; + default: + pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); + return -EINVAL; + } + set_irq_flags(virq, IRQF_VALID); + + if (irq_data->parent_irq) { + parent_intc = intc->parent; + if (!parent_intc) { + pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n", + hw); + goto err; + } + + parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; + if (!irq_data) { + pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", + hw); + goto err; + } + + parent_irq_data->sub_intc = intc; + parent_irq_data->sub_bits |= (1UL << hw); + + /* attach the demuxer to the parent irq */ + irqno = irq_find_mapping(parent_intc->domain, + irq_data->parent_irq); + if (!irqno) { + pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", + irq_data->parent_irq); + goto err; + } + irq_set_chained_handler(irqno, s3c_irq_demux); + } + + return 0; + +err: + set_irq_flags(virq, 0); + + /* the only error can result from bad mapping data*/ + return -EINVAL; +} + +static struct irq_domain_ops s3c24xx_irq_ops = { + .map = s3c24xx_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) +{ + void __iomem *reg_source; + unsigned long pend; + unsigned long last; + int i; + + /* if intpnd is set, read the next pending irq from there */ + reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; + + last = 0; + for (i = 0; i < 4; i++) { + pend = __raw_readl(reg_source); + + if (pend == 0 || pend == last) + break; + + __raw_writel(pend, intc->reg_pending); + if (intc->reg_intpnd) + __raw_writel(pend, intc->reg_intpnd); + + pr_info("irq: clearing pending status %08x\n", (int)pend); + last = pend; + } +} + +struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, + struct s3c_irq_data *irq_data, + struct s3c_irq_intc *parent, + unsigned long address) +{ + struct s3c_irq_intc *intc; + void __iomem *base = (void *)0xf6000000; /* static mapping */ + int irq_num; + int irq_start; + int irq_offset; + int ret; + + intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); + if (!intc) + return ERR_PTR(-ENOMEM); + + intc->irqs = irq_data; + + if (parent) + intc->parent = parent; + + /* select the correct data for the controller. + * Need to hard code the irq num start and offset + * to preserve the static mapping for now + */ + switch (address) { + case 0x4a000000: + pr_debug("irq: found main intc\n"); + intc->reg_pending = base; + intc->reg_mask = base + 0x08; + intc->reg_intpnd = base + 0x10; + irq_num = 32; + irq_start = S3C2410_IRQ(0); + irq_offset = 0; + break; + case 0x4a000018: + pr_debug("irq: found subintc\n"); + intc->reg_pending = base + 0x18; + intc->reg_mask = base + 0x1c; + irq_num = 29; + irq_start = S3C2410_IRQSUB(0); + irq_offset = 0; + break; + case 0x4a000040: + pr_debug("irq: found intc2\n"); + intc->reg_pending = base + 0x40; + intc->reg_mask = base + 0x48; + intc->reg_intpnd = base + 0x50; + irq_num = 8; + irq_start = S3C2416_IRQ(0); + irq_offset = 0; + break; + case 0x560000a4: + pr_debug("irq: found eintc\n"); + base = (void *)0xfd000000; + + intc->reg_mask = base + 0xa4; + intc->reg_pending = base + 0x08; + irq_num = 20; + irq_start = S3C2410_IRQ(32); + irq_offset = 4; + break; + default: + pr_err("irq: unsupported controller address\n"); + ret = -EINVAL; + goto err; + } + + /* now that all the data is complete, init the irq-domain */ + s3c24xx_clear_intc(intc); + intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, + irq_offset, &s3c24xx_irq_ops, + intc); + if (!intc->domain) { + pr_err("irq: could not create irq-domain\n"); + ret = -EINVAL; + goto err; + } + + return intc; + +err: + kfree(intc); + return ERR_PTR(ret); +} + +/* s3c24xx_init_irq + * + * Initialise S3C2410 IRQ system +*/ + +static struct s3c_irq_data init_base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_eint[32] = { + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ +}; + +static struct s3c_irq_data init_subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ +}; + +void __init s3c24xx_init_irq(void) +{ + struct s3c_irq_intc *main_intc; + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); +} + +#ifdef CONFIG_CPU_S3C2416 +static struct s3c_irq_data init_s3c2416base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ + { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_NONE, }, + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_s3c2416subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ +}; + +static struct s3c_irq_data init_s3c2416_second[32] = { + { .type = S3C_IRQTYPE_EDGE }, /* 2D */ + { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ + { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */ + { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ + { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */ +}; + +void __init s3c2416_init_irq(void) +{ + struct s3c_irq_intc *main_intc; + + pr_info("S3C2416: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); + s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018); + + s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040); +} + +#endif + +#ifdef CONFIG_CPU_S3C2443 +static struct s3c_irq_data init_s3c2443base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ + { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + + +static struct s3c_irq_data init_s3c2443subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ +}; + +void __init s3c2443_init_irq(void) +{ + struct s3c_irq_intc *main_intc; + + pr_info("S3C2443: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000); + if (IS_ERR(main_intc)) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); + s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018); +} +#endif diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c index f4ad99c1e47..0e0279e7915 100644 --- a/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c @@ -237,6 +237,6 @@ MACHINE_START(AML_M5900, "AML_M5900") .map_io = amlm5900_map_io, .init_irq = s3c24xx_init_irq, .init_machine = amlm5900_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c index 1ee8c463874..bb595f15ce3 100644 --- a/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/arch/arm/mach-s3c24xx/mach-anubis.c @@ -28,17 +28,12 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/anubis-map.h> -#include <mach/anubis-irq.h> -#include <mach/anubis-cpld.h> - #include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -55,8 +50,9 @@ #include <plat/cpu.h> #include <linux/platform_data/asoc-s3c24xx_simtec.h> -#include "simtec.h" +#include "anubis.h" #include "common.h" +#include "simtec.h" #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics" @@ -237,7 +233,7 @@ static struct pata_platform_info anubis_ide_platdata = { static struct resource anubis_ide0_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32), [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32), - [3] = DEFINE_RES_IRQ(IRQ_IDE0), + [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0), }; static struct platform_device anubis_device_ide0 = { @@ -254,7 +250,7 @@ static struct platform_device anubis_device_ide0 = { static struct resource anubis_ide1_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32), [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32), - [2] = DEFINE_RES_IRQ(IRQ_IDE0), + [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0), }; static struct platform_device anubis_device_ide1 = { @@ -279,7 +275,7 @@ static struct ax_plat_data anubis_asix_platdata = { static struct resource anubis_asix_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20), - [1] = DEFINE_RES_IRQ(IRQ_ASIX), + [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX), }; static struct platform_device anubis_device_asix = { @@ -448,6 +444,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis") .map_io = anubis_map_io, .init_machine = anubis_init, .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c index 00381fe5de3..b4bc60c78eb 100644 --- a/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/types.h> +#include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/timer.h> @@ -34,7 +35,6 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -210,6 +210,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB") .map_io = at2440evb_map_io, .init_machine = at2440evb_init, .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c index 6a30ce7e4aa..ca661808104 100644 --- a/arch/arm/mach-s3c24xx/mach-bast.c +++ b/arch/arm/mach-s3c24xx/mach-bast.c @@ -24,48 +24,41 @@ #include <linux/ata_platform.h> #include <linux/i2c.h> #include <linux/io.h> +#include <linux/serial_8250.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/partitions.h> + +#include <linux/platform_data/asoc-s3c24xx_simtec.h> +#include <linux/platform_data/hwmon-s3c.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <linux/platform_data/mtd-nand-s3c2410.h> #include <net/ax88796.h> +#include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> - -#include <mach/bast-map.h> -#include <mach/bast-irq.h> -#include <mach/bast-cpld.h> - -#include <mach/hardware.h> -#include <asm/irq.h> #include <asm/mach-types.h> -//#include <asm/debug-ll.h> -#include <plat/regs-serial.h> +#include <mach/fb.h> +#include <mach/hardware.h> #include <mach/regs-gpio.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> -#include <linux/platform_data/hwmon-s3c.h> -#include <linux/platform_data/mtd-nand-s3c2410.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <mach/fb.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/partitions.h> - -#include <linux/serial_8250.h> - #include <plat/clock.h> -#include <plat/devs.h> #include <plat/cpu.h> #include <plat/cpu-freq.h> +#include <plat/devs.h> #include <plat/gpio-cfg.h> -#include <linux/platform_data/asoc-s3c24xx_simtec.h> +#include <plat/regs-serial.h> -#include "simtec.h" +#include "bast.h" #include "common.h" +#include "simtec.h" #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" @@ -312,7 +305,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = { static struct resource bast_dm9k_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4), [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40), - [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \ + [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \ | IORESOURCE_IRQ_HIGHLEVEL), }; @@ -343,7 +336,7 @@ static struct platform_device bast_device_dm9k = { static struct plat_serial8250_port bast_sio_data[] = { [0] = { .mapbase = SERIAL_BASE + 0x2f8, - .irq = IRQ_PCSERIAL1, + .irq = BAST_IRQ_PCSERIAL1, .flags = SERIAL_FLAGS, .iotype = UPIO_MEM, .regshift = 0, @@ -351,7 +344,7 @@ static struct plat_serial8250_port bast_sio_data[] = { }, [1] = { .mapbase = SERIAL_BASE + 0x3f8, - .irq = IRQ_PCSERIAL2, + .irq = BAST_IRQ_PCSERIAL2, .flags = SERIAL_FLAGS, .iotype = UPIO_MEM, .regshift = 0, @@ -390,7 +383,7 @@ static struct ax_plat_data bast_asix_platdata = { static struct resource bast_asix_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20), [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1), - [2] = DEFINE_RES_IRQ(IRQ_ASIX), + [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX), }; static struct platform_device bast_device_asix = { @@ -612,6 +605,6 @@ MACHINE_START(BAST, "Simtec-BAST") .map_io = bast_map_io, .init_irq = s3c24xx_init_irq, .init_machine = bast_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c index 973b87ca87f..a25e8c5a7b4 100644 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/arch/arm/mach-s3c24xx/mach-gta02.c @@ -1,6 +1,4 @@ /* - * linux/arch/arm/mach-s3c2442/mach-gta02.c - * * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner. * * Copyright (C) 2006-2009 by Openmoko, Inc. @@ -23,7 +21,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * */ #include <linux/kernel.h> @@ -34,62 +31,59 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> +#include <linux/gpio_keys.h> #include <linux/workqueue.h> #include <linux/platform_device.h> #include <linux/serial_core.h> -#include <linux/spi/spi.h> -#include <linux/spi/s3c24xx.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/i2c.h> #include <linux/mmc/host.h> +#include <linux/mfd/pcf50633/adc.h> +#include <linux/mfd/pcf50633/backlight.h> +#include <linux/mfd/pcf50633/core.h> +#include <linux/mfd/pcf50633/gpio.h> +#include <linux/mfd/pcf50633/mbc.h> +#include <linux/mfd/pcf50633/pmic.h> + #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> -#include <linux/io.h> -#include <linux/i2c.h> #include <linux/regulator/machine.h> -#include <linux/mfd/pcf50633/core.h> -#include <linux/mfd/pcf50633/mbc.h> -#include <linux/mfd/pcf50633/adc.h> -#include <linux/mfd/pcf50633/gpio.h> -#include <linux/mfd/pcf50633/pmic.h> -#include <linux/mfd/pcf50633/backlight.h> - -#include <linux/input.h> -#include <linux/gpio_keys.h> +#include <linux/spi/spi.h> +#include <linux/spi/s3c24xx.h> +#include <asm/irq.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <asm/irq.h> -#include <asm/mach-types.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <linux/platform_data/mtd-nand-s3c2410.h> +#include <linux/platform_data/touchscreen-s3c2410.h> +#include <linux/platform_data/usb-ohci-s3c2410.h> +#include <linux/platform_data/usb-s3c2410_udc.h> -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> #include <mach/fb.h> - -#include <linux/platform_data/usb-ohci-s3c2410.h> -#include <mach/regs-mem.h> #include <mach/hardware.h> +#include <mach/regs-gpio.h> +#include <mach/regs-irq.h> -#include <mach/gta02.h> - -#include <plat/regs-serial.h> -#include <linux/platform_data/mtd-nand-s3c2410.h> -#include <plat/devs.h> #include <plat/cpu.h> -#include <plat/pm.h> -#include <linux/platform_data/usb-s3c2410_udc.h> +#include <plat/devs.h> #include <plat/gpio-cfg.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/touchscreen-s3c2410.h> +#include <plat/pm.h> +#include <plat/regs-serial.h> #include "common.h" +#include "gta02.h" static struct pcf50633 *gta02_pcf; @@ -595,6 +589,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02") .map_io = gta02_map_io, .init_irq = s3c24xx_init_irq, .init_machine = gta02_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index b23dd1b106e..79bc0830d74 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/mach-h1940.c - * +/* * Copyright (c) 2003-2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * @@ -37,40 +36,36 @@ #include <linux/mmc/host.h> #include <linux/export.h> +#include <asm/irq.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> -#include <mach/regs-lcd.h> -#include <mach/regs-clock.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <linux/platform_data/mmc-s3cmci.h> +#include <linux/platform_data/touchscreen-s3c2410.h> +#include <linux/platform_data/usb-s3c2410_udc.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-fns.h> -#include <mach/gpio-nrs.h> +#include <sound/uda1380.h> -#include <mach/h1940.h> -#include <mach/h1940-latch.h> #include <mach/fb.h> -#include <linux/platform_data/usb-s3c2410_udc.h> -#include <linux/platform_data/i2c-s3c2410.h> +#include <mach/hardware.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> +#include <mach/regs-lcd.h> -#include <plat/gpio-cfg.h> #include <plat/clock.h> -#include <plat/devs.h> #include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> #include <plat/pll.h> #include <plat/pm.h> -#include <linux/platform_data/mmc-s3cmci.h> -#include <linux/platform_data/touchscreen-s3c2410.h> +#include <plat/regs-serial.h> -#include <sound/uda1380.h> #include "common.h" +#include "h1940.h" #define H1940_LATCH ((void __force __iomem *)0xF8000000) @@ -746,6 +741,6 @@ MACHINE_START(H1940, "IPAQ-H1940") .reserve = h1940_reserve, .init_irq = h1940_init_irq, .init_machine = h1940_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index c9954e26b49..54e83c1f780 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c @@ -35,9 +35,7 @@ #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/regs-power.h> #include <mach/regs-gpio.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/fb.h> @@ -56,6 +54,8 @@ #include <plat/pm.h> #include <linux/platform_data/usb-s3c2410_udc.h> +#include "s3c2412-power.h" + static struct map_desc jive_iodesc[] __initdata = { }; @@ -661,6 +661,6 @@ MACHINE_START(JIVE, "JIVE") .init_irq = s3c24xx_init_irq, .map_io = jive_map_io, .init_machine = jive_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index a31d5b83e5f..2865e5919f2 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -40,7 +40,6 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> #include <linux/platform_data/leds-s3c24xx.h> -#include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/irqs.h> #include <linux/platform_data/mtd-nand-s3c2410.h> @@ -688,6 +687,6 @@ MACHINE_START(MINI2440, "MINI2440") .map_io = mini2440_map_io, .init_machine = mini2440_init, .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c index c53a9bfe141..d9d04b24029 100644 --- a/arch/arm/mach-s3c24xx/mach-n30.c +++ b/arch/arm/mach-s3c24xx/mach-n30.c @@ -589,7 +589,7 @@ MACHINE_START(N30, "Acer-N30") Ben Dooks <ben-linux@fluff.org> */ .atag_offset = 0x100, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .init_machine = n30_init, .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, @@ -600,7 +600,7 @@ MACHINE_START(N35, "Acer-N35") /* Maintainer: Christer Weinigel <christer@weinigel.se> */ .atag_offset = 0x100, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .init_machine = n30_init, .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c index a2b92b0898e..a454e246186 100644 --- a/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c @@ -153,6 +153,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") .map_io = nexcoder_map_io, .init_machine = nexcoder_init, .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c index bb36d832bd3..ae2cbdf3e3c 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/arch/arm/mach-s3c24xx/mach-osiris.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2440/mach-osiris.c - * +/* * Copyright (c) 2005-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -22,25 +21,16 @@ #include <linux/clk.h> #include <linux/i2c.h> #include <linux/io.h> +#include <linux/platform_device.h> #include <linux/i2c/tps65010.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> - -#include <mach/osiris-map.h> -#include <mach/osiris-cpld.h> - -#include <mach/hardware.h> #include <asm/irq.h> -#include <asm/mach-types.h> -#include <plat/cpu-freq.h> -#include <plat/regs-serial.h> -#include <mach/regs-gpio.h> -#include <mach/regs-mem.h> -#include <mach/regs-lcd.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -49,12 +39,20 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/gpio-cfg.h> #include <plat/clock.h> -#include <plat/devs.h> #include <plat/cpu.h> +#include <plat/cpu-freq.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> + +#include <mach/hardware.h> +#include <mach/regs-gpio.h> +#include <mach/regs-lcd.h> #include "common.h" +#include "osiris.h" +#include "regs-mem.h" /* onboard perihperal map */ @@ -428,6 +426,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS") .map_io = osiris_map_io, .init_irq = s3c24xx_init_irq, .init_machine = osiris_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c index bca39f0232b..40a47d6c6a8 100644 --- a/arch/arm/mach-s3c24xx/mach-otom.c +++ b/arch/arm/mach-s3c24xx/mach-otom.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/mach-otom.c +/* * * Copyright (c) 2004 Nex Vision * Guillaume GOURAT <guillaume.gourat@nexvision.fr> @@ -6,7 +6,6 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * */ #include <linux/kernel.h> @@ -19,26 +18,25 @@ #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/platform_data/i2c-s3c2410.h> + +#include <asm/irq.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/otom-map.h> - #include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -#include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <plat/s3c2410.h> #include <plat/clock.h> -#include <plat/devs.h> -#include <linux/platform_data/i2c-s3c2410.h> #include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/regs-serial.h> +#include <plat/s3c2410.h> #include "common.h" +#include "otom.h" static struct map_desc otom11_iodesc[] __initdata = { /* Device area */ @@ -118,6 +116,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1") .map_io = otom11_map_io, .init_machine = otom11_init, .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index 7b6ba13d728..56175f0941b 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -343,6 +343,6 @@ MACHINE_START(QT2410, "QT2410") .map_io = qt2410_map_io, .init_irq = s3c24xx_init_irq, .init_machine = qt2410_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index 0606f2faaa5..1f9ba2ae528 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2440/mach-rx1950.c - * +/* * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev, * Copyright (c) 2007-2010 Vasily Khoruzhick * @@ -37,31 +36,31 @@ #include <linux/mmc/host.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach-types.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <linux/platform_data/mmc-s3cmci.h> +#include <linux/platform_data/mtd-nand-s3c2410.h> +#include <linux/platform_data/touchscreen-s3c2410.h> +#include <linux/platform_data/usb-s3c2410_udc.h> + +#include <sound/uda1380.h> + +#include <mach/fb.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> -#include <mach/h1940.h> -#include <mach/fb.h> #include <plat/clock.h> -#include <plat/regs-serial.h> -#include <plat/regs-iic.h> -#include <linux/platform_data/mmc-s3cmci.h> -#include <linux/platform_data/usb-s3c2410_udc.h> -#include <linux/platform_data/mtd-nand-s3c2410.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/devs.h> #include <plat/cpu.h> +#include <plat/devs.h> #include <plat/pm.h> -#include <plat/irq.h> -#include <linux/platform_data/touchscreen-s3c2410.h> - -#include <sound/uda1380.h> +#include <plat/regs-iic.h> +#include <plat/regs-serial.h> #include "common.h" +#include "h1940.h" #define LCD_PWM_PERIOD 192960 #define LCD_PWM_DUTY 127353 @@ -814,6 +813,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950") .reserve = rx1950_reserve, .init_irq = s3c24xx_init_irq, .init_machine = rx1950_init_machine, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c index dacbb9a2122..f20418a2fb1 100644 --- a/arch/arm/mach-s3c24xx/mach-rx3715.c +++ b/arch/arm/mach-s3c24xx/mach-rx3715.c @@ -31,27 +31,27 @@ #include <linux/mtd/partitions.h> #include <asm/mach/arch.h> -#include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <asm/mach/map.h> + +#include <linux/platform_data/mtd-nand-s3c2410.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> +#include <mach/fb.h> +#include <mach/hardware.h> #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> -#include <mach/h1940.h> -#include <linux/platform_data/mtd-nand-s3c2410.h> -#include <mach/fb.h> - #include <plat/clock.h> -#include <plat/devs.h> #include <plat/cpu.h> +#include <plat/devs.h> #include <plat/pm.h> +#include <plat/regs-serial.h> #include "common.h" +#include "h1940.h" static struct map_desc rx3715_iodesc[] __initdata = { /* dump ISA space somewhere unused */ @@ -212,6 +212,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715") .reserve = rx3715_reserve, .init_irq = rx3715_init_irq, .init_machine = rx3715_init_machine, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c index 82796b97cb0..e184bfa9613 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c @@ -117,6 +117,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc .map_io = smdk2410_map_io, .init_irq = s3c24xx_init_irq, .init_machine = smdk2410_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c index ce99fd8bbbc..86d7847c9d4 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c @@ -37,7 +37,6 @@ #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> -#include <mach/idle.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/i2c-s3c2410.h> #include <mach/fb.h> @@ -133,7 +132,7 @@ MACHINE_START(S3C2413, "S3C2413") .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END @@ -145,7 +144,7 @@ MACHINE_START(SMDK2412, "SMDK2412") .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END @@ -157,6 +156,6 @@ MACHINE_START(SMDK2413, "SMDK2413") .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c index f30d7fccbfe..ebb2e61f3d0 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -39,7 +39,6 @@ #include <mach/regs-lcd.h> #include <mach/regs-s3c2443-clock.h> -#include <mach/idle.h> #include <linux/platform_data/leds-s3c24xx.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -251,9 +250,9 @@ MACHINE_START(SMDK2416, "SMDK2416") /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */ .atag_offset = 0x100, - .init_irq = s3c24xx_init_irq, + .init_irq = s3c2416_init_irq, .map_io = smdk2416_map_io, .init_machine = smdk2416_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2416_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c index b7ff882c6ce..08cc38c8a4a 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2440.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c @@ -35,7 +35,6 @@ #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> -#include <mach/idle.h> #include <mach/fb.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -182,6 +181,6 @@ MACHINE_START(S3C2440, "SMDK2440") .init_irq = s3c24xx_init_irq, .map_io = smdk2440_map_io, .init_machine = smdk2440_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c index 2568656f046..fc65d74d3c7 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c @@ -35,7 +35,6 @@ #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> -#include <mach/idle.h> #include <mach/fb.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -141,9 +140,9 @@ MACHINE_START(SMDK2443, "SMDK2443") /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ .atag_offset = 0x100, - .init_irq = s3c24xx_init_irq, + .init_irq = s3c2443_init_irq, .map_io = smdk2443_map_io, .init_machine = smdk2443_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2443_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c index 495bf5cf52e..24b3d79e7b2 100644 --- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c @@ -149,6 +149,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER") .map_io = tct_hammer_map_io, .init_irq = s3c24xx_init_irq, .init_machine = tct_hammer_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c index 14d5b12e388..ec42d1e4e46 100644 --- a/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/arch/arm/mach-s3c24xx/mach-vr1000.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2410/mach-vr1000.c - * +/* * Copyright (c) 2003-2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * @@ -32,27 +31,25 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/bast-map.h> -#include <mach/vr1000-map.h> -#include <mach/vr1000-irq.h> -#include <mach/vr1000-cpld.h> - -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <plat/regs-serial.h> -#include <mach/regs-gpio.h> #include <linux/platform_data/leds-s3c24xx.h> +#include <linux/platform_data/i2c-s3c2410.h> +#include <linux/platform_data/asoc-s3c24xx_simtec.h> + +#include <mach/hardware.h> +#include <mach/regs-gpio.h> #include <plat/clock.h> -#include <plat/devs.h> #include <plat/cpu.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/asoc-s3c24xx_simtec.h> +#include <plat/devs.h> +#include <plat/regs-serial.h> -#include "simtec.h" +#include "bast.h" #include "common.h" +#include "simtec.h" +#include "vr1000.h" /* macros for virtual address mods for the io space entries */ #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) @@ -143,7 +140,7 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { static struct plat_serial8250_port serial_platform_data[] = { [0] = { .mapbase = VR1000_SERIAL_MAPBASE(0), - .irq = IRQ_VR1000_SERIAL + 0, + .irq = VR1000_IRQ_SERIAL + 0, .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, .iotype = UPIO_MEM, .regshift = 0, @@ -151,7 +148,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, [1] = { .mapbase = VR1000_SERIAL_MAPBASE(1), - .irq = IRQ_VR1000_SERIAL + 1, + .irq = VR1000_IRQ_SERIAL + 1, .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, .iotype = UPIO_MEM, .regshift = 0, @@ -159,7 +156,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, [2] = { .mapbase = VR1000_SERIAL_MAPBASE(2), - .irq = IRQ_VR1000_SERIAL + 2, + .irq = VR1000_IRQ_SERIAL + 2, .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, .iotype = UPIO_MEM, .regshift = 0, @@ -167,7 +164,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, [3] = { .mapbase = VR1000_SERIAL_MAPBASE(3), - .irq = IRQ_VR1000_SERIAL + 3, + .irq = VR1000_IRQ_SERIAL + 3, .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, .iotype = UPIO_MEM, .regshift = 0, @@ -189,14 +186,14 @@ static struct platform_device serial_device = { static struct resource vr1000_dm9k0_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4), [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40), - [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \ + [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000A, 1, NULL, IORESOURCE_IRQ \ | IORESOURCE_IRQ_HIGHLEVEL), }; static struct resource vr1000_dm9k1_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4), [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40), - [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \ + [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000N, 1, NULL, IORESOURCE_IRQ \ | IORESOURCE_IRQ_HIGHLEVEL), }; @@ -357,6 +354,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000") .map_io = vr1000_map_io, .init_machine = vr1000_init, .init_irq = s3c24xx_init_irq, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c index f1d44ae1183..3e2bfddc9df 100644 --- a/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/arch/arm/mach-s3c24xx/mach-vstms.c @@ -36,7 +36,6 @@ #include <mach/regs-gpio.h> #include <mach/regs-lcd.h> -#include <mach/idle.h> #include <mach/fb.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -161,6 +160,6 @@ MACHINE_START(VSTMS, "VSTMS") .init_irq = s3c24xx_init_irq, .init_machine = vstms_init, .map_io = vstms_map_io, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/osiris.h index 17380f84842..b8d56074aba 100644 --- a/arch/arm/mach-s3c24xx/include/mach/osiris-map.h +++ b/arch/arm/mach-s3c24xx/osiris.h @@ -1,9 +1,9 @@ -/* arch/arm/mach-s3c2410/include/mach/osiris-map.h - * +/* * Copyright 2005 Simtec Electronics * http://www.simtec.co.uk/products/ * Ben Dooks <ben@simtec.co.uk> * + * OSIRIS - CPLD control constants * OSIRIS - Memory map definitions * * This program is free software; you can redistribute it and/or modify @@ -11,10 +11,21 @@ * published by the Free Software Foundation. */ -/* needs arch/map.h including with this */ +#ifndef __MACH_S3C24XX_OSIRIS_H +#define __MACH_S3C24XX_OSIRIS_H __FILE__ + +/* CTRL0 - NAND WP control */ + +#define OSIRIS_CTRL0_NANDSEL (0x3) +#define OSIRIS_CTRL0_BOOT_INT (1<<3) +#define OSIRIS_CTRL0_PCMCIA (1<<4) +#define OSIRIS_CTRL0_FIX8 (1<<5) +#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) +#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) + +#define OSIRIS_CTRL1_FIX8 (1<<0) -#ifndef __ASM_ARCH_OSIRISMAP_H -#define __ASM_ARCH_OSIRISMAP_H +#define OSIRIS_ID_REVMASK (0x7) /* start peripherals off after the S3C2410 */ @@ -39,4 +50,4 @@ #define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) #define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) -#endif /* __ASM_ARCH_OSIRISMAP_H */ +#endif /* __MACH_S3C24XX_OSIRIS_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/otom.h index f9277a52c14..321b7be1c0f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/otom-map.h +++ b/arch/arm/mach-s3c24xx/otom.h @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/otom-map.h - * +/* * (c) 2005 Guillaume GOURAT / NexVision * guillaume.gourat@nexvision.fr * @@ -10,21 +9,20 @@ * published by the Free Software Foundation. */ -/* needs arch/map.h including with this */ - -/* ok, we've used up to 0x01300000, now we need to find space for the +/* + * ok, we've used up to 0x01300000, now we need to find space for the * peripherals that live in the nGCS[x] areas, which are quite numerous * in their space. */ -#ifndef __ASM_ARCH_OTOMMAP_H -#define __ASM_ARCH_OTOMMAP_H +#ifndef __MACH_S3C24XX_OTOM_H +#define __MACH_S3C24XX_OTOM_H __FILE__ -#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */ -#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */ +#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */ +#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */ /* physical offset addresses for the peripherals */ -#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */ +#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) -#endif /* __ASM_ARCH_OTOMMAP_H */ +#endif /* __MACH_S3C24XX_OTOM_H */ diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c index e0b3b347da8..dcf3420a327 100644 --- a/arch/arm/mach-s3c2410/pll.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2410/pll.c - * +/* * Copyright (c) 2006-2007 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -82,7 +81,6 @@ static int __init s3c2410_pll_init(void) return subsys_interface_register(&s3c2410_plls_interface); } - arch_initcall(s3c2410_pll_init); static struct subsys_interface s3c2410a_plls_interface = { @@ -95,5 +93,4 @@ static int __init s3c2410a_pll_init(void) { return subsys_interface_register(&s3c2410a_plls_interface); } - arch_initcall(s3c2410a_pll_init); diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c index 551fb433be8..67378175831 100644 --- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2440/s3c2440-pll-12000000.c - * +/* * Copyright (c) 2006-2007 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -83,7 +82,6 @@ static int __init s3c2440_pll_12mhz(void) return subsys_interface_register(&s3c2440_plls12_interface); } - arch_initcall(s3c2440_pll_12mhz); static struct subsys_interface s3c2442_plls12_interface = { @@ -97,5 +95,4 @@ static int __init s3c2442_pll_12mhz(void) return subsys_interface_register(&s3c2442_plls12_interface); } - arch_initcall(s3c2442_pll_12mhz); diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c index 3f15bcf6429..debfa106289 100644 --- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2440/s3c2440-pll-16934400.c - * +/* * Copyright (c) 2006-2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> @@ -111,7 +110,6 @@ static int __init s3c2440_pll_16934400(void) { return subsys_interface_register(&s3c2440_plls169344_interface); } - arch_initcall(s3c2440_pll_16934400); static struct subsys_interface s3c2442_plls169344_interface = { @@ -124,5 +122,4 @@ static int __init s3c2442_pll_16934400(void) { return subsys_interface_register(&s3c2442_plls169344_interface); } - arch_initcall(s3c2442_pll_16934400); diff --git a/arch/arm/mach-s3c24xx/pm-h1940.S b/arch/arm/mach-s3c24xx/pm-h1940.S index c93bf2db9f4..6183a688012 100644 --- a/arch/arm/mach-s3c24xx/pm-h1940.S +++ b/arch/arm/mach-s3c24xx/pm-h1940.S @@ -30,4 +30,4 @@ h1940_pm_return: mov r0, #S3C2410_PA_GPIO - ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ] + ldr pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO] diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c index 949ae05e07c..2d82c4f116c 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2410.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c @@ -29,16 +29,16 @@ #include <linux/gpio.h> #include <linux/io.h> -#include <mach/hardware.h> - #include <asm/mach-types.h> +#include <mach/hardware.h> #include <mach/regs-gpio.h> -#include <mach/h1940.h> #include <plat/cpu.h> #include <plat/pm.h> +#include "h1940.h" + static void s3c2410_pm_prepare(void) { /* ensure at least GSTATUS3 has the resume address */ diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c index c60f67a75af..668a78a8b19 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c @@ -21,19 +21,19 @@ #include <linux/platform_device.h> #include <linux/io.h> -#include <mach/hardware.h> #include <asm/cacheflush.h> #include <asm/irq.h> -#include <mach/regs-power.h> +#include <mach/hardware.h> #include <mach/regs-gpio.h> -#include <mach/regs-dsc.h> #include <plat/cpu.h> #include <plat/pm.h> - #include <plat/s3c2412.h> +#include "regs-dsc.h" +#include "s3c2412-power.h" + extern void s3c2412_sleep_enter(void); static int s3c2412_cpu_suspend(unsigned long arg) @@ -48,7 +48,8 @@ static int s3c2412_cpu_suspend(unsigned long arg) s3c2412_sleep_enter(); - panic("sleep resumed to originator?"); + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ } static void s3c2412_pm_prepare(void) diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c index 1bd4817b8eb..44923895f55 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2416.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c @@ -16,12 +16,13 @@ #include <asm/cacheflush.h> -#include <mach/regs-power.h> #include <mach/regs-s3c2443-clock.h> #include <plat/cpu.h> #include <plat/pm.h> +#include "s3c2412-power.h" + extern void s3c2412_sleep_enter(void); static int s3c2416_cpu_suspend(unsigned long arg) @@ -34,7 +35,8 @@ static int s3c2416_cpu_suspend(unsigned long arg) s3c2412_sleep_enter(); - panic("sleep resumed to originator?"); + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ } static void s3c2416_pm_prepare(void) diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c index 724755f0b0f..caa5b721138 100644 --- a/arch/arm/mach-s3c24xx/pm.c +++ b/arch/arm/mach-s3c24xx/pm.c @@ -38,7 +38,6 @@ #include <plat/regs-serial.h> #include <mach/regs-clock.h> #include <mach/regs-gpio.h> -#include <mach/regs-mem.h> #include <mach/regs-irq.h> #include <asm/mach/time.h> @@ -46,6 +45,8 @@ #include <plat/gpio-cfg.h> #include <plat/pm.h> +#include "regs-mem.h" + #define PFX "s3c24xx-pm: " static struct sleep_save core_save[] = { diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h index 98fd4a05587..98fd4a05587 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h +++ b/arch/arm/mach-s3c24xx/regs-dsc.h diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c24xx/regs-mem.h new file mode 100644 index 00000000000..86b1258368c --- /dev/null +++ b/arch/arm/mach-s3c24xx/regs-mem.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 Memory Control register definitions + */ + +#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H +#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__ + +#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) + +#define S3C2410_BWSCON S3C2410_MEMREG(0x00) +#define S3C2410_BANKCON0 S3C2410_MEMREG(0x04) +#define S3C2410_BANKCON1 S3C2410_MEMREG(0x08) +#define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C) +#define S3C2410_BANKCON3 S3C2410_MEMREG(0x10) +#define S3C2410_BANKCON4 S3C2410_MEMREG(0x14) +#define S3C2410_BANKCON5 S3C2410_MEMREG(0x18) +#define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C) +#define S3C2410_BANKCON7 S3C2410_MEMREG(0x20) +#define S3C2410_REFRESH S3C2410_MEMREG(0x24) +#define S3C2410_BANKSIZE S3C2410_MEMREG(0x28) + +#define S3C2410_BWSCON_ST1 (1 << 7) +#define S3C2410_BWSCON_ST2 (1 << 11) +#define S3C2410_BWSCON_ST3 (1 << 15) +#define S3C2410_BWSCON_ST4 (1 << 19) +#define S3C2410_BWSCON_ST5 (1 << 23) + +#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) + +#define S3C2410_BWSCON_WS (1 << 2) + +#define S3C2410_BANKCON_PMC16 (0x3) + +#define S3C2410_BANKCON_Tacp_SHIFT (2) +#define S3C2410_BANKCON_Tcah_SHIFT (4) +#define S3C2410_BANKCON_Tcoh_SHIFT (6) +#define S3C2410_BANKCON_Tacc_SHIFT (8) +#define S3C2410_BANKCON_Tcos_SHIFT (11) +#define S3C2410_BANKCON_Tacs_SHIFT (13) + +#define S3C2410_BANKCON_SDRAM (0x3 << 15) + +#define S3C2410_REFRESH_SELF (1 << 22) + +#define S3C2410_BANKSIZE_MASK (0x7 << 0) + +#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */ diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c index a3c5cb086ee..9ebef95da72 100644 --- a/arch/arm/mach-s3c24xx/s3c2410.c +++ b/arch/arm/mach-s3c24xx/s3c2410.c @@ -49,6 +49,8 @@ #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> +#include "common.h" + /* Initial IO mappings */ static struct map_desc s3c2410_iodesc[] __initdata = { @@ -182,8 +184,8 @@ int __init s3c2410_init(void) #ifdef CONFIG_PM register_syscore_ops(&s3c2410_pm_syscore_ops); -#endif register_syscore_ops(&s3c24xx_irq_syscore_ops); +#endif return device_register(&s3c2410_dev); } diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c24xx/s3c2412-power.h new file mode 100644 index 00000000000..1b02c5ddb31 --- /dev/null +++ b/arch/arm/mach-s3c24xx/s3c2412-power.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H +#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__ + +#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) + +#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) +#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) + +#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) +#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) +#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) +#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) + +#define S3C2412_PWRCFG_BATF_IRQ (1 << 0) +#define S3C2412_PWRCFG_BATF_IGNORE (2 << 0) +#define S3C2412_PWRCFG_BATF_SLEEP (3 << 0) +#define S3C2412_PWRCFG_BATF_MASK (3 << 0) + +#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0 << 6) +#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1 << 6) +#define S3C2412_PWRCFG_STANDBYWFI_STOP (2 << 6) +#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3 << 6) +#define S3C2412_PWRCFG_STANDBYWFI_MASK (3 << 6) + +#define S3C2412_PWRCFG_RTC_MASKIRQ (1 << 8) +#define S3C2412_PWRCFG_NAND_NORST (1 << 9) + +#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */ diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index 6c5f4031ff0..0d592159a5c 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s3c2412/s3c2412.c - * +/* * Copyright (c) 2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * @@ -28,28 +27,31 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/proc-fns.h> #include <asm/irq.h> #include <asm/system_misc.h> -#include <plat/cpu-freq.h> - +#include <mach/hardware.h> #include <mach/regs-clock.h> -#include <plat/regs-serial.h> -#include <mach/regs-power.h> #include <mach/regs-gpio.h> -#include <mach/regs-dsc.h> -#include <plat/regs-spi.h> -#include <mach/regs-s3c2412.h> -#include <plat/s3c2412.h> +#include <plat/clock.h> #include <plat/cpu.h> +#include <plat/cpu-freq.h> #include <plat/devs.h> -#include <plat/clock.h> -#include <plat/pm.h> -#include <plat/pll.h> #include <plat/nand-core.h> +#include <plat/pll.h> +#include <plat/pm.h> +#include <plat/regs-serial.h> +#include <plat/regs-spi.h> +#include <plat/s3c2412.h> + +#include "common.h" +#include "regs-dsc.h" +#include "s3c2412-power.h" + +#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) +#define S3C2412_SWRST_RESET (0x533C2412) #ifndef CONFIG_CPU_S3C2412_ONLY void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; @@ -244,8 +246,8 @@ int __init s3c2412_init(void) #ifdef CONFIG_PM register_syscore_ops(&s3c2412_pm_syscore_ops); -#endif register_syscore_ops(&s3c24xx_irq_syscore_ops); +#endif return device_register(&s3c2412_dev); } diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/s3c2412.h new file mode 100644 index 00000000000..548ced42cbb --- /dev/null +++ b/arch/arm/mach-s3c24xx/s3c2412.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H +#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__ + +#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) +#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) + +#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) +#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) + +#define S3C2412_REFRESH S3C2412_MEMREG(0x10) + +#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4) + +#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0) + +#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */ diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c index 77ee0b73223..e30476db029 100644 --- a/arch/arm/mach-s3c24xx/s3c2416.c +++ b/arch/arm/mach-s3c24xx/s3c2416.c @@ -63,6 +63,8 @@ #include <plat/rtc-core.h> #include <plat/spi-core.h> +#include "common.h" + static struct map_desc s3c2416_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), IODESC_ENT(CLKPWR), @@ -105,9 +107,9 @@ int __init s3c2416_init(void) #ifdef CONFIG_PM register_syscore_ops(&s3c2416_pm_syscore_ops); -#endif register_syscore_ops(&s3c24xx_irq_syscore_ops); register_syscore_ops(&s3c2416_irq_syscore_ops); +#endif return device_register(&s3c2416_dev); } diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c index 2b3dddb49af..559e394e898 100644 --- a/arch/arm/mach-s3c24xx/s3c2440.c +++ b/arch/arm/mach-s3c24xx/s3c2440.c @@ -40,6 +40,8 @@ #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> +#include "common.h" + static struct device s3c2440_dev = { .bus = &s3c2440_subsys, }; @@ -57,9 +59,9 @@ int __init s3c2440_init(void) #ifdef CONFIG_PM register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); #endif register_syscore_ops(&s3c244x_pm_syscore_ops); - register_syscore_ops(&s3c24xx_irq_syscore_ops); /* register our system device for everything else */ diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c index 22cb7c94a8c..f732826c235 100644 --- a/arch/arm/mach-s3c24xx/s3c2442.c +++ b/arch/arm/mach-s3c24xx/s3c2442.c @@ -51,6 +51,8 @@ #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> +#include "common.h" + /* S3C2442 extended clock support */ static unsigned long s3c2442_camif_upll_round(struct clk *clk, @@ -172,9 +174,9 @@ int __init s3c2442_init(void) #ifdef CONFIG_PM register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); #endif register_syscore_ops(&s3c244x_pm_syscore_ops); - register_syscore_ops(&s3c24xx_irq_syscore_ops); return device_register(&s3c2442_dev); } diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index b0b60a1154d..ad2671baa91 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c @@ -36,7 +36,6 @@ #include <mach/regs-clock.h> #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <mach/regs-dsc.h> #include <plat/s3c2410.h> #include <plat/s3c244x.h> @@ -48,6 +47,8 @@ #include <plat/nand-core.h> #include <plat/watchdog-reset.h> +#include "regs-dsc.h" + static struct map_desc s3c244x_iodesc[] __initdata = { IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c index fd0ef05763a..67cb5120dfe 100644 --- a/arch/arm/mach-s3c24xx/simtec-audio.c +++ b/arch/arm/mach-s3c24xx/simtec-audio.c @@ -17,16 +17,13 @@ #include <linux/device.h> #include <linux/io.h> -#include <mach/bast-map.h> -#include <mach/bast-irq.h> -#include <mach/bast-cpld.h> - #include <mach/hardware.h> #include <mach/regs-gpio.h> #include <linux/platform_data/asoc-s3c24xx_simtec.h> #include <plat/devs.h> +#include "bast.h" #include "simtec.h" /* platform ops for audio */ diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c index 029744fcaac..8884bffa619 100644 --- a/arch/arm/mach-s3c24xx/simtec-nor.c +++ b/arch/arm/mach-s3c24xx/simtec-nor.c @@ -27,9 +27,8 @@ #include <asm/mach/irq.h> #include <mach/map.h> -#include <mach/bast-map.h> -#include <mach/bast-cpld.h> +#include "bast.h" #include "simtec.h" static void simtec_nor_vpp(struct platform_device *pdev, int vpp) diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c24xx/simtec-pm.c index 699f9317129..38a2f1fdeba 100644 --- a/arch/arm/mach-s3c24xx/simtec-pm.c +++ b/arch/arm/mach-s3c24xx/simtec-pm.c @@ -28,12 +28,13 @@ #include <mach/map.h> #include <mach/regs-gpio.h> -#include <mach/regs-mem.h> #include <asm/mach-types.h> #include <plat/pm.h> +#include "regs-mem.h" + #define COPYRIGHT ", Copyright 2005 Simtec Electronics" /* pm_simtec_init diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c index ddf7a3c743a..2ed2e32430d 100644 --- a/arch/arm/mach-s3c24xx/simtec-usb.c +++ b/arch/arm/mach-s3c24xx/simtec-usb.c @@ -28,15 +28,13 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/bast-map.h> -#include <mach/bast-irq.h> - #include <mach/hardware.h> #include <asm/irq.h> #include <linux/platform_data/usb-ohci-s3c2410.h> #include <plat/devs.h> +#include "bast.h" #include "simtec.h" /* control power and monitor over-current events on various Simtec @@ -79,7 +77,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) int ret; if (on) { - ret = request_irq(IRQ_USBOC, usb_simtec_ocirq, + ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "USB Over-current", info); @@ -87,7 +85,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) printk(KERN_ERR "failed to request usb oc irq\n"); } } else { - free_irq(IRQ_USBOC, info); + free_irq(BAST_IRQ_USBOC, info); } } diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S index dd5b6388a5a..dd47c8fa07f 100644 --- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S +++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S @@ -31,9 +31,10 @@ #include <mach/regs-gpio.h> #include <mach/regs-clock.h> -#include <mach/regs-mem.h> #include <plat/regs-serial.h> +#include "regs-mem.h" + /* s3c2410_cpu_suspend * * put the cpu into sleep mode @@ -45,9 +46,9 @@ ENTRY(s3c2410_cpu_suspend) ldr r4, =S3C2410_REFRESH ldr r5, =S3C24XX_MISCCR ldr r6, =S3C2410_CLKCON - ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB) - ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB) - ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB) + ldr r7, [r4] @ get REFRESH (and ensure in TLB) + ldr r8, [r5] @ get MISCCR (and ensure in TLB) + ldr r9, [r6] @ get CLKCON (and ensure in TLB) orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals @@ -61,8 +62,8 @@ ENTRY(s3c2410_cpu_suspend) @@ align next bit of code to cache line .align 5 s3c2410_do_sleep: - streq r7, [ r4 ] @ SDRAM sleep command - streq r8, [ r5 ] @ SDRAM power-down config - streq r9, [ r6 ] @ CPU sleep + streq r7, [r4] @ SDRAM sleep command + streq r8, [r5] @ SDRAM power-down config + streq r9, [r6] @ CPU sleep 1: beq 1b mov pc, r14 diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2412.S b/arch/arm/mach-s3c24xx/sleep-s3c2412.S index c82418ed714..5adaceb7da1 100644 --- a/arch/arm/mach-s3c24xx/sleep-s3c2412.S +++ b/arch/arm/mach-s3c24xx/sleep-s3c2412.S @@ -57,12 +57,12 @@ s3c2412_sleep_enter1: * retry, as simply returning causes the system to lock. */ - ldrne r9, [ r1 ] - strne r9, [ r1 ] - ldrne r9, [ r2 ] - strne r9, [ r2 ] - ldrne r9, [ r3 ] - strne r9, [ r3 ] + ldrne r9, [r1] + strne r9, [r1] + ldrne r9, [r2] + strne r9, [r2] + ldrne r9, [r3] + strne r9, [r3] bne s3c2412_sleep_enter1 mov pc, r14 diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S index c56612569b4..7f378b662da 100644 --- a/arch/arm/mach-s3c24xx/sleep.S +++ b/arch/arm/mach-s3c24xx/sleep.S @@ -31,7 +31,6 @@ #include <mach/regs-gpio.h> #include <mach/regs-clock.h> -#include <mach/regs-mem.h> #include <plat/regs-serial.h> /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c24xx/vr1000.h new file mode 100644 index 00000000000..7fcd2c2f183 --- /dev/null +++ b/arch/arm/mach-s3c24xx/vr1000.h @@ -0,0 +1,118 @@ + +/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h + * + * Copyright (c) 2003 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * VR1000 - CPLD control constants + * Machine VR1000 - IRQ Number definitions + * Machine VR1000 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __MACH_S3C24XX_VR1000_H +#define __MACH_S3C24XX_VR1000_H __FILE__ + +#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ + +/* irq numbers to onboard peripherals */ + +#define VR1000_IRQ_USBOC IRQ_EINT19 +#define VR1000_IRQ_IDE0 IRQ_EINT16 +#define VR1000_IRQ_IDE1 IRQ_EINT17 +#define VR1000_IRQ_SERIAL IRQ_EINT12 +#define VR1000_IRQ_DM9000A IRQ_EINT10 +#define VR1000_IRQ_DM9000N IRQ_EINT9 +#define VR1000_IRQ_SMALERT IRQ_EINT8 + +/* map */ + +#define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) + +/* we put the CPLD registers next, to get them out of the way */ + +#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ +#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) + +#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ +#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) + +#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ +#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) + +#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ +#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) + +/* next, we have the PC104 ISA interrupt registers */ + +#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ +#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) + +#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ +#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) + +#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ +#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) + +/* + * 0xE0000000 contains the IO space that is split by speed and + * whether the access is for 8 or 16bit IO... this ensures that + * the correct access is made + * + * 0x10000000 of space, partitioned as so: + * + * 0x00000000 to 0x04000000 8bit, slow + * 0x04000000 to 0x08000000 16bit, slow + * 0x08000000 to 0x0C000000 16bit, net + * 0x0C000000 to 0x10000000 16bit, fast + * + * each of these spaces has the following in: + * + * 0x02000000 to 0x02100000 1MB IDE primary channel + * 0x02100000 to 0x02200000 1MB IDE primary channel aux + * 0x02200000 to 0x02400000 1MB IDE secondary channel + * 0x02300000 to 0x02400000 1MB IDE secondary channel aux + * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers + * 0x02600000 to 0x02700000 1MB + * + * the phyiscal layout of the zones are: + * nGCS2 - 8bit, slow + * nGCS3 - 16bit, slow + * nGCS4 - 16bit, net + * nGCS5 - 16bit, fast + */ + +#define VR1000_VA_MULTISPACE (0xE0000000) + +#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) +#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) +#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) +#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) +#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) +#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) +#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) +#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) +#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) + +/* physical offset addresses for the peripherals */ + +#define VR1000_PA_IDEPRI (0x02000000) +#define VR1000_PA_IDEPRIAUX (0x02800000) +#define VR1000_PA_IDESEC (0x03000000) +#define VR1000_PA_IDESECAUX (0x03800000) +#define VR1000_PA_DM9000 (0x05000000) + +#define VR1000_PA_SERIAL (0x11800000) +#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) + +/* VR1000 ram is in CS1, with A26..A24 = 2_101 */ +#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) + +/* some configurations for the peripherals */ + +#define VR1000_DM9000_CS VR1000_VAM_CS4 + +#endif /* __MACH_S3C24XX_VR1000_H */ diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 803711e283b..8499415be9c 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -23,7 +23,6 @@ #include <mach/hardware.h> #include <mach/map.h> -#include <mach/regs-sys.h> #include <mach/regs-clock.h> #include <plat/cpu.h> @@ -33,6 +32,8 @@ #include <plat/clock-clksrc.h> #include <plat/pll.h> +#include "regs-sys.h" + /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call * ext_xtal_mux for want of an actual name from the manual. */ diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index aef303b8997..0b9c0ba4483 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -25,10 +25,10 @@ #include <linux/dma-mapping.h> #include <linux/irq.h> #include <linux/gpio.h> +#include <linux/irqchip/arm-vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/hardware/vic.h> #include <asm/system_misc.h> #include <mach/map.h> diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c index acb197ccf3f..ead5fab0dbb 100644 --- a/arch/arm/mach-s3c64xx/cpuidle.c +++ b/arch/arm/mach-s3c64xx/cpuidle.c @@ -20,8 +20,8 @@ #include <mach/map.h> -#include <mach/regs-sys.h> -#include <mach/regs-syscon-power.h> +#include "regs-sys.h" +#include "regs-syscon-power.h" static int s3c64xx_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/crag6410.h index 4c3c9994fc2..4c3c9994fc2 100644 --- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h +++ b/arch/arm/mach-s3c64xx/crag6410.h diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index f2a7a172559..ec29b35f25c 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -28,10 +28,10 @@ #include <mach/map.h> #include <mach/irqs.h> -#include <mach/regs-sys.h> - #include <asm/hardware/pl080.h> +#include "regs-sys.h" + /* dma channel state information */ struct s3c64xx_dmac { diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h index bcce68a0bb7..6a1127891c8 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h @@ -15,6 +15,5 @@ #ifndef __ASM_ARCH_REGS_IRQ_H #define __ASM_ARCH_REGS_IRQ_H __FILE__ -#include <asm/hardware/vic.h> #endif /* __ASM_ARCH_6400_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h deleted file mode 100644 index b91e0209328..00000000000 --- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h +++ /dev/null @@ -1,31 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX system register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_SYS_H -#define __PLAT_REGS_SYS_H __FILE__ - -#define S3C_SYSREG(x) (S3C_VA_SYS + (x)) - -#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100) -#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) -#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) - -#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110) - -#define S3C64XX_OTHERS S3C_SYSREG(0x900) - -#define S3C64XX_OTHERS_USBMASK (1 << 16) -#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6) - -#endif /* _PLAT_REGS_SYS_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h index ebe18a9469b..db9c1b1d56a 100644 --- a/arch/arm/mach-s3c64xx/include/mach/tick.h +++ b/arch/arm/mach-s3c64xx/include/mach/tick.h @@ -15,6 +15,8 @@ #ifndef __ASM_ARCH_TICK_H #define __ASM_ARCH_TICK_H __FILE__ +#include <linux/irqchip/arm-vic.h> + /* note, the timer interrutps turn up in 2 places, the vic and then * the timer block. We take the VIC as the base at the moment. */ diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index 99e82ac81b6..728eef3296b 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -31,7 +31,6 @@ #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -50,9 +49,9 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <mach/regs-gpio.h> -#include <mach/regs-modem.h> #include "common.h" +#include "regs-modem.h" /* DM9000 */ #define ANW6410_PA_DM9000 (0x18000000) @@ -230,10 +229,9 @@ MACHINE_START(ANW6410, "A&W6410") .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = anw6410_map_io, .init_machine = anw6410_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c index 755c0bb119f..bf3d1c09b08 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c @@ -29,7 +29,7 @@ #include <linux/platform_data/spi-s3c64xx.h> -#include <mach/crag6410.h> +#include "crag6410.h" static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = { .line = S3C64XX_GPC(3), diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index bf6311a28f3..1acf02bace5 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -42,7 +42,6 @@ #include <sound/wm1250-ev1.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -50,12 +49,7 @@ #include <mach/hardware.h> #include <mach/map.h> -#include <mach/regs-sys.h> #include <mach/regs-gpio.h> -#include <mach/regs-modem.h> -#include <mach/crag6410.h> - -#include <mach/regs-gpio-memport.h> #include <plat/regs-serial.h> #include <plat/fb.h> @@ -72,6 +66,10 @@ #include <plat/pm.h> #include "common.h" +#include "crag6410.h" +#include "regs-gpio-memport.h" +#include "regs-modem.h" +#include "regs-sys.h" /* serial port setup */ @@ -867,10 +865,9 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */ .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = crag6410_map_io, .init_machine = crag6410_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 2b144893ddc..7212eb9cfeb 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -30,7 +30,6 @@ #include <mach/hardware.h> #include <mach/map.h> -#include <asm/hardware/vic.h> #include <asm/irq.h> #include <asm/mach-types.h> @@ -273,10 +272,9 @@ MACHINE_START(HMT, "Airgoo-HMT") /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */ .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = hmt_map_io, .init_machine = hmt_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index 07c349cca33..4b41fcdaa7b 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -24,15 +24,12 @@ #include <linux/serial_core.h> #include <linux/types.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/map.h> #include <mach/regs-gpio.h> -#include <mach/regs-modem.h> -#include <mach/regs-srom.h> #include <plat/adc.h> #include <plat/cpu.h> @@ -46,6 +43,8 @@ #include <video/samsung_fimd.h> #include "common.h" +#include "regs-modem.h" +#include "regs-srom.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) @@ -352,10 +351,9 @@ MACHINE_START(MINI6410, "MINI6410") /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = mini6410_map_io, .init_machine = mini6410_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index e5f9a79b535..8d3cedd995f 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c @@ -26,7 +26,6 @@ #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -101,10 +100,9 @@ MACHINE_START(NCP, "NCP") /* Maintainer: Samsung Electronics */ .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = ncp_map_io, .init_machine = ncp_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index 7476f7c722a..fa12bd21ad8 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -25,15 +25,12 @@ #include <linux/serial_core.h> #include <linux/types.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/map.h> #include <mach/regs-gpio.h> -#include <mach/regs-modem.h> -#include <mach/regs-srom.h> #include <plat/adc.h> #include <plat/cpu.h> @@ -47,6 +44,8 @@ #include <video/samsung_fimd.h> #include "common.h" +#include "regs-modem.h" +#include "regs-srom.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) @@ -331,10 +330,9 @@ MACHINE_START(REAL6410, "REAL6410") .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = real6410_map_io, .init_machine = real6410_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index c6d7390939a..fc3e9b32e26 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -25,7 +25,6 @@ #include <mach/map.h> #include <mach/regs-gpio.h> -#include <mach/regs-modem.h> #include <plat/clock.h> #include <plat/cpu.h> @@ -41,6 +40,7 @@ #include <video/platform_lcd.h> #include "common.h" +#include "regs-modem.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c index 96d6da2b6b5..ca2afcfce57 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c @@ -17,7 +17,6 @@ #include <linux/leds.h> #include <linux/platform_device.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -153,10 +152,9 @@ MACHINE_START(SMARTQ5, "SmartQ 5") /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = smartq_map_io, .init_machine = smartq5_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c index 7d1167bdc92..37bb0c632a5 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c @@ -17,7 +17,6 @@ #include <linux/leds.h> #include <linux/platform_device.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -169,10 +168,9 @@ MACHINE_START(SMARTQ7, "SmartQ 7") /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = smartq_map_io, .init_machine = smartq7_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index a928fae5694..a392869c834 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c @@ -22,7 +22,6 @@ #include <asm/mach-types.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -90,10 +89,9 @@ MACHINE_START(SMDK6400, "SMDK6400") .atag_offset = 0x100, .init_irq = s3c6400_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdk6400_map_io, .init_machine = smdk6400_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 574a9eef588..ba7544e2d04 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -45,7 +45,6 @@ #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> @@ -57,10 +56,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> -#include <mach/regs-modem.h> #include <mach/regs-gpio.h> -#include <mach/regs-sys.h> -#include <mach/regs-srom.h> #include <linux/platform_data/ata-samsung_cf.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/fb.h> @@ -75,6 +71,9 @@ #include <plat/backlight.h> #include "common.h" +#include "regs-modem.h" +#include "regs-srom.h" +#include "regs-sys.h" #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB @@ -700,10 +699,9 @@ MACHINE_START(SMDK6410, "SMDK6410") .atag_offset = 0x100, .init_irq = s3c6410_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdk6410_map_io, .init_machine = smdk6410_machine_init, .init_late = s3c64xx_init_late, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index d2e1a16690b..6a1f91fea67 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -26,12 +26,13 @@ #include <plat/pm.h> #include <plat/wakeup-mask.h> -#include <mach/regs-sys.h> #include <mach/regs-gpio.h> #include <mach/regs-clock.h> -#include <mach/regs-syscon-power.h> -#include <mach/regs-gpio-memport.h> -#include <mach/regs-modem.h> + +#include "regs-gpio-memport.h" +#include "regs-modem.h" +#include "regs-sys.h" +#include "regs-syscon-power.h" struct s3c64xx_pm_domain { char *const name; @@ -296,7 +297,8 @@ static int s3c64xx_cpu_suspend(unsigned long arg) /* we should never get past here */ - panic("sleep resumed to originator?"); + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ } /* mapping of interrupts to parts of the wakeup mask */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h b/arch/arm/mach-s3c64xx/regs-gpio-memport.h index 82342f6fd27..b927593019f 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-gpio-memport.h +++ b/arch/arm/mach-s3c64xx/regs-gpio-memport.h @@ -1,5 +1,4 @@ -/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h - * +/* * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> @@ -8,8 +7,8 @@ * S3C64XX - GPIO memory port register definitions */ -#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H -#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ +#ifndef __MACH_S3C64XX_REGS_GPIO_MEMPORT_H +#define __MACH_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) @@ -21,5 +20,5 @@ #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4) -#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */ +#endif /* __MACH_S3C64XX_REGS_GPIO_MEMPORT_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h b/arch/arm/mach-s3c64xx/regs-modem.h index 49f7759dedf..073cdd3a03b 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-modem.h +++ b/arch/arm/mach-s3c64xx/regs-modem.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h - * +/* * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ @@ -12,10 +11,10 @@ * published by the Free Software Foundation. */ -#ifndef __PLAT_S3C64XX_REGS_MODEM_H -#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__ +#ifndef __MACH_S3C64XX_REGS_MODEM_H +#define __MACH_S3C64XX_REGS_MODEM_H __FILE__ -#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) +#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) #define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0) #define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4) @@ -28,4 +27,4 @@ #define MIFPCON_INT2M_LEVEL (1 << 4) #define MIFPCON_LCD_BYPASS (1 << 3) -#endif /* __PLAT_S3C64XX_REGS_MODEM_H */ +#endif /* __MACH_S3C64XX_REGS_MODEM_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h b/arch/arm/mach-s3c64xx/regs-srom.h index 756731b3629..d56f3386eb0 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-srom.h +++ b/arch/arm/mach-s3c64xx/regs-srom.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h - * +/* * Copyright 2009 Andy Green <andy@warmcat.com> * * S3C64XX SROM definitions @@ -9,8 +8,8 @@ * published by the Free Software Foundation. */ -#ifndef __PLAT_REGS_SROM_H -#define __PLAT_REGS_SROM_H __FILE__ +#ifndef __MACH_S3C64XX_REGS_SROM_H +#define __MACH_S3C64XX_REGS_SROM_H __FILE__ #define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) @@ -29,7 +28,7 @@ #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 #define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 -#define S3C64XX_SROM_BW__CS_MASK 0xf +#define S3C64XX_SROM_BW__CS_MASK 0xf #define S3C64XX_SROM_BW__NCS0__SHIFT 0 #define S3C64XX_SROM_BW__NCS1__SHIFT 4 @@ -56,4 +55,4 @@ #define S3C64XX_SROM_BCX__TACS__SHIFT 28 #define S3C64XX_SROM_BCX__TACS__MASK 0xf -#endif /* _PLAT_REGS_SROM_H */ +#endif /* __MACH_S3C64XX_REGS_SROM_H */ diff --git a/arch/arm/mach-s3c64xx/regs-sys.h b/arch/arm/mach-s3c64xx/regs-sys.h new file mode 100644 index 00000000000..8c411fbb0cd --- /dev/null +++ b/arch/arm/mach-s3c64xx/regs-sys.h @@ -0,0 +1,30 @@ +/* + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX system register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __MACH_S3C64XX_REGS_SYS_H +#define __MACH_S3C64XX_REGS_SYS_H __FILE__ + +#define S3C_SYSREG(x) (S3C_VA_SYS + (x)) + +#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100) +#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) +#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) + +#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110) + +#define S3C64XX_OTHERS S3C_SYSREG(0x900) + +#define S3C64XX_OTHERS_USBMASK (1 << 16) +#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6) + +#endif /* __MACH_S3C64XX_REGS_SYS_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h b/arch/arm/mach-s3c64xx/regs-syscon-power.h index 270d96ac970..6e16b3404da 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-syscon-power.h +++ b/arch/arm/mach-s3c64xx/regs-syscon-power.h @@ -1,5 +1,4 @@ -/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h - * +/* * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ @@ -12,8 +11,8 @@ * published by the Free Software Foundation. */ -#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H -#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__ +#ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H +#define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__ #define S3C64XX_PWR_CFG S3C_SYSREG(0x804) @@ -113,4 +112,4 @@ #define S3C64XX_INFORM2 S3C_SYSREG(0xA08) #define S3C64XX_INFORM3 S3C_SYSREG(0xA0C) -#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */ +#endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */ diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c index f6757e02d7d..c8174d95339 100644 --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c @@ -15,11 +15,12 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <mach/map.h> -#include <mach/regs-sys.h> #include <plat/cpu.h> #include <plat/regs-usb-hsotg-phy.h> #include <plat/usb-phy.h> +#include "regs-sys.h" + static int s3c_usb_otgphy_init(struct platform_device *pdev) { struct clk *xusbxti; diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 5112371079d..3537815247f 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -23,7 +23,6 @@ #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/s5p64x0-clock.h> #include <plat/cpu-freq.h> #include <plat/clock.h> @@ -32,6 +31,7 @@ #include <plat/s5p-clock.h> #include <plat/clock-clksrc.h> +#include "clock.h" #include "common.h" static u32 epll_div[][5] = { diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 154dea702d7..af384ddd2dc 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -23,7 +23,6 @@ #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/s5p64x0-clock.h> #include <plat/cpu-freq.h> #include <plat/clock.h> @@ -32,6 +31,7 @@ #include <plat/s5p-clock.h> #include <plat/clock-clksrc.h> +#include "clock.h" #include "common.h" static struct clksrc_clk clk_mout_dpll = { diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/clock.h index 0ef47d1b767..28b8e3c6bd2 100644 --- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h +++ b/arch/arm/mach-s5p64x0/clock.h @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h - * +/* * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com * @@ -10,8 +9,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H __FILE__ +#ifndef __MACH_S5P64X0_CLOCK_H +#define __MACH_S5P64X0_CLOCK_H __FILE__ #include <linux/clk.h> @@ -36,4 +35,4 @@ extern int s5p64x0_mem_ctrl(struct clk *clk, int enable); extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable); -#endif /* __ASM_ARCH_CLOCK_H */ +#endif /* __MACH_S5P64X0_CLOCK_H */ diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c deleted file mode 100644 index 700dac6c43f..00000000000 --- a/arch/arm/mach-s5p64x0/gpiolib.c +++ /dev/null @@ -1,508 +0,0 @@ -/* linux/arch/arm/mach-s5p64x0/gpiolib.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5P64X0 - GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> - -#include <plat/cpu.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -/* - * S5P6440 GPIO bank summary: - * - * Bank GPIOs Style SlpCon ExtInt Group - * A 6 4Bit Yes 1 - * B 7 4Bit Yes 1 - * C 8 4Bit Yes 2 - * F 2 2Bit Yes 4 [1] - * G 7 4Bit Yes 5 - * H 10 4Bit[2] Yes 6 - * I 16 2Bit Yes None - * J 12 2Bit Yes None - * N 16 2Bit No IRQ_EINT - * P 8 2Bit Yes 8 - * R 15 4Bit[2] Yes 8 - * - * S5P6450 GPIO bank summary: - * - * Bank GPIOs Style SlpCon ExtInt Group - * A 6 4Bit Yes 1 - * B 7 4Bit Yes 1 - * C 8 4Bit Yes 2 - * D 8 4Bit Yes None - * F 2 2Bit Yes None - * G 14 4Bit[2] Yes 5 - * H 10 4Bit[2] Yes 6 - * I 16 2Bit Yes None - * J 12 2Bit Yes None - * K 5 4Bit Yes None - * N 16 2Bit No IRQ_EINT - * P 11 2Bit Yes 8 - * Q 14 2Bit Yes None - * R 15 4Bit[2] Yes None - * S 8 2Bit Yes None - * - * [1] BANKF pins 14,15 do not form part of the external interrupt sources - * [2] BANK has two control registers, GPxCON0 and GPxCON1 - */ - -static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long flags; - - switch (offset) { - case 6: - offset += 1; - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - regcon -= 4; - break; - default: - offset -= 7; - break; - } - - s3c_gpio_lock(ourchip, flags); - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); - - s3c_gpio_unlock(ourchip, flags); - - return 0; -} - -static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long dat; - unsigned long flags; - unsigned con_offset = offset; - - switch (con_offset) { - case 6: - con_offset += 1; - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - regcon -= 4; - break; - default: - con_offset -= 7; - break; - } - - s3c_gpio_lock(ourchip, flags); - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(con_offset)); - con |= 0x1 << con_4bit_shift(con_offset); - - dat = __raw_readl(base + GPIODAT_OFF); - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(con, regcon); - __raw_writel(dat, base + GPIODAT_OFF); - - s3c_gpio_unlock(ourchip, flags); - - return 0; -} - -int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift; - u32 con; - - switch (off) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - shift = (off & 7) * 4; - reg -= 4; - break; - case 6: - shift = ((off + 1) & 7) * 4; - reg -= 4; - default: - shift = ((off + 1) & 7) * 4; - break; - } - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0xf << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} - -static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = { - { - .cfg_eint = 0, - }, { - .cfg_eint = 7, - }, { - .cfg_eint = 3, - .set_config = s5p64x0_gpio_setcfg_4bit_rbank, - }, { - .cfg_eint = 0, - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, - }, { - .cfg_eint = 2, - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, - }, { - .cfg_eint = 3, - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, - }, -}; - -static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { - { - .base = S5P64X0_GPA_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6440_GPA(0), - .ngpio = S5P6440_GPIO_A_NR, - .label = "GPA", - }, - }, { - .base = S5P64X0_GPB_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6440_GPB(0), - .ngpio = S5P6440_GPIO_B_NR, - .label = "GPB", - }, - }, { - .base = S5P64X0_GPC_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6440_GPC(0), - .ngpio = S5P6440_GPIO_C_NR, - .label = "GPC", - }, - }, { - .base = S5P64X0_GPG_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6440_GPG(0), - .ngpio = S5P6440_GPIO_G_NR, - .label = "GPG", - }, - }, -}; - -static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { - { - .base = S5P64X0_GPH_BASE + 0x4, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6440_GPH(0), - .ngpio = S5P6440_GPIO_H_NR, - .label = "GPH", - }, - }, -}; - -static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { - { - .base = S5P64X0_GPR_BASE + 0x4, - .config = &s5p64x0_gpio_cfgs[2], - .chip = { - .base = S5P6440_GPR(0), - .ngpio = S5P6440_GPIO_R_NR, - .label = "GPR", - }, - }, -}; - -static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { - { - .base = S5P64X0_GPF_BASE, - .config = &s5p64x0_gpio_cfgs[5], - .chip = { - .base = S5P6440_GPF(0), - .ngpio = S5P6440_GPIO_F_NR, - .label = "GPF", - }, - }, { - .base = S5P64X0_GPI_BASE, - .config = &s5p64x0_gpio_cfgs[3], - .chip = { - .base = S5P6440_GPI(0), - .ngpio = S5P6440_GPIO_I_NR, - .label = "GPI", - }, - }, { - .base = S5P64X0_GPJ_BASE, - .config = &s5p64x0_gpio_cfgs[3], - .chip = { - .base = S5P6440_GPJ(0), - .ngpio = S5P6440_GPIO_J_NR, - .label = "GPJ", - }, - }, { - .base = S5P64X0_GPN_BASE, - .config = &s5p64x0_gpio_cfgs[4], - .chip = { - .base = S5P6440_GPN(0), - .ngpio = S5P6440_GPIO_N_NR, - .label = "GPN", - }, - }, { - .base = S5P64X0_GPP_BASE, - .config = &s5p64x0_gpio_cfgs[5], - .chip = { - .base = S5P6440_GPP(0), - .ngpio = S5P6440_GPIO_P_NR, - .label = "GPP", - }, - }, -}; - -static struct s3c_gpio_chip s5p6450_gpio_4bit[] = { - { - .base = S5P64X0_GPA_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPA(0), - .ngpio = S5P6450_GPIO_A_NR, - .label = "GPA", - }, - }, { - .base = S5P64X0_GPB_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPB(0), - .ngpio = S5P6450_GPIO_B_NR, - .label = "GPB", - }, - }, { - .base = S5P64X0_GPC_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPC(0), - .ngpio = S5P6450_GPIO_C_NR, - .label = "GPC", - }, - }, { - .base = S5P6450_GPD_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPD(0), - .ngpio = S5P6450_GPIO_D_NR, - .label = "GPD", - }, - }, { - .base = S5P6450_GPK_BASE, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPK(0), - .ngpio = S5P6450_GPIO_K_NR, - .label = "GPK", - }, - }, -}; - -static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = { - { - .base = S5P64X0_GPG_BASE + 0x4, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPG(0), - .ngpio = S5P6450_GPIO_G_NR, - .label = "GPG", - }, - }, { - .base = S5P64X0_GPH_BASE + 0x4, - .config = &s5p64x0_gpio_cfgs[1], - .chip = { - .base = S5P6450_GPH(0), - .ngpio = S5P6450_GPIO_H_NR, - .label = "GPH", - }, - }, -}; - -static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = { - { - .base = S5P64X0_GPR_BASE + 0x4, - .config = &s5p64x0_gpio_cfgs[2], - .chip = { - .base = S5P6450_GPR(0), - .ngpio = S5P6450_GPIO_R_NR, - .label = "GPR", - }, - }, -}; - -static struct s3c_gpio_chip s5p6450_gpio_2bit[] = { - { - .base = S5P64X0_GPF_BASE, - .config = &s5p64x0_gpio_cfgs[5], - .chip = { - .base = S5P6450_GPF(0), - .ngpio = S5P6450_GPIO_F_NR, - .label = "GPF", - }, - }, { - .base = S5P64X0_GPI_BASE, - .config = &s5p64x0_gpio_cfgs[3], - .chip = { - .base = S5P6450_GPI(0), - .ngpio = S5P6450_GPIO_I_NR, - .label = "GPI", - }, - }, { - .base = S5P64X0_GPJ_BASE, - .config = &s5p64x0_gpio_cfgs[3], - .chip = { - .base = S5P6450_GPJ(0), - .ngpio = S5P6450_GPIO_J_NR, - .label = "GPJ", - }, - }, { - .base = S5P64X0_GPN_BASE, - .config = &s5p64x0_gpio_cfgs[4], - .chip = { - .base = S5P6450_GPN(0), - .ngpio = S5P6450_GPIO_N_NR, - .label = "GPN", - }, - }, { - .base = S5P64X0_GPP_BASE, - .config = &s5p64x0_gpio_cfgs[5], - .chip = { - .base = S5P6450_GPP(0), - .ngpio = S5P6450_GPIO_P_NR, - .label = "GPP", - }, - }, { - .base = S5P6450_GPQ_BASE, - .config = &s5p64x0_gpio_cfgs[4], - .chip = { - .base = S5P6450_GPQ(0), - .ngpio = S5P6450_GPIO_Q_NR, - .label = "GPQ", - }, - }, { - .base = S5P6450_GPS_BASE, - .config = &s5p64x0_gpio_cfgs[5], - .chip = { - .base = S5P6450_GPS(0), - .ngpio = S5P6450_GPIO_S_NR, - .label = "GPS", - }, - }, -}; - -void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chipcfg++) { - if (!chipcfg->set_config) - chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; - if (!chipcfg->get_config) - chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit; - if (!chipcfg->set_pull) - chipcfg->set_pull = s3c_gpio_setpull_updown; - if (!chipcfg->get_pull) - chipcfg->get_pull = s3c_gpio_getpull_updown; - } -} - -static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input; - chip->chip.direction_output = - s5p64x0_gpiolib_rbank_4bit2_output; - s3c_gpiolib_add(chip); - } -} - -static int __init s5p64x0_gpiolib_init(void) -{ - s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, - ARRAY_SIZE(s5p64x0_gpio_cfgs)); - - if (soc_is_s5p6450()) { - samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, - ARRAY_SIZE(s5p6450_gpio_2bit)); - - samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit, - ARRAY_SIZE(s5p6450_gpio_4bit)); - - samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2, - ARRAY_SIZE(s5p6450_gpio_4bit2)); - - s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2, - ARRAY_SIZE(s5p6450_gpio_rbank_4bit2)); - } else { - samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit, - ARRAY_SIZE(s5p6440_gpio_2bit)); - - samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, - ARRAY_SIZE(s5p6440_gpio_4bit)); - - samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, - ARRAY_SIZE(s5p6440_gpio_4bit2)); - - s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, - ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); - } - - return 0; -} -core_initcall(s5p64x0_gpiolib_init); diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/i2c.h index 887d25209e8..1e5bb4ea200 100644 --- a/arch/arm/mach-s5p64x0/include/mach/i2c.h +++ b/arch/arm/mach-s5p64x0/i2c.h @@ -1,5 +1,4 @@ -/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h - * +/* * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com * diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h index 4aaebdace55..d60397d1ff4 100644 --- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h +++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h @@ -13,7 +13,6 @@ #ifndef __ASM_ARCH_REGS_IRQ_H #define __ASM_ARCH_REGS_IRQ_H __FILE__ -#include <asm/hardware/vic.h> #include <mach/map.h> #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5p64x0/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h deleted file mode 100644 index 00aa7f1d8e5..00000000000 --- a/arch/arm/mach-s5p64x0/include/mach/tick.h +++ /dev/null @@ -1,29 +0,0 @@ -/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S5P64X0 - Timer tick support definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TICK_H -#define __ASM_ARCH_TICK_H __FILE__ - -static inline u32 s3c24xx_ostimer_pending(void) -{ - u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); - return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); -} - -#define TICK_MAX (0xffffffff) - -#endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h index 1608faf870f..19e0d64d78c 100644 --- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h +++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h @@ -116,33 +116,6 @@ static inline void flush(void) *((volatile unsigned int __force *)(ad)) = (d); \ } while (0) -/* - * CONFIG_S3C_BOOT_WATCHDOG - * - * Simple boot-time watchdog setup, to reboot the system if there is - * any problem with the boot process - */ - -#ifdef CONFIG_S3C_BOOT_WATCHDOG - -#define WDOG_COUNT (0xff00) - -static inline void arch_decomp_wdog(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); -} - -static void arch_decomp_wdog_start(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTDAT); - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); -} - -#else -#define arch_decomp_wdog_start() -#define arch_decomp_wdog() -#endif #ifdef CONFIG_S3C_BOOT_ERROR_RESET @@ -192,7 +165,6 @@ static void arch_decomp_setup(void) */ arch_detect_cpu(); - arch_decomp_wdog_start(); /* * Enable the UART FIFOs if they where not enabled and our diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 1af823558c6..e23723a5a21 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -29,7 +29,6 @@ #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/irq.h> @@ -38,7 +37,6 @@ #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/i2c.h> #include <mach/regs-gpio.h> #include <plat/regs-serial.h> @@ -56,6 +54,7 @@ #include <plat/sdhci.h> #include "common.h" +#include "i2c.h" #define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -272,9 +271,8 @@ MACHINE_START(SMDK6440, "SMDK6440") .atag_offset = 0x100, .init_irq = s5p6440_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdk6440_map_io, .init_machine = smdk6440_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .restart = s5p64x0_restart, MACHINE_END diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index 62526ccf6b7..ca10963a959 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -29,7 +29,6 @@ #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/irq.h> @@ -38,7 +37,6 @@ #include <mach/hardware.h> #include <mach/map.h> #include <mach/regs-clock.h> -#include <mach/i2c.h> #include <mach/regs-gpio.h> #include <plat/regs-serial.h> @@ -56,6 +54,7 @@ #include <plat/sdhci.h> #include "common.h" +#include "i2c.h" #define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -291,9 +290,8 @@ MACHINE_START(SMDK6450, "SMDK6450") .atag_offset = 0x100, .init_irq = s5p6450_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdk6450_map_io, .init_machine = smdk6450_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .restart = s5p64x0_restart, MACHINE_END diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c index 9cba18bfe47..97c2a08ad49 100644 --- a/arch/arm/mach-s5p64x0/pm.c +++ b/arch/arm/mach-s5p64x0/pm.c @@ -103,8 +103,8 @@ static int s5p64x0_cpu_suspend(unsigned long arg) "mcr p15, 0, %0, c7, c10, 4\n\t" "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp)); - /* we should never get past here */ - panic("sleep resumed to originator?"); + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ } /* mapping of interrupts to parts of the wakeup mask */ diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c index a32edc545e6..569b76ac98c 100644 --- a/arch/arm/mach-s5p64x0/setup-i2c0.c +++ b/arch/arm/mach-s5p64x0/setup-i2c0.c @@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */ #include <plat/gpio-cfg.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/i2c.h> +#include "i2c.h" void s5p6440_i2c0_cfg_gpio(struct platform_device *dev) { diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c index ca2c5c7f8aa..867374e6d0b 100644 --- a/arch/arm/mach-s5p64x0/setup-i2c1.c +++ b/arch/arm/mach-s5p64x0/setup-i2c1.c @@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */ #include <plat/gpio-cfg.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/i2c.h> +#include "i2c.h" void s5p6440_i2c1_cfg_gpio(struct platform_device *dev) { diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h index 4d9036d0f28..761627897f3 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h @@ -14,6 +14,5 @@ #define __ASM_ARCH_REGS_IRQ_H __FILE__ #include <mach/map.h> -#include <asm/hardware/vic.h> #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h index 20f68730ed1..0af8e41230e 100644 --- a/arch/arm/mach-s5pc100/include/mach/tick.h +++ b/arch/arm/mach-s5pc100/include/mach/tick.h @@ -15,6 +15,8 @@ #ifndef __ASM_ARCH_TICK_H #define __ASM_ARCH_TICK_H __FILE__ +#include <linux/irqchip/arm-vic.h> + /* note, the timer interrutps turn up in 2 places, the vic and then * the timer block. We take the VIC as the base at the moment. */ diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 9abe95e806a..185a1958389 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -25,7 +25,6 @@ #include <linux/input.h> #include <linux/pwm_backlight.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -254,9 +253,8 @@ MACHINE_START(SMDKC100, "SMDKC100") /* Maintainer: Byungho Min <bhmin@samsung.com> */ .atag_offset = 0x100, .init_irq = s5pc100_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdkc100_map_io, .init_machine = smdkc100_machine_init, - .timer = &s3c24xx_timer, + .init_time = s3c24xx_timer_init, .restart = s5pc100_restart, MACHINE_END diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index addfb165c13..2d67361ef43 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c @@ -18,7 +18,8 @@ #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> -#include <mach/regs-audss.h> + +#define S5PV210_AUDSS_INT_MEM (0xC0000000) static int s5pv210_cfg_i2s(struct platform_device *pdev) { diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h deleted file mode 100644 index eacc1f79080..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/regs-audss.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-s5pv210/include/mach/regs-audss.h - * - * Copyright (c) 2011 Samsung Electronics - * http://www.samsung.com - * - * S5PV210 Audio SubSystem clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_REGS_AUDSS_H -#define __PLAT_REGS_AUDSS_H __FILE__ - -#define S5PV210_AUDSS_INT_MEM (0xC0000000) - -#endif /* _PLAT_REGS_AUDSS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h index 5c3b104a7c8..d8bc1e6c7aa 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h @@ -13,7 +13,6 @@ #ifndef __ASM_ARCH_REGS_IRQ_H #define __ASM_ARCH_REGS_IRQ_H __FILE__ -#include <asm/hardware/vic.h> #include <mach/map.h> #endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-sys.h b/arch/arm/mach-s5pv210/include/mach/regs-sys.h deleted file mode 100644 index cccb1eddaa3..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/regs-sys.h +++ /dev/null @@ -1,15 +0,0 @@ -/* arch/arm/mach-s5pv210/include/mach/regs-sys.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5PV210 - System registers definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C) -#define S5PV210_USB_PHY0_EN (1 << 0) -#define S5PV210_USB_PHY1_EN (1 << 1) diff --git a/arch/arm/mach-s5pv210/include/mach/tick.h b/arch/arm/mach-s5pv210/include/mach/tick.h deleted file mode 100644 index 7993b3603cc..00000000000 --- a/arch/arm/mach-s5pv210/include/mach/tick.h +++ /dev/null @@ -1,26 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/tick.h - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Based on arch/arm/mach-s3c6400/include/mach/tick.h - * - * S5PV210 - Timer tick support definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_TICK_H -#define __ASM_ARCH_TICK_H __FILE__ - -static inline u32 s3c24xx_ostimer_pending(void) -{ - u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); - return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); -} - -#define TICK_MAX (0xffffffff) - -#endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h index 08ff2fda1fb..ef977ea8546 100644 --- a/arch/arm/mach-s5pv210/include/mach/uncompress.h +++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h @@ -19,6 +19,8 @@ static void arch_detect_cpu(void) { /* we do not need to do any cpu detection here at the moment. */ + fifo_mask = S5PV210_UFSTAT_TXMASK; + fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT; } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index ee9fa5c2ef2..11900a8e88a 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -22,7 +22,6 @@ #include <linux/input.h> #include <linux/gpio.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> @@ -685,9 +684,8 @@ MACHINE_START(AQUILA, "Aquila") Kyungmin Park <kyungmin.park@samsung.com> */ .atag_offset = 0x100, .init_irq = s5pv210_init_irq, - .handle_irq = vic_handle_irq, .map_io = aquila_map_io, .init_machine = aquila_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .restart = s5pv210_restart, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index c72b31078c9..57048159174 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -29,7 +29,6 @@ #include <linux/interrupt.h> #include <linux/platform_data/s3c-hsotg.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> @@ -972,10 +971,9 @@ MACHINE_START(GONI, "GONI") /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */ .atag_offset = 0x100, .init_irq = s5pv210_init_irq, - .handle_irq = vic_handle_irq, .map_io = goni_map_io, .init_machine = goni_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .reserve = &goni_reserve, .restart = s5pv210_restart, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index f1f3bd37ecd..28bd0248a3e 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c @@ -15,7 +15,6 @@ #include <linux/i2c.h> #include <linux/device.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> @@ -152,10 +151,9 @@ MACHINE_START(SMDKC110, "SMDKC110") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ .atag_offset = 0x100, .init_irq = s5pv210_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdkc110_map_io, .init_machine = smdkc110_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .restart = s5pv210_restart, .reserve = &smdkc110_reserve, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 6bc8404bf67..3c73f36869b 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -21,7 +21,6 @@ #include <linux/pwm_backlight.h> #include <linux/platform_data/s3c-hsotg.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> @@ -328,10 +327,9 @@ MACHINE_START(SMDKV210, "SMDKV210") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ .atag_offset = 0x100, .init_irq = s5pv210_init_irq, - .handle_irq = vic_handle_irq, .map_io = smdkv210_map_io, .init_machine = smdkv210_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .restart = s5pv210_restart, .reserve = &smdkv210_reserve, MACHINE_END diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c index 18785cb5e1e..2d4c5531819 100644 --- a/arch/arm/mach-s5pv210/mach-torbreck.c +++ b/arch/arm/mach-s5pv210/mach-torbreck.c @@ -14,7 +14,6 @@ #include <linux/init.h> #include <linux/serial_core.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/setup.h> @@ -129,9 +128,8 @@ MACHINE_START(TORBRECK, "TORBRECK") /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */ .atag_offset = 0x100, .init_irq = s5pv210_init_irq, - .handle_irq = vic_handle_irq, .map_io = torbreck_map_io, .init_machine = torbreck_machine_init, - .timer = &s5p_timer, + .init_time = s5p_timer_init, .restart = s5pv210_restart, MACHINE_END diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 736bfb103cb..2b68a67b6e9 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -104,8 +104,8 @@ static int s5pv210_cpu_suspend(unsigned long arg) "mcr p15, 0, %0, c7, c10, 4\n\t" "wfi" : : "r" (tmp)); - /* we should never get past here */ - panic("sleep resumed to originator?"); + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ } static void s5pv210_pm_prepare(void) diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c index be39cf4aa91..356a0900af0 100644 --- a/arch/arm/mach-s5pv210/setup-usb-phy.c +++ b/arch/arm/mach-s5pv210/setup-usb-phy.c @@ -12,12 +12,17 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/platform_device.h> + #include <mach/map.h> -#include <mach/regs-sys.h> + #include <plat/cpu.h> #include <plat/regs-usb-hsotg-phy.h> #include <plat/usb-phy.h> +#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C) +#define S5PV210_USB_PHY0_EN (1 << 0) +#define S5PV210_USB_PHY1_EN (1 << 1) + static int s5pv210_usb_otgphy_init(struct platform_device *pdev) { struct clk *xusbxti; diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index 9a23739f702..e838ba27e44 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -16,6 +16,7 @@ #include <linux/ioport.h> #include <linux/platform_data/sa11x0-serial.h> #include <linux/serial_core.h> +#include <linux/platform_device.h> #include <linux/mfd/ucb1x00.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> @@ -621,7 +622,7 @@ MACHINE_START(ASSABET, "Intel-Assabet") .map_io = assabet_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = assabet_init, .init_late = sa11x0_init_late, #ifdef CONFIG_SA1111 diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index b2dadf3ea3d..63361b6d04e 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -336,7 +336,7 @@ MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4") .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, .init_late = sa11x0_init_late, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, #ifdef CONFIG_SA1111 .dma_zone_size = SZ_1M, #endif diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 304bca4a07c..2d25ececb41 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -174,7 +174,7 @@ MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube") .map_io = cerf_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = cerf_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = cerf_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 45f424f5fca..612a4568977 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -399,7 +399,7 @@ MACHINE_START(COLLIE, "Sharp-Collie") .map_io = collie_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = collie_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h index a5b7c13da3e..2abc6a1f6e8 100644 --- a/arch/arm/mach-sa1100/generic.h +++ b/arch/arm/mach-sa1100/generic.h @@ -4,9 +4,7 @@ * Author: Nicolas Pitre */ -struct sys_timer; - -extern struct sys_timer sa1100_timer; +extern void sa1100_timer_init(void); extern void __init sa1100_map_io(void); extern void __init sa1100_init_irq(void); extern void __init sa1100_init_gpio(void); diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c index e1571eab08a..b8f2b151539 100644 --- a/arch/arm/mach-sa1100/h3100.c +++ b/arch/arm/mach-sa1100/h3100.c @@ -108,7 +108,7 @@ MACHINE_START(H3100, "Compaq iPAQ H3100") .map_io = h3100_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = h3100_mach_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index ba7a2901ab8..b8dc5bd2262 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c @@ -158,7 +158,7 @@ MACHINE_START(H3600, "Compaq iPAQ H3600") .map_io = h3600_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = h3600_mach_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c index d005939c41f..643d5f2d9af 100644 --- a/arch/arm/mach-sa1100/hackkit.c +++ b/arch/arm/mach-sa1100/hackkit.c @@ -229,7 +229,7 @@ MACHINE_START(HACKKIT, "HackKit Cpu Board") .map_io = hackkit_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = hackkit_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h index 5cf71da60e4..73093dc8982 100644 --- a/arch/arm/mach-sa1100/include/mach/uncompress.h +++ b/arch/arm/mach-sa1100/include/mach/uncompress.h @@ -49,4 +49,3 @@ static inline void flush(void) * Nothing to do for these */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 35cfc428b4d..c0b1f5bafae 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c @@ -346,7 +346,7 @@ MACHINE_START(JORNADA720, "HP Jornada 720") .map_io = jornada720_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = jornada720_mach_init, .init_late = sa11x0_init_late, #ifdef CONFIG_SA1111 diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c index f69f78fc3dd..51b0eb52c01 100644 --- a/arch/arm/mach-sa1100/lart.c +++ b/arch/arm/mach-sa1100/lart.c @@ -24,9 +24,6 @@ #include "generic.h" - -#warning "include/asm/arch-sa1100/ide.h needs fixing for lart" - static struct mcp_plat_data lart_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, @@ -174,6 +171,6 @@ MACHINE_START(LART, "LART") .init_irq = sa1100_init_irq, .init_machine = lart_init, .init_late = sa11x0_init_late, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c index 102e08f7b10..f1cb3784d52 100644 --- a/arch/arm/mach-sa1100/nanoengine.c +++ b/arch/arm/mach-sa1100/nanoengine.c @@ -110,7 +110,7 @@ MACHINE_START(NANOENGINE, "BSE nanoEngine") .map_io = nanoengine_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = nanoengine_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index c51bb63f90f..091261878ef 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -133,7 +133,7 @@ MACHINE_START(PLEB, "PLEB") .map_io = pleb_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = pleb_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index 6460d25fbb8..c8866bce738 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c @@ -102,7 +102,7 @@ MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)") .map_io = shannon_map_io, .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .init_machine = shannon_init, .init_late = sa11x0_init_late, .restart = sa11x0_restart, diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 6d65f65fcb2..bcbc94540e4 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -396,6 +396,6 @@ MACHINE_START(SIMPAD, "Simpad") .nr_irqs = SA1100_NR_IRQS, .init_irq = sa1100_init_irq, .init_late = sa11x0_init_late, - .timer = &sa1100_timer, + .init_time = sa1100_timer_init, .restart = sa11x0_restart, MACHINE_END diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 80702c9ecc7..a59a13a665a 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -69,46 +69,10 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) } } -static struct clock_event_device ckevt_sa1100_osmr0 = { - .name = "osmr0", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = sa1100_osmr0_set_next_event, - .set_mode = sa1100_osmr0_set_mode, -}; - -static struct irqaction sa1100_timer_irq = { - .name = "ost0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = sa1100_ost0_interrupt, - .dev_id = &ckevt_sa1100_osmr0, -}; - -static void __init sa1100_timer_init(void) -{ - writel_relaxed(0, OIER); - writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); - - setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); - - clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4); - ckevt_sa1100_osmr0.max_delta_ns = - clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); - ckevt_sa1100_osmr0.min_delta_ns = - clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; - ckevt_sa1100_osmr0.cpumask = cpumask_of(0); - - setup_irq(IRQ_OST0, &sa1100_timer_irq); - - clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, - clocksource_mmio_readl_up); - clockevents_register_device(&ckevt_sa1100_osmr0); -} - #ifdef CONFIG_PM unsigned long osmr[4], oier; -static void sa1100_timer_suspend(void) +static void sa1100_timer_suspend(struct clock_event_device *cedev) { osmr[0] = readl_relaxed(OSMR0); osmr[1] = readl_relaxed(OSMR1); @@ -117,7 +81,7 @@ static void sa1100_timer_suspend(void) oier = readl_relaxed(OIER); } -static void sa1100_timer_resume(void) +static void sa1100_timer_resume(struct clock_event_device *cedev) { writel_relaxed(0x0f, OSSR); writel_relaxed(osmr[0], OSMR0); @@ -136,8 +100,36 @@ static void sa1100_timer_resume(void) #define sa1100_timer_resume NULL #endif -struct sys_timer sa1100_timer = { - .init = sa1100_timer_init, +static struct clock_event_device ckevt_sa1100_osmr0 = { + .name = "osmr0", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 200, + .set_next_event = sa1100_osmr0_set_next_event, + .set_mode = sa1100_osmr0_set_mode, .suspend = sa1100_timer_suspend, .resume = sa1100_timer_resume, }; + +static struct irqaction sa1100_timer_irq = { + .name = "ost0", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = sa1100_ost0_interrupt, + .dev_id = &ckevt_sa1100_osmr0, +}; + +void __init sa1100_timer_init(void) +{ + writel_relaxed(0, OIER); + writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); + + setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); + + ckevt_sa1100_osmr0.cpumask = cpumask_of(0); + + setup_irq(IRQ_OST0, &sa1100_timer_irq); + + clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, + clocksource_mmio_readl_up); + clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, + MIN_OSCR_DELTA * 2, 0x7fffffff); +} diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index 9ad2e9737fb..b63dec84819 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c @@ -128,10 +128,6 @@ static void __init shark_timer_init(void) setup_irq(IRQ_TIMER, &shark_timer_irq); } -static struct sys_timer shark_timer = { - .init = shark_timer_init, -}; - static void shark_init_early(void) { disable_hlt(); @@ -142,7 +138,7 @@ MACHINE_START(SHARK, "Shark") .atag_offset = 0x3000, .init_early = shark_init_early, .init_irq = shark_init_irq, - .timer = &shark_timer, + .init_time = shark_timer_init, .dma_zone_size = SZ_4M, .restart = shark_restart, MACHINE_END diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h index 22ccab4c3c5..a168435aecc 100644 --- a/arch/arm/mach-shark/include/mach/uncompress.h +++ b/arch/arm/mach-shark/include/mach/uncompress.h @@ -48,4 +48,3 @@ static void putr() * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c index 032d10817e7..705bc63c798 100644 --- a/arch/arm/mach-shmobile/board-ag5evm.c +++ b/arch/arm/mach-shmobile/board-ag5evm.c @@ -40,6 +40,7 @@ #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> #include <linux/sh_clk.h> +#include <linux/irqchip/arm-gic.h> #include <video/sh_mobile_lcdc.h> #include <video/sh_mipi_dsi.h> #include <sound/sh_fsi.h> @@ -49,7 +50,6 @@ #include <mach/common.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/traps.h> @@ -668,8 +668,7 @@ MACHINE_START(AG5EVM, "ag5evm") .init_early = sh73a0_add_early_devices, .nr_irqs = NR_IRQS_LEGACY, .init_irq = sh73a0_init_irq, - .handle_irq = gic_handle_irq, .init_machine = ag5evm_init, .init_late = shmobile_init_late, - .timer = &shmobile_timer, + .init_time = sh73a0_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 99ef190d090..2928cd68680 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -657,14 +657,8 @@ static struct platform_device lcdc_device = { /* FSI */ #define IRQ_FSI evt2irq(0x1840) static struct sh_fsi_platform_info fsi_info = { - .port_a = { - .flags = SH_FSI_BRS_INV, - }, .port_b = { - .flags = SH_FSI_BRS_INV | - SH_FSI_BRM_INV | - SH_FSI_LRS_INV | - SH_FSI_CLK_CPG | + .flags = SH_FSI_CLK_CPG | SH_FSI_FMT_SPDIF, }, }; @@ -692,21 +686,21 @@ static struct platform_device fsi_device = { }, }; -static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = { - .fmt = SND_SOC_DAIFMT_LEFT_J, - .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM, - .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS, - .sysclk = 11289600, -}; - static struct asoc_simple_card_info fsi2_ak4643_info = { .name = "AK4643", .card = "FSI2A-AK4643", - .cpu_dai = "fsia-dai", .codec = "ak4642-codec.0-0013", .platform = "sh_fsi2", - .codec_dai = "ak4642-hifi", - .init = &fsi2_ak4643_init_info, + .daifmt = SND_SOC_DAIFMT_LEFT_J, + .cpu_dai = { + .name = "fsia-dai", + .fmt = SND_SOC_DAIFMT_CBS_CFS, + }, + .codec_dai = { + .name = "ak4642-hifi", + .fmt = SND_SOC_DAIFMT_CBM_CFM, + .sysclk = 11289600, + }, }; static struct platform_device fsi_ak4643_device = { @@ -815,18 +809,18 @@ static struct platform_device lcdc1_device = { }, }; -static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = { - .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM, -}; - static struct asoc_simple_card_info fsi2_hdmi_info = { .name = "HDMI", .card = "FSI2B-HDMI", - .cpu_dai = "fsib-dai", .codec = "sh-mobile-hdmi", .platform = "sh_fsi2", - .codec_dai = "sh_mobile_hdmi-hifi", - .init = &fsi2_hdmi_init_info, + .cpu_dai = { + .name = "fsib-dai", + .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF, + }, + .codec_dai = { + .name = "sh_mobile_hdmi-hifi", + }, }; static struct platform_device fsi_hdmi_device = { @@ -1350,5 +1344,5 @@ MACHINE_START(AP4EVB, "ap4evb") .handle_irq = shmobile_handle_irq_intc, .init_machine = ap4evb_init, .init_late = sh7372_pm_init_late, - .timer = &shmobile_timer, + .init_time = sh7372_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 5353adf6b82..6bcf3cbd922 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -806,21 +806,21 @@ static struct platform_device fsi_device = { }; /* FSI-WM8978 */ -static struct asoc_simple_dai_init_info fsi_wm8978_init_info = { - .fmt = SND_SOC_DAIFMT_I2S, - .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF, - .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS, - .sysclk = 12288000, -}; - static struct asoc_simple_card_info fsi_wm8978_info = { .name = "wm8978", .card = "FSI2A-WM8978", - .cpu_dai = "fsia-dai", .codec = "wm8978.0-001a", .platform = "sh_fsi2", - .codec_dai = "wm8978-hifi", - .init = &fsi_wm8978_init_info, + .daifmt = SND_SOC_DAIFMT_I2S, + .cpu_dai = { + .name = "fsia-dai", + .fmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF, + }, + .codec_dai = { + .name = "wm8978-hifi", + .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF, + .sysclk = 12288000, + }, }; static struct platform_device fsi_wm8978_device = { @@ -832,18 +832,18 @@ static struct platform_device fsi_wm8978_device = { }; /* FSI-HDMI */ -static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = { - .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM, -}; - static struct asoc_simple_card_info fsi2_hdmi_info = { .name = "HDMI", .card = "FSI2B-HDMI", - .cpu_dai = "fsib-dai", .codec = "sh-mobile-hdmi", .platform = "sh_fsi2", - .codec_dai = "sh_mobile_hdmi-hifi", - .init = &fsi2_hdmi_init_info, + .cpu_dai = { + .name = "fsib-dai", + .fmt = SND_SOC_DAIFMT_CBM_CFM, + }, + .codec_dai = { + .name = "sh_mobile_hdmi-hifi", + }, }; static struct platform_device fsi_hdmi_device = { @@ -1192,9 +1192,6 @@ static void __init eva_earlytimer_init(void) static void __init eva_add_early_devices(void) { r8a7740_add_early_devices(); - - /* override timer setup with board-specific code */ - shmobile_timer.init = eva_earlytimer_init; } #define RESCNT2 IOMEM(0xe6188020) @@ -1216,7 +1213,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") .handle_irq = shmobile_handle_irq_intc, .init_machine = eva_init, .init_late = shmobile_init_late, - .timer = &shmobile_timer, + .init_time = eva_earlytimer_init, .dt_compat = eva_boards_compat_dt, .restart = eva_restart, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c index cb8c994e143..331b7ce4edd 100644 --- a/arch/arm/mach-shmobile/board-bonito.c +++ b/arch/arm/mach-shmobile/board-bonito.c @@ -499,9 +499,6 @@ static void __init bonito_earlytimer_init(void) static void __init bonito_add_early_devices(void) { r8a7740_add_early_devices(); - - /* override timer setup with board-specific code */ - shmobile_timer.init = bonito_earlytimer_init; } MACHINE_START(BONITO, "bonito") @@ -511,5 +508,5 @@ MACHINE_START(BONITO, "bonito") .handle_irq = shmobile_handle_irq_intc, .init_machine = bonito_init, .init_late = shmobile_init_late, - .timer = &shmobile_timer, + .init_time = bonito_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c index bf88f9a8b7a..d759a9c2b9e 100644 --- a/arch/arm/mach-shmobile/board-kota2.c +++ b/arch/arm/mach-shmobile/board-kota2.c @@ -35,6 +35,7 @@ #include <linux/input/sh_keysc.h> #include <linux/gpio_keys.h> #include <linux/leds.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/leds-renesas-tpu.h> #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> @@ -47,7 +48,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include <asm/traps.h> @@ -550,8 +550,7 @@ MACHINE_START(KOTA2, "kota2") .init_early = sh73a0_add_early_devices, .nr_irqs = NR_IRQS_LEGACY, .init_irq = sh73a0_init_irq, - .handle_irq = gic_handle_irq, .init_machine = kota2_init, .init_late = shmobile_init_late, - .timer = &shmobile_timer, + .init_time = sh73a0_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c index b52bc0d1273..c254782aa72 100644 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ b/arch/arm/mach-shmobile/board-kzm9d.c @@ -28,7 +28,6 @@ #include <mach/emev2.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> /* Dummy supplies, where voltage doesn't matter */ static struct regulator_consumer_supply dummy_supplies[] = { @@ -89,9 +88,8 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d") .init_early = emev2_add_early_devices, .nr_irqs = NR_IRQS_LEGACY, .init_irq = emev2_init_irq, - .handle_irq = gic_handle_irq, .init_machine = kzm9d_add_standard_devices, .init_late = shmobile_init_late, - .timer = &shmobile_timer, + .init_time = shmobile_timer_init, .dt_compat = kzm9d_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index c02448d6847..5394d804a71 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -25,6 +25,7 @@ #include <linux/i2c.h> #include <linux/i2c/pcf857x.h> #include <linux/input.h> +#include <linux/irqchip/arm-gic.h> #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> #include <linux/mmc/sh_mobile_sdhi.h> @@ -42,7 +43,6 @@ #include <mach/sh73a0.h> #include <mach/common.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <video/sh_mobile_lcdc.h> @@ -525,21 +525,21 @@ static struct platform_device fsi_device = { }, }; -static struct asoc_simple_dai_init_info fsi2_ak4648_init_info = { - .fmt = SND_SOC_DAIFMT_LEFT_J, - .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM, - .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS, - .sysclk = 11289600, -}; - static struct asoc_simple_card_info fsi2_ak4648_info = { .name = "AK4648", .card = "FSI2A-AK4648", - .cpu_dai = "fsia-dai", .codec = "ak4642-codec.0-0012", .platform = "sh_fsi2", - .codec_dai = "ak4642-hifi", - .init = &fsi2_ak4648_init_info, + .daifmt = SND_SOC_DAIFMT_LEFT_J, + .cpu_dai = { + .name = "fsia-dai", + .fmt = SND_SOC_DAIFMT_CBS_CFS, + }, + .codec_dai = { + .name = "ak4642-hifi", + .fmt = SND_SOC_DAIFMT_CBM_CFM, + .sysclk = 11289600, + }, }; static struct platform_device fsi_ak4648_device = { @@ -792,10 +792,9 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g") .init_early = sh73a0_add_early_devices, .nr_irqs = NR_IRQS_LEGACY, .init_irq = sh73a0_init_irq, - .handle_irq = gic_handle_irq, .init_machine = kzm_init, .init_late = shmobile_init_late, - .timer = &shmobile_timer, + .init_time = sh73a0_earlytimer_init, .restart = kzm9g_restart, .dt_compat = kzm9g_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 2fed62f6604..e2fafca9432 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -502,18 +502,18 @@ static struct platform_device hdmi_lcdc_device = { }, }; -static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = { - .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM, -}; - static struct asoc_simple_card_info fsi2_hdmi_info = { .name = "HDMI", .card = "FSI2B-HDMI", - .cpu_dai = "fsib-dai", .codec = "sh-mobile-hdmi", .platform = "sh_fsi2", - .codec_dai = "sh_mobile_hdmi-hifi", - .init = &fsi2_hdmi_init_info, + .cpu_dai = { + .name = "fsib-dai", + .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF, + }, + .codec_dai = { + .name = "sh_mobile_hdmi-hifi", + }, }; static struct platform_device fsi_hdmi_device = { @@ -858,16 +858,12 @@ static struct platform_device leds_device = { #define IRQ_FSI evt2irq(0x1840) static struct sh_fsi_platform_info fsi_info = { .port_a = { - .flags = SH_FSI_BRS_INV, .tx_id = SHDMA_SLAVE_FSIA_TX, .rx_id = SHDMA_SLAVE_FSIA_RX, }, .port_b = { - .flags = SH_FSI_BRS_INV | - SH_FSI_BRM_INV | - SH_FSI_LRS_INV | - SH_FSI_CLK_CPG | - SH_FSI_FMT_SPDIF, + .flags = SH_FSI_CLK_CPG | + SH_FSI_FMT_SPDIF, } }; @@ -896,21 +892,21 @@ static struct platform_device fsi_device = { }, }; -static struct asoc_simple_dai_init_info fsi2_ak4643_init_info = { - .fmt = SND_SOC_DAIFMT_LEFT_J, - .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM, - .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS, - .sysclk = 11289600, -}; - static struct asoc_simple_card_info fsi2_ak4643_info = { .name = "AK4643", .card = "FSI2A-AK4643", - .cpu_dai = "fsia-dai", .codec = "ak4642-codec.0-0013", .platform = "sh_fsi2", - .codec_dai = "ak4642-hifi", - .init = &fsi2_ak4643_init_info, + .daifmt = SND_SOC_DAIFMT_LEFT_J, + .cpu_dai = { + .name = "fsia-dai", + .fmt = SND_SOC_DAIFMT_CBS_CFS, + }, + .codec_dai = { + .name = "ak4642-hifi", + .fmt = SND_SOC_DAIFMT_CBM_CFM, + .sysclk = 11289600, + }, }; static struct platform_device fsi_ak4643_device = { @@ -1593,6 +1589,6 @@ DT_MACHINE_START(MACKEREL_DT, "mackerel") .handle_irq = shmobile_handle_irq_intc, .init_machine = mackerel_init, .init_late = sh7372_pm_init_late, - .timer = &shmobile_timer, + .init_time = sh7372_earlytimer_init, .dt_compat = mackerel_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 449f9289567..cdcb799e802 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -44,7 +44,6 @@ #include <mach/irqs.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <asm/traps.h> /* Fixed 3.3V regulator to be used by SDHI0 */ @@ -382,8 +381,7 @@ MACHINE_START(MARZEN, "marzen") .init_early = r8a7779_add_early_devices, .nr_irqs = NR_IRQS_LEGACY, .init_irq = r8a7779_init_irq, - .handle_irq = gic_handle_irq, .init_machine = marzen_init, .init_late = marzen_init_late, - .timer = &shmobile_timer, + .init_time = r8a7779_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index dfeca79e9e9..a57439eec11 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -2,7 +2,7 @@ #define __ARCH_MACH_COMMON_H extern void shmobile_earlytimer_init(void); -extern struct sys_timer shmobile_timer; +extern void shmobile_timer_init(void); extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, unsigned int mult, unsigned int div); struct twd_local_timer; @@ -20,6 +20,7 @@ extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); extern void sh7372_init_irq(void); extern void sh7372_map_io(void); +extern void sh7372_earlytimer_init(void); extern void sh7372_add_early_devices(void); extern void sh7372_add_standard_devices(void); extern void sh7372_clock_init(void); @@ -32,6 +33,7 @@ extern struct clk sh7372_extal2_clk; extern void sh73a0_init_irq(void); extern void sh73a0_map_io(void); +extern void sh73a0_earlytimer_init(void); extern void sh73a0_add_early_devices(void); extern void sh73a0_add_standard_devices(void); extern void sh73a0_clock_init(void); @@ -50,6 +52,7 @@ extern void r8a7740_pinmux_init(void); extern void r8a7779_init_irq(void); extern void r8a7779_map_io(void); +extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_clock_init(void); diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h index 0bd7556b138..f1aee56781e 100644 --- a/arch/arm/mach-shmobile/include/mach/uncompress.h +++ b/arch/arm/mach-shmobile/include/mach/uncompress.h @@ -16,6 +16,4 @@ static void arch_decomp_setup(void) { } -#define arch_decomp_wdog() - #endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index ef66f1a8aa2..8807c27f71f 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -22,10 +22,10 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/intc.h> #include <mach/r8a7779.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index f0c5e519060..978369973be 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -23,10 +23,10 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sh_intc.h> +#include <linux/irqchip/arm-gic.h> #include <mach/intc.h> #include <mach/irqs.h> #include <mach/sh73a0.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index ed8d2351915..1f958d7b0ba 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -12,7 +12,6 @@ */ #include <linux/init.h> #include <linux/smp.h> -#include <asm/hardware/gic.h> void __init shmobile_smp_init_cpus(unsigned int ncores) { @@ -26,6 +25,4 @@ void __init shmobile_smp_init_cpus(unsigned int ncores) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index a47beeb1828..47662a581c0 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -20,13 +20,14 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/platform_device.h> #include <linux/platform_data/gpio-em.h> #include <linux/of_platform.h> #include <linux/delay.h> #include <linux/input.h> #include <linux/io.h> -#include <linux/of_irq.h> +#include <linux/irqchip/arm-gic.h> #include <mach/hardware.h> #include <mach/common.h> #include <mach/emev2.h> @@ -35,7 +36,6 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/hardware/gic.h> static struct map_desc emev2_io_desc[] __initdata = { #ifdef CONFIG_SMP @@ -445,29 +445,18 @@ void __init emev2_add_standard_devices_dt(void) emev2_auxdata_lookup, NULL); } -static const struct of_device_id emev2_dt_irq_match[] = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {}, -}; - static const char *emev2_boards_compat_dt[] __initdata = { "renesas,emev2", NULL, }; -void __init emev2_init_irq_dt(void) -{ - of_irq_init(emev2_dt_irq_match); -} - DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") .smp = smp_ops(emev2_smp_ops), .init_early = emev2_init_delay, .nr_irqs = NR_IRQS_LEGACY, - .init_irq = emev2_init_irq_dt, - .handle_irq = gic_handle_irq, + .init_irq = irqchip_init, .init_machine = emev2_add_standard_devices_dt, - .timer = &shmobile_timer, + .init_time = shmobile_timer_init, .dt_compat = emev2_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index a35a6e0ff29..b580979923e 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -731,12 +731,6 @@ void __init r8a7740_add_standard_devices(void) rmobile_add_device_to_domain("A3SP", &i2c1_device); } -static void __init r8a7740_earlytimer_init(void) -{ - r8a7740_clock_init(0); - shmobile_earlytimer_init(); -} - void __init r8a7740_add_early_devices(void) { early_platform_add_devices(r8a7740_early_devices, @@ -744,9 +738,6 @@ void __init r8a7740_add_early_devices(void) /* setup early console here as well */ shmobile_setup_console(); - - /* override timer setup with soc-specific code */ - shmobile_timer.init = r8a7740_earlytimer_init; } #ifdef CONFIG_USE_OF @@ -789,7 +780,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") .init_irq = r8a7740_init_irq, .handle_irq = shmobile_handle_irq_intc, .init_machine = r8a7740_add_standard_devices_dt, - .timer = &shmobile_timer, + .init_time = shmobile_timer_init, .dt_compat = r8a7740_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index ac7e4fc26a0..344eb79658f 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -364,7 +364,7 @@ void __init r8a7779_add_standard_devices(void) /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } -static void __init r8a7779_earlytimer_init(void) +void __init r8a7779_earlytimer_init(void) { r8a7779_clock_init(); shmobile_earlytimer_init(); @@ -391,7 +391,4 @@ void __init r8a7779_add_early_devices(void) * As a final step pass earlyprint=sh-sci.2,115200 on the kernel * command line in case of the marzen board. */ - - /* override timer setup with soc-specific code */ - shmobile_timer.init = r8a7779_earlytimer_init; } diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 42f1945de97..d2079d5e333 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -1080,7 +1080,7 @@ void __init sh7372_add_standard_devices(void) ARRAY_SIZE(domain_devices)); } -static void __init sh7372_earlytimer_init(void) +void __init sh7372_earlytimer_init(void) { sh7372_clock_init(); shmobile_earlytimer_init(); @@ -1093,9 +1093,6 @@ void __init sh7372_add_early_devices(void) /* setup early console here as well */ shmobile_setup_console(); - - /* override timer setup with soc-specific code */ - shmobile_timer.init = sh7372_earlytimer_init; } #ifdef CONFIG_USE_OF @@ -1139,7 +1136,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") .init_irq = sh7372_init_irq, .handle_irq = shmobile_handle_irq_intc, .init_machine = sh7372_add_standard_devices_dt, - .timer = &shmobile_timer, + .init_time = shmobile_timer_init, .dt_compat = sh7372_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index eab1bae785a..48f7f583647 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -821,7 +821,7 @@ void __init sh73a0_add_standard_devices(void) /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak sh73a0_register_twd(void) { } -static void __init sh73a0_earlytimer_init(void) +void __init sh73a0_earlytimer_init(void) { sh73a0_clock_init(); shmobile_earlytimer_init(); @@ -835,7 +835,4 @@ void __init sh73a0_add_early_devices(void) /* setup early console here as well */ shmobile_setup_console(); - - /* override timer setup with soc-specific code */ - shmobile_timer.init = sh73a0_earlytimer_init; } diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index f6745628628..953eb1f9388 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -23,11 +23,11 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> +#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/emev2.h> #include <asm/smp_plat.h> #include <asm/smp_scu.h> -#include <asm/hardware/gic.h> #include <asm/cacheflush.h> #define EMEV2_SCU_BASE 0x1e000000 @@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct * /* Tell ROM loader about our vector (in headsmp.S) */ emev2_set_boot_vector(__pa(shmobile_secondary_vector)); - gic_raise_softirq(cpumask_of(cpu), 0); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); return 0; } diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 2ce6af9a6a3..3a4acf23edc 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -23,12 +23,12 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> +#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <mach/r8a7779.h> #include <asm/smp_plat.h> #include <asm/smp_scu.h> #include <asm/smp_twd.h> -#include <asm/hardware/gic.h> #define AVECR IOMEM(0xfe700040) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 624f00f70ab..5c5bcb59535 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -23,12 +23,12 @@ #include <linux/spinlock.h> #include <linux/io.h> #include <linux/delay.h> +#include <linux/irqchip/arm-gic.h> #include <mach/common.h> #include <asm/smp_plat.h> #include <mach/sh73a0.h> #include <asm/smp_scu.h> #include <asm/smp_twd.h> -#include <asm/hardware/gic.h> #define WUPCR IOMEM(0xe6151010) #define SRESCR IOMEM(0xe6151018) diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index a68919727e2..fdbe54a1155 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -60,10 +60,6 @@ void __init shmobile_earlytimer_init(void) late_time_init = shmobile_late_time_init; } -static void __init shmobile_timer_init(void) +void __init shmobile_timer_init(void) { } - -struct sys_timer shmobile_timer = { - .init = shmobile_timer_init, -}; diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 68dd1b69512..4e9e69d9e7d 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -22,9 +22,9 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> -#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <asm/smp_plat.h> @@ -83,8 +83,6 @@ static void __init socfpga_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 6732924a5fe..27d68468a02 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -15,12 +15,12 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/dw_apb_timer.h> +#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -62,11 +62,6 @@ static void __init socfpga_map_io(void) early_printk("Early printk initialized\n"); } -const static struct of_device_id irq_match[] = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {} -}; - void __init socfpga_sysmgr_init(void) { struct device_node *np; @@ -78,9 +73,9 @@ void __init socfpga_sysmgr_init(void) rst_manager_base_addr = of_iomap(np, 0); } -static void __init gic_init_irq(void) +static void __init socfpga_init_irq(void) { - of_irq_init(irq_match); + irqchip_init(); socfpga_sysmgr_init(); } @@ -105,9 +100,8 @@ static const char *altera_dt_match[] = { DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .smp = smp_ops(socfpga_smp_ops), .map_io = socfpga_map_io, - .init_irq = gic_init_irq, - .handle_irq = gic_handle_irq, - .timer = &dw_apb_timer, + .init_irq = socfpga_init_irq, + .init_time = dw_apb_timer_init, .init_machine = socfpga_cyclone5_init, .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h index c33f4d9361b..633e678e01a 100644 --- a/arch/arm/mach-spear13xx/include/mach/generic.h +++ b/arch/arm/mach-spear13xx/include/mach/generic.h @@ -18,7 +18,7 @@ #include <asm/mach/time.h> /* Add spear13xx structure declarations here */ -extern struct sys_timer spear13xx_timer; +extern void spear13xx_timer_init(void); extern struct pl022_ssp_controller pl022_plat_data; extern struct dw_dma_platform_data dmac_plat_data; extern struct dw_dma_slave cf_dma_priv; @@ -28,7 +28,6 @@ extern struct dw_dma_slave nand_write_dma_priv; /* Add spear13xx family function declarations here */ void __init spear_setup_of_timer(void); void __init spear13xx_map_io(void); -void __init spear13xx_dt_init_irq(void); void __init spear13xx_l2x0_init(void); bool dw_dma_filter(struct dma_chan *chan, void *slave); void spear_restart(char, const char *); diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c index 2eaa3fa7b43..af4ade61cd9 100644 --- a/arch/arm/mach-spear13xx/platsmp.c +++ b/arch/arm/mach-spear13xx/platsmp.c @@ -15,8 +15,8 @@ #include <linux/jiffies.h> #include <linux/io.h> #include <linux/smp.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> -#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <mach/spear.h> #include <mach/generic.h> @@ -104,8 +104,6 @@ static void __init spear13xx_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c index 02f4724bb0d..56214d1076e 100644 --- a/arch/arm/mach-spear13xx/spear1310.c +++ b/arch/arm/mach-spear13xx/spear1310.c @@ -14,9 +14,9 @@ #define pr_fmt(fmt) "SPEAr1310: " fmt #include <linux/amba/pl022.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> #include <linux/pata_arasan_cf_data.h> -#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/generic.h> @@ -90,9 +90,8 @@ static void __init spear1310_map_io(void) DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") .smp = smp_ops(spear13xx_smp_ops), .map_io = spear1310_map_io, - .init_irq = spear13xx_dt_init_irq, - .handle_irq = gic_handle_irq, - .timer = &spear13xx_timer, + .init_irq = irqchip_init, + .init_time = spear13xx_timer_init, .init_machine = spear1310_dt_init, .restart = spear_restart, .dt_compat = spear1310_dt_board_compat, diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c index 081014fb314..9a28beb2a11 100644 --- a/arch/arm/mach-spear13xx/spear1340.c +++ b/arch/arm/mach-spear13xx/spear1340.c @@ -18,7 +18,7 @@ #include <linux/delay.h> #include <linux/dw_dmac.h> #include <linux/of_platform.h> -#include <asm/hardware/gic.h> +#include <linux/irqchip.h> #include <asm/mach/arch.h> #include <mach/dma.h> #include <mach/generic.h> @@ -184,9 +184,8 @@ static const char * const spear1340_dt_board_compat[] = { DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") .smp = smp_ops(spear13xx_smp_ops), .map_io = spear13xx_map_io, - .init_irq = spear13xx_dt_init_irq, - .handle_irq = gic_handle_irq, - .timer = &spear13xx_timer, + .init_irq = irqchip_init, + .init_time = spear13xx_timer_init, .init_machine = spear1340_dt_init, .restart = spear_restart, .dt_compat = spear1340_dt_board_compat, diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index c4af775a845..c7d2b4a8d8c 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -17,9 +17,8 @@ #include <linux/clk.h> #include <linux/dw_dmac.h> #include <linux/err.h> -#include <linux/of_irq.h> +#include <linux/of.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <asm/smp_twd.h> #include <mach/dma.h> @@ -153,7 +152,7 @@ static void __init spear13xx_clk_init(void) pr_err("%s: Unknown machine\n", __func__); } -static void __init spear13xx_timer_init(void) +void __init spear13xx_timer_init(void) { char pclk_name[] = "osc_24m_clk"; struct clk *gpt_clk, *pclk; @@ -182,17 +181,3 @@ static void __init spear13xx_timer_init(void) spear_setup_of_timer(); twd_local_timer_of_register(); } - -struct sys_timer spear13xx_timer = { - .init = spear13xx_timer_init, -}; - -static const struct of_device_id gic_of_match[] __initconst = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, - { /* Sentinel */ } -}; - -void __init spear13xx_dt_init_irq(void) -{ - of_irq_init(gic_of_match); -} diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index ce19113ca79..df310799e41 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -22,7 +22,7 @@ #include <asm/mach/map.h> /* Add spear3xx family device structure declarations here */ -extern struct sys_timer spear3xx_timer; +extern void spear3xx_timer_init(void); extern struct pl022_ssp_controller pl022_plat_data; extern struct pl08x_platform_data pl080_plat_data; @@ -30,7 +30,6 @@ extern struct pl08x_platform_data pl080_plat_data; void __init spear_setup_of_timer(void); void __init spear3xx_clk_init(void); void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); void spear_restart(char, const char *); diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index a69cbfdb07e..bbc9b7e9c62 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -14,8 +14,8 @@ #define pr_fmt(fmt) "SPEAr300: " fmt #include <linux/amba/pl08x.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <mach/generic.h> #include <mach/spear.h> @@ -212,9 +212,8 @@ static void __init spear300_map_io(void) DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") .map_io = spear300_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, + .init_irq = irqchip_init, + .init_time = spear3xx_timer_init, .init_machine = spear300_dt_init, .restart = spear_restart, .dt_compat = spear300_dt_board_compat, diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index b963ebb10b5..c13a434a819 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -15,8 +15,8 @@ #include <linux/amba/pl08x.h> #include <linux/amba/serial.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <mach/generic.h> #include <mach/spear.h> @@ -254,9 +254,8 @@ static void __init spear310_map_io(void) DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") .map_io = spear310_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, + .init_irq = irqchip_init, + .init_time = spear3xx_timer_init, .init_machine = spear310_dt_init, .restart = spear_restart, .dt_compat = spear310_dt_board_compat, diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index 66e3a0c33e7..e1c77079a3e 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -16,8 +16,8 @@ #include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> #include <linux/amba/serial.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <mach/generic.h> #include <mach/spear.h> @@ -268,9 +268,8 @@ static void __init spear320_map_io(void) DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") .map_io = spear320_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, + .init_irq = irqchip_init, + .init_time = spear3xx_timer_init, .init_machine = spear320_dt_init, .restart = spear_restart, .dt_compat = spear320_dt_board_compat, diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 38fe95db31a..b2ba516ca2d 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -15,11 +15,8 @@ #include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> -#include <linux/irqchip/spear-shirq.h> -#include <linux/of_irq.h> #include <linux/io.h> #include <asm/hardware/pl080.h> -#include <asm/hardware/vic.h> #include <plat/pl080.h> #include <mach/generic.h> #include <mach/spear.h> @@ -87,7 +84,7 @@ void __init spear3xx_map_io(void) iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); } -static void __init spear3xx_timer_init(void) +void __init spear3xx_timer_init(void) { char pclk_name[] = "pll3_clk"; struct clk *gpt_clk, *pclk; @@ -115,20 +112,3 @@ static void __init spear3xx_timer_init(void) spear_setup_of_timer(); } - -struct sys_timer spear3xx_timer = { - .init = spear3xx_timer_init, -}; - -static const struct of_device_id vic_of_match[] __initconst = { - { .compatible = "arm,pl190-vic", .data = vic_of_init, }, - { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, }, - { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, }, - { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, }, - { /* Sentinel */ } -}; - -void __init spear3xx_dt_init_irq(void) -{ - of_irq_init(vic_of_match); -} diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 5a5a52db252..b8bd33ca88b 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -16,12 +16,11 @@ #include <linux/amba/pl08x.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_irq.h> #include <linux/of_platform.h> #include <asm/hardware/pl080.h> -#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> @@ -374,7 +373,7 @@ void __init spear6xx_map_io(void) iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); } -static void __init spear6xx_timer_init(void) +void __init spear6xx_timer_init(void) { char pclk_name[] = "pll3_clk"; struct clk *gpt_clk, *pclk; @@ -403,10 +402,6 @@ static void __init spear6xx_timer_init(void) spear_setup_of_timer(); } -struct sys_timer spear6xx_timer = { - .init = spear6xx_timer_init, -}; - /* Add auxdata to pass platform data */ struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, @@ -425,21 +420,10 @@ static const char *spear600_dt_board_compat[] = { NULL }; -static const struct of_device_id vic_of_match[] __initconst = { - { .compatible = "arm,pl190-vic", .data = vic_of_init, }, - { /* Sentinel */ } -}; - -static void __init spear6xx_dt_init_irq(void) -{ - of_irq_init(vic_of_match); -} - DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") .map_io = spear6xx_map_io, - .init_irq = spear6xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear6xx_timer, + .init_irq = irqchip_init, + .init_time = spear6xx_timer_init, .init_machine = spear600_dt_init, .restart = spear_restart, .dt_compat = spear600_dt_board_compat, diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3fdd0085e30..8709a39bd34 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -7,3 +7,4 @@ config ARCH_SUNXI select PINCTRL select SPARSE_IRQ select SUNXI_TIMER + select PINCTRL_SUNXI
\ No newline at end of file diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 1dc8a92e5a5..23afb732cb4 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -21,15 +21,16 @@ #include <linux/irqchip/sunxi.h> -#include <asm/hardware/vic.h> - #include <asm/mach/arch.h> #include <asm/mach/map.h> #include "sunxi.h" #define WATCHDOG_CTRL_REG 0x00 +#define WATCHDOG_CTRL_RESTART (1 << 0) #define WATCHDOG_MODE_REG 0x04 +#define WATCHDOG_MODE_ENABLE (1 << 0) +#define WATCHDOG_MODE_RESET_ENABLE (1 << 1) static void __iomem *wdt_base; @@ -50,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd) return; /* Enable timer and set reset bit in the watchdog */ - writel(3, wdt_base + WATCHDOG_MODE_REG); - writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG); - while(1) { + writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE, + wdt_base + WATCHDOG_MODE_REG); + + /* + * Restart the watchdog. The default (and lowest) interval + * value for the watchdog is 0.5s. + */ + writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG); + + while (1) { mdelay(5); - writel(3, wdt_base + WATCHDOG_MODE_REG); + writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE, + wdt_base + WATCHDOG_MODE_REG); } } @@ -91,6 +100,6 @@ DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") .init_irq = sunxi_init_irq, .handle_irq = sunxi_handle_irq, .restart = sunxi_restart, - .timer = &sunxi_timer, + .init_time = &sunxi_timer_init, .dt_compat = sunxi_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b442f15fd01..1ec7f80e2af 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -6,9 +6,9 @@ config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_720789 - select ARM_ERRATA_742230 + select ARM_ERRATA_742230 if SMP select ARM_ERRATA_751472 - select ARM_ERRATA_754327 + select ARM_ERRATA_754327 if SMP select ARM_ERRATA_764369 if SMP select ARM_GIC select CPU_FREQ_TABLE if CPU_FREQ diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 0979e8bba78..f0520961baf 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -2,15 +2,16 @@ obj-y += common.o obj-y += io.o obj-y += irq.o obj-y += clock.o -obj-y += timer.o obj-y += fuse.o obj-y += pmc.o obj-y += flowctrl.o obj-y += powergate.o obj-y += apbio.o obj-y += pm.o +obj-y += reset.o +obj-y += reset-handler.o +obj-y += sleep.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_CPU_IDLE) += sleep.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o @@ -27,7 +28,6 @@ ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o endif obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_SMP) += reset.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index d091675ba37..d7aa52ea6cf 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c @@ -38,7 +38,7 @@ static void tegra_apb_writel_direct(u32 value, unsigned long offset); static struct dma_chan *tegra_apb_dma_chan; static struct dma_slave_config dma_sconfig; -bool tegra_apb_dma_init(void) +static bool tegra_apb_dma_init(void) { dma_cap_mask_t mask; diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 734d9cc87f2..d320f7ad735 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -15,6 +15,7 @@ * */ +#include <linux/clocksource.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> @@ -25,7 +26,6 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_fdt.h> -#include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/pda_power.h> #include <linux/platform_data/tegra_usb.h> @@ -34,7 +34,6 @@ #include <linux/i2c-tegra.h> #include <linux/usb/tegra_usb_phy.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> @@ -45,31 +44,31 @@ #include "common.h" #include "iomap.h" -struct tegra_ehci_platform_data tegra_ehci1_pdata = { +static struct tegra_ehci_platform_data tegra_ehci1_pdata = { .operating_mode = TEGRA_USB_OTG, .power_down_on_bus_suspend = 1, .vbus_gpio = -1, }; -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { +static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { .reset_gpio = -1, .clk = "cdev2", }; -struct tegra_ehci_platform_data tegra_ehci2_pdata = { +static struct tegra_ehci_platform_data tegra_ehci2_pdata = { .phy_config = &tegra_ehci2_ulpi_phy_config, .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, .vbus_gpio = -1, }; -struct tegra_ehci_platform_data tegra_ehci3_pdata = { +static struct tegra_ehci_platform_data tegra_ehci3_pdata = { .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, .vbus_gpio = -1, }; -struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), @@ -202,8 +201,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") .smp = smp_ops(tegra_smp_ops), .init_early = tegra20_init_early, .init_irq = tegra_dt_init_irq, - .handle_irq = gic_handle_irq, - .timer = &tegra_sys_timer, + .init_time = clocksource_of_init, .init_machine = tegra_dt_init, .init_late = tegra_dt_init_late, .restart = tegra_assert_system_reset, diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 6497d1236b0..97e1f67fc31 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -23,6 +23,7 @@ * */ +#include <linux/clocksource.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> @@ -31,14 +32,13 @@ #include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include "board.h" #include "clock.h" #include "common.h" #include "iomap.h" -struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL), @@ -112,8 +112,7 @@ DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") .map_io = tegra_map_common_io, .init_early = tegra30_init_early, .init_irq = tegra_dt_init_irq, - .handle_irq = gic_handle_irq, - .timer = &tegra_sys_timer, + .init_time = clocksource_of_init, .init_machine = tegra30_dt_init, .init_late = tegra_init_late, .restart = tegra_assert_system_reset, diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 91fbe733a21..da8f5a3c424 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -55,5 +55,4 @@ static inline int harmony_pcie_init(void) { return 0; } void __init tegra_paz00_wifikill_init(void); -extern struct sys_timer tegra_sys_timer; #endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index d54cfc54b9f..8f0ffe97ffe 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -21,10 +21,9 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/delay.h> -#include <linux/of_irq.h> +#include <linux/irqchip.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <mach/powergate.h> @@ -37,6 +36,7 @@ #include "apbio.h" #include "sleep.h" #include "pm.h" +#include "reset.h" /* * Storage for debug-macro.S's state. @@ -57,15 +57,10 @@ u32 tegra_uart_config[4] = { }; #ifdef CONFIG_OF -static const struct of_device_id tegra_dt_irq_match[] __initconst = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, - { } -}; - void __init tegra_dt_init_irq(void) { tegra_init_irq(); - of_irq_init(tegra_dt_irq_match); + irqchip_init(); } #endif @@ -137,6 +132,7 @@ static void __init tegra_init_cache(void) #ifdef CONFIG_ARCH_TEGRA_2x_SOC void __init tegra20_init_early(void) { + tegra_cpu_reset_handler_init(); tegra_apb_io_init(); tegra_init_fuse(); tegra2_init_clocks(); @@ -150,6 +146,7 @@ void __init tegra20_init_early(void) #ifdef CONFIG_ARCH_TEGRA_3x_SOC void __init tegra30_init_early(void) { + tegra_cpu_reset_handler_init(); tegra_apb_io_init(); tegra_init_fuse(); tegra30_init_clocks(); diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 02f71b4f1e5..32f8eb3fe34 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -1,4 +1,5 @@ extern struct smp_operations tegra_smp_ops; +extern int tegra_cpu_kill(unsigned int cpu); extern void tegra_cpu_die(unsigned int cpu); extern int tegra_cpu_disable(unsigned int cpu); diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index a74d3c7d2e2..ece29ab15b5 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -214,24 +214,6 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) if (policy->cpu >= NUM_CPUS) return -EINVAL; - cpu_clk = clk_get_sys(NULL, "cpu"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(pll_x_clk)) - return PTR_ERR(pll_x_clk); - - pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(pll_p_clk)) - return PTR_ERR(pll_p_clk); - - emc_clk = clk_get_sys("cpu", "emc"); - if (IS_ERR(emc_clk)) { - clk_put(cpu_clk); - return PTR_ERR(emc_clk); - } - clk_prepare_enable(emc_clk); clk_prepare_enable(cpu_clk); @@ -243,8 +225,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) /* FIXME: what's the actual transition time? */ policy->cpuinfo.transition_latency = 300 * 1000; - policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; - cpumask_copy(policy->related_cpus, cpu_possible_mask); + cpumask_copy(policy->cpus, cpu_possible_mask); if (policy->cpu == 0) register_pm_notifier(&tegra_cpu_pm_notifier); @@ -256,8 +237,6 @@ static int tegra_cpu_exit(struct cpufreq_policy *policy) { cpufreq_frequency_table_cpuinfo(policy, freq_table); clk_disable_unprepare(emc_clk); - clk_put(emc_clk); - clk_put(cpu_clk); return 0; } @@ -278,12 +257,32 @@ static struct cpufreq_driver tegra_cpufreq_driver = { static int __init tegra_cpufreq_init(void) { + cpu_clk = clk_get_sys(NULL, "cpu"); + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + pll_x_clk = clk_get_sys(NULL, "pll_x"); + if (IS_ERR(pll_x_clk)) + return PTR_ERR(pll_x_clk); + + pll_p_clk = clk_get_sys(NULL, "pll_p"); + if (IS_ERR(pll_p_clk)) + return PTR_ERR(pll_p_clk); + + emc_clk = clk_get_sys("cpu", "emc"); + if (IS_ERR(emc_clk)) { + clk_put(cpu_clk); + return PTR_ERR(emc_clk); + } + return cpufreq_register_driver(&tegra_cpufreq_driver); } static void __exit tegra_cpufreq_exit(void) { cpufreq_unregister_driver(&tegra_cpufreq_driver); + clk_put(emc_clk); + clk_put(cpu_clk); } diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 5e8cbf5b799..82530bd9b8c 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -121,9 +121,9 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, } #endif -static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) +static int tegra30_idle_lp2(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) { u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; bool entered_lp2 = false; diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index a2250ddae79..5393eb2cae2 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -26,14 +26,14 @@ #include "flowctrl.h" #include "iomap.h" -u8 flowctrl_offset_halt_cpu[] = { +static u8 flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, FLOW_CTRL_HALT_CPU1_EVENTS, FLOW_CTRL_HALT_CPU1_EVENTS + 8, FLOW_CTRL_HALT_CPU1_EVENTS + 16, }; -u8 flowctrl_offset_cpu_csr[] = { +static u8 flowctrl_offset_cpu_csr[] = { FLOW_CTRL_CPU0_CSR, FLOW_CTRL_CPU1_CSR, FLOW_CTRL_CPU1_CSR + 8, diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4a317fae686..b2834810b02 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -1,22 +1,9 @@ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/cache.h> -#include <asm/asm-offsets.h> -#include <asm/hardware/cache-l2x0.h> - -#include "flowctrl.h" -#include "iomap.h" -#include "reset.h" #include "sleep.h" -#define APB_MISC_GP_HIDREV 0x804 -#define PMC_SCRATCH41 0x140 - -#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - .section ".text.head", "ax" - __CPUINIT /* * Tegra specific entry point for secondary CPUs. @@ -61,7 +48,6 @@ ENTRY(v7_invalidate_l1) mov pc, lr ENDPROC(v7_invalidate_l1) - ENTRY(tegra_secondary_startup) bl v7_invalidate_l1 /* Enable coresight */ @@ -69,210 +55,3 @@ ENTRY(tegra_secondary_startup) mcr p14, 0, r0, c7, c12, 6 b secondary_startup ENDPROC(tegra_secondary_startup) - -#ifdef CONFIG_PM_SLEEP -/* - * tegra_resume - * - * CPU boot vector when restarting the a CPU following - * an LP2 transition. Also branched to by LP0 and LP1 resume after - * re-enabling sdram. - */ -ENTRY(tegra_resume) - bl v7_invalidate_l1 - /* Enable coresight */ - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 - - cpu_id r0 - cmp r0, #0 @ CPU0? - bne cpu_resume @ no - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC - /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) - beq 1f @ Yes - /* Clear the flow controller flags for this CPU. */ - mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR - ldr r1, [r2] - /* Clear event & intr flag */ - orr r1, r1, \ - #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps - bic r1, r1, r0 - str r1, [r2] -1: -#endif - -#ifdef CONFIG_HAVE_ARM_SCU - /* enable SCU */ - mov32 r0, TEGRA_ARM_PERIF_BASE - ldr r1, [r0] - orr r1, r1, #1 - str r1, [r0] -#endif - - /* L2 cache resume & re-enable */ - l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr - - b cpu_resume -ENDPROC(tegra_resume) -#endif - -#ifdef CONFIG_CACHE_L2X0 - .globl l2x0_saved_regs_addr -l2x0_saved_regs_addr: - .long 0 -#endif - - .align L1_CACHE_SHIFT -ENTRY(__tegra_cpu_reset_handler_start) - -/* - * __tegra_cpu_reset_handler: - * - * Common handler for all CPU reset events. - * - * Register usage within the reset handler: - * - * R7 = CPU present (to the OS) mask - * R8 = CPU in LP1 state mask - * R9 = CPU in LP2 state mask - * R10 = CPU number - * R11 = CPU mask - * R12 = pointer to reset handler data - * - * NOTE: This code is copied to IRAM. All code and data accesses - * must be position-independent. - */ - - .align L1_CACHE_SHIFT -ENTRY(__tegra_cpu_reset_handler) - - cpsid aif, 0x13 @ SVC mode, interrupts disabled - mrc p15, 0, r10, c0, c0, 5 @ MPIDR - and r10, r10, #0x3 @ R10 = CPU number - mov r11, #1 - mov r11, r11, lsl r10 @ R11 = CPU mask - adr r12, __tegra_cpu_reset_handler_data - -#ifdef CONFIG_SMP - /* Does the OS know about this CPU? */ - ldr r7, [r12, #RESET_DATA(MASK_PRESENT)] - tst r7, r11 @ if !present - bleq __die @ CPU not present (to OS) -#endif - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) - bne 1f - /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov32 r6, TEGRA_PMC_BASE - mov r0, #0 - cmp r10, #0 - strne r0, [r6, #PMC_SCRATCH41] -1: -#endif - - /* Waking up from LP2? */ - ldr r9, [r12, #RESET_DATA(MASK_LP2)] - tst r9, r11 @ if in_lp2 - beq __is_not_lp2 - ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] - cmp lr, #0 - bleq __die @ no LP2 startup handler - bx lr - -__is_not_lp2: - -#ifdef CONFIG_SMP - /* - * Can only be secondary boot (initial or hotplug) but CPU 0 - * cannot be here. - */ - cmp r10, #0 - bleq __die @ CPU0 cannot be here - ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] - cmp lr, #0 - bleq __die @ no secondary startup handler - bx lr -#endif - -/* - * We don't know why the CPU reset. Just kill it. - * The LR register will contain the address we died at + 4. - */ - -__die: - sub lr, lr, #4 - mov32 r7, TEGRA_PMC_BASE - str lr, [r7, #PMC_SCRATCH41] - - mov32 r7, TEGRA_CLK_RESET_BASE - - /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) - bne 1f - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - mov32 r0, 0x1111 - mov r1, r0, lsl r10 - str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET -#endif -1: -#ifdef CONFIG_ARCH_TEGRA_3x_SOC - mov32 r6, TEGRA_FLOW_CTRL_BASE - - cmp r10, #0 - moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS - moveq r2, #FLOW_CTRL_CPU0_CSR - movne r1, r10, lsl #3 - addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) - addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) - - /* Clear CPU "event" and "interrupt" flags and power gate - it when halting but not before it is in the "WFI" state. */ - ldr r0, [r6, +r2] - orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - orr r0, r0, #FLOW_CTRL_CSR_ENABLE - str r0, [r6, +r2] - - /* Unconditionally halt this CPU */ - mov r0, #FLOW_CTRL_WAITEVENT - str r0, [r6, +r1] - ldr r0, [r6, +r1] @ memory barrier - - dsb - isb - wfi @ CPU should be power gated here - - /* If the CPU didn't power gate above just kill it's clock. */ - - mov r0, r11, lsl #8 - str r0, [r7, #348] @ CLK_CPU_CMPLX_SET -#endif - - /* If the CPU still isn't dead, just spin here. */ - b . -ENDPROC(__tegra_cpu_reset_handler) - - .align L1_CACHE_SHIFT - .type __tegra_cpu_reset_handler_data, %object - .globl __tegra_cpu_reset_handler_data -__tegra_cpu_reset_handler_data: - .rept TEGRA_RESET_DATA_SIZE - .long 0 - .endr - .align L1_CACHE_SHIFT - -ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index dca5141a2c3..6a27de4001e 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -19,6 +19,17 @@ static void (*tegra_hotplug_shutdown)(void); +int tegra_cpu_kill(unsigned cpu) +{ + cpu = cpu_logical_map(cpu); + + /* Clock gate the CPU */ + tegra_wait_cpu_in_reset(cpu); + tegra_disable_cpu_clock(cpu); + + return 1; +} + /* * platform-specific code to shutdown a CPU * @@ -26,18 +37,12 @@ static void (*tegra_hotplug_shutdown)(void); */ void __ref tegra_cpu_die(unsigned int cpu) { - cpu = cpu_logical_map(cpu); - - /* Flush the L1 data cache. */ - flush_cache_all(); + /* Clean L1 data cache */ + tegra_disable_clean_inv_dcache(); /* Shut down the current CPU. */ tegra_hotplug_shutdown(); - /* Clock gate the CPU */ - tegra_wait_cpu_in_reset(cpu); - tegra_disable_cpu_clock(cpu); - /* Should never return here. */ BUG(); } diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h index 485003f9b63..08386418196 100644 --- a/arch/arm/mach-tegra/include/mach/uncompress.h +++ b/arch/arm/mach-tegra/include/mach/uncompress.h @@ -172,8 +172,4 @@ static inline void arch_decomp_setup(void) uart[UART_LCR << DEBUG_UART_SHIFT] = 3; } -static inline void arch_decomp_wdog(void) -{ -} - #endif diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index b7886f18351..2ff2128cb9d 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -22,8 +22,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/of.h> - -#include <asm/hardware/gic.h> +#include <linux/irqchip/arm-gic.h> #include "board.h" #include "iomap.h" diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 1b926df99c4..3c4a43c892a 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -18,11 +18,12 @@ #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> -#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> +#include <asm/smp_plat.h> #include <mach/powergate.h> @@ -36,6 +37,7 @@ extern void tegra_secondary_startup(void); +static cpumask_t tegra_cpu_init_mask; static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); #define EVP_CPU_RESET_VECTOR \ @@ -50,6 +52,7 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu) */ gic_secondary_init(0); + cpumask_set_cpu(cpu, &tegra_cpu_init_mask); } static int tegra20_power_up_cpu(unsigned int cpu) @@ -72,14 +75,42 @@ static int tegra30_power_up_cpu(unsigned int cpu) if (pwrgateid < 0) return pwrgateid; - /* If this is the first boot, toggle powergates directly. */ + /* + * The power up sequence of cold boot CPU and warm boot CPU + * was different. + * + * For warm boot CPU that was resumed from CPU hotplug, the + * power will be resumed automatically after un-halting the + * flow controller of the warm boot CPU. We need to wait for + * the confirmaiton that the CPU is powered then removing + * the IO clamps. + * For cold boot CPU, do not wait. After the cold boot CPU be + * booted, it will run to tegra_secondary_init() and set + * tegra_cpu_init_mask which influences what tegra30_power_up_cpu() + * next time around. + */ + if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { + timeout = jiffies + msecs_to_jiffies(50); + do { + if (!tegra_powergate_is_powered(pwrgateid)) + goto remove_clamps; + udelay(10); + } while (time_before(jiffies, timeout)); + } + + /* + * The power status of the cold boot CPU is power gated as + * default. To power up the cold boot CPU, the power should + * be un-gated by un-toggling the power gate register + * manually. + */ if (!tegra_powergate_is_powered(pwrgateid)) { ret = tegra_powergate_power_on(pwrgateid); if (ret) return ret; /* Wait for the power to come up. */ - timeout = jiffies + 10*HZ; + timeout = jiffies + msecs_to_jiffies(100); while (tegra_powergate_is_powered(pwrgateid)) { if (time_after(jiffies, timeout)) return -ETIMEDOUT; @@ -87,6 +118,7 @@ static int tegra30_power_up_cpu(unsigned int cpu) } } +remove_clamps: /* CPU partition is powered. Enable the CPU clock. */ tegra_enable_cpu_clock(cpu); udelay(10); @@ -105,6 +137,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct * { int status; + cpu = cpu_logical_map(cpu); + /* * Force the CPU into reset. The CPU must remain in reset when the * flow controller state is cleared (which will cause the flow @@ -159,13 +193,13 @@ static void __init tegra_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) { - tegra_cpu_reset_handler_init(); + /* Always mark the boot CPU (CPU0) as initialized. */ + cpumask_set_cpu(0, &tegra_cpu_init_mask); + scu_enable(scu_base); } @@ -175,6 +209,7 @@ struct smp_operations tegra_smp_ops __initdata = { .smp_secondary_init = tegra_secondary_init, .smp_boot_secondary = tegra_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = tegra_cpu_kill, .cpu_die = tegra_cpu_die, .cpu_disable = tegra_cpu_disable, #endif diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 1b11707eaca..498d70b3377 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -148,7 +148,7 @@ static void suspend_cpu_complex(void) save_cpu_arch_register(); } -void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id) +void tegra_clear_cpu_in_lp2(int phy_cpu_id) { u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -160,7 +160,7 @@ void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id) spin_unlock(&tegra_lp2_lock); } -bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id) +bool tegra_set_cpu_in_lp2(int phy_cpu_id) { bool last_cpu = false; cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S new file mode 100644 index 00000000000..54382ceade4 --- /dev/null +++ b/arch/arm/mach-tegra/reset-handler.S @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +#include <asm/cache.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h> + +#include "flowctrl.h" +#include "iomap.h" +#include "reset.h" +#include "sleep.h" + +#define APB_MISC_GP_HIDREV 0x804 +#define PMC_SCRATCH41 0x140 + +#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) + +#ifdef CONFIG_PM_SLEEP +/* + * tegra_resume + * + * CPU boot vector when restarting the a CPU following + * an LP2 transition. Also branched to by LP0 and LP1 resume after + * re-enabling sdram. + */ +ENTRY(tegra_resume) + bl v7_invalidate_l1 + /* Enable coresight */ + mov32 r0, 0xC5ACCE55 + mcr p14, 0, r0, c7, c12, 6 + + cpu_id r0 + cmp r0, #0 @ CPU0? + bne cpu_resume @ no + +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + beq 1f @ Yes + /* Clear the flow controller flags for this CPU. */ + mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR + ldr r1, [r2] + /* Clear event & intr flag */ + orr r1, r1, \ + #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps + bic r1, r1, r0 + str r1, [r2] +1: +#endif + +#ifdef CONFIG_HAVE_ARM_SCU + /* enable SCU */ + mov32 r0, TEGRA_ARM_PERIF_BASE + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] +#endif + + /* L2 cache resume & re-enable */ + l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr + + b cpu_resume +ENDPROC(tegra_resume) +#endif + +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_saved_regs_addr +l2x0_saved_regs_addr: + .long 0 +#endif + + .align L1_CACHE_SHIFT +ENTRY(__tegra_cpu_reset_handler_start) + +/* + * __tegra_cpu_reset_handler: + * + * Common handler for all CPU reset events. + * + * Register usage within the reset handler: + * + * R7 = CPU present (to the OS) mask + * R8 = CPU in LP1 state mask + * R9 = CPU in LP2 state mask + * R10 = CPU number + * R11 = CPU mask + * R12 = pointer to reset handler data + * + * NOTE: This code is copied to IRAM. All code and data accesses + * must be position-independent. + */ + + .align L1_CACHE_SHIFT +ENTRY(__tegra_cpu_reset_handler) + + cpsid aif, 0x13 @ SVC mode, interrupts disabled + mrc p15, 0, r10, c0, c0, 5 @ MPIDR + and r10, r10, #0x3 @ R10 = CPU number + mov r11, #1 + mov r11, r11, lsl r10 @ R11 = CPU mask + adr r12, __tegra_cpu_reset_handler_data + +#ifdef CONFIG_SMP + /* Does the OS know about this CPU? */ + ldr r7, [r12, #RESET_DATA(MASK_PRESENT)] + tst r7, r11 @ if !present + bleq __die @ CPU not present (to OS) +#endif + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + bne 1f + /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ + mov32 r6, TEGRA_PMC_BASE + mov r0, #0 + cmp r10, #0 + strne r0, [r6, #PMC_SCRATCH41] +1: +#endif + + /* Waking up from LP2? */ + ldr r9, [r12, #RESET_DATA(MASK_LP2)] + tst r9, r11 @ if in_lp2 + beq __is_not_lp2 + ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] + cmp lr, #0 + bleq __die @ no LP2 startup handler + bx lr + +__is_not_lp2: + +#ifdef CONFIG_SMP + /* + * Can only be secondary boot (initial or hotplug) but CPU 0 + * cannot be here. + */ + cmp r10, #0 + bleq __die @ CPU0 cannot be here + ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] + cmp lr, #0 + bleq __die @ no secondary startup handler + bx lr +#endif + +/* + * We don't know why the CPU reset. Just kill it. + * The LR register will contain the address we died at + 4. + */ + +__die: + sub lr, lr, #4 + mov32 r7, TEGRA_PMC_BASE + str lr, [r7, #PMC_SCRATCH41] + + mov32 r7, TEGRA_CLK_RESET_BASE + + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + bne 1f + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + mov32 r0, 0x1111 + mov r1, r0, lsl r10 + str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET +#endif +1: +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + mov32 r6, TEGRA_FLOW_CTRL_BASE + + cmp r10, #0 + moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS + moveq r2, #FLOW_CTRL_CPU0_CSR + movne r1, r10, lsl #3 + addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) + addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) + + /* Clear CPU "event" and "interrupt" flags and power gate + it when halting but not before it is in the "WFI" state. */ + ldr r0, [r6, +r2] + orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + orr r0, r0, #FLOW_CTRL_CSR_ENABLE + str r0, [r6, +r2] + + /* Unconditionally halt this CPU */ + mov r0, #FLOW_CTRL_WAITEVENT + str r0, [r6, +r1] + ldr r0, [r6, +r1] @ memory barrier + + dsb + isb + wfi @ CPU should be power gated here + + /* If the CPU didn't power gate above just kill it's clock. */ + + mov r0, r11, lsl #8 + str r0, [r7, #348] @ CLK_CPU_CMPLX_SET +#endif + + /* If the CPU still isn't dead, just spin here. */ + b . +ENDPROC(__tegra_cpu_reset_handler) + + .align L1_CACHE_SHIFT + .type __tegra_cpu_reset_handler_data, %object + .globl __tegra_cpu_reset_handler_data +__tegra_cpu_reset_handler_data: + .rept TEGRA_RESET_DATA_SIZE + .long 0 + .endr + .align L1_CACHE_SHIFT + +ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 3fd89ecd158..1ac434e0068 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -75,7 +75,7 @@ void __init tegra_cpu_reset_handler_init(void) #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = - *((u32 *)cpu_present_mask); + *((u32 *)cpu_possible_mask); __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = virt_to_phys((void *)tegra_secondary_startup); #endif diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 72ce709799d..ad2ca07d057 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -33,9 +33,6 @@ * should never return */ ENTRY(tegra20_hotplug_shutdown) - /* Turn off SMP coherency */ - exit_smp r4, r5 - /* Put this CPU down */ cpu_id r0 bl tegra20_cpu_shutdown diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 562a8e7e413..63a15bd9b65 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -32,9 +32,6 @@ * Should never return. */ ENTRY(tegra30_hotplug_shutdown) - /* Turn off SMP coherency */ - exit_smp r4, r5 - /* Powergate this CPU */ mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN bl tegra30_cpu_shutdown diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 26afa7cbed1..addae357da3 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -34,7 +34,7 @@ #include "flowctrl.h" #include "sleep.h" -#ifdef CONFIG_PM_SLEEP +#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) /* * tegra_disable_clean_inv_dcache * @@ -60,7 +60,9 @@ ENTRY(tegra_disable_clean_inv_dcache) ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} ENDPROC(tegra_disable_clean_inv_dcache) +#endif +#ifdef CONFIG_PM_SLEEP /* * tegra_sleep_cpu_finish(unsigned long v2p) * diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 9821ee72542..56505c381ea 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -106,6 +106,7 @@ exit_l2_resume: #else void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); +void tegra_disable_clean_inv_dcache(void); #ifdef CONFIG_HOTPLUG_CPU void tegra20_hotplug_init(void); diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c index e18aa2f83eb..ce7ce42a1ac 100644 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ b/arch/arm/mach-tegra/tegra2_emc.c @@ -312,11 +312,9 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENOMEM; } - emc_regbase = devm_request_and_ioremap(&pdev->dev, res); - if (!emc_regbase) { - dev_err(&pdev->dev, "failed to remap registers\n"); - return -ENOMEM; - } + emc_regbase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(emc_regbase)) + return PTR_ERR(emc_regbase); pdata = pdev->dev.platform_data; diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c index 6942c7add3b..741d264d5ec 100644 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c @@ -1183,7 +1183,7 @@ static struct clk tegra_dsib = { .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0), }; -struct clk *tegra_list_clks[] = { +static struct clk *tegra_list_clks[] = { &tegra_apbdma, &tegra_rtc, &tegra_kbc, @@ -1289,7 +1289,7 @@ struct clk *tegra_list_clks[] = { * configuration. List those here to register them twice in the clock lookup * table under two names. */ -struct clk_duplicate tegra_clk_duplicates[] = { +static struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("uarta", "serial8250.0", NULL), CLK_DUPLICATE("uartb", "serial8250.1", NULL), CLK_DUPLICATE("uartc", "serial8250.2", NULL), @@ -1340,7 +1340,7 @@ struct clk_duplicate tegra_clk_duplicates[] = { CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"), }; -struct clk *tegra_ptr_clks[] = { +static struct clk *tegra_ptr_clks[] = { &tegra_clk_32k, &tegra_clk_m, &tegra_clk_m_div2, diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c deleted file mode 100644 index e4863f3e9ee..00000000000 --- a/arch/arm/mach-tegra/timer.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * arch/arch/mach-tegra/timer.c - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/init.h> -#include <linux/err.h> -#include <linux/time.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include <asm/mach/time.h> -#include <asm/smp_twd.h> -#include <asm/sched_clock.h> - -#include "board.h" - -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 - -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c - -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 - -#define TIMER_PTV 0x0 -#define TIMER_PCR 0x4 - -static void __iomem *timer_reg_base; -static void __iomem *rtc_base; - -static struct timespec persistent_ts; -static u64 persistent_ms, last_persistent_ms; - -#define timer_writel(value, reg) \ - __raw_writel(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - __raw_readl(timer_reg_base + (reg)) - -static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - u32 reg; - - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); - - return 0; -} - -static void tegra_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - u32 reg; - - timer_writel(0, TIMER3_BASE + TIMER_PTV); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - reg = 0xC0000000 | ((1000000/HZ)-1); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); - break; - case CLOCK_EVT_MODE_ONESHOT: - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static struct clock_event_device tegra_clockevent = { - .name = "timer0", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_next_event = tegra_timer_set_next_event, - .set_mode = tegra_timer_set_mode, -}; - -static u32 notrace tegra_read_sched_clock(void) -{ - return timer_readl(TIMERUS_CNTR_1US); -} - -/* - * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static u64 tegra_rtc_read_ms(void) -{ - u32 ms = readl(rtc_base + RTC_MILLISECONDS); - u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); - return (u64)s * MSEC_PER_SEC + ms; -} - -/* - * tegra_read_persistent_clock - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec. - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static void tegra_read_persistent_clock(struct timespec *ts) -{ - u64 delta; - struct timespec *tsp = &persistent_ts; - - last_persistent_ms = persistent_ms; - persistent_ms = tegra_rtc_read_ms(); - delta = persistent_ms - last_persistent_ms; - - timespec_add_ns(tsp, delta * NSEC_PER_MSEC); - *ts = *tsp; -} - -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction tegra_timer_irq = { - .name = "timer0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_interrupt, - .dev_id = &tegra_clockevent, -}; - -static const struct of_device_id timer_match[] __initconst = { - { .compatible = "nvidia,tegra20-timer" }, - {} -}; - -static const struct of_device_id rtc_match[] __initconst = { - { .compatible = "nvidia,tegra20-rtc" }, - {} -}; - -static void __init tegra_init_timer(void) -{ - struct device_node *np; - struct clk *clk; - unsigned long rate; - int ret; - - np = of_find_matching_node(NULL, timer_match); - if (!np) { - pr_err("Failed to find timer DT node\n"); - BUG(); - } - - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers"); - BUG(); - } - - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - BUG(); - } - - clk = clk_get_sys("timer", NULL); - if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); - rate = 12000000; - } else { - clk_prepare_enable(clk); - rate = clk_get_rate(clk); - } - - of_node_put(np); - - np = of_find_matching_node(NULL, rtc_match); - if (!np) { - pr_err("Failed to find RTC DT node\n"); - BUG(); - } - - rtc_base = of_iomap(np, 0); - if (!rtc_base) { - pr_err("Can't map RTC registers"); - BUG(); - } - - /* - * rtc registers are used by read_persistent_clock, keep the rtc clock - * enabled - */ - clk = clk_get_sys("rtc-tegra", NULL); - if (IS_ERR(clk)) - pr_warn("Unable to get rtc-tegra clock\n"); - else - clk_prepare_enable(clk); - - of_node_put(np); - - switch (rate) { - case 12000000: - timer_writel(0x000b, TIMERUS_USEC_CFG); - break; - case 13000000: - timer_writel(0x000c, TIMERUS_USEC_CFG); - break; - case 19200000: - timer_writel(0x045f, TIMERUS_USEC_CFG); - break; - case 26000000: - timer_writel(0x0019, TIMERUS_USEC_CFG); - break; - default: - WARN(1, "Unknown clock rate"); - } - - setup_sched_clock(tegra_read_sched_clock, 32, 1000000); - - if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { - pr_err("Failed to register clocksource\n"); - BUG(); - } - - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); - if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); - BUG(); - } - - clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); - tegra_clockevent.max_delta_ns = - clockevent_delta2ns(0x1fffffff, &tegra_clockevent); - tegra_clockevent.min_delta_ns = - clockevent_delta2ns(0x1, &tegra_clockevent); - tegra_clockevent.cpumask = cpu_all_mask; - tegra_clockevent.irq = tegra_timer_irq.irq; - clockevents_register_device(&tegra_clockevent); -#ifdef CONFIG_HAVE_ARM_TWD - twd_local_timer_of_register(); -#endif - register_persistent_clock(NULL, tegra_read_persistent_clock); -} - -struct sys_timer tegra_sys_timer = { - .init = tegra_init_timer, -}; - -#ifdef CONFIG_PM -static u32 usec_config; - -void tegra_timer_suspend(void) -{ - usec_config = timer_readl(TIMERUS_USEC_CFG); -} - -void tegra_timer_resume(void) -{ - timer_writel(usec_config, TIMERUS_USEC_CFG); -} -#endif diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 4ce77cdc31c..12060ae4e8f 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -31,11 +31,11 @@ #include <linux/dma-mapping.h> #include <linux/platform_data/clk-u300.h> #include <linux/platform_data/pinctrl-coh901.h> +#include <linux/irqchip/arm-vic.h> #include <asm/types.h> #include <asm/setup.h> #include <asm/memory.h> -#include <asm/hardware/vic.h> #include <asm/mach/map.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -1779,8 +1779,7 @@ MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") .map_io = u300_map_io, .nr_irqs = 0, .init_irq = u300_init_irq, - .handle_irq = vic_handle_irq, - .timer = &u300_timer, + .init_time = u300_timer_init, .init_machine = u300_init_machine, .restart = u300_restart, MACHINE_END diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h index 29acb718acf..783e7e60101 100644 --- a/arch/arm/mach-u300/include/mach/uncompress.h +++ b/arch/arm/mach-u300/include/mach/uncompress.h @@ -43,4 +43,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 1da10e20e99..d9e73209c9b 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -349,7 +349,7 @@ static u32 notrace u300_read_sched_clock(void) /* * This sets up the system timers, clock source and clock event. */ -static void __init u300_timer_init(void) +void __init u300_timer_init(void) { struct clk *clk; unsigned long rate; @@ -413,11 +413,3 @@ static void __init u300_timer_init(void) * used by hrtimers! */ } - -/* - * Very simple system timer that only register the clock event and - * clock source. - */ -struct sys_timer u300_timer = { - .init = u300_timer_init, -}; diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h index b5e9791762e..d34287bc34f 100644 --- a/arch/arm/mach-u300/timer.h +++ b/arch/arm/mach-u300/timer.h @@ -1 +1 @@ -extern struct sys_timer u300_timer; +extern void u300_timer_init(void); diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 5dea90636d9..3e5bbd0e5b2 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -11,6 +11,7 @@ config UX500_SOC_COMMON select COMMON_CLK select PINCTRL select PINCTRL_NOMADIK + select PINCTRL_ABX500 select PL310_ERRATA_753970 if CACHE_PL310 config UX500_SOC_DB8500 @@ -18,6 +19,11 @@ config UX500_SOC_DB8500 select CPU_FREQ_TABLE if CPU_FREQ select MFD_DB8500_PRCMU select PINCTRL_DB8500 + select PINCTRL_DB8540 + select PINCTRL_AB8500 + select PINCTRL_AB8505 + select PINCTRL_AB9540 + select PINCTRL_AB8540 select REGULATOR select REGULATOR_DB8500_PRCMU diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c index 1f47d962e3a..7037d3687e9 100644 --- a/arch/arm/mach-ux500/board-mop500-uib.c +++ b/arch/arm/mach-ux500/board-mop500-uib.c @@ -13,6 +13,7 @@ #include <mach/hardware.h> #include "board-mop500.h" +#include "id.h" enum mop500_uib { STUIB, diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index d453522edb0..3868aa4ff15 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -40,7 +40,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <mach/hardware.h> #include <mach/setup.h> @@ -90,26 +89,8 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = { }, }; -static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { +static struct abx500_gpio_platform_data ab8500_gpio_pdata = { .gpio_base = MOP500_AB8500_PIN_GPIO(1), - .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, - /* config_reg is the initial configuration of ab8500 pins. - * The pins can be configured as GPIO or alt functions based - * on value present in GpioSel1 to GpioSel6 and AlternatFunction - * register. This is the array of 7 configuration settings. - * One has to compile time decide these settings. Below is the - * explanation of these setting - * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO - * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO - * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO - * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO - * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO - * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO - * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured - * as GPIO then this register selectes the alternate fucntions - */ - .config_reg = {0x00, 0x1E, 0x80, 0x01, - 0x7A, 0x00, 0x00}, }; /* ab8500-codec */ @@ -215,7 +196,7 @@ static struct platform_device snowball_sbnet_dev = { }, }; -static struct ab8500_platform_data ab8500_platdata = { +struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, .regulator_reg_init = ab8500_regulator_reg_init, .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init), @@ -651,6 +632,7 @@ static void __init mop500_init_machine(void) int i2c0_devs; int i; + platform_device_register(&db8500_prcmu_device); mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; mop500_pinmaps_init(); @@ -685,6 +667,7 @@ static void __init snowball_init_machine(void) struct device *parent = NULL; int i; + platform_device_register(&db8500_prcmu_device); snowball_pinmaps_init(); parent = u8500_init_devices(&ab8500_platdata); @@ -710,6 +693,7 @@ static void __init hrefv60_init_machine(void) int i2c0_devs; int i; + platform_device_register(&db8500_prcmu_device); /* * The HREFv60 board removed a GPIO expander and routed * all these GPIO pins to the internal GPIO controller @@ -751,8 +735,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform") .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, + .init_time = ux500_timer_init, .init_machine = mop500_init_machine, .init_late = ux500_init_late, MACHINE_END @@ -761,8 +744,7 @@ MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") .atag_offset = 0x100, .map_io = u8500_map_io, .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, + .init_time = ux500_timer_init, .init_machine = mop500_init_machine, .init_late = ux500_init_late, MACHINE_END @@ -772,8 +754,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") .smp = smp_ops(ux500_smp_ops), .map_io = u8500_map_io, .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, + .init_time = ux500_timer_init, .init_machine = hrefv60_init_machine, .init_late = ux500_init_late, MACHINE_END @@ -784,8 +765,7 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, + .init_time = ux500_timer_init, .init_machine = snowball_init_machine, .init_late = NULL, MACHINE_END diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 75d5b512a3d..1c1609da76c 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -10,7 +10,8 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> #include <mach/hardware.h> -#include <mach/id.h> + +#include "id.h" static void __iomem *l2x0_base; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 5b286e06474..19235cf7bbe 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -27,7 +27,6 @@ #include <asm/pmu.h> #include <asm/mach/map.h> #include <asm/mach/arch.h> -#include <asm/hardware/gic.h> #include <mach/hardware.h> #include <mach/setup.h> @@ -37,7 +36,9 @@ #include "devices-db8500.h" #include "ste-dma40-db8500.h" + #include "board-mop500.h" +#include "id.h" /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_uart_io_desc[] __initdata = { @@ -137,14 +138,9 @@ static struct platform_device db8500_pmu_device = { .dev.platform_data = &db8500_pmu_platdata, }; -static struct platform_device db8500_prcmu_device = { - .name = "db8500-prcmu", -}; - static struct platform_device *platform_devs[] __initdata = { &u8500_dma40_device, &db8500_pmu_device, - &db8500_prcmu_device, }; static resource_size_t __initdata db8500_gpio_base[] = { @@ -284,8 +280,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), + OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", + &db8500_prcmu_pdata), /* Requires device name bindings. */ - OF_DEV_AUXDATA("stericsson,nmk_pinctrl", U8500_PRCMU_BASE, + OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE, "pinctrl-db8500", NULL), /* Requires clock name and DMA bindings. */ OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, @@ -341,8 +339,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, + .init_time = ux500_timer_init, .init_machine = u8500_init_machine, .init_late = NULL, .dt_compat = stericsson_dt_platform_compat, diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 721e7b4275f..537870d3fea 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -17,9 +17,10 @@ #include <linux/of.h> #include <linux/of_irq.h> #include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-ux500.h> -#include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <mach/hardware.h> @@ -27,6 +28,7 @@ #include <mach/devices.h> #include "board-mop500.h" +#include "id.h" void __iomem *_PRCMU_BASE; @@ -42,11 +44,6 @@ void __iomem *_PRCMU_BASE; * This feels fragile because it depends on the gpio device getting probed * _before_ any device uses the gpio interrupts. */ -static const struct of_device_id ux500_dt_irq_match[] = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {}, -}; - void __init ux500_init_irq(void) { void __iomem *dist_base; @@ -62,7 +59,7 @@ void __init ux500_init_irq(void) #ifdef CONFIG_OF if (of_have_populated_dt()) - of_irq_init(ux500_dt_irq_match); + irqchip_init(); else #endif gic_init(0, 29, dist_base, cpu_base); @@ -71,13 +68,11 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - if (cpu_is_u8500_family()) + if (cpu_is_u8500_family() || cpu_is_u9540()) db8500_prcmu_early_init(); - if (cpu_is_u8500_family()) + if (cpu_is_u8500_family() || cpu_is_u9540()) u8500_clk_init(); - else if (cpu_is_u9540()) - u9540_clk_init(); else if (cpu_is_u8540()) u8540_clk_init(); } diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c index b54884bd254..ce9149302cc 100644 --- a/arch/arm/mach-ux500/cpuidle.c +++ b/arch/arm/mach-ux500/cpuidle.c @@ -40,8 +40,10 @@ static inline int ux500_enter_idle(struct cpuidle_device *dev, goto wfi; /* decouple the gic from the A9 cores */ - if (prcmu_gic_decouple()) + if (prcmu_gic_decouple()) { + spin_unlock(&master_lock); goto out; + } /* If an error occur, we will have to recouple the gic * manually */ diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 318d4902089..f3d9419f75d 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -13,11 +13,13 @@ #include <linux/amba/bus.h> #include <linux/amba/pl022.h> #include <linux/platform_data/dma-ste-dma40.h> +#include <linux/mfd/dbx500-prcmu.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/irqs.h> +#include "devices-db8500.h" #include "ste-dma40-db8500.h" static struct resource dma40_resources[] = { @@ -194,3 +196,45 @@ struct platform_device u8500_ske_keypad_device = { .num_resources = ARRAY_SIZE(keypad_resources), .resource = keypad_resources, }; + +struct prcmu_pdata db8500_prcmu_pdata = { + .ab_platdata = &ab8500_platdata, + .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, + .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, +}; + +static struct resource db8500_prcmu_res[] = { + { + .name = "prcmu", + .start = U8500_PRCMU_BASE, + .end = U8500_PRCMU_BASE + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "prcmu-tcdm", + .start = U8500_PRCMU_TCDM_BASE, + .end = U8500_PRCMU_TCDM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "irq", + .start = IRQ_DB8500_PRCMU1, + .end = IRQ_DB8500_PRCMU1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "prcmu-tcpm", + .start = U8500_PRCMU_TCPM_BASE, + .end = U8500_PRCMU_TCPM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device db8500_prcmu_device = { + .name = "db8500-prcmu", + .resource = db8500_prcmu_res, + .num_resources = ARRAY_SIZE(db8500_prcmu_res), + .dev = { + .platform_data = &db8500_prcmu_pdata, + }, +}; diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index a5e05f6e256..dbcb35c48f0 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -14,6 +14,11 @@ struct ske_keypad_platform_data; struct pl022_ssp_controller; +struct platform_device; + +extern struct ab8500_platform_data ab8500_platdata; +extern struct prcmu_pdata db8500_prcmu_pdata; +extern struct platform_device db8500_prcmu_device; static inline struct platform_device * db8500_add_ske_keypad(struct device *parent, diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index d1579920139..9f951842e1e 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -17,6 +17,8 @@ #include <mach/hardware.h> #include <mach/setup.h> +#include "id.h" + struct dbx500_asic_id dbx500_id; static unsigned int ux500_read_asicid(phys_addr_t addr) diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/id.h index 9c42642ab16..bcc58a8cccb 100644 --- a/arch/arm/mach-ux500/include/mach/id.h +++ b/arch/arm/mach-ux500/id.h @@ -61,9 +61,14 @@ static inline bool __attribute_const__ cpu_is_u8540(void) return dbx500_partnumber() == 0x8540; } +static inline bool __attribute_const__ cpu_is_u8580(void) +{ + return dbx500_partnumber() == 0x8580; +} + static inline bool cpu_is_ux540_family(void) { - return cpu_is_u9540() || cpu_is_u8540(); + return cpu_is_u9540() || cpu_is_u8540() || cpu_is_u8580(); } /* @@ -115,6 +120,20 @@ static inline bool cpu_is_u8500v20_or_later(void) return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11()); } +/* + * 8540 revisions + */ + +static inline bool __attribute_const__ cpu_is_u8540v10(void) +{ + return cpu_is_u8540() && dbx500_revision() == 0xA0; +} + +static inline bool __attribute_const__ cpu_is_u8580v10(void) +{ + return cpu_is_u8580() && dbx500_revision() == 0xA0; +} + static inline bool ux500_is_svp(void) { return false; diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 28d16e744bf..5201ddace50 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -39,7 +39,6 @@ #ifndef __ASSEMBLY__ -#include <mach/id.h> extern void __iomem *_PRCMU_BASE; #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index 7d34c52798b..d526dd8e87d 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -38,15 +38,7 @@ #define MOP500_STMPE1601_IRQ_END \ MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) -/* AB8500 virtual gpio IRQ */ -#define AB8500_VIR_GPIO_NR_IRQS 16 - -#define MOP500_AB8500_VIR_GPIO_IRQ_BASE \ - MOP500_STMPE1601_IRQ_END -#define MOP500_AB8500_VIR_GPIO_IRQ_END \ - (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS) - -#define MOP500_NR_IRQS MOP500_AB8500_VIR_GPIO_IRQ_END +#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ_END #define MOP500_IRQ_END MOP500_NR_IRQS diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index 6be4c4d2ab8..bddce2b4937 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -28,8 +28,7 @@ extern struct device *ux500_soc_device_init(const char *soc_id); struct amba_device; extern void __init amba_add_devices(struct amba_device *devs[], int num); -struct sys_timer; -extern struct sys_timer ux500_timer; +extern void ux500_timer_init(void); #define __IO_DEV_DESC(x, sz) { \ .virtual = IO_ADDRESS(x), \ diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index d60ecd1753f..36969d52e53 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -54,6 +54,4 @@ static inline void arch_decomp_setup(void) ux500_uart_base = (void __iomem *)U8500_UART2_BASE; } -#define arch_decomp_wdog() /* nothing to do here */ - #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 3db7782f3af..18f7af339dc 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -16,14 +16,17 @@ #include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> -#include <asm/hardware/gic.h> #include <asm/smp_plat.h> #include <asm/smp_scu.h> + #include <mach/hardware.h> #include <mach/setup.h> +#include "id.h" + /* This is called from headsmp.S to wakeup the secondary core */ extern void u8500_secondary_startup(void); @@ -91,7 +94,7 @@ static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct * */ write_pen_release(cpu_logical_map(cpu)); - smp_send_reschedule(cpu); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -155,8 +158,6 @@ static void __init ux500_smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 875309acb02..a6af0b8732b 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -17,6 +17,8 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#include "id.h" + #ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, U8500_TWD_BASE, IRQ_LOCALTIMER); @@ -46,7 +48,7 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = { { }, }; -static void __init ux500_timer_init(void) +void __init ux500_timer_init(void) { void __iomem *mtu_timer_base; void __iomem *prcmu_timer_base; @@ -99,14 +101,3 @@ dt_fail: clksrc_dbx500_prcmu_init(prcmu_timer_base); ux500_twd_init(); } - -static void ux500_timer_reset(void) -{ - nmdk_clkevt_reset(); - nmdk_clksrc_reset(); -} - -struct sys_timer ux500_timer = { - .init = ux500_timer_init, - .resume = ux500_timer_reset, -}; diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index 63d8e9f81b9..1dba3688275 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -25,4 +25,9 @@ config MACH_VERSATILE_DT Include support for the ARM(R) Versatile/PB platform, using the device tree for discovery +config MACH_VERSATILE_AUTO + def_bool y + depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB + select MACH_VERSATILE_DT + endmenu diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 5d592945036..25160aeaa3b 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -32,15 +32,16 @@ #include <linux/amba/mmci.h> #include <linux/amba/pl022.h> #include <linux/io.h> +#include <linux/irqchip/arm-vic.h> #include <linux/irqchip/versatile-fpga.h> #include <linux/gfp.h> #include <linux/clkdev.h> #include <linux/mtd/physmap.h> +#include <linux/bitops.h> #include <asm/irq.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/icst.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -65,16 +66,28 @@ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) +/* These PIC IRQs are valid in each configuration */ +#define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \ + BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \ + BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \ + BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \ + BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \ + BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \ + BIT(SIC_INT_PCI3) #if 1 #define IRQ_MMCI0A IRQ_VICSOURCE22 #define IRQ_AACI IRQ_VICSOURCE24 #define IRQ_ETH IRQ_VICSOURCE25 #define PIC_MASK 0xFFD00000 +#define PIC_VALID PIC_VALID_ALL #else #define IRQ_MMCI0A IRQ_SIC_MMCI0A #define IRQ_AACI IRQ_SIC_AACI #define IRQ_ETH IRQ_SIC_ETH #define PIC_MASK 0 +#define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \ + BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \ + BIT(SIC_INT_ETH) #endif /* Lookup table for finding a DT node that represents the vic instance */ @@ -102,7 +115,7 @@ void __init versatile_init_irq(void) VERSATILE_SIC_BASE); fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START, - IRQ_VICSOURCE31, ~PIC_MASK, np); + IRQ_VICSOURCE31, PIC_VALID, np); /* * Interrupts on secondary controller from 0 to 8 are routed to @@ -114,7 +127,7 @@ void __init versatile_init_irq(void) writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); } -static struct map_desc versatile_io_desc[] __initdata = { +static struct map_desc versatile_io_desc[] __initdata __maybe_unused = { { .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), .pfn = __phys_to_pfn(VERSATILE_SYS_BASE), @@ -770,7 +783,7 @@ void __init versatile_init(void) /* * Set up timer interrupt, and return the current time in seconds. */ -static void __init versatile_timer_init(void) +void __init versatile_timer_init(void) { u32 val; @@ -797,8 +810,3 @@ static void __init versatile_timer_init(void) sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0"); } - -struct sys_timer versatile_timer = { - .init = versatile_timer_init, -}; - diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h index 683e60776a8..5c1b87d1da6 100644 --- a/arch/arm/mach-versatile/core.h +++ b/arch/arm/mach-versatile/core.h @@ -29,7 +29,7 @@ extern void __init versatile_init(void); extern void __init versatile_init_early(void); extern void __init versatile_init_irq(void); extern void __init versatile_map_io(void); -extern struct sys_timer versatile_timer; +extern void versatile_timer_init(void); extern void versatile_restart(char, const char *); extern unsigned int mmc_status(struct device *dev); #ifdef CONFIG_OF diff --git a/arch/arm/mach-versatile/include/mach/uncompress.h b/arch/arm/mach-versatile/include/mach/uncompress.h index 3dd0048afb3..986e3d303f3 100644 --- a/arch/arm/mach-versatile/include/mach/uncompress.h +++ b/arch/arm/mach-versatile/include/mach/uncompress.h @@ -43,4 +43,3 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c index 2f84f4094f1..e92e5e0705b 100644 --- a/arch/arm/mach-versatile/pci.c +++ b/arch/arm/mach-versatile/pci.c @@ -23,6 +23,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <mach/irqs.h> #include <asm/irq.h> #include <asm/mach/pci.h> @@ -327,12 +328,12 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) int irq; /* slot, pin, irq - * 24 1 27 - * 25 1 28 - * 26 1 29 - * 27 1 30 + * 24 1 IRQ_SIC_PCI0 + * 25 1 IRQ_SIC_PCI1 + * 26 1 IRQ_SIC_PCI2 + * 27 1 IRQ_SIC_PCI3 */ - irq = 27 + ((slot - 24 + pin - 1) & 3); + irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3); return irq; } diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c index 98f65493177..1caef109379 100644 --- a/arch/arm/mach-versatile/versatile_ab.c +++ b/arch/arm/mach-versatile/versatile_ab.c @@ -26,7 +26,6 @@ #include <mach/hardware.h> #include <asm/irq.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -39,8 +38,7 @@ MACHINE_START(VERSATILE_AB, "ARM-Versatile AB") .map_io = versatile_map_io, .init_early = versatile_init_early, .init_irq = versatile_init_irq, - .handle_irq = vic_handle_irq, - .timer = &versatile_timer, + .init_time = versatile_timer_init, .init_machine = versatile_init, .restart = versatile_restart, MACHINE_END diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c index ae5ad3c8f3d..2558f2e957c 100644 --- a/arch/arm/mach-versatile/versatile_dt.c +++ b/arch/arm/mach-versatile/versatile_dt.c @@ -24,7 +24,6 @@ #include <linux/init.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <asm/hardware/vic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -46,8 +45,7 @@ DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)") .map_io = versatile_map_io, .init_early = versatile_init_early, .init_irq = versatile_init_irq, - .handle_irq = vic_handle_irq, - .timer = &versatile_timer, + .init_time = versatile_timer_init, .init_machine = versatile_dt_init, .dt_compat = versatile_dt_match, .restart = versatile_restart, diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c index 19738331bd3..611d140c869 100644 --- a/arch/arm/mach-versatile/versatile_pb.c +++ b/arch/arm/mach-versatile/versatile_pb.c @@ -27,7 +27,6 @@ #include <linux/io.h> #include <mach/hardware.h> -#include <asm/hardware/vic.h> #include <asm/irq.h> #include <asm/mach-types.h> @@ -107,8 +106,7 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB") .map_io = versatile_map_io, .init_early = versatile_init_early, .init_irq = versatile_init_irq, - .handle_irq = vic_handle_irq, - .timer = &versatile_timer, + .init_time = versatile_timer_init, .init_machine = versatile_pb_init, .restart = versatile_restart, MACHINE_END diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 60838ddb856..6f34497a424 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -10,10 +10,10 @@ #include <linux/amba/clcd.h> #include <linux/clkdev.h> #include <linux/vexpress.h> +#include <linux/irqchip/arm-gic.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <asm/smp_twd.h> @@ -182,8 +182,6 @@ static void __init ct_ca9x4_init_cpu_map(void) for (i = 0; i < ncores; ++i) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init ct_ca9x4_smp_enable(unsigned int max_cpus) diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index c5d70de9bb4..dc1ace55d55 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -16,7 +16,6 @@ #include <linux/vexpress.h> #include <asm/smp_scu.h> -#include <asm/hardware/gic.h> #include <asm/mach/map.h> #include <mach/motherboard.h> @@ -128,8 +127,6 @@ static void __init vexpress_dt_smp_init_cpus(void) for (i = 0; i < ncores; ++i) set_cpu_possible(i, true); - - set_smp_cross_call(gic_raise_softirq); } static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 011661a6c5c..915683cb67d 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -7,6 +7,7 @@ #include <linux/io.h> #include <linux/smp.h> #include <linux/init.h> +#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_fdt.h> #include <linux/of_irq.h> @@ -30,7 +31,6 @@ #include <asm/mach/time.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/cache-l2x0.h> -#include <asm/hardware/gic.h> #include <asm/hardware/timer-sp.h> #include <mach/ct-ca9x4.h> @@ -291,10 +291,6 @@ static void __init v2m_timer_init(void) v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0); } -static struct sys_timer v2m_timer = { - .init = v2m_timer_init, -}; - static void __init v2m_init_early(void) { if (ct_desc->init_early) @@ -376,8 +372,7 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express") .map_io = v2m_map_io, .init_early = v2m_init_early, .init_irq = v2m_init_irq, - .timer = &v2m_timer, - .handle_irq = gic_handle_irq, + .init_time = v2m_timer_init, .init_machine = v2m_init, .restart = vexpress_restart, MACHINE_END @@ -434,16 +429,6 @@ void __init v2m_dt_init_early(void) } } -static struct of_device_id vexpress_irq_match[] __initdata = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - {} -}; - -static void __init v2m_dt_init_irq(void) -{ - of_irq_init(vexpress_irq_match); -} - static void __init v2m_dt_timer_init(void) { struct device_node *node = NULL; @@ -468,10 +453,6 @@ static void __init v2m_dt_timer_init(void) 24000000); } -static struct sys_timer v2m_dt_timer = { - .init = v2m_dt_timer_init, -}; - static const struct of_device_id v2m_dt_bus_match[] __initconst = { { .compatible = "simple-bus", }, { .compatible = "arm,amba-bus", }, @@ -497,9 +478,8 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") .smp = smp_ops(vexpress_smp_ops), .map_io = v2m_dt_map_io, .init_early = v2m_dt_init_early, - .init_irq = v2m_dt_init_irq, - .timer = &v2m_dt_timer, + .init_irq = irqchip_init, + .init_time = v2m_dt_timer_init, .init_machine = v2m_dt_init, - .handle_irq = gic_handle_irq, .restart = vexpress_restart, MACHINE_END diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig index 2ed0b7d95db..9adcb9e76f5 100644 --- a/arch/arm/mach-vt8500/Kconfig +++ b/arch/arm/mach-vt8500/Kconfig @@ -4,9 +4,10 @@ config ARCH_VT8500 select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_OF select CPU_ARM926T select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK + select VT8500_TIMER help Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile index e035251cda4..92ceb2436b6 100644 --- a/arch/arm/mach-vt8500/Makefile +++ b/arch/arm/mach-vt8500/Makefile @@ -1 +1 @@ -obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o +obj-$(CONFIG_ARCH_VT8500) += irq.o vt8500.o diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h index 6f2b843115d..77611a6968d 100644 --- a/arch/arm/mach-vt8500/common.h +++ b/arch/arm/mach-vt8500/common.h @@ -18,7 +18,6 @@ #include <linux/of.h> -void __init vt8500_timer_init(void); int __init vt8500_irq_init(struct device_node *node, struct device_node *parent); diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h index e6e81fdaf10..5b4f19ecb4c 100644 --- a/arch/arm/mach-vt8500/include/mach/uncompress.h +++ b/arch/arm/mach-vt8500/include/mach/uncompress.h @@ -34,4 +34,3 @@ static void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c deleted file mode 100644 index 3dd21a47881..00000000000 --- a/arch/arm/mach-vt8500/timer.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * arch/arm/mach-vt8500/timer.c - * - * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * This file is copied and modified from the original timer.c provided by - * Alexey Charkov. Minor changes have been made for Device Tree Support. - */ - -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/delay.h> -#include <asm/mach/time.h> - -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#define VT8500_TIMER_OFFSET 0x0100 -#define VT8500_TIMER_HZ 3000000 -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0010 -#define TIMER_STATUS_VAL 0x0014 -#define TIMER_IER_VAL 0x001c /* interrupt enable */ -#define TIMER_CTRL_VAL 0x0020 -#define TIMER_AS_VAL 0x0024 /* access status */ -#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ -#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ -#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ - -#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) - -static void __iomem *regbase; - -static cycle_t vt8500_timer_read(struct clocksource *cs) -{ - int loops = msecs_to_loops(10); - writel(3, regbase + TIMER_CTRL_VAL); - while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) - && --loops) - cpu_relax(); - return readl(regbase + TIMER_COUNT_VAL); -} - -static struct clocksource clocksource = { - .name = "vt8500_timer", - .rating = 200, - .read = vt8500_timer_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int vt8500_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - int loops = msecs_to_loops(10); - cycle_t alarm = clocksource.read(&clocksource) + cycles; - while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) - && --loops) - cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); - - if ((signed)(alarm - clocksource.read(&clocksource)) <= 16) - return -ETIME; - - writel(1, regbase + TIMER_IER_VAL); - - return 0; -} - -static void vt8500_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - switch (mode) { - case CLOCK_EVT_MODE_RESUME: - case CLOCK_EVT_MODE_PERIODIC: - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - writel(readl(regbase + TIMER_CTRL_VAL) | 1, - regbase + TIMER_CTRL_VAL); - writel(0, regbase + TIMER_IER_VAL); - break; - } -} - -static struct clock_event_device clockevent = { - .name = "vt8500_timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = vt8500_timer_set_next_event, - .set_mode = vt8500_timer_set_mode, -}; - -static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - writel(0xf, regbase + TIMER_STATUS_VAL); - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction irq = { - .name = "vt8500_timer", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = vt8500_timer_interrupt, - .dev_id = &clockevent, -}; - -static struct of_device_id vt8500_timer_ids[] = { - { .compatible = "via,vt8500-timer" }, - { } -}; - -void __init vt8500_timer_init(void) -{ - struct device_node *np; - int timer_irq; - - np = of_find_matching_node(NULL, vt8500_timer_ids); - if (!np) { - pr_err("%s: Timer description missing from Device Tree\n", - __func__); - return; - } - regbase = of_iomap(np, 0); - if (!regbase) { - pr_err("%s: Missing iobase description in Device Tree\n", - __func__); - of_node_put(np); - return; - } - timer_irq = irq_of_parse_and_map(np, 0); - if (!timer_irq) { - pr_err("%s: Missing irq description in Device Tree\n", - __func__); - of_node_put(np); - return; - } - - writel(1, regbase + TIMER_CTRL_VAL); - writel(0xf, regbase + TIMER_STATUS_VAL); - writel(~0, regbase + TIMER_MATCH_VAL); - - if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ)) - pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n", - __func__, clocksource.name); - - clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4); - - /* copy-pasted from mach-msm; no idea */ - clockevent.max_delta_ns = - clockevent_delta2ns(0xf0000000, &clockevent); - clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent); - clockevent.cpumask = cpumask_of(0); - - if (setup_irq(timer_irq, &irq)) - pr_err("%s: setup_irq failed for %s\n", __func__, - clockevent.name); - clockevents_register_device(&clockevent); -} - diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 3c66d48ea08..fe99b709f11 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -18,6 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <linux/clocksource.h> #include <linux/io.h> #include <linux/pm.h> @@ -175,10 +176,6 @@ static void __init vt8500_init_irq(void) of_irq_init(vt8500_irq_match); }; -static struct sys_timer vt8500_timer = { - .init = vt8500_timer_init, -}; - static const char * const vt8500_dt_compat[] = { "via,vt8500", "wm,wm8650", @@ -189,8 +186,8 @@ DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") .dt_compat = vt8500_dt_compat, .map_io = vt8500_map_io, .init_irq = vt8500_init_irq, - .timer = &vt8500_timer, .init_machine = vt8500_init, + .init_time = clocksource_of_init, .restart = vt8500_restart, .handle_irq = vt8500_handle_irq, MACHINE_END diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S index e286daca682..0ff612ac95b 100644 --- a/arch/arm/mach-w90x900/include/mach/entry-macro.S +++ b/arch/arm/mach-w90x900/include/mach/entry-macro.S @@ -19,8 +19,8 @@ mov \base, #AIC_BA - ldr \irqnr, [ \base, #AIC_IPER] - ldr \irqnr, [ \base, #AIC_ISNR] + ldr \irqnr, [\base, #AIC_IPER] + ldr \irqnr, [\base, #AIC_ISNR] cmp \irqnr, #0 .endm diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h index 03130212ace..4b7c324ff66 100644 --- a/arch/arm/mach-w90x900/include/mach/uncompress.h +++ b/arch/arm/mach-w90x900/include/mach/uncompress.h @@ -24,8 +24,6 @@ #include <mach/map.h> #include <linux/serial_reg.h> -#define arch_decomp_wdog() - #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) static volatile u32 * const uart_base = (u32 *)UART0_PA; diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c index b4243e4f156..92f1c978f35 100644 --- a/arch/arm/mach-w90x900/mach-nuc910evb.c +++ b/arch/arm/mach-w90x900/mach-nuc910evb.c @@ -37,6 +37,6 @@ MACHINE_START(W90P910EVB, "W90P910EVB") .map_io = nuc910evb_map_io, .init_irq = nuc900_init_irq, .init_machine = nuc910evb_init, - .timer = &nuc900_timer, + .init_time = nuc900_timer_init, .restart = nuc9xx_restart, MACHINE_END diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c index 500fe5932ce..26f7189056e 100644 --- a/arch/arm/mach-w90x900/mach-nuc950evb.c +++ b/arch/arm/mach-w90x900/mach-nuc950evb.c @@ -40,6 +40,6 @@ MACHINE_START(W90P950EVB, "W90P950EVB") .map_io = nuc950evb_map_io, .init_irq = nuc900_init_irq, .init_machine = nuc950evb_init, - .timer = &nuc900_timer, + .init_time = nuc900_timer_init, .restart = nuc9xx_restart, MACHINE_END diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c index cbb3adc3db1..9b4e73fe10e 100644 --- a/arch/arm/mach-w90x900/mach-nuc960evb.c +++ b/arch/arm/mach-w90x900/mach-nuc960evb.c @@ -37,6 +37,6 @@ MACHINE_START(W90N960EVB, "W90N960EVB") .map_io = nuc960evb_map_io, .init_irq = nuc900_init_irq, .init_machine = nuc960evb_init, - .timer = &nuc900_timer, + .init_time = nuc900_timer_init, .restart = nuc9xx_restart, MACHINE_END diff --git a/arch/arm/mach-w90x900/nuc9xx.h b/arch/arm/mach-w90x900/nuc9xx.h index 91acb404779..88ef4b26708 100644 --- a/arch/arm/mach-w90x900/nuc9xx.h +++ b/arch/arm/mach-w90x900/nuc9xx.h @@ -15,10 +15,9 @@ * */ struct map_desc; -struct sys_timer; /* core initialisation functions */ extern void nuc900_init_irq(void); -extern struct sys_timer nuc900_timer; +extern void nuc900_timer_init(void); extern void nuc9xx_restart(char, const char *); diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index fa27c498ac0..30fbca84457 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c @@ -91,7 +91,6 @@ static int nuc900_clockevent_setnextevent(unsigned long evt, static struct clock_event_device nuc900_clockevent_device = { .name = "nuc900-timer0", - .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = nuc900_clockevent_setmode, .set_next_event = nuc900_clockevent_setnextevent, @@ -133,15 +132,10 @@ static void __init nuc900_clockevents_init(void) __raw_writel(RESETINT, REG_TISR); setup_irq(IRQ_TIMER0, &nuc900_timer0_irq); - nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC, - nuc900_clockevent_device.shift); - nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff, - &nuc900_clockevent_device); - nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf, - &nuc900_clockevent_device); nuc900_clockevent_device.cpumask = cpumask_of(0); - clockevents_register_device(&nuc900_clockevent_device); + clockevents_config_and_register(&nuc900_clockevent_device, rate, + 0xf, 0xffffffff); } static void __init nuc900_clocksource_init(void) @@ -167,12 +161,8 @@ static void __init nuc900_clocksource_init(void) TDR_SHIFT, clocksource_mmio_readl_down); } -static void __init nuc900_timer_init(void) +void __init nuc900_timer_init(void) { nuc900_clocksource_init(); nuc900_clockevents_init(); } - -struct sys_timer nuc900_timer = { - .init = nuc900_timer_init, -}; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index e16d4bed0f7..5c898321818 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -24,6 +24,7 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/of.h> +#include <linux/irqchip.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -31,7 +32,6 @@ #include <asm/mach-types.h> #include <asm/page.h> #include <asm/pgtable.h> -#include <asm/hardware/gic.h> #include <asm/hardware/cache-l2x0.h> #include "common.h" @@ -55,19 +55,6 @@ static void __init xilinx_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } -static struct of_device_id irq_match[] __initdata = { - { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, - { } -}; - -/** - * xilinx_irq_init() - Interrupt controller initialization for the GIC. - */ -static void __init xilinx_irq_init(void) -{ - of_irq_init(irq_match); -} - #define SCU_PERIPH_PHYS 0xF8F00000 #define SCU_PERIPH_SIZE SZ_8K #define SCU_PERIPH_VIRT (VMALLOC_END - SCU_PERIPH_SIZE) @@ -90,16 +77,9 @@ static void __init xilinx_zynq_timer_init(void) xilinx_zynq_clocks_init(slcr); - xttcpss_timer_init(); + xttcps_timer_init(); } -/* - * Instantiate and initialize the system timer structure - */ -static struct sys_timer xttcpss_sys_timer = { - .init = xilinx_zynq_timer_init, -}; - /** * xilinx_map_io() - Create memory mappings needed for early I/O. */ @@ -117,9 +97,8 @@ static const char *xilinx_dt_match[] = { MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") .map_io = xilinx_map_io, - .init_irq = xilinx_irq_init, - .handle_irq = gic_handle_irq, + .init_irq = irqchip_init, .init_machine = xilinx_init_machine, - .timer = &xttcpss_sys_timer, + .init_time = xilinx_zynq_timer_init, .dt_compat = xilinx_dt_match, MACHINE_END diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 954b91c13c9..8b4dbbaa01c 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,6 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -void __init xttcpss_timer_init(void); +void __init xttcps_timer_init(void); #endif diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index de3df283da7..f9fbc9c1e7a 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -15,39 +15,29 @@ * GNU General Public License for more details. */ -#include <linux/kernel.h> -#include <linux/init.h> #include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/types.h> -#include <linux/clocksource.h> #include <linux/clockchips.h> -#include <linux/io.h> -#include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/slab.h> #include <linux/clk-provider.h> - #include "common.h" /* * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 */ -#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ -#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ -#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */ -#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */ -#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */ -#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ -#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ - -#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 - -/* Setup the timers to use pre-scaling, using a fixed value for now that will +#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ + +#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1 + +/* + * Setup the timers to use pre-scaling, using a fixed value for now that will * work across most input frequency, but it may need to be more dynamic */ #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ @@ -57,72 +47,73 @@ #define CNT_CNTRL_RESET (1<<4) /** - * struct xttcpss_timer - This definition defines local timer structure + * struct xttcps_timer - This definition defines local timer structure * * @base_addr: Base address of timer **/ -struct xttcpss_timer { +struct xttcps_timer { void __iomem *base_addr; }; -struct xttcpss_timer_clocksource { - struct xttcpss_timer xttc; +struct xttcps_timer_clocksource { + struct xttcps_timer xttc; struct clocksource cs; }; -#define to_xttcpss_timer_clksrc(x) \ - container_of(x, struct xttcpss_timer_clocksource, cs) +#define to_xttcps_timer_clksrc(x) \ + container_of(x, struct xttcps_timer_clocksource, cs) -struct xttcpss_timer_clockevent { - struct xttcpss_timer xttc; +struct xttcps_timer_clockevent { + struct xttcps_timer xttc; struct clock_event_device ce; struct clk *clk; }; -#define to_xttcpss_timer_clkevent(x) \ - container_of(x, struct xttcpss_timer_clockevent, ce) +#define to_xttcps_timer_clkevent(x) \ + container_of(x, struct xttcps_timer_clockevent, ce) /** - * xttcpss_set_interval - Set the timer interval value + * xttcps_set_interval - Set the timer interval value * * @timer: Pointer to the timer instance * @cycles: Timer interval ticks **/ -static void xttcpss_set_interval(struct xttcpss_timer *timer, +static void xttcps_set_interval(struct xttcps_timer *timer, unsigned long cycles) { u32 ctrl_reg; /* Disable the counter, set the counter value and re-enable counter */ - ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); - ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); - __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET); + __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET); - /* Reset the counter (0x10) so that it starts from 0, one-shot - mode makes this needed for timing to be right. */ + /* + * Reset the counter (0x10) so that it starts from 0, one-shot + * mode makes this needed for timing to be right. + */ ctrl_reg |= CNT_CNTRL_RESET; - ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); } /** - * xttcpss_clock_event_interrupt - Clock event timer interrupt handler + * xttcps_clock_event_interrupt - Clock event timer interrupt handler * * @irq: IRQ number of the Timer - * @dev_id: void pointer to the xttcpss_timer instance + * @dev_id: void pointer to the xttcps_timer instance * * returns: Always IRQ_HANDLED - success **/ -static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) +static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id) { - struct xttcpss_timer_clockevent *xttce = dev_id; - struct xttcpss_timer *timer = &xttce->xttc; + struct xttcps_timer_clockevent *xttce = dev_id; + struct xttcps_timer *timer = &xttce->xttc; /* Acknowledge the interrupt and call event handler */ - __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), - timer->base_addr + XTTCPSS_ISR_OFFSET); + __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET); xttce->ce.event_handler(&xttce->ce); @@ -136,46 +127,46 @@ static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) **/ static cycle_t __xttc_clocksource_read(struct clocksource *cs) { - struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc; + struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc; return (cycle_t)__raw_readl(timer->base_addr + - XTTCPSS_COUNT_VAL_OFFSET); + XTTCPS_COUNT_VAL_OFFSET); } /** - * xttcpss_set_next_event - Sets the time interval for next event + * xttcps_set_next_event - Sets the time interval for next event * * @cycles: Timer interval ticks * @evt: Address of clock event instance * * returns: Always 0 - success **/ -static int xttcpss_set_next_event(unsigned long cycles, +static int xttcps_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); - struct xttcpss_timer *timer = &xttce->xttc; + struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt); + struct xttcps_timer *timer = &xttce->xttc; - xttcpss_set_interval(timer, cycles); + xttcps_set_interval(timer, cycles); return 0; } /** - * xttcpss_set_mode - Sets the mode of timer + * xttcps_set_mode - Sets the mode of timer * * @mode: Mode to be set * @evt: Address of clock event instance **/ -static void xttcpss_set_mode(enum clock_event_mode mode, +static void xttcps_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { - struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt); - struct xttcpss_timer *timer = &xttce->xttc; + struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt); + struct xttcps_timer *timer = &xttce->xttc; u32 ctrl_reg; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - xttcpss_set_interval(timer, + xttcps_set_interval(timer, DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk), PRESCALE * HZ)); break; @@ -183,17 +174,17 @@ static void xttcpss_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: ctrl_reg = __raw_readl(timer->base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, - timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); break; case CLOCK_EVT_MODE_RESUME: ctrl_reg = __raw_readl(timer->base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; __raw_writel(ctrl_reg, - timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); break; } } @@ -201,7 +192,7 @@ static void xttcpss_set_mode(enum clock_event_mode mode, static void __init zynq_ttc_setup_clocksource(struct device_node *np, void __iomem *base) { - struct xttcpss_timer_clocksource *ttccs; + struct xttcps_timer_clocksource *ttccs; struct clk *clk; int err; u32 reg; @@ -230,11 +221,11 @@ static void __init zynq_ttc_setup_clocksource(struct device_node *np, ttccs->cs.mask = CLOCKSOURCE_MASK(16); ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; - __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET); + __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); + ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); __raw_writel(CNT_CNTRL_RESET, - ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE); if (WARN_ON(err)) @@ -244,7 +235,7 @@ static void __init zynq_ttc_setup_clocksource(struct device_node *np, static void __init zynq_ttc_setup_clockevent(struct device_node *np, void __iomem *base) { - struct xttcpss_timer_clockevent *ttcce; + struct xttcps_timer_clockevent *ttcce; int err, irq; u32 reg; @@ -272,17 +263,18 @@ static void __init zynq_ttc_setup_clockevent(struct device_node *np, ttcce->ce.name = np->name; ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - ttcce->ce.set_next_event = xttcpss_set_next_event; - ttcce->ce.set_mode = xttcpss_set_mode; + ttcce->ce.set_next_event = xttcps_set_next_event; + ttcce->ce.set_mode = xttcps_set_mode; ttcce->ce.rating = 200; ttcce->ce.irq = irq; + ttcce->ce.cpumask = cpu_possible_mask; - __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET); + __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET); + ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET); - err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER, + err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER, np->name, ttcce); if (WARN_ON(err)) return; @@ -301,12 +293,12 @@ static const __initconst struct of_device_id zynq_ttc_match[] = { }; /** - * xttcpss_timer_init - Initialize the timer + * xttcps_timer_init - Initialize the timer * * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework **/ -void __init xttcpss_timer_init(void) +void __init xttcps_timer_init(void) { struct device_node *np; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 3fd629d5a51..025d1732873 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -629,8 +629,9 @@ config ARM_THUMBEE make use of it. Say N for code that can run on CPUs without ThumbEE. config ARM_VIRT_EXT - bool "Native support for the ARM Virtualization Extensions" - depends on MMU && CPU_V7 + bool + depends on MMU + default y if CPU_V7 help Enable the kernel to make use of the ARM Virtualization Extensions to install hypervisors without run-time firmware @@ -640,11 +641,6 @@ config ARM_VIRT_EXT use of this feature. Refer to Documentation/arm/Booting for details. - It is safe to enable this option even if the kernel may not be - booted in HYP mode, may not have support for the - virtualization extensions, or may be booted with a - non-compliant bootloader. - config SWP_EMULATE bool "Emulate SWP/SWPB instructions" depends on !CPU_USE_DOMAINS && CPU_V7 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 8a9c4cb50a9..4e333fa2756 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -6,7 +6,7 @@ obj-y := dma-mapping.o extable.o fault.o init.o \ iomap.o obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \ - mmap.o pgd.o mmu.o vmregion.o + mmap.o pgd.o mmu.o ifneq ($(CONFIG_MMU),y) obj-y += nommu.o diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index bc4a5e9ebb7..7a0511191f6 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -34,6 +34,9 @@ * The ASID is used to tag entries in the CPU caches and TLBs. * The context ID is used by debuggers and trace logic, and * should be unique within all running processes. + * + * In big endian operation, the two 32 bit words are swapped if accesed by + * non 64-bit operations. */ #define ASID_FIRST_VERSION (1ULL << ASID_BITS) #define NUM_USER_ASIDS (ASID_FIRST_VERSION - 1) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 076c26d4386..dda3904dc64 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -640,7 +640,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, if (is_coherent || nommu()) addr = __alloc_simple_buffer(dev, size, gfp, &page); - else if (gfp & GFP_ATOMIC) + else if (!(gfp & __GFP_WAIT)) addr = __alloc_from_pool(size, &page); else if (!IS_ENABLED(CONFIG_CMA)) addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c index 99db769307e..2dffc010cc4 100644 --- a/arch/arm/mm/idmap.c +++ b/arch/arm/mm/idmap.c @@ -1,4 +1,6 @@ +#include <linux/module.h> #include <linux/kernel.h> +#include <linux/slab.h> #include <asm/cputype.h> #include <asm/idmap.h> @@ -6,6 +8,7 @@ #include <asm/pgtable.h> #include <asm/sections.h> #include <asm/system_info.h> +#include <asm/virt.h> pgd_t *idmap_pgd; @@ -59,11 +62,17 @@ static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end, } while (pud++, addr = next, addr != end); } -static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end) +static void identity_mapping_add(pgd_t *pgd, const char *text_start, + const char *text_end, unsigned long prot) { - unsigned long prot, next; + unsigned long addr, end; + unsigned long next; + + addr = virt_to_phys(text_start); + end = virt_to_phys(text_end); + + prot |= PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF; - prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF; if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) prot |= PMD_BIT4; @@ -74,28 +83,52 @@ static void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long e } while (pgd++, addr = next, addr != end); } +#if defined(CONFIG_ARM_VIRT_EXT) && defined(CONFIG_ARM_LPAE) +pgd_t *hyp_pgd; + +extern char __hyp_idmap_text_start[], __hyp_idmap_text_end[]; + +static int __init init_static_idmap_hyp(void) +{ + hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); + if (!hyp_pgd) + return -ENOMEM; + + pr_info("Setting up static HYP identity map for 0x%p - 0x%p\n", + __hyp_idmap_text_start, __hyp_idmap_text_end); + identity_mapping_add(hyp_pgd, __hyp_idmap_text_start, + __hyp_idmap_text_end, PMD_SECT_AP1); + + return 0; +} +#else +static int __init init_static_idmap_hyp(void) +{ + return 0; +} +#endif + extern char __idmap_text_start[], __idmap_text_end[]; static int __init init_static_idmap(void) { - phys_addr_t idmap_start, idmap_end; + int ret; idmap_pgd = pgd_alloc(&init_mm); if (!idmap_pgd) return -ENOMEM; - /* Add an identity mapping for the physical address of the section. */ - idmap_start = virt_to_phys((void *)__idmap_text_start); - idmap_end = virt_to_phys((void *)__idmap_text_end); + pr_info("Setting up static identity map for 0x%p - 0x%p\n", + __idmap_text_start, __idmap_text_end); + identity_mapping_add(idmap_pgd, __idmap_text_start, + __idmap_text_end, 0); - pr_info("Setting up static identity map for 0x%llx - 0x%llx\n", - (long long)idmap_start, (long long)idmap_end); - identity_mapping_add(idmap_pgd, idmap_start, idmap_end); + ret = init_static_idmap_hyp(); /* Flush L1 for the hardware to see this page table content */ flush_cache_louis(); - return 0; + return ret; } early_initcall(init_static_idmap); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 88fd86cf3d9..04d9006eab1 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -39,6 +39,70 @@ #include <asm/mach/pci.h> #include "mm.h" + +LIST_HEAD(static_vmlist); + +static struct static_vm *find_static_vm_paddr(phys_addr_t paddr, + size_t size, unsigned int mtype) +{ + struct static_vm *svm; + struct vm_struct *vm; + + list_for_each_entry(svm, &static_vmlist, list) { + vm = &svm->vm; + if (!(vm->flags & VM_ARM_STATIC_MAPPING)) + continue; + if ((vm->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype)) + continue; + + if (vm->phys_addr > paddr || + paddr + size - 1 > vm->phys_addr + vm->size - 1) + continue; + + return svm; + } + + return NULL; +} + +struct static_vm *find_static_vm_vaddr(void *vaddr) +{ + struct static_vm *svm; + struct vm_struct *vm; + + list_for_each_entry(svm, &static_vmlist, list) { + vm = &svm->vm; + + /* static_vmlist is ascending order */ + if (vm->addr > vaddr) + break; + + if (vm->addr <= vaddr && vm->addr + vm->size > vaddr) + return svm; + } + + return NULL; +} + +void __init add_static_vm_early(struct static_vm *svm) +{ + struct static_vm *curr_svm; + struct vm_struct *vm; + void *vaddr; + + vm = &svm->vm; + vm_area_add_early(vm); + vaddr = vm->addr; + + list_for_each_entry(curr_svm, &static_vmlist, list) { + vm = &curr_svm->vm; + + if (vm->addr > vaddr) + break; + } + list_add_tail(&svm->list, &curr_svm->list); +} + int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype) { @@ -197,13 +261,14 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, const struct mem_type *type; int err; unsigned long addr; - struct vm_struct * area; + struct vm_struct *area; + phys_addr_t paddr = __pfn_to_phys(pfn); #ifndef CONFIG_ARM_LPAE /* * High mappings must be supersection aligned */ - if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK)) + if (pfn >= 0x100000 && (paddr & ~SUPERSECTION_MASK)) return NULL; #endif @@ -219,24 +284,16 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, /* * Try to reuse one of the static mapping whenever possible. */ - read_lock(&vmlist_lock); - for (area = vmlist; area; area = area->next) { - if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000)) - break; - if (!(area->flags & VM_ARM_STATIC_MAPPING)) - continue; - if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype)) - continue; - if (__phys_to_pfn(area->phys_addr) > pfn || - __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1) - continue; - /* we can drop the lock here as we know *area is static */ - read_unlock(&vmlist_lock); - addr = (unsigned long)area->addr; - addr += __pfn_to_phys(pfn) - area->phys_addr; - return (void __iomem *) (offset + addr); + if (size && !(sizeof(phys_addr_t) == 4 && pfn >= 0x100000)) { + struct static_vm *svm; + + svm = find_static_vm_paddr(paddr, size, mtype); + if (svm) { + addr = (unsigned long)svm->vm.addr; + addr += paddr - svm->vm.phys_addr; + return (void __iomem *) (offset + addr); + } } - read_unlock(&vmlist_lock); /* * Don't allow RAM to be mapped - this causes problems with ARMv6+ @@ -248,21 +305,21 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, if (!area) return NULL; addr = (unsigned long)area->addr; - area->phys_addr = __pfn_to_phys(pfn); + area->phys_addr = paddr; #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) if (DOMAIN_IO == 0 && (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) || cpu_is_xsc3()) && pfn >= 0x100000 && - !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) { + !((paddr | size | addr) & ~SUPERSECTION_MASK)) { area->flags |= VM_ARM_SECTION_MAPPING; err = remap_area_supersections(addr, pfn, size, type); - } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) { + } else if (!((paddr | size | addr) & ~PMD_MASK)) { area->flags |= VM_ARM_SECTION_MAPPING; err = remap_area_sections(addr, pfn, size, type); } else #endif - err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn), + err = ioremap_page_range(addr, addr + size, paddr, __pgprot(type->prot_pte)); if (err) { @@ -346,34 +403,28 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached) void __iounmap(volatile void __iomem *io_addr) { void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr); - struct vm_struct *vm; + struct static_vm *svm; + + /* If this is a static mapping, we must leave it alone */ + svm = find_static_vm_vaddr(addr); + if (svm) + return; - read_lock(&vmlist_lock); - for (vm = vmlist; vm; vm = vm->next) { - if (vm->addr > addr) - break; - if (!(vm->flags & VM_IOREMAP)) - continue; - /* If this is a static mapping we must leave it alone */ - if ((vm->flags & VM_ARM_STATIC_MAPPING) && - (vm->addr <= addr) && (vm->addr + vm->size > addr)) { - read_unlock(&vmlist_lock); - return; - } #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) + { + struct vm_struct *vm; + + vm = find_vm_area(addr); + /* * If this is a section based mapping we need to handle it * specially as the VM subsystem does not know how to handle * such a beast. */ - if ((vm->addr == addr) && - (vm->flags & VM_ARM_SECTION_MAPPING)) { + if (vm && (vm->flags & VM_ARM_SECTION_MAPPING)) unmap_area_sections((unsigned long)vm->addr, vm->size); - break; - } -#endif } - read_unlock(&vmlist_lock); +#endif vunmap(addr); } diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index a8ee92da354..d5a4e9ad8f0 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -1,4 +1,6 @@ #ifdef CONFIG_MMU +#include <linux/list.h> +#include <linux/vmalloc.h> /* the upper-most page table pointer */ extern pmd_t *top_pmd; @@ -65,6 +67,16 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page /* consistent regions used by dma_alloc_attrs() */ #define VM_ARM_DMA_CONSISTENT 0x20000000 + +struct static_vm { + struct vm_struct vm; + struct list_head list; +}; + +extern struct list_head static_vmlist; +extern struct static_vm *find_static_vm_vaddr(void *vaddr); +extern __init void add_static_vm_early(struct static_vm *svm); + #endif #ifdef CONFIG_ZONE_DMA diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ce328c7f5c9..e95a996ab78 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -57,6 +57,9 @@ static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; static unsigned int ecc_mask __initdata = 0; pgprot_t pgprot_user; pgprot_t pgprot_kernel; +pgprot_t pgprot_hyp_device; +pgprot_t pgprot_s2; +pgprot_t pgprot_s2_device; EXPORT_SYMBOL(pgprot_user); EXPORT_SYMBOL(pgprot_kernel); @@ -66,34 +69,46 @@ struct cachepolicy { unsigned int cr_mask; pmdval_t pmd; pteval_t pte; + pteval_t pte_s2; }; +#ifdef CONFIG_ARM_LPAE +#define s2_policy(policy) policy +#else +#define s2_policy(policy) 0 +#endif + static struct cachepolicy cache_policies[] __initdata = { { .policy = "uncached", .cr_mask = CR_W|CR_C, .pmd = PMD_SECT_UNCACHED, .pte = L_PTE_MT_UNCACHED, + .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), }, { .policy = "buffered", .cr_mask = CR_C, .pmd = PMD_SECT_BUFFERED, .pte = L_PTE_MT_BUFFERABLE, + .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), }, { .policy = "writethrough", .cr_mask = 0, .pmd = PMD_SECT_WT, .pte = L_PTE_MT_WRITETHROUGH, + .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), }, { .policy = "writeback", .cr_mask = 0, .pmd = PMD_SECT_WB, .pte = L_PTE_MT_WRITEBACK, + .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), }, { .policy = "writealloc", .cr_mask = 0, .pmd = PMD_SECT_WBWA, .pte = L_PTE_MT_WRITEALLOC, + .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), } }; @@ -310,6 +325,7 @@ static void __init build_mem_type_table(void) struct cachepolicy *cp; unsigned int cr = get_cr(); pteval_t user_pgprot, kern_pgprot, vecs_pgprot; + pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; int cpu_arch = cpu_architecture(); int i; @@ -421,6 +437,8 @@ static void __init build_mem_type_table(void) */ cp = &cache_policies[cachepolicy]; vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; + s2_pgprot = cp->pte_s2; + hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; /* * ARMv6 and above have extended page tables. @@ -444,6 +462,7 @@ static void __init build_mem_type_table(void) user_pgprot |= L_PTE_SHARED; kern_pgprot |= L_PTE_SHARED; vecs_pgprot |= L_PTE_SHARED; + s2_pgprot |= L_PTE_SHARED; mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; @@ -498,6 +517,9 @@ static void __init build_mem_type_table(void) pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | kern_pgprot); + pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); + pgprot_s2_device = __pgprot(s2_device_pgprot); + pgprot_hyp_device = __pgprot(hyp_device_pgprot); mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; @@ -757,21 +779,24 @@ void __init iotable_init(struct map_desc *io_desc, int nr) { struct map_desc *md; struct vm_struct *vm; + struct static_vm *svm; if (!nr) return; - vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm)); + svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); for (md = io_desc; nr; md++, nr--) { create_mapping(md); + + vm = &svm->vm; vm->addr = (void *)(md->virtual & PAGE_MASK); vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); vm->phys_addr = __pfn_to_phys(md->pfn); vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; vm->flags |= VM_ARM_MTYPE(md->type); vm->caller = iotable_init; - vm_area_add_early(vm++); + add_static_vm_early(svm++); } } @@ -779,13 +804,16 @@ void __init vm_reserve_area_early(unsigned long addr, unsigned long size, void *caller) { struct vm_struct *vm; + struct static_vm *svm; + + svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); - vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); + vm = &svm->vm; vm->addr = (void *)addr; vm->size = size; vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; vm->caller = caller; - vm_area_add_early(vm); + add_static_vm_early(svm); } #ifndef CONFIG_ARM_LPAE @@ -810,14 +838,13 @@ static void __init pmd_empty_section_gap(unsigned long addr) static void __init fill_pmd_gaps(void) { + struct static_vm *svm; struct vm_struct *vm; unsigned long addr, next = 0; pmd_t *pmd; - /* we're still single threaded hence no lock needed here */ - for (vm = vmlist; vm; vm = vm->next) { - if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING))) - continue; + list_for_each_entry(svm, &static_vmlist, list) { + vm = &svm->vm; addr = (unsigned long)vm->addr; if (addr < next) continue; @@ -857,19 +884,12 @@ static void __init fill_pmd_gaps(void) #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) static void __init pci_reserve_io(void) { - struct vm_struct *vm; - unsigned long addr; + struct static_vm *svm; - /* we're still single threaded hence no lock needed here */ - for (vm = vmlist; vm; vm = vm->next) { - if (!(vm->flags & VM_ARM_STATIC_MAPPING)) - continue; - addr = (unsigned long)vm->addr; - addr &= ~(SZ_2M - 1); - if (addr == PCI_IO_VIRT_BASE) - return; + svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); + if (svm) + return; - } vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); } #else diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index eb6aa73bc8b..f9a0aa725ea 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -38,9 +38,14 @@ /* * mmid - get context id from mm pointer (mm->context.id) + * note, this field is 64bit, so in big-endian the two words are swapped too. */ .macro mmid, rd, rn +#ifdef __ARMEB__ + ldr \rd, [\rn, #MM_CONTEXT_ID + 4 ] +#else ldr \rd, [\rn, #MM_CONTEXT_ID] +#endif .endm /* diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 09c5233f4df..bcaaa8de932 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -101,7 +101,7 @@ ENTRY(cpu_v6_dcache_clean_area) ENTRY(cpu_v6_switch_mm) #ifdef CONFIG_MMU mov r2, #0 - ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mmid r1, r1 @ get mm->context.id ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 6d98c13ab82..78f520bc0e9 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -40,7 +40,7 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mov r2, #0 - ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mmid r1, r1 @ get mm->context.id ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 7b56386f949..50bf1dafc9e 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -47,7 +47,7 @@ */ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU - ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mmid r1, r1 @ get mm->context.id and r3, r1, #0xff mov r3, r3, lsl #(48 - 32) @ ASID mcrr p15, 0, r0, r3, c2 @ set TTB 0 diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c deleted file mode 100644 index a631016e1f8..00000000000 --- a/arch/arm/mm/vmregion.c +++ /dev/null @@ -1,205 +0,0 @@ -#include <linux/fs.h> -#include <linux/spinlock.h> -#include <linux/list.h> -#include <linux/proc_fs.h> -#include <linux/seq_file.h> -#include <linux/slab.h> - -#include "vmregion.h" - -/* - * VM region handling support. - * - * This should become something generic, handling VM region allocations for - * vmalloc and similar (ioremap, module space, etc). - * - * I envisage vmalloc()'s supporting vm_struct becoming: - * - * struct vm_struct { - * struct vmregion region; - * unsigned long flags; - * struct page **pages; - * unsigned int nr_pages; - * unsigned long phys_addr; - * }; - * - * get_vm_area() would then call vmregion_alloc with an appropriate - * struct vmregion head (eg): - * - * struct vmregion vmalloc_head = { - * .vm_list = LIST_HEAD_INIT(vmalloc_head.vm_list), - * .vm_start = VMALLOC_START, - * .vm_end = VMALLOC_END, - * }; - * - * However, vmalloc_head.vm_start is variable (typically, it is dependent on - * the amount of RAM found at boot time.) I would imagine that get_vm_area() - * would have to initialise this each time prior to calling vmregion_alloc(). - */ - -struct arm_vmregion * -arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align, - size_t size, gfp_t gfp, const void *caller) -{ - unsigned long start = head->vm_start, addr = head->vm_end; - unsigned long flags; - struct arm_vmregion *c, *new; - - if (head->vm_end - head->vm_start < size) { - printk(KERN_WARNING "%s: allocation too big (requested %#x)\n", - __func__, size); - goto out; - } - - new = kmalloc(sizeof(struct arm_vmregion), gfp); - if (!new) - goto out; - - new->caller = caller; - - spin_lock_irqsave(&head->vm_lock, flags); - - addr = rounddown(addr - size, align); - list_for_each_entry_reverse(c, &head->vm_list, vm_list) { - if (addr >= c->vm_end) - goto found; - addr = rounddown(c->vm_start - size, align); - if (addr < start) - goto nospc; - } - - found: - /* - * Insert this entry after the one we found. - */ - list_add(&new->vm_list, &c->vm_list); - new->vm_start = addr; - new->vm_end = addr + size; - new->vm_active = 1; - - spin_unlock_irqrestore(&head->vm_lock, flags); - return new; - - nospc: - spin_unlock_irqrestore(&head->vm_lock, flags); - kfree(new); - out: - return NULL; -} - -static struct arm_vmregion *__arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr) -{ - struct arm_vmregion *c; - - list_for_each_entry(c, &head->vm_list, vm_list) { - if (c->vm_active && c->vm_start == addr) - goto out; - } - c = NULL; - out: - return c; -} - -struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *head, unsigned long addr) -{ - struct arm_vmregion *c; - unsigned long flags; - - spin_lock_irqsave(&head->vm_lock, flags); - c = __arm_vmregion_find(head, addr); - spin_unlock_irqrestore(&head->vm_lock, flags); - return c; -} - -struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *head, unsigned long addr) -{ - struct arm_vmregion *c; - unsigned long flags; - - spin_lock_irqsave(&head->vm_lock, flags); - c = __arm_vmregion_find(head, addr); - if (c) - c->vm_active = 0; - spin_unlock_irqrestore(&head->vm_lock, flags); - return c; -} - -void arm_vmregion_free(struct arm_vmregion_head *head, struct arm_vmregion *c) -{ - unsigned long flags; - - spin_lock_irqsave(&head->vm_lock, flags); - list_del(&c->vm_list); - spin_unlock_irqrestore(&head->vm_lock, flags); - - kfree(c); -} - -#ifdef CONFIG_PROC_FS -static int arm_vmregion_show(struct seq_file *m, void *p) -{ - struct arm_vmregion *c = list_entry(p, struct arm_vmregion, vm_list); - - seq_printf(m, "0x%08lx-0x%08lx %7lu", c->vm_start, c->vm_end, - c->vm_end - c->vm_start); - if (c->caller) - seq_printf(m, " %pS", (void *)c->caller); - seq_putc(m, '\n'); - return 0; -} - -static void *arm_vmregion_start(struct seq_file *m, loff_t *pos) -{ - struct arm_vmregion_head *h = m->private; - spin_lock_irq(&h->vm_lock); - return seq_list_start(&h->vm_list, *pos); -} - -static void *arm_vmregion_next(struct seq_file *m, void *p, loff_t *pos) -{ - struct arm_vmregion_head *h = m->private; - return seq_list_next(p, &h->vm_list, pos); -} - -static void arm_vmregion_stop(struct seq_file *m, void *p) -{ - struct arm_vmregion_head *h = m->private; - spin_unlock_irq(&h->vm_lock); -} - -static const struct seq_operations arm_vmregion_ops = { - .start = arm_vmregion_start, - .stop = arm_vmregion_stop, - .next = arm_vmregion_next, - .show = arm_vmregion_show, -}; - -static int arm_vmregion_open(struct inode *inode, struct file *file) -{ - struct arm_vmregion_head *h = PDE(inode)->data; - int ret = seq_open(file, &arm_vmregion_ops); - if (!ret) { - struct seq_file *m = file->private_data; - m->private = h; - } - return ret; -} - -static const struct file_operations arm_vmregion_fops = { - .open = arm_vmregion_open, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release, -}; - -int arm_vmregion_create_proc(const char *path, struct arm_vmregion_head *h) -{ - proc_create_data(path, S_IRUSR, NULL, &arm_vmregion_fops, h); - return 0; -} -#else -int arm_vmregion_create_proc(const char *path, struct arm_vmregion_head *h) -{ - return 0; -} -#endif diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h deleted file mode 100644 index 0f5a5f2a2c7..00000000000 --- a/arch/arm/mm/vmregion.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef VMREGION_H -#define VMREGION_H - -#include <linux/spinlock.h> -#include <linux/list.h> - -struct page; - -struct arm_vmregion_head { - spinlock_t vm_lock; - struct list_head vm_list; - unsigned long vm_start; - unsigned long vm_end; -}; - -struct arm_vmregion { - struct list_head vm_list; - unsigned long vm_start; - unsigned long vm_end; - int vm_active; - const void *caller; -}; - -struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t, const void *); -struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long); -struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long); -void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *); - -int arm_vmregion_create_proc(const char *, struct arm_vmregion_head *); - -#endif diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index a34f1e21411..6828ef6ce80 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -341,10 +341,17 @@ static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx) static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx) { - emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx); - emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx); - emit(ARM_LSL_I(r_dst, r_dst, 8), ctx); - emit(ARM_LSL_R(r_dst, r_dst, 8), ctx); + /* r_dst = (r_src << 8) | (r_src >> 8) */ + emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx); + emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx); + + /* + * we need to mask out the bits set in r_dst[23:16] due to + * the first shift instruction. + * + * note that 0x8ff is the encoded immediate 0x00ff0000. + */ + emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx); } #else /* ARMv6+ */ diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index cbfbbe46178..837a2d52e9d 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -156,14 +156,9 @@ void __init iop_init_time(unsigned long tick_rate) write_tmr0(timer_ctl & ~IOP_TMR_EN); write_tisr(1); setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); - clockevents_calc_mult_shift(&iop_clockevent, - tick_rate, IOP_MIN_RANGE); - iop_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &iop_clockevent); - iop_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &iop_clockevent); iop_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&iop_clockevent); + clockevents_config_and_register(&iop_clockevent, tick_rate, + 0xf, 0xfffffffe); /* * Set up free-running clocksource timer 1. diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 4136b20cba3..e06c34bdc34 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -2019,7 +2019,7 @@ static int omap_system_dma_probe(struct platform_device *pdev) errata = p->errata; if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels - && (omap_dma_reserve_channels <= dma_lch_count)) + && (omap_dma_reserve_channels < d->lch_count)) d->lch_count = omap_dma_reserve_channels; dma_lch_count = d->lch_count; diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 7b433f3bddc..a0daa2fb5de 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -808,11 +808,9 @@ static int omap_dm_timer_probe(struct platform_device *pdev) return -ENOMEM; } - timer->io_base = devm_request_and_ioremap(dev, mem); - if (!timer->io_base) { - dev_err(dev, "%s: region already claimed.\n", __func__); - return -ENOMEM; - } + timer->io_base = devm_ioremap_resource(dev, mem); + if (IS_ERR(timer->io_base)) + return PTR_ERR(timer->io_base); if (dev->of_node) { if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index e686fe76a96..7310bcfb299 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -49,7 +49,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, "number (%u)\n", num); continue; } - if (variant_mask & !(*mpp_list & variant_mask)) { + if (variant_mask && !(*mpp_list & variant_mask)) { printk(KERN_WARNING "orion_mpp_conf: requested MPP%u config " "unavailable on this hardware\n", num); diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 0f4fa863dd5..5d5ac0f0542 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -156,7 +156,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) static struct clock_event_device orion_clkevt = { .name = "orion_tick", .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .shift = 32, .rating = 300, .set_next_event = orion_clkevt_next_event, .set_mode = orion_clkevt_mode, @@ -221,9 +220,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, * Setup clockevent timer (interrupt-driven). */ setup_irq(irq, &orion_timer_irq); - orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); orion_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&orion_clkevt); + clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); } diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig deleted file mode 100644 index eef3b6a2f8a..00000000000 --- a/arch/arm/plat-s3c24xx/Kconfig +++ /dev/null @@ -1,116 +0,0 @@ -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -config PLAT_S3C24XX - bool - depends on ARCH_S3C24XX - default y - select ARCH_REQUIRE_GPIOLIB - select NO_IOPORT - select S3C_DEV_NAND - help - Base platform code for any Samsung S3C24XX device - -if PLAT_S3C24XX - -# low-level serial option nodes - -config CPU_LLSERIAL_S3C2410_ONLY - bool - default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 - -config CPU_LLSERIAL_S3C2440_ONLY - bool - default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 - -config CPU_LLSERIAL_S3C2410 - bool - help - Selected if there is an S3C2410 (or register compatible) serial - low-level implementation needed - -config CPU_LLSERIAL_S3C2440 - bool - help - Selected if there is an S3C2440 (or register compatible) serial - low-level implementation needed - -# code that is shared between a number of the s3c24xx implementations - -config S3C2410_CLOCK - bool - help - Clock code for the S3C2410, and similar processors which - is currently includes the S3C2410, S3C2440, S3C2442. - -config S3C24XX_DCLK - bool - help - Clock code for supporting DCLK/CLKOUT on S3C24XX architectures - -# gpio configurations - -config S3C24XX_GPIO_EXTRA - int - default 128 if S3C24XX_GPIO_EXTRA128 - default 64 if S3C24XX_GPIO_EXTRA64 - default 16 if ARCH_H1940 - default 0 - -config S3C24XX_GPIO_EXTRA64 - bool - help - Add an extra 64 gpio numbers to the available GPIO pool. This is - available for boards that need extra gpios for external devices. - -config S3C24XX_GPIO_EXTRA128 - bool - help - Add an extra 128 gpio numbers to the available GPIO pool. This is - available for boards that need extra gpios for external devices. - -config S3C24XX_DMA - bool "S3C2410 DMA support" - depends on ARCH_S3C24XX - select S3C_DMA - help - S3C2410 DMA support. This is needed for drivers like sound which - use the S3C2410's DMA system to move data to and from the - peripheral blocks. - -config S3C2410_DMA_DEBUG - bool "S3C2410 DMA support debug" - depends on ARCH_S3C24XX && S3C2410_DMA - help - Enable debugging output for the DMA code. This option sends info - to the kernel log, at priority KERN_DEBUG. - -# common code for s3c24xx based machines, such as the SMDKs. - -# cpu frequency items common between s3c2410 and s3c2440/s3c2442 - -config S3C2410_IOTIMING - bool - depends on CPU_FREQ_S3C24XX - help - Internal node to select io timing code that is common to the s3c2410 - and s3c2440/s3c2442 cpu frequency support. - -config S3C2410_CPUFREQ_UTILS - bool - depends on CPU_FREQ_S3C24XX - help - Internal node to select timing code that is common to the s3c2410 - and s3c2440/s3c244 cpu frequency support. - -# cpu frequency support common to s3c2412, s3c2413 and s3c2442 - -config S3C2412_IOTIMING - bool - depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) - help - Intel node to select io timing code that is common to the s3c2412 - and the s3c2443. - -endif diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile deleted file mode 100644 index 9f60549c8da..00000000000 --- a/arch/arm/plat-s3c24xx/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# arch/arm/plat-s3c24xx/Makefile -# -# Copyright 2007 Simtec Electronics -# -# Licensed under GPLv2 - -obj-y := -obj-m := -obj-n := -obj- := - - -# Core files - -obj-y += irq.o -obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o - -obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o -obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o - -# Architecture dependent builds - -obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o -obj-$(CONFIG_S3C24XX_DMA) += dma.o -obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o -obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o -obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c deleted file mode 100644 index fe57bbbf166..00000000000 --- a/arch/arm/plat-s3c24xx/irq.c +++ /dev/null @@ -1,676 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/irq.c - * - * Copyright (c) 2003-2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/device.h> -#include <linux/syscore_ops.h> - -#include <asm/irq.h> -#include <asm/mach/irq.h> - -#include <plat/regs-irqtype.h> - -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/irq.h> - -static void -s3c_irq_mask(struct irq_data *data) -{ - unsigned int irqno = data->irq - IRQ_EINT0; - unsigned long mask; - - mask = __raw_readl(S3C2410_INTMSK); - mask |= 1UL << irqno; - __raw_writel(mask, S3C2410_INTMSK); -} - -static inline void -s3c_irq_ack(struct irq_data *data) -{ - unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); - - __raw_writel(bitval, S3C2410_SRCPND); - __raw_writel(bitval, S3C2410_INTPND); -} - -static inline void -s3c_irq_maskack(struct irq_data *data) -{ - unsigned long bitval = 1UL << (data->irq - IRQ_EINT0); - unsigned long mask; - - mask = __raw_readl(S3C2410_INTMSK); - __raw_writel(mask|bitval, S3C2410_INTMSK); - - __raw_writel(bitval, S3C2410_SRCPND); - __raw_writel(bitval, S3C2410_INTPND); -} - - -static void -s3c_irq_unmask(struct irq_data *data) -{ - unsigned int irqno = data->irq; - unsigned long mask; - - if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) - irqdbf2("s3c_irq_unmask %d\n", irqno); - - irqno -= IRQ_EINT0; - - mask = __raw_readl(S3C2410_INTMSK); - mask &= ~(1UL << irqno); - __raw_writel(mask, S3C2410_INTMSK); -} - -struct irq_chip s3c_irq_level_chip = { - .name = "s3c-level", - .irq_ack = s3c_irq_maskack, - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_set_wake = s3c_irq_wake -}; - -struct irq_chip s3c_irq_chip = { - .name = "s3c", - .irq_ack = s3c_irq_ack, - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_set_wake = s3c_irq_wake -}; - -static void -s3c_irqext_mask(struct irq_data *data) -{ - unsigned int irqno = data->irq - EXTINT_OFF; - unsigned long mask; - - mask = __raw_readl(S3C24XX_EINTMASK); - mask |= ( 1UL << irqno); - __raw_writel(mask, S3C24XX_EINTMASK); -} - -static void -s3c_irqext_ack(struct irq_data *data) -{ - unsigned long req; - unsigned long bit; - unsigned long mask; - - bit = 1UL << (data->irq - EXTINT_OFF); - - mask = __raw_readl(S3C24XX_EINTMASK); - - __raw_writel(bit, S3C24XX_EINTPEND); - - req = __raw_readl(S3C24XX_EINTPEND); - req &= ~mask; - - /* not sure if we should be acking the parent irq... */ - - if (data->irq <= IRQ_EINT7) { - if ((req & 0xf0) == 0) - s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7)); - } else { - if ((req >> 8) == 0) - s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23)); - } -} - -static void -s3c_irqext_unmask(struct irq_data *data) -{ - unsigned int irqno = data->irq - EXTINT_OFF; - unsigned long mask; - - mask = __raw_readl(S3C24XX_EINTMASK); - mask &= ~(1UL << irqno); - __raw_writel(mask, S3C24XX_EINTMASK); -} - -int -s3c_irqext_type(struct irq_data *data, unsigned int type) -{ - void __iomem *extint_reg; - void __iomem *gpcon_reg; - unsigned long gpcon_offset, extint_offset; - unsigned long newvalue = 0, value; - - if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) { - gpcon_reg = S3C2410_GPFCON; - extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (data->irq - IRQ_EINT0) * 2; - extint_offset = (data->irq - IRQ_EINT0) * 4; - } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) { - gpcon_reg = S3C2410_GPFCON; - extint_reg = S3C24XX_EXTINT0; - gpcon_offset = (data->irq - (EXTINT_OFF)) * 2; - extint_offset = (data->irq - (EXTINT_OFF)) * 4; - } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) { - gpcon_reg = S3C2410_GPGCON; - extint_reg = S3C24XX_EXTINT1; - gpcon_offset = (data->irq - IRQ_EINT8) * 2; - extint_offset = (data->irq - IRQ_EINT8) * 4; - } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) { - gpcon_reg = S3C2410_GPGCON; - extint_reg = S3C24XX_EXTINT2; - gpcon_offset = (data->irq - IRQ_EINT8) * 2; - extint_offset = (data->irq - IRQ_EINT16) * 4; - } else { - return -1; - } - - /* Set the GPIO to external interrupt mode */ - value = __raw_readl(gpcon_reg); - value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); - __raw_writel(value, gpcon_reg); - - /* Set the external interrupt to pointed trigger type */ - switch (type) - { - case IRQ_TYPE_NONE: - printk(KERN_WARNING "No edge setting!\n"); - break; - - case IRQ_TYPE_EDGE_RISING: - newvalue = S3C2410_EXTINT_RISEEDGE; - break; - - case IRQ_TYPE_EDGE_FALLING: - newvalue = S3C2410_EXTINT_FALLEDGE; - break; - - case IRQ_TYPE_EDGE_BOTH: - newvalue = S3C2410_EXTINT_BOTHEDGE; - break; - - case IRQ_TYPE_LEVEL_LOW: - newvalue = S3C2410_EXTINT_LOWLEV; - break; - - case IRQ_TYPE_LEVEL_HIGH: - newvalue = S3C2410_EXTINT_HILEV; - break; - - default: - printk(KERN_ERR "No such irq type %d", type); - return -1; - } - - value = __raw_readl(extint_reg); - value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); - __raw_writel(value, extint_reg); - - return 0; -} - -static struct irq_chip s3c_irqext_chip = { - .name = "s3c-ext", - .irq_mask = s3c_irqext_mask, - .irq_unmask = s3c_irqext_unmask, - .irq_ack = s3c_irqext_ack, - .irq_set_type = s3c_irqext_type, - .irq_set_wake = s3c_irqext_wake -}; - -static struct irq_chip s3c_irq_eint0t4 = { - .name = "s3c-ext0", - .irq_ack = s3c_irq_ack, - .irq_mask = s3c_irq_mask, - .irq_unmask = s3c_irq_unmask, - .irq_set_wake = s3c_irq_wake, - .irq_set_type = s3c_irqext_type, -}; - -/* mask values for the parent registers for each of the interrupt types */ - -#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0)) -#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0)) -#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) -#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) - - -/* UART0 */ - -static void -s3c_irq_uart0_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_UART0, 7); -} - -static void -s3c_irq_uart0_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_UART0); -} - -static void -s3c_irq_uart0_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7); -} - -static struct irq_chip s3c_irq_uart0 = { - .name = "s3c-uart0", - .irq_mask = s3c_irq_uart0_mask, - .irq_unmask = s3c_irq_uart0_unmask, - .irq_ack = s3c_irq_uart0_ack, -}; - -/* UART1 */ - -static void -s3c_irq_uart1_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3); -} - -static void -s3c_irq_uart1_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_UART1); -} - -static void -s3c_irq_uart1_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3); -} - -static struct irq_chip s3c_irq_uart1 = { - .name = "s3c-uart1", - .irq_mask = s3c_irq_uart1_mask, - .irq_unmask = s3c_irq_uart1_unmask, - .irq_ack = s3c_irq_uart1_ack, -}; - -/* UART2 */ - -static void -s3c_irq_uart2_mask(struct irq_data *data) -{ - s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6); -} - -static void -s3c_irq_uart2_unmask(struct irq_data *data) -{ - s3c_irqsub_unmask(data->irq, INTMSK_UART2); -} - -static void -s3c_irq_uart2_ack(struct irq_data *data) -{ - s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6); -} - -static struct irq_chip s3c_irq_uart2 = { - .name = "s3c-uart2", - .irq_mask = s3c_irq_uart2_mask, - .irq_unmask = s3c_irq_uart2_unmask, - .irq_ack = s3c_irq_uart2_ack, -}; - -/* ADC and Touchscreen */ - -static void -s3c_irq_adc_mask(struct irq_data *d) -{ - s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9); -} - -static void -s3c_irq_adc_unmask(struct irq_data *d) -{ - s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT); -} - -static void -s3c_irq_adc_ack(struct irq_data *d) -{ - s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9); -} - -static struct irq_chip s3c_irq_adc = { - .name = "s3c-adc", - .irq_mask = s3c_irq_adc_mask, - .irq_unmask = s3c_irq_adc_unmask, - .irq_ack = s3c_irq_adc_ack, -}; - -/* irq demux for adc */ -static void s3c_irq_demux_adc(unsigned int irq, - struct irq_desc *desc) -{ - unsigned int subsrc, submsk; - unsigned int offset = 9; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - subsrc &= ~submsk; - subsrc >>= offset; - subsrc &= 3; - - if (subsrc != 0) { - if (subsrc & 1) { - generic_handle_irq(IRQ_TC); - } - if (subsrc & 2) { - generic_handle_irq(IRQ_ADC); - } - } -} - -static void s3c_irq_demux_uart(unsigned int start) -{ - unsigned int subsrc, submsk; - unsigned int offset = start - IRQ_S3CUART_RX0; - - /* read the current pending interrupts, and the mask - * for what it is available */ - - subsrc = __raw_readl(S3C2410_SUBSRCPND); - submsk = __raw_readl(S3C2410_INTSUBMSK); - - irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n", - start, offset, subsrc, submsk); - - subsrc &= ~submsk; - subsrc >>= offset; - subsrc &= 7; - - if (subsrc != 0) { - if (subsrc & 1) - generic_handle_irq(start); - - if (subsrc & 2) - generic_handle_irq(start+1); - - if (subsrc & 4) - generic_handle_irq(start+2); - } -} - -/* uart demux entry points */ - -static void -s3c_irq_demux_uart0(unsigned int irq, - struct irq_desc *desc) -{ - irq = irq; - s3c_irq_demux_uart(IRQ_S3CUART_RX0); -} - -static void -s3c_irq_demux_uart1(unsigned int irq, - struct irq_desc *desc) -{ - irq = irq; - s3c_irq_demux_uart(IRQ_S3CUART_RX1); -} - -static void -s3c_irq_demux_uart2(unsigned int irq, - struct irq_desc *desc) -{ - irq = irq; - s3c_irq_demux_uart(IRQ_S3CUART_RX2); -} - -static void -s3c_irq_demux_extint8(unsigned int irq, - struct irq_desc *desc) -{ - unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); - unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); - - eintpnd &= ~eintmsk; - eintpnd &= ~0xff; /* ignore lower irqs */ - - /* we may as well handle all the pending IRQs here */ - - while (eintpnd) { - irq = __ffs(eintpnd); - eintpnd &= ~(1<<irq); - - irq += (IRQ_EINT4 - 4); - generic_handle_irq(irq); - } - -} - -static void -s3c_irq_demux_extint4t7(unsigned int irq, - struct irq_desc *desc) -{ - unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); - unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); - - eintpnd &= ~eintmsk; - eintpnd &= 0xff; /* only lower irqs */ - - /* we may as well handle all the pending IRQs here */ - - while (eintpnd) { - irq = __ffs(eintpnd); - eintpnd &= ~(1<<irq); - - irq += (IRQ_EINT4 - 4); - - generic_handle_irq(irq); - } -} - -#ifdef CONFIG_FIQ -/** - * s3c24xx_set_fiq - set the FIQ routing - * @irq: IRQ number to route to FIQ on processor. - * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. - * - * Change the state of the IRQ to FIQ routing depending on @irq and @on. If - * @on is true, the @irq is checked to see if it can be routed and the - * interrupt controller updated to route the IRQ. If @on is false, the FIQ - * routing is cleared, regardless of which @irq is specified. - */ -int s3c24xx_set_fiq(unsigned int irq, bool on) -{ - u32 intmod; - unsigned offs; - - if (on) { - offs = irq - FIQ_START; - if (offs > 31) - return -EINVAL; - - intmod = 1 << offs; - } else { - intmod = 0; - } - - __raw_writel(intmod, S3C2410_INTMOD); - return 0; -} - -EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); -#endif - - -/* s3c24xx_init_irq - * - * Initialise S3C2410 IRQ system -*/ - -void __init s3c24xx_init_irq(void) -{ - unsigned long pend; - unsigned long last; - int irqno; - int i; - -#ifdef CONFIG_FIQ - init_FIQ(FIQ_START); -#endif - - irqdbf("s3c2410_init_irq: clearing interrupt status flags\n"); - - /* first, clear all interrupts pending... */ - - last = 0; - for (i = 0; i < 4; i++) { - pend = __raw_readl(S3C24XX_EINTPEND); - - if (pend == 0 || pend == last) - break; - - __raw_writel(pend, S3C24XX_EINTPEND); - printk("irq: clearing pending ext status %08x\n", (int)pend); - last = pend; - } - - last = 0; - for (i = 0; i < 4; i++) { - pend = __raw_readl(S3C2410_INTPND); - - if (pend == 0 || pend == last) - break; - - __raw_writel(pend, S3C2410_SRCPND); - __raw_writel(pend, S3C2410_INTPND); - printk("irq: clearing pending status %08x\n", (int)pend); - last = pend; - } - - last = 0; - for (i = 0; i < 4; i++) { - pend = __raw_readl(S3C2410_SUBSRCPND); - - if (pend == 0 || pend == last) - break; - - printk("irq: clearing subpending status %08x\n", (int)pend); - __raw_writel(pend, S3C2410_SUBSRCPND); - last = pend; - } - - /* register the main interrupts */ - - irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n"); - - for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) { - /* set all the s3c2410 internal irqs */ - - switch (irqno) { - /* deal with the special IRQs (cascaded) */ - - case IRQ_EINT4t7: - case IRQ_EINT8t23: - case IRQ_UART0: - case IRQ_UART1: - case IRQ_UART2: - case IRQ_ADCPARENT: - irq_set_chip_and_handler(irqno, &s3c_irq_level_chip, - handle_level_irq); - break; - - case IRQ_RESERVED6: - case IRQ_RESERVED24: - /* no IRQ here */ - break; - - default: - //irqdbf("registering irq %d (s3c irq)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irq_chip, - handle_edge_irq); - set_irq_flags(irqno, IRQF_VALID); - } - } - - /* setup the cascade irq handlers */ - - irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); - irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); - - irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); - irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); - irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); - irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); - - /* external interrupts */ - - for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { - irqdbf("registering irq %d (ext int)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4, - handle_edge_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { - irqdbf("registering irq %d (extended s3c irq)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irqext_chip, - handle_edge_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - /* register the uart interrupts */ - - irqdbf("s3c2410: registering external interrupts\n"); - - for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { - irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irq_uart0, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { - irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irq_uart1, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { - irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irq_uart2, - handle_level_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { - irqdbf("registering irq %d (s3c adc irq)\n", irqno); - irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq); - set_irq_flags(irqno, IRQF_VALID); - } - - irqdbf("s3c2410: registered interrupt handlers\n"); -} - -struct syscore_ops s3c24xx_irq_syscore_ops = { - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 2d676ab50f7..ca07cb1b155 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -386,11 +386,9 @@ static int s3c_adc_probe(struct platform_device *pdev) return -ENXIO; } - adc->regs = devm_request_and_ioremap(dev, regs); - if (!adc->regs) { - dev_err(dev, "failed to map registers\n"); - return -ENXIO; - } + adc->regs = devm_ioremap_resource(dev, regs); + if (IS_ERR(adc->regs)) + return PTR_ERR(adc->regs); ret = regulator_enable(adc->vdd); if (ret) diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index d088afa034e..71d58ddea9c 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c @@ -19,7 +19,8 @@ #include <mach/dma.h> static unsigned samsung_dmadev_request(enum dma_ch dma_ch, - struct samsung_dma_req *param) + struct samsung_dma_req *param, + struct device *dev, char *ch_name) { dma_cap_mask_t mask; void *filter_param; @@ -33,7 +34,12 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch, */ filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)param->dt_dmach_prop : (void *)dma_ch; - return (unsigned)dma_request_channel(mask, pl330_filter, filter_param); + + if (dev->of_node) + return (unsigned)dma_request_slave_channel(dev, ch_name); + else + return (unsigned)dma_request_channel(mask, pl330_filter, + filter_param); } static int samsung_dmadev_release(unsigned ch, void *param) diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index b258a08de59..2fc89315553 100644 --- a/arch/arm/plat-samsung/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -15,6 +15,7 @@ #define __ASM_PLAT_ADC_H __FILE__ struct s3c_adc_client; +struct platform_device; extern int s3c_adc_start(struct s3c_adc_client *client, unsigned int channel, unsigned int nr_samples); diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index b69e11dc679..37703ef6dfc 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -194,8 +194,7 @@ extern void s3c24xx_init_uartdevs(char *name, /* timer for 2410/2440 */ -struct sys_timer; -extern struct sys_timer s3c24xx_timer; +extern void s3c24xx_timer_init(void); extern struct syscore_ops s3c2410_pm_syscore_ops; extern struct syscore_ops s3c2412_pm_syscore_ops; diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S index 207e275362a..f3a9cff6d5d 100644 --- a/arch/arm/plat-samsung/include/plat/debug-macro.S +++ b/arch/arm/plat-samsung/include/plat/debug-macro.S @@ -14,12 +14,12 @@ /* The S5PV210/S5PC110 implementations are as belows. */ .macro fifo_level_s5pv210 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] and \rd, \rd, #S5PV210_UFSTAT_TXMASK .endm .macro fifo_full_s5pv210 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] tst \rd, #S5PV210_UFSTAT_TXFULL .endm @@ -27,7 +27,7 @@ * most widely re-used */ .macro fifo_level_s3c2440 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] and \rd, \rd, #S3C2440_UFSTAT_TXMASK .endm @@ -36,7 +36,7 @@ #endif .macro fifo_full_s3c2440 rd, rx - ldr \rd, [ \rx, # S3C2410_UFSTAT ] + ldr \rd, [\rx, # S3C2410_UFSTAT] tst \rd, #S3C2440_UFSTAT_TXFULL .endm @@ -45,11 +45,11 @@ #endif .macro senduart,rd,rx - strb \rd, [\rx, # S3C2410_UTXH ] + strb \rd, [\rx, # S3C2410_UTXH] .endm .macro busyuart, rd, rx - ldr \rd, [ \rx, # S3C2410_UFCON ] + ldr \rd, [\rx, # S3C2410_UFCON] tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? beq 1001f @ @ FIFO enabled... @@ -60,7 +60,7 @@ 1001: @ busy waiting for non fifo - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] + ldr \rd, [\rx, # S3C2410_UTRSTAT] tst \rd, #S3C2410_UTRSTAT_TXFE beq 1001b @@ -68,7 +68,7 @@ .endm .macro waituart,rd,rx - ldr \rd, [ \rx, # S3C2410_UFCON ] + ldr \rd, [\rx, # S3C2410_UFCON] tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? beq 1001f @ @ FIFO enabled... @@ -79,7 +79,7 @@ b 1002f 1001: @ idle waiting for non fifo - ldr \rd, [ \rx, # S3C2410_UTRSTAT ] + ldr \rd, [\rx, # S3C2410_UTRSTAT] tst \rd, #S3C2410_UTRSTAT_TXFE beq 1001b diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h index f5144cdd300..114178268b7 100644 --- a/arch/arm/plat-samsung/include/plat/dma-ops.h +++ b/arch/arm/plat-samsung/include/plat/dma-ops.h @@ -39,7 +39,8 @@ struct samsung_dma_config { }; struct samsung_dma_ops { - unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param); + unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param, + struct device *dev, char *ch_name); int (*release)(unsigned ch, void *param); int (*config)(unsigned ch, struct samsung_dma_config *param); int (*prepare)(unsigned ch, struct samsung_dma_prep *param); diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h index 945a99d5956..1d6cb2b8b09 100644 --- a/arch/arm/plat-samsung/include/plat/fimc-core.h +++ b/arch/arm/plat-samsung/include/plat/fimc-core.h @@ -43,6 +43,8 @@ static inline void s3c_fimc_setname(int id, char *name) s5p_device_fimc3.name = name; break; #endif + default: + break; } } diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index f7a3ea2c498..cf5aae5b097 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -106,7 +106,18 @@ static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chi #else /* machine specific code should provide samsung_gpiolib_getchip */ -#include <mach/gpio-track.h> +extern struct samsung_gpio_chip s3c24xx_gpios[]; + +static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) +{ + struct samsung_gpio_chip *chip; + + if (pin > S3C_GPIO_END) + return NULL; + + chip = &s3c24xx_gpios[pin/32]; + return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; +} static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { } #endif diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h deleted file mode 100644 index d1ecef0e38e..00000000000 --- a/arch/arm/plat-samsung/include/plat/gpio-fns.h +++ /dev/null @@ -1 +0,0 @@ -#include <plat/gpio-cfg.h> diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 887a0c95437..f6fcadeee96 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -109,17 +109,11 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); #ifdef CONFIG_PM extern int s3c_irq_wake(struct irq_data *data, unsigned int state); extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); -extern int s3c24xx_irq_suspend(void); -extern void s3c24xx_irq_resume(void); #else #define s3c_irq_wake NULL #define s3c_irqext_wake NULL -#define s3c24xx_irq_suspend NULL -#define s3c24xx_irq_resume NULL #endif -extern struct syscore_ops s3c24xx_irq_syscore_ops; - /* PM debug functions */ #ifdef CONFIG_SAMSUNG_PM_DEBUG diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h index 7178e338e25..f27399a3c68 100644 --- a/arch/arm/plat-samsung/include/plat/s3c2416.h +++ b/arch/arm/plat-samsung/include/plat/s3c2416.h @@ -25,6 +25,7 @@ extern int s3c2416_baseclk_add(void); extern void s3c2416_restart(char mode, const char *cmd); +extern void s3c2416_init_irq(void); extern struct syscore_ops s3c2416_irq_syscore_ops; #else diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h index a5b794ff838..71b88ec4895 100644 --- a/arch/arm/plat-samsung/include/plat/s3c2443.h +++ b/arch/arm/plat-samsung/include/plat/s3c2443.h @@ -25,6 +25,8 @@ extern void s3c2443_init_clocks(int xtal); extern int s3c2443_baseclk_add(void); extern void s3c2443_restart(char mode, const char *cmd); + +extern void s3c2443_init_irq(void); #else #define s3c2443_init_clocks NULL #define s3c2443_init_uarts NULL diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h index 3a70aebc920..9c96f3586ce 100644 --- a/arch/arm/plat-samsung/include/plat/s5p-time.h +++ b/arch/arm/plat-samsung/include/plat/s5p-time.h @@ -36,5 +36,5 @@ struct s5p_timer_source { extern void __init s5p_set_timer_source(enum s5p_timer_mode event, enum s5p_timer_mode source); -extern struct sys_timer s5p_timer; +extern void s5p_timer_init(void); #endif /* __ASM_PLAT_S5P_TIME_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 151cc9195cf..9b87f38fc4f 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -374,6 +374,8 @@ static inline void s3c_sdhci_setname(int id, char *name) s3c_device_hsmmc3.name = name; break; #endif + default: + break; } } diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 7e068d182c3..438b24846e7 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -97,33 +97,6 @@ static inline void flush(void) *((volatile unsigned int __force *)(ad)) = (d); \ } while (0) -/* CONFIG_S3C_BOOT_WATCHDOG - * - * Simple boot-time watchdog setup, to reboot the system if there is - * any problem with the boot process -*/ - -#ifdef CONFIG_S3C_BOOT_WATCHDOG - -#define WDOG_COUNT (0xff00) - -static inline void arch_decomp_wdog(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); -} - -static void arch_decomp_wdog_start(void) -{ - __raw_writel(WDOG_COUNT, S3C2410_WTDAT); - __raw_writel(WDOG_COUNT, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); -} - -#else -#define arch_decomp_wdog_start() -#define arch_decomp_wdog() -#endif - #ifdef CONFIG_S3C_BOOT_ERROR_RESET static void arch_decomp_error(const char *x) @@ -173,7 +146,6 @@ arch_decomp_setup(void) */ arch_detect_cpu(); - arch_decomp_wdog_start(); /* Enable the UART FIFOs if they where not enabled and our * configuration says we should turn them on. diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 15070284343..002b1472293 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -51,7 +51,7 @@ void s3c_pm_dbg(const char *fmt, ...) char buff[256]; va_start(va, fmt); - vsprintf(buff, fmt, va); + vsnprintf(buff, sizeof(buff), fmt, va); va_end(va); printascii(buff); @@ -243,6 +243,7 @@ int (*pm_cpu_sleep)(unsigned long); static int s3c_pm_enter(suspend_state_t state) { + int ret; /* ensure the debug is initialised (if enabled) */ s3c_pm_debug_init(); @@ -300,7 +301,9 @@ static int s3c_pm_enter(suspend_state_t state) * we resume as it saves its own register state and restores it * during the resume. */ - cpu_suspend(0, pm_cpu_sleep); + ret = cpu_suspend(0, pm_cpu_sleep); + if (ret) + return ret; /* restore the system state */ diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c index f99448c48d3..0cc40aea3f5 100644 --- a/arch/arm/plat-samsung/s3c-dma-ops.c +++ b/arch/arm/plat-samsung/s3c-dma-ops.c @@ -36,7 +36,8 @@ static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param, } static unsigned s3c_dma_request(enum dma_ch dma_ch, - struct samsung_dma_req *param) + struct samsung_dma_req *param, + struct device *dev, char *ch_name) { struct cb_data *data; diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c index 33bd3f3d20f..faa65160278 100644 --- a/arch/arm/plat-samsung/s5p-irq-eint.c +++ b/arch/arm/plat-samsung/s5p-irq-eint.c @@ -15,8 +15,7 @@ #include <linux/io.h> #include <linux/device.h> #include <linux/gpio.h> - -#include <asm/hardware/vic.h> +#include <linux/irqchip/arm-vic.h> #include <plat/regs-irqtype.h> diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c index dfb47d638f0..103e371f5e3 100644 --- a/arch/arm/plat-samsung/s5p-irq.c +++ b/arch/arm/plat-samsung/s5p-irq.c @@ -13,8 +13,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> - -#include <asm/hardware/vic.h> +#include <linux/irqchip/arm-vic.h> #include <mach/map.h> #include <plat/regs-timer.h> diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/s5p-time.c index 028b6e877eb..e92510cf82e 100644 --- a/arch/arm/plat-samsung/s5p-time.c +++ b/arch/arm/plat-samsung/s5p-time.c @@ -274,15 +274,8 @@ static void __init s5p_clockevent_init(void) clock_rate = clk_get_rate(tin_event); clock_count_per_tick = clock_rate / HZ; - clockevents_calc_mult_shift(&time_event_device, - clock_rate, S5PTIMER_MIN_RANGE); - time_event_device.max_delta_ns = - clockevent_delta2ns(-1, &time_event_device); - time_event_device.min_delta_ns = - clockevent_delta2ns(1, &time_event_device); - time_event_device.cpumask = cpumask_of(0); - clockevents_register_device(&time_event_device); + clockevents_config_and_register(&time_event_device, clock_rate, 1, -1); irq_number = timer_source.event_id + IRQ_TIMER0; setup_irq(irq_number, &s5p_clock_event_irq); @@ -393,13 +386,9 @@ static void __init s5p_timer_resources(void) clk_enable(tin_source); } -static void __init s5p_timer_init(void) +void __init s5p_timer_init(void) { s5p_timer_resources(); s5p_clockevent_init(); s5p_clocksource_init(); } - -struct sys_timer s5p_timer = { - .init = s5p_timer_init, -}; diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c index 60552e22f22..73defd00c3e 100644 --- a/arch/arm/plat-samsung/time.c +++ b/arch/arm/plat-samsung/time.c @@ -27,6 +27,7 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/platform_device.h> +#include <linux/syscore_ops.h> #include <asm/mach-types.h> @@ -95,7 +96,7 @@ static inline unsigned long timer_ticks_to_usec(unsigned long ticks) * IRQs are disabled before entering here from do_gettimeofday() */ -static unsigned long s3c2410_gettimeoffset (void) +static u32 s3c2410_gettimeoffset(void) { unsigned long tdone; unsigned long tval; @@ -120,7 +121,7 @@ static unsigned long s3c2410_gettimeoffset (void) tdone += timer_startval; } - return timer_ticks_to_usec(tdone); + return timer_ticks_to_usec(tdone) * 1000; } @@ -271,15 +272,16 @@ static void __init s3c2410_timer_resources(void) clk_enable(tin); } -static void __init s3c2410_timer_init(void) +static struct syscore_ops s3c24xx_syscore_ops = { + .resume = s3c2410_timer_setup, +}; + +void __init s3c24xx_timer_init(void) { + arch_gettimeoffset = s3c2410_gettimeoffset; + s3c2410_timer_resources(); s3c2410_timer_setup(); setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); + register_syscore_ops(&s3c24xx_syscore_ops); } - -struct sys_timer s3c24xx_timer = { - .init = s3c2410_timer_init, - .offset = s3c2410_gettimeoffset, - .resume = s3c2410_timer_setup -}; diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig index 87dbd81bdf5..739d016eb27 100644 --- a/arch/arm/plat-spear/Kconfig +++ b/arch/arm/plat-spear/Kconfig @@ -10,6 +10,7 @@ choice config ARCH_SPEAR13XX bool "ST SPEAr13xx with Device Tree" + select ARCH_HAVE_CPUFREQ select ARM_GIC select CPU_V7 select GPIO_SPEAR_SPICS diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h index 2ce6cb17a98..51b2dc93e4d 100644 --- a/arch/arm/plat-spear/include/plat/uncompress.h +++ b/arch/arm/plat-spear/include/plat/uncompress.h @@ -38,6 +38,5 @@ static inline void flush(void) * nothing to do */ #define arch_decomp_setup() -#define arch_decomp_wdog() #endif /* __PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index 03321af5de9..bd5c53cd696 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -186,15 +186,9 @@ static void __init spear_clockevent_init(int irq) tick_rate = clk_get_rate(gpt_clk); tick_rate >>= CTRL_PRESCALER16; - clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE); - - clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, - &clkevt); - clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt); - clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&clkevt); + clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0); setup_irq(irq, &spear_timer_irq); } diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index 04ca4937d8c..f2ac1556177 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -14,10 +14,10 @@ #include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> +#include <linux/irqchip/arm-gic.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> -#include <asm/hardware/gic.h> /* * Write pen_release in a way that is guaranteed to be visible to all @@ -79,7 +79,7 @@ int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idl * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - gic_raise_softirq(cpumask_of(cpu), 0); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { |