diff options
Diffstat (limited to 'arch/arm')
494 files changed, 18234 insertions, 23199 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49d993cee51..7a13c2cd7a8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -9,7 +9,7 @@ config ARM select BUILDTIME_EXTABLE_SORT if MMU select CPU_PM if (SUSPEND || CPU_IDLE) select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU - select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) + select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW @@ -366,11 +366,12 @@ config ARCH_CLPS711X select ARCH_REQUIRE_GPIOLIB select AUTO_ZRELADDR select CLKDEV_LOOKUP + select CLKSRC_MMIO select COMMON_CLK select CPU_ARM720T select GENERIC_CLOCKEVENTS + select MFD_SYSCON select MULTI_IRQ_HANDLER - select NEED_MACH_MEMORY_H select SPARSE_IRQ help Support for Cirrus Logic 711x/721x/731x based boards. @@ -502,6 +503,7 @@ config ARCH_DOVE config ARCH_KIRKWOOD bool "Marvell Kirkwood" + select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CPU_FEROCEON select GENERIC_CLOCKEVENTS @@ -634,6 +636,7 @@ config ARCH_MSM config ARCH_SHMOBILE bool "Renesas SH-Mobile / R-Mobile" + select ARM_PATCH_PHYS_VIRT select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP @@ -643,9 +646,8 @@ config ARCH_SHMOBILE select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MULTI_IRQ_HANDLER - select NEED_MACH_MEMORY_H select NO_IOPORT - select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ help @@ -695,6 +697,7 @@ config ARCH_S3C24XX select CLKDEV_LOOKUP select CLKSRC_MMIO select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -702,6 +705,7 @@ config ARCH_S3C24XX select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select NEED_MACH_IO_H + select SAMSUNG_ATAGS help Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST @@ -717,6 +721,7 @@ config ARCH_S3C64XX select CLKSRC_MMIO select CPU_V6 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -726,9 +731,11 @@ config ARCH_S3C64XX select PLAT_SAMSUNG select S3C_DEV_NAND select S3C_GPIO_TRACK + select SAMSUNG_ATAGS select SAMSUNG_CLKSRC select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI help Samsung S3C64XX series based systems @@ -739,11 +746,14 @@ config ARCH_S5P64X0 select CLKSRC_MMIO select CPU_V6 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H + select SAMSUNG_WDT_RESET + select SAMSUNG_ATAGS help Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, SMDK6450. @@ -755,11 +765,14 @@ config ARCH_S5PC100 select CLKSRC_MMIO select CPU_V7 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H + select SAMSUNG_WDT_RESET + select SAMSUNG_ATAGS help Samsung S5PC100 series based systems @@ -772,12 +785,14 @@ config ARCH_S5PV210 select CLKSRC_MMIO select CPU_V7 select GENERIC_CLOCKEVENTS + select GPIO_SAMSUNG select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H + select SAMSUNG_ATAGS help Samsung S5PV210/S5PC110 series based systems @@ -785,7 +800,9 @@ config ARCH_EXYNOS bool "Samsung EXYNOS" select ARCH_HAS_CPUFREQ select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_REQUIRE_GPIOLIB select ARCH_SPARSEMEM_ENABLE + select ARM_GIC select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 @@ -794,8 +811,9 @@ config ARCH_EXYNOS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS - select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H + select SPARSE_IRQ + select USE_OF help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) @@ -813,23 +831,6 @@ config ARCH_SHARK Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>). -config ARCH_U300 - bool "ST-Ericsson U300 Series" - depends on MMU - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select ARM_PATCH_PHYS_VIRT - select ARM_VIC - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select COMMON_CLK - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_TCM - select SPARSE_IRQ - help - Support for ST-Ericsson U300 series mobile platforms. - config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL @@ -840,6 +841,7 @@ config ARCH_DAVINCI select GENERIC_IRQ_CHIP select HAVE_IDE select NEED_MACH_GPIO_H + select TI_PRIV_EDMA select USE_OF select ZONE_DMA help @@ -871,20 +873,21 @@ menu "Multiple platform selection" comment "CPU Core family selection" -config ARCH_MULTI_V4 - bool "ARMv4 based platforms (FA526, StrongARM)" - depends on !ARCH_MULTI_V6_V7 - select ARCH_MULTI_V4_V5 - config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" depends on !ARCH_MULTI_V6_V7 select ARCH_MULTI_V4_V5 + select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ + CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ + CPU_ARM925T || CPU_ARM940T) config ARCH_MULTI_V5 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" depends on !ARCH_MULTI_V6_V7 select ARCH_MULTI_V4_V5 + select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ + CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ + CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) config ARCH_MULTI_V4_V5 bool @@ -948,6 +951,8 @@ source "arch/arm/mach-iop13xx/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" +source "arch/arm/mach-keystone/Kconfig" + source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" @@ -981,6 +986,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-realview/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" + source "arch/arm/mach-sa1100/Kconfig" source "arch/arm/plat-samsung/Kconfig" @@ -1087,6 +1094,20 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config PJ4B_ERRATA_4742 + bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" + depends on CPU_PJ4B && MACH_ARMADA_370 + default y + help + When coming out of either a Wait for Interrupt (WFI) or a Wait for + Event (WFE) IDLE states, a specific timing sensitivity exists between + the retiring WFI/WFE instructions and the newly issued subsequent + instructions. This sensitivity can result in a CPU hang scenario. + Workaround: + The software must insert either a Data Synchronization Barrier (DSB) + or Data Memory Barrier (DMB) command immediately after the WFI/WFE + instruction + config ARM_ERRATA_326103 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" depends on CPU_V6 @@ -1189,6 +1210,16 @@ config PL310_ERRATA_588369 is not correctly implemented in PL310 as clean lines are not invalidated as a result of these operations. +config ARM_ERRATA_643719 + bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 643719 Cortex-A9 (prior to + r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR + register returns zero when it should return one. The workaround + corrects this value, ensuring cache maintenance operations which use + it behave as intended and avoiding data corruption. + config ARM_ERRATA_720789 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" depends on CPU_V7 @@ -1393,6 +1424,7 @@ config PCI_HOST_ITE8152 select DMABOUNCE source "drivers/pci/Kconfig" +source "drivers/pci/pcie/Kconfig" source "drivers/pcmcia/Kconfig" @@ -1528,7 +1560,7 @@ config NR_CPUS config HOTPLUG_CPU bool "Support for hot-pluggable CPUs" - depends on SMP && HOTPLUG + depends on SMP help Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. @@ -1560,6 +1592,7 @@ config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA default 512 if SOC_OMAP5 + default 512 if ARCH_KEYSTONE default 392 if ARCH_U8500 default 352 if ARCH_VT8500 default 288 if ARCH_SUNXI @@ -1585,7 +1618,7 @@ config SCHED_HRTICK config THUMB2_KERNEL bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY - depends on CPU_V7 && !CPU_V6 && !CPU_V6K + depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K default y if CPU_THUMBONLY select AEABI select ARM_ASM_UNIFIED @@ -2006,7 +2039,7 @@ config XIP_PHYS_ADDR config KEXEC bool "Kexec system call (EXPERIMENTAL)" - depends on (!SMP || HOTPLUG_CPU) + depends on (!SMP || PM_SLEEP_SMP) help kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot @@ -2040,7 +2073,7 @@ config CRASH_DUMP config AUTO_ZRELADDR bool "Auto calculation of the decompressed kernel image address" - depends on !ZBOOT_ROM && !ARCH_U300 + depends on !ZBOOT_ROM help ZRELADDR is the physical address where the decompressed kernel image will be placed. If AUTO_ZRELADDR is selected, the address diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index 2cef8e13f9f..c859495da48 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -28,7 +28,7 @@ config FLASH_SIZE config PROCESSOR_ID hex 'Hard wire the processor ID' default 0x00007700 - depends on !CPU_CP15 + depends on !(CPU_CP15 || CPU_V7M) help If processor has no CP15 register, this processor ID is used instead of the auto-probing which utilizes the register. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 29f7623553c..ab95f07e154 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -258,6 +258,20 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6SL. + config DEBUG_KEYSTONE_UART0 + bool "Kernel low-level debugging on KEYSTONE2 using UART0" + depends on ARCH_KEYSTONE + help + Say Y here if you want the debug print routines to direct + their output to UART0 serial port on KEYSTONE2 devices. + + config DEBUG_KEYSTONE_UART1 + bool "Kernel low-level debugging on KEYSTONE2 using UART1" + depends on ARCH_KEYSTONE + help + Say Y here if you want the debug print routines to direct + their output to UART1 serial port on KEYSTONE2 devices. + config DEBUG_MMP_UART2 bool "Kernel low-level debugging message via MMP UART2" depends on ARCH_MMP @@ -310,12 +324,37 @@ choice their output to the serial port on MSM 8960 devices. config DEBUG_MVEBU_UART - bool "Kernel low-level debugging messages via MVEBU UART" + bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)" + depends on ARCH_MVEBU + help + Say Y here if you want kernel low-level debugging support + on MVEBU based platforms. + + This option should be used with the old bootloaders + that left the internal registers mapped at + 0xd0000000. As of today, this is the case on + platforms such as the Globalscale Mirabox or the + Plathome OpenBlocks AX3, when using the original + bootloader. + + If the wrong DEBUG_MVEBU_UART* option is selected, + when u-boot hands over to the kernel, the system + silently crashes, with no serial output at all. + + config DEBUG_MVEBU_UART_ALTERNATE + bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)" depends on ARCH_MVEBU help Say Y here if you want kernel low-level debugging support on MVEBU based platforms. + This option should be used with the new bootloaders + that remap the internal registers at 0xf1000000. + + If the wrong DEBUG_MVEBU_UART* option is selected, + when u-boot hands over to the kernel, the system + silently crashes, with no serial output at all. + config DEBUG_NOMADIK_UART bool "Kernel low-level debugging messages via NOMADIK UART" depends on ARCH_NOMADIK @@ -360,6 +399,13 @@ choice their output to the standard serial port on the RealView PB1176 platform. + config DEBUG_ROCKCHIP_UART + bool "Kernel low-level debugging messages via Rockchip UART" + depends on ARCH_ROCKCHIP + help + Say Y here if you want kernel low-level debugging support + on Rockchip based platforms. + config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG select DEBUG_EXYNOS_UART if ARCH_EXYNOS @@ -450,6 +496,13 @@ choice Say Y here if you want the debug print routines to direct their output to the uart1 port on SiRFmarco devices. + config DEBUG_U300_UART + bool "Kernel low-level debugging messages via U300 UART0" + depends on ARCH_U300 + help + Say Y here if you want the debug print routines to direct + their output to the uart port on U300 devices. + config DEBUG_UX500_UART depends on ARCH_U8500 bool "Use Ux500 UART for low-level debug" @@ -597,6 +650,32 @@ endchoice choice prompt "Low-level debug console UART" + depends on DEBUG_ROCKCHIP_UART + + config DEBUG_RK29_UART0 + bool "RK29 UART0" + + config DEBUG_RK29_UART1 + bool "RK29 UART1" + + config DEBUG_RK29_UART2 + bool "RK29 UART2" + + config DEBUG_RK3X_UART0 + bool "RK3X UART0" + + config DEBUG_RK3X_UART1 + bool "RK3X UART1" + + config DEBUG_RK3X_UART2 + bool "RK3X UART2" + + config DEBUG_RK3X_UART3 + bool "RK3X UART3" +endchoice + +choice + prompt "Low-level debug console UART" depends on DEBUG_LL && DEBUG_TEGRA_UART config TEGRA_DEBUG_UART_AUTO_ODMDATA @@ -641,17 +720,22 @@ config DEBUG_LL_INCLUDE DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART - default "debug/mvebu.S" if DEBUG_MVEBU_UART + default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \ + DEBUG_KEYSTONE_UART1 + default "debug/mvebu.S" if DEBUG_MVEBU_UART || \ + DEBUG_MVEBU_UART_ALTERNATE default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART default "debug/nomadik.S" if DEBUG_NOMADIK_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ DEBUG_MMP_UART3 + default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/tegra.S" if DEBUG_TEGRA_UART + default "debug/u300.S" if DEBUG_U300_UART default "debug/ux500.S" if DEBUG_UX500_UART default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1ba358ba16b..c01e4a72855 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -59,6 +59,7 @@ comma = , # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes # testing for a specific architecture or later rather impossible. +arch-$(CONFIG_CPU_32v7M) :=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) # Only override the compiler option if ARMv6. The ARMv6K extensions are @@ -168,9 +169,10 @@ machine-$(CONFIG_ARCH_OMAP1) += omap1 machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell -machine-$(CONFIG_ARCH_PRIMA2) += prima2 +machine-$(CONFIG_ARCH_SIRF) += prima2 machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_REALVIEW) += realview +machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx @@ -194,9 +196,11 @@ machine-$(CONFIG_PLAT_SPEAR) += spear machine-$(CONFIG_ARCH_VIRT) += virt machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_SUNXI) += sunxi +machine-$(CONFIG_ARCH_KEYSTONE) += keystone # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +plat-$(CONFIG_ARCH_EXYNOS) += samsung plat-$(CONFIG_ARCH_OMAP) += omap plat-$(CONFIG_ARCH_S3C64XX) += samsung plat-$(CONFIG_PLAT_IOP) += iop diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 79e9bdbfc49..120b83bfde2 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -116,7 +116,8 @@ targets := vmlinux vmlinux.lds \ # Make sure files are removed during clean extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \ - lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) + lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \ + hyp-stub.S ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S index fe3719b516f..e2d636336b7 100644 --- a/arch/arm/boot/compressed/head-shmobile.S +++ b/arch/arm/boot/compressed/head-shmobile.S @@ -46,7 +46,7 @@ __image_start: __image_end: .long _got_end __load_base: - .long CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM + .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM __loaded: .long __continue .align @@ -55,26 +55,9 @@ __tmp_stack: __continue: #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ - b 1f -__atags:@ tag #1 - .long 12 @ tag->hdr.size = tag_size(tag_core); - .long 0x54410001 @ tag->hdr.tag = ATAG_CORE; - .long 0 @ tag->u.core.flags = 0; - .long 0 @ tag->u.core.pagesize = 0; - .long 0 @ tag->u.core.rootdev = 0; - @ tag #2 - .long 8 @ tag->hdr.size = tag_size(tag_mem32); - .long 0x54410002 @ tag->hdr.tag = ATAG_MEM; - .long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE; - .long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START; - @ tag #3 - .long 0 @ tag->hdr.size = 0 - .long 0 @ tag->hdr.tag = ATAG_NONE; -1: - /* Set board ID necessary for boot */ ldr r7, 1f @ Set machine type register - adr r8, __atags @ Set atag register + mov r8, #0 @ pass null pointer as atag b 2f 1 : .long MACH_TYPE diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 049422b06f4..962c0eee303 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -66,6 +66,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ @@ -218,6 +220,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-pluto.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb +dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d1e4929231d..0d4df90477f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -485,7 +485,6 @@ compatible = "ti,am3352-ocmcram"; reg = <0x40300000 0x10000>; ti,hwmods = "ocmcram"; - ti,no_idle_on_suspend; }; wkup_m3: wkup_m3@44d00000 { diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index a679b6697a9..90b117624ab 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -89,7 +89,7 @@ sata@a0000 { compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; + reg = <0xa0000 0x5000>; interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1"; @@ -105,7 +105,7 @@ eth0: ethernet@70000 { compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x2500>; + reg = <0x70000 0x4000>; interrupts = <8>; clocks = <&gateclk 4>; status = "disabled"; @@ -113,7 +113,7 @@ eth1: ethernet@74000 { compatible = "marvell,armada-370-neta"; - reg = <0x74000 0x2500>; + reg = <0x74000 0x4000>; interrupts = <10>; clocks = <&gateclk 3>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index f4029f015af..2d9335da210 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -92,7 +92,7 @@ ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 386f0ce4845..c7b1f4d5c1c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -108,7 +108,7 @@ eth3: ethernet@34000 { compatible = "marvell,armada-370-neta"; - reg = <0x34000 0x2500>; + reg = <0x34000 0x4000>; interrupts = <14>; clocks = <&gateclk 1>; status = "disabled"; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index e481d54b565..416eb948184 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -92,7 +92,7 @@ eth2: ethernet@30000 { compatible = "marvell,armada-370-neta"; - reg = <0x30000 0x2500>; + reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index e9cdee38509..724a22f9b1c 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -770,7 +770,7 @@ }; }; - pinctrl@03680000 { + pinctrl@03860000 { gpz: gpz { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 8b1f9b63f9f..54a35e64c78 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -161,9 +161,9 @@ interrupts = <0 50 0>; }; - pinctrl_3: pinctrl@03680000 { + pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5250-pinctrl"; - reg = <0x0368000 0x1000>; + reg = <0x03860000 0x1000>; interrupts = <0 47 0>; }; diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index 3aa65bb2802..ba88cfd2486 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -65,4 +65,12 @@ clock-frequency = <50000000>; }; }; + + pcie@290000 { + reset-gpio = <&pin_ctrl 5 0>; + }; + + pcie@2a0000 { + reset-gpio = <&pin_ctrl 22 0>; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 9589ed9282f..bfcb907b7e3 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -126,7 +126,7 @@ clock-names = "spi", "spi_busclk0"; }; - pinctrl { + pin_ctrl: pinctrl { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, @@ -230,4 +230,42 @@ clocks = <&clock 24>; clock-names = "usbhost"; }; + + pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + clocks = <&clock 28>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; + }; + + pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + clocks = <&clock 29>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; + }; }; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index c9c3fa34464..b6b82eca8d1 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -39,6 +39,47 @@ valid-mask = <0x003fffff>; }; + pci: pciv3@62000000 { + compatible = "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + ranges = <0x00000000 0 0x61000000 /* config space */ + 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ + 0x01000000 0 0x0 /* I/O space */ + 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ + 0x02000000 0 0x00000000 /* non-prefectable memory */ + 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ + 0x42000000 0 0x10000000 /* prefetchable memory */ + 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; + }; + fpga { /* * The Integator/AP predates the idea to have magic numbers diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts new file mode 100644 index 00000000000..1334b42c6b7 --- /dev/null +++ b/arch/arm/boot/dts/keystone.dts @@ -0,0 +1,117 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + compatible = "ti,keystone-evm"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0x308>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 20 0xf01>, + <0 21 0xf01>, + <0 22 0xf01>, + <0 23 0xf01>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0x0 0xc0000000>; + + rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x023100e8 4>; /* pll reset control reg */ + }; + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clock-frequency = <133120000>; + interrupts = <0 277 0xf01>; + }; + + uart1: serial@02531000 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clock-frequency = <133120000>; + interrupts = <0 280 0xf01>; + }; + + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 0ed2f56a91f..1e5bef0bead 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -41,6 +41,37 @@ }; }; + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 69b760d5b11..a63a1113726 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -93,5 +93,53 @@ clocks = <&gate_clk 7>; status = "disabled"; }; + + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 10>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts new file mode 100644 index 00000000000..9d777edd1f3 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -0,0 +1,30 @@ +/* + * Marvell DB-88F6281-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6281.dtsi" + +/ { + model = "Marvell DB-88F6281-BP Development Board"; + compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts new file mode 100644 index 00000000000..f4c852886d2 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -0,0 +1,34 @@ +/* + * Marvell DB-88F6282-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "kirkwood-db.dtsi" +/include/ "kirkwood-6282.dtsi" + +/ { + model = "Marvell DB-88F6282-BP Development Board"; + compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + ocp@f1000000 { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + + pcie@2,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi new file mode 100644 index 00000000000..c87cfb81612 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -0,0 +1,89 @@ +/* + * Marvell DB-{88F6281,88F6282}-BP Development Board Setup + * + * Saeed Bishara <saeed@marvell.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the 6281 + * and 6282 variants of the Marvell Kirkwood Development Board. + */ + +/include/ "kirkwood.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + pinctrl@10000 { + pmx_sdio_gpios: pmx-sdio-gpios { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + chip-delay = <25>; + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "root"; + reg = <0x500000 0x1fb00000>; + }; + }; + + sata@80000 { + nr-ports = <2>; + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + + mvsdio@90000 { + pinctrl-0 = <&pmx_sdio_gpios>; + pinctrl-names = "default"; + wp-gpios = <&gpio1 5 0>; + cd-gpios = <&gpio1 6 0>; + status = "okay"; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 027501857cb..441204e8abc 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -101,6 +101,14 @@ reg = <0x980000 0x1f400000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 4945eba03ae..31b17f5b9d2 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -172,6 +172,10 @@ alarm-gpios = <&gpio1 8 0>; }; + restart_poweroff { + compatible = "restart-poweroff"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 211916a5a0f..6179333fd71 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -134,6 +134,14 @@ cd-gpios = <&gpio1 15 1>; /* No WP GPIO */ }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index b79ea8cebf4..ad6ade7d919 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -101,6 +101,14 @@ status = "okay"; nr-ports = <2>; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 089024a6dea..69003598f5f 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -162,6 +162,14 @@ reg = <0x5040000 0x2fc0000>; }; }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; gpio_keys { diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index a2a90c40bef..6dd1038e4de 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -1,7 +1,8 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6281.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index b5be3ea9b34..6fdc5ffcaae 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -1,7 +1,8 @@ /dts-v1/; -/include/ "kirkwood-ts219.dtsi" +/include/ "kirkwood.dtsi" /include/ "kirkwood-6282.dtsi" +/include/ "kirkwood-ts219.dtsi" / { ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index b9325d45be7..0c9a94cd666 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -1,5 +1,3 @@ -/include/ "kirkwood.dtsi" - / { model = "QNAP TS219 family"; compatible = "qnap,ts219", "marvell,kirkwood"; @@ -37,6 +35,11 @@ pinctrl-0 = <&pmx_uart1>; pinctrl-names = "default"; }; + poweroff@12100 { + compatible = "qnap,power-off"; + reg = <0x12000 0x100>; + clocks = <&gate_clk 7>; + }; spi@10600 { status = "okay"; pinctrl-0 = <&pmx_spi>; @@ -84,5 +87,12 @@ status = "okay"; nr-ports = <2>; }; + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 1ae3eb2dea2..9809fc1f105 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -31,6 +31,7 @@ ocp@f1000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf1000000 0x0100000 + 0xe0000000 0xe0000000 0x8100000 /* PCIE */ 0xf4000000 0xf4000000 0x0000400 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 9bf49b3826e..cdc010e0f93 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -15,7 +15,7 @@ < 0x02081000 0x1000 >; }; - timer@2000004 { + timer@2000000 { compatible = "qcom,scss-timer", "qcom,msm-timer"; interrupts = <1 0 0x301>, <1 1 0x301>, @@ -26,7 +26,18 @@ cpu-offset = <0x40000>; }; - serial@19c400000 { + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + reg = <0x00800000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <173>; + interrupts = <0 32 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial@19c40000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts index 2e4d87a125d..db2060c4654 100644 --- a/arch/arm/boot/dts/msm8960-cdp.dts +++ b/arch/arm/boot/dts/msm8960-cdp.dts @@ -26,7 +26,18 @@ cpu-offset = <0x80000>; }; - serial@19c400000 { + msmgpio: gpio@fd510000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <150>; + interrupts = <0 32 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xfd510000 0x4000>; + }; + + serial@16440000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi new file mode 100644 index 00000000000..6e307fc4c45 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * This is a dummy clock, to be used as placeholder on + * other mux clocks when a specific parent clock is not + * yet implemented. It should be dropped when the driver + * is complete. + */ + dummy: dummy { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + dummy48m: dummy48m { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + dummy150m: dummy150m { + compatible = "fixed-clock"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gates0: gate-clk@200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk@200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + }; + + clk_gates2: gate-clk@200000d8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d8 0x4>; + clocks = <&clk_gates2 1>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&clk_gates2 3>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy48m>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_periph_src", "gate_aclk_periph", + "gate_hclk_periph", "gate_pclk_periph", + "gate_smc", "gate_mac", + "gate_hsadc", "gate_hsadc_frac", + "gate_saradc", "gate_spi0", + "gate_spi1", "gate_mmc0", + "gate_mac_lbtest", "gate_mmc1", + "gate_emmc", "gate_tsadc"; + + #clock-cells = <1>; + }; + + clk_gates3: gate-clk@200000dc { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000dc 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0_src", "gate_dclk_lcdc0", + "gate_dclk_lcdc1", "gate_pclkin_cif0", + "gate_pclkin_cif1", "reserved", + "reserved", "gate_cif0_out", + "gate_cif1_out", "gate_aclk_vepu", + "gate_hclk_vepu", "gate_aclk_vdpu", + "gate_hclk_vdpu", "gate_gpu_src", + "reserved", "gate_xin27m"; + + #clock-cells = <1>; + }; + + clk_gates4: gate-clk@200000e0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e0 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates2 3>, + <&clk_gates2 1>, <&clk_gates2 1>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 3>, <&clk_gates0 3>, + <&clk_gates0 3>, <&clk_gates2 3>, + <&clk_gates0 4>; + + clock-output-names = + "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix", + "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix", + "gate_aclk_pei_niu", "gate_hclk_usb_peri", + "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri", + "gate_hclk_cpubus", "gate_hclk_ahb2apb", + "gate_aclk_strc_sys", "gate_aclk_l2mem_con", + "gate_aclk_intmem", "gate_pclk_tsadc", + "gate_hclk_hdmi"; + + #clock-cells = <1>; + }; + + clk_gates5: gate-clk@200000e4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e4 0x4>; + clocks = <&clk_gates0 3>, <&clk_gates2 1>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 4>, <&clk_gates0 5>, + <&clk_gates2 1>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates4 5>, + <&clk_gates4 5>, <&dummy>; + + clock-output-names = + "gate_aclk_dmac1", "gate_aclk_dmac2", + "gate_pclk_efuse", "gate_pclk_tzpc", + "gate_pclk_grf", "gate_pclk_pmu", + "gate_hclk_rom", "gate_pclk_ddrupctl", + "gate_aclk_smc", "gate_hclk_nandc", + "gate_hclk_mmc0", "gate_hclk_mmc1", + "gate_hclk_emmc", "gate_hclk_otg0", + "gate_hclk_otg1", "gate_aclk_gpu"; + + #clock-cells = <1>; + }; + + clk_gates6: gate-clk@200000e8 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000e8 0x4>; + clocks = <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates3 0>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates1 4>, + <&clk_gates0 4>, <&clk_gates3 0>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_aclk_lcdc0", "gate_hclk_lcdc0", + "gate_hclk_lcdc1", "gate_aclk_lcdc1", + "gate_hclk_cif0", "gate_aclk_cif0", + "gate_hclk_cif1", "gate_aclk_cif1", + "gate_aclk_ipp", "gate_hclk_ipp", + "gate_hclk_rga", "gate_aclk_rga", + "gate_hclk_vio_bus", "gate_aclk_vio0", + "gate_aclk_vcodec", "gate_shclk_vio_h2h"; + + #clock-cells = <1>; + }; + + clk_gates7: gate-clk@200000ec { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000ec 0x4>; + clocks = <&clk_gates2 2>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates0 4>, + <&clk_gates0 4>, <&clk_gates2 2>, + <&clk_gates2 2>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates2 3>; + + clock-output-names = + "gate_hclk_emac", "gate_hclk_spdif", + "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch", + "gate_hclk_i2s_8ch", "gate_hclk_hsadc", + "gate_hclk_pidf", "gate_pclk_timer0", + "gate_pclk_timer1", "gate_pclk_timer2", + "gate_pclk_pwm01", "gate_pclk_pwm23", + "gate_pclk_spi0", "gate_pclk_spi1", + "gate_pclk_saradc", "gate_pclk_wdt"; + + #clock-cells = <1>; + }; + + clk_gates8: gate-clk@200000f0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f0 0x4>; + clocks = <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&clk_gates2 3>, <&clk_gates0 5>, + <&clk_gates0 5>, <&clk_gates0 5>, + <&clk_gates2 3>, <&clk_gates2 3>, + <&dummy>, <&clk_gates0 5>; + + clock-output-names = + "gate_pclk_uart0", "gate_pclk_uart1", + "gate_pclk_uart2", "gate_pclk_uart3", + "gate_pclk_i2c0", "gate_pclk_i2c1", + "gate_pclk_i2c2", "gate_pclk_i2c3", + "gate_pclk_i2c4", "gate_pclk_gpio0", + "gate_pclk_gpio1", "gate_pclk_gpio2", + "gate_pclk_gpio3", "gate_pclk_gpio4", + "reserved", "gate_pclk_gpio6"; + + #clock-cells = <1>; + }; + + clk_gates9: gate-clk@200000f4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000f4 0x4>; + clocks = <&dummy>, <&clk_gates0 5>, + <&dummy>, <&dummy>, + <&dummy>, <&clk_gates1 4>, + <&clk_gates0 5>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>; + + clock-output-names = + "gate_clk_core_dbg", "gate_pclk_dbg", + "gate_clk_trace", "gate_atclk", + "gate_clk_l2c", "gate_aclk_vio1", + "gate_pclk_publ", "gate_aclk_intmem0", + "gate_aclk_intmem1", "gate_aclk_intmem2", + "gate_aclk_intmem3"; + + #clock-cells = <1>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi new file mode 100644 index 00000000000..56bfac93d3f --- /dev/null +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "skeleton.dtsi" +#include "rk3066a-clocks.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&dummy150m>; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 0>, <&clk_gates7 7>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 1>, <&clk_gates7 8>; + clock-names = "timer", "pclk"; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates1 2>, <&clk_gates7 9>; + clock-names = "timer", "pclk"; + }; + + pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + reg = <0x20008000 0x150>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 13>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 15>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; + rockchip,config = <&pcfg_pull_default>; + }; + }; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 8>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 10>; + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 12>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&clk_gates1 14>; + status = "disabled"; + }; + + dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 10>, <&clk_gates2 11>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + + dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&clk_gates5 11>, <&clk_gates2 13>; + clock-names = "biu", "ciu"; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts new file mode 100644 index 00000000000..8a1032c1ffc --- /dev/null +++ b/arch/arm/boot/dts/ste-u300.dts @@ -0,0 +1,473 @@ +/* + * Device Tree for the ST-Ericsson U300 Machine and SoC + */ + +/dts-v1/; +/include/ "skeleton.dtsi" + +/ { + model = "ST-Ericsson U300"; + compatible = "stericsson,u300"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory { + reg = <0x48000000 0x03c00000>; + }; + + s365 { + compatible = "stericsson,s365"; + vana15-supply = <&ab3100_ldo_d_reg>; + syscon = <&syscon>; + }; + + syscon: syscon@c0011000 { + compatible = "stericsson,u300-syscon", "syscon"; + reg = <0xc0011000 0x1000>; + clk32: app_32_clk@32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + pll13: pll13@13M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + /* Slow bridge clocks under PLL13 */ + slow_clk: slow_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <0>; + clocks = <&pll13>; + }; + uart0_clk: uart0_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <1>; + clocks = <&slow_clk>; + }; + gpio_clk: gpio_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <4>; + clocks = <&slow_clk>; + }; + rtc_clk: rtc_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <6>; + clocks = <&slow_clk>; + }; + apptimer_clk: app_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <7>; + clocks = <&slow_clk>; + }; + acc_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <8>; + clocks = <&slow_clk>; + }; + pll208: pll208@208M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; + }; + app208: app_208_clk@208M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&pll208>; + }; + cpu_clk@208M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <3>; + clocks = <&app208>; + }; + app104: app_104_clk@104M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll208>; + }; + semi_clk@104M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <9>; + clocks = <&app104>; + }; + app52: app_52_clk@52M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll208>; + }; + /* AHB subsystem clocks */ + ahb_clk: ahb_subsys_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <10>; + clocks = <&app52>; + }; + intcon_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <12>; + clocks = <&ahb_clk>; + }; + emif_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <5>; + clocks = <&ahb_clk>; + }; + dmac_clk: dmac_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <4>; + clocks = <&app52>; + }; + fsmc_clk: fsmc_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <6>; + clocks = <&app52>; + }; + xgam_clk: xgam_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <8>; + clocks = <&app52>; + }; + app26: app_26_clk@26M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&app52>; + }; + /* Fast bridge clocks */ + fast_clk: fast_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <0>; + clocks = <&app26>; + }; + i2c0_clk: i2c0_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <1>; + clocks = <&fast_clk>; + }; + i2c1_clk: i2c1_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <2>; + clocks = <&fast_clk>; + }; + mmc_pclk: mmc_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <5>; + clocks = <&fast_clk>; + }; + mmc_mclk: mmc_mclk { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-mclk"; + clocks = <&mmc_pclk>; + }; + spi_clk: spi_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <6>; + clocks = <&fast_clk>; + }; + }; + + timer: timer@c0014000 { + compatible = "stericsson,u300-apptimer"; + reg = <0xc0014000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <24 25 26 27>; + clocks = <&apptimer_clk>; + }; + + gpio: gpio@c0016000 { + compatible = "stericsson,gpio-coh901"; + reg = <0xc0016000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <0 1 2 18 21 22 23>; + clocks = <&gpio_clk>; + interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pinctrl: pinctrl@c0011000 { + compatible = "stericsson,pinctrl-u300"; + reg = <0xc0011000 0x1000>; + }; + + watchdog: watchdog@c0012000 { + compatible = "stericsson,coh901327"; + reg = <0xc0012000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <3>; + clocks = <&clk32>; + }; + + rtc: rtc@c0017000 { + compatible = "stericsson,coh901331"; + reg = <0xc0017000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <10>; + clocks = <&rtc_clk>; + }; + + dmac: dma-controller@c00020000 { + compatible = "stericsson,coh901318"; + reg = <0xc0020000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <2>; + #dma-cells = <1>; + dma-channels = <40>; + clocks = <&dmac_clk>; + }; + + /* A NAND flash of 128 MiB */ + fsmc: flash@40000000 { + compatible = "stericsson,fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x9f800000 0x1000>, /* FSMC Register*/ + <0x80000000 0x4000>, /* NAND Base DATA */ + <0x80020000 0x4000>, /* NAND Base ADDR */ + <0x80010000 0x4000>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + nand-skip-bbtscan; + clocks = <&fsmc_clk>; + + partition@0 { + label = "boot records"; + reg = <0x0 0x20000>; + }; + partition@20000 { + label = "free"; + reg = <0x20000 0x7e0000>; + }; + partition@800000 { + label = "platform"; + reg = <0x800000 0xf800000>; + }; + }; + + i2c0: i2c@c0004000 { + compatible = "st,ddci2c"; + reg = <0xc0004000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <8>; + clocks = <&i2c0_clk>; + #address-cells = <1>; + #size-cells = <0>; + ab3100: ab3100@0x48 { + compatible = "stericsson,ab3100"; + reg = <0x48>; + interrupt-parent = <&vica>; + interrupts = <0>; /* EXT0 IRQ */ + ab3100-regulators { + compatible = "stericsson,ab3100-regulators"; + ab3100_ldo_a_reg: ab3100_ldo_a { + regulator-compatible = "ab3100_ldo_a"; + startup-delay-us = <200>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_c_reg: ab3100_ldo_c { + regulator-compatible = "ab3100_ldo_c"; + startup-delay-us = <200>; + }; + ab3100_ldo_d_reg: ab3100_ldo_d { + regulator-compatible = "ab3100_ldo_d"; + startup-delay-us = <200>; + }; + ab3100_ldo_e_reg: ab3100_ldo_e { + regulator-compatible = "ab3100_ldo_e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_f_reg: ab3100_ldo_f { + regulator-compatible = "ab3100_ldo_f"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + startup-delay-us = <600>; + regulator-always-on; + regulator-boot-on; + }; + ab3100_ldo_g_reg: ab3100_ldo_g { + regulator-compatible = "ab3100_ldo_g"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2850000>; + startup-delay-us = <400>; + }; + ab3100_ldo_h_reg: ab3100_ldo_h { + regulator-compatible = "ab3100_ldo_h"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2750000>; + startup-delay-us = <200>; + }; + ab3100_ldo_k_reg: ab3100_ldo_k { + regulator-compatible = "ab3100_ldo_k"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2750000>; + startup-delay-us = <200>; + }; + ab3100_ext_reg: ab3100_ext { + regulator-compatible = "ab3100_ext"; + }; + ab3100_buck_reg: ab3100_buck { + regulator-compatible = "ab3100_buck"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <1000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + i2c1: i2c@c0005000 { + compatible = "st,ddci2c"; + reg = <0xc0005000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <9>; + clocks = <&i2c1_clk>; + #address-cells = <1>; + #size-cells = <0>; + fwcam0: fwcam@0x10 { + reg = <0x10>; + }; + fwcam1: fwcam@0x5d { + reg = <0x5d>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vica: interrupt-controller@a0001000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0001000 0x20>; + }; + + vicb: interrupt-controller@a0002000 { + compatible = "arm,versatile-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xa0002000 0x20>; + }; + + uart0: serial@c0013000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0013000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <22>; + clocks = <&uart0_clk>, <&uart0_clk>; + clock-names = "apb_pclk", "uart0_clk"; + dmas = <&dmac 17 &dmac 18>; + dma-names = "tx", "rx"; + }; + + uart1: serial@c0007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xc0007000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <20>; + dmas = <&dmac 38 &dmac 39>; + dma-names = "tx", "rx"; + }; + + mmcsd: mmcsd@c0001000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0xc0001000 0x1000>; + interrupt-parent = <&vicb>; + interrupts = <6 7>; + clocks = <&mmc_pclk>, <&mmc_mclk>; + clock-names = "apb_pclk", "mclk"; + max-frequency = <24000000>; + bus-width = <4>; // SD-card slot + mmc-cap-mmc-highspeed; + mmc-cap-sd-highspeed; + cd-gpios = <&gpio 12 0x4>; + cd-inverted; + vmmc-supply = <&ab3100_ldo_g_reg>; + dmas = <&dmac 14>; + dma-names = "rx"; + }; + + spi: ssp@c0006000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xc0006000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <23>; + clocks = <&spi_clk>, <&spi_clk>; + clock-names = "apb_pclk", "spi_clk"; + dmas = <&dmac 27 &dmac 28>; + dma-names = "tx", "rx"; + num-cs = <3>; + #address-cells = <1>; + #size-cells = <0>; + spi-dummy@1 { + compatible = "arm,pl022-dummy"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + }; +}; diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 9353184d730..c3a4e9ceba3 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -17,3 +17,6 @@ config SHARP_PARAM config SHARP_SCOOP bool + +config TI_PRIV_EDMA + bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 48434cbe3e8..8c60f473e97 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o AFLAGS_mcpm_head.o := -march=armv7-a AFLAGS_vlock.o := -march=armv7-a +obj-$(CONFIG_TI_PRIV_EDMA) += edma.o diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c index 45b7c71d9cc..a432e6c1dac 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/common/edma.c @@ -17,6 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include <linux/err.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> @@ -24,8 +25,15 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/edma.h> +#include <linux/err.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_dma.h> +#include <linux/of_irq.h> +#include <linux/pm_runtime.h> -#include <mach/edma.h> +#include <linux/platform_data/edma.h> /* Offsets matching "struct edmacc_param" */ #define PARM_OPT 0x00 @@ -494,26 +502,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_HANDLED; } -/****************************************************************************** - * - * Transfer controller error interrupt handlers - * - *****************************************************************************/ - -#define tc_errs_handled false /* disabled as long as they're NOPs */ - -static irqreturn_t dma_tc0err_handler(int irq, void *data) -{ - dev_dbg(data, "dma_tc0err_handler\n"); - return IRQ_HANDLED; -} - -static irqreturn_t dma_tc1err_handler(int irq, void *data) -{ - dev_dbg(data, "dma_tc1err_handler\n"); - return IRQ_HANDLED; -} - static int reserve_contiguous_slots(int ctlr, unsigned int id, unsigned int num_slots, unsigned int start_slot) @@ -1388,32 +1376,236 @@ void edma_clear_event(unsigned channel) } EXPORT_SYMBOL(edma_clear_event); -/*-----------------------------------------------------------------------*/ +#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) + +static int edma_of_read_u32_to_s16_array(const struct device_node *np, + const char *propname, s16 *out_values, + size_t sz) +{ + int ret; + + ret = of_property_read_u16_array(np, propname, out_values, sz); + if (ret) + return ret; + + /* Terminate it */ + *out_values++ = -1; + *out_values++ = -1; + + return 0; +} + +static int edma_xbar_event_map(struct device *dev, + struct device_node *node, + struct edma_soc_info *pdata, int len) +{ + int ret, i; + struct resource res; + void __iomem *xbar; + const s16 (*xbar_chans)[2]; + u32 shift, offset, mux; + + xbar_chans = devm_kzalloc(dev, + len/sizeof(s16) + 2*sizeof(s16), + GFP_KERNEL); + if (!xbar_chans) + return -ENOMEM; + + ret = of_address_to_resource(node, 1, &res); + if (ret) + return -EIO; + + xbar = devm_ioremap(dev, res.start, resource_size(&res)); + if (!xbar) + return -ENOMEM; + + ret = edma_of_read_u32_to_s16_array(node, + "ti,edma-xbar-event-map", + (s16 *)xbar_chans, + len/sizeof(u32)); + if (ret) + return -EIO; + + for (i = 0; xbar_chans[i][0] != -1; i++) { + shift = (xbar_chans[i][1] & 0x03) << 3; + offset = xbar_chans[i][1] & 0xfffffffc; + mux = readl(xbar + offset); + mux &= ~(0xff << shift); + mux |= xbar_chans[i][0] << shift; + writel(mux, (xbar + offset)); + } + + pdata->xbar_chans = xbar_chans; + + return 0; +} + +static int edma_of_parse_dt(struct device *dev, + struct device_node *node, + struct edma_soc_info *pdata) +{ + int ret = 0, i; + u32 value; + struct property *prop; + size_t sz; + struct edma_rsv_info *rsv_info; + s8 (*queue_tc_map)[2], (*queue_priority_map)[2]; + + memset(pdata, 0, sizeof(struct edma_soc_info)); + + ret = of_property_read_u32(node, "dma-channels", &value); + if (ret < 0) + return ret; + pdata->n_channel = value; + + ret = of_property_read_u32(node, "ti,edma-regions", &value); + if (ret < 0) + return ret; + pdata->n_region = value; + + ret = of_property_read_u32(node, "ti,edma-slots", &value); + if (ret < 0) + return ret; + pdata->n_slot = value; + + pdata->n_cc = 1; + + rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); + if (!rsv_info) + return -ENOMEM; + pdata->rsv = rsv_info; + + queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL); + if (!queue_tc_map) + return -ENOMEM; + + for (i = 0; i < 3; i++) { + queue_tc_map[i][0] = i; + queue_tc_map[i][1] = i; + } + queue_tc_map[i][0] = -1; + queue_tc_map[i][1] = -1; + + pdata->queue_tc_mapping = queue_tc_map; + + queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL); + if (!queue_priority_map) + return -ENOMEM; + + for (i = 0; i < 3; i++) { + queue_priority_map[i][0] = i; + queue_priority_map[i][1] = i; + } + queue_priority_map[i][0] = -1; + queue_priority_map[i][1] = -1; + + pdata->queue_priority_mapping = queue_priority_map; + + pdata->default_queue = 0; + + prop = of_find_property(node, "ti,edma-xbar-event-map", &sz); + if (prop) + ret = edma_xbar_event_map(dev, node, pdata, sz); + + return ret; +} + +static struct of_dma_filter_info edma_filter_info = { + .filter_fn = edma_filter_fn, +}; + +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, + struct device_node *node) +{ + struct edma_soc_info *info; + int ret; + + info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); -static int __init edma_probe(struct platform_device *pdev) + ret = edma_of_parse_dt(dev, node, info); + if (ret) + return ERR_PTR(ret); + + dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); + of_dma_controller_register(dev->of_node, of_dma_simple_xlate, + &edma_filter_info); + + return info; +} +#else +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, + struct device_node *node) +{ + return ERR_PTR(-ENOSYS); +} +#endif + +static int edma_probe(struct platform_device *pdev) { struct edma_soc_info **info = pdev->dev.platform_data; - const s8 (*queue_priority_mapping)[2]; - const s8 (*queue_tc_mapping)[2]; + struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL}; + s8 (*queue_priority_mapping)[2]; + s8 (*queue_tc_mapping)[2]; int i, j, off, ln, found = 0; int status = -1; const s16 (*rsv_chans)[2]; const s16 (*rsv_slots)[2]; + const s16 (*xbar_chans)[2]; int irq[EDMA_MAX_CC] = {0, 0}; int err_irq[EDMA_MAX_CC] = {0, 0}; struct resource *r[EDMA_MAX_CC] = {NULL}; - resource_size_t len[EDMA_MAX_CC]; + struct resource res[EDMA_MAX_CC]; char res_name[10]; char irq_name[10]; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + int ret; + + if (node) { + /* Check if this is a second instance registered */ + if (arch_num_cc) { + dev_err(dev, "only one EDMA instance is supported via DT\n"); + return -ENODEV; + } + + ninfo[0] = edma_setup_info_from_dt(dev, node); + if (IS_ERR(ninfo[0])) { + dev_err(dev, "failed to get DT data\n"); + return PTR_ERR(ninfo[0]); + } + + info = ninfo; + } if (!info) return -ENODEV; + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + return ret; + } + for (j = 0; j < EDMA_MAX_CC; j++) { - sprintf(res_name, "edma_cc%d", j); - r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, + if (!info[j]) { + if (!found) + return -ENODEV; + break; + } + if (node) { + ret = of_address_to_resource(node, j, &res[j]); + if (!ret) + r[j] = &res[j]; + } else { + sprintf(res_name, "edma_cc%d", j); + r[j] = platform_get_resource_byname(pdev, + IORESOURCE_MEM, res_name); - if (!r[j] || !info[j]) { + } + if (!r[j]) { if (found) break; else @@ -1422,26 +1614,14 @@ static int __init edma_probe(struct platform_device *pdev) found = 1; } - len[j] = resource_size(r[j]); - - r[j] = request_mem_region(r[j]->start, len[j], - dev_name(&pdev->dev)); - if (!r[j]) { - status = -EBUSY; - goto fail1; - } - - edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); - if (!edmacc_regs_base[j]) { - status = -EBUSY; - goto fail1; - } + edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]); + if (IS_ERR(edmacc_regs_base[j])) + return PTR_ERR(edmacc_regs_base[j]); - edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL); - if (!edma_cc[j]) { - status = -ENOMEM; - goto fail1; - } + edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma), + GFP_KERNEL); + if (!edma_cc[j]) + return -ENOMEM; edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, EDMA_MAX_DMACH); @@ -1472,7 +1652,7 @@ static int __init edma_probe(struct platform_device *pdev) off = rsv_chans[i][0]; ln = rsv_chans[i][1]; clear_bits(off, ln, - edma_cc[j]->edma_unused); + edma_cc[j]->edma_unused); } } @@ -1488,26 +1668,48 @@ static int __init edma_probe(struct platform_device *pdev) } } - sprintf(irq_name, "edma%d", j); - irq[j] = platform_get_irq_byname(pdev, irq_name); + /* Clear the xbar mapped channels in unused list */ + xbar_chans = info[j]->xbar_chans; + if (xbar_chans) { + for (i = 0; xbar_chans[i][1] != -1; i++) { + off = xbar_chans[i][1]; + clear_bits(off, 1, + edma_cc[j]->edma_unused); + } + } + + if (node) { + irq[j] = irq_of_parse_and_map(node, 0); + } else { + sprintf(irq_name, "edma%d", j); + irq[j] = platform_get_irq_byname(pdev, irq_name); + } edma_cc[j]->irq_res_start = irq[j]; - status = request_irq(irq[j], dma_irq_handler, 0, "edma", - &pdev->dev); + status = devm_request_irq(&pdev->dev, irq[j], + dma_irq_handler, 0, "edma", + &pdev->dev); if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + dev_dbg(&pdev->dev, + "devm_request_irq %d failed --> %d\n", irq[j], status); - goto fail; + return status; } - sprintf(irq_name, "edma%d_err", j); - err_irq[j] = platform_get_irq_byname(pdev, irq_name); + if (node) { + err_irq[j] = irq_of_parse_and_map(node, 2); + } else { + sprintf(irq_name, "edma%d_err", j); + err_irq[j] = platform_get_irq_byname(pdev, irq_name); + } edma_cc[j]->irq_res_end = err_irq[j]; - status = request_irq(err_irq[j], dma_ccerr_handler, 0, - "edma_error", &pdev->dev); + status = devm_request_irq(&pdev->dev, err_irq[j], + dma_ccerr_handler, 0, + "edma_error", &pdev->dev); if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", + dev_dbg(&pdev->dev, + "devm_request_irq %d failed --> %d\n", err_irq[j], status); - goto fail; + return status; } for (i = 0; i < edma_cc[j]->num_channels; i++) @@ -1541,46 +1743,20 @@ static int __init edma_probe(struct platform_device *pdev) arch_num_cc++; } - if (tc_errs_handled) { - status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, - "edma_tc0", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", - IRQ_TCERRINT0, status); - return status; - } - status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, - "edma_tc1", &pdev->dev); - if (status < 0) { - dev_dbg(&pdev->dev, "request_irq %d --> %d\n", - IRQ_TCERRINT, status); - return status; - } - } - return 0; - -fail: - for (i = 0; i < EDMA_MAX_CC; i++) { - if (err_irq[i]) - free_irq(err_irq[i], &pdev->dev); - if (irq[i]) - free_irq(irq[i], &pdev->dev); - } -fail1: - for (i = 0; i < EDMA_MAX_CC; i++) { - if (r[i]) - release_mem_region(r[i]->start, len[i]); - if (edmacc_regs_base[i]) - iounmap(edmacc_regs_base[i]); - kfree(edma_cc[i]); - } - return status; } +static const struct of_device_id edma_of_ids[] = { + { .compatible = "ti,edma3", }, + {} +}; static struct platform_driver edma_driver = { - .driver.name = "edma", + .driver = { + .name = "edma", + .of_match_table = edma_of_ids, + }, + .probe = edma_probe, }; static int __init edma_init(void) diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig deleted file mode 100644 index 66894f736d0..00000000000 --- a/arch/arm/configs/ap4evb_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_BLK_DEV_INITRD=y -CONFIG_SLAB=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y -CONFIG_ARCH_SH7372=y -CONFIG_MACH_AP4EVB=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200" -CONFIG_KEXEC=y -CONFIG_PM=y -# CONFIG_SUSPEND is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_NAND=y -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=8 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig index 0f2d80da737..fae939d3d7f 100644 --- a/arch/arm/configs/armadillo800eva_defconfig +++ b/arch/arm/configs/armadillo800eva_defconfig @@ -86,7 +86,7 @@ CONFIG_TOUCHSCREEN_ST1232=y # CONFIG_SERIO is not set # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=8 +CONFIG_SERIAL_SH_SCI_NR_UARTS=9 CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index 8b099349c4b..75502c4d222 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -18,7 +18,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91RM9200=y CONFIG_MACH_ONEARM=y -CONFIG_ARCH_AT91RM9200DK=y CONFIG_MACH_AT91RM9200EK=y CONFIG_MACH_CSB337=y CONFIG_MACH_CSB637=y diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index ce987211a60..34e9780e63b 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -55,14 +55,11 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set -# CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_TTY_PRINTK=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_BCM2835=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_BCM2835=y @@ -70,11 +67,27 @@ CONFIG_SPI=y CONFIG_SPI_BCM2835=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FB_SIMPLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig index 6524cdf3b08..845f5cdf62b 100644 --- a/arch/arm/configs/bockw_defconfig +++ b/arch/arm/configs/bockw_defconfig @@ -31,6 +31,7 @@ CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp" CONFIG_CMDLINE_FORCE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_UNIX=y CONFIG_INET=y @@ -48,6 +49,14 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_M25P80=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y # CONFIG_NET_CADENCE is not set # CONFIG_NET_VENDOR_BROADCOM is not set @@ -71,7 +80,23 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=6 CONFIG_SERIAL_SH_SCI_CONSOLE=y # CONFIG_HW_RANDOM is not set # CONFIG_HWMON is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_I2C=y +CONFIG_I2C_RCAR=y +CONFIG_SPI=y +CONFIG_SPI_SH_HSPI=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_RCAR_PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_SH_MMCIF=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_RX8581=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y # CONFIG_IOMMU_SUPPORT is not set diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig deleted file mode 100644 index 54571082d92..00000000000 --- a/arch/arm/configs/bonito_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE=y -CONFIG_ARCH_R8A7740=y -CONFIG_MACH_BONITO=y -# CONFIG_SH_TIMER_TMU is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_FORCE_MAX_ZONEORDER=12 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel" -CONFIG_KEXEC=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_SUSPEND is not set -CONFIG_PM_RUNTIME=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_MTD=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_ARM_INTEGRATOR=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=9 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_UIO=y -CONFIG_UIO_PDRV=y -CONFIG_UIO_PDRV_GENIRQ=y -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig index 1cd94c36321..9e8c8316d6b 100644 --- a/arch/arm/configs/clps711x_defconfig +++ b/arch/arm/configs/clps711x_defconfig @@ -31,21 +31,18 @@ CONFIG_EP7211_DONGLE=y # CONFIG_WIRELESS is not set CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_AUTCPU12=y CONFIG_MTD_PLATRAM=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_GPIO=y CONFIG_NETDEVICES=y # CONFIG_NET_CADENCE is not set # CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set CONFIG_CS89x0=y CONFIG_CS89x0_PLATFORM=y # CONFIG_NET_VENDOR_FARADAY is not set @@ -63,7 +60,11 @@ CONFIG_CS89x0_PLATFORM=y # CONFIG_VT is not set CONFIG_SERIAL_CLPS711X_CONSOLE=y # CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_GPIO=y CONFIG_SPI=y +CONFIG_SPI_CLPS711X=y +CONFIG_GPIO_CLPS711X=y CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_HWMON is not set CONFIG_FB=y @@ -87,4 +88,3 @@ CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 227abf9cc60..ad7dfbbafa4 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -50,6 +50,7 @@ CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_CROS_EC=y # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_CYAPA=y @@ -104,6 +105,8 @@ CONFIG_MMC_SDHCI_S3C=y CONFIG_MMC_DW=y CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig new file mode 100644 index 00000000000..62e968cac9d --- /dev/null +++ b/arch/arm/configs/keystone_defconfig @@ -0,0 +1,157 @@ +# CONFIG_SWAP is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_ELF_CORE is not set +# CONFIG_BASE_FULL is not set +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_ARCH_KEYSTONE=y +CONFIG_ARM_LPAE=y +CONFIG_SMP=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IPGRE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y +CONFIG_INET_AH=y +CONFIG_INET_IPCOMP=y +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_CPU=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_CLUSTERIP=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP_SCTP=y +CONFIG_VLAN_8021Q=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_CMA=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_PLATRAM=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_UBI=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_NETDEVICES=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_SPI=y +CONFIG_SPI_SPIDEV=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_USB_SUPPORT is not set +CONFIG_DMADEVICES=y +CONFIG_COMMON_CLK_DEBUG=y +CONFIG_MEMORY=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_WBUF_VERIFY=y +CONFIG_UBIFS_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index a1d8252e9ec..0f2aa61911a 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,4 +1,3 @@ -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -31,6 +30,7 @@ CONFIG_MACH_T5325=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_CLOUDBOX_DT=y +CONFIG_MACH_DB88F628X_BP_DT=y CONFIG_MACH_DLINK_KIRKWOOD_DT=y CONFIG_MACH_DOCKSTAR_DT=y CONFIG_MACH_DREAMPLUG_DT=y @@ -50,14 +50,19 @@ CONFIG_MACH_NETSPACE_V2_DT=y CONFIG_MACH_NSA310_DT=y CONFIG_MACH_OPENBLOCKS_A6_DT=y CONFIG_MACH_READYNAS_DT=y +CONFIG_MACH_SHEEVAPLUG_DT=y CONFIG_MACH_TOPKICK_DT=y CONFIG_MACH_TS219_DT=y # CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_PCI_MVEBU=y CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_IDLE=y CONFIG_NET=y CONFIG_PACKET=y @@ -68,14 +73,12 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IPV6 is not set -CONFIG_NET_DSA=y CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -140,6 +143,7 @@ CONFIG_HID_TOPSEED=y CONFIG_HID_THRUSTMASTER=y CONFIG_HID_ZEROPLUS=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_PRINTER=m diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig index f6e585b353a..1ad028023a6 100644 --- a/arch/arm/configs/kzm9g_defconfig +++ b/arch/arm/configs/kzm9g_defconfig @@ -84,9 +84,12 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_SH_MOBILE=y CONFIG_GPIO_PCF857X=y # CONFIG_HWMON is not set +CONFIG_MFD_AS3711=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_AS3711=y CONFIG_FB=y CONFIG_FB_SH_MOBILE_LCDC=y +CONFIG_BACKLIGHT_AS3711=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_FB_SH_MOBILE_MERAM=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 2e67a272df7..340d550c12b 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1,6 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_ARCH_SIRF=y @@ -31,10 +32,12 @@ CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y +CONFIG_SUN4I_EMAC=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y CONFIG_SERIO_AMBAKMI=y +CONFIG_MDIO_SUN4I=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y @@ -46,6 +49,8 @@ CONFIG_SERIAL_SIRFSOC=y CONFIG_SERIAL_SIRFSOC_CONSOLE=y CONFIG_SERIAL_VT8500=y CONFIG_SERIAL_VT8500_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_SI=y CONFIG_I2C=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index f3e8ae001ff..731814e2c18 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y # CONFIG_CACHE_L2X0 is not set # CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y CONFIG_SMP=y CONFIG_AEABI=y CONFIG_HIGHMEM=y @@ -60,6 +62,8 @@ CONFIG_USB_SUPPORT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_HCD=y CONFIG_MMC=y CONFIG_MMC_MVSDIO=y CONFIG_NEW_LEDS=y @@ -96,5 +100,3 @@ CONFIG_TIMER_STATS=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index abbe31937c6..2ac0ffb12f0 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -210,6 +210,8 @@ CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y CONFIG_USB_LIBUSUAL=y CONFIG_USB_TEST=y +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_DEBUG_FILES=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index f7ba316164d..1effb43dab8 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -21,8 +21,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_TEGRA=y CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y @@ -36,7 +36,6 @@ CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_KEXEC=y -CONFIG_AUTO_ZRELADDR=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_IDLE=y @@ -81,7 +80,6 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_CMA=y CONFIG_MTD=y -CONFIG_MTD_CHAR=y CONFIG_MTD_M25P80=y CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y @@ -105,8 +103,8 @@ CONFIG_BRCMFMAC=m CONFIG_RT2X00=y CONFIG_RT2800USB=m CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_TEGRA=y CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_TEGRA=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MPU3050=y # CONFIG_LEGACY_PTYS is not set @@ -121,6 +119,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_TEGRA=y CONFIG_SPI=y +CONFIG_SPI_TEGRA114=y CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y CONFIG_GPIO_PCA953X_IRQ=y @@ -129,14 +128,15 @@ CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y CONFIG_POWER_SUPPLY=y CONFIG_BATTERY_SBS=y +CONFIG_CHARGER_TPS65090=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_SENSORS_LM90=y -CONFIG_MFD_TPS6586X=y -CONFIG_MFD_TPS65910=y CONFIG_MFD_MAX8907=y -CONFIG_MFD_TPS65090=y CONFIG_MFD_PALMAS=y +CONFIG_MFD_TPS65090=y +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y @@ -171,6 +171,7 @@ CONFIG_SND=y # CONFIG_SND_USB is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_TEGRA=y +CONFIG_SND_SOC_TEGRA_RT5640=y CONFIG_SND_SOC_TEGRA_WM8753=y CONFIG_SND_SOC_TEGRA_WM8903=y CONFIG_SND_SOC_TEGRA_TRIMSLICE=y @@ -190,7 +191,13 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_PALMAS=y @@ -203,7 +210,6 @@ CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y -CONFIG_AK8975=y CONFIG_MFD_NVEC=y CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y @@ -213,6 +219,7 @@ CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_MEMORY=y CONFIG_IIO=y +CONFIG_AK8975=y CONFIG_PWM=y CONFIG_PWM_TEGRA=y CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig index 374000ec4e4..fd81a1b99cc 100644 --- a/arch/arm/configs/u300_defconfig +++ b/arch/arm/configs/u300_defconfig @@ -1,7 +1,8 @@ -CONFIG_EXPERIMENTAL=y # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_EXPERT=y # CONFIG_AIO is not set @@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_CFQ is not set +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_U300=y -CONFIG_MACH_U300=y -CONFIG_MACH_U300_BS335=y CONFIG_MACH_U300_SPIDUMMY=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -44,14 +42,15 @@ CONFIG_I2C=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y -CONFIG_MMC_CLKGATE=y +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_ARMMMCI=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set @@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 05ee9eebad6..a5fef710af3 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -136,7 +136,11 @@ * assumes FIQs are enabled, and that the processor is in SVC mode. */ .macro save_and_disable_irqs, oldcpsr +#ifdef CONFIG_CPU_V7M + mrs \oldcpsr, primask +#else mrs \oldcpsr, cpsr +#endif disable_irq .endm @@ -150,7 +154,11 @@ * guarantee that this will preserve the flags. */ .macro restore_irqs_notrace, oldcpsr +#ifdef CONFIG_CPU_V7M + msr primask, \oldcpsr +#else msr cpsr_c, \oldcpsr +#endif .endm .macro restore_irqs, oldcpsr @@ -229,7 +237,14 @@ #endif .endm -#ifdef CONFIG_THUMB2_KERNEL +#if defined(CONFIG_CPU_V7M) + /* + * setmode is used to assert to be in svc mode during boot. For v7-M + * this is done in __v7m_setup, so setmode can be empty here. + */ + .macro setmode, mode, reg + .endm +#elif defined(CONFIG_THUMB2_KERNEL) .macro setmode, mode, reg mov \reg, #\mode msr cpsr_c, \reg diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index bff71388e72..17d0ae8672f 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -320,9 +320,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma, } #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE -static inline void flush_kernel_dcache_page(struct page *page) -{ -} +extern void flush_kernel_dcache_page(struct page *); #define flush_dcache_mmap_lock(mapping) \ spin_lock_irq(&(mapping)->tree_lock) diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index 1f3262e99d8..cedd3721318 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val) isb(); } +static inline unsigned int get_auxcr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); + return val; +} + +static inline void set_auxcr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR" + : : "r" (val)); + isb(); +} + #ifndef CONFIG_SMP extern void adjust_cr(unsigned long mask, unsigned long set); #endif diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 7652712d1d1..d7deb62554c 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -10,6 +10,22 @@ #define CPUID_TLBTYPE 3 #define CPUID_MPIDR 5 +#ifdef CONFIG_CPU_V7M +#define CPUID_EXT_PFR0 0x40 +#define CPUID_EXT_PFR1 0x44 +#define CPUID_EXT_DFR0 0x48 +#define CPUID_EXT_AFR0 0x4c +#define CPUID_EXT_MMFR0 0x50 +#define CPUID_EXT_MMFR1 0x54 +#define CPUID_EXT_MMFR2 0x58 +#define CPUID_EXT_MMFR3 0x5c +#define CPUID_EXT_ISAR0 0x60 +#define CPUID_EXT_ISAR1 0x64 +#define CPUID_EXT_ISAR2 0x68 +#define CPUID_EXT_ISAR3 0x6c +#define CPUID_EXT_ISAR4 0x70 +#define CPUID_EXT_ISAR5 0x74 +#else #define CPUID_EXT_PFR0 "c1, 0" #define CPUID_EXT_PFR1 "c1, 1" #define CPUID_EXT_DFR0 "c1, 2" @@ -24,6 +40,7 @@ #define CPUID_EXT_ISAR3 "c2, 3" #define CPUID_EXT_ISAR4 "c2, 4" #define CPUID_EXT_ISAR5 "c2, 5" +#endif #define MPIDR_SMP_BITMASK (0x3 << 30) #define MPIDR_SMP_VALUE (0x2 << 30) @@ -32,6 +49,8 @@ #define MPIDR_HWID_BITMASK 0xFFFFFF +#define MPIDR_INVALID (~MPIDR_HWID_BITMASK) + #define MPIDR_LEVEL_BITS 8 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) @@ -79,7 +98,23 @@ extern unsigned int processor_id; __val; \ }) -#else /* ifdef CONFIG_CPU_CP15 */ +#elif defined(CONFIG_CPU_V7M) + +#include <asm/io.h> +#include <asm/v7m.h> + +#define read_cpuid(reg) \ + ({ \ + WARN_ON_ONCE(1); \ + 0; \ + }) + +static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset) +{ + return readl(BASEADDR_V7M_SCB + offset); +} + +#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */ /* * read_cpuid and read_cpuid_ext should only ever be called on machines that @@ -106,7 +141,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } -#else /* ifdef CONFIG_CPU_CP15 */ +#elif defined(CONFIG_CPU_V7M) + +static inline unsigned int __attribute_const__ read_cpuid_id(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); +} + +#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ static inline unsigned int __attribute_const__ read_cpuid_id(void) { diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index ea289e1435e..c81adc08b3f 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -117,10 +117,37 @@ # endif #endif +#if defined(CONFIG_CPU_V7M) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE nop +# endif +#endif + #if !defined(_CACHE) && !defined(MULTI_CACHE) #error Unknown cache maintenance model #endif +#ifndef __ASSEMBLER__ +extern inline void nop_flush_icache_all(void) { } +extern inline void nop_flush_kern_cache_all(void) { } +extern inline void nop_flush_kern_cache_louis(void) { } +extern inline void nop_flush_user_cache_all(void) { } +extern inline void nop_flush_user_cache_range(unsigned long a, + unsigned long b, unsigned int c) { } + +extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { } +extern inline int nop_coherent_user_range(unsigned long a, + unsigned long b) { return 0; } +extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { } + +extern inline void nop_dma_flush_range(const void *a, const void *b) { } + +extern inline void nop_dma_map_area(const void *s, size_t l, int f) { } +extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } +#endif + #ifndef MULTI_CACHE #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h index b6e9f2c108b..6b70f1b46a6 100644 --- a/arch/arm/include/asm/glue-df.h +++ b/arch/arm/include/asm/glue-df.h @@ -95,6 +95,14 @@ # endif #endif +#ifdef CONFIG_CPU_ABRT_NOMMU +# ifdef CPU_DABORT_HANDLER +# define MULTI_DABORT 1 +# else +# define CPU_DABORT_HANDLER nommu_early_abort +# endif +#endif + #ifndef CPU_DABORT_HANDLER #error Unknown data abort handler type #endif diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h index ac1dd54724b..e6168c0c18e 100644 --- a/arch/arm/include/asm/glue-proc.h +++ b/arch/arm/include/asm/glue-proc.h @@ -230,6 +230,24 @@ # endif #endif +#ifdef CONFIG_CPU_PJ4B +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_pj4b +# endif +#endif + +#ifdef CONFIG_CPU_V7M +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_v7m +# endif +#endif + #ifndef MULTI_CPU #define cpu_proc_init __glue(CPU_NAME,_proc_init) #define cpu_proc_fin __glue(CPU_NAME,_proc_fin) diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h deleted file mode 100644 index 2811c7e2cfd..00000000000 --- a/arch/arm/include/asm/hardware/pci_v3.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * arch/arm/include/asm/hardware/pci_v3.h - * - * Internal header file PCI V3 chip - * - * Copyright (C) ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef ASM_ARM_HARDWARE_PCI_V3_H -#define ASM_ARM_HARDWARE_PCI_V3_H - -/* ------------------------------------------------------------------------------- - * V3 Local Bus to PCI Bridge definitions - * ------------------------------------------------------------------------------- - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -#endif diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h index 1e6cca55c75..3b763d6652a 100644 --- a/arch/arm/include/asm/irqflags.h +++ b/arch/arm/include/asm/irqflags.h @@ -8,6 +8,16 @@ /* * CPU interrupt mask handling. */ +#ifdef CONFIG_CPU_V7M +#define IRQMASK_REG_NAME_R "primask" +#define IRQMASK_REG_NAME_W "primask" +#define IRQMASK_I_BIT 1 +#else +#define IRQMASK_REG_NAME_R "cpsr" +#define IRQMASK_REG_NAME_W "cpsr_c" +#define IRQMASK_I_BIT PSR_I_BIT +#endif + #if __LINUX_ARM_ARCH__ >= 6 static inline unsigned long arch_local_irq_save(void) @@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void) unsigned long flags; asm volatile( - " mrs %0, cpsr @ arch_local_irq_save\n" + " mrs %0, " IRQMASK_REG_NAME_R " @ arch_local_irq_save\n" " cpsid i" : "=r" (flags) : : "memory", "cc"); return flags; @@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void) { unsigned long flags; asm volatile( - " mrs %0, cpsr @ local_save_flags" + " mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags" : "=r" (flags) : : "memory", "cc"); return flags; } @@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void) static inline void arch_local_irq_restore(unsigned long flags) { asm volatile( - " msr cpsr_c, %0 @ local_irq_restore" + " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" : : "r" (flags) : "memory", "cc"); @@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags) static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags & PSR_I_BIT; + return flags & IRQMASK_I_BIT; } -#endif -#endif +#endif /* ifdef __KERNEL__ */ +#endif /* ifndef __ASM_ARM_IRQFLAGS_H */ diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 308ad7d6f98..75bf07910b8 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include <linux/types.h> + #ifndef __ASSEMBLY__ struct tag; @@ -16,8 +18,10 @@ struct pt_regs; struct smp_operations; #ifdef CONFIG_SMP #define smp_ops(ops) (&(ops)) +#define smp_init_ops(ops) (&(ops)) #else #define smp_ops(ops) (struct smp_operations *)NULL +#define smp_init_ops(ops) (bool (*)(void))NULL #endif struct machine_desc { @@ -41,6 +45,7 @@ struct machine_desc { unsigned char reserve_lp2 :1; /* never has lp2 */ char restart_mode; /* default restart mode */ struct smp_operations *smp; /* SMP operations */ + bool (*smp_init)(void); void (*fixup)(struct tag *, char **, struct meminfo *); void (*reserve)(void);/* reserve mem blocks */ diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 7d2c3c84380..a1c90d7feb0 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -16,6 +16,7 @@ struct pci_sys_data; struct pci_ops; struct pci_bus; +struct device; struct hw_pci { #ifdef CONFIG_PCI_DOMAINS @@ -68,7 +69,16 @@ struct pci_sys_data { /* * Call this with your hw_pci struct to initialise the PCI system. */ -void pci_common_init(struct hw_pci *); +void pci_common_init_dev(struct device *, struct hw_pci *); + +/* + * Compatibility wrapper for older platforms that do not care about + * passing the parent device. + */ +static inline void pci_common_init(struct hw_pci *hw) +{ + pci_common_init_dev(NULL, hw); +} /* * Setup early fixed I/O mapping. @@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops; extern int via82c505_setup(int nr, struct pci_sys_data *); extern void via82c505_init(void *sysdata); -extern struct pci_ops pci_v3_ops; -extern int pci_v3_setup(int nr, struct pci_sys_data *); -extern void pci_v3_preinit(void); -extern void pci_v3_postinit(void); - #endif /* __ASM_MACH_PCI_H */ diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h index 7ec60d6075b..0642228ff78 100644 --- a/arch/arm/include/asm/pgtable-nommu.h +++ b/arch/arm/include/asm/pgtable-nommu.h @@ -79,8 +79,6 @@ extern unsigned int kobjsize(const void *objp); * No page table caches to initialise. */ #define pgtable_cache_init() do { } while (0) -#define io_remap_pfn_range remap_pfn_range - /* * All 32bit addresses are effectively valid for vmalloc... diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 9bcd262a900..229e0dde9c7 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -318,13 +318,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #define HAVE_ARCH_UNMAPPED_AREA #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN -/* - * remap a physical page `pfn' of size `size' with page protection `prot' - * into virtual address `from' - */ -#define io_remap_pfn_range(vma,from,pfn,size,prot) \ - remap_pfn_range(vma, from, pfn, size, prot) - #define pgtable_cache_init() do { } while (0) #endif /* !__ASSEMBLY__ */ diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index ce0dbe7c162..c4ae171850f 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -32,5 +32,14 @@ struct psci_operations { }; extern struct psci_operations psci_ops; +extern struct smp_operations psci_smp_ops; + +#ifdef CONFIG_ARM_PSCI +void psci_init(void); +bool psci_smp_available(void); +#else +static inline void psci_init(void) { } +static inline bool psci_smp_available(void) { return false; } +#endif #endif /* __ASM_ARM_PSCI_H */ diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 3d52ee1bfb3..04c99f36ff7 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -45,6 +45,7 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { +#ifndef CONFIG_CPU_V7M unsigned long mode = regs->ARM_cpsr & MODE_MASK; /* @@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs) regs->ARM_cpsr |= USR_MODE; return 0; +#else /* ifndef CONFIG_CPU_V7M */ + return 1; +#endif } static inline long regs_return_value(struct pt_regs *regs) diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index aaa61b6f50f..e7898320273 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h @@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void) /* * Logical CPU mapping. */ -extern int __cpu_logical_map[]; +extern u32 __cpu_logical_map[]; #define cpu_logical_map(cpu) __cpu_logical_map[cpu] /* * Retrieve logical cpu index corresponding to a given MPIDR[23:0] diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h index dfd386d0c02..720ea0320a6 100644 --- a/arch/arm/include/asm/system_info.h +++ b/arch/arm/include/asm/system_info.h @@ -11,6 +11,7 @@ #define CPU_ARCH_ARMv5TEJ 7 #define CPU_ARCH_ARMv6 8 #define CPU_ARCH_ARMv7 9 +#define CPU_ARCH_ARMv7M 10 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h new file mode 100644 index 00000000000..fa88d09fa3d --- /dev/null +++ b/arch/arm/include/asm/v7m.h @@ -0,0 +1,44 @@ +/* + * Common defines for v7m cpus + */ +#define V7M_SCS_ICTR IOMEM(0xe000e004) +#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f + +#define BASEADDR_V7M_SCB IOMEM(0xe000ed00) + +#define V7M_SCB_CPUID 0x00 + +#define V7M_SCB_ICSR 0x04 +#define V7M_SCB_ICSR_PENDSVSET (1 << 28) +#define V7M_SCB_ICSR_PENDSVCLR (1 << 27) +#define V7M_SCB_ICSR_RETTOBASE (1 << 11) + +#define V7M_SCB_VTOR 0x08 + +#define V7M_SCB_SCR 0x10 +#define V7M_SCB_SCR_SLEEPDEEP (1 << 2) + +#define V7M_SCB_CCR 0x14 +#define V7M_SCB_CCR_STKALIGN (1 << 9) + +#define V7M_SCB_SHPR2 0x1c +#define V7M_SCB_SHPR3 0x20 + +#define V7M_SCB_SHCSR 0x24 +#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18) +#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) +#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) + +#define V7M_xPSR_FRAMEPTRALIGN 0x00000200 +#define V7M_xPSR_EXCEPTIONNO 0x000001ff + +/* + * When branching to an address that has bits [31:28] == 0xf an exception return + * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP + * extension Bit [4] defines if the exception frame has space allocated for FP + * state information, SBOP otherwise. Bit [3] defines the mode that is returned + * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used + * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. + */ +#define EXC_RET_STACK_MASK 0x00000004 +#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S new file mode 100644 index 00000000000..9aef9ba3f4f --- /dev/null +++ b/arch/arm/include/debug/keystone.S @@ -0,0 +1,43 @@ +/* + * Early serial debug output macro for Keystone SOCs + * + * Copyright 2013 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Based on RMKs low level debug code. + * Copyright (C) 1994-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/serial_reg.h> + +#define UART_SHIFT 2 +#if defined(CONFIG_DEBUG_KEYSTONE_UART0) +#define UART_PHYS 0x02530c00 +#define UART_VIRT 0xfeb30c00 +#elif defined(CONFIG_DEBUG_KEYSTONE_UART1) +#define UART_PHYS 0x02531000 +#define UART_VIRT 0xfeb31000 +#endif + + .macro addruart, rp, rv, tmp + ldr \rv, =UART_VIRT @ physical base address + ldr \rp, =UART_PHYS @ virtual base address + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx + .endm diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S index df191afa3be..6517311a1c9 100644 --- a/arch/arm/include/debug/mvebu.S +++ b/arch/arm/include/debug/mvebu.S @@ -11,7 +11,12 @@ * published by the Free Software Foundation. */ +#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE +#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000 +#else #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 +#endif + #define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000 .macro addruart, rp, rv, tmp diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S new file mode 100644 index 00000000000..cfd883e6958 --- /dev/null +++ b/arch/arm/include/debug/rockchip.S @@ -0,0 +1,42 @@ +/* + * Early serial output macro for Rockchip SoCs + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#if defined(CONFIG_DEBUG_RK29_UART0) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000 +#elif defined(CONFIG_DEBUG_RK29_UART1) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 +#elif defined(CONFIG_DEBUG_RK29_UART2) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 +#elif defined(CONFIG_DEBUG_RK3X_UART0) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000 +#elif defined(CONFIG_DEBUG_RK3X_UART1) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000 +#elif defined(CONFIG_DEBUG_RK3X_UART2) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000 +#elif defined(CONFIG_DEBUG_RK3X_UART3) +#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000 +#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000 +#endif + + .macro addruart, rp, rv, tmp + ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE + ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S index 8ae8e4ab34b..6f04f08a203 100644 --- a/arch/arm/mach-u300/include/mach/debug-macro.S +++ b/arch/arm/include/debug/u300.S @@ -1,14 +1,11 @@ /* - * - * arch-arm/mach-u300/include/mach/debug-macro.S - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB + * Copyright (C) 2006-2013 ST-Ericsson AB * License terms: GNU General Public License (GPL) version 2 * Debugging macro include header. * Author: Linus Walleij <linus.walleij@stericsson.com> */ -#include <mach/hardware.h> +#define U300_SLOW_PER_PHYS_BASE 0xc0010000 +#define U300_SLOW_PER_VIRT_BASE 0xff000000 .macro addruart, rp, rv, tmp /* If we move the address using MMU, use this. */ diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h index 96ee0929790..5af0ed1b825 100644 --- a/arch/arm/include/uapi/asm/ptrace.h +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -34,28 +34,47 @@ /* * PSR bits + * Note on V7M there is no mode contained in the PSR */ #define USR26_MODE 0x00000000 #define FIQ26_MODE 0x00000001 #define IRQ26_MODE 0x00000002 #define SVC26_MODE 0x00000003 +#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M) +/* + * Use 0 here to get code right that creates a userspace + * or kernel space thread. + */ +#define USR_MODE 0x00000000 +#define SVC_MODE 0x00000000 +#else #define USR_MODE 0x00000010 +#define SVC_MODE 0x00000013 +#endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 -#define SVC_MODE 0x00000013 #define ABT_MODE 0x00000017 #define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b #define SYSTEM_MODE 0x0000001f #define MODE32_BIT 0x00000010 #define MODE_MASK 0x0000001f -#define PSR_T_BIT 0x00000020 -#define PSR_F_BIT 0x00000040 -#define PSR_I_BIT 0x00000080 -#define PSR_A_BIT 0x00000100 -#define PSR_E_BIT 0x00000200 -#define PSR_J_BIT 0x01000000 -#define PSR_Q_BIT 0x08000000 + +#define V4_PSR_T_BIT 0x00000020 /* >= V4T, but not V7M */ +#define V7M_PSR_T_BIT 0x01000000 +#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M) +#define PSR_T_BIT V7M_PSR_T_BIT +#else +/* for compatibility */ +#define PSR_T_BIT V4_PSR_T_BIT +#endif + +#define PSR_F_BIT 0x00000040 /* >= V4, but not V7M */ +#define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */ +#define PSR_A_BIT 0x00000100 /* >= V6, but not V7M */ +#define PSR_E_BIT 0x00000200 /* >= V6, but not V7M */ +#define PSR_J_BIT 0x01000000 /* >= V5J, but not V7M */ +#define PSR_Q_BIT 0x08000000 /* >= V5E, including V7M */ #define PSR_V_BIT 0x10000000 #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5f3338eacad..f4285b5ffb0 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -15,7 +15,7 @@ CFLAGS_REMOVE_return_address.o = -pg # Object file lists. -obj-y := elf.o entry-armv.o entry-common.o irq.o opcodes.o \ +obj-y := elf.o entry-common.o irq.o opcodes.o \ process.o ptrace.o return_address.o sched_clock.o \ setup.o signal.o stacktrace.o sys_arm.o time.o traps.o @@ -23,6 +23,12 @@ obj-$(CONFIG_ATAGS) += atags_parse.o obj-$(CONFIG_ATAGS_PROC) += atags_proc.o obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o +ifeq ($(CONFIG_CPU_V7M),y) +obj-y += entry-v7m.o +else +obj-y += entry-armv.o +endif + obj-$(CONFIG_OC_ETM) += etm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ISA_DMA_API) += dma.o @@ -82,6 +88,9 @@ obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o -obj-$(CONFIG_ARM_PSCI) += psci.o +ifeq ($(CONFIG_ARM_PSCI),y) +obj-y += psci.o +obj-$(CONFIG_SMP) += psci_smp.o +endif extra-y := $(head-y) vmlinux.lds diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index b2ed73c4548..261fcc82616 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) return 0; } -static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) +static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, + struct list_head *head) { struct pci_sys_data *sys = NULL; int ret; @@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) if (hw->scan) sys->bus = hw->scan(nr, sys); else - sys->bus = pci_scan_root_bus(NULL, sys->busnr, + sys->bus = pci_scan_root_bus(parent, sys->busnr, hw->ops, sys, &sys->resources); if (!sys->bus) @@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) } } -void pci_common_init(struct hw_pci *hw) +void pci_common_init_dev(struct device *parent, struct hw_pci *hw) { struct pci_sys_data *sys; LIST_HEAD(head); @@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw) pci_add_flags(PCI_REASSIGN_ALL_RSRC); if (hw->preinit) hw->preinit(); - pcibios_init_hw(hw, &head); + pcibios_init_hw(parent, hw, &head); if (hw->postinit) hw->postinit(); diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 5af04f6daa3..5859c8bc727 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void) u32 i, j, cpuidx = 1; u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; - u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX }; + u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; bool bootcpu_valid = false; cpus = of_find_node_by_path("/cpus"); @@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void) for_each_child_of_node(cpus, cpu) { u32 hwid; + if (of_node_cmp(cpu->type, "cpu")) + continue; + pr_debug(" * %s...\n", cpu->full_name); /* * A device tree containing CPU nodes with missing "reg" @@ -149,9 +152,10 @@ void __init arm_dt_init_cpu_maps(void) tmp_map[i] = hwid; } - if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], " - "fall back to default cpu_logical_map\n")) + if (!bootcpu_valid) { + pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); return; + } /* * Since the boot CPU node contains proper data, and all nodes have diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index bc5bc0a9713..85a72b0809c 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -350,6 +350,9 @@ ENDPROC(ftrace_stub) .align 5 ENTRY(vector_swi) +#ifdef CONFIG_CPU_V7M + v7m_exception_entry +#else sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0 - r12 ARM( add r8, sp, #S_PC ) @@ -360,6 +363,7 @@ ENTRY(vector_swi) str lr, [sp, #S_PC] @ Save calling PC str r8, [sp, #S_PSR] @ Save CPSR str r0, [sp, #S_OLD_R0] @ Save OLD_R0 +#endif zero_fp /* diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 160f3376ba6..de23a9beed1 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -5,6 +5,7 @@ #include <asm/asm-offsets.h> #include <asm/errno.h> #include <asm/thread_info.h> +#include <asm/v7m.h> @ Bad Abort numbers @ ----------------- @@ -44,6 +45,116 @@ #endif .endm +#ifdef CONFIG_CPU_V7M +/* + * ARMv7-M exception entry/exit macros. + * + * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are + * automatically saved on the current stack (32 words) before + * switching to the exception stack (SP_main). + * + * If exception is taken while in user mode, SP_main is + * empty. Otherwise, SP_main is aligned to 64 bit automatically + * (CCR.STKALIGN set). + * + * Linux assumes that the interrupts are disabled when entering an + * exception handler and it may BUG if this is not the case. Interrupts + * are disabled during entry and reenabled in the exit macro. + * + * v7m_exception_slow_exit is used when returning from SVC or PendSV. + * When returning to kernel mode, we don't return from exception. + */ + .macro v7m_exception_entry + @ determine the location of the registers saved by the core during + @ exception entry. Depending on the mode the cpu was in when the + @ exception happend that is either on the main or the process stack. + @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack + @ was used. + tst lr, #EXC_RET_STACK_MASK + mrsne r12, psp + moveq r12, sp + + @ we cannot rely on r0-r3 and r12 matching the value saved in the + @ exception frame because of tail-chaining. So these have to be + @ reloaded. + ldmia r12!, {r0-r3} + + @ Linux expects to have irqs off. Do it here before taking stack space + cpsid i + + sub sp, #S_FRAME_SIZE-S_IP + stmdb sp!, {r0-r11} + + @ load saved r12, lr, return address and xPSR. + @ r0-r7 are used for signals and never touched from now on. Clobbering + @ r8-r12 is OK. + mov r9, r12 + ldmia r9!, {r8, r10-r12} + + @ calculate the original stack pointer value. + @ r9 currently points to the memory location just above the auto saved + @ xPSR. + @ The cpu might automatically 8-byte align the stack. Bit 9 + @ of the saved xPSR specifies if stack aligning took place. In this case + @ another 32-bit value is included in the stack. + + tst r12, V7M_xPSR_FRAMEPTRALIGN + addne r9, r9, #4 + + @ store saved r12 using str to have a register to hold the base for stm + str r8, [sp, #S_IP] + add r8, sp, #S_SP + @ store r13-r15, xPSR + stmia r8!, {r9-r12} + @ store old_r0 + str r0, [r8] + .endm + + /* + * PENDSV and SVCALL are configured to have the same exception + * priorities. As a kernel thread runs at SVCALL execution priority it + * can never be preempted and so we will never have to return to a + * kernel thread here. + */ + .macro v7m_exception_slow_exit ret_r0 + cpsid i + ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK + + @ read original r12, sp, lr, pc and xPSR + add r12, sp, #S_IP + ldmia r12, {r1-r5} + + @ an exception frame is always 8-byte aligned. To tell the hardware if + @ the sp to be restored is aligned or not set bit 9 of the saved xPSR + @ accordingly. + tst r2, #4 + subne r2, r2, #4 + orrne r5, V7M_xPSR_FRAMEPTRALIGN + biceq r5, V7M_xPSR_FRAMEPTRALIGN + + @ write basic exception frame + stmdb r2!, {r1, r3-r5} + ldmia sp, {r1, r3-r5} + .if \ret_r0 + stmdb r2!, {r0, r3-r5} + .else + stmdb r2!, {r1, r3-r5} + .endif + + @ restore process sp + msr psp, r2 + + @ restore original r4-r11 + ldmia sp!, {r0-r11} + + @ restore main sp + add sp, sp, #S_FRAME_SIZE-S_IP + + cpsie i + bx lr + .endm +#endif /* CONFIG_CPU_V7M */ + @ @ Store/load the USER SP and LR registers by switching to the SYS @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not @@ -165,6 +276,18 @@ rfeia sp! .endm +#ifdef CONFIG_CPU_V7M + /* + * Note we don't need to do clrex here as clearing the local monitor is + * part of each exception entry and exit sequence. + */ + .macro restore_user_regs, fast = 0, offset = 0 + .if \offset + add sp, #\offset + .endif + v7m_exception_slow_exit ret_r0 = \fast + .endm +#else /* ifdef CONFIG_CPU_V7M */ .macro restore_user_regs, fast = 0, offset = 0 clrex @ clear the exclusive monitor mov r2, sp @@ -181,6 +304,7 @@ add sp, sp, #S_FRAME_SIZE - S_SP movs pc, lr @ return & move spsr_svc into cpsr .endm +#endif /* ifdef CONFIG_CPU_V7M / else */ .macro get_thread_info, rd mov \rd, sp diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S new file mode 100644 index 00000000000..e00621f1403 --- /dev/null +++ b/arch/arm/kernel/entry-v7m.S @@ -0,0 +1,143 @@ +/* + * linux/arch/arm/kernel/entry-v7m.S + * + * Copyright (C) 2008 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Low-level vector interface routines for the ARMv7-M architecture + */ +#include <asm/memory.h> +#include <asm/glue.h> +#include <asm/thread_notify.h> +#include <asm/v7m.h> + +#include <mach/entry-macro.S> + +#include "entry-header.S" + +#ifdef CONFIG_TRACE_IRQFLAGS +#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation" +#endif + +__invalid_entry: + v7m_exception_entry + adr r0, strerr + mrs r1, ipsr + mov r2, lr + bl printk + mov r0, sp + bl show_regs +1: b 1b +ENDPROC(__invalid_entry) + +strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n" + + .align 2 +__irq_entry: + v7m_exception_entry + + @ + @ Invoke the IRQ handler + @ + mrs r0, ipsr + ldr r1, =V7M_xPSR_EXCEPTIONNO + and r0, r1 + sub r0, #16 + mov r1, sp + stmdb sp!, {lr} + @ routine called with r0 = irq number, r1 = struct pt_regs * + bl nvic_do_IRQ + + pop {lr} + @ + @ Check for any pending work if returning to user + @ + ldr r1, =BASEADDR_V7M_SCB + ldr r0, [r1, V7M_SCB_ICSR] + tst r0, V7M_SCB_ICSR_RETTOBASE + beq 2f + + get_thread_info tsk + ldr r2, [tsk, #TI_FLAGS] + tst r2, #_TIF_WORK_MASK + beq 2f @ no work pending + mov r0, #V7M_SCB_ICSR_PENDSVSET + str r0, [r1, V7M_SCB_ICSR] @ raise PendSV + +2: + @ registers r0-r3 and r12 are automatically restored on exception + @ return. r4-r7 were not clobbered in v7m_exception_entry so for + @ correctness they don't need to be restored. So only r8-r11 must be + @ restored here. The easiest way to do so is to restore r0-r7, too. + ldmia sp!, {r0-r11} + add sp, #S_FRAME_SIZE-S_IP + cpsie i + bx lr +ENDPROC(__irq_entry) + +__pendsv_entry: + v7m_exception_entry + + ldr r1, =BASEADDR_V7M_SCB + mov r0, #V7M_SCB_ICSR_PENDSVCLR + str r0, [r1, V7M_SCB_ICSR] @ clear PendSV + + @ execute the pending work, including reschedule + get_thread_info tsk + mov why, #0 + b ret_to_user +ENDPROC(__pendsv_entry) + +/* + * Register switch for ARMv7-M processors. + * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info + * previous and next are guaranteed not to be the same. + */ +ENTRY(__switch_to) + .fnstart + .cantunwind + add ip, r1, #TI_CPU_SAVE + stmia ip!, {r4 - r11} @ Store most regs on stack + str sp, [ip], #4 + str lr, [ip], #4 + mov r5, r0 + add r4, r2, #TI_CPU_SAVE + ldr r0, =thread_notify_head + mov r1, #THREAD_NOTIFY_SWITCH + bl atomic_notifier_call_chain + mov ip, r4 + mov r0, r5 + ldmia ip!, {r4 - r11} @ Load all regs saved previously + ldr sp, [ip] + ldr pc, [ip, #4]! + .fnend +ENDPROC(__switch_to) + + .data + .align 8 +/* + * Vector table (64 words => 256 bytes natural alignment) + */ +ENTRY(vector_table) + .long 0 @ 0 - Reset stack pointer + .long __invalid_entry @ 1 - Reset + .long __invalid_entry @ 2 - NMI + .long __invalid_entry @ 3 - HardFault + .long __invalid_entry @ 4 - MemManage + .long __invalid_entry @ 5 - BusFault + .long __invalid_entry @ 6 - UsageFault + .long __invalid_entry @ 7 - Reserved + .long __invalid_entry @ 8 - Reserved + .long __invalid_entry @ 9 - Reserved + .long __invalid_entry @ 10 - Reserved + .long vector_swi @ 11 - SVCall + .long __invalid_entry @ 12 - Debug Monitor + .long __invalid_entry @ 13 - Reserved + .long __pendsv_entry @ 14 - PendSV + .long __invalid_entry @ 15 - SysTick + .rept 64 - 16 + .long __irq_entry @ 16..64 - External Interrupts + .endr diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 6a2e09c952c..8812ce88f7a 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -19,6 +19,7 @@ #include <asm/asm-offsets.h> #include <asm/cp15.h> #include <asm/thread_info.h> +#include <asm/v7m.h> /* * Kernel startup entry point. @@ -50,10 +51,13 @@ ENTRY(stext) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled -#ifndef CONFIG_CPU_CP15 - ldr r9, =CONFIG_PROCESSOR_ID -#else +#if defined(CONFIG_CPU_CP15) mrc p15, 0, r9, c0, c0 @ get processor id +#elif defined(CONFIG_CPU_V7M) + ldr r9, =BASEADDR_V7M_SCB + ldr r9, [r9, V7M_SCB_CPUID] +#else + ldr r9, =CONFIG_PROCESSOR_ID #endif bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 8ef8c933780..4fb074c446b 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -134,6 +134,10 @@ void machine_kexec(struct kimage *image) unsigned long reboot_code_buffer_phys; void *reboot_code_buffer; + if (num_online_cpus() > 1) { + pr_err("kexec: error: multiple CPUs still online\n"); + return; + } page_list = image->head & PAGE_MASK; diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 1e9be5d25e5..85c3fb6c93c 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -288,24 +288,16 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, if (strcmp(".ARM.exidx.init.text", secname) == 0) maps[ARM_SEC_INIT].unw_sec = s; - else if (strcmp(".ARM.exidx.devinit.text", secname) == 0) - maps[ARM_SEC_DEVINIT].unw_sec = s; else if (strcmp(".ARM.exidx", secname) == 0) maps[ARM_SEC_CORE].unw_sec = s; else if (strcmp(".ARM.exidx.exit.text", secname) == 0) maps[ARM_SEC_EXIT].unw_sec = s; - else if (strcmp(".ARM.exidx.devexit.text", secname) == 0) - maps[ARM_SEC_DEVEXIT].unw_sec = s; else if (strcmp(".init.text", secname) == 0) maps[ARM_SEC_INIT].txt_sec = s; - else if (strcmp(".devinit.text", secname) == 0) - maps[ARM_SEC_DEVINIT].txt_sec = s; else if (strcmp(".text", secname) == 0) maps[ARM_SEC_CORE].txt_sec = s; else if (strcmp(".exit.text", secname) == 0) maps[ARM_SEC_EXIT].txt_sec = s; - else if (strcmp(".devexit.text", secname) == 0) - maps[ARM_SEC_DEVEXIT].txt_sec = s; } for (i = 0; i < ARM_SEC_MAX; i++) diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 282de4826ab..6e8931ccf13 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -184,30 +184,61 @@ int __init reboot_setup(char *str) __setup("reboot=", reboot_setup); +/* + * Called by kexec, immediately prior to machine_kexec(). + * + * This must completely disable all secondary CPUs; simply causing those CPUs + * to execute e.g. a RAM-based pin loop is not sufficient. This allows the + * kexec'd kernel to use any and all RAM as it sees fit, without having to + * avoid any code or data used by any SW CPU pin loop. The CPU hotplug + * functionality embodied in disable_nonboot_cpus() to achieve this. + */ void machine_shutdown(void) { -#ifdef CONFIG_SMP - smp_send_stop(); -#endif + disable_nonboot_cpus(); } +/* + * Halting simply requires that the secondary CPUs stop performing any + * activity (executing tasks, handling interrupts). smp_send_stop() + * achieves this. + */ void machine_halt(void) { - machine_shutdown(); + smp_send_stop(); + local_irq_disable(); while (1); } +/* + * Power-off simply requires that the secondary CPUs stop performing any + * activity (executing tasks, handling interrupts). smp_send_stop() + * achieves this. When the system power is turned off, it will take all CPUs + * with it. + */ void machine_power_off(void) { - machine_shutdown(); + smp_send_stop(); + if (pm_power_off) pm_power_off(); } +/* + * Restart requires that the secondary CPUs stop performing any activity + * while the primary CPU resets the system. Systems with a single CPU can + * use soft_restart() as their machine descriptor's .restart hook, since that + * will cause the only available CPU to reset. Systems with multiple CPUs must + * provide a HW restart implementation, to ensure that all CPUs reset at once. + * This is required so that any code running after reset on the primary CPU + * doesn't have to co-ordinate with other CPUs to ensure they aren't still + * executing pre-reset code, and using RAM that the primary CPU's code wishes + * to use. Implementing such co-ordination would be essentially impossible. + */ void machine_restart(char *cmd) { - machine_shutdown(); + smp_send_stop(); arm_pm_restart(reboot_mode, cmd); diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c index 36531643cc2..46931880093 100644 --- a/arch/arm/kernel/psci.c +++ b/arch/arm/kernel/psci.c @@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = { {}, }; -static int __init psci_init(void) +void __init psci_init(void) { struct device_node *np; const char *method; @@ -166,7 +166,7 @@ static int __init psci_init(void) np = of_find_matching_node(NULL, psci_of_match); if (!np) - return 0; + return; pr_info("probing function IDs from device-tree\n"); @@ -206,6 +206,5 @@ static int __init psci_init(void) out_put_node: of_node_put(np); - return 0; + return; } -early_initcall(psci_init); diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c new file mode 100644 index 00000000000..23a11424c56 --- /dev/null +++ b/arch/arm/kernel/psci_smp.c @@ -0,0 +1,84 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2012 ARM Limited + * + * Author: Will Deacon <will.deacon@arm.com> + */ + +#include <linux/init.h> +#include <linux/irqchip/arm-gic.h> +#include <linux/smp.h> +#include <linux/of.h> + +#include <asm/psci.h> +#include <asm/smp_plat.h> + +/* + * psci_smp assumes that the following is true about PSCI: + * + * cpu_suspend Suspend the execution on a CPU + * @state we don't currently describe affinity levels, so just pass 0. + * @entry_point the first instruction to be executed on return + * returns 0 success, < 0 on failure + * + * cpu_off Power down a CPU + * @state we don't currently describe affinity levels, so just pass 0. + * no return on successful call + * + * cpu_on Power up a CPU + * @cpuid cpuid of target CPU, as from MPIDR + * @entry_point the first instruction to be executed on return + * returns 0 success, < 0 on failure + * + * migrate Migrate the context to a different CPU + * @cpuid cpuid of target CPU, as from MPIDR + * returns 0 success, < 0 on failure + * + */ + +extern void secondary_startup(void); + +static int __cpuinit psci_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + if (psci_ops.cpu_on) + return psci_ops.cpu_on(cpu_logical_map(cpu), + __pa(secondary_startup)); + return -ENODEV; +} + +#ifdef CONFIG_HOTPLUG_CPU +void __ref psci_cpu_die(unsigned int cpu) +{ + const struct psci_power_state ps = { + .type = PSCI_POWER_STATE_TYPE_POWER_DOWN, + }; + + if (psci_ops.cpu_off) + psci_ops.cpu_off(ps); + + /* We should never return */ + panic("psci: cpu %d failed to shutdown\n", cpu); +} +#else +#define psci_cpu_die NULL +#endif + +bool __init psci_smp_available(void) +{ + /* is cpu_on available at least? */ + return (psci_ops.cpu_on != NULL); +} + +struct smp_operations __initdata psci_smp_ops = { + .smp_boot_secondary = psci_boot_secondary, + .cpu_die = psci_cpu_die, +}; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1522c7ae31b..1c8278de6c4 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -37,6 +37,7 @@ #include <asm/cputype.h> #include <asm/elf.h> #include <asm/procinfo.h> +#include <asm/psci.h> #include <asm/sections.h> #include <asm/setup.h> #include <asm/smp_plat.h> @@ -128,7 +129,9 @@ struct stack { u32 und[3]; } ____cacheline_aligned; +#ifndef CONFIG_CPU_V7M static struct stack stacks[NR_CPUS]; +#endif char elf_platform[ELF_PLATFORM_SIZE]; EXPORT_SYMBOL(elf_platform); @@ -207,7 +210,7 @@ static const char *proc_arch[] = { "5TEJ", "6TEJ", "7", - "?(11)", + "7M", "?(12)", "?(13)", "?(14)", @@ -216,6 +219,12 @@ static const char *proc_arch[] = { "?(17)", }; +#ifdef CONFIG_CPU_V7M +static int __get_cpu_architecture(void) +{ + return CPU_ARCH_ARMv7M; +} +#else static int __get_cpu_architecture(void) { int cpu_arch; @@ -248,6 +257,7 @@ static int __get_cpu_architecture(void) return cpu_arch; } +#endif int __pure cpu_architecture(void) { @@ -293,7 +303,9 @@ static void __init cacheid_init(void) { unsigned int arch = cpu_architecture(); - if (arch >= CPU_ARCH_ARMv6) { + if (arch == CPU_ARCH_ARMv7M) { + cacheid = 0; + } else if (arch >= CPU_ARCH_ARMv6) { unsigned int cachetype = read_cpuid_cachetype(); if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ @@ -392,6 +404,7 @@ static void __init feat_v6_fixup(void) */ void notrace cpu_init(void) { +#ifndef CONFIG_CPU_V7M unsigned int cpu = smp_processor_id(); struct stack *stk = &stacks[cpu]; @@ -442,9 +455,10 @@ void notrace cpu_init(void) "I" (offsetof(struct stack, und[0])), PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) : "r14"); +#endif } -int __cpu_logical_map[NR_CPUS]; +u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; void __init smp_setup_processor_id(void) { @@ -796,9 +810,15 @@ void __init setup_arch(char **cmdline_p) unflatten_device_tree(); arm_dt_init_cpu_maps(); + psci_init(); #ifdef CONFIG_SMP if (is_smp()) { - smp_set_ops(mdesc->smp); + if (!mdesc->smp_init || !mdesc->smp_init()) { + if (psci_smp_available()) + smp_set_ops(&psci_smp_ops); + else if (mdesc->smp) + smp_set_ops(mdesc->smp); + } smp_init_cpus(); } #endif diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 550d63cef68..5919eb451bb 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -651,17 +651,6 @@ void smp_send_reschedule(int cpu) smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } -#ifdef CONFIG_HOTPLUG_CPU -static void smp_kill_cpus(cpumask_t *mask) -{ - unsigned int cpu; - for_each_cpu(cpu, mask) - platform_cpu_kill(cpu); -} -#else -static void smp_kill_cpus(cpumask_t *mask) { } -#endif - void smp_send_stop(void) { unsigned long timeout; @@ -679,8 +668,6 @@ void smp_send_stop(void) if (num_online_cpus() > 1) pr_warning("SMP: failed to stop secondary CPUs\n"); - - smp_kill_cpus(&mask); } /* diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 18b32e8e449..486e12a0f26 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -812,6 +812,7 @@ static void __init kuser_get_tls_init(unsigned long vectors) void __init early_trap_init(void *vectors_base) { +#ifndef CONFIG_CPU_V7M unsigned long vectors = (unsigned long)vectors_base; extern char __stubs_start[], __stubs_end[]; extern char __vectors_start[], __vectors_end[]; @@ -843,4 +844,11 @@ void __init early_trap_init(void *vectors_base) flush_icache_range(vectors, vectors + PAGE_SIZE); modify_domain(DOMAIN_USER, DOMAIN_CLIENT); +#else /* ifndef CONFIG_CPU_V7M */ + /* + * on V7-M there is no need to copy the vector table to a dedicated + * memory area. The address is configurable and so a table in the kernel + * image can be used. + */ +#endif } diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index a871b8e00fc..fa25e4e425f 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -70,10 +70,6 @@ SECTIONS ARM_EXIT_DISCARD(EXIT_TEXT) ARM_EXIT_DISCARD(EXIT_DATA) EXIT_CALL -#ifndef CONFIG_HOTPLUG - *(.ARM.exidx.devexit.text) - *(.ARM.extab.devexit.text) -#endif #ifndef CONFIG_MMU *(.fixup) *(__ex_table) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 02802386b89..699b71e7f7e 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -163,6 +163,7 @@ config MACH_SAMA5_DT bool "Atmel SAMA5 Evaluation Kits with device-tree support" depends on SOC_SAMA5 select USE_OF + select PHYLIB if NETDEVICES help Select this if you want to experiment device-tree with an Atmel Evaluation Kit. diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 6cd554a4e73..ca900be144c 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt @@ -62,13 +62,6 @@ config MACH_ONEARM Select this if you are using Ajeco's 1ARM Single Board Computer. <http://www.ajeco.fi/> -config ARCH_AT91RM9200DK - bool "Atmel AT91RM9200-DK Development board" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91RM9200-DK Development board. - (Discontinued) - config MACH_AT91RM9200EK bool "Atmel AT91RM9200-EK Evaluation Kit" select HAVE_AT91_DATAFLASH_CARD diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index d07bcfad444..3b0a9538093 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -34,7 +34,6 @@ obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support obj-$(CONFIG_MACH_ONEARM) += board-1arm.o -obj-$(CONFIG_ARCH_AT91RM9200DK) += board-rm9200dk.o obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o obj-$(CONFIG_MACH_CSB337) += board-csb337.o obj-$(CONFIG_MACH_CSB637) += board-csb637.o diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index d193a409bc4..9eb574397ee 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -332,10 +332,6 @@ static void __init at91rm9200_initialize(void) { arm_pm_idle = at91rm9200_idle; arm_pm_restart = at91rm9200_restart; - at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) - | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) - | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) - | (1 << AT91RM9200_ID_IRQ6); /* Initialize GPIO subsystem */ at91_gpio_init(at91rm9200_gpio, @@ -388,6 +384,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { AT91_SOC_START(at91rm9200) .map_io = at91rm9200_map_io, .default_irq_priority = at91rm9200_default_irq_priority, + .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) + | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) + | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) + | (1 << AT91RM9200_ID_IRQ6), .ioremap_registers = at91rm9200_ioremap_registers, .register_clocks = at91rm9200_register_clocks, .init = at91rm9200_initialize, diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index a8ce24538da..5de6074b4f4 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -348,8 +348,6 @@ static void __init at91sam9260_initialize(void) { arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) - | (1 << AT91SAM9260_ID_IRQ2); /* Register GPIO subsystem */ at91_gpio_init(at91sam9260_gpio, 3); @@ -400,6 +398,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { AT91_SOC_START(at91sam9260) .map_io = at91sam9260_map_io, .default_irq_priority = at91sam9260_default_irq_priority, + .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) + | (1 << AT91SAM9260_ID_IRQ2), .ioremap_registers = at91sam9260_ioremap_registers, .register_clocks = at91sam9260_register_clocks, .init = at91sam9260_initialize, diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 25efb5ac30f..0e0793241ab 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -290,8 +290,6 @@ static void __init at91sam9261_initialize(void) { arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) - | (1 << AT91SAM9261_ID_IRQ2); /* Register GPIO subsystem */ at91_gpio_init(at91sam9261_gpio, 3); @@ -342,6 +340,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { AT91_SOC_START(at91sam9261) .map_io = at91sam9261_map_io, .default_irq_priority = at91sam9261_default_irq_priority, + .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) + | (1 << AT91SAM9261_ID_IRQ2), .ioremap_registers = at91sam9261_ioremap_registers, .register_clocks = at91sam9261_register_clocks, .init = at91sam9261_initialize, diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index f44ffd2105a..6ce7d185089 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -327,7 +327,6 @@ static void __init at91sam9263_initialize(void) { arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); /* Register GPIO subsystem */ at91_gpio_init(at91sam9263_gpio, 5); @@ -378,6 +377,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { AT91_SOC_START(at91sam9263) .map_io = at91sam9263_map_io, .default_irq_priority = at91sam9263_default_irq_priority, + .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1), .ioremap_registers = at91sam9263_ioremap_registers, .register_clocks = at91sam9263_register_clocks, .init = at91sam9263_initialize, diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 95a418a7aab..474ee04d24b 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -376,7 +376,6 @@ static void __init at91sam9g45_initialize(void) { arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9g45_restart; - at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); /* Register GPIO subsystem */ at91_gpio_init(at91sam9g45_gpio, 5); @@ -427,6 +426,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { AT91_SOC_START(at91sam9g45) .map_io = at91sam9g45_map_io, .default_irq_priority = at91sam9g45_default_irq_priority, + .extern_irq = (1 << AT91SAM9G45_ID_IRQ0), .ioremap_registers = at91sam9g45_ioremap_registers, .register_clocks = at91sam9g45_register_clocks, .init = at91sam9g45_initialize, diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index f77fae5591b..d4ec0d9a987 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -293,7 +293,6 @@ static void __init at91sam9rl_initialize(void) { arm_pm_idle = at91sam9_idle; arm_pm_restart = at91sam9_alt_restart; - at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); /* Register GPIO subsystem */ at91_gpio_init(at91sam9rl_gpio, 4); @@ -344,6 +343,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { AT91_SOC_START(at91sam9rl) .map_io = at91sam9rl_map_io, .default_irq_priority = at91sam9rl_default_irq_priority, + .extern_irq = (1 << AT91SAM9RL_ID_IRQ0), .ioremap_registers = at91sam9rl_ioremap_registers, .register_clocks = at91sam9rl_register_clocks, .init = at91sam9rl_initialize, diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c index 19ca7939690..bad94b84a46 100644 --- a/arch/arm/mach-at91/at91x40.c +++ b/arch/arm/mach-at91/at91x40.c @@ -55,8 +55,6 @@ static void at91x40_idle(void) void __init at91x40_initialize(unsigned long main_clock) { arm_pm_idle = at91x40_idle; - at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) - | (1 << AT91X40_ID_IRQ2); } /* @@ -86,9 +84,10 @@ static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = { void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) { + u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) + | (1 << AT91X40_ID_IRQ2); if (!priority) priority = at91x40_default_irq_priority; - at91_aic_init(priority, at91_extern_irq); + at91_aic_init(priority, extern_irq); } - diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index 705305e62bb..ad95f6a23a2 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c @@ -62,7 +62,8 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy) static void __init sama5_dt_device_init(void) { - if (of_machine_is_compatible("atmel,sama5d3xcm")) + if (of_machine_is_compatible("atmel,sama5d3xcm") && + IS_ENABLED(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, ksz9021rn_phy_fixup); diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c deleted file mode 100644 index 690541b18cb..00000000000 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-rm9200dk.c - * - * Copyright (C) 2005 SAN People - * - * Epson S1D framebuffer glue code is: - * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/types.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/mtd/physmap.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/irq.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/at91rm9200_mc.h> -#include <mach/at91_ramc.h> - -#include "at91_aic.h" -#include "board.h" -#include "generic.h" - - -static void __init dk_init_early(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91_initialize(18432000); -} - -static struct macb_platform_data __initdata dk_eth_data = { - .phy_irq_pin = AT91_PIN_PC4, - .is_rmii = 1, -}; - -static struct at91_usbh_data __initdata dk_usbh_data = { - .ports = 2, - .vbus_pin = {-EINVAL, -EINVAL}, - .overcurrent_pin= {-EINVAL, -EINVAL}, -}; - -static struct at91_udc_data __initdata dk_udc_data = { - .vbus_pin = AT91_PIN_PD4, - .pullup_pin = AT91_PIN_PD5, -}; - -static struct at91_cf_data __initdata dk_cf_data = { - .irq_pin = -EINVAL, - .det_pin = AT91_PIN_PB0, - .vcc_pin = -EINVAL, - .rst_pin = AT91_PIN_PC5, -}; - -#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD -static struct mci_platform_data __initdata dk_mci0_data = { - .slot[0] = { - .bus_width = 4, - .detect_pin = -EINVAL, - .wp_pin = -EINVAL, - }, -}; -#endif - -static struct spi_board_info dk_spi_devices[] = { - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - }, - { /* UR6HCPS2-SP40 PS2-to-SPI adapter */ - .modalias = "ur6hcps2", - .chip_select = 1, - .max_speed_hz = 250 * 1000, - }, - { /* TLV1504 ADC, 4 channels, 10 bits; one is a temp sensor */ - .modalias = "tlv1504", - .chip_select = 2, - .max_speed_hz = 20 * 1000 * 1000, - }, -#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD - { /* DataFlash card */ - .modalias = "mtd_dataflash", - .chip_select = 3, - .max_speed_hz = 15 * 1000 * 1000, - } -#endif -}; - -static struct i2c_board_info __initdata dk_i2c_devices[] = { - { - I2C_BOARD_INFO("ics1523", 0x26), - }, - { - I2C_BOARD_INFO("x9429", 0x28), - }, - { - I2C_BOARD_INFO("24c1024", 0x50), - } -}; - -static struct mtd_partition __initdata dk_nand_partition[] = { - { - .name = "NAND Partition 1", - .offset = 0, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct atmel_nand_data __initdata dk_nand_data = { - .ale = 22, - .cle = 21, - .det_pin = AT91_PIN_PB1, - .rdy_pin = AT91_PIN_PC2, - .enable_pin = -EINVAL, - .ecc_mode = NAND_ECC_SOFT, - .on_flash_bbt = 1, - .parts = dk_nand_partition, - .num_parts = ARRAY_SIZE(dk_nand_partition), -}; - -#define DK_FLASH_BASE AT91_CHIPSELECT_0 -#define DK_FLASH_SIZE SZ_2M - -static struct physmap_flash_data dk_flash_data = { - .width = 2, -}; - -static struct resource dk_flash_resource = { - .start = DK_FLASH_BASE, - .end = DK_FLASH_BASE + DK_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device dk_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &dk_flash_data, - }, - .resource = &dk_flash_resource, - .num_resources = 1, -}; - -static struct gpio_led dk_leds[] = { - { - .name = "led0", - .gpio = AT91_PIN_PB2, - .active_low = 1, - .default_trigger = "heartbeat", - } -}; - -static void __init dk_board_init(void) -{ - /* Serial */ - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - at91_add_device_serial(); - /* Ethernet */ - at91_add_device_eth(&dk_eth_data); - /* USB Host */ - at91_add_device_usbh(&dk_usbh_data); - /* USB Device */ - at91_add_device_udc(&dk_udc_data); - at91_set_multi_drive(dk_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */ - /* Compact Flash */ - at91_add_device_cf(&dk_cf_data); - /* I2C */ - at91_add_device_i2c(dk_i2c_devices, ARRAY_SIZE(dk_i2c_devices)); - /* SPI */ - at91_add_device_spi(dk_spi_devices, ARRAY_SIZE(dk_spi_devices)); -#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD - /* DataFlash card */ - at91_set_gpio_output(AT91_PIN_PB7, 0); -#else - /* MMC */ - at91_set_gpio_output(AT91_PIN_PB7, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */ - at91_add_device_mci(0, &dk_mci0_data); -#endif - /* NAND */ - at91_add_device_nand(&dk_nand_data); - /* NOR Flash */ - platform_device_register(&dk_flash); - /* LEDs */ - at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds)); - /* VGA */ -// dk_add_device_video(); -} - -MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") - /* Maintainer: SAN People/Atmel */ - .init_time = at91rm9200_timer_init, - .map_io = at91_map_io, - .handle_irq = at91_aic_handle_irq, - .init_early = dk_init_early, - .init_irq = at91_init_irq_default, - .init_machine = dk_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index da841885d01..6b2630a92f7 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12())) + || cpu_is_sama5d3())) #define cpu_has_upll() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ @@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused) seq_printf(s, "UCKR = %8x\n", uckr); } seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); - if (cpu_has_upll()) + if (cpu_has_upll() || cpu_is_at91sam9n12()) seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); seq_printf(s, "SR = %8x\n", sr); @@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) { if (pll == &pllb && (reg & AT91_PMC_USB96M)) return freq / 2; + else if (pll == &utmi_clk || cpu_is_at91sam9n12()) + return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8)); else return freq; } @@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = { /* PLLB generated USB full speed clock init */ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) { + unsigned int reg; + /* * USB clock init: choose 48 MHz PLLB value, * disable 48MHz clock during usb peripheral suspend. @@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) */ uhpck.parent = &pllb; - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2); pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); if (cpu_is_at91rm9200()) { + reg = at91_pllb_usb_init |= AT91_PMC_USB96M; uhpck.pmc_mask = AT91RM9200_PMC_UHP; udpck.pmc_mask = AT91RM9200_PMC_UDP; at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) { + reg = at91_pllb_usb_init |= AT91_PMC_USB96M; + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + udpck.pmc_mask = AT91SAM926x_PMC_UDP; + } else if (cpu_is_at91sam9n12()) { + /* Divider for USB clock is in USB clock register for 9n12 */ + reg = AT91_PMC_USBS_PLLB; + + /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */ + reg |= AT91_PMC_OHCIUSBDIV_2; + at91_pmc_write(AT91_PMC_USB, reg); + + /* Still setup masks */ uhpck.pmc_mask = AT91SAM926x_PMC_UHP; udpck.pmc_mask = AT91SAM926x_PMC_UDP; } at91_pmc_write(AT91_CKGR_PLLBR, 0); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg); } /* UPLL generated USB full speed clock init */ @@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) /* Now set uhpck values */ uhpck.parent = &utmi_clk; uhpck.pmc_mask = AT91SAM926x_PMC_UHP; - uhpck.rate_hz = utmi_clk.rate_hz; - uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); + uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr); } static int __init at91_pmc_init(unsigned long main_clock) diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c index 69f9e3bbf4e..4ec6a6d9b9b 100644 --- a/arch/arm/mach-at91/cpuidle.c +++ b/arch/arm/mach-at91/cpuidle.c @@ -51,7 +51,7 @@ static struct cpuidle_driver at91_idle_driver = { .states[1] = { .enter = at91_enter_idle, .exit_latency = 10, - .target_residency = 100000, + .target_residency = 10000, .flags = CPUIDLE_FLAG_TIME_VALID, .name = "RAM_SR", .desc = "WFI and DDR Self Refresh", diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 78ab0654865..f6de36aefe8 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -85,4 +85,4 @@ extern void __init at91_gpio_irq_setup(void); extern int __init at91_gpio_of_irq_setup(struct device_node *node, struct device_node *parent); -extern int at91_extern_irq; +extern u32 at91_get_extern_irq(void); diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 2bd7f51b0b8..c604cc69acb 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -130,7 +130,10 @@ extern void __iomem *at91_pmc_base; #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ #define AT91_PMC_USBS_PLLA (0 << 0) #define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ +#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) +#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index e0ca5917102..3d192c5aee6 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c @@ -232,7 +232,14 @@ static void __maybe_unused at91_aic5_eoi(struct irq_data *d) at91_aic_write(AT91_AIC5_EOICR, 0); } -unsigned long *at91_extern_irq; +static unsigned long *at91_extern_irq; + +u32 at91_get_extern_irq(void) +{ + if (!at91_extern_irq) + return 0; + return *at91_extern_irq; +} #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 530db304ec5..15afb5d9271 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -212,7 +212,7 @@ static int at91_pm_enter(suspend_state_t state) (at91_pmc_read(AT91_PMC_PCSR) | (1 << AT91_ID_FIQ) | (1 << AT91_ID_SYS) - | (at91_extern_irq)) + | (at91_get_extern_irq())) & at91_aic_read(AT91_AIC_IMR), state); diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index e2f4bdd146d..b17fbcf4d9e 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -48,7 +48,7 @@ void __init at91_init_irq_default(void) void __init at91_init_interrupts(unsigned int *priority) { /* Initialize the AIC interrupt controller */ - at91_aic_init(priority, at91_extern_irq); + at91_aic_init(priority, at91_boot_soc.extern_irq); /* Enable GPIO interrupts */ at91_gpio_irq_setup(); @@ -80,7 +80,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) desc->pfn = __phys_to_pfn(base); desc->length = length; - desc->type = MT_DEVICE; + desc->type = MT_MEMORY_NONCACHED; pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", base, length, desc->virtual); diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 43a225f9e71..a1e1482c6da 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -6,6 +6,7 @@ struct at91_init_soc { int builtin; + u32 extern_irq; unsigned int *default_irq_priority; void (*map_io)(void); void (*ioremap_registers)(void); diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c index 22e8421b1df..28599326d4a 100644 --- a/arch/arm/mach-bcm/board_bcm.c +++ b/arch/arm/mach-bcm/board_bcm.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/device.h> #include <linux/platform_device.h> -#include <linux/irqchip.h> #include <linux/clocksource.h> #include <asm/mach/arch.h> @@ -54,7 +53,6 @@ static void __init board_init(void) static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, }; DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") - .init_irq = irqchip_init, .init_time = clocksource_of_init, .init_machine = board_init, .dt_compat = bcm11351_dt_compat, diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index 2d00165e85e..01ad4d41e72 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -22,8 +22,7 @@ config ARCH_CLEP7312 config ARCH_EDB7211 bool "EDB7211" - select ARCH_SELECT_MEMORY_MODEL - select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_HOLES_MEMORYMODEL help Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211 evaluation board. diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile index 992995af666..f30ed2b496f 100644 --- a/arch/arm/mach-clps711x/Makefile +++ b/arch/arm/mach-clps711x/Makefile @@ -4,10 +4,7 @@ # Object file lists. -obj-y := common.o -obj-m := -obj-n := -obj- := +obj-y := common.o devices.o obj-$(CONFIG_ARCH_AUTCPU12) += board-autcpu12.o obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index f38584709df..5867aebd8d0 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -26,6 +26,8 @@ #include <linux/gpio.h> #include <linux/ioport.h> #include <linux/interrupt.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/plat-ram.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand-gpio.h> #include <linux/platform_device.h> @@ -40,38 +42,49 @@ #include <asm/page.h> #include <asm/mach/map.h> -#include <mach/autcpu12.h> #include "common.h" +#include "devices.h" -#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300) -#define AUTCPU12_CS8900_IRQ (IRQ_EINT3) +/* NOR flash */ +#define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE) + +/* Board specific hardware definitions */ +#define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000) +#define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000) +#define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000) +#define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000) +#define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000) +#define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000) + +/* NVRAM */ +#define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000) +/* SmartMedia flash */ #define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000) #define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10) +/* Ethernet */ +#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300) +#define AUTCPU12_CS8900_IRQ (IRQ_EINT3) + +/* NAND flash */ #define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO) #define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */ #define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2) #define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3) #define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3) +/* LCD contrast digital potentiometer */ +#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0) +#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1) +#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2) + static struct resource autcpu12_cs8900_resource[] __initdata = { DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ), }; -static struct resource autcpu12_nvram_resource[] __initdata = { - DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"), -}; - -static struct platform_device autcpu12_nvram_pdev __initdata = { - .name = "autcpu12_nvram", - .id = -1, - .resource = autcpu12_nvram_resource, - .num_resources = ARRAY_SIZE(autcpu12_nvram_resource), -}; - static struct resource autcpu12_nand_resource[] __initdata = { DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16), }; @@ -147,17 +160,106 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = { }, }; +static const struct gpio autcpu12_gpios[] __initconst = { + { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" }, + { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" }, + { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" }, +}; + +static struct mtd_partition autcpu12_flash_partitions[] = { + { + .name = "NOR.0", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data autcpu12_flash_pdata = { + .width = 4, + .parts = autcpu12_flash_partitions, + .nr_parts = ARRAY_SIZE(autcpu12_flash_partitions), +}; + +static struct resource autcpu12_flash_resources[] __initdata = { + DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M), +}; + +static struct platform_device autcpu12_flash_pdev __initdata = { + .name = "physmap-flash", + .id = 0, + .resource = autcpu12_flash_resources, + .num_resources = ARRAY_SIZE(autcpu12_flash_resources), + .dev = { + .platform_data = &autcpu12_flash_pdata, + }, +}; + +static struct resource autcpu12_nvram_resource[] __initdata = { + DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0), +}; + +static struct platdata_mtd_ram autcpu12_nvram_pdata = { + .bankwidth = 4, +}; + +static struct platform_device autcpu12_nvram_pdev __initdata = { + .name = "mtd-ram", + .id = 0, + .resource = autcpu12_nvram_resource, + .num_resources = ARRAY_SIZE(autcpu12_nvram_resource), + .dev = { + .platform_data = &autcpu12_nvram_pdata, + }, +}; + +static void __init autcpu12_nvram_init(void) +{ + void __iomem *nvram; + unsigned int save[2]; + resource_size_t nvram_size = SZ_128K; + + /* + * Check for 32K/128K + * Read ofs 0K + * Read ofs 64K + * Write complement to ofs 64K + * Read and check result on ofs 0K + * Restore contents + */ + nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K); + if (nvram) { + save[0] = readl(nvram + 0); + save[1] = readl(nvram + SZ_64K); + writel(~save[0], nvram + SZ_64K); + if (readl(nvram + 0) != save[0]) { + writel(save[0], nvram + 0); + nvram_size = SZ_32K; + } else + writel(save[1], nvram + SZ_64K); + iounmap(nvram); + + autcpu12_nvram_resource[0].end = + autcpu12_nvram_resource[0].start + nvram_size - 1; + platform_device_register(&autcpu12_nvram_pdev); + } else + pr_err("Failed to remap NVRAM resource\n"); +} + static void __init autcpu12_init(void) { + clps711x_devices_init(); + platform_device_register(&autcpu12_flash_pdev); platform_device_register_simple("video-clps711x", 0, NULL, 0); platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource, ARRAY_SIZE(autcpu12_cs8900_resource)); platform_device_register(&autcpu12_mmgpio_pdev); - platform_device_register(&autcpu12_nvram_pdev); + autcpu12_nvram_init(); } static void __init autcpu12_init_late(void) { + gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios)); + if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) { /* We are need both drivers to handle NAND */ platform_device_register(&autcpu12_nand_pdev); @@ -169,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12") .atag_offset = 0x20000, .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = autcpu12_init, diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c index baab7da33c9..a9e38c6bcfb 100644 --- a/arch/arm/mach-clps711x/board-cdb89712.c +++ b/arch/arm/mach-clps711x/board-cdb89712.c @@ -39,6 +39,7 @@ #include <asm/mach/map.h> #include "common.h" +#include "devices.h" #define CDB89712_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define CDB89712_CS8900_IRQ (IRQ_EINT3) @@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = { static void __init cdb89712_init(void) { + clps711x_devices_init(); platform_device_register(&cdb89712_flash_pdev); platform_device_register(&cdb89712_bootrom_pdev); platform_device_register(&cdb89712_sram_pdev); @@ -139,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712") .atag_offset = 0x100, .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = cdb89712_init, diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c index 014aa3c19a0..b4764246d0f 100644 --- a/arch/arm/mach-clps711x/board-clep7312.c +++ b/arch/arm/mach-clps711x/board-clep7312.c @@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_clep7312, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .handle_irq = clps711x_handle_irq, diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c index 5f928e9ed2e..9dfb990f080 100644 --- a/arch/arm/mach-clps711x/board-edb7211.c +++ b/arch/arm/mach-clps711x/board-edb7211.c @@ -12,6 +12,7 @@ #include <linux/delay.h> #include <linux/memblock.h> #include <linux/types.h> +#include <linux/i2c-gpio.h> #include <linux/interrupt.h> #include <linux/backlight.h> #include <linux/platform_device.h> @@ -29,6 +30,7 @@ #include <mach/hardware.h> #include "common.h" +#include "devices.h" #define VIDEORAM_SIZE SZ_128K @@ -36,11 +38,24 @@ #define EDB7211_LCDEN CLPS711X_GPIO(3, 2) #define EDB7211_LCDBL CLPS711X_GPIO(3, 3) +#define EDB7211_I2C_SDA CLPS711X_GPIO(3, 4) +#define EDB7211_I2C_SCL CLPS711X_GPIO(3, 5) + #define EDB7211_FLASH0_BASE (CS0_PHYS_BASE) #define EDB7211_FLASH1_BASE (CS1_PHYS_BASE) + #define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define EDB7211_CS8900_IRQ (IRQ_EINT3) +/* The extra 8 lines of the keyboard matrix */ +#define EDB7211_EXTKBD_BASE (CS3_PHYS_BASE) + +static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = { + .sda_pin = EDB7211_I2C_SDA, + .scl_pin = EDB7211_I2C_SCL, + .scl_is_output_only = 1, +}; + static struct resource edb7211_cs8900_resource[] __initdata = { DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(EDB7211_CS8900_IRQ), @@ -94,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = { static void edb7211_lcd_backlight_set_intensity(int intensity) { - gpio_set_value(EDB7211_LCDBL, intensity); + gpio_set_value(EDB7211_LCDBL, !!intensity); + clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON); } static struct generic_bl_info edb7211_lcd_backlight_pdata = { .name = "lcd-backlight.0", .default_intensity = 0x01, - .max_intensity = 0x01, + .max_intensity = 0x0f, .set_bl_intensity = edb7211_lcd_backlight_set_intensity, }; @@ -112,8 +128,8 @@ static struct gpio edb7211_gpios[] __initconst = { static struct map_desc edb7211_io_desc[] __initdata = { { /* Memory-mapped extra keyboard row */ - .virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD), - .pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD), + .virtual = IO_ADDRESS(EDB7211_EXTKBD_BASE), + .pfn = __phys_to_pfn(EDB7211_EXTKBD_BASE), .length = SZ_1M, .type = MT_DEVICE, }, @@ -151,6 +167,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi) static void __init edb7211_init(void) { + clps711x_devices_init(); +} + +static void __init edb7211_init_late(void) +{ gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios)); platform_device_register(&edb7211_flash_pdev); @@ -163,6 +184,9 @@ static void __init edb7211_init(void) platform_device_register_simple("video-clps711x", 0, NULL, 0); platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource, ARRAY_SIZE(edb7211_cs8900_resource)); + platform_device_register_data(&platform_bus, "i2c-gpio", 0, + &edb7211_i2c_pdata, + sizeof(edb7211_i2c_pdata)); } MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") @@ -172,9 +196,11 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .fixup = fixup_edb7211, .reserve = edb7211_reserve, .map_io = edb7211_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = edb7211_init, + .init_late = edb7211_init_late, .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c index c5675efc8c6..b1561e3d7c5 100644 --- a/arch/arm/mach-clps711x/board-fortunet.c +++ b/arch/arm/mach-clps711x/board-fortunet.c @@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet") .nr_irqs = CLPS711X_NR_IRQS, .fixup = fortunet_fixup, .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .handle_irq = clps711x_handle_irq, diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c index 8d3ee677113..dd81b06f68f 100644 --- a/arch/arm/mach-clps711x/board-p720t.c +++ b/arch/arm/mach-clps711x/board-p720t.c @@ -23,10 +23,12 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/io.h> +#include <linux/gpio.h> #include <linux/slab.h> #include <linux/leds.h> #include <linux/sizes.h> #include <linux/backlight.h> +#include <linux/basic_mmio_gpio.h> #include <linux/platform_device.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand-gpio.h> @@ -38,11 +40,11 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/syspld.h> #include <video/platform_lcd.h> #include "common.h" +#include "devices.h" #define P720T_USERLED CLPS711X_GPIO(3, 0) #define P720T_NAND_CLE CLPS711X_GPIO(4, 0) @@ -51,6 +53,178 @@ #define P720T_NAND_BASE (CLPS711X_SDRAM1_BASE) +#define P720T_MMGPIO_BASE (CLPS711X_NR_GPIO) + +#define SYSPLD_PHYS_BASE IOMEM(CS1_PHYS_BASE) + +#define PLD_INT (SYSPLD_PHYS_BASE + 0x000000) +#define PLD_INT_MMGPIO_BASE (P720T_MMGPIO_BASE + 0) +#define PLD_INT_PENIRQ (PLD_INT_MMGPIO_BASE + 5) +#define PLD_INT_UCB_IRQ (PLD_INT_MMGPIO_BASE + 1) +#define PLD_INT_KBD_ATN (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */ + +#define PLD_PWR (SYSPLD_PHYS_BASE + 0x000004) +#define PLD_PWR_MMGPIO_BASE (P720T_MMGPIO_BASE + 8) +#define PLD_PWR_EXT (PLD_PWR_MMGPIO_BASE + 5) +#define PLD_PWR_MODE (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */ +#define PLD_S4_ON (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */ +#define PLD_S3_ON (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */ +#define PLD_S2_ON (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */ +#define PLD_S1_ON (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */ + +#define PLD_KBD (SYSPLD_PHYS_BASE + 0x000008) +#define PLD_KBD_MMGPIO_BASE (P720T_MMGPIO_BASE + 16) +#define PLD_KBD_WAKE (PLD_KBD_MMGPIO_BASE + 1) +#define PLD_KBD_EN (PLD_KBD_MMGPIO_BASE + 0) + +#define PLD_SPI (SYSPLD_PHYS_BASE + 0x00000c) +#define PLD_SPI_MMGPIO_BASE (P720T_MMGPIO_BASE + 24) +#define PLD_SPI_EN (PLD_SPI_MMGPIO_BASE + 0) + +#define PLD_IO (SYSPLD_PHYS_BASE + 0x000010) +#define PLD_IO_MMGPIO_BASE (P720T_MMGPIO_BASE + 32) +#define PLD_IO_BOOTSEL (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */ +#define PLD_IO_USER (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */ +#define PLD_IO_LED3 (PLD_IO_MMGPIO_BASE + 4) +#define PLD_IO_LED2 (PLD_IO_MMGPIO_BASE + 3) +#define PLD_IO_LED1 (PLD_IO_MMGPIO_BASE + 2) +#define PLD_IO_LED0 (PLD_IO_MMGPIO_BASE + 1) +#define PLD_IO_LEDEN (PLD_IO_MMGPIO_BASE + 0) + +#define PLD_IRDA (SYSPLD_PHYS_BASE + 0x000014) +#define PLD_IRDA_MMGPIO_BASE (P720T_MMGPIO_BASE + 40) +#define PLD_IRDA_EN (PLD_IRDA_MMGPIO_BASE + 0) + +#define PLD_COM2 (SYSPLD_PHYS_BASE + 0x000018) +#define PLD_COM2_MMGPIO_BASE (P720T_MMGPIO_BASE + 48) +#define PLD_COM2_EN (PLD_COM2_MMGPIO_BASE + 0) + +#define PLD_COM1 (SYSPLD_PHYS_BASE + 0x00001c) +#define PLD_COM1_MMGPIO_BASE (P720T_MMGPIO_BASE + 56) +#define PLD_COM1_EN (PLD_COM1_MMGPIO_BASE + 0) + +#define PLD_AUD (SYSPLD_PHYS_BASE + 0x000020) +#define PLD_AUD_MMGPIO_BASE (P720T_MMGPIO_BASE + 64) +#define PLD_AUD_DIV1 (PLD_AUD_MMGPIO_BASE + 6) +#define PLD_AUD_DIV0 (PLD_AUD_MMGPIO_BASE + 5) +#define PLD_AUD_CLK_SEL1 (PLD_AUD_MMGPIO_BASE + 4) +#define PLD_AUD_CLK_SEL0 (PLD_AUD_MMGPIO_BASE + 3) +#define PLD_AUD_MIC_PWR (PLD_AUD_MMGPIO_BASE + 2) +#define PLD_AUD_MIC_GAIN (PLD_AUD_MMGPIO_BASE + 1) +#define PLD_AUD_CODEC_EN (PLD_AUD_MMGPIO_BASE + 0) + +#define PLD_CF (SYSPLD_PHYS_BASE + 0x000024) +#define PLD_CF_MMGPIO_BASE (P720T_MMGPIO_BASE + 72) +#define PLD_CF2_SLEEP (PLD_CF_MMGPIO_BASE + 5) +#define PLD_CF1_SLEEP (PLD_CF_MMGPIO_BASE + 4) +#define PLD_CF2_nPDREQ (PLD_CF_MMGPIO_BASE + 3) +#define PLD_CF1_nPDREQ (PLD_CF_MMGPIO_BASE + 2) +#define PLD_CF2_nIRQ (PLD_CF_MMGPIO_BASE + 1) +#define PLD_CF1_nIRQ (PLD_CF_MMGPIO_BASE + 0) + +#define PLD_SDC (SYSPLD_PHYS_BASE + 0x000028) +#define PLD_SDC_MMGPIO_BASE (P720T_MMGPIO_BASE + 80) +#define PLD_SDC_INT_EN (PLD_SDC_MMGPIO_BASE + 2) +#define PLD_SDC_WP (PLD_SDC_MMGPIO_BASE + 1) +#define PLD_SDC_CD (PLD_SDC_MMGPIO_BASE + 0) + +#define PLD_CODEC (SYSPLD_PHYS_BASE + 0x400000) +#define PLD_CODEC_MMGPIO_BASE (P720T_MMGPIO_BASE + 88) +#define PLD_CODEC_IRQ3 (PLD_CODEC_MMGPIO_BASE + 4) +#define PLD_CODEC_IRQ2 (PLD_CODEC_MMGPIO_BASE + 3) +#define PLD_CODEC_IRQ1 (PLD_CODEC_MMGPIO_BASE + 2) +#define PLD_CODEC_EN (PLD_CODEC_MMGPIO_BASE + 0) + +#define PLD_BRITE (SYSPLD_PHYS_BASE + 0x400004) +#define PLD_BRITE_MMGPIO_BASE (P720T_MMGPIO_BASE + 96) +#define PLD_BRITE_UP (PLD_BRITE_MMGPIO_BASE + 1) +#define PLD_BRITE_DN (PLD_BRITE_MMGPIO_BASE + 0) + +#define PLD_LCDEN (SYSPLD_PHYS_BASE + 0x400008) +#define PLD_LCDEN_MMGPIO_BASE (P720T_MMGPIO_BASE + 104) +#define PLD_LCDEN_EN (PLD_LCDEN_MMGPIO_BASE + 0) + +#define PLD_TCH (SYSPLD_PHYS_BASE + 0x400010) +#define PLD_TCH_MMGPIO_BASE (P720T_MMGPIO_BASE + 112) +#define PLD_TCH_PENIRQ (PLD_TCH_MMGPIO_BASE + 1) +#define PLD_TCH_EN (PLD_TCH_MMGPIO_BASE + 0) + +#define PLD_GPIO (SYSPLD_PHYS_BASE + 0x400014) +#define PLD_GPIO_MMGPIO_BASE (P720T_MMGPIO_BASE + 120) +#define PLD_GPIO2 (PLD_GPIO_MMGPIO_BASE + 2) +#define PLD_GPIO1 (PLD_GPIO_MMGPIO_BASE + 1) +#define PLD_GPIO0 (PLD_GPIO_MMGPIO_BASE + 0) + +static struct gpio p720t_gpios[] __initconst = { + { PLD_S1_ON, GPIOF_OUT_INIT_LOW, "PLD_S1_ON" }, + { PLD_S2_ON, GPIOF_OUT_INIT_LOW, "PLD_S2_ON" }, + { PLD_S3_ON, GPIOF_OUT_INIT_LOW, "PLD_S3_ON" }, + { PLD_S4_ON, GPIOF_OUT_INIT_LOW, "PLD_S4_ON" }, + { PLD_KBD_EN, GPIOF_OUT_INIT_LOW, "PLD_KBD_EN" }, + { PLD_SPI_EN, GPIOF_OUT_INIT_LOW, "PLD_SPI_EN" }, + { PLD_IO_USER, GPIOF_OUT_INIT_LOW, "PLD_IO_USER" }, + { PLD_IO_LED0, GPIOF_OUT_INIT_LOW, "PLD_IO_LED0" }, + { PLD_IO_LED1, GPIOF_OUT_INIT_LOW, "PLD_IO_LED1" }, + { PLD_IO_LED2, GPIOF_OUT_INIT_LOW, "PLD_IO_LED2" }, + { PLD_IO_LED3, GPIOF_OUT_INIT_LOW, "PLD_IO_LED3" }, + { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW, "PLD_IO_LEDEN" }, + { PLD_IRDA_EN, GPIOF_OUT_INIT_LOW, "PLD_IRDA_EN" }, + { PLD_COM1_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM1_EN" }, + { PLD_COM2_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM2_EN" }, + { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW, "PLD_CODEC_EN" }, + { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW, "PLD_LCDEN_EN" }, + { PLD_TCH_EN, GPIOF_OUT_INIT_LOW, "PLD_TCH_EN" }, + { P720T_USERLED,GPIOF_OUT_INIT_LOW, "USER_LED" }, +}; + +static struct resource p720t_mmgpio_resource[] __initdata = { + DEFINE_RES_MEM_NAMED(0, 4, "dat"), +}; + +static struct bgpio_pdata p720t_mmgpio_pdata = { + .ngpio = 8, +}; + +static struct platform_device p720t_mmgpio __initdata = { + .name = "basic-mmio-gpio", + .id = -1, + .resource = p720t_mmgpio_resource, + .num_resources = ARRAY_SIZE(p720t_mmgpio_resource), + .dev = { + .platform_data = &p720t_mmgpio_pdata, + }, +}; + +static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase) +{ + p720t_mmgpio_resource[0].start = (unsigned long)addrbase; + p720t_mmgpio_pdata.base = gpiobase; + + platform_device_register(&p720t_mmgpio); +} + +static struct { + void __iomem *addrbase; + int gpiobase; +} mmgpios[] __initconst = { + { PLD_INT, PLD_INT_MMGPIO_BASE }, + { PLD_PWR, PLD_PWR_MMGPIO_BASE }, + { PLD_KBD, PLD_KBD_MMGPIO_BASE }, + { PLD_SPI, PLD_SPI_MMGPIO_BASE }, + { PLD_IO, PLD_IO_MMGPIO_BASE }, + { PLD_IRDA, PLD_IRDA_MMGPIO_BASE }, + { PLD_COM2, PLD_COM2_MMGPIO_BASE }, + { PLD_COM1, PLD_COM1_MMGPIO_BASE }, + { PLD_AUD, PLD_AUD_MMGPIO_BASE }, + { PLD_CF, PLD_CF_MMGPIO_BASE }, + { PLD_SDC, PLD_SDC_MMGPIO_BASE }, + { PLD_CODEC, PLD_CODEC_MMGPIO_BASE }, + { PLD_BRITE, PLD_BRITE_MMGPIO_BASE }, + { PLD_LCDEN, PLD_LCDEN_MMGPIO_BASE }, + { PLD_TCH, PLD_TCH_MMGPIO_BASE }, + { PLD_GPIO, PLD_GPIO_MMGPIO_BASE }, +}; + static struct resource p720t_nand_resource[] __initdata = { DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4), }; @@ -92,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = { static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) { if (power) { - PLD_LCDEN = PLD_LCDEN_EN; - PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON; + gpio_set_value(PLD_LCDEN_EN, 1); + gpio_set_value(PLD_S1_ON, 1); + gpio_set_value(PLD_S2_ON, 1); + gpio_set_value(PLD_S4_ON, 1); } else { - PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON); - PLD_LCDEN = 0; + gpio_set_value(PLD_S1_ON, 0); + gpio_set_value(PLD_S2_ON, 0); + gpio_set_value(PLD_S4_ON, 0); + gpio_set_value(PLD_LCDEN_EN, 0); } } @@ -106,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = { static void p720t_lcd_backlight_set_intensity(int intensity) { - if (intensity) - PLD_PWR |= PLD_S3_ON; - else - PLD_PWR = 0; + gpio_set_value(PLD_S3_ON, intensity); } static struct generic_bl_info p720t_lcd_backlight_pdata = { @@ -119,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = { .set_bl_intensity = p720t_lcd_backlight_set_intensity, }; -/* - * Map the P720T system PLD. It occupies two address spaces: - * 0x10000000 and 0x10400000. We map both regions as one. - */ -static struct map_desc p720t_io_desc[] __initdata = { - { - .virtual = SYSPLD_VIRT_BASE, - .pfn = __phys_to_pfn(SYSPLD_PHYS_BASE), - .length = SZ_8M, - .type = MT_DEVICE, - }, -}; - static void __init fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi) { @@ -157,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi) } } -static void __init p720t_map_io(void) -{ - clps711x_map_io(); - iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc)); -} - -static void __init p720t_init_early(void) -{ - /* - * Power down as much as possible in case we don't - * have the drivers loaded. - */ - PLD_LCDEN = 0; - PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON); - - PLD_KBD = 0; - PLD_IO = 0; - PLD_IRDA = 0; - PLD_CODEC = 0; - PLD_TCH = 0; - PLD_SPI = 0; - if (!IS_ENABLED(CONFIG_DEBUG_LL)) { - PLD_COM2 = 0; - PLD_COM1 = 0; - } -} - static struct gpio_led p720t_gpio_leds[] = { { .name = "User LED", @@ -199,7 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = { static void __init p720t_init(void) { + int i; + + clps711x_devices_init(); + + for (i = 0; i < ARRAY_SIZE(mmgpios); i++) + p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase); + platform_device_register(&p720t_nand_pdev); +} + +static void __init p720t_init_late(void) +{ + WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios))); + platform_device_register_data(&platform_bus, "platform-lcd", 0, &p720t_lcd_power_pdata, sizeof(p720t_lcd_power_pdata)); @@ -207,10 +355,6 @@ static void __init p720t_init(void) &p720t_lcd_backlight_pdata, sizeof(p720t_lcd_backlight_pdata)); platform_device_register_simple("video-clps711x", 0, NULL, 0); -} - -static void __init p720t_init_late(void) -{ platform_device_register_data(&platform_bus, "leds-gpio", 0, &p720t_gpio_led_pdata, sizeof(p720t_gpio_led_pdata)); @@ -221,8 +365,8 @@ MACHINE_START(P720T, "ARM-Prospector720T") .atag_offset = 0x100, .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_p720t, - .map_io = p720t_map_io, - .init_early = p720t_init_early, + .map_io = clps711x_map_io, + .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = p720t_init, diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 20ff50f3ccf..f6d1746366d 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -27,12 +27,14 @@ #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clockchips.h> +#include <linux/clocksource.h> #include <linux/clk-provider.h> #include <asm/exception.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> +#include <asm/sched_clock.h> #include <asm/system_misc.h> #include <mach/hardware.h> @@ -213,7 +215,7 @@ void __init clps711x_init_irq(void) } } -inline u32 fls16(u32 x) +static inline u32 fls16(u32 x) { u32 r = 15; @@ -237,27 +239,52 @@ inline u32 fls16(u32 x) asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) { - u32 irqstat; - void __iomem *base = CLPS711X_VIRT_BASE; - - irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1); - if (irqstat) { - handle_IRQ(fls16(irqstat), regs); - return; - } + do { + u32 irqstat; + void __iomem *base = CLPS711X_VIRT_BASE; + + irqstat = readw_relaxed(base + INTSR1) & + readw_relaxed(base + INTMR1); + if (irqstat) + handle_IRQ(fls16(irqstat), regs); + + irqstat = readw_relaxed(base + INTSR2) & + readw_relaxed(base + INTMR2); + if (irqstat) { + handle_IRQ(fls16(irqstat) + 16, regs); + continue; + } + + break; + } while (1); +} - irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2); - if (likely(irqstat)) - handle_IRQ(fls16(irqstat) + 16, regs); +static u32 notrace clps711x_sched_clock_read(void) +{ + return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); } static void clps711x_clockevent_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { + disable_irq(IRQ_TC2OI); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + enable_irq(IRQ_TC2OI); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* Not supported */ + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } } static struct clock_event_device clockevent_clps711x = { - .name = "CLPS711x Clockevents", + .name = "clps711x-clockevent", .rating = 300, .features = CLOCK_EVT_FEAT_PERIODIC, .set_mode = clps711x_clockevent_set_mode, @@ -271,8 +298,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id) } static struct irqaction clps711x_timer_irq = { - .name = "CLPS711x Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .name = "clps711x-timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = clps711x_timer_interrupt, }; @@ -301,6 +328,7 @@ void __init clps711x_timer_init(void) cpu = ext; bus = cpu; spi = 135400; + pll = 0; } else { cpu = pll; if (cpu >= 36864000) @@ -319,9 +347,9 @@ void __init clps711x_timer_init(void) else timh = 541440; } else - timh = cpu / 144; + timh = DIV_ROUND_CLOSEST(cpu, 144); - timl = timh / 256; + timl = DIV_ROUND_CLOSEST(timh, 256); /* All clocks are fixed */ add_fixed_clk(clk_pll, "pll", pll); @@ -334,13 +362,24 @@ void __init clps711x_timer_init(void) pr_info("CPU frequency set at %i Hz.\n", cpu); + /* Start Timer1 in free running mode (Low frequency) */ + tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); + clps_writel(tmp, SYSCON1); + + setup_sched_clock(clps711x_sched_clock_read, 16, timl); + + clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, + "clps711x_clocksource", timl, 300, 16, + clocksource_mmio_readw_down); + + /* Set Timer2 prescaler */ clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D); - tmp = clps_readl(SYSCON1); - tmp |= SYSCON1_TC2S | SYSCON1_TC2M; + /* Start Timer2 in prescale mode (High frequency)*/ + tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S; clps_writel(tmp, SYSCON1); - clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff); + clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0); setup_irq(IRQ_TC2OI, &clps711x_timer_irq); } @@ -353,15 +392,11 @@ void clps711x_restart(char mode, const char *cmd) static void clps711x_idle(void) { clps_writel(1, HALT); - __asm__ __volatile__( - "mov r0, r0\n\ - mov r0, r0"); + asm("mov r0, r0"); + asm("mov r0, r0"); } -static int __init clps711x_idle_init(void) +void __init clps711x_init_early(void) { arm_pm_idle = clps711x_idle; - return 0; } - -arch_initcall(clps711x_idle_init); diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h index f84a7292c70..2a22f4c6cc7 100644 --- a/arch/arm/mach-clps711x/common.h +++ b/arch/arm/mach-clps711x/common.h @@ -13,3 +13,4 @@ extern void clps711x_init_irq(void); extern void clps711x_timer_init(void); extern void clps711x_handle_irq(struct pt_regs *regs); extern void clps711x_restart(char mode, const char *cmd); +extern void clps711x_init_early(void); diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c new file mode 100644 index 00000000000..856b81cf2f8 --- /dev/null +++ b/arch/arm/mach-clps711x/devices.c @@ -0,0 +1,68 @@ +/* + * CLPS711X common devices definitions + * + * Author: Alexander Shiyan <shc_work@mail.ru>, 2013 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/platform_device.h> +#include <linux/sizes.h> + +#include <mach/hardware.h> + +static const phys_addr_t clps711x_gpios[][2] __initconst = { + { PADR, PADDR }, + { PBDR, PBDDR }, + { PCDR, PCDDR }, + { PDDR, PDDDR }, + { PEDR, PEDDR }, +}; + +static void __init clps711x_add_gpio(void) +{ + unsigned i; + struct resource gpio_res[2]; + + memset(gpio_res, 0, sizeof(gpio_res)); + + gpio_res[0].flags = IORESOURCE_MEM; + gpio_res[1].flags = IORESOURCE_MEM; + + for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) { + gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0]; + gpio_res[0].end = gpio_res[0].start; + gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1]; + gpio_res[1].end = gpio_res[1].start; + + platform_device_register_simple("clps711x-gpio", i, + gpio_res, ARRAY_SIZE(gpio_res)); + } +} + +const struct resource clps711x_syscon_res[] __initconst = { + /* SYSCON1, SYSFLG1 */ + DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128), + /* SYSCON2, SYSFLG2 */ + DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128), + /* SYSCON3 */ + DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64), +}; + +static void __init clps711x_add_syscon(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++) + platform_device_register_simple("clps711x-syscon", i + 1, + &clps711x_syscon_res[i], 1); +} + +void __init clps711x_devices_init(void) +{ + clps711x_add_gpio(); + clps711x_add_syscon(); +} diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h new file mode 100644 index 00000000000..a5efc1744b8 --- /dev/null +++ b/arch/arm/mach-clps711x/devices.h @@ -0,0 +1,12 @@ +/* + * CLPS711X common devices definitions + * + * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +void clps711x_devices_init(void); diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h deleted file mode 100644 index 0452f5f3f03..00000000000 --- a/arch/arm/mach-clps711x/include/mach/autcpu12.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * AUTCPU12 specific defines - * - * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_AUTCPU12_H -#define __ASM_ARCH_AUTCPU12_H - -/* - * The flash bank is wired to chip select 0 - */ -#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */ - -/* offset for device specific information structure */ -#define AUTCPU12_LCDINFO_OFFS (0x00010000) - -/* Videomemory in the internal SRAM (CS 6) */ -#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE - -/* -* All special IO's are tied to CS1 -*/ -#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */ - -#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */ - -#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */ - -#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */ - -#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */ - -#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */ - -#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */ - -/* -* defines for lcd contrast -*/ -#define AUTCPU12_DPOT_PORT_OFFSET PEDR -#define AUTCPU12_DPOT_CS (1<<0) -#define AUTCPU12_DPOT_CLK (1<<1) -#define AUTCPU12_DPOT_UD (1<<2) - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 01d1b955971..0286f4bf994 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -21,6 +21,8 @@ #ifndef __MACH_CLPS711X_H #define __MACH_CLPS711X_H +#include <linux/mfd/syscon/clps711x.h> + #define CLPS711X_PHYS_BASE (0x80000000) #define PADR (0x0000) @@ -96,83 +98,9 @@ #define RANDID2 (0x2708) #define RANDID3 (0x270c) -/* common bits: SYSCON1 / SYSCON2 */ -#define SYSCON_UARTEN (1 << 8) - -#define SYSCON1_KBDSCAN(x) ((x) & 15) -#define SYSCON1_KBDSCANMASK (15) -#define SYSCON1_TC1M (1 << 4) -#define SYSCON1_TC1S (1 << 5) -#define SYSCON1_TC2M (1 << 6) -#define SYSCON1_TC2S (1 << 7) -#define SYSCON1_UART1EN SYSCON_UARTEN -#define SYSCON1_BZTOG (1 << 9) -#define SYSCON1_BZMOD (1 << 10) -#define SYSCON1_DBGEN (1 << 11) -#define SYSCON1_LCDEN (1 << 12) -#define SYSCON1_CDENTX (1 << 13) -#define SYSCON1_CDENRX (1 << 14) -#define SYSCON1_SIREN (1 << 15) -#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) -#define SYSCON1_ADCKSEL_MASK (3 << 16) -#define SYSCON1_EXCKEN (1 << 18) -#define SYSCON1_WAKEDIS (1 << 19) -#define SYSCON1_IRTXM (1 << 20) - -/* common bits: SYSFLG1 / SYSFLG2 */ -#define SYSFLG_UBUSY (1 << 11) -#define SYSFLG_URXFE (1 << 22) -#define SYSFLG_UTXFF (1 << 23) - -#define SYSFLG1_MCDR (1 << 0) -#define SYSFLG1_DCDET (1 << 1) -#define SYSFLG1_WUDR (1 << 2) -#define SYSFLG1_WUON (1 << 3) -#define SYSFLG1_CTS (1 << 8) -#define SYSFLG1_DSR (1 << 9) -#define SYSFLG1_DCD (1 << 10) -#define SYSFLG1_UBUSY SYSFLG_UBUSY -#define SYSFLG1_NBFLG (1 << 12) -#define SYSFLG1_RSTFLG (1 << 13) -#define SYSFLG1_PFFLG (1 << 14) -#define SYSFLG1_CLDFLG (1 << 15) -#define SYSFLG1_URXFE SYSFLG_URXFE -#define SYSFLG1_UTXFF SYSFLG_UTXFF -#define SYSFLG1_CRXFE (1 << 24) -#define SYSFLG1_CTXFF (1 << 25) -#define SYSFLG1_SSIBUSY (1 << 26) -#define SYSFLG1_ID (1 << 29) -#define SYSFLG1_VERID(x) (((x) >> 30) & 3) -#define SYSFLG1_VERID_MASK (3 << 30) - -#define SYSFLG2_SSRXOF (1 << 0) -#define SYSFLG2_RESVAL (1 << 1) -#define SYSFLG2_RESFRM (1 << 2) -#define SYSFLG2_SS2RXFE (1 << 3) -#define SYSFLG2_SS2TXFF (1 << 4) -#define SYSFLG2_SS2TXUF (1 << 5) -#define SYSFLG2_CKMODE (1 << 6) -#define SYSFLG2_UBUSY SYSFLG_UBUSY -#define SYSFLG2_URXFE SYSFLG_URXFE -#define SYSFLG2_UTXFF SYSFLG_UTXFF - #define LCDCON_GSEN (1 << 30) #define LCDCON_GSMD (1 << 31) -#define SYSCON2_SERSEL (1 << 0) -#define SYSCON2_KBD6 (1 << 1) -#define SYSCON2_DRAMZ (1 << 2) -#define SYSCON2_KBWEN (1 << 3) -#define SYSCON2_SS2TXEN (1 << 4) -#define SYSCON2_PCCARD1 (1 << 5) -#define SYSCON2_PCCARD2 (1 << 6) -#define SYSCON2_SS2RXEN (1 << 7) -#define SYSCON2_UART2EN SYSCON_UARTEN -#define SYSCON2_SS2MAEN (1 << 9) -#define SYSCON2_OSTB (1 << 12) -#define SYSCON2_CLKENSL (1 << 13) -#define SYSCON2_BUZFREQ (1 << 14) - /* common bits: UARTDR1 / UARTDR2 */ #define UARTDR_FRMERR (1 << 8) #define UARTDR_PARERR (1 << 9) @@ -228,18 +156,6 @@ #define DAI64FS_MCLK256EN (1 << 3) #define DAI64FS_LOOPBACK (1 << 5) -#define SYSCON3_ADCCON (1 << 0) -#define SYSCON3_CLKCTL0 (1 << 1) -#define SYSCON3_CLKCTL1 (1 << 2) -#define SYSCON3_DAISEL (1 << 3) -#define SYSCON3_ADCCKNSEN (1 << 4) -#define SYSCON3_VERSN(x) (((x) >> 5) & 7) -#define SYSCON3_VERSN_MASK (7 << 5) -#define SYSCON3_FASTWAKE (1 << 8) -#define SYSCON3_DAIEN (1 << 9) -#define SYSCON3_128FS SYSCON3_DAIEN -#define SYSCON3_ENPD67 (1 << 10) - #define SDCONF_ACTIVE (1 << 10) #define SDCONF_CLKCTL (1 << 9) #define SDCONF_WIDTH_4 (0 << 7) diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 2f23dd5d73e..c5a8ea6839e 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -70,11 +70,4 @@ #define CLPS711X_SDRAM0_BASE (0xc0000000) #define CLPS711X_SDRAM1_BASE (0xd0000000) -#if defined (CONFIG_ARCH_EDB7211) - -/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */ -#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE - -#endif /* CONFIG_ARCH_EDB7211 */ - #endif diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h deleted file mode 100644 index fc0e028d940..00000000000 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/memory.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0xc0000000) - -/* - * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 - * uses only one of the two banks (bank #1). However, even within - * bank #1, memory is discontiguous. - * - * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between - * them, so we use 24 for the node max shift to get 16MB node sizes. - */ - -#define SECTION_SIZE_BITS 24 -#define MAX_PHYSMEM_BITS 32 - -#endif - diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h deleted file mode 100644 index 9a433155bf5..00000000000 --- a/arch/arm/mach-clps711x/include/mach/syspld.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/syspld.h - * - * System Control PLD register definitions. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_SYSPLD_H -#define __ASM_ARCH_SYSPLD_H - -#define SYSPLD_PHYS_BASE (0x10000000) -#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE) - -#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off))) - -#define PLD_INT SYSPLD_REG(u32, 0x000000) -#define PLD_INT_PENIRQ (1 << 5) -#define PLD_INT_UCB_IRQ (1 << 1) -#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */ - -#define PLD_PWR SYSPLD_REG(u32, 0x000004) -#define PLD_PWR_EXT (1 << 5) -#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */ -#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */ -#define PLD_S3_ON (1 << 2) /* LCD backlight enable */ -#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */ -#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */ - -#define PLD_KBD SYSPLD_REG(u32, 0x000008) -#define PLD_KBD_WAKE (1 << 1) -#define PLD_KBD_EN (1 << 0) - -#define PLD_SPI SYSPLD_REG(u32, 0x00000c) -#define PLD_SPI_EN (1 << 0) - -#define PLD_IO SYSPLD_REG(u32, 0x000010) -#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */ -#define PLD_IO_USER (1 << 5) /* user defined switch */ -#define PLD_IO_LED3 (1 << 4) -#define PLD_IO_LED2 (1 << 3) -#define PLD_IO_LED1 (1 << 2) -#define PLD_IO_LED0 (1 << 1) -#define PLD_IO_LEDEN (1 << 0) - -#define PLD_IRDA SYSPLD_REG(u32, 0x000014) -#define PLD_IRDA_EN (1 << 0) - -#define PLD_COM2 SYSPLD_REG(u32, 0x000018) -#define PLD_COM2_EN (1 << 0) - -#define PLD_COM1 SYSPLD_REG(u32, 0x00001c) -#define PLD_COM1_EN (1 << 0) - -#define PLD_AUD SYSPLD_REG(u32, 0x000020) -#define PLD_AUD_DIV1 (1 << 6) -#define PLD_AUD_DIV0 (1 << 5) -#define PLD_AUD_CLK_SEL1 (1 << 4) -#define PLD_AUD_CLK_SEL0 (1 << 3) -#define PLD_AUD_MIC_PWR (1 << 2) -#define PLD_AUD_MIC_GAIN (1 << 1) -#define PLD_AUD_CODEC_EN (1 << 0) - -#define PLD_CF SYSPLD_REG(u32, 0x000024) -#define PLD_CF2_SLEEP (1 << 5) -#define PLD_CF1_SLEEP (1 << 4) -#define PLD_CF2_nPDREQ (1 << 3) -#define PLD_CF1_nPDREQ (1 << 2) -#define PLD_CF2_nIRQ (1 << 1) -#define PLD_CF1_nIRQ (1 << 0) - -#define PLD_SDC SYSPLD_REG(u32, 0x000028) -#define PLD_SDC_INT_EN (1 << 2) -#define PLD_SDC_WP (1 << 1) -#define PLD_SDC_CD (1 << 0) - -#define PLD_FPGA SYSPLD_REG(u32, 0x00002c) - -#define PLD_CODEC SYSPLD_REG(u32, 0x400000) -#define PLD_CODEC_IRQ3 (1 << 4) -#define PLD_CODEC_IRQ2 (1 << 3) -#define PLD_CODEC_IRQ1 (1 << 2) -#define PLD_CODEC_EN (1 << 0) - -#define PLD_BRITE SYSPLD_REG(u32, 0x400004) -#define PLD_BRITE_UP (1 << 1) -#define PLD_BRITE_DN (1 << 0) - -#define PLD_LCDEN SYSPLD_REG(u32, 0x400008) -#define PLD_LCDEN_EN (1 << 0) - -#define PLD_ID SYSPLD_REG(u32, 0x40000c) - -#define PLD_TCH SYSPLD_REG(u32, 0x400010) -#define PLD_TCH_PENIRQ (1 << 1) -#define PLD_TCH_EN (1 << 0) - -#define PLD_GPIO SYSPLD_REG(u32, 0x400014) -#define PLD_GPIO2 (1 << 2) -#define PLD_GPIO1 (1 << 1) -#define PLD_GPIO0 (1 << 0) - -#endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index dd1ffccc75e..63997a1128e 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,7 @@ # Common objects obj-y := time.o clock.o serial.o psc.o \ - dma.o usb.o common.o sram.o aemif.o + usb.o common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 739be7e738f..513eee14f77 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -151,7 +151,6 @@ static __init void davinci_sffsdr_init(void) } MACHINE_START(SFFSDR, "Lyrtech SFFSDR") - /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ .atag_offset = 0x100, .map_io = davinci_sffsdr_map_io, .init_irq = davinci_irq_init, diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index ba798370fc9..78ea395d2ac 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -26,12 +26,12 @@ #include <linux/input.h> #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> +#include <linux/platform_data/edma.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/irqs.h> -#include <mach/edma.h> #include <mach/mux.h> #include <mach/cp_intc.h> #include <mach/tnetv107x.h> diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 1ab3df423da..a883043d082 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -23,9 +23,9 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> #include <linux/platform_data/davinci_asp.h> +#include <linux/platform_data/edma.h> #include <linux/platform_data/keyscan-davinci.h> #include <mach/hardware.h> -#include <mach/edma.h> #include <media/davinci/vpfe_capture.h> #include <media/davinci/vpif_types.h> @@ -77,32 +77,32 @@ void davinci_map_sysmod(void); #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 /* DM355 function declarations */ -void __init dm355_init(void); +void dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); -void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); +void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); int dm355_init_video(struct vpfe_config *, struct vpbe_config *); /* DM365 function declarations */ -void __init dm365_init(void); -void __init dm365_init_asp(struct snd_platform_data *pdata); -void __init dm365_init_vc(struct snd_platform_data *pdata); -void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); -void __init dm365_init_rtc(void); +void dm365_init(void); +void dm365_init_asp(struct snd_platform_data *pdata); +void dm365_init_vc(struct snd_platform_data *pdata); +void dm365_init_ks(struct davinci_ks_platform_data *pdata); +void dm365_init_rtc(void); void dm365_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); int dm365_init_video(struct vpfe_config *, struct vpbe_config *); /* DM644x function declarations */ -void __init dm644x_init(void); -void __init dm644x_init_asp(struct snd_platform_data *pdata); -int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *); +void dm644x_init(void); +void dm644x_init_asp(struct snd_platform_data *pdata); +int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); /* DM646x function declarations */ -void __init dm646x_init(void); -void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); -void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); -int __init dm646x_init_edma(struct edma_rsv_info *rsv); +void dm646x_init(void); +void dm646x_init_mcasp0(struct snd_platform_data *pdata); +void dm646x_init_mcasp1(struct snd_platform_data *pdata); +int dm646x_init_edma(struct edma_rsv_info *rsv); void dm646x_video_init(void); void dm646x_setup_vpif(struct vpif_display_config *, struct vpif_capture_config *); diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index bf572525175..eb254fe861a 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -105,27 +105,27 @@ struct platform_device da8xx_serial_device = { }, }; -static const s8 da8xx_queue_tc_mapping[][2] = { +static s8 da8xx_queue_tc_mapping[][2] = { /* {event queue no, TC no} */ {0, 0}, {1, 1}, {-1, -1} }; -static const s8 da8xx_queue_priority_mapping[][2] = { +static s8 da8xx_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, {1, 7}, {-1, -1} }; -static const s8 da850_queue_tc_mapping[][2] = { +static s8 da850_queue_tc_mapping[][2] = { /* {event queue no, TC no} */ {0, 0}, {-1, -1} }; -static const s8 da850_queue_priority_mapping[][2] = { +static s8 da850_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, {-1, -1} diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index cfb194df18e..128cb9ae80f 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -18,10 +18,10 @@ #include <linux/dma-mapping.h> #include <linux/clk.h> #include <linux/slab.h> +#include <linux/platform_data/edma.h> #include <mach/common.h> #include <mach/irqs.h> -#include <mach/edma.h> #include <mach/tnetv107x.h> #include "clock.h" @@ -58,14 +58,14 @@ #define TNETV107X_DMACH_SDIO1_RX 28 #define TNETV107X_DMACH_SDIO1_TX 29 -static const s8 edma_tc_mapping[][2] = { +static s8 edma_tc_mapping[][2] = { /* event queue no TC no */ { 0, 0 }, { 1, 1 }, { -1, -1 } }; -static const s8 edma_priority_mapping[][2] = { +static s8 edma_priority_mapping[][2] = { /* event queue no Prio */ { 0, 3 }, { 1, 7 }, diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index a7068a3aa9d..90b83d00fe2 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -19,9 +19,10 @@ #include <mach/irqs.h> #include <mach/cputype.h> #include <mach/mux.h> -#include <mach/edma.h> #include <linux/platform_data/mmc-davinci.h> #include <mach/time.h> +#include <linux/platform_data/edma.h> + #include "davinci.h" #include "clock.h" @@ -34,6 +35,9 @@ #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD1_BASE 0x01D00000 +#define DAVINCI_DMA_MMCRXEVT 26 +#define DAVINCI_DMA_MMCTXEVT 27 + void __iomem *davinci_sysmod_base; void davinci_map_sysmod(void) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index a11034a358f..42ef53f62c6 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -19,7 +19,6 @@ #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> @@ -28,6 +27,7 @@ #include <mach/common.h> #include <linux/platform_data/spi-davinci.h> #include <mach/gpio-davinci.h> +#include <linux/platform_data/edma.h> #include "davinci.h" #include "clock.h" @@ -569,7 +569,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ -static const s8 +static s8 queue_tc_mapping[][2] = { /* {event queue no, TC no} */ {0, 0}, @@ -577,7 +577,7 @@ queue_tc_mapping[][2] = { {-1, -1}, }; -static const s8 +static s8 queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 40fa4fee933..fa7af5eda52 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -18,11 +18,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/spi/spi.h> +#include <linux/platform_data/edma.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/psc.h> #include <mach/mux.h> #include <mach/irqs.h> @@ -826,7 +826,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { }; /* Four Transfer Controllers on DM365 */ -static const s8 +static s8 dm365_queue_tc_mapping[][2] = { /* {event queue no, TC no} */ {0, 0}, @@ -836,7 +836,7 @@ dm365_queue_tc_mapping[][2] = { {-1, -1}, }; -static const s8 +static s8 dm365_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 7}, diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 4d37d3e2a19..a49d18246fe 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -12,11 +12,11 @@ #include <linux/clk.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> +#include <linux/platform_data/edma.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> @@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ -static const s8 +static s8 queue_tc_mapping[][2] = { /* {event queue no, TC no} */ {0, 0}, @@ -505,7 +505,7 @@ queue_tc_mapping[][2] = { {-1, -1}, }; -static const s8 +static s8 queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index ac7b431c4c8..d1259e80141 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -13,11 +13,11 @@ #include <linux/clk.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> +#include <linux/platform_data/edma.h> #include <asm/mach/map.h> #include <mach/cputype.h> -#include <mach/edma.h> #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> @@ -531,7 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ /* Four Transfer Controllers on DM646x */ -static const s8 +static s8 dm646x_queue_tc_mapping[][2] = { /* {event queue no, TC no} */ {0, 0}, @@ -541,7 +541,7 @@ dm646x_queue_tc_mapping[][2] = { {-1, -1}, }; -static const s8 +static s8 dm646x_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 4}, diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index d13d8dfa2b0..827bbe9baed 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -51,7 +51,7 @@ #define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) -void __init cp_intc_init(void); -int __init cp_intc_of_init(struct device_node *, struct device_node *); +void cp_intc_init(void); +int cp_intc_of_init(struct device_node *, struct device_node *); #endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 2e1c9eae0a5..3c797e2272f 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -20,8 +20,8 @@ #include <linux/videodev2.h> #include <mach/serial.h> -#include <mach/edma.h> #include <mach/pm.h> +#include <linux/platform_data/edma.h> #include <linux/platform_data/i2c-davinci.h> #include <linux/platform_data/mmc-davinci.h> #include <linux/platform_data/usb-davinci.h> @@ -79,8 +79,8 @@ extern unsigned int da850_max_speed; #define DA8XX_SHARED_RAM_BASE 0x80000000 #define DA8XX_ARM_RAM_BASE 0xffff0000 -void __init da830_init(void); -void __init da850_init(void); +void da830_init(void); +void da850_init(void); int da830_register_edma(struct edma_rsv_info *rsv); int da850_register_edma(struct edma_rsv_info *rsv[2]); @@ -94,17 +94,17 @@ int da8xx_register_uio_pruss(void); int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); int da850_register_mmcsd1(struct davinci_mmc_config *config); -void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); +void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); -void __iomem * __init da8xx_get_mem_ctlr(void); +void __iomem *da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); -int __init da850_register_sata(unsigned long refclkpn); -int __init da850_register_vpif(void); -int __init da850_register_vpif_display +int da850_register_sata(unsigned long refclkpn); +int da850_register_vpif(void); +int da850_register_vpif_display (struct vpif_display_config *display_config); -int __init da850_register_vpif_capture +int da850_register_vpif_capture (struct vpif_capture_config *capture_config); void da8xx_restart(char mode, const char *cmd); void da8xx_rproc_reserve_cma(void); diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h deleted file mode 100644 index 7e84c906cef..00000000000 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * TI DAVINCI dma definitions - * - * Copyright (C) 2006-2009 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -/* - * This EDMA3 programming framework exposes two basic kinds of resource: - * - * Channel Triggers transfers, usually from a hardware event but - * also manually or by "chaining" from DMA completions. - * Each channel is coupled to a Parameter RAM (PaRAM) slot. - * - * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM - * "set"), source and destination addresses, a link to a - * next PaRAM slot (if any), options for the transfer, and - * instructions for updating those addresses. There are - * more than twice as many slots as event channels. - * - * Each PaRAM set describes a sequence of transfers, either for one large - * buffer or for several discontiguous smaller buffers. An EDMA transfer - * is driven only from a channel, which performs the transfers specified - * in its PaRAM slot until there are no more transfers. When that last - * transfer completes, the "link" field may be used to reload the channel's - * PaRAM slot with a new transfer descriptor. - * - * The EDMA Channel Controller (CC) maps requests from channels into physical - * Transfer Controller (TC) requests when the channel triggers (by hardware - * or software events, or by chaining). The two physical DMA channels provided - * by the TCs are thus shared by many logical channels. - * - * DaVinci hardware also has a "QDMA" mechanism which is not currently - * supported through this interface. (DSP firmware uses it though.) - */ - -#ifndef EDMA_H_ -#define EDMA_H_ - -/* PaRAM slots are laid out like this */ -struct edmacc_param { - unsigned int opt; - unsigned int src; - unsigned int a_b_cnt; - unsigned int dst; - unsigned int src_dst_bidx; - unsigned int link_bcntrld; - unsigned int src_dst_cidx; - unsigned int ccnt; -}; - -#define CCINT0_INTERRUPT 16 -#define CCERRINT_INTERRUPT 17 -#define TCERRINT0_INTERRUPT 18 -#define TCERRINT1_INTERRUPT 19 - -/* fields in edmacc_param.opt */ -#define SAM BIT(0) -#define DAM BIT(1) -#define SYNCDIM BIT(2) -#define STATIC BIT(3) -#define EDMA_FWID (0x07 << 8) -#define TCCMODE BIT(11) -#define EDMA_TCC(t) ((t) << 12) -#define TCINTEN BIT(20) -#define ITCINTEN BIT(21) -#define TCCHEN BIT(22) -#define ITCCHEN BIT(23) - -#define TRWORD (0x7<<2) -#define PAENTRY (0x1ff<<5) - -/* Drivers should avoid using these symbolic names for dm644x - * channels, and use platform_device IORESOURCE_DMA resources - * instead. (Other DaVinci chips have different peripherals - * and thus have different DMA channel mappings.) - */ -#define DAVINCI_DMA_MCBSP_TX 2 -#define DAVINCI_DMA_MCBSP_RX 3 -#define DAVINCI_DMA_VPSS_HIST 4 -#define DAVINCI_DMA_VPSS_H3A 5 -#define DAVINCI_DMA_VPSS_PRVU 6 -#define DAVINCI_DMA_VPSS_RSZ 7 -#define DAVINCI_DMA_IMCOP_IMXINT 8 -#define DAVINCI_DMA_IMCOP_VLCDINT 9 -#define DAVINCI_DMA_IMCO_PASQINT 10 -#define DAVINCI_DMA_IMCOP_DSQINT 11 -#define DAVINCI_DMA_SPI_SPIX 16 -#define DAVINCI_DMA_SPI_SPIR 17 -#define DAVINCI_DMA_UART0_URXEVT0 18 -#define DAVINCI_DMA_UART0_UTXEVT0 19 -#define DAVINCI_DMA_UART1_URXEVT1 20 -#define DAVINCI_DMA_UART1_UTXEVT1 21 -#define DAVINCI_DMA_UART2_URXEVT2 22 -#define DAVINCI_DMA_UART2_UTXEVT2 23 -#define DAVINCI_DMA_MEMSTK_MSEVT 24 -#define DAVINCI_DMA_MMCRXEVT 26 -#define DAVINCI_DMA_MMCTXEVT 27 -#define DAVINCI_DMA_I2C_ICREVT 28 -#define DAVINCI_DMA_I2C_ICXEVT 29 -#define DAVINCI_DMA_GPIO_GPINT0 32 -#define DAVINCI_DMA_GPIO_GPINT1 33 -#define DAVINCI_DMA_GPIO_GPINT2 34 -#define DAVINCI_DMA_GPIO_GPINT3 35 -#define DAVINCI_DMA_GPIO_GPINT4 36 -#define DAVINCI_DMA_GPIO_GPINT5 37 -#define DAVINCI_DMA_GPIO_GPINT6 38 -#define DAVINCI_DMA_GPIO_GPINT7 39 -#define DAVINCI_DMA_GPIO_GPBNKINT0 40 -#define DAVINCI_DMA_GPIO_GPBNKINT1 41 -#define DAVINCI_DMA_GPIO_GPBNKINT2 42 -#define DAVINCI_DMA_GPIO_GPBNKINT3 43 -#define DAVINCI_DMA_GPIO_GPBNKINT4 44 -#define DAVINCI_DMA_TIMER0_TINT0 48 -#define DAVINCI_DMA_TIMER1_TINT1 49 -#define DAVINCI_DMA_TIMER2_TINT2 50 -#define DAVINCI_DMA_TIMER3_TINT3 51 -#define DAVINCI_DMA_PWM0 52 -#define DAVINCI_DMA_PWM1 53 -#define DAVINCI_DMA_PWM2 54 - -/* DA830 specific EDMA3 information */ -#define EDMA_DA830_NUM_DMACH 32 -#define EDMA_DA830_NUM_TCC 32 -#define EDMA_DA830_NUM_PARAMENTRY 128 -#define EDMA_DA830_NUM_EVQUE 2 -#define EDMA_DA830_NUM_TC 2 -#define EDMA_DA830_CHMAP_EXIST 0 -#define EDMA_DA830_NUM_REGIONS 4 -#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu -#define DA830_DMACH2EVENT_MAP1 0x00000000u -#define DA830_EDMA_ARM_OWN 0x30FFCCFFu - -/*ch_status paramater of callback function possible values*/ -#define DMA_COMPLETE 1 -#define DMA_CC_ERROR 2 -#define DMA_TC1_ERROR 3 -#define DMA_TC2_ERROR 4 - -enum address_mode { - INCR = 0, - FIFO = 1 -}; - -enum fifo_width { - W8BIT = 0, - W16BIT = 1, - W32BIT = 2, - W64BIT = 3, - W128BIT = 4, - W256BIT = 5 -}; - -enum dma_event_q { - EVENTQ_0 = 0, - EVENTQ_1 = 1, - EVENTQ_2 = 2, - EVENTQ_3 = 3, - EVENTQ_DEFAULT = -1 -}; - -enum sync_dimension { - ASYNC = 0, - ABSYNC = 1 -}; - -#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) -#define EDMA_CTLR(i) ((i) >> 16) -#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) - -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ -#define EDMA_CONT_PARAMS_ANY 1001 -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 -#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 - -#define EDMA_MAX_CC 2 - -/* alloc/free DMA channels and their dedicated parameter RAM slots */ -int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data, enum dma_event_q); -void edma_free_channel(unsigned channel); - -/* alloc/free parameter RAM slots */ -int edma_alloc_slot(unsigned ctlr, int slot); -void edma_free_slot(unsigned slot); - -/* alloc/free a set of contiguous parameter RAM slots */ -int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); -int edma_free_cont_slots(unsigned slot, int count); - -/* calls that operate on part of a parameter RAM slot */ -void edma_set_src(unsigned slot, dma_addr_t src_port, - enum address_mode mode, enum fifo_width); -void edma_set_dest(unsigned slot, dma_addr_t dest_port, - enum address_mode mode, enum fifo_width); -void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst); -void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); -void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); -void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, - u16 bcnt_rld, enum sync_dimension sync_mode); -void edma_link(unsigned from, unsigned to); -void edma_unlink(unsigned from); - -/* calls that operate on an entire parameter RAM slot */ -void edma_write_slot(unsigned slot, const struct edmacc_param *params); -void edma_read_slot(unsigned slot, struct edmacc_param *params); - -/* channel control operations */ -int edma_start(unsigned channel); -void edma_stop(unsigned channel); -void edma_clean_channel(unsigned channel); -void edma_clear_event(unsigned channel); -void edma_pause(unsigned channel); -void edma_resume(unsigned channel); - -struct edma_rsv_info { - - const s16 (*rsv_chans)[2]; - const s16 (*rsv_slots)[2]; -}; - -/* platform_data for EDMA driver */ -struct edma_soc_info { - - /* how many dma resources of each type */ - unsigned n_channel; - unsigned n_region; - unsigned n_slot; - unsigned n_tc; - unsigned n_cc; - /* - * Default queue is expected to be a low-priority queue. - * This way, long transfers on the default queue started - * by the codec engine will not cause audio defects. - */ - enum dma_event_q default_queue; - - /* Resource reservation for other cores */ - struct edma_rsv_info *rsv; - - const s8 (*queue_tc_mapping)[2]; - const s8 (*queue_priority_mapping)[2]; -}; - -#endif diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h index 1656a02e3ed..366e975effa 100644 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -51,9 +51,9 @@ struct tnetv107x_device_info { extern struct platform_device tnetv107x_wdt_device; extern struct platform_device tnetv107x_serial_device; -extern void __init tnetv107x_init(void); -extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *); -extern void __init tnetv107x_irq_init(void); +extern void tnetv107x_init(void); +extern void tnetv107x_devices_init(struct tnetv107x_device_info *); +extern void tnetv107x_irq_init(void); void tnetv107x_restart(char mode, const char *cmd); #endif diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 36469d81395..dff7b2fd4e2 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -22,8 +22,7 @@ config MACH_CM_A510 config MACH_DOVE_DT bool "Marvell Dove Flattened Device Tree" - select MVEBU_CLK_CORE - select MVEBU_CLK_GATING + select DOVE_CLK select REGULATOR select REGULATOR_FIXED_VOLTAGE select USE_OF diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c index 0b142803b2e..f3755ac8114 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-dove/board-dt.c @@ -10,7 +10,6 @@ #include <linux/init.h> #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_data/usb-ehci-orion.h> @@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void) static void __init dove_of_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); dove_legacy_clk_init(); } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index e2b5da031f9..2a9443d04d9 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -9,7 +9,6 @@ */ #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/of.h> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index ff18fc2ea46..0ecd5af2054 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -14,9 +14,11 @@ menu "SAMSUNG EXYNOS SoCs Support" config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y + select GIC_NON_BANKED select HAVE_ARM_SCU if SMP select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL help Samsung EXYNOS4 SoCs based systems @@ -24,6 +26,7 @@ config ARCH_EXYNOS5 bool "SAMSUNG EXYNOS5" select HAVE_ARM_SCU if SMP select HAVE_SMP + select PINCTRL help Samsung EXYNOS5 (Cortex-A15) SoC based systems @@ -34,6 +37,7 @@ config CPU_EXYNOS4210 default y depends on ARCH_EXYNOS4 select ARM_CPU_SUSPEND if PM + select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS select S5P_PM if PM select S5P_SLEEP if PM @@ -45,6 +49,7 @@ config SOC_EXYNOS4212 bool "SAMSUNG EXYNOS4212" default y depends on ARCH_EXYNOS4 + select PINCTRL_EXYNOS select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -55,6 +60,7 @@ config SOC_EXYNOS4412 bool "SAMSUNG EXYNOS4412" default y depends on ARCH_EXYNOS4 + select PINCTRL_EXYNOS select SAMSUNG_DMADEV help Enable EXYNOS4412 SoC support @@ -63,6 +69,7 @@ config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y depends on ARCH_EXYNOS5 + select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM @@ -78,345 +85,25 @@ config SOC_EXYNOS5440 select ARCH_HAS_OPP select ARM_ARCH_TIMER select AUTO_ZRELADDR - select PINCTRL + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI select PINCTRL_EXYNOS5440 select PM_OPP help Enable EXYNOS5440 SoC support -config EXYNOS_ATAGS - bool "ATAGS based boot for EXYNOS (deprecated)" - depends on !ARCH_MULTIPLATFORM - depends on ATAGS - default y - help - The EXYNOS platform is moving towards being completely probed - through device tree. This enables support for board files using - the traditional ATAGS boot format. - Note that this option is not available for multiplatform builds. - -if EXYNOS_ATAGS - -config EXYNOS_DEV_DMA - bool - help - Compile in amba device definitions for DMA controller - -config EXYNOS4_DEV_AHCI - bool - help - Compile in platform device definitions for AHCI - -config EXYNOS4_SETUP_FIMD0 - bool - help - Common setup code for FIMD0. - -config EXYNOS4_DEV_USB_OHCI - bool - help - Compile in platform device definition for USB OHCI - -config EXYNOS4_SETUP_I2C1 - bool - help - Common setup code for i2c bus 1. - -config EXYNOS4_SETUP_I2C2 - bool - help - Common setup code for i2c bus 2. - -config EXYNOS4_SETUP_I2C3 - bool - help - Common setup code for i2c bus 3. - -config EXYNOS4_SETUP_I2C4 - bool - help - Common setup code for i2c bus 4. - -config EXYNOS4_SETUP_I2C5 - bool - help - Common setup code for i2c bus 5. - -config EXYNOS4_SETUP_I2C6 - bool - help - Common setup code for i2c bus 6. - -config EXYNOS4_SETUP_I2C7 - bool - help - Common setup code for i2c bus 7. - -config EXYNOS4_SETUP_KEYPAD - bool - help - Common setup code for keypad. - -config EXYNOS4_SETUP_SDHCI - bool - select EXYNOS4_SETUP_SDHCI_GPIO - help - Internal helper functions for EXYNOS4 based SDHCI systems. - -config EXYNOS4_SETUP_SDHCI_GPIO - bool - help - Common setup code for SDHCI gpio. - -config EXYNOS4_SETUP_FIMC - bool - help - Common setup code for the camera interfaces. - -config EXYNOS4_SETUP_USB_PHY - bool - help - Common setup code for USB PHY controller - -config EXYNOS_SETUP_SPI - bool - help - Common setup code for SPI GPIO configurations. - -# machine support - -if ARCH_EXYNOS4 - -comment "EXYNOS4210 Boards" - -config MACH_SMDKC210 - bool "SMDKC210" - select MACH_SMDKV310 - help - Machine support for Samsung SMDKC210 - -config MACH_SMDKV310 - bool "SMDKV310" - select CPU_EXYNOS4210 - select EXYNOS4_DEV_AHCI - select EXYNOS4_DEV_USB_OHCI - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C24XX_PWM - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC1 - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_I2C_HDMIPHY - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_TV - select S5P_DEV_USB_EHCI - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - help - Machine support for Samsung SMDKV310 - -config MACH_ARMLEX4210 - bool "ARMLEX4210" - select CPU_EXYNOS4210 - select EXYNOS4_DEV_AHCI - select EXYNOS4_SETUP_SDHCI - select EXYNOS_DEV_DMA - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_RTC - select S3C_DEV_WDT - help - Machine support for Samsung ARMLEX4210 based on EXYNOS4210 - -config MACH_UNIVERSAL_C210 - bool "Mobile UNIVERSAL_C210 Board" - select CLKSRC_MMIO - select CLKSRC_SAMSUNG_PWM - select CPU_EXYNOS4210 - select EXYNOS4_SETUP_FIMC - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C5 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C5 - select S3C_DEV_USB_HSOTG - select S5P_DEV_CSIS0 - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_I2C_HDMIPHY - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_ONENAND - select S5P_DEV_TV - select S5P_GPIO_INT - select S5P_SETUP_MIPIPHY - help - Machine support for Samsung Mobile Universal S5PC210 Reference - Board. - -config MACH_NURI - bool "Mobile NURI Board" - select CPU_EXYNOS4210 - select EXYNOS4_SETUP_FIMC - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C5 - select EXYNOS4_SETUP_I2C6 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C5 - select S3C_DEV_I2C6 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_CSIS0 - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_USB_EHCI - select S5P_GPIO_INT - select S5P_SETUP_MIPIPHY - select SAMSUNG_DEV_ADC - select SAMSUNG_DEV_PWM - help - Machine support for Samsung Mobile NURI Board. - -config MACH_ORIGEN - bool "ORIGEN" - select CPU_EXYNOS4210 - select EXYNOS4_DEV_USB_OHCI - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C24XX_PWM - select S3C_DEV_HSMMC - select S3C_DEV_HSMMC2 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_G2D - select S5P_DEV_I2C_HDMIPHY - select S5P_DEV_JPEG - select S5P_DEV_MFC - select S5P_DEV_TV - select S5P_DEV_USB_EHCI - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_PWM - help - Machine support for ORIGEN based on Samsung EXYNOS4210 - -comment "EXYNOS4212 Boards" - -config MACH_SMDK4212 - bool "SMDK4212" - select EXYNOS4_SETUP_FIMD0 - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C7 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - select EXYNOS4_SETUP_USB_PHY - select EXYNOS_DEV_DMA - select EXYNOS_DEV_SYSMMU - select S3C24XX_PWM - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C7 - select S3C_DEV_RTC - select S3C_DEV_USB_HSOTG - select S3C_DEV_WDT - select S5P_DEV_FIMC0 - select S5P_DEV_FIMC1 - select S5P_DEV_FIMC2 - select S5P_DEV_FIMC3 - select S5P_DEV_FIMD0 - select S5P_DEV_MFC - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - select SOC_EXYNOS4212 - help - Machine support for Samsung SMDK4212 - -comment "EXYNOS4412 Boards" - -config MACH_SMDK4412 - bool "SMDK4412" - select MACH_SMDK4212 - select SOC_EXYNOS4412 - help - Machine support for Samsung SMDK4412 -endif - -endif - comment "Flattened Device Tree based board for EXYNOS SoCs" config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" + default y depends on ARCH_EXYNOS4 select ARM_AMBA select CLKSRC_OF select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CPU_EXYNOS4210 select KEYBOARD_SAMSUNG if INPUT_KEYBOARD - select PINCTRL - select PINCTRL_EXYNOS select S5P_DEV_MFC - select USE_OF help Machine support for Samsung Exynos4 machine with device tree enabled. Select this if a fdt blob is available for the Exynos4 SoC based board. @@ -429,28 +116,11 @@ config MACH_EXYNOS5_DT depends on ARCH_EXYNOS5 select ARM_AMBA select CLKSRC_OF - select USE_OF + select USB_ARCH_HAS_XHCI help Machine support for Samsung EXYNOS5 machine with device tree enabled. Select this if a fdt blob is available for the EXYNOS5 SoC based board. -if ARCH_EXYNOS4 - -comment "Configuration for HSMMC 8-bit bus width" - -config EXYNOS4_SDHCI_CH0_8BIT - bool "Channel 0 with 8-bit bus" - help - Support HSMMC Channel 0 8-bit bus. - If selected, Channel 1 is disabled. - -config EXYNOS4_SDHCI_CH2_8BIT - bool "Channel 2 with 8-bit bus" - help - Support HSMMC Channel 2 8-bit bus. - If selected, Channel 3 is disabled. -endif - endmenu endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index b09b027178f..e970a7a4e27 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec) # machine support -obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o -obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o -obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o -obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o -obj-$(CONFIG_MACH_NURI) += mach-nuri.o -obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o - -obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o -obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o - obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o - -# device support - -obj-y += dev-uart.o -obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o -obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o -obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o -obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o - -obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o -obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o -obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o -obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o -obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o -obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index f7e504b7874..81e6320ca09 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -40,20 +40,9 @@ #include <mach/regs-irq.h> #include <mach/regs-pmu.h> -#include <mach/regs-gpio.h> -#include <mach/irqs.h> #include <plat/cpu.h> -#include <plat/devs.h> #include <plat/pm.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> -#include <plat/adc-core.h> -#include <plat/fb-core.h> -#include <plat/fimc-core.h> -#include <plat/iic-core.h> -#include <plat/tv-core.h> -#include <plat/spi-core.h> #include <plat/regs-serial.h> #include "common.h" @@ -69,31 +58,25 @@ static const char name_exynos5440[] = "EXYNOS5440"; static void exynos4_map_io(void); static void exynos5_map_io(void); static void exynos5440_map_io(void); -static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); static int exynos_init(void); -unsigned long xxti_f = 0, xusbxti_f = 0; - static struct cpu_table cpu_ids[] __initdata = { { .idcode = EXYNOS4210_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4210, }, { .idcode = EXYNOS4212_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4212, }, { .idcode = EXYNOS4412_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, - .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4412, }, { @@ -113,15 +96,6 @@ static struct cpu_table cpu_ids[] __initdata = { /* Initial IO mappings */ -static struct map_desc exynos_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_CHIPID, - .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static struct map_desc exynos4_iodesc[] __initdata = { { .virtual = (unsigned long)S3C_VA_SYS, @@ -304,13 +278,6 @@ static struct map_desc exynos5440_iodesc0[] __initdata = { }, }; -static struct samsung_pwm_variant exynos4_pwm_variant = { - .bits = 32, - .div_base = 0, - .has_tint_cstat = true, - .tclk_mask = 0, -}; - void exynos4_restart(char mode, const char *cmd) { __raw_writel(0x1, S5P_SWRESET); @@ -353,8 +320,7 @@ void __init exynos_init_late(void) exynos_pm_late_initcall(); } -#ifdef CONFIG_OF -int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, +static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, int depth, void *data) { struct map_desc iodesc; @@ -376,7 +342,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, iotable_init(&iodesc, 1); return 1; } -#endif /* * exynos_map_io @@ -384,19 +349,11 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, * register the standard cpu IO areas */ -void __init exynos_init_io(struct map_desc *mach_desc, int size) +void __init exynos_init_io(void) { debug_ll_io_init(); -#ifdef CONFIG_OF - if (initial_boot_params) - of_scan_flat_dt(exynos_fdt_map_chipid, NULL); - else -#endif - iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); - - if (mach_desc) - iotable_init(mach_desc, size); + of_scan_flat_dt(exynos_fdt_map_chipid, NULL); /* detect cpu id and rev. */ s5p_init_cpu(S5P_VA_CHIPID); @@ -417,34 +374,6 @@ static void __init exynos4_map_io(void) iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); if (soc_is_exynos4212() || soc_is_exynos4412()) iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); - - /* initialize device information early */ - exynos4_default_sdhci0(); - exynos4_default_sdhci1(); - exynos4_default_sdhci2(); - exynos4_default_sdhci3(); - - s3c_adc_setname("samsung-adc-v3"); - - s3c_fimc_setname(0, "exynos4-fimc"); - s3c_fimc_setname(1, "exynos4-fimc"); - s3c_fimc_setname(2, "exynos4-fimc"); - s3c_fimc_setname(3, "exynos4-fimc"); - - s3c_sdhci_setname(0, "exynos4-sdhci"); - s3c_sdhci_setname(1, "exynos4-sdhci"); - s3c_sdhci_setname(2, "exynos4-sdhci"); - s3c_sdhci_setname(3, "exynos4-sdhci"); - - /* The I2C bus controllers are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); - s3c_i2c1_setname("s3c2440-i2c"); - s3c_i2c2_setname("s3c2440-i2c"); - - s5p_fb_setname(0, "exynos4-fb"); - s5p_hdmi_setname("exynos4-hdmi"); - - s3c64xx_spi_setname("exynos4210-spi"); } static void __init exynos5_map_io(void) @@ -460,81 +389,10 @@ static void __init exynos5440_map_io(void) iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); } -void __init exynos_set_timer_source(u8 channels) -{ - exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; - exynos4_pwm_variant.output_mask &= ~channels; -} - void __init exynos_init_time(void) { - unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { - EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC, - EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC, - EXYNOS4_IRQ_TIMER4_VIC, - }; - - if (of_have_populated_dt()) { -#ifdef CONFIG_OF - of_clk_init(NULL); - clocksource_of_init(); -#endif - } else { - /* todo: remove after migrating legacy E4 platforms to dt */ -#ifdef CONFIG_ARCH_EXYNOS4 - exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1); - exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); -#endif -#ifdef CONFIG_CLKSRC_SAMSUNG_PWM - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) - samsung_pwm_clocksource_init(S3C_VA_TIMER, - timer_irqs, &exynos4_pwm_variant); - else -#endif - mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, - EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); - } -} - -static unsigned int max_combiner_nr(void) -{ - if (soc_is_exynos5250()) - return EXYNOS5_MAX_COMBINER_NR; - else if (soc_is_exynos4412()) - return EXYNOS4412_MAX_COMBINER_NR; - else if (soc_is_exynos4212()) - return EXYNOS4212_MAX_COMBINER_NR; - else - return EXYNOS4210_MAX_COMBINER_NR; -} - - -void __init exynos4_init_irq(void) -{ - unsigned int gic_bank_offset; - - gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - - if (!of_have_populated_dt()) - gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); -#ifdef CONFIG_OF - else - irqchip_init(); -#endif - - if (!of_have_populated_dt()) - combiner_init(S5P_VA_COMBINER_BASE, NULL, - max_combiner_nr(), COMBINER_IRQ(0, 0)); - - gic_arch_extn.irq_set_wake = s3c_irq_wake; -} - -void __init exynos5_init_irq(void) -{ -#ifdef CONFIG_OF - irqchip_init(); -#endif - gic_arch_extn.irq_set_wake = s3c_irq_wake; + of_clk_init(NULL); + clocksource_of_init(); } struct bus_type exynos_subsys = { @@ -552,59 +410,19 @@ static int __init exynos_core_init(void) } core_initcall(exynos_core_init); -#ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { int ret; - if (soc_is_exynos5250() || soc_is_exynos5440()) - return 0; - ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); - if (!ret) { - l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); - clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); - return 0; - } - - if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { - l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; - /* TAG, Data Latency Control: 2 cycles */ - l2x0_saved_regs.tag_latency = 0x110; - - if (soc_is_exynos4212() || soc_is_exynos4412()) - l2x0_saved_regs.data_latency = 0x120; - else - l2x0_saved_regs.data_latency = 0x110; - - l2x0_saved_regs.prefetch_ctrl = 0x30000007; - l2x0_saved_regs.pwr_ctrl = - (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); - - l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); + if (ret) + return ret; - __raw_writel(l2x0_saved_regs.tag_latency, - S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); - __raw_writel(l2x0_saved_regs.data_latency, - S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - - /* L2X0 Prefetch Control */ - __raw_writel(l2x0_saved_regs.prefetch_ctrl, - S5P_VA_L2CC + L2X0_PREFETCH_CTRL); - - /* L2X0 Power Control */ - __raw_writel(l2x0_saved_regs.pwr_ctrl, - S5P_VA_L2CC + L2X0_POWER_CTRL); - - clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); - clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); - } - - l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); return 0; } early_initcall(exynos4_l2x0_cache_init); -#endif static int __init exynos_init(void) { @@ -612,350 +430,3 @@ static int __init exynos_init(void) return device_register(&exynos4_dev); } - -/* uart registration process */ - -static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - struct s3c2410_uartcfg *tcfg = cfg; - u32 ucnt; - - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) - tcfg->has_fracval = 1; - - s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no); -} - -static void __iomem *exynos_eint_base; - -static DEFINE_SPINLOCK(eint_lock); - -static unsigned int eint0_15_data[16]; - -static inline int exynos4_irq_to_gpio(unsigned int irq) -{ - if (irq < IRQ_EINT(0)) - return -EINVAL; - - irq -= IRQ_EINT(0); - if (irq < 8) - return EXYNOS4_GPX0(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS4_GPX1(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS4_GPX2(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS4_GPX3(irq); - - return -EINVAL; -} - -static inline int exynos5_irq_to_gpio(unsigned int irq) -{ - if (irq < IRQ_EINT(0)) - return -EINVAL; - - irq -= IRQ_EINT(0); - if (irq < 8) - return EXYNOS5_GPX0(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS5_GPX1(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS5_GPX2(irq); - - irq -= 8; - if (irq < 8) - return EXYNOS5_GPX3(irq); - - return -EINVAL; -} - -static unsigned int exynos4_eint0_15_src_int[16] = { - EXYNOS4_IRQ_EINT0, - EXYNOS4_IRQ_EINT1, - EXYNOS4_IRQ_EINT2, - EXYNOS4_IRQ_EINT3, - EXYNOS4_IRQ_EINT4, - EXYNOS4_IRQ_EINT5, - EXYNOS4_IRQ_EINT6, - EXYNOS4_IRQ_EINT7, - EXYNOS4_IRQ_EINT8, - EXYNOS4_IRQ_EINT9, - EXYNOS4_IRQ_EINT10, - EXYNOS4_IRQ_EINT11, - EXYNOS4_IRQ_EINT12, - EXYNOS4_IRQ_EINT13, - EXYNOS4_IRQ_EINT14, - EXYNOS4_IRQ_EINT15, -}; - -static unsigned int exynos5_eint0_15_src_int[16] = { - EXYNOS5_IRQ_EINT0, - EXYNOS5_IRQ_EINT1, - EXYNOS5_IRQ_EINT2, - EXYNOS5_IRQ_EINT3, - EXYNOS5_IRQ_EINT4, - EXYNOS5_IRQ_EINT5, - EXYNOS5_IRQ_EINT6, - EXYNOS5_IRQ_EINT7, - EXYNOS5_IRQ_EINT8, - EXYNOS5_IRQ_EINT9, - EXYNOS5_IRQ_EINT10, - EXYNOS5_IRQ_EINT11, - EXYNOS5_IRQ_EINT12, - EXYNOS5_IRQ_EINT13, - EXYNOS5_IRQ_EINT14, - EXYNOS5_IRQ_EINT15, -}; -static inline void exynos_irq_eint_mask(struct irq_data *data) -{ - u32 mask; - - spin_lock(&eint_lock); - mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); - mask |= EINT_OFFSET_BIT(data->irq); - __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); - spin_unlock(&eint_lock); -} - -static void exynos_irq_eint_unmask(struct irq_data *data) -{ - u32 mask; - - spin_lock(&eint_lock); - mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); - mask &= ~(EINT_OFFSET_BIT(data->irq)); - __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); - spin_unlock(&eint_lock); -} - -static inline void exynos_irq_eint_ack(struct irq_data *data) -{ - __raw_writel(EINT_OFFSET_BIT(data->irq), - EINT_PEND(exynos_eint_base, data->irq)); -} - -static void exynos_irq_eint_maskack(struct irq_data *data) -{ - exynos_irq_eint_mask(data); - exynos_irq_eint_ack(data); -} - -static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type) -{ - int offs = EINT_OFFSET(data->irq); - int shift; - u32 ctrl, mask; - u32 newvalue = 0; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - newvalue = S5P_IRQ_TYPE_EDGE_RISING; - break; - - case IRQ_TYPE_EDGE_FALLING: - newvalue = S5P_IRQ_TYPE_EDGE_FALLING; - break; - - case IRQ_TYPE_EDGE_BOTH: - newvalue = S5P_IRQ_TYPE_EDGE_BOTH; - break; - - case IRQ_TYPE_LEVEL_LOW: - newvalue = S5P_IRQ_TYPE_LEVEL_LOW; - break; - - case IRQ_TYPE_LEVEL_HIGH: - newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; - break; - - default: - printk(KERN_ERR "No such irq type %d", type); - return -EINVAL; - } - - shift = (offs & 0x7) * 4; - mask = 0x7 << shift; - - spin_lock(&eint_lock); - ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq)); - ctrl &= ~mask; - ctrl |= newvalue << shift; - __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq)); - spin_unlock(&eint_lock); - - if (soc_is_exynos5250()) - s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf)); - else - s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf)); - - return 0; -} - -static struct irq_chip exynos_irq_eint = { - .name = "exynos-eint", - .irq_mask = exynos_irq_eint_mask, - .irq_unmask = exynos_irq_eint_unmask, - .irq_mask_ack = exynos_irq_eint_maskack, - .irq_ack = exynos_irq_eint_ack, - .irq_set_type = exynos_irq_eint_set_type, -#ifdef CONFIG_PM - .irq_set_wake = s3c_irqext_wake, -#endif -}; - -/* - * exynos4_irq_demux_eint - * - * This function demuxes the IRQ from from EINTs 16 to 31. - * It is designed to be inlined into the specific handler - * s5p_irq_demux_eintX_Y. - * - * Each EINT pend/mask registers handle eight of them. - */ -static inline void exynos_irq_demux_eint(unsigned int start) -{ - unsigned int irq; - - u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start)); - u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start)); - - status &= ~mask; - status &= 0xff; - - while (status) { - irq = fls(status) - 1; - generic_handle_irq(irq + start); - status &= ~(1 << irq); - } -} - -static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) -{ - struct irq_chip *chip = irq_get_chip(irq); - chained_irq_enter(chip, desc); - exynos_irq_demux_eint(IRQ_EINT(16)); - exynos_irq_demux_eint(IRQ_EINT(24)); - chained_irq_exit(chip, desc); -} - -static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) -{ - u32 *irq_data = irq_get_handler_data(irq); - struct irq_chip *chip = irq_get_chip(irq); - - chained_irq_enter(chip, desc); - generic_handle_irq(*irq_data); - chained_irq_exit(chip, desc); -} - -static int __init exynos_init_irq_eint(void) -{ - int irq; - -#ifdef CONFIG_PINCTRL_SAMSUNG - /* - * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf - * functionality along with support for external gpio and wakeup - * interrupts. If the samsung pinctrl driver is enabled and includes - * the wakeup interrupt support, then the setting up external wakeup - * interrupts here can be skipped. This check here is temporary to - * allow exynos4 platforms that do not use Samsung pinctrl driver to - * co-exist with platforms that do. When all of the Samsung Exynos4 - * platforms switch over to using the pinctrl driver, the wakeup - * interrupt support code here can be completely removed. - */ - static const struct of_device_id exynos_pinctrl_ids[] = { - { .compatible = "samsung,exynos4210-pinctrl", }, - { .compatible = "samsung,exynos4x12-pinctrl", }, - { .compatible = "samsung,exynos5250-pinctrl", }, - }; - struct device_node *pctrl_np, *wkup_np; - const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; - - for_each_matching_node(pctrl_np, exynos_pinctrl_ids) { - if (of_device_is_available(pctrl_np)) { - wkup_np = of_find_compatible_node(pctrl_np, NULL, - wkup_compat); - if (wkup_np) - return -ENODEV; - } - } -#endif - if (soc_is_exynos5440()) - return 0; - - if (soc_is_exynos5250()) - exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); - else - exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K); - - if (exynos_eint_base == NULL) { - pr_err("unable to ioremap for EINT base address\n"); - return -ENOMEM; - } - - for (irq = 0 ; irq <= 31 ; irq++) { - irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint, - handle_level_irq); - set_irq_flags(IRQ_EINT(irq), IRQF_VALID); - } - - irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31); - - for (irq = 0 ; irq <= 15 ; irq++) { - eint0_15_data[irq] = IRQ_EINT(irq); - - if (soc_is_exynos5250()) { - irq_set_handler_data(exynos5_eint0_15_src_int[irq], - &eint0_15_data[irq]); - irq_set_chained_handler(exynos5_eint0_15_src_int[irq], - exynos_irq_eint0_15); - } else { - irq_set_handler_data(exynos4_eint0_15_src_int[irq], - &eint0_15_data[irq]); - irq_set_chained_handler(exynos4_eint0_15_src_int[irq], - exynos_irq_eint0_15); - } - } - - return 0; -} -arch_initcall(exynos_init_irq_eint); - -static struct resource exynos4_pmu_resource[] = { - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU), - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1), -#if defined(CONFIG_SOC_EXYNOS4412) - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2), - DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3), -#endif -}; - -static struct platform_device exynos4_device_pmu = { - .name = "arm-pmu", - .num_resources = ARRAY_SIZE(exynos4_pmu_resource), - .resource = exynos4_pmu_resource, -}; - -static int __init exynos_armpmu_init(void) -{ - if (!of_have_populated_dt()) { - if (soc_is_exynos4210() || soc_is_exynos4212()) - exynos4_device_pmu.num_resources = 2; - platform_device_register(&exynos4_device_pmu); - } - - return 0; -} -arch_initcall(exynos_armpmu_init); diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 11fc1e29819..38d45fd23be 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -19,9 +19,7 @@ void exynos_init_time(void); extern unsigned long xxti_f, xusbxti_f; struct map_desc; -void exynos_init_io(struct map_desc *mach_desc, int size); -void exynos4_init_irq(void); -void exynos5_init_irq(void); +void exynos_init_io(void); void exynos4_restart(char mode, const char *cmd); void exynos5_restart(char mode, const char *cmd); void exynos_init_late(void); diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c deleted file mode 100644 index ce1aad3eeeb..00000000000 --- a/arch/arm/mach-exynos/dev-ahci.c +++ /dev/null @@ -1,255 +0,0 @@ -/* linux/arch/arm/mach-exynos4/dev-ahci.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - AHCI support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/ahci_platform.h> - -#include <plat/cpu.h> - -#include <mach/irqs.h> -#include <mach/map.h> -#include <mach/regs-pmu.h> - -/* PHY Control Register */ -#define SATA_CTRL0 0x0 -/* PHY Link Control Register */ -#define SATA_CTRL1 0x4 -/* PHY Status Register */ -#define SATA_PHY_STATUS 0x8 - -#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27) -#define SATA_CTRL0_SPEED_MODE (1 << 26) -#define SATA_CTRL0_M_PHY_CAL (1 << 19) -#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10) -#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9) -#define SATA_CTRL0_PHY_POR_N (1 << 8) - -#define SATA_CTRL1_RST_PMALIVE_N (1 << 8) -#define SATA_CTRL1_RST_RXOOB_N (1 << 7) -#define SATA_CTRL1_RST_RX_N (1 << 6) -#define SATA_CTRL1_RST_TX_N (1 << 5) - -#define SATA_PHY_STATUS_CMU_OK (1 << 18) -#define SATA_PHY_STATUS_LANE_OK (1 << 16) - -#define LANE0 0x200 -#define COM_LANE 0xA00 - -#define HOST_PORTS_IMPL 0xC -#define SCLK_SATA_FREQ (67 * MHZ) - -static void __iomem *phy_base, *phy_ctrl; - -struct phy_reg { - u8 reg; - u8 val; -}; - -/* SATA PHY setup */ -static const struct phy_reg exynos4_sataphy_cmu[] = { - { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 }, - { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 }, - { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 }, - { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 }, - { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 }, - { 0x6b, 0xc8 }, { 0x6c, 0x06 }, -}; - -static const struct phy_reg exynos4_sataphy_lane[] = { - { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 }, - { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 }, - { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e }, - { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 }, - { 0x51, 0x0f }, -}; - -static const struct phy_reg exynos4_sataphy_comlane[] = { - { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d }, - { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 }, - { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 }, - { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 }, - { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 }, - { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 }, - { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 }, - { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d }, - { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 }, - { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 }, - { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 }, - { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff }, - { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 }, - { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 }, -}; - -static int wait_for_phy_ready(void __iomem *reg, unsigned long bit) -{ - unsigned long timeout; - - /* wait for maximum of 3 sec */ - timeout = jiffies + msecs_to_jiffies(3000); - while (!(__raw_readl(reg) & bit)) { - if (time_after(jiffies, timeout)) - return -1; - cpu_relax(); - } - return 0; -} - -static int ahci_phy_init(void __iomem *mmio) -{ - int i, ctrl0; - - for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++) - __raw_writeb(exynos4_sataphy_cmu[i].val, - phy_base + (exynos4_sataphy_cmu[i].reg * 4)); - - for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++) - __raw_writeb(exynos4_sataphy_lane[i].val, - phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4); - - for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++) - __raw_writeb(exynos4_sataphy_comlane[i].val, - phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4); - - __raw_writeb(0x07, phy_base); - - ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); - ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N; - __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); - - if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, - SATA_PHY_STATUS_CMU_OK) < 0) { - printk(KERN_ERR "PHY CMU not ready\n"); - return -EBUSY; - } - - __raw_writeb(0x03, phy_base + (COM_LANE * 4)); - - ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); - ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N; - __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); - - if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, - SATA_PHY_STATUS_LANE_OK) < 0) { - printk(KERN_ERR "PHY LANE not ready\n"); - return -EBUSY; - } - - ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); - ctrl0 |= SATA_CTRL0_M_PHY_CAL; - __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); - - return 0; -} - -static int exynos4_ahci_init(struct device *dev, void __iomem *mmio) -{ - struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata; - int val, ret; - - phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K); - if (!phy_base) { - dev_err(dev, "failed to allocate memory for SATA PHY\n"); - return -ENOMEM; - } - - phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16); - if (!phy_ctrl) { - dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n"); - ret = -ENOMEM; - goto err1; - } - - clk_sata = clk_get(dev, "sata"); - if (IS_ERR(clk_sata)) { - dev_err(dev, "failed to get sata clock\n"); - ret = PTR_ERR(clk_sata); - clk_sata = NULL; - goto err2; - - } - clk_enable(clk_sata); - - clk_sataphy = clk_get(dev, "sataphy"); - if (IS_ERR(clk_sataphy)) { - dev_err(dev, "failed to get sataphy clock\n"); - ret = PTR_ERR(clk_sataphy); - clk_sataphy = NULL; - goto err3; - } - clk_enable(clk_sataphy); - - clk_sclk_sata = clk_get(dev, "sclk_sata"); - if (IS_ERR(clk_sclk_sata)) { - dev_err(dev, "failed to get sclk_sata\n"); - ret = PTR_ERR(clk_sclk_sata); - clk_sclk_sata = NULL; - goto err4; - } - clk_enable(clk_sclk_sata); - clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ); - - __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL); - - /* Enable PHY link control */ - val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N | - SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N; - __raw_writel(val, phy_ctrl + SATA_CTRL1); - - /* Set communication speed as 3Gbps and enable PHY power */ - val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE | - SATA_CTRL0_PHY_POR_N; - __raw_writel(val, phy_ctrl + SATA_CTRL0); - - /* Port0 is available */ - __raw_writel(0x1, mmio + HOST_PORTS_IMPL); - - return ahci_phy_init(mmio); - -err4: - clk_disable(clk_sataphy); - clk_put(clk_sataphy); -err3: - clk_disable(clk_sata); - clk_put(clk_sata); -err2: - iounmap(phy_ctrl); -err1: - iounmap(phy_base); - - return ret; -} - -static struct ahci_platform_data exynos4_ahci_pdata = { - .init = exynos4_ahci_init, -}; - -static struct resource exynos4_ahci_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K), - [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA), -}; - -static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_ahci = { - .name = "ahci", - .id = -1, - .resource = exynos4_ahci_resource, - .num_resources = ARRAY_SIZE(exynos4_ahci_resource), - .dev = { - .platform_data = &exynos4_ahci_pdata, - .dma_mask = &exynos4_ahci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c deleted file mode 100644 index c662c89794b..00000000000 --- a/arch/arm/mach-exynos/dev-audio.c +++ /dev/null @@ -1,254 +0,0 @@ -/* linux/arch/arm/mach-exynos4/dev-audio.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2010 Samsung Electronics Co. Ltd - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> -#include <linux/platform_data/asoc-s3c.h> - -#include <plat/gpio-cfg.h> - -#include <mach/map.h> -#include <mach/dma.h> -#include <mach/irqs.h> - -#define EXYNOS4_AUDSS_INT_MEM (0x03000000) - -static int exynos4_cfg_i2s(struct platform_device *pdev) -{ - /* configure GPIO for i2s port */ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2)); - break; - case 1: - s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2)); - break; - case 2: - s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4)); - break; - default: - printk(KERN_ERR "Invalid Device %d\n", pdev->id); - return -EINVAL; - } - - return 0; -} - -static struct s3c_audio_pdata i2sv5_pdata = { - .cfg_gpio = exynos4_cfg_i2s, - .type = { - .i2s = { - .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI - | QUIRK_NEED_RSTCLR, - .idma_addr = EXYNOS4_AUDSS_INT_MEM, - }, - }, -}; - -static struct resource exynos4_i2s0_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), - [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), - [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), -}; - -struct platform_device exynos4_device_i2s0 = { - .name = "samsung-i2s", - .id = 0, - .num_resources = ARRAY_SIZE(exynos4_i2s0_resource), - .resource = exynos4_i2s0_resource, - .dev = { - .platform_data = &i2sv5_pdata, - }, -}; - -static struct s3c_audio_pdata i2sv3_pdata = { - .cfg_gpio = exynos4_cfg_i2s, - .type = { - .i2s = { - .quirks = QUIRK_NO_MUXPSR, - }, - }, -}; - -static struct resource exynos4_i2s1_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), - [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), -}; - -struct platform_device exynos4_device_i2s1 = { - .name = "samsung-i2s", - .id = 1, - .num_resources = ARRAY_SIZE(exynos4_i2s1_resource), - .resource = exynos4_i2s1_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; - -static struct resource exynos4_i2s2_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), - [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), -}; - -struct platform_device exynos4_device_i2s2 = { - .name = "samsung-i2s", - .id = 2, - .num_resources = ARRAY_SIZE(exynos4_i2s2_resource), - .resource = exynos4_i2s2_resource, - .dev = { - .platform_data = &i2sv3_pdata, - }, -}; - -/* PCM Controller platform_devices */ - -static int exynos4_pcm_cfg_gpio(struct platform_device *pdev) -{ - switch (pdev->id) { - case 0: - s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3)); - break; - case 1: - s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3)); - break; - case 2: - s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3)); - break; - default: - printk(KERN_DEBUG "Invalid PCM Controller number!"); - return -EINVAL; - } - - return 0; -} - -static struct s3c_audio_pdata s3c_pcm_pdata = { - .cfg_gpio = exynos4_pcm_cfg_gpio, -}; - -static struct resource exynos4_pcm0_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), - [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), -}; - -struct platform_device exynos4_device_pcm0 = { - .name = "samsung-pcm", - .id = 0, - .num_resources = ARRAY_SIZE(exynos4_pcm0_resource), - .resource = exynos4_pcm0_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -static struct resource exynos4_pcm1_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), - [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), -}; - -struct platform_device exynos4_device_pcm1 = { - .name = "samsung-pcm", - .id = 1, - .num_resources = ARRAY_SIZE(exynos4_pcm1_resource), - .resource = exynos4_pcm1_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -static struct resource exynos4_pcm2_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_PCM2_TX), - [2] = DEFINE_RES_DMA(DMACH_PCM2_RX), -}; - -struct platform_device exynos4_device_pcm2 = { - .name = "samsung-pcm", - .id = 2, - .num_resources = ARRAY_SIZE(exynos4_pcm2_resource), - .resource = exynos4_pcm2_resource, - .dev = { - .platform_data = &s3c_pcm_pdata, - }, -}; - -/* AC97 Controller platform devices */ - -static int exynos4_ac97_cfg_gpio(struct platform_device *pdev) -{ - return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4)); -} - -static struct resource exynos4_ac97_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), - [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), - [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), - [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97), -}; - -static struct s3c_audio_pdata s3c_ac97_pdata = { - .cfg_gpio = exynos4_ac97_cfg_gpio, -}; - -static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_ac97 = { - .name = "samsung-ac97", - .id = -1, - .num_resources = ARRAY_SIZE(exynos4_ac97_resource), - .resource = exynos4_ac97_resource, - .dev = { - .platform_data = &s3c_ac97_pdata, - .dma_mask = &exynos4_ac97_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* S/PDIF Controller platform_device */ - -static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) -{ - s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4)); - - return 0; -} - -static struct resource exynos4_spdif_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256), - [1] = DEFINE_RES_DMA(DMACH_SPDIF), -}; - -static struct s3c_audio_pdata samsung_spdif_pdata = { - .cfg_gpio = exynos4_spdif_cfg_gpio, -}; - -static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_spdif = { - .name = "samsung-spdif", - .id = -1, - .num_resources = ARRAY_SIZE(exynos4_spdif_resource), - .resource = exynos4_spdif_resource, - .dev = { - .platform_data = &samsung_spdif_pdata, - .dma_mask = &exynos4_spdif_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c deleted file mode 100644 index d5bc129e6bb..00000000000 --- a/arch/arm/mach-exynos/dev-ohci.c +++ /dev/null @@ -1,52 +0,0 @@ -/* linux/arch/arm/mach-exynos/dev-ohci.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - OHCI support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/platform_data/usb-ohci-exynos.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> -#include <plat/usb-phy.h> - -static struct resource exynos4_ohci_resource[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256), - [1] = DEFINE_RES_IRQ(IRQ_USB_HOST), -}; - -static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32); - -struct platform_device exynos4_device_ohci = { - .name = "exynos-ohci", - .id = -1, - .num_resources = ARRAY_SIZE(exynos4_ohci_resource), - .resource = exynos4_ohci_resource, - .dev = { - .dma_mask = &exynos4_ohci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; - -void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd) -{ - struct exynos4_ohci_platdata *npd; - - npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata), - &exynos4_device_ohci); - - if (!npd->phy_init) - npd->phy_init = s5p_usb_phy_init; - if (!npd->phy_exit) - npd->phy_exit = s5p_usb_phy_exit; -} diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c deleted file mode 100644 index c48aff02c78..00000000000 --- a/arch/arm/mach-exynos/dev-uart.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Base EXYNOS UART resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/ioport.h> -#include <linux/platform_device.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/map.h> -#include <mach/irqs.h> - -#include <plat/devs.h> - -#define EXYNOS_UART_RESOURCE(_series, _nr) \ -static struct resource exynos##_series##_uart##_nr##_resource[] = { \ - [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \ - [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \ -}; - -EXYNOS_UART_RESOURCE(4, 0) -EXYNOS_UART_RESOURCE(4, 1) -EXYNOS_UART_RESOURCE(4, 2) -EXYNOS_UART_RESOURCE(4, 3) - -struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = { - [0] = { - .resources = exynos4_uart0_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart0_resource), - }, - [1] = { - .resources = exynos4_uart1_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart1_resource), - }, - [2] = { - .resources = exynos4_uart2_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart2_resource), - }, - [3] = { - .resources = exynos4_uart3_resource, - .nr_resources = ARRAY_SIZE(exynos4_uart3_resource), - }, -}; diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c deleted file mode 100644 index 87e07d6fc61..00000000000 --- a/arch/arm/mach-exynos/dma.c +++ /dev/null @@ -1,322 +0,0 @@ -/* linux/arch/arm/mach-exynos4/dma.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (C) 2010 Samsung Electronics Co. Ltd. - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/dma-mapping.h> -#include <linux/amba/bus.h> -#include <linux/amba/pl330.h> -#include <linux/of.h> - -#include <asm/irq.h> -#include <plat/devs.h> -#include <plat/irqs.h> -#include <plat/cpu.h> - -#include <mach/map.h> -#include <mach/irqs.h> -#include <mach/dma.h> - -static u8 exynos4210_pdma0_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM2_RX, - DMACH_PCM2_TX, - DMACH_MSM_REQ0, - DMACH_MSM_REQ2, - DMACH_SPI0_RX, - DMACH_SPI0_TX, - DMACH_SPI2_RX, - DMACH_SPI2_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S2_RX, - DMACH_I2S2_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART2_RX, - DMACH_UART2_TX, - DMACH_UART4_RX, - DMACH_UART4_TX, - DMACH_SLIMBUS0_RX, - DMACH_SLIMBUS0_TX, - DMACH_SLIMBUS2_RX, - DMACH_SLIMBUS2_TX, - DMACH_SLIMBUS4_RX, - DMACH_SLIMBUS4_TX, - DMACH_AC97_MICIN, - DMACH_AC97_PCMIN, - DMACH_AC97_PCMOUT, -}; - -static u8 exynos4212_pdma0_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM2_RX, - DMACH_PCM2_TX, - DMACH_MIPI_HSI0, - DMACH_MIPI_HSI1, - DMACH_SPI0_RX, - DMACH_SPI0_TX, - DMACH_SPI2_RX, - DMACH_SPI2_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S2_RX, - DMACH_I2S2_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART2_RX, - DMACH_UART2_TX, - DMACH_UART4_RX, - DMACH_UART4_TX, - DMACH_SLIMBUS0_RX, - DMACH_SLIMBUS0_TX, - DMACH_SLIMBUS2_RX, - DMACH_SLIMBUS2_TX, - DMACH_SLIMBUS4_RX, - DMACH_SLIMBUS4_TX, - DMACH_AC97_MICIN, - DMACH_AC97_PCMIN, - DMACH_AC97_PCMOUT, - DMACH_MIPI_HSI4, - DMACH_MIPI_HSI5, -}; - -static u8 exynos5250_pdma0_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM2_RX, - DMACH_PCM2_TX, - DMACH_SPI0_RX, - DMACH_SPI0_TX, - DMACH_SPI2_RX, - DMACH_SPI2_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S2_RX, - DMACH_I2S2_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART2_RX, - DMACH_UART2_TX, - DMACH_UART4_RX, - DMACH_UART4_TX, - DMACH_SLIMBUS0_RX, - DMACH_SLIMBUS0_TX, - DMACH_SLIMBUS2_RX, - DMACH_SLIMBUS2_TX, - DMACH_SLIMBUS4_RX, - DMACH_SLIMBUS4_TX, - DMACH_AC97_MICIN, - DMACH_AC97_PCMIN, - DMACH_AC97_PCMOUT, - DMACH_MIPI_HSI0, - DMACH_MIPI_HSI2, - DMACH_MIPI_HSI4, - DMACH_MIPI_HSI6, -}; - -static struct dma_pl330_platdata exynos_pdma0_pdata; - -static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330, - EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata); - -static u8 exynos4210_pdma1_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM1_RX, - DMACH_PCM1_TX, - DMACH_MSM_REQ1, - DMACH_MSM_REQ3, - DMACH_SPI1_RX, - DMACH_SPI1_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S1_RX, - DMACH_I2S1_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART1_RX, - DMACH_UART1_TX, - DMACH_UART3_RX, - DMACH_UART3_TX, - DMACH_SLIMBUS1_RX, - DMACH_SLIMBUS1_TX, - DMACH_SLIMBUS3_RX, - DMACH_SLIMBUS3_TX, - DMACH_SLIMBUS5_RX, - DMACH_SLIMBUS5_TX, -}; - -static u8 exynos4212_pdma1_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM1_RX, - DMACH_PCM1_TX, - DMACH_MIPI_HSI2, - DMACH_MIPI_HSI3, - DMACH_SPI1_RX, - DMACH_SPI1_TX, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S1_RX, - DMACH_I2S1_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART1_RX, - DMACH_UART1_TX, - DMACH_UART3_RX, - DMACH_UART3_TX, - DMACH_SLIMBUS1_RX, - DMACH_SLIMBUS1_TX, - DMACH_SLIMBUS3_RX, - DMACH_SLIMBUS3_TX, - DMACH_SLIMBUS5_RX, - DMACH_SLIMBUS5_TX, - DMACH_SLIMBUS0AUX_RX, - DMACH_SLIMBUS0AUX_TX, - DMACH_SPDIF, - DMACH_MIPI_HSI6, - DMACH_MIPI_HSI7, -}; - -static u8 exynos5250_pdma1_peri[] = { - DMACH_PCM0_RX, - DMACH_PCM0_TX, - DMACH_PCM1_RX, - DMACH_PCM1_TX, - DMACH_SPI1_RX, - DMACH_SPI1_TX, - DMACH_PWM, - DMACH_SPDIF, - DMACH_I2S0S_TX, - DMACH_I2S0_RX, - DMACH_I2S0_TX, - DMACH_I2S1_RX, - DMACH_I2S1_TX, - DMACH_UART0_RX, - DMACH_UART0_TX, - DMACH_UART1_RX, - DMACH_UART1_TX, - DMACH_UART3_RX, - DMACH_UART3_TX, - DMACH_SLIMBUS1_RX, - DMACH_SLIMBUS1_TX, - DMACH_SLIMBUS3_RX, - DMACH_SLIMBUS3_TX, - DMACH_SLIMBUS5_RX, - DMACH_SLIMBUS5_TX, - DMACH_SLIMBUS0AUX_RX, - DMACH_SLIMBUS0AUX_TX, - DMACH_DISP1, - DMACH_MIPI_HSI1, - DMACH_MIPI_HSI3, - DMACH_MIPI_HSI5, - DMACH_MIPI_HSI7, -}; - -static struct dma_pl330_platdata exynos_pdma1_pdata; - -static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330, - EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata); - -static u8 mdma_peri[] = { - DMACH_MTOM_0, - DMACH_MTOM_1, - DMACH_MTOM_2, - DMACH_MTOM_3, - DMACH_MTOM_4, - DMACH_MTOM_5, - DMACH_MTOM_6, - DMACH_MTOM_7, -}; - -static struct dma_pl330_platdata exynos_mdma1_pdata = { - .nr_valid_peri = ARRAY_SIZE(mdma_peri), - .peri_id = mdma_peri, -}; - -static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330, - EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata); - -static int __init exynos_dma_init(void) -{ - if (of_have_populated_dt()) - return 0; - - if (soc_is_exynos4210()) { - exynos_pdma0_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4210_pdma0_peri); - exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri; - exynos_pdma1_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4210_pdma1_peri); - exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri; - - if (samsung_rev() == EXYNOS4210_REV_0) - exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1; - } else if (soc_is_exynos4212() || soc_is_exynos4412()) { - exynos_pdma0_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4212_pdma0_peri); - exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri; - exynos_pdma1_pdata.nr_valid_peri = - ARRAY_SIZE(exynos4212_pdma1_peri); - exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri; - } else if (soc_is_exynos5250()) { - exynos_pdma0_pdata.nr_valid_peri = - ARRAY_SIZE(exynos5250_pdma0_peri); - exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri; - exynos_pdma1_pdata.nr_valid_peri = - ARRAY_SIZE(exynos5250_pdma1_peri); - exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri; - - exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0; - exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K; - exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0; - exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1; - exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K; - exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1; - exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1; - exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K; - exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1; - } - - dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask); - dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask); - dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask); - amba_device_register(&exynos_pdma0_device, &iomem_resource); - - dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask); - dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask); - dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask); - amba_device_register(&exynos_pdma1_device, &iomem_resource); - - dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask); - amba_device_register(&exynos_mdma1_device, &iomem_resource); - - return 0; -} -arch_initcall(exynos_dma_init); diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index ed11f100d47..932129ef26c 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = { void __init exynos_firmware_init(void) { - if (of_have_populated_dt()) { - struct device_node *nd; - const __be32 *addr; + struct device_node *nd; + const __be32 *addr; - nd = of_find_compatible_node(NULL, NULL, - "samsung,secure-firmware"); - if (!nd) - return; + nd = of_find_compatible_node(NULL, NULL, + "samsung,secure-firmware"); + if (!nd) + return; - addr = of_get_address(nd, 0, NULL, NULL); - if (!addr) { - pr_err("%s: No address specified.\n", __func__); - return; - } + addr = of_get_address(nd, 0, NULL, NULL); + if (!addr) { + pr_err("%s: No address specified.\n", __func__); + return; } pr_info("Running under secure firmware.\n"); diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h deleted file mode 100644 index eb24f1eb8e3..00000000000 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - GPIO lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H __FILE__ - -/* Macro for EXYNOS GPIO numbering */ - -#define EXYNOS_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) - -/* EXYNOS4 GPIO bank sizes */ - -#define EXYNOS4_GPIO_A0_NR (8) -#define EXYNOS4_GPIO_A1_NR (6) -#define EXYNOS4_GPIO_B_NR (8) -#define EXYNOS4_GPIO_C0_NR (5) -#define EXYNOS4_GPIO_C1_NR (5) -#define EXYNOS4_GPIO_D0_NR (4) -#define EXYNOS4_GPIO_D1_NR (4) -#define EXYNOS4_GPIO_E0_NR (5) -#define EXYNOS4_GPIO_E1_NR (8) -#define EXYNOS4_GPIO_E2_NR (6) -#define EXYNOS4_GPIO_E3_NR (8) -#define EXYNOS4_GPIO_E4_NR (8) -#define EXYNOS4_GPIO_F0_NR (8) -#define EXYNOS4_GPIO_F1_NR (8) -#define EXYNOS4_GPIO_F2_NR (8) -#define EXYNOS4_GPIO_F3_NR (6) -#define EXYNOS4_GPIO_J0_NR (8) -#define EXYNOS4_GPIO_J1_NR (5) -#define EXYNOS4_GPIO_K0_NR (7) -#define EXYNOS4_GPIO_K1_NR (7) -#define EXYNOS4_GPIO_K2_NR (7) -#define EXYNOS4_GPIO_K3_NR (7) -#define EXYNOS4_GPIO_L0_NR (8) -#define EXYNOS4_GPIO_L1_NR (3) -#define EXYNOS4_GPIO_L2_NR (8) -#define EXYNOS4_GPIO_X0_NR (8) -#define EXYNOS4_GPIO_X1_NR (8) -#define EXYNOS4_GPIO_X2_NR (8) -#define EXYNOS4_GPIO_X3_NR (8) -#define EXYNOS4_GPIO_Y0_NR (6) -#define EXYNOS4_GPIO_Y1_NR (4) -#define EXYNOS4_GPIO_Y2_NR (6) -#define EXYNOS4_GPIO_Y3_NR (8) -#define EXYNOS4_GPIO_Y4_NR (8) -#define EXYNOS4_GPIO_Y5_NR (8) -#define EXYNOS4_GPIO_Y6_NR (8) -#define EXYNOS4_GPIO_Z_NR (7) - -/* EXYNOS4 GPIO bank numbers */ - -enum exynos4_gpio_number { - EXYNOS4_GPIO_A0_START = 0, - EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0), - EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1), - EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B), - EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0), - EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1), - EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0), - EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1), - EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0), - EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1), - EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2), - EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3), - EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4), - EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0), - EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1), - EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2), - EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3), - EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0), - EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1), - EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0), - EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1), - EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2), - EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3), - EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0), - EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1), - EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2), - EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0), - EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1), - EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2), - EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3), - EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0), - EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1), - EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2), - EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3), - EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4), - EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5), - EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6), -}; - -/* EXYNOS4 GPIO number definitions */ - -#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr)) -#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr)) -#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr)) -#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr)) -#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr)) -#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr)) -#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr)) -#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr)) -#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr)) -#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr)) -#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr)) -#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr)) -#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr)) -#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr)) -#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr)) -#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr)) -#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr)) -#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr)) -#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr)) -#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr)) -#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr)) -#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr)) -#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr)) -#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr)) -#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr)) -#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr)) -#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr)) -#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr)) -#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr)) -#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr)) -#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr)) -#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr)) -#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr)) -#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr)) -#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr)) -#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr)) -#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr)) - -/* the end of the EXYNOS4 specific gpios */ - -#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1) - -/* EXYNOS5 GPIO bank sizes */ - -#define EXYNOS5_GPIO_A0_NR (8) -#define EXYNOS5_GPIO_A1_NR (6) -#define EXYNOS5_GPIO_A2_NR (8) -#define EXYNOS5_GPIO_B0_NR (5) -#define EXYNOS5_GPIO_B1_NR (5) -#define EXYNOS5_GPIO_B2_NR (4) -#define EXYNOS5_GPIO_B3_NR (4) -#define EXYNOS5_GPIO_C0_NR (7) -#define EXYNOS5_GPIO_C1_NR (4) -#define EXYNOS5_GPIO_C2_NR (7) -#define EXYNOS5_GPIO_C3_NR (7) -#define EXYNOS5_GPIO_C4_NR (7) -#define EXYNOS5_GPIO_D0_NR (4) -#define EXYNOS5_GPIO_D1_NR (8) -#define EXYNOS5_GPIO_Y0_NR (6) -#define EXYNOS5_GPIO_Y1_NR (4) -#define EXYNOS5_GPIO_Y2_NR (6) -#define EXYNOS5_GPIO_Y3_NR (8) -#define EXYNOS5_GPIO_Y4_NR (8) -#define EXYNOS5_GPIO_Y5_NR (8) -#define EXYNOS5_GPIO_Y6_NR (8) -#define EXYNOS5_GPIO_X0_NR (8) -#define EXYNOS5_GPIO_X1_NR (8) -#define EXYNOS5_GPIO_X2_NR (8) -#define EXYNOS5_GPIO_X3_NR (8) -#define EXYNOS5_GPIO_E0_NR (8) -#define EXYNOS5_GPIO_E1_NR (2) -#define EXYNOS5_GPIO_F0_NR (4) -#define EXYNOS5_GPIO_F1_NR (4) -#define EXYNOS5_GPIO_G0_NR (8) -#define EXYNOS5_GPIO_G1_NR (8) -#define EXYNOS5_GPIO_G2_NR (2) -#define EXYNOS5_GPIO_H0_NR (4) -#define EXYNOS5_GPIO_H1_NR (8) -#define EXYNOS5_GPIO_V0_NR (8) -#define EXYNOS5_GPIO_V1_NR (8) -#define EXYNOS5_GPIO_V2_NR (8) -#define EXYNOS5_GPIO_V3_NR (8) -#define EXYNOS5_GPIO_V4_NR (2) -#define EXYNOS5_GPIO_Z_NR (7) - -/* EXYNOS5 GPIO bank numbers */ - -enum exynos5_gpio_number { - EXYNOS5_GPIO_A0_START = 0, - EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0), - EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1), - EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2), - EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0), - EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1), - EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2), - EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3), - EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0), - EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1), - EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2), - EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3), - EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4), - EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0), - EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1), - EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0), - EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1), - EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2), - EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3), - EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4), - EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5), - EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6), - EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0), - EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1), - EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2), - EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3), - EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0), - EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1), - EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0), - EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1), - EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0), - EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1), - EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2), - EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0), - EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1), - EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0), - EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1), - EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2), - EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3), - EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4), -}; - -/* EXYNOS5 GPIO number definitions */ - -#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr)) -#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr)) -#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr)) -#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr)) -#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr)) -#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr)) -#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr)) -#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr)) -#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr)) -#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr)) -#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr)) -#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr)) -#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr)) -#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr)) -#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr)) -#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr)) -#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr)) -#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr)) -#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr)) -#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr)) -#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr)) -#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr)) -#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr)) -#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr)) -#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr)) -#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr)) -#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr)) -#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr)) -#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr)) -#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr)) -#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr)) -#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr)) -#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr)) -#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr)) -#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr)) -#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr)) -#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr)) -#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr)) -#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr)) -#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr)) - -/* the end of the EXYNOS5 specific gpios */ - -#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1) - -/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */ - -#define S3C_GPIO_END (EXYNOS5_GPIO_END) - -/* define the number of gpios */ - -#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END) - -#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h deleted file mode 100644 index c72f59d91fc..00000000000 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - IRQ definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H __FILE__ - -#include <plat/irqs.h> - -/* PPI: Private Peripheral Interrupt */ - -#define IRQ_PPI(x) (x + 16) - -/* SPI: Shared Peripheral Interrupt */ - -#define IRQ_SPI(x) (x + 32) - -/* COMBINER */ - -#define MAX_IRQ_IN_COMBINER 8 -#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) -#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) - -/* For EXYNOS4 and EXYNOS5 */ - -#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) - -/* For EXYNOS4 SoCs */ - -#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16) -#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17) -#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18) -#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19) -#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20) -#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21) -#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22) -#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23) -#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24) -#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25) -#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26) -#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27) -#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28) -#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29) -#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30) -#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31) - -#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33) -#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34) -#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35) -#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36) -#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37) -#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38) -#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39) -#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40) -#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41) -#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42) -#define EXYNOS4_IRQ_WDT IRQ_SPI(43) -#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44) -#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45) -#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46) -#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47) -#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48) - -#define EXYNOS4_IRQ_UART0 IRQ_SPI(52) -#define EXYNOS4_IRQ_UART1 IRQ_SPI(53) -#define EXYNOS4_IRQ_UART2 IRQ_SPI(54) -#define EXYNOS4_IRQ_UART3 IRQ_SPI(55) -#define EXYNOS4_IRQ_UART4 IRQ_SPI(56) -#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57) -#define EXYNOS4_IRQ_IIC IRQ_SPI(58) -#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59) -#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60) -#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61) -#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62) -#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63) -#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64) -#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65) -#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66) -#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67) -#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68) - -#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70) -#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71) -#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72) -#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73) -#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74) -#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75) -#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76) -#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77) - -#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78) -#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80) - -#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82) -#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83) -#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84) -#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85) -#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86) -#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87) -#define EXYNOS4_IRQ_JPEG IRQ_SPI(88) -#define EXYNOS4_IRQ_2D IRQ_SPI(89) -#define EXYNOS4_IRQ_PCIE IRQ_SPI(90) - -#define EXYNOS4_IRQ_MIXER IRQ_SPI(91) -#define EXYNOS4_IRQ_HDMI IRQ_SPI(92) -#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93) -#define EXYNOS4_IRQ_MFC IRQ_SPI(94) -#define EXYNOS4_IRQ_SDO IRQ_SPI(95) - -#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96) -#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97) -#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98) -#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99) -#define EXYNOS4_IRQ_AC97 IRQ_SPI(100) - -#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104) -#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105) -#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106) -#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107) -#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108) -#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109) -#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110) -#define EXYNOS4_IRQ_GPS IRQ_SPI(111) -#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) -#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113) - -#define EXYNOS4_IRQ_TSI IRQ_SPI(115) -#define EXYNOS4_IRQ_SATA IRQ_SPI(116) - -#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2) -#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2) -#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2) -#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2) - -#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4) -#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4) - -#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) -#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) -#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) -#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) -#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) -#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) -#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) -#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) - -#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) -#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) -#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) -#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) -#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) -#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) -#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) -#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) - -#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0) -#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1) -#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2) -#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3) -#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4) -#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5) - -#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) -#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) -#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) - -#define EXYNOS4210_MAX_COMBINER_NR 16 -#define EXYNOS4212_MAX_COMBINER_NR 18 -#define EXYNOS4412_MAX_COMBINER_NR 20 -#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR - -#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 -#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 - -/* - * For Compatibility: - * the default is for EXYNOS4, and - * for exynos5, should be re-mapped at function - */ - -#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC -#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC -#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC -#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC -#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC - -#define IRQ_WDT EXYNOS4_IRQ_WDT -#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM -#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC -#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB -#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA - -#define IRQ_IIC EXYNOS4_IRQ_IIC -#define IRQ_IIC1 EXYNOS4_IRQ_IIC1 -#define IRQ_IIC3 EXYNOS4_IRQ_IIC3 -#define IRQ_IIC5 EXYNOS4_IRQ_IIC5 -#define IRQ_IIC6 EXYNOS4_IRQ_IIC6 -#define IRQ_IIC7 EXYNOS4_IRQ_IIC7 - -#define IRQ_SPI0 EXYNOS4_IRQ_SPI0 -#define IRQ_SPI1 EXYNOS4_IRQ_SPI1 -#define IRQ_SPI2 EXYNOS4_IRQ_SPI2 - -#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST -#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG - -#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0 -#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1 -#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2 -#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3 - -#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0 - -#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI - -#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0 -#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1 -#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2 -#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3 -#define IRQ_JPEG EXYNOS4_IRQ_JPEG -#define IRQ_2D EXYNOS4_IRQ_2D - -#define IRQ_MIXER EXYNOS4_IRQ_MIXER -#define IRQ_HDMI EXYNOS4_IRQ_HDMI -#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY -#define IRQ_MFC EXYNOS4_IRQ_MFC -#define IRQ_SDO EXYNOS4_IRQ_SDO - -#define IRQ_I2S0 EXYNOS4_IRQ_I2S0 - -#define IRQ_ADC EXYNOS4_IRQ_ADC0 -#define IRQ_TC EXYNOS4_IRQ_PEN0 - -#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD - -#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO -#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC -#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM - -#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS -#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS - -/* For EXYNOS5 SoCs */ - -#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33) -#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34) -#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35) -#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36) -#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37) -#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38) -#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39) -#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40) -#define EXYNOS5_IRQ_RTIC IRQ_SPI(41) -#define EXYNOS5_IRQ_WDT IRQ_SPI(42) -#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43) -#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44) -#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45) -#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46) -#define EXYNOS5_IRQ_GPIO IRQ_SPI(47) -#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48) -#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49) -#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50) -#define EXYNOS5_IRQ_IIC IRQ_SPI(56) -#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57) -#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58) -#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59) -#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60) -#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61) -#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62) -#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63) -#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64) -#define EXYNOS5_IRQ_TMU IRQ_SPI(65) -#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66) -#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67) -#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68) -#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69) -#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70) -#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71) -#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72) -#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73) -#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74) -#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75) -#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76) -#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77) -#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78) -#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79) -#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) -#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) -#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) -#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83) -#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) -#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) -#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) -#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87) -#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88) -#define EXYNOS5_IRQ_JPEG IRQ_SPI(89) -#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) -#define EXYNOS5_IRQ_2D IRQ_SPI(91) -#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92) -#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93) -#define EXYNOS5_IRQ_MIXER IRQ_SPI(94) -#define EXYNOS5_IRQ_HDMI IRQ_SPI(95) -#define EXYNOS5_IRQ_MFC IRQ_SPI(96) -#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97) -#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98) -#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99) -#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100) -#define EXYNOS5_IRQ_AC97 IRQ_SPI(101) -#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102) -#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103) -#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) -#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) -#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) -#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107) -#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) -#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) -#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) -#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111) -#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) -#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) -#define EXYNOS5_IRQ_CEC IRQ_SPI(114) -#define EXYNOS5_IRQ_SATA IRQ_SPI(115) - -#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) -#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) -#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) -#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126) -#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) - -/* EXYNOS5440 */ - -#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2) -#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3) - -#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) - -#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) -#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) -#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2) -#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3) -#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4) -#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5) -#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) -#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) - -#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0) -#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1) -#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) -#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) -#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) -#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5) -#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6) -#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7) - -#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0) -#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1) -#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2) -#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3) - -#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0) -#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1) -#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2) -#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3) -#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4) -#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5) -#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6) -#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7) - -#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) -#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) -#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2) -#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3) -#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) -#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) -#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) -#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7) - -#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0) -#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1) -#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2) -#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) -#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) -#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) - -#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5) -#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6) - -#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) -#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) - -#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3) -#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4) -#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5) -#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6) -#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7) - -#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0) -#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1) -#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) -#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) - -#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1) - -#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3) - -#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) -#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) -#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) - -#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0) -#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1) -#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3) -#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4) - -#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) - -#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) - -#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) -#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) -#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2) -#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5) -#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6) - -#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0) -#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1) - -#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0) -#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1) - -#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0) -#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1) - -#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0) -#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1) - -#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0) -#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1) - -#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0) -#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1) - -#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0) -#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1) - -#define EXYNOS5_MAX_COMBINER_NR 32 - -#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14 -#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 -#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 -#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 - -#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \ - EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR) - -#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0) -#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16) -#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) -#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) -#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) - -/* Set the default NR_IRQS */ -#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) - -#ifndef CONFIG_SPARSE_IRQ -#define NR_IRQS EXYNOS_NR_IRQS -#endif - -#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 92b29bb583c..7b046b59d9e 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -30,31 +30,6 @@ #define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 #define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 -#define EXYNOS4_PA_FIMC0 0x11800000 -#define EXYNOS4_PA_FIMC1 0x11810000 -#define EXYNOS4_PA_FIMC2 0x11820000 -#define EXYNOS4_PA_FIMC3 0x11830000 - -#define EXYNOS4_PA_JPEG 0x11840000 - -/* x = 0...1 */ -#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000)) - -#define EXYNOS4_PA_G2D 0x12800000 - -#define EXYNOS4_PA_I2S0 0x03830000 -#define EXYNOS4_PA_I2S1 0xE3100000 -#define EXYNOS4_PA_I2S2 0xE2A00000 - -#define EXYNOS4_PA_PCM0 0x03840000 -#define EXYNOS4_PA_PCM1 0x13980000 -#define EXYNOS4_PA_PCM2 0x13990000 - -#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) - -#define EXYNOS4_PA_ONENAND 0x0C000000 -#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 - #define EXYNOS_PA_CHIPID 0x10000000 #define EXYNOS4_PA_SYSCON 0x10010000 @@ -71,10 +46,6 @@ #define EXYNOS4_PA_WATCHDOG 0x10060000 #define EXYNOS5_PA_WATCHDOG 0x101D0000 -#define EXYNOS4_PA_RTC 0x10070000 - -#define EXYNOS4_PA_KEYPAD 0x100A0000 - #define EXYNOS4_PA_DMC0 0x10400000 #define EXYNOS4_PA_DMC1 0x10410000 @@ -87,207 +58,22 @@ #define EXYNOS5_PA_GIC_DIST 0x10481000 #define EXYNOS4_PA_COREPERI 0x10500000 -#define EXYNOS4_PA_TWD 0x10500600 #define EXYNOS4_PA_L2CC 0x10502000 -#define EXYNOS4_PA_TMU 0x100C0000 - -#define EXYNOS4_PA_MDMA0 0x10810000 -#define EXYNOS4_PA_MDMA1 0x12850000 -#define EXYNOS4_PA_S_MDMA1 0x12840000 -#define EXYNOS4_PA_PDMA0 0x12680000 -#define EXYNOS4_PA_PDMA1 0x12690000 -#define EXYNOS5_PA_MDMA0 0x10800000 -#define EXYNOS5_PA_MDMA1 0x11C10000 -#define EXYNOS5_PA_PDMA0 0x121A0000 -#define EXYNOS5_PA_PDMA1 0x121B0000 - -#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 -#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000 -#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 -#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 -#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 -#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000 -#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000 -#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 -#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 -#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 -#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000 -#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000 -#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000 -#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000 -#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000 -#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000 -#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 -#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 -#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 -#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000 -#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 -#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 -#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 - -#define EXYNOS5_PA_GSC0 0x13E00000 -#define EXYNOS5_PA_GSC1 0x13E10000 -#define EXYNOS5_PA_GSC2 0x13E20000 -#define EXYNOS5_PA_GSC3 0x13E30000 - -#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000 -#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000 -#define EXYNOS5_PA_SYSMMU_2D 0x10A60000 -#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000 -#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000 -#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000 -#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000 -#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 -#define EXYNOS5_PA_SYSMMU_IOP 0x12360000 -#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 -#define EXYNOS5_PA_SYSMMU_ISP 0x13260000 -#define EXYNOS5_PA_SYSMMU_DRC 0x12370000 -#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 -#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000 -#define EXYNOS5_PA_SYSMMU_FD 0x132A0000 -#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000 -#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000 -#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000 -#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000 -#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000 -#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000 -#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000 -#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000 -#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000 -#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000 -#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000 -#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000 -#define EXYNOS5_PA_SYSMMU_TV 0x14650000 - -#define EXYNOS4_PA_SPI0 0x13920000 -#define EXYNOS4_PA_SPI1 0x13930000 -#define EXYNOS4_PA_SPI2 0x13940000 -#define EXYNOS5_PA_SPI0 0x12D20000 -#define EXYNOS5_PA_SPI1 0x12D30000 -#define EXYNOS5_PA_SPI2 0x12D40000 - -#define EXYNOS4_PA_GPIO1 0x11400000 -#define EXYNOS4_PA_GPIO2 0x11000000 -#define EXYNOS4_PA_GPIO3 0x03860000 -#define EXYNOS5_PA_GPIO1 0x11400000 -#define EXYNOS5_PA_GPIO2 0x13400000 -#define EXYNOS5_PA_GPIO3 0x10D10000 -#define EXYNOS5_PA_GPIO4 0x03860000 - -#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 -#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 - -#define EXYNOS4_PA_FIMD0 0x11C00000 - -#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) -#define EXYNOS4_PA_DWMCI 0x12550000 -#define EXYNOS5_PA_DWMCI0 0x12200000 -#define EXYNOS5_PA_DWMCI1 0x12210000 -#define EXYNOS5_PA_DWMCI2 0x12220000 -#define EXYNOS5_PA_DWMCI3 0x12230000 - -#define EXYNOS4_PA_HSOTG 0x12480000 -#define EXYNOS4_PA_USB_HSPHY 0x125B0000 - -#define EXYNOS4_PA_SATA 0x12560000 -#define EXYNOS4_PA_SATAPHY 0x125D0000 -#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 - #define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS5_PA_SROMC 0x12250000 -#define EXYNOS4_PA_EHCI 0x12580000 -#define EXYNOS4_PA_OHCI 0x12590000 #define EXYNOS4_PA_HSPHY 0x125B0000 -#define EXYNOS4_PA_MFC 0x13400000 #define EXYNOS4_PA_UART 0x13800000 #define EXYNOS5_PA_UART 0x12C00000 -#define EXYNOS4_PA_VP 0x12C00000 -#define EXYNOS4_PA_MIXER 0x12C10000 -#define EXYNOS4_PA_SDO 0x12C20000 -#define EXYNOS4_PA_HDMI 0x12D00000 -#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 - -#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) -#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000)) - -#define EXYNOS4_PA_ADC 0x13910000 -#define EXYNOS4_PA_ADC1 0x13911000 - -#define EXYNOS4_PA_AC97 0x139A0000 - -#define EXYNOS4_PA_SPDIF 0x139B0000 - #define EXYNOS4_PA_TIMER 0x139D0000 #define EXYNOS5_PA_TIMER 0x12DD0000 -#define EXYNOS4_PA_SDRAM 0x40000000 -#define EXYNOS5_PA_SDRAM 0x40000000 - -/* Compatibiltiy Defines */ - -#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0) -#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1) -#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2) -#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3) -#define S3C_PA_IIC EXYNOS4_PA_IIC(0) -#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1) -#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2) -#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3) -#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4) -#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) -#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) -#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) -#define S3C_PA_RTC EXYNOS4_PA_RTC -#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG -#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 -#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 -#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 -#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG - -#define S5P_PA_EHCI EXYNOS4_PA_EHCI -#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 -#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 -#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 -#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 -#define S5P_PA_JPEG EXYNOS4_PA_JPEG -#define S5P_PA_G2D EXYNOS4_PA_G2D -#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 -#define S5P_PA_HDMI EXYNOS4_PA_HDMI -#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY -#define S5P_PA_MFC EXYNOS4_PA_MFC -#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 -#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 -#define S5P_PA_MIXER EXYNOS4_PA_MIXER -#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND -#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA -#define S5P_PA_SDO EXYNOS4_PA_SDO -#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM -#define S5P_PA_VP EXYNOS4_PA_VP - -#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC -#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 -#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD - /* Compatibility UART */ -#define EXYNOS4_PA_UART0 0x13800000 -#define EXYNOS4_PA_UART1 0x13810000 -#define EXYNOS4_PA_UART2 0x13820000 -#define EXYNOS4_PA_UART3 0x13830000 -#define EXYNOS4_SZ_UART SZ_256 - -#define EXYNOS5_PA_UART0 0x12C00000 -#define EXYNOS5_PA_UART1 0x12C10000 -#define EXYNOS5_PA_UART2 0x12C20000 -#define EXYNOS5_PA_UART3 0x12C30000 - #define EXYNOS5440_PA_UART0 0x000B0000 -#define EXYNOS5440_PA_UART1 0x000C0000 -#define EXYNOS5440_SZ_UART SZ_256 #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 296090e7f42..2b00833b664 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void) static inline void s3c_pm_arch_prepare_irqs(void) { - u32 eintmask = s3c_irqwake_eintmask; - - if (of_have_populated_dt()) - eintmask = exynos_get_eint_wake_mask(); - - __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK); + __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); } @@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void) /* nothing here yet */ } +/* Compatibility definitions to make plat-samsung/pm.c compile */ +#define IRQ_EINT_BIT(x) 1 +#define s3c_irqwake_intallow 0 +#define s3c_irqwake_eintallow 0 + #endif /* __ASM_ARCH_PM_CORE_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h deleted file mode 100644 index e4b5b60dcb8..00000000000 --- a/arch/arm/mach-exynos/include/mach/regs-gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - GPIO (including EINT) register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_GPIO_H -#define __ASM_ARCH_REGS_GPIO_H __FILE__ - -#include <mach/map.h> -#include <mach/irqs.h> - -#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) -#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4)) -#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4)) -#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4)) -#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4)) - -#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7)) - -/* compatibility for plat-s5p/irq-pm.c */ -#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) -#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) - -#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80) -#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4)) - -#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00) -#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4)) - -#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) -#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) - -#endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h deleted file mode 100644 index 07277735252..00000000000 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __PLAT_S5P_REGS_USB_PHY_H -#define __PLAT_S5P_REGS_USB_PHY_H - -#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) - -#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00) -#define PHY1_HSIC_NORMAL_MASK (0xf << 9) -#define PHY1_HSIC1_SLEEP (1 << 12) -#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11) -#define PHY1_HSIC0_SLEEP (1 << 10) -#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9) - -#define PHY1_STD_NORMAL_MASK (0x7 << 6) -#define PHY1_STD_SLEEP (1 << 8) -#define PHY1_STD_ANALOG_POWERDOWN (1 << 7) -#define PHY1_STD_FORCE_SUSPEND (1 << 6) - -#define PHY0_NORMAL_MASK (0x39 << 0) -#define PHY0_SLEEP (1 << 5) -#define PHY0_OTG_DISABLE (1 << 4) -#define PHY0_ANALOG_POWERDOWN (1 << 3) -#define PHY0_FORCE_SUSPEND (1 << 0) - -#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04) -#define PHY1_COMMON_ON_N (1 << 7) -#define PHY0_COMMON_ON_N (1 << 4) -#define PHY0_ID_PULLUP (1 << 2) - -#define EXYNOS4_CLKSEL_SHIFT (0) - -#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) -#define EXYNOS4210_CLKSEL_48M (0x0 << 0) -#define EXYNOS4210_CLKSEL_12M (0x2 << 0) -#define EXYNOS4210_CLKSEL_24M (0x3 << 0) - -#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) -#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) -#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) -#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) -#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) -#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) -#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) - -#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) -#define HOST_LINK_PORT_SWRST_MASK (0xf << 6) -#define HOST_LINK_PORT2_SWRST (1 << 9) -#define HOST_LINK_PORT1_SWRST (1 << 8) -#define HOST_LINK_PORT0_SWRST (1 << 7) -#define HOST_LINK_ALL_SWRST (1 << 6) - -#define PHY1_SWRST_MASK (0x7 << 3) -#define PHY1_HSIC_SWRST (1 << 5) -#define PHY1_STD_SWRST (1 << 4) -#define PHY1_ALL_SWRST (1 << 3) - -#define PHY0_SWRST_MASK (0x7 << 0) -#define PHY0_PHYLINK_SWRST (1 << 2) -#define PHY0_HLINK_SWRST (1 << 1) -#define PHY0_SWRST (1 << 0) - -#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34) -#define FPENABLEN (1 << 0) - -#endif /* __PLAT_S5P_REGS_USB_PHY_H */ diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h index 2979995d5a6..d405762be18 100644 --- a/arch/arm/mach-exynos/include/mach/uncompress.h +++ b/arch/arm/mach-exynos/include/mach/uncompress.h @@ -15,9 +15,6 @@ #include <asm/mach-types.h> #include <mach/map.h> - -volatile u8 *uart_base; - #include <plat/uncompress.h> static unsigned int __raw_readl(unsigned int ptr) diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c deleted file mode 100644 index 5f0f5570137..00000000000 --- a/arch/arm/mach-exynos/mach-armlex4210.c +++ /dev/null @@ -1,207 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-armlex4210.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <linux/io.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/smsc911x.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/regs-serial.h> -#include <plat/regs-srom.h> -#include <plat/sdhci.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = ARMLEX4210_UCON_DEFAULT, - .ulcon = ARMLEX4210_ULCON_DEFAULT, - .ufcon = ARMLEX4210_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_PERMANENT, -#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPX2(5), - .ext_cd_gpio_invert = 1, - .max_width = 4, -}; - -static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_PERMANENT, - .max_width = 4, -}; - -static void __init armlex4210_sdhci_init(void) -{ - s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata); - s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata); -} - -static void __init armlex4210_wlan_init(void) -{ - /* enable */ - s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP); - - /* reset */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP); - - /* wakeup */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP); -} - -static struct resource armlex4210_smsc911x_resources[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K), - [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \ - | IRQF_TRIGGER_HIGH), -}; - -static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, - .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, -}; - -static struct platform_device armlex4210_smsc911x = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources), - .resource = armlex4210_smsc911x_resources, - .dev = { - .platform_data = &smsc9215_config, - }, -}; - -static struct platform_device *armlex4210_devices[] __initdata = { - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_rtc, - &s3c_device_wdt, - &armlex4210_smsc911x, - &exynos4_device_ahci, -}; - -static void __init armlex4210_smsc911x_init(void) -{ - u32 cs1; - - /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5P_SROM_BW) & - ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | - (0 << S5P_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5P_SROM_BW__ADDRMODE__SHIFT) | - (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << - S5P_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5P_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | - (0x9 << S5P_SROM_BCX__TACP__SHIFT) | - (0xc << S5P_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5P_SROM_BCX__TACC__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); -} - -static void __init armlex4210_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(armlex4210_uartcfgs, - ARRAY_SIZE(armlex4210_uartcfgs)); -} - -static void __init armlex4210_machine_init(void) -{ - armlex4210_smsc911x_init(); - - armlex4210_sdhci_init(); - - armlex4210_wlan_init(); - - platform_add_devices(armlex4210_devices, - ARRAY_SIZE(armlex4210_devices)); -} - -MACHINE_START(ARMLEX4210, "ARMLEX4210") - /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = armlex4210_map_io, - .init_machine = armlex4210_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index b9ed834a7ee..0099c6c13bb 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -23,11 +23,6 @@ #include "common.h" -static void __init exynos4_dt_map_io(void) -{ - exynos_init_io(NULL, 0); -} - static void __init exynos4_dt_machine_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -55,8 +50,7 @@ static void __init exynos4_reserve(void) DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = exynos4_dt_map_io, + .map_io = exynos_init_io, .init_early = exynos_firmware_init, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 753b94f3fca..d5c8afdeaa3 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -23,11 +23,6 @@ #include "common.h" -static void __init exynos5_dt_map_io(void) -{ - exynos_init_io(NULL, 0); -} - static void __init exynos5_dt_machine_init(void) { struct device_node *i2c_np; @@ -76,9 +71,8 @@ static void __init exynos5_reserve(void) DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .init_irq = exynos5_init_irq, .smp = smp_ops(exynos_smp_ops), - .map_io = exynos5_dt_map_io, + .map_io = exynos_init_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, .init_time = exynos_init_time, diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c deleted file mode 100644 index 5c8b2878dbb..00000000000 --- a/arch/arm/mach-exynos/mach-nuri.c +++ /dev/null @@ -1,1388 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/mach-nuri.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/i2c/atmel_mxt_ts.h> -#include <linux/i2c-gpio.h> -#include <linux/gpio_keys.h> -#include <linux/gpio.h> -#include <linux/power/max8903_charger.h> -#include <linux/power/max17042_battery.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/max8997.h> -#include <linux/mfd/max8997-private.h> -#include <linux/mmc/host.h> -#include <linux/fb.h> -#include <linux/pwm_backlight.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/mipi-csis.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/usb-ehci-s5p.h> -#include <drm/exynos_drm.h> - -#include <video/platform_lcd.h> -#include <video/samsung_fimd.h> -#include <media/m5mols.h> -#include <media/s5k6aa.h> -#include <media/s5p_fimc.h> -#include <media/v4l2-mediabus.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/adc.h> -#include <plat/regs-serial.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/sdhci.h> -#include <plat/clock.h> -#include <plat/gpio-cfg.h> -#include <plat/mfc.h> -#include <plat/fimc-core.h> -#include <plat/camport.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG256 | \ - S5PV210_UFCON_RXTRIG256) - -enum fixed_regulator_id { - FIXED_REG_ID_MMC = 0, - FIXED_REG_ID_MAX8903, - FIXED_REG_ID_CAM_A28V, - FIXED_REG_ID_CAM_12V, - FIXED_REG_ID_CAM_VT_15V, -}; - -static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = { - { - .hwport = 0, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, - { - .hwport = 1, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, - { - .hwport = 2, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, - { - .hwport = 3, - .ucon = NURI_UCON_DEFAULT, - .ulcon = NURI_ULCON_DEFAULT, - .ufcon = NURI_UFCON_DEFAULT, - }, -}; - -/* eMMC */ -static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { - .max_width = 8, - .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | - MMC_CAP_ERASE), - .cd_type = S3C_SDHCI_CD_PERMANENT, -}; - -static struct regulator_consumer_supply emmc_supplies[] = { - REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"), - REGULATOR_SUPPLY("vmmc", "dw_mmc"), -}; - -static struct regulator_init_data emmc_fixed_voltage_init_data = { - .constraints = { - .name = "VMEM_VDD_2.8V", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(emmc_supplies), - .consumer_supplies = emmc_supplies, -}; - -static struct fixed_voltage_config emmc_fixed_voltage_config = { - .supply_name = "MASSMEMORY_EN (inverted)", - .microvolts = 2800000, - .gpio = EXYNOS4_GPL1(1), - .enable_high = false, - .init_data = &emmc_fixed_voltage_init_data, -}; - -static struct platform_device emmc_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_MMC, - .dev = { - .platform_data = &emmc_fixed_voltage_config, - }, -}; - -/* SD */ -static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */ - .ext_cd_gpio_invert = 1, - .cd_type = S3C_SDHCI_CD_GPIO, -}; - -/* WLAN */ -static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .cd_type = S3C_SDHCI_CD_EXTERNAL, -}; - -static void __init nuri_sdhci_init(void) -{ - s3c_sdhci0_set_platdata(&nuri_hsmmc0_data); - s3c_sdhci2_set_platdata(&nuri_hsmmc2_data); - s3c_sdhci3_set_platdata(&nuri_hsmmc3_data); -} - -/* GPIO KEYS */ -static struct gpio_keys_button nuri_gpio_keys_tables[] = { - { - .code = KEY_VOLUMEUP, - .gpio = EXYNOS4_GPX2(0), /* XEINT16 */ - .desc = "gpio-keys: KEY_VOLUMEUP", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_VOLUMEDOWN, - .gpio = EXYNOS4_GPX2(1), /* XEINT17 */ - .desc = "gpio-keys: KEY_VOLUMEDOWN", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_POWER, - .gpio = EXYNOS4_GPX2(7), /* XEINT23 */ - .desc = "gpio-keys: KEY_POWER", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, -}; - -static struct gpio_keys_platform_data nuri_gpio_keys_data = { - .buttons = nuri_gpio_keys_tables, - .nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables), -}; - -static struct platform_device nuri_gpio_keys = { - .name = "gpio-keys", - .dev = { - .platform_data = &nuri_gpio_keys_data, - }, -}; - -#ifdef CONFIG_DRM_EXYNOS -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .xres = 1024, - .yres = 600, - .hsync_len = 40, - .left_margin = 79, - .right_margin = 200, - .vsync_len = 10, - .upper_margin = 10, - .lower_margin = 11, - .refresh = 60, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 3, - .bpp = 32, -}; - -#else -/* Frame Buffer */ -static struct s3c_fb_pd_win nuri_fb_win0 = { - .max_bpp = 24, - .default_bpp = 16, - .xres = 1024, - .yres = 600, - .virtual_x = 1024, - .virtual_y = 2 * 600, -}; - -static struct fb_videomode nuri_lcd_timing = { - .left_margin = 64, - .right_margin = 16, - .upper_margin = 64, - .lower_margin = 1, - .hsync_len = 48, - .vsync_len = 3, - .xres = 1024, - .yres = 600, - .refresh = 60, -}; - -static struct s3c_fb_platdata nuri_fb_pdata __initdata = { - .win[0] = &nuri_fb_win0, - .vtiming = &nuri_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power) -{ - int gpio = EXYNOS4_GPE1(5); - - gpio_request(gpio, "LVDS_nSHDN"); - gpio_direction_output(gpio, power); - gpio_free(gpio); -} - -static int nuri_bl_init(struct device *dev) -{ - return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW, - "LCD_LD0_EN"); -} - -static int nuri_bl_notify(struct device *dev, int brightness) -{ - if (brightness < 1) - brightness = 0; - - gpio_set_value(EXYNOS4_GPE2(3), 1); - - return brightness; -} - -static void nuri_bl_exit(struct device *dev) -{ - gpio_free(EXYNOS4_GPE2(3)); -} - -/* nuri pwm backlight */ -static struct platform_pwm_backlight_data nuri_backlight_data = { - .pwm_id = 0, - .pwm_period_ns = 30000, - .max_brightness = 100, - .dft_brightness = 50, - .init = nuri_bl_init, - .notify = nuri_bl_notify, - .exit = nuri_bl_exit, -}; - -static struct platform_device nuri_backlight_device = { - .name = "pwm-backlight", - .id = -1, - .dev = { - .parent = &s3c_device_timer[0].dev, - .platform_data = &nuri_backlight_data, - }, -}; - -static struct plat_lcd_data nuri_lcd_platform_data = { - .set_power = nuri_lcd_power_on, -}; - -static struct platform_device nuri_lcd_device = { - .name = "platform-lcd", - .id = -1, - .dev = { - .platform_data = &nuri_lcd_platform_data, - }, -}; - -/* I2C1 */ -static struct i2c_board_info i2c1_devs[] __initdata = { - /* Gyro, To be updated */ -}; - -/* TSP */ -static struct mxt_platform_data mxt_platform_data = { - .x_line = 18, - .y_line = 11, - .x_size = 1024, - .y_size = 600, - .blen = 0x1, - .threshold = 0x28, - .voltage = 2800000, /* 2.8V */ - .orient = MXT_DIAGONAL_COUNTER, - .irqflags = IRQF_TRIGGER_FALLING, -}; - -static struct s3c2410_platform_i2c i2c3_data __initdata = { - .flags = 0, - .bus_num = 3, - .slave_addr = 0x10, - .frequency = 400 * 1000, - .sda_delay = 100, -}; - -static struct i2c_board_info i2c3_devs[] __initdata = { - { - I2C_BOARD_INFO("atmel_mxt_ts", 0x4a), - .platform_data = &mxt_platform_data, - .irq = IRQ_EINT(4), - }, -}; - -static void __init nuri_tsp_init(void) -{ - int gpio; - - /* TOUCH_INT: XEINT_4 */ - gpio = EXYNOS4_GPX0(4); - gpio_request(gpio, "TOUCH_INT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); -} - -static struct regulator_consumer_supply __initdata max8997_ldo1_[] = { - REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo3_[] = { - REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */ - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo4_[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo5_[] = { - REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */ -}; -static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = { - REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo7_[] = { - REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo8_[] = { - REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */ - REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo11_[] = { - REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo12_[] = { - REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo13_[] = { - REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo14_[] = { - REGULATOR_SUPPLY("inmotor", "max8997-haptic"), -}; -static struct regulator_consumer_supply __initdata max8997_ldo15_[] = { - REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo16_[] = { - REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */ -}; -static struct regulator_consumer_supply __initdata max8997_ldo18_[] = { - REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */ -}; -static struct regulator_consumer_supply __initdata max8997_buck1_[] = { - REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata max8997_buck2_[] = { - REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata max8997_buck3_[] = { - REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */ -}; -static struct regulator_consumer_supply __initdata max8997_buck4_[] = { - REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */ -}; -static struct regulator_consumer_supply __initdata max8997_buck6_[] = { - REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */ -}; -static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = { - REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */ -}; -static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = { - REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */ -}; - -static struct regulator_consumer_supply __initdata max8997_charger_[] = { - REGULATOR_SUPPLY("vinchg1", "charger-manager.0"), -}; -static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = { - REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */ -}; - -static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = { - REGULATOR_SUPPLY("gps_clk", "bcm4751"), - REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"), - REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"), -}; - -static struct regulator_init_data __initdata max8997_ldo1_data = { - .constraints = { - .name = "VADC_3.3V_C210", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_), - .consumer_supplies = max8997_ldo1_, -}; - -static struct regulator_init_data __initdata max8997_ldo2_data = { - .constraints = { - .name = "VALIVE_1.1V_C210", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo3_data = { - .constraints = { - .name = "VUSB_1.1V_C210", - .min_uV = 1100000, - .max_uV = 1100000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_), - .consumer_supplies = max8997_ldo3_, -}; - -static struct regulator_init_data __initdata max8997_ldo4_data = { - .constraints = { - .name = "VMIPI_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_), - .consumer_supplies = max8997_ldo4_, -}; - -static struct regulator_init_data __initdata max8997_ldo5_data = { - .constraints = { - .name = "VHSIC_1.2V_C210", - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_), - .consumer_supplies = max8997_ldo5_, -}; - -static struct regulator_init_data __initdata max8997_ldo6_data = { - .constraints = { - .name = "VCC_1.8V_PDA", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(nuri_max8997_ldo6_consumer), - .consumer_supplies = nuri_max8997_ldo6_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo7_data = { - .constraints = { - .name = "CAM_ISP_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_), - .consumer_supplies = max8997_ldo7_, -}; - -static struct regulator_init_data __initdata max8997_ldo8_data = { - .constraints = { - .name = "VUSB+VDAC_3.3V_C210", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_), - .consumer_supplies = max8997_ldo8_, -}; - -static struct regulator_init_data __initdata max8997_ldo9_data = { - .constraints = { - .name = "VCC_2.8V_PDA", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo10_data = { - .constraints = { - .name = "VPLL_1.1V_C210", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo11_data = { - .constraints = { - .name = "LVDS_VDD3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_), - .consumer_supplies = max8997_ldo11_, -}; - -static struct regulator_init_data __initdata max8997_ldo12_data = { - .constraints = { - .name = "VT_CAM_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_), - .consumer_supplies = max8997_ldo12_, -}; - -static struct regulator_init_data __initdata max8997_ldo13_data = { - .constraints = { - .name = "VTF_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_), - .consumer_supplies = max8997_ldo13_, -}; - -static struct regulator_init_data __initdata max8997_ldo14_data = { - .constraints = { - .name = "VCC_3.0V_MOTOR", - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_), - .consumer_supplies = max8997_ldo14_, -}; - -static struct regulator_init_data __initdata max8997_ldo15_data = { - .constraints = { - .name = "VTOUCH_ADVV2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_), - .consumer_supplies = max8997_ldo15_, -}; - -static struct regulator_init_data __initdata max8997_ldo16_data = { - .constraints = { - .name = "CAM_SENSOR_IO_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_), - .consumer_supplies = max8997_ldo16_, -}; - -static struct regulator_init_data __initdata max8997_ldo18_data = { - .constraints = { - .name = "VTOUCH_VDD2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_), - .consumer_supplies = max8997_ldo18_, -}; - -static struct regulator_init_data __initdata max8997_ldo21_data = { - .constraints = { - .name = "VDDQ_M1M2_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck1_data = { - .constraints = { - .name = "VARM_1.2V_C210", - .min_uV = 900000, - .max_uV = 1350000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_), - .consumer_supplies = max8997_buck1_, -}; - -static struct regulator_init_data __initdata max8997_buck2_data = { - .constraints = { - .name = "VINT_1.1V_C210", - .min_uV = 900000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_), - .consumer_supplies = max8997_buck2_, -}; - -static struct regulator_init_data __initdata max8997_buck3_data = { - .constraints = { - .name = "VG3D_1.1V_C210", - .min_uV = 900000, - .max_uV = 1100000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_), - .consumer_supplies = max8997_buck3_, -}; - -static struct regulator_init_data __initdata max8997_buck4_data = { - .constraints = { - .name = "CAM_ISP_CORE_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_), - .consumer_supplies = max8997_buck4_, -}; - -static struct regulator_init_data __initdata max8997_buck5_data = { - .constraints = { - .name = "VMEM_1.2V_C210", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck6_data = { - .constraints = { - .name = "CAM_AF_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_), - .consumer_supplies = max8997_buck6_, -}; - -static struct regulator_init_data __initdata max8997_buck7_data = { - .constraints = { - .name = "VCC_SUB_2.0V", - .min_uV = 2000000, - .max_uV = 2000000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_32khz_ap_data = { - .constraints = { - .name = "32KHz AP", - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_), - .consumer_supplies = max8997_32khz_ap_, -}; - -static struct regulator_init_data __initdata max8997_32khz_cp_data = { - .constraints = { - .name = "32KHz CP", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_vichg_data = { - .constraints = { - .name = "VICHG", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_esafeout1_data = { - .constraints = { - .name = "SAFEOUT1", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_), - .consumer_supplies = max8997_esafeout1_, -}; - -static struct regulator_init_data __initdata max8997_esafeout2_data = { - .constraints = { - .name = "SAFEOUT2", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_), - .consumer_supplies = max8997_esafeout2_, -}; - -static struct regulator_init_data __initdata max8997_charger_cv_data = { - .constraints = { - .name = "CHARGER_CV", - .min_uV = 4200000, - .max_uV = 4200000, - .apply_uV = 1, - }, -}; - -static struct regulator_init_data __initdata max8997_charger_data = { - .constraints = { - .name = "CHARGER", - .min_uA = 200000, - .max_uA = 950000, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_CURRENT, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_charger_), - .consumer_supplies = max8997_charger_, -}; - -static struct regulator_init_data __initdata max8997_charger_topoff_data = { - .constraints = { - .name = "CHARGER TOPOFF", - .min_uA = 50000, - .max_uA = 200000, - .valid_ops_mask = REGULATOR_CHANGE_CURRENT, - }, - .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_), - .consumer_supplies = max8997_chg_toff_, -}; - -static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = { - { MAX8997_LDO1, &max8997_ldo1_data }, - { MAX8997_LDO2, &max8997_ldo2_data }, - { MAX8997_LDO3, &max8997_ldo3_data }, - { MAX8997_LDO4, &max8997_ldo4_data }, - { MAX8997_LDO5, &max8997_ldo5_data }, - { MAX8997_LDO6, &max8997_ldo6_data }, - { MAX8997_LDO7, &max8997_ldo7_data }, - { MAX8997_LDO8, &max8997_ldo8_data }, - { MAX8997_LDO9, &max8997_ldo9_data }, - { MAX8997_LDO10, &max8997_ldo10_data }, - { MAX8997_LDO11, &max8997_ldo11_data }, - { MAX8997_LDO12, &max8997_ldo12_data }, - { MAX8997_LDO13, &max8997_ldo13_data }, - { MAX8997_LDO14, &max8997_ldo14_data }, - { MAX8997_LDO15, &max8997_ldo15_data }, - { MAX8997_LDO16, &max8997_ldo16_data }, - - { MAX8997_LDO18, &max8997_ldo18_data }, - { MAX8997_LDO21, &max8997_ldo21_data }, - - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, - { MAX8997_BUCK4, &max8997_buck4_data }, - { MAX8997_BUCK5, &max8997_buck5_data }, - { MAX8997_BUCK6, &max8997_buck6_data }, - { MAX8997_BUCK7, &max8997_buck7_data }, - - { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data }, - { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data }, - - { MAX8997_ENVICHG, &max8997_vichg_data }, - { MAX8997_ESAFEOUT1, &max8997_esafeout1_data }, - { MAX8997_ESAFEOUT2, &max8997_esafeout2_data }, - { MAX8997_CHARGER_CV, &max8997_charger_cv_data }, - { MAX8997_CHARGER, &max8997_charger_data }, - { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data }, -}; - -static struct max8997_platform_data __initdata nuri_max8997_pdata = { - .wakeup = 1, - - .num_regulators = ARRAY_SIZE(nuri_max8997_regulators), - .regulators = nuri_max8997_regulators, - - .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) }, - - .buck1_voltage[0] = 1350000, /* 1.35V */ - .buck1_voltage[1] = 1300000, /* 1.3V */ - .buck1_voltage[2] = 1250000, /* 1.25V */ - .buck1_voltage[3] = 1200000, /* 1.2V */ - .buck1_voltage[4] = 1150000, /* 1.15V */ - .buck1_voltage[5] = 1100000, /* 1.1V */ - .buck1_voltage[6] = 1000000, /* 1.0V */ - .buck1_voltage[7] = 950000, /* 0.95V */ - - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1000000, /* 1.0V */ - .buck2_voltage[2] = 950000, /* 0.95V */ - .buck2_voltage[3] = 900000, /* 0.9V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1000000, /* 1.0V */ - .buck2_voltage[6] = 950000, /* 0.95V */ - .buck2_voltage[7] = 900000, /* 0.9V */ - - .buck5_voltage[0] = 1200000, /* 1.2V */ - .buck5_voltage[1] = 1200000, /* 1.2V */ - .buck5_voltage[2] = 1200000, /* 1.2V */ - .buck5_voltage[3] = 1200000, /* 1.2V */ - .buck5_voltage[4] = 1200000, /* 1.2V */ - .buck5_voltage[5] = 1200000, /* 1.2V */ - .buck5_voltage[6] = 1200000, /* 1.2V */ - .buck5_voltage[7] = 1200000, /* 1.2V */ -}; - -/* GPIO I2C 5 (PMIC) */ -enum { I2C5_MAX8997 }; -static struct i2c_board_info i2c5_devs[] __initdata = { - [I2C5_MAX8997] = { - I2C_BOARD_INFO("max8997", 0xCC >> 1), - .platform_data = &nuri_max8997_pdata, - }, -}; - -static struct max17042_platform_data nuri_battery_platform_data = { -}; - -/* GPIO I2C 9 (Fuel Gauge) */ -static struct i2c_gpio_platform_data i2c9_gpio_data = { - .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */ - .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */ -}; -static struct platform_device i2c9_gpio = { - .name = "i2c-gpio", - .id = 9, - .dev = { - .platform_data = &i2c9_gpio_data, - }, -}; -enum { I2C9_MAX17042}; -static struct i2c_board_info i2c9_devs[] __initdata = { - [I2C9_MAX17042] = { - I2C_BOARD_INFO("max17042", 0x36), - .platform_data = &nuri_battery_platform_data, - }, -}; - -/* MAX8903 Secondary Charger */ -static struct regulator_consumer_supply supplies_max8903[] = { - REGULATOR_SUPPLY("vinchg2", "charger-manager.0"), -}; - -static struct regulator_init_data max8903_charger_en_data = { - .constraints = { - .name = "VOUT_CHARGER", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(supplies_max8903), - .consumer_supplies = supplies_max8903, -}; - -static struct fixed_voltage_config max8903_charger_en = { - .supply_name = "VOUT_CHARGER", - .microvolts = 5000000, /* Assume 5VDC */ - .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */ - .enable_high = 0, /* Enable = Low */ - .enabled_at_boot = 1, - .init_data = &max8903_charger_en_data, -}; - -static struct platform_device max8903_fixed_reg_dev = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_MAX8903, - .dev = { .platform_data = &max8903_charger_en }, -}; - -static struct max8903_pdata nuri_max8903 = { - /* - * cen: don't control with the driver, let it be - * controlled by regulator above - */ - .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */ - /* uok, usus: not connected */ - .chg = EXYNOS4_GPE2(0), /* TA_nCHG */ - /* flt: vcc_1.8V_pda */ - .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */ - - .dc_valid = true, - .usb_valid = false, /* USB is not wired to MAX8903 */ -}; - -static struct platform_device nuri_max8903_device = { - .name = "max8903-charger", - .dev = { - .platform_data = &nuri_max8903, - }, -}; - -static void __init nuri_power_init(void) -{ - int gpio; - int ta_en = 0; - - gpio = EXYNOS4_GPX0(7); - gpio_request(gpio, "AP_PMIC_IRQ"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - - gpio = EXYNOS4_GPX2(3); - gpio_request(gpio, "FUEL_ALERT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - - gpio = nuri_max8903.dok; - gpio_request(gpio, "TA_nCONNECTED"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - ta_en = gpio_get_value(gpio) ? 0 : 1; - - gpio = nuri_max8903.chg; - gpio_request(gpio, "TA_nCHG"); - gpio_direction_input(gpio); - - gpio = nuri_max8903.dcm; - gpio_request(gpio, "CURR_ADJ"); - gpio_direction_output(gpio, ta_en); -} - -/* USB EHCI */ -static struct s5p_ehci_platdata nuri_ehci_pdata; - -static void __init nuri_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata; - - s5p_ehci_set_platdata(pdata); -} - -/* USB OTG */ -static struct s3c_hsotg_plat nuri_hsotg_pdata; - -/* CAMERA */ -static struct regulator_consumer_supply cam_vt_cam15_supply = - REGULATOR_SUPPLY("vdd_core", "6-003c"); - -static struct regulator_init_data cam_vt_cam15_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_vt_cam15_supply, -}; - -static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = { - .supply_name = "VT_CAM_1.5V", - .microvolts = 1500000, - .gpio = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */ - .enable_high = 1, - .init_data = &cam_vt_cam15_reg_init_data, -}; - -static struct platform_device cam_vt_cam15_fixed_rdev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V, - .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply cam_vdda_supply[] = { - REGULATOR_SUPPLY("vdda", "6-003c"), - REGULATOR_SUPPLY("a_sensor", "0-001f"), -}; - -static struct regulator_init_data cam_vdda_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply), - .consumer_supplies = cam_vdda_supply, -}; - -static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = { - .supply_name = "CAM_IO_EN", - .microvolts = 2800000, - .gpio = EXYNOS4_GPE2(1), /* CAM_IO_EN */ - .enable_high = 1, - .init_data = &cam_vdda_reg_init_data, -}; - -static struct platform_device cam_vdda_fixed_rdev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V, - .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply camera_8m_12v_supply = - REGULATOR_SUPPLY("dig_12", "0-001f"); - -static struct regulator_init_data cam_8m_12v_reg_init_data = { - .num_consumer_supplies = 1, - .consumer_supplies = &camera_8m_12v_supply, - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS - }, -}; - -static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = { - .supply_name = "8M_1.2V", - .microvolts = 1200000, - .gpio = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */ - .enable_high = 1, - .init_data = &cam_8m_12v_reg_init_data, -}; - -static struct platform_device cam_8m_12v_fixed_rdev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V, - .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg }, -}; - -static struct s5p_platform_mipi_csis mipi_csis_platdata = { - .clk_rate = 166000000UL, - .lanes = 2, - .hs_settle = 12, -}; - -#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */ -#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPL2(5) -#define GPIO_CAM_VT_NSTBY EXYNOS4_GPL2(0) -#define GPIO_CAM_VT_NRST EXYNOS4_GPL2(1) - -static struct s5k6aa_platform_data s5k6aa_pldata = { - .mclk_frequency = 24000000UL, - .gpio_reset = { GPIO_CAM_VT_NRST, 0 }, - .gpio_stby = { GPIO_CAM_VT_NSTBY, 0 }, - .bus_type = V4L2_MBUS_PARALLEL, - .horiz_flip = 1, -}; - -static struct i2c_board_info s5k6aa_board_info = { - I2C_BOARD_INFO("S5K6AA", 0x3c), - .platform_data = &s5k6aa_pldata, -}; - -static struct m5mols_platform_data m5mols_platdata = { - .gpio_reset = GPIO_CAM_MEGA_RST, -}; - -static struct i2c_board_info m5mols_board_info = { - I2C_BOARD_INFO("M5MOLS", 0x1F), - .platform_data = &m5mols_platdata, -}; - -static struct fimc_source_info nuri_camera_sensors[] = { - { - .flags = V4L2_MBUS_PCLK_SAMPLE_RISING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_ITU_601, - .board_info = &s5k6aa_board_info, - .clk_frequency = 24000000UL, - .i2c_bus_num = 6, - }, { - .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_MIPI_CSI2, - .board_info = &m5mols_board_info, - .clk_frequency = 24000000UL, - }, -}; - -static struct s5p_platform_fimc fimc_md_platdata = { - .source_info = nuri_camera_sensors, - .num_clients = ARRAY_SIZE(nuri_camera_sensors), -}; - -static struct gpio nuri_camera_gpios[] = { - { GPIO_CAM_VT_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" }, - { GPIO_CAM_VT_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" }, - { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, - { GPIO_CAM_MEGA_RST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, -}; - -static void __init nuri_camera_init(void) -{ - s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), - &s5p_device_mipi_csis0); - s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata), - &s5p_device_fimc_md); - - if (gpio_request_array(nuri_camera_gpios, - ARRAY_SIZE(nuri_camera_gpios))) { - pr_err("%s: GPIO request failed\n", __func__); - return; - } - - m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT); - if (m5mols_board_info.irq >= 0) - s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF)); - else - pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__); - - /* Free GPIOs controlled directly by the sensor drivers. */ - gpio_free(GPIO_CAM_VT_NRST); - gpio_free(GPIO_CAM_VT_NSTBY); - gpio_free(GPIO_CAM_MEGA_RST); - - if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) { - pr_err("%s: Camera port A setup failed\n", __func__); - return; - } - /* Increase drive strength of the sensor clock output */ - s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4); -} - -static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = { - .frequency = 400000U, - .sda_delay = 200, - .bus_num = 6, -}; - -static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = { - .frequency = 400000U, - .sda_delay = 200, -}; - -/* DEVFREQ controlling memory/bus */ -static struct platform_device exynos4_bus_devfreq = { - .name = "exynos4210-busfreq", -}; - -static struct platform_device *nuri_devices[] __initdata = { - /* Samsung Platform Devices */ - &s3c_device_i2c5, /* PMIC should initialize first */ - &s3c_device_i2c0, - &s3c_device_i2c6, - &emmc_fixed_voltage, - &s5p_device_mipi_csis0, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimd0, - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_wdt, - &s3c_device_timer[0], - &s5p_device_ehci, - &s3c_device_i2c3, - &i2c9_gpio, - &s3c_device_adc, - &s5p_device_g2d, - &s5p_device_jpeg, - &s3c_device_rtc, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &s5p_device_fimc_md, - &s3c_device_usb_hsotg, - - /* NURI Devices */ - &nuri_gpio_keys, - &nuri_lcd_device, - &nuri_backlight_device, - &max8903_fixed_reg_dev, - &nuri_max8903_device, - &cam_vt_cam15_fixed_rdev, - &cam_vdda_fixed_rdev, - &cam_8m_12v_fixed_rdev, - &exynos4_bus_devfreq, -}; - -static void __init nuri_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); - xxti_f = 0; - xusbxti_f = 24000000; -} - -static void __init nuri_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init nuri_machine_init(void) -{ - nuri_sdhci_init(); - nuri_tsp_init(); - nuri_power_init(); - - s3c_i2c0_set_platdata(&nuri_i2c0_platdata); - i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); - s3c_i2c3_set_platdata(&i2c3_data); - i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); - s3c_i2c5_set_platdata(NULL); - i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7)); - i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); - i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3)); - i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs)); - s3c_i2c6_set_platdata(&nuri_i2c6_platdata); - -#ifdef CONFIG_DRM_EXYNOS - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&nuri_fb_pdata); -#endif - - nuri_camera_init(); - - nuri_ehci_init(); - s3c_hsotg_set_platdata(&nuri_hsotg_pdata); - - /* Last */ - platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); -} - -MACHINE_START(NURI, "NURI") - /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = nuri_map_io, - .init_machine = nuri_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &nuri_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c deleted file mode 100644 index 27f03ed5d06..00000000000 --- a/arch/arm/mach-exynos/mach-origen.c +++ /dev/null @@ -1,823 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-origen.c - * - * Copyright (c) 2011 Insignal Co., Ltd. - * http://www.insignal.co.kr/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/serial_core.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/gpio_keys.h> -#include <linux/i2c.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/max8997.h> -#include <linux/lcd.h> -#include <linux/rfkill-gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/usb-ehci-s5p.h> -#include <linux/platform_data/usb-ohci-exynos.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/platform_lcd.h> -#include <video/samsung_fimd.h> - -#include <plat/regs-serial.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/sdhci.h> -#include <plat/clock.h> -#include <plat/gpio-cfg.h> -#include <plat/backlight.h> -#include <plat/fb.h> -#include <plat/mfc.h> -#include <plat/hdmi.h> - -#include <mach/map.h> -#include <mach/irqs.h> - -#include <drm/exynos_drm.h> -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, -}; - -static struct regulator_consumer_supply __initdata ldo3_consumer[] = { - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ - REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */ - REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */ - REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */ -}; -static struct regulator_consumer_supply __initdata ldo6_consumer[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ -}; -static struct regulator_consumer_supply __initdata ldo7_consumer[] = { - REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ -}; -static struct regulator_consumer_supply __initdata ldo8_consumer[] = { - REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */ - REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */ - REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */ -}; -static struct regulator_consumer_supply __initdata ldo9_consumer[] = { - REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ -}; -static struct regulator_consumer_supply __initdata ldo11_consumer[] = { - REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */ -}; -static struct regulator_consumer_supply __initdata ldo14_consumer[] = { - REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ -}; -static struct regulator_consumer_supply __initdata ldo17_consumer[] = { - REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ -}; -static struct regulator_consumer_supply __initdata buck1_consumer[] = { - REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata buck2_consumer[] = { - REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ -}; -static struct regulator_consumer_supply __initdata buck3_consumer[] = { - REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */ -}; -static struct regulator_consumer_supply __initdata buck7_consumer[] = { - REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */ -}; - -static struct regulator_init_data __initdata max8997_ldo1_data = { - .constraints = { - .name = "VDD_ABB_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo2_data = { - .constraints = { - .name = "VDD_ALIVE_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo3_data = { - .constraints = { - .name = "VMIPI_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), - .consumer_supplies = ldo3_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo4_data = { - .constraints = { - .name = "VDD_RTC_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo6_data = { - .constraints = { - .name = "VMIPI_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer), - .consumer_supplies = ldo6_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo7_data = { - .constraints = { - .name = "VDD_AUD_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), - .consumer_supplies = ldo7_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo8_data = { - .constraints = { - .name = "VADC_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), - .consumer_supplies = ldo8_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo9_data = { - .constraints = { - .name = "DVDD_SWB_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer), - .consumer_supplies = ldo9_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo10_data = { - .constraints = { - .name = "VDD_PLL_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_ldo11_data = { - .constraints = { - .name = "VDD_AUD_3V", - .min_uV = 3000000, - .max_uV = 3000000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), - .consumer_supplies = ldo11_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo14_data = { - .constraints = { - .name = "AVDD18_SWB_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), - .consumer_supplies = ldo14_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo17_data = { - .constraints = { - .name = "VDD_SWB_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), - .consumer_supplies = ldo17_consumer, -}; - -static struct regulator_init_data __initdata max8997_ldo21_data = { - .constraints = { - .name = "VDD_MIF_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck1_data = { - .constraints = { - .name = "VDD_ARM_1.2V", - .min_uV = 950000, - .max_uV = 1350000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), - .consumer_supplies = buck1_consumer, -}; - -static struct regulator_init_data __initdata max8997_buck2_data = { - .constraints = { - .name = "VDD_INT_1.1V", - .min_uV = 900000, - .max_uV = 1100000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), - .consumer_supplies = buck2_consumer, -}; - -static struct regulator_init_data __initdata max8997_buck3_data = { - .constraints = { - .name = "VDD_G3D_1.1V", - .min_uV = 900000, - .max_uV = 1100000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck3_consumer), - .consumer_supplies = buck3_consumer, -}; - -static struct regulator_init_data __initdata max8997_buck5_data = { - .constraints = { - .name = "VDDQ_M1M2_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data __initdata max8997_buck7_data = { - .constraints = { - .name = "VDD_LCD_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .boot_on = 1, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1 - }, - }, - .num_consumer_supplies = ARRAY_SIZE(buck7_consumer), - .consumer_supplies = buck7_consumer, -}; - -static struct max8997_regulator_data __initdata origen_max8997_regulators[] = { - { MAX8997_LDO1, &max8997_ldo1_data }, - { MAX8997_LDO2, &max8997_ldo2_data }, - { MAX8997_LDO3, &max8997_ldo3_data }, - { MAX8997_LDO4, &max8997_ldo4_data }, - { MAX8997_LDO6, &max8997_ldo6_data }, - { MAX8997_LDO7, &max8997_ldo7_data }, - { MAX8997_LDO8, &max8997_ldo8_data }, - { MAX8997_LDO9, &max8997_ldo9_data }, - { MAX8997_LDO10, &max8997_ldo10_data }, - { MAX8997_LDO11, &max8997_ldo11_data }, - { MAX8997_LDO14, &max8997_ldo14_data }, - { MAX8997_LDO17, &max8997_ldo17_data }, - { MAX8997_LDO21, &max8997_ldo21_data }, - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, - { MAX8997_BUCK5, &max8997_buck5_data }, - { MAX8997_BUCK7, &max8997_buck7_data }, -}; - -static struct max8997_platform_data __initdata origen_max8997_pdata = { - .num_regulators = ARRAY_SIZE(origen_max8997_regulators), - .regulators = origen_max8997_regulators, - - .wakeup = true, - .buck1_gpiodvs = false, - .buck2_gpiodvs = false, - .buck5_gpiodvs = false, - - .ignore_gpiodvs_side_effect = true, - .buck125_default_idx = 0x0, - - .buck125_gpios[0] = EXYNOS4_GPX0(0), - .buck125_gpios[1] = EXYNOS4_GPX0(1), - .buck125_gpios[2] = EXYNOS4_GPX0(2), - - .buck1_voltage[0] = 1350000, - .buck1_voltage[1] = 1300000, - .buck1_voltage[2] = 1250000, - .buck1_voltage[3] = 1200000, - .buck1_voltage[4] = 1150000, - .buck1_voltage[5] = 1100000, - .buck1_voltage[6] = 1000000, - .buck1_voltage[7] = 950000, - - .buck2_voltage[0] = 1100000, - .buck2_voltage[1] = 1100000, - .buck2_voltage[2] = 1100000, - .buck2_voltage[3] = 1100000, - .buck2_voltage[4] = 1000000, - .buck2_voltage[5] = 1000000, - .buck2_voltage[6] = 1000000, - .buck2_voltage[7] = 1000000, - - .buck5_voltage[0] = 1200000, - .buck5_voltage[1] = 1200000, - .buck5_voltage[2] = 1200000, - .buck5_voltage[3] = 1200000, - .buck5_voltage[4] = 1200000, - .buck5_voltage[5] = 1200000, - .buck5_voltage[6] = 1200000, - .buck5_voltage[7] = 1200000, -}; - -/* I2C0 */ -static struct i2c_board_info i2c0_devs[] __initdata = { - { - I2C_BOARD_INFO("max8997", (0xCC >> 1)), - .platform_data = &origen_max8997_pdata, - .irq = IRQ_EINT(4), - }, -}; - -static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -}; - -static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -}; - -/* USB EHCI */ -static struct s5p_ehci_platdata origen_ehci_pdata; - -static void __init origen_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &origen_ehci_pdata; - - s5p_ehci_set_platdata(pdata); -} - -/* USB OHCI */ -static struct exynos4_ohci_platdata origen_ohci_pdata; - -static void __init origen_ohci_init(void) -{ - struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata; - - exynos4_ohci_set_platdata(pdata); -} - -/* USB OTG */ -static struct s3c_hsotg_plat origen_hsotg_pdata; - -static struct gpio_led origen_gpio_leds[] = { - { - .name = "origen::status1", - .default_trigger = "heartbeat", - .gpio = EXYNOS4_GPX1(3), - .active_low = 1, - }, - { - .name = "origen::status2", - .default_trigger = "mmc0", - .gpio = EXYNOS4_GPX1(4), - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data origen_gpio_led_info = { - .leds = origen_gpio_leds, - .num_leds = ARRAY_SIZE(origen_gpio_leds), -}; - -static struct platform_device origen_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &origen_gpio_led_info, - }, -}; - -static struct gpio_keys_button origen_gpio_keys_table[] = { - { - .code = KEY_MENU, - .gpio = EXYNOS4_GPX1(5), - .desc = "gpio-keys: KEY_MENU", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_HOME, - .gpio = EXYNOS4_GPX1(6), - .desc = "gpio-keys: KEY_HOME", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_BACK, - .gpio = EXYNOS4_GPX1(7), - .desc = "gpio-keys: KEY_BACK", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_UP, - .gpio = EXYNOS4_GPX2(0), - .desc = "gpio-keys: KEY_UP", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, { - .code = KEY_DOWN, - .gpio = EXYNOS4_GPX2(1), - .desc = "gpio-keys: KEY_DOWN", - .type = EV_KEY, - .active_low = 1, - .wakeup = 1, - .debounce_interval = 1, - }, -}; - -static struct gpio_keys_platform_data origen_gpio_keys_data = { - .buttons = origen_gpio_keys_table, - .nbuttons = ARRAY_SIZE(origen_gpio_keys_table), -}; - -static struct platform_device origen_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &origen_gpio_keys_data, - }, -}; - -static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) -{ - int ret; - - if (power) - ret = gpio_request_one(EXYNOS4_GPE3(4), - GPIOF_OUT_INIT_HIGH, "GPE3_4"); - else - ret = gpio_request_one(EXYNOS4_GPE3(4), - GPIOF_OUT_INIT_LOW, "GPE3_4"); - - gpio_free(EXYNOS4_GPE3(4)); - - if (ret) - pr_err("failed to request gpio for LCD power: %d\n", ret); -} - -static struct plat_lcd_data origen_lcd_hv070wsa_data = { - .set_power = lcd_hv070wsa_set_power, -}; - -static struct platform_device origen_lcd_hv070wsa = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &origen_lcd_hv070wsa_data, -}; - -static struct pwm_lookup origen_pwm_lookup[] = { - PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL), -}; - -#ifdef CONFIG_DRM_EXYNOS_FIMD -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 64, - .right_margin = 16, - .upper_margin = 64, - .lower_margin = 16, - .hsync_len = 48, - .vsync_len = 3, - .xres = 1024, - .yres = 600, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | - VIDCON1_INV_VCLK, - .default_win = 0, - .bpp = 32, -}; -#else -static struct s3c_fb_pd_win origen_fb_win0 = { - .xres = 1024, - .yres = 600, - .max_bpp = 32, - .default_bpp = 24, - .virtual_x = 1024, - .virtual_y = 2 * 600, -}; - -static struct fb_videomode origen_lcd_timing = { - .left_margin = 64, - .right_margin = 16, - .upper_margin = 64, - .lower_margin = 16, - .hsync_len = 48, - .vsync_len = 3, - .xres = 1024, - .yres = 600, -}; - -static struct s3c_fb_platdata origen_lcd_pdata __initdata = { - .win[0] = &origen_fb_win0, - .vtiming = &origen_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | - VIDCON1_INV_VCLK, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -/* Bluetooth rfkill gpio platform data */ -static struct rfkill_gpio_platform_data origen_bt_pdata = { - .reset_gpio = EXYNOS4_GPX2(2), - .shutdown_gpio = -1, - .type = RFKILL_TYPE_BLUETOOTH, - .name = "origen-bt", -}; - -/* Bluetooth Platform device */ -static struct platform_device origen_device_bluetooth = { - .name = "rfkill_gpio", - .id = -1, - .dev = { - .platform_data = &origen_bt_pdata, - }, -}; - -static struct platform_device *origen_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_hsmmc0, - &s3c_device_i2c0, - &s3c_device_rtc, - &s3c_device_usb_hsotg, - &s3c_device_wdt, - &s5p_device_ehci, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimc_md, - &s5p_device_fimd0, - &s5p_device_g2d, - &s5p_device_hdmi, - &s5p_device_i2c_hdmiphy, - &s5p_device_jpeg, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &s5p_device_mixer, - &exynos4_device_ohci, - &origen_device_gpiokeys, - &origen_lcd_hv070wsa, - &origen_leds_gpio, - &origen_device_bluetooth, -}; - -/* LCD Backlight data */ -static struct samsung_bl_gpio_info origen_bl_gpio_info = { - .no = EXYNOS4_GPD0(0), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data origen_bl_data = { - .pwm_id = 0, - .pwm_period_ns = 1000, -}; - -static void __init origen_bt_setup(void) -{ - gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART"); - /* 4 UART Pins configuration */ - s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2)); - /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */ - s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); -} - -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - -static void s5p_tv_setup(void) -{ - /* Direct HPD to HDMI chip */ - gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); -} - -static void __init origen_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); - xxti_f = 0; - xusbxti_f = 24000000; -} - -static void __init origen_power_init(void) -{ - gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ"); - s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE); -} - -static void __init origen_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init origen_machine_init(void) -{ - origen_power_init(); - - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); - - /* - * Since sdhci instance 2 can contain a bootable media, - * sdhci instance 0 is registered after instance 2. - */ - s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); - s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); - - origen_ehci_init(); - origen_ohci_init(); - s3c_hsotg_set_platdata(&origen_hsotg_pdata); - - s5p_tv_setup(); - s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); - -#ifdef CONFIG_DRM_EXYNOS_FIMD - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&origen_lcd_pdata); -#endif - - platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); - - pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup)); - samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); - - origen_bt_setup(); -} - -MACHINE_START(ORIGEN, "ORIGEN") - /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = origen_map_io, - .init_machine = origen_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &origen_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c deleted file mode 100644 index 2c8af961792..00000000000 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/mach-smdk4x12.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/lcd.h> -#include <linux/mfd/max8997.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/regulator/machine.h> -#include <linux/serial_core.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/s3c-hsotg.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/samsung_fimd.h> -#include <plat/backlight.h> -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <plat/keypad.h> -#include <plat/mfc.h> -#include <plat/regs-serial.h> -#include <plat/sdhci.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <drm/exynos_drm.h> -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDK4X12_UCON_DEFAULT, - .ulcon = SMDK4X12_ULCON_DEFAULT, - .ufcon = SMDK4X12_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -}; - -static struct regulator_consumer_supply max8997_buck1 = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_consumer_supply max8997_buck2 = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply max8997_buck3 = - REGULATOR_SUPPLY("vdd_g3d", NULL); - -static struct regulator_init_data max8997_buck1_data = { - .constraints = { - .name = "VDD_ARM_SMDK4X12", - .min_uV = 925000, - .max_uV = 1350000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck1, -}; - -static struct regulator_init_data max8997_buck2_data = { - .constraints = { - .name = "VDD_INT_SMDK4X12", - .min_uV = 950000, - .max_uV = 1150000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck2, -}; - -static struct regulator_init_data max8997_buck3_data = { - .constraints = { - .name = "VDD_G3D_SMDK4X12", - .min_uV = 950000, - .max_uV = 1150000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck3, -}; - -static struct max8997_regulator_data smdk4x12_max8997_regulators[] = { - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, -}; - -static struct max8997_platform_data smdk4x12_max8997_pdata = { - .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators), - .regulators = smdk4x12_max8997_regulators, - - .buck1_voltage[0] = 1100000, /* 1.1V */ - .buck1_voltage[1] = 1100000, /* 1.1V */ - .buck1_voltage[2] = 1100000, /* 1.1V */ - .buck1_voltage[3] = 1100000, /* 1.1V */ - .buck1_voltage[4] = 1100000, /* 1.1V */ - .buck1_voltage[5] = 1100000, /* 1.1V */ - .buck1_voltage[6] = 1000000, /* 1.0V */ - .buck1_voltage[7] = 950000, /* 0.95V */ - - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1000000, /* 1.0V */ - .buck2_voltage[2] = 950000, /* 0.95V */ - .buck2_voltage[3] = 900000, /* 0.9V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1000000, /* 1.0V */ - .buck2_voltage[6] = 950000, /* 0.95V */ - .buck2_voltage[7] = 900000, /* 0.9V */ - - .buck5_voltage[0] = 1100000, /* 1.1V */ - .buck5_voltage[1] = 1100000, /* 1.1V */ - .buck5_voltage[2] = 1100000, /* 1.1V */ - .buck5_voltage[3] = 1100000, /* 1.1V */ - .buck5_voltage[4] = 1100000, /* 1.1V */ - .buck5_voltage[5] = 1100000, /* 1.1V */ - .buck5_voltage[6] = 1100000, /* 1.1V */ - .buck5_voltage[7] = 1100000, /* 1.1V */ -}; - -static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = { - { - I2C_BOARD_INFO("max8997", 0x66), - .platform_data = &smdk4x12_max8997_pdata, - } -}; - -static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = { - { I2C_BOARD_INFO("wm8994", 0x1a), } -}; - -static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = { - /* nothing here yet */ -}; - -static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = { - /* nothing here yet */ -}; - -static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = { - .no = EXYNOS4_GPD0(1), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdk4x12_bl_data = { - .pwm_id = 1, - .pwm_period_ns = 1000, -}; - -static struct pwm_lookup smdk4x12_pwm_lookup[] = { - PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL), -}; - -static uint32_t smdk4x12_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3), - KEY(1, 6, KEY_4), KEY(1, 7, KEY_5), - KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B), - KEY(0, 7, KEY_E), KEY(0, 5, KEY_C) -}; - -static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { - .keymap = smdk4x12_keymap, - .keymap_size = ARRAY_SIZE(smdk4x12_keymap), -}; - -static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = { - .keymap_data = &smdk4x12_keymap_data, - .rows = 3, - .cols = 8, -}; - -#ifdef CONFIG_DRM_EXYNOS_FIMD -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 8, - .right_margin = 8, - .upper_margin = 6, - .lower_margin = 6, - .hsync_len = 6, - .vsync_len = 4, - .xres = 480, - .yres = 800, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 0, - .bpp = 32, -}; -#else -static struct s3c_fb_pd_win smdk4x12_fb_win0 = { - .xres = 480, - .yres = 800, - .virtual_x = 480, - .virtual_y = 800 * 2, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct fb_videomode smdk4x12_lcd_timing = { - .left_margin = 8, - .right_margin = 8, - .upper_margin = 6, - .lower_margin = 6, - .hsync_len = 6, - .vsync_len = 4, - .xres = 480, - .yres = 800, -}; - -static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = { - .win[0] = &smdk4x12_fb_win0, - .vtiming = &smdk4x12_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -/* USB OTG */ -static struct s3c_hsotg_plat smdk4x12_hsotg_pdata; - -static struct platform_device *smdk4x12_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c0, - &s3c_device_i2c1, - &s3c_device_i2c3, - &s3c_device_i2c7, - &s3c_device_rtc, - &s3c_device_usb_hsotg, - &s3c_device_wdt, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimc_md, - &s5p_device_fimd0, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &samsung_device_keypad, -}; - -static void __init smdk4x12_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); -} - -static void __init smdk4x12_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init smdk4x12_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, smdk4x12_i2c_devs0, - ARRAY_SIZE(smdk4x12_i2c_devs0)); - - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, smdk4x12_i2c_devs1, - ARRAY_SIZE(smdk4x12_i2c_devs1)); - - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, smdk4x12_i2c_devs3, - ARRAY_SIZE(smdk4x12_i2c_devs3)); - - s3c_i2c7_set_platdata(NULL); - i2c_register_board_info(7, smdk4x12_i2c_devs7, - ARRAY_SIZE(smdk4x12_i2c_devs7)); - - samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data); - pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup)); - - samsung_keypad_set_platdata(&smdk4x12_keypad_data); - - s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata); - - s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata); - -#ifdef CONFIG_DRM_EXYNOS_FIMD - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata); -#endif - - platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices)); -} - -MACHINE_START(SMDK4212, "SMDK4212") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdk4x12_map_io, - .init_machine = smdk4x12_machine_init, - .init_time = exynos_init_time, - .restart = exynos4_restart, - .reserve = &smdk4x12_reserve, -MACHINE_END - -MACHINE_START(SMDK4412, "SMDK4412") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdk4x12_map_io, - .init_machine = smdk4x12_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .restart = exynos4_restart, - .reserve = &smdk4x12_reserve, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c deleted file mode 100644 index d95b8cf8525..00000000000 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ /dev/null @@ -1,444 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-smdkv310.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/serial_core.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/lcd.h> -#include <linux/mmc/host.h> -#include <linux/platform_device.h> -#include <linux/smsc911x.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/input.h> -#include <linux/pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <linux/platform_data/usb-ehci-s5p.h> -#include <linux/platform_data/usb-ohci-exynos.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/platform_lcd.h> -#include <video/samsung_fimd.h> -#include <plat/regs-serial.h> -#include <plat/regs-srom.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/keypad.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> -#include <plat/backlight.h> -#include <plat/mfc.h> -#include <plat/clock.h> -#include <plat/hdmi.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <drm/exynos_drm.h> -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDKV310_UCON_DEFAULT, - .ulcon = SMDKV310_ULCON_DEFAULT, - .ufcon = SMDKV310_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK0(2), - .ext_cd_gpio_invert = 1, -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK2(2), - .ext_cd_gpio_invert = 1, -}; - -static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0"); - gpio_free(EXYNOS4_GPD0(1)); -#endif - /* fire nRESET on power up */ - gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0"); - mdelay(100); - - gpio_set_value(EXYNOS4_GPX0(6), 0); - mdelay(10); - - gpio_set_value(EXYNOS4_GPX0(6), 1); - mdelay(10); - - gpio_free(EXYNOS4_GPX0(6)); - } else { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0"); - gpio_free(EXYNOS4_GPD0(1)); -#endif - } -} - -static struct plat_lcd_data smdkv310_lcd_lte480wv_data = { - .set_power = lcd_lte480wv_set_power, -}; - -static struct platform_device smdkv310_lcd_lte480wv = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &smdkv310_lcd_lte480wv_data, -}; - -#ifdef CONFIG_DRM_EXYNOS_FIMD -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 13, - .right_margin = 8, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 0, - .bpp = 32, -}; -#else -static struct s3c_fb_pd_win smdkv310_fb_win0 = { - .max_bpp = 32, - .default_bpp = 24, - .xres = 800, - .yres = 480, -}; - -static struct fb_videomode smdkv310_lcd_timing = { - .left_margin = 13, - .right_margin = 8, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, -}; - -static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = { - .win[0] = &smdkv310_fb_win0, - .vtiming = &smdkv310_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -static struct resource smdkv310_smsc911x_resources[] = { - [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K), - [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \ - | IRQF_TRIGGER_LOW), -}; - -static struct smsc911x_platform_config smsc9215_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, - .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, -}; - -static struct platform_device smdkv310_smsc911x = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources), - .resource = smdkv310_smsc911x_resources, - .dev = { - .platform_data = &smsc9215_config, - }, -}; - -static uint32_t smdkv310_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), - KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), - KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), - KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) -}; - -static struct matrix_keymap_data smdkv310_keymap_data __initdata = { - .keymap = smdkv310_keymap, - .keymap_size = ARRAY_SIZE(smdkv310_keymap), -}; - -static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = { - .keymap_data = &smdkv310_keymap_data, - .rows = 2, - .cols = 8, -}; - -static struct i2c_board_info i2c_devs1[] __initdata = { - {I2C_BOARD_INFO("wm8994", 0x1a),}, -}; - -/* USB EHCI */ -static struct s5p_ehci_platdata smdkv310_ehci_pdata; - -static void __init smdkv310_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata; - - s5p_ehci_set_platdata(pdata); -} - -/* USB OHCI */ -static struct exynos4_ohci_platdata smdkv310_ohci_pdata; - -static void __init smdkv310_ohci_init(void) -{ - struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata; - - exynos4_ohci_set_platdata(pdata); -} - -/* USB OTG */ -static struct s3c_hsotg_plat smdkv310_hsotg_pdata; - -/* Audio device */ -static struct platform_device smdkv310_device_audio = { - .name = "smdk-audio", - .id = -1, -}; - -static struct platform_device *smdkv310_devices[] __initdata = { - &s3c_device_hsmmc0, - &s3c_device_hsmmc1, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c1, - &s5p_device_i2c_hdmiphy, - &s3c_device_rtc, - &s3c_device_usb_hsotg, - &s3c_device_wdt, - &s5p_device_ehci, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_fimc_md, - &s5p_device_g2d, - &s5p_device_jpeg, - &exynos4_device_ac97, - &exynos4_device_i2s0, - &exynos4_device_ohci, - &samsung_device_keypad, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &exynos4_device_spdif, - &samsung_asoc_idma, - &s5p_device_fimd0, - &smdkv310_device_audio, - &smdkv310_lcd_lte480wv, - &smdkv310_smsc911x, - &exynos4_device_ahci, - &s5p_device_hdmi, - &s5p_device_mixer, -}; - -static void __init smdkv310_smsc911x_init(void) -{ - u32 cs1; - - /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5P_SROM_BW) & - ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << - S5P_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5P_SROM_BW); - - /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | - (0x9 << S5P_SROM_BCX__TACP__SHIFT) | - (0xc << S5P_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5P_SROM_BCX__TACC__SHIFT) | - (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); -} - -/* LCD Backlight data */ -static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = { - .no = EXYNOS4_GPD0(1), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdkv310_bl_data = { - .pwm_id = 1, - .pwm_period_ns = 1000, -}; - -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - -static struct pwm_lookup smdkv310_pwm_lookup[] = { - PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL), -}; - -static void s5p_tv_setup(void) -{ - /* direct HPD to HDMI chip */ - WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); -} - -static void __init smdkv310_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); - xxti_f = 12000000; - xusbxti_f = 24000000; -} - -static void __init smdkv310_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init smdkv310_machine_init(void) -{ - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); - - smdkv310_smsc911x_init(); - - s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); - s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata); - s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); - - s5p_tv_setup(); - s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); - - samsung_keypad_set_platdata(&smdkv310_keypad_data); - - samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); - pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup)); - -#ifdef CONFIG_DRM_EXYNOS_FIMD - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); -#endif - - smdkv310_ehci_init(); - smdkv310_ohci_init(); - s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata); - - platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); -} - -MACHINE_START(SMDKV310, "SMDKV310") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdkv310_map_io, - .init_machine = smdkv310_machine_init, - .init_time = exynos_init_time, - .reserve = &smdkv310_reserve, - .restart = exynos4_restart, -MACHINE_END - -MACHINE_START(SMDKC210, "SMDKC210") - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = smdkv310_map_io, - .init_machine = smdkv310_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &smdkv310_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c deleted file mode 100644 index 74ddb2b5561..00000000000 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ /dev/null @@ -1,1159 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-universal_c210.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/gpio_keys.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/fb.h> -#include <linux/mfd/max8998.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/max8952.h> -#include <linux/mmc/host.h> -#include <linux/i2c-gpio.h> -#include <linux/i2c/mcs.h> -#include <linux/i2c/atmel_mxt_ts.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <linux/platform_data/mipi-csis.h> -#include <linux/platform_data/s3c-hsotg.h> -#include <drm/exynos_drm.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <video/samsung_fimd.h> -#include <plat/regs-serial.h> -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/fb.h> -#include <plat/mfc.h> -#include <plat/sdhci.h> -#include <plat/fimc-core.h> -#include <plat/camport.h> - -#include <mach/map.h> - -#include <media/v4l2-mediabus.h> -#include <media/s5p_fimc.h> -#include <media/m5mols.h> -#include <media/s5k6aa.h> - -#include "common.h" - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG256 | \ - S5PV210_UFCON_RXTRIG256) - -static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .ucon = UNIVERSAL_UCON_DEFAULT, - .ulcon = UNIVERSAL_ULCON_DEFAULT, - .ufcon = UNIVERSAL_UFCON_DEFAULT, - }, -}; - -static struct regulator_consumer_supply max8952_consumer = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_init_data universal_max8952_reg_data = { - .constraints = { - .name = "VARM_1.2V", - .min_uV = 770000, - .max_uV = 1400000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8952_consumer, -}; - -static struct max8952_platform_data universal_max8952_pdata __initdata = { - .gpio_vid0 = EXYNOS4_GPX0(3), - .gpio_vid1 = EXYNOS4_GPX0(4), - .gpio_en = -1, /* Not controllable, set "Always High" */ - .default_mode = 0, /* vid0 = 0, vid1 = 0 */ - .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */ - .sync_freq = 0, /* default: fastest */ - .ramp_speed = 0, /* default: fastest */ - .reg_data = &universal_max8952_reg_data, -}; - -static struct regulator_consumer_supply lp3974_buck1_consumer = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply lp3974_buck2_consumer = - REGULATOR_SUPPLY("vddg3d", NULL); - -static struct regulator_consumer_supply lp3974_buck3_consumer[] = { - REGULATOR_SUPPLY("vdet", "s5p-sdo"), - REGULATOR_SUPPLY("vdd_reg", "0-003c"), -}; - -static struct regulator_init_data lp3974_buck1_data = { - .constraints = { - .name = "VINT_1.1V", - .min_uV = 750000, - .max_uV = 1500000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_buck1_consumer, -}; - -static struct regulator_init_data lp3974_buck2_data = { - .constraints = { - .name = "VG3D_1.1V", - .min_uV = 750000, - .max_uV = 1500000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_buck2_consumer, -}; - -static struct regulator_init_data lp3974_buck3_data = { - .constraints = { - .name = "VCC_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer), - .consumer_supplies = lp3974_buck3_consumer, -}; - -static struct regulator_init_data lp3974_buck4_data = { - .constraints = { - .name = "VMEM_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_ldo2_data = { - .constraints = { - .name = "VALIVE_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo3_consumer[] = { - REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), - REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), - REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), -}; - -static struct regulator_init_data lp3974_ldo3_data = { - .constraints = { - .name = "VUSB+MIPI_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer), - .consumer_supplies = lp3974_ldo3_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo4_consumer[] = { - REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), -}; - -static struct regulator_init_data lp3974_ldo4_data = { - .constraints = { - .name = "VADC_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer), - .consumer_supplies = lp3974_ldo4_consumer, -}; - -static struct regulator_init_data lp3974_ldo5_data = { - .constraints = { - .name = "VTF_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_ldo6_data = { - .constraints = { - .name = "LDO6", - .min_uV = 2000000, - .max_uV = 2000000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo7_consumer[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), -}; - -static struct regulator_init_data lp3974_ldo7_data = { - .constraints = { - .name = "VLCD+VMIPI_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer), - .consumer_supplies = lp3974_ldo7_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo8_consumer[] = { - REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), - REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"), -}; - -static struct regulator_init_data lp3974_ldo8_data = { - .constraints = { - .name = "VUSB+VDAC_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer), - .consumer_supplies = lp3974_ldo8_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo9_consumer = - REGULATOR_SUPPLY("vddio", "0-003c"); - -static struct regulator_init_data lp3974_ldo9_data = { - .constraints = { - .name = "VCC_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo9_consumer, -}; - -static struct regulator_init_data lp3974_ldo10_data = { - .constraints = { - .name = "VPLL_1.1V", - .min_uV = 1100000, - .max_uV = 1100000, - .boot_on = 1, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo11_consumer = - REGULATOR_SUPPLY("dig_28", "0-001f"); - -static struct regulator_init_data lp3974_ldo11_data = { - .constraints = { - .name = "CAM_AF_3.3V", - .min_uV = 3300000, - .max_uV = 3300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo11_consumer, -}; - -static struct regulator_init_data lp3974_ldo12_data = { - .constraints = { - .name = "PS_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_ldo13_data = { - .constraints = { - .name = "VHIC_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_consumer_supply lp3974_ldo14_consumer = - REGULATOR_SUPPLY("dig_18", "0-001f"); - -static struct regulator_init_data lp3974_ldo14_data = { - .constraints = { - .name = "CAM_I_HOST_1.8V", - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo14_consumer, -}; - - -static struct regulator_consumer_supply lp3974_ldo15_consumer = - REGULATOR_SUPPLY("dig_12", "0-001f"); - -static struct regulator_init_data lp3974_ldo15_data = { - .constraints = { - .name = "CAM_S_DIG+FM33_CORE_1.2V", - .min_uV = 1200000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &lp3974_ldo15_consumer, -}; - -static struct regulator_consumer_supply lp3974_ldo16_consumer[] = { - REGULATOR_SUPPLY("vdda", "0-003c"), - REGULATOR_SUPPLY("a_sensor", "0-001f"), -}; - -static struct regulator_init_data lp3974_ldo16_data = { - .constraints = { - .name = "CAM_S_ANA_2.8V", - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer), - .consumer_supplies = lp3974_ldo16_consumer, -}; - -static struct regulator_init_data lp3974_ldo17_data = { - .constraints = { - .name = "VCC_3.0V_LCD", - .min_uV = 3000000, - .max_uV = 3000000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_32khz_ap_data = { - .constraints = { - .name = "32KHz AP", - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_32khz_cp_data = { - .constraints = { - .name = "32KHz CP", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_vichg_data = { - .constraints = { - .name = "VICHG", - .state_mem = { - .disabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_esafeout1_data = { - .constraints = { - .name = "SAFEOUT1", - .min_uV = 4800000, - .max_uV = 4800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .always_on = 1, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct regulator_init_data lp3974_esafeout2_data = { - .constraints = { - .name = "SAFEOUT2", - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .enabled = 1, - }, - }, -}; - -static struct max8998_regulator_data lp3974_regulators[] = { - { MAX8998_LDO2, &lp3974_ldo2_data }, - { MAX8998_LDO3, &lp3974_ldo3_data }, - { MAX8998_LDO4, &lp3974_ldo4_data }, - { MAX8998_LDO5, &lp3974_ldo5_data }, - { MAX8998_LDO6, &lp3974_ldo6_data }, - { MAX8998_LDO7, &lp3974_ldo7_data }, - { MAX8998_LDO8, &lp3974_ldo8_data }, - { MAX8998_LDO9, &lp3974_ldo9_data }, - { MAX8998_LDO10, &lp3974_ldo10_data }, - { MAX8998_LDO11, &lp3974_ldo11_data }, - { MAX8998_LDO12, &lp3974_ldo12_data }, - { MAX8998_LDO13, &lp3974_ldo13_data }, - { MAX8998_LDO14, &lp3974_ldo14_data }, - { MAX8998_LDO15, &lp3974_ldo15_data }, - { MAX8998_LDO16, &lp3974_ldo16_data }, - { MAX8998_LDO17, &lp3974_ldo17_data }, - { MAX8998_BUCK1, &lp3974_buck1_data }, - { MAX8998_BUCK2, &lp3974_buck2_data }, - { MAX8998_BUCK3, &lp3974_buck3_data }, - { MAX8998_BUCK4, &lp3974_buck4_data }, - { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data }, - { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data }, - { MAX8998_ENVICHG, &lp3974_vichg_data }, - { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data }, - { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data }, -}; - -static struct max8998_platform_data universal_lp3974_pdata = { - .num_regulators = ARRAY_SIZE(lp3974_regulators), - .regulators = lp3974_regulators, - .buck1_voltage1 = 1100000, /* INT */ - .buck1_voltage2 = 1000000, - .buck1_voltage3 = 1100000, - .buck1_voltage4 = 1000000, - .buck1_set1 = EXYNOS4_GPX0(5), - .buck1_set2 = EXYNOS4_GPX0(6), - .buck2_voltage1 = 1200000, /* G3D */ - .buck2_voltage2 = 1100000, - .buck1_default_idx = 0, - .buck2_set3 = EXYNOS4_GPE2(0), - .buck2_default_idx = 0, - .wakeup = true, -}; - - -enum fixed_regulator_id { - FIXED_REG_ID_MMC0, - FIXED_REG_ID_HDMI_5V, - FIXED_REG_ID_CAM_S_IF, - FIXED_REG_ID_CAM_I_CORE, - FIXED_REG_ID_CAM_VT_DIO, -}; - -static struct regulator_consumer_supply hdmi_fixed_consumer = - REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi"); - -static struct regulator_init_data hdmi_fixed_voltage_init_data = { - .constraints = { - .name = "HDMI_5V", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &hdmi_fixed_consumer, -}; - -static struct fixed_voltage_config hdmi_fixed_voltage_config = { - .supply_name = "HDMI_EN1", - .microvolts = 5000000, - .gpio = EXYNOS4_GPE0(1), - .enable_high = true, - .init_data = &hdmi_fixed_voltage_init_data, -}; - -static struct platform_device hdmi_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_HDMI_5V, - .dev = { - .platform_data = &hdmi_fixed_voltage_config, - }, -}; - -/* GPIO I2C 5 (PMIC) */ -static struct i2c_board_info i2c5_devs[] __initdata = { - { - I2C_BOARD_INFO("max8952", 0xC0 >> 1), - .platform_data = &universal_max8952_pdata, - }, { - I2C_BOARD_INFO("lp3974", 0xCC >> 1), - .platform_data = &universal_lp3974_pdata, - }, -}; - -/* I2C3 (TSP) */ -static struct mxt_platform_data qt602240_platform_data = { - .x_line = 19, - .y_line = 11, - .x_size = 800, - .y_size = 480, - .blen = 0x11, - .threshold = 0x28, - .voltage = 2800000, /* 2.8V */ - .orient = MXT_DIAGONAL, - .irqflags = IRQF_TRIGGER_FALLING, -}; - -static struct i2c_board_info i2c3_devs[] __initdata = { - { - I2C_BOARD_INFO("qt602240_ts", 0x4a), - .platform_data = &qt602240_platform_data, - }, -}; - -static void __init universal_tsp_init(void) -{ - int gpio; - - /* TSP_LDO_ON: XMDMADDR_11 */ - gpio = EXYNOS4_GPE2(3); - gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON"); - gpio_export(gpio, 0); - - /* TSP_INT: XMDMADDR_7 */ - gpio = EXYNOS4_GPE1(7); - gpio_request(gpio, "TSP_INT"); - - s5p_register_gpio_interrupt(gpio); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - i2c3_devs[0].irq = gpio_to_irq(gpio); -} - - -/* GPIO I2C 12 (3 Touchkey) */ -static uint32_t touchkey_keymap[] = { - /* MCS_KEY_MAP(value, keycode) */ - MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */ - MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */ -}; - -static struct mcs_platform_data touchkey_data = { - .keymap = touchkey_keymap, - .keymap_size = ARRAY_SIZE(touchkey_keymap), - .key_maxval = 2, -}; - -/* GPIO I2C 3_TOUCH 2.8V */ -#define I2C_GPIO_BUS_12 12 -static struct i2c_gpio_platform_data i2c_gpio12_data = { - .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */ - .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */ -}; - -static struct platform_device i2c_gpio12 = { - .name = "i2c-gpio", - .id = I2C_GPIO_BUS_12, - .dev = { - .platform_data = &i2c_gpio12_data, - }, -}; - -static struct i2c_board_info i2c_gpio12_devs[] __initdata = { - { - I2C_BOARD_INFO("mcs5080_touchkey", 0x20), - .platform_data = &touchkey_data, - }, -}; - -static void __init universal_touchkey_init(void) -{ - int gpio; - - gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */ - gpio_request(gpio, "3_TOUCH_INT"); - s5p_register_gpio_interrupt(gpio); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); - - gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ - gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN"); -} - -static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = { - .frequency = 300 * 1000, - .sda_delay = 200, -}; - -/* GPIO KEYS */ -static struct gpio_keys_button universal_gpio_keys_tables[] = { - { - .code = KEY_VOLUMEUP, - .gpio = EXYNOS4_GPX2(0), /* XEINT16 */ - .desc = "gpio-keys: KEY_VOLUMEUP", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_VOLUMEDOWN, - .gpio = EXYNOS4_GPX2(1), /* XEINT17 */ - .desc = "gpio-keys: KEY_VOLUMEDOWN", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_CONFIG, - .gpio = EXYNOS4_GPX2(2), /* XEINT18 */ - .desc = "gpio-keys: KEY_CONFIG", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_CAMERA, - .gpio = EXYNOS4_GPX2(3), /* XEINT19 */ - .desc = "gpio-keys: KEY_CAMERA", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, { - .code = KEY_OK, - .gpio = EXYNOS4_GPX3(5), /* XEINT29 */ - .desc = "gpio-keys: KEY_OK", - .type = EV_KEY, - .active_low = 1, - .debounce_interval = 1, - }, -}; - -static struct gpio_keys_platform_data universal_gpio_keys_data = { - .buttons = universal_gpio_keys_tables, - .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables), -}; - -static struct platform_device universal_gpio_keys = { - .name = "gpio-keys", - .dev = { - .platform_data = &universal_gpio_keys_data, - }, -}; - -/* eMMC */ -static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { - .max_width = 8, - .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .cd_type = S3C_SDHCI_CD_PERMANENT, -}; - -static struct regulator_consumer_supply mmc0_supplies[] = { - REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"), -}; - -static struct regulator_init_data mmc0_fixed_voltage_init_data = { - .constraints = { - .name = "VMEM_VDD_2.8V", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies), - .consumer_supplies = mmc0_supplies, -}; - -static struct fixed_voltage_config mmc0_fixed_voltage_config = { - .supply_name = "MASSMEMORY_EN", - .microvolts = 2800000, - .gpio = EXYNOS4_GPE1(3), - .enable_high = true, - .init_data = &mmc0_fixed_voltage_init_data, -}; - -static struct platform_device mmc0_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = FIXED_REG_ID_MMC0, - .dev = { - .platform_data = &mmc0_fixed_voltage_config, - }, -}; - -/* SD */ -static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */ - .ext_cd_gpio_invert = 1, - .cd_type = S3C_SDHCI_CD_GPIO, -}; - -/* WiFi */ -static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = { - .max_width = 4, - .host_caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, - .cd_type = S3C_SDHCI_CD_EXTERNAL, -}; - -static void __init universal_sdhci_init(void) -{ - s3c_sdhci0_set_platdata(&universal_hsmmc0_data); - s3c_sdhci2_set_platdata(&universal_hsmmc2_data); - s3c_sdhci3_set_platdata(&universal_hsmmc3_data); -} - -/* I2C1 */ -static struct i2c_board_info i2c1_devs[] __initdata = { - /* Gyro, To be updated */ -}; - -#ifdef CONFIG_DRM_EXYNOS -static struct exynos_drm_fimd_pdata drm_fimd_pdata = { - .panel = { - .timing = { - .left_margin = 16, - .right_margin = 16, - .upper_margin = 2, - .lower_margin = 28, - .hsync_len = 2, - .vsync_len = 1, - .xres = 480, - .yres = 800, - .refresh = 55, - }, - }, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN - | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .default_win = 3, - .bpp = 32, -}; -#else -/* Frame Buffer */ -static struct s3c_fb_pd_win universal_fb_win0 = { - .max_bpp = 32, - .default_bpp = 16, - .xres = 480, - .yres = 800, - .virtual_x = 480, - .virtual_y = 2 * 800, -}; - -static struct fb_videomode universal_lcd_timing = { - .left_margin = 16, - .right_margin = 16, - .upper_margin = 2, - .lower_margin = 28, - .hsync_len = 2, - .vsync_len = 1, - .xres = 480, - .yres = 800, - .refresh = 55, -}; - -static struct s3c_fb_platdata universal_lcd_pdata __initdata = { - .win[0] = &universal_fb_win0, - .vtiming = &universal_lcd_timing, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | - VIDCON0_CLKSEL_LCD, - .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN - | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - -static struct regulator_consumer_supply cam_vt_dio_supply = - REGULATOR_SUPPLY("vdd_core", "0-003c"); - -static struct regulator_init_data cam_vt_dio_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_vt_dio_supply, -}; - -static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = { - .supply_name = "CAM_VT_D_IO", - .microvolts = 2800000, - .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */ - .enable_high = 1, - .init_data = &cam_vt_dio_reg_init_data, -}; - -static struct platform_device cam_vt_dio_fixed_reg_dev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO, - .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply cam_i_core_supply = - REGULATOR_SUPPLY("core", "0-001f"); - -static struct regulator_init_data cam_i_core_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_i_core_supply, -}; - -static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = { - .supply_name = "CAM_I_CORE_1.2V", - .microvolts = 1200000, - .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */ - .enable_high = 1, - .init_data = &cam_i_core_reg_init_data, -}; - -static struct platform_device cam_i_core_fixed_reg_dev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE, - .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg }, -}; - -static struct regulator_consumer_supply cam_s_if_supply = - REGULATOR_SUPPLY("d_sensor", "0-001f"); - -static struct regulator_init_data cam_s_if_reg_init_data = { - .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, - .num_consumer_supplies = 1, - .consumer_supplies = &cam_s_if_supply, -}; - -static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = { - .supply_name = "CAM_S_IF_1.8V", - .microvolts = 1800000, - .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */ - .enable_high = 1, - .init_data = &cam_s_if_reg_init_data, -}; - -static struct platform_device cam_s_if_fixed_reg_dev = { - .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF, - .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg }, -}; - -static struct s5p_platform_mipi_csis mipi_csis_platdata = { - .clk_rate = 166000000UL, - .lanes = 2, - .hs_settle = 12, -}; - -#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3) -#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */ -#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5) -#define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7) -#define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6) - -static int s5k6aa_set_power(int on) -{ - gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on); - return 0; -} - -static struct s5k6aa_platform_data s5k6aa_platdata = { - .mclk_frequency = 21600000UL, - .gpio_reset = { GPIO_CAM_VGA_NRST, 0 }, - .gpio_stby = { GPIO_CAM_VGA_NSTBY, 0 }, - .bus_type = V4L2_MBUS_PARALLEL, - .horiz_flip = 1, - .set_power = s5k6aa_set_power, -}; - -static struct i2c_board_info s5k6aa_board_info = { - I2C_BOARD_INFO("S5K6AA", 0x3C), - .platform_data = &s5k6aa_platdata, -}; - -static int m5mols_set_power(struct device *dev, int on) -{ - gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on); - gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on); - return 0; -} - -static struct m5mols_platform_data m5mols_platdata = { - .gpio_reset = GPIO_CAM_MEGA_nRST, - .reset_polarity = 0, - .set_power = m5mols_set_power, -}; - -static struct i2c_board_info m5mols_board_info = { - I2C_BOARD_INFO("M5MOLS", 0x1F), - .platform_data = &m5mols_platdata, -}; - -static struct fimc_source_info universal_camera_sensors[] = { - { - .mux_id = 0, - .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_ITU_601, - .board_info = &s5k6aa_board_info, - .i2c_bus_num = 0, - .clk_frequency = 24000000UL, - }, { - .mux_id = 0, - .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_VSYNC_ACTIVE_LOW, - .fimc_bus_type = FIMC_BUS_TYPE_MIPI_CSI2, - .board_info = &m5mols_board_info, - .i2c_bus_num = 0, - .clk_frequency = 24000000UL, - }, -}; - -static struct s5p_platform_fimc fimc_md_platdata = { - .source_info = universal_camera_sensors, - .num_clients = ARRAY_SIZE(universal_camera_sensors), -}; - -static struct gpio universal_camera_gpios[] = { - { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" }, - { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" }, - { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, - { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, - { GPIO_CAM_VGA_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" }, - { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" }, -}; - -/* USB OTG */ -static struct s3c_hsotg_plat universal_hsotg_pdata; - -static void __init universal_camera_init(void) -{ - s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), - &s5p_device_mipi_csis0); - s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata), - &s5p_device_fimc_md); - - if (gpio_request_array(universal_camera_gpios, - ARRAY_SIZE(universal_camera_gpios))) { - pr_err("%s: GPIO request failed\n", __func__); - return; - } - - if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf))) - m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT); - else - pr_err("Failed to configure 8M_ISP_INT GPIO\n"); - - /* Free GPIOs controlled directly by the sensor drivers. */ - gpio_free(GPIO_CAM_MEGA_nRST); - gpio_free(GPIO_CAM_8M_ISP_INT); - gpio_free(GPIO_CAM_VGA_NRST); - gpio_free(GPIO_CAM_VGA_NSTBY); - - if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) - pr_err("Camera port A setup failed\n"); -} - -static struct platform_device *universal_devices[] __initdata = { - /* Samsung Platform Devices */ - &s5p_device_mipi_csis0, - &s5p_device_fimc0, - &s5p_device_fimc1, - &s5p_device_fimc2, - &s5p_device_fimc3, - &s5p_device_g2d, - &mmc0_fixed_voltage, - &s3c_device_hsmmc0, - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c0, - &s3c_device_i2c3, - &s3c_device_i2c5, - &s5p_device_i2c_hdmiphy, - &hdmi_fixed_voltage, - &s5p_device_hdmi, - &s5p_device_sdo, - &s5p_device_mixer, - - /* Universal Devices */ - &i2c_gpio12, - &universal_gpio_keys, - &s5p_device_onenand, - &s5p_device_fimd0, - &s5p_device_jpeg, - &s3c_device_usb_hsotg, - &s5p_device_mfc, - &s5p_device_mfc_l, - &s5p_device_mfc_r, - &cam_vt_dio_fixed_reg_dev, - &cam_i_core_fixed_reg_dev, - &cam_s_if_fixed_reg_dev, - &s5p_device_fimc_md, -}; - -static void __init universal_map_io(void) -{ - exynos_init_io(NULL, 0); - s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); - exynos_set_timer_source(BIT(2) | BIT(4)); - xxti_f = 0; - xusbxti_f = 24000000; -} - -static void s5p_tv_setup(void) -{ - /* direct HPD to HDMI chip */ - gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); - s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); -} - -static void __init universal_reserve(void) -{ - s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); -} - -static void __init universal_machine_init(void) -{ - universal_sdhci_init(); - s5p_tv_setup(); - - s3c_i2c0_set_platdata(&universal_i2c0_platdata); - i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); - - universal_tsp_init(); - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); - - s3c_i2c5_set_platdata(NULL); - s5p_i2c_hdmiphy_set_platdata(NULL); - i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); - -#ifdef CONFIG_DRM_EXYNOS - s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; - exynos4_fimd0_gpio_setup_24bpp(); -#else - s5p_fimd0_set_platdata(&universal_lcd_pdata); -#endif - - universal_touchkey_init(); - i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, - ARRAY_SIZE(i2c_gpio12_devs)); - - s3c_hsotg_set_platdata(&universal_hsotg_pdata); - universal_camera_init(); - - /* Last */ - platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); -} - -MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") - /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ - .atag_offset = 0x100, - .smp = smp_ops(exynos_smp_ops), - .init_irq = exynos4_init_irq, - .map_io = universal_map_io, - .init_machine = universal_machine_init, - .init_late = exynos_init_late, - .init_time = exynos_init_time, - .reserve = &universal_reserve, - .restart = exynos4_restart, -MACHINE_END diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index a0e8ff7758a..d9c6d0ab6a0 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -200,7 +200,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { int i; - if (!(soc_is_exynos5250() || soc_is_exynos5440())) + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) scu_enable(scu_base_addr()); /* diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index e3faaa81201..41c20692a13 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -30,7 +30,6 @@ #include <plat/regs-srom.h> #include <mach/regs-irq.h> -#include <mach/regs-gpio.h> #include <mach/regs-clock.h> #include <mach/regs-pmu.h> #include <mach/pm-core.h> diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 9f1351de52f..1703593e366 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -74,17 +74,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain) return exynos_pd_power(domain, false); } -#define EXYNOS_GPD(PD, BASE, NAME) \ -static struct exynos_pm_domain PD = { \ - .base = (void __iomem *)BASE, \ - .name = NAME, \ - .pd = { \ - .power_off = exynos_pd_power_off, \ - .power_on = exynos_pd_power_on, \ - }, \ -} - -#ifdef CONFIG_OF static void exynos_add_device_to_domain(struct exynos_pm_domain *pd, struct device *dev) { @@ -157,7 +146,7 @@ static struct notifier_block platform_nb = { .notifier_call = exynos_pm_notifier_call, }; -static __init int exynos_pm_dt_parse_domains(void) +static __init int exynos4_pm_init_power_domain(void) { struct platform_device *pdev; struct device_node *np; @@ -193,94 +182,6 @@ static __init int exynos_pm_dt_parse_domains(void) return 0; } -#else -static __init int exynos_pm_dt_parse_domains(void) -{ - return 0; -} -#endif /* CONFIG_OF */ - -static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, - struct exynos_pm_domain *pd) -{ - if (pdev->dev.bus) { - if (!pm_genpd_add_device(&pd->pd, &pdev->dev)) - pm_genpd_dev_need_restore(&pdev->dev, true); - else - pr_info("%s: error in adding %s device to %s power" - "domain\n", __func__, dev_name(&pdev->dev), - pd->name); - } -} - -EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc"); -EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d"); -EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0"); -EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1"); -EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv"); -EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam"); -EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps"); - -static struct exynos_pm_domain *exynos4_pm_domains[] = { - &exynos4_pd_mfc, - &exynos4_pd_g3d, - &exynos4_pd_lcd0, - &exynos4_pd_lcd1, - &exynos4_pd_tv, - &exynos4_pd_cam, - &exynos4_pd_gps, -}; - -static __init int exynos4_pm_init_power_domain(void) -{ - int idx; - - if (of_have_populated_dt()) - return exynos_pm_dt_parse_domains(); - - for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) { - struct exynos_pm_domain *pd = exynos4_pm_domains[idx]; - int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; - - pm_genpd_init(&pd->pd, NULL, !on); - } - -#ifdef CONFIG_S5P_DEV_FIMD0 - exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); -#endif -#ifdef CONFIG_S5P_DEV_TV - exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv); - exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv); -#endif -#ifdef CONFIG_S5P_DEV_MFC - exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc); -#endif -#ifdef CONFIG_S5P_DEV_FIMC0 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_FIMC1 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_FIMC2 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_FIMC3 - exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_CSIS0 - exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_CSIS1 - exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam); -#endif -#ifdef CONFIG_S5P_DEV_G2D - exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0); -#endif -#ifdef CONFIG_S5P_DEV_JPEG - exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam); -#endif - return 0; -} arch_initcall(exynos4_pm_init_power_domain); int __init exynos_pm_late_initcall(void) diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c deleted file mode 100644 index 6a45078d9d1..00000000000 --- a/arch/arm/mach-exynos/setup-fimc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co., Ltd. - * - * Exynos4 camera interface GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/camport.h> - -int exynos4_fimc_setup_gpio(enum s5p_camport_id id) -{ - u32 gpio8, gpio5; - u32 sfn; - int ret; - - switch (id) { - case S5P_CAMPORT_A: - gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */ - gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */ - sfn = S3C_GPIO_SFN(2); - break; - - case S5P_CAMPORT_B: - gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */ - gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */ - sfn = S3C_GPIO_SFN(3); - break; - - default: - WARN(1, "Wrong camport id: %d\n", id); - return -EINVAL; - } - - ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP); - if (ret) - return ret; - - return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c deleted file mode 100644 index 5665bb4e980..00000000000 --- a/arch/arm/mach-exynos/setup-fimd0.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-fimd0.c - * - * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Base Exynos4 FIMD 0 configuration - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/fb.h> -#include <linux/gpio.h> - -#include <video/samsung_fimd.h> -#include <plat/gpio-cfg.h> - -#include <mach/map.h> - -void exynos4_fimd0_gpio_setup_24bpp(void) -{ - unsigned int reg; - - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2)); - - /* - * Set DISPLAY_CONTROL register for Display path selection. - * - * DISPLAY_CONTROL[1:0] - * --------------------- - * 00 | MIE - * 01 | MDINE - * 10 | FIMD : selected - * 11 | FIMD - */ - reg = __raw_readl(S3C_VA_SYS + 0x0210); - reg |= (1 << 1); - __raw_writel(reg, S3C_VA_SYS + 0x0210); -} diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c deleted file mode 100644 index e2d9dfbf102..00000000000 --- a/arch/arm/mach-exynos/setup-i2c0.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * I2C0 GPIO configuration. - * - * Based on plat-s3c64xx/setup-i2c0.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <plat/cpu.h> - -void s3c_i2c0_cfg_gpio(struct platform_device *dev) -{ - if (soc_is_exynos5250() || soc_is_exynos5440()) - /* will be implemented with gpio function */ - return; - - s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c deleted file mode 100644 index 8d2279cc85d..00000000000 --- a/arch/arm/mach-exynos/setup-i2c1.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c1.c - * - * Copyright (C) 2010 Samsung Electronics Co., Ltd. - * - * I2C1 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c1_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c deleted file mode 100644 index 0ed62fc42a7..00000000000 --- a/arch/arm/mach-exynos/setup-i2c2.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c2.c - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * - * I2C2 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c2_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c deleted file mode 100644 index 7787fd26076..00000000000 --- a/arch/arm/mach-exynos/setup-i2c3.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c3.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C3 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c3_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c deleted file mode 100644 index edc847f8982..00000000000 --- a/arch/arm/mach-exynos/setup-i2c4.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c4.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C4 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c4_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c deleted file mode 100644 index d88af7f7595..00000000000 --- a/arch/arm/mach-exynos/setup-i2c5.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c5.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C5 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c5_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c deleted file mode 100644 index c590286c9d3..00000000000 --- a/arch/arm/mach-exynos/setup-i2c6.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c6.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C6 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c6_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, - S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c deleted file mode 100644 index 1bba75568a5..00000000000 --- a/arch/arm/mach-exynos/setup-i2c7.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/setup-i2c7.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * - * I2C7 GPIO configuration. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -struct platform_device; /* don't need the contents */ - -#include <linux/gpio.h> -#include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> - -void s3c_i2c7_cfg_gpio(struct platform_device *dev) -{ - s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2, - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); -} diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c deleted file mode 100644 index 7862bfb5933..00000000000 --- a/arch/arm/mach-exynos/setup-keypad.c +++ /dev/null @@ -1,36 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-keypad.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * GPIO configuration for Exynos4 KeyPad device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> - -void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) -{ - /* Keypads can be of various combinations, Just making sure */ - - if (rows > 8) { - /* Set all the necessary GPX2 pins: KP_ROW[0~7] */ - s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3), - S3C_GPIO_PULL_UP); - - /* Set all the necessary GPX3 pins: KP_ROW[8~] */ - s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8), - S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); - } else { - /* Set all the necessary GPX2 pins: KP_ROW[x] */ - s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3), - S3C_GPIO_PULL_UP); - } - - /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */ - s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3)); -} diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c deleted file mode 100644 index d5b98c86673..00000000000 --- a/arch/arm/mach-exynos/setup-sdhci-gpio.c +++ /dev/null @@ -1,152 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/mmc/host.h> -#include <linux/mmc/card.h> - -#include <mach/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/sdhci.h> - -void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK0[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case 8: - for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-function 3 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case 4: - for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) { - /* Data pin GPK0[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - default: - break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK1[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) { - /* Data pin GPK1[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK2[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case 8: - for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { - /* Data pin GPK3[3:6] to special-function 3 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case 4: - for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) { - /* Data pin GPK2[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - default: - break; - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} - -void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) -{ - struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; - unsigned int gpio; - - /* Set all the necessary GPK3[0:1] pins to special-function 2 */ - for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { - /* Data pin GPK3[3:6] to special-function 2 */ - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { - s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } -} diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c deleted file mode 100644 index 4999829d1c6..00000000000 --- a/arch/arm/mach-exynos/setup-spi.c +++ /dev/null @@ -1,45 +0,0 @@ -/* linux/arch/arm/mach-exynos4/setup-spi.c - * - * Copyright (C) 2011 Samsung Electronics Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> - -#ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(void) -{ - s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - return 0; -} -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(void) -{ - s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2, - S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); - return 0; -} -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI2 -int s3c64xx_spi2_cfg_gpio(void) -{ - s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); - s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); - s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, - S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP); - return 0; -} -#endif diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c deleted file mode 100644 index 6af40662a44..00000000000 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <mach/regs-pmu.h> -#include <mach/regs-usb-phy.h> -#include <plat/cpu.h> -#include <plat/usb-phy.h> - -static atomic_t host_usage; - -static int exynos4_usb_host_phy_is_on(void) -{ - return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1; -} - -static void exynos4210_usb_phy_clkset(struct platform_device *pdev) -{ - struct clk *xusbxti_clk; - u32 phyclk; - - xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); - if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - if (soc_is_exynos4210()) { - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; - - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= EXYNOS4210_CLKSEL_12M; - break; - case 48 * MHZ: - phyclk |= EXYNOS4210_CLKSEL_48M; - break; - default: - case 24 * MHZ: - phyclk |= EXYNOS4210_CLKSEL_24M; - break; - } - writel(phyclk, EXYNOS4_PHYCLK); - } else if (soc_is_exynos4212() || soc_is_exynos4412()) { - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; - - switch (clk_get_rate(xusbxti_clk)) { - case 9600 * KHZ: - phyclk |= EXYNOS4X12_CLKSEL_9600K; - break; - case 10 * MHZ: - phyclk |= EXYNOS4X12_CLKSEL_10M; - break; - case 12 * MHZ: - phyclk |= EXYNOS4X12_CLKSEL_12M; - break; - case 19200 * KHZ: - phyclk |= EXYNOS4X12_CLKSEL_19200K; - break; - case 20 * MHZ: - phyclk |= EXYNOS4X12_CLKSEL_20M; - break; - default: - case 24 * MHZ: - /* default reference clock */ - phyclk |= EXYNOS4X12_CLKSEL_24M; - break; - } - writel(phyclk, EXYNOS4_PHYCLK); - } - clk_put(xusbxti_clk); - } -} - -static int exynos4210_usb_phy0_init(struct platform_device *pdev) -{ - u32 rstcon; - - writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE, - S5P_USBDEVICE_PHY_CONTROL); - - exynos4210_usb_phy_clkset(pdev); - - /* set to normal PHY0 */ - writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR); - - /* reset PHY0 and Link */ - rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK; - writel(rstcon, EXYNOS4_RSTCON); - udelay(10); - - rstcon &= ~PHY0_SWRST_MASK; - writel(rstcon, EXYNOS4_RSTCON); - - return 0; -} - -static int exynos4210_usb_phy0_exit(struct platform_device *pdev) -{ - writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN | - PHY0_OTG_DISABLE), EXYNOS4_PHYPWR); - - writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE, - S5P_USBDEVICE_PHY_CONTROL); - - return 0; -} - -static int exynos4210_usb_phy1_init(struct platform_device *pdev) -{ - struct clk *otg_clk; - u32 rstcon; - int err; - - atomic_inc(&host_usage); - - otg_clk = clk_get(&pdev->dev, "otg"); - if (IS_ERR(otg_clk)) { - dev_err(&pdev->dev, "Failed to get otg clock\n"); - return PTR_ERR(otg_clk); - } - - err = clk_enable(otg_clk); - if (err) { - clk_put(otg_clk); - return err; - } - - if (exynos4_usb_host_phy_is_on()) - return 0; - - writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, - S5P_USBHOST_PHY_CONTROL); - - exynos4210_usb_phy_clkset(pdev); - - /* floating prevention logic: disable */ - writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); - - /* set to normal HSIC 0 and 1 of PHY1 */ - writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK), - EXYNOS4_PHYPWR); - - /* set to normal standard USB of PHY1 */ - writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR); - - /* reset all ports of both PHY and Link */ - rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK | - PHY1_SWRST_MASK; - writel(rstcon, EXYNOS4_RSTCON); - udelay(10); - - rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK); - writel(rstcon, EXYNOS4_RSTCON); - udelay(80); - - clk_disable(otg_clk); - clk_put(otg_clk); - - return 0; -} - -static int exynos4210_usb_phy1_exit(struct platform_device *pdev) -{ - struct clk *otg_clk; - int err; - - if (atomic_dec_return(&host_usage) > 0) - return 0; - - otg_clk = clk_get(&pdev->dev, "otg"); - if (IS_ERR(otg_clk)) { - dev_err(&pdev->dev, "Failed to get otg clock\n"); - return PTR_ERR(otg_clk); - } - - err = clk_enable(otg_clk); - if (err) { - clk_put(otg_clk); - return err; - } - - writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN), - EXYNOS4_PHYPWR); - - writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE, - S5P_USBHOST_PHY_CONTROL); - - clk_disable(otg_clk); - clk_put(otg_clk); - - return 0; -} - -int s5p_usb_phy_init(struct platform_device *pdev, int type) -{ - if (type == USB_PHY_TYPE_DEVICE) - return exynos4210_usb_phy0_init(pdev); - else if (type == USB_PHY_TYPE_HOST) - return exynos4210_usb_phy1_init(pdev); - - return -EINVAL; -} - -int s5p_usb_phy_exit(struct platform_device *pdev, int type) -{ - if (type == USB_PHY_TYPE_DEVICE) - return exynos4210_usb_phy0_exit(pdev); - else if (type == USB_PHY_TYPE_HOST) - return exynos4210_usb_phy1_exit(pdev); - - return -EINVAL; -} diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index e7df2dd43a4..dc5d6becd8c 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -176,7 +176,6 @@ static const char *highbank_match[] __initconst = { DT_MACHINE_START(HIGHBANK, "Highbank") .smp = smp_ops(highbank_smp_ops), - .map_io = debug_ll_io_init, .init_irq = highbank_init_irq, .init_time = highbank_timer_init, .init_machine = highbank_init, diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f25cf888f3d..60661a4b0e2 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -173,6 +173,7 @@ config ARCH_MX1ADS config MACH_SCB9328 bool "Synertronixx scb9328" select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX1 help Say Y here if you are using a Synertronixx scb9328 board @@ -823,6 +824,7 @@ config SOC_IMX6SL select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC + select MFD_SYSCON select PINCTRL select PINCTRL_IMX6SL select PL310_ERRATA_588369 if CACHE_PL310 diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index d14d6b76f4c..ec759ded7b6 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -8,5 +8,5 @@ obj-y := core.o lm.o leds.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o -obj-$(CONFIG_PCI) += pci_v3.o pci.o +obj-$(CONFIG_PCI) += pci_v3.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h index be5859efe10..306d025d973 100644 --- a/arch/arm/mach-integrator/include/mach/platform.h +++ b/arch/arm/mach-integrator/include/mach/platform.h @@ -305,29 +305,6 @@ /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ /* ------------------------------------------------------------------------ - * Where in the memory map does PCI live? - * ------------------------------------------------------------------------ - * This represents a fairly liberal usage of address space. Even though - * the V3 only has two windows (therefore we need to map stuff on the fly), - * we maintain the same addresses, even if they're not mapped. - * - */ -#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */ -/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? - */ -#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */ -/* unused (128-16)M from B1000000-B7FFFFFF - */ -#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ -/* unused ((128-16)M - 64K) from XXX - */ -#define PHYS_PCI_V3_BASE 0x62000000 - -#define PCI_MEMORY_VADDR IOMEM(0xe8000000) -#define PCI_CONFIG_VADDR IOMEM(0xec000000) -#define PCI_V3_VADDR IOMEM(0xed000000) - -/* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ * diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index b23c8e4f28e..a5b15c4e8de 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -41,7 +41,6 @@ #include <linux/stat.h> #include <linux/sys_soc.h> #include <linux/termios.h> -#include <video/vga.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -57,10 +56,10 @@ #include <asm/mach/arch.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> -#include <asm/mach/pci.h> #include <asm/mach/time.h> #include "common.h" +#include "pci_v3.h" /* Base address to the AP system controller */ void __iomem *ap_syscon_base; @@ -78,10 +77,6 @@ void __iomem *ap_syscon_base; /* * Logical Physical - * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) - * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) - * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = { .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), .length = SZ_4K, .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_MEMORY_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_CONFIG_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_V3_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), - .length = SZ_64K, - .type = MT_DEVICE } }; static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); - vga_base = (unsigned long)PCI_MEMORY_VADDR; - pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); + pci_v3_early_init(); } #ifdef CONFIG_PM @@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void) * for eventual deletion. */ +static struct platform_device pci_v3_device = { + .name = "pci-v3", + .id = 0, +}; + static struct resource cfi_flash_resource = { .start = INTEGRATOR_FLASH_BASE, .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, @@ -672,6 +656,7 @@ static void __init ap_init(void) unsigned long sc_dec; int i; + platform_device_register(&pci_v3_device); platform_device_register(&cfi_flash_device); ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c deleted file mode 100644 index 6c1667e728f..00000000000 --- a/arch/arm/mach-integrator/pci.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/pci-integrator.c - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * - * PCI functions for Integrator - */ -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/init.h> - -#include <asm/mach/pci.h> -#include <asm/mach-types.h> - -#include <mach/irqs.h> - -/* - * A small note about bridges and interrupts. The DECchip 21050 (and - * later) adheres to the PCI-PCI bridge specification. This says that - * the interrupts on the other side of a bridge are swizzled in the - * following manner: - * - * Dev Interrupt Interrupt - * Pin on Pin on - * Device Connector - * - * 4 A A - * B B - * C C - * D D - * - * 5 A B - * B C - * C D - * D A - * - * 6 A C - * B D - * C A - * D B - * - * 7 A D - * B A - * C B - * D C - * - * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. - * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 - */ - -/* - * This routine handles multiple bridges. - */ -static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp) -{ - if (*pinp == 0) - *pinp = 1; - - return pci_common_swizzle(dev, pinp); -} - -static int irq_tab[4] __initdata = { - IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 -}; - -/* - * map the specified device/slot/pin to an IRQ. This works out such - * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. - */ -static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int intnr = ((slot - 9) + (pin - 1)) & 3; - - return irq_tab[intnr]; -} - -extern void pci_v3_init(void *); - -static struct hw_pci integrator_pci __initdata = { - .swizzle = integrator_swizzle, - .map_irq = integrator_map_irq, - .setup = pci_v3_setup, - .nr_controllers = 1, - .ops = &pci_v3_ops, - .preinit = pci_v3_preinit, - .postinit = pci_v3_postinit, -}; - -static int __init integrator_pci_init(void) -{ - if (machine_is_integrator()) - pci_common_init(&integrator_pci); - return 0; -} - -subsys_initcall(integrator_pci_init); diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index e7fcea7f330..bef100527c4 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -27,16 +27,199 @@ #include <linux/spinlock.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <video/vga.h> #include <mach/hardware.h> #include <mach/platform.h> #include <mach/irqs.h> +#include <asm/mach/map.h> #include <asm/signal.h> #include <asm/mach/pci.h> #include <asm/irq_regs.h> -#include <asm/hardware/pci_v3.h> +#include "pci_v3.h" + +/* + * Where in the memory map does PCI live? + * + * This represents a fairly liberal usage of address space. Even though + * the V3 only has two windows (therefore we need to map stuff on the fly), + * we maintain the same addresses, even if they're not mapped. + */ +#define PHYS_PCI_MEM_BASE 0x40000000 /* 256M */ +#define PHYS_PCI_PRE_BASE 0x50000000 /* 256M */ +#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */ +#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */ +#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */ + +#define PCI_MEMORY_VADDR IOMEM(0xe8000000) +#define PCI_CONFIG_VADDR IOMEM(0xec000000) + +/* + * V3 Local Bus to PCI Bridge definitions + * + * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 + * All V3 register names are prefaced by V3_ to avoid clashing with any other + * PCI definitions. Their names match the user's manual. + * + * I'm assuming that I20 is disabled. + * + */ +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CFG 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC + +/* PCI COMMAND REGISTER bits + */ +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) + +/* SYSTEM REGISTER bits + */ +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) + +/* PCI_CFG bits + */ +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) + +/* PCI_BASE register bits (PCI -> Local Bus) + */ +#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 +#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) + +/* PCI MAP register bits (PCI -> Local bus) + */ +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) + +/* + * LB_BASE0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) + +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) + +/* + * LB_MAP2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) /* * The V3 PCI interface chip in Integrator provides several windows from @@ -101,15 +284,28 @@ * the mappings into PCI memory. */ +/* Filled in by probe */ +static void __iomem *pci_v3_base; +/* CPU side memory ranges */ +static struct resource conf_mem; /* FIXME: remap this instead of static map */ +static struct resource io_mem; +static struct resource non_mem; +static struct resource pre_mem; +/* PCI side memory ranges */ +static u64 non_mem_pci; +static u64 non_mem_pci_sz; +static u64 pre_mem_pci; +static u64 pre_mem_pci_sz; + // V3 access routines -#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o)) +#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o))) -#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o)) +#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o))) -#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o))) +#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o)) +#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o))) /*============================================================================ * @@ -165,19 +361,6 @@ */ static DEFINE_RAW_SPINLOCK(v3_lock); -#define PCI_BUS_NONMEM_START 0x00000000 -#define PCI_BUS_NONMEM_SIZE SZ_256M - -#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE -#define PCI_BUS_PREMEM_SIZE SZ_256M - -#if PCI_BUS_NONMEM_START & 0x000fffff -#error PCI_BUS_NONMEM_START must be megabyte aligned -#endif -#if PCI_BUS_PREMEM_START & 0x000fffff -#error PCI_BUS_PREMEM_START must be megabyte aligned -#endif - #undef V3_LB_BASE_PREFETCH #define V3_LB_BASE_PREFETCH 0 @@ -243,13 +426,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus, * prefetchable), this frees up base1 for re-use by * configuration memory */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); /* * Set up base1/map1 to point into configuration space. */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) | V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP1, mapaddress); @@ -261,16 +444,16 @@ static void v3_close_config_window(void) /* * Reassign base1 for use by prefetchable PCI memory */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | + v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) | V3_LB_MAP_TYPE_MEM_MULTIPLE); /* * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); } @@ -337,25 +520,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, return PCIBIOS_SUCCESSFUL; } -struct pci_ops pci_v3_ops = { +static struct pci_ops pci_v3_ops = { .read = v3_read_config, .write = v3_write_config, }; -static struct resource non_mem = { - .name = "PCI non-prefetchable", - .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START, - .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1, - .flags = IORESOURCE_MEM, -}; - -static struct resource pre_mem = { - .name = "PCI prefetchable", - .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START, - .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1, - .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, -}; - static int __init pci_v3_setup_resources(struct pci_sys_data *sys) { if (request_resource(&iomem_resource, &non_mem)) { @@ -471,7 +640,7 @@ static irqreturn_t v3_irq(int dummy, void *devid) return IRQ_HANDLED; } -int __init pci_v3_setup(int nr, struct pci_sys_data *sys) +static int __init pci_v3_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -479,7 +648,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) return -EINVAL; if (nr == 0) { - sys->mem_offset = PHYS_PCI_MEM_BASE; + sys->mem_offset = non_mem.start; ret = pci_v3_setup_resources(sys); } @@ -490,18 +659,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) * V3_LB_BASE? - local bus address * V3_LB_MAP? - pci bus address */ -void __init pci_v3_preinit(void) +static void __init pci_v3_preinit(void) { unsigned long flags; unsigned int temp; - int ret; - - /* Remap the Integrator system controller */ - ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); - if (!ap_syscon_base) { - pr_err("unable to remap the AP syscon for PCIv3\n"); - return; - } pcibios_min_mem = 0x00100000; @@ -525,25 +686,25 @@ void __init pci_v3_preinit(void) * Setup window 0 - PCI non-prefetchable memory * Local: 0x40000000 Bus: 0x00000000 Size: 256MB */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | + v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) | V3_LB_MAP_TYPE_MEM); /* * Setup window 1 - PCI prefetchable memory * Local: 0x50000000 Bus: 0x10000000 Size: 256MB */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | + v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) | V3_LB_MAP_TYPE_MEM_MULTIPLE); /* * Setup window 2 - PCI IO */ - v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) | + v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) | V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); @@ -578,18 +739,10 @@ void __init pci_v3_preinit(void) v3_writeb(V3_LB_IMASK, 0x28); __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); - /* - * Grab the PCI error interrupt. - */ - ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); - if (ret) - printk(KERN_ERR "PCI: unable to grab PCI error " - "interrupt: %d\n", ret); - raw_spin_unlock_irqrestore(&v3_lock, flags); } -void __init pci_v3_postinit(void) +static void __init pci_v3_postinit(void) { unsigned int pci_cmd; @@ -608,5 +761,284 @@ void __init pci_v3_postinit(void) "interrupt: %d\n", ret); #endif - register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0); + register_isa_ports(non_mem.start, io_mem.start, 0); +} + +/* + * A small note about bridges and interrupts. The DECchip 21050 (and + * later) adheres to the PCI-PCI bridge specification. This says that + * the interrupts on the other side of a bridge are swizzled in the + * following manner: + * + * Dev Interrupt Interrupt + * Pin on Pin on + * Device Connector + * + * 4 A A + * B B + * C C + * D D + * + * 5 A B + * B C + * C D + * D A + * + * 6 A C + * B D + * C A + * D B + * + * 7 A D + * B A + * C B + * D C + * + * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. + * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 + */ + +/* + * This routine handles multiple bridges. + */ +static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) +{ + if (*pinp == 0) + *pinp = 1; + + return pci_common_swizzle(dev, pinp); +} + +static int irq_tab[4] __initdata = { + IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 +}; + +/* + * map the specified device/slot/pin to an IRQ. This works out such + * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. + */ +static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int intnr = ((slot - 9) + (pin - 1)) & 3; + + return irq_tab[intnr]; +} + +static struct hw_pci pci_v3 __initdata = { + .swizzle = pci_v3_swizzle, + .setup = pci_v3_setup, + .nr_controllers = 1, + .ops = &pci_v3_ops, + .preinit = pci_v3_preinit, + .postinit = pci_v3_postinit, +}; + +#ifdef CONFIG_OF + +static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct of_irq oirq; + int ret; + + ret = of_irq_map_pci(dev, &oirq); + if (ret) { + dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret); + /* Proper return code 0 == NO_IRQ */ + return 0; + } + + return irq_create_of_mapping(oirq.controller, oirq.specifier, + oirq.size); +} + +static int __init pci_v3_dtprobe(struct platform_device *pdev, + struct device_node *np) +{ + struct of_pci_range_parser parser; + struct of_pci_range range; + struct resource *res; + int irq, ret; + + if (of_pci_range_parser_init(&parser, np)) + return -EINVAL; + + /* Get base for bridge registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to obtain PCIv3 base\n"); + return -ENODEV; + } + pci_v3_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!pci_v3_base) { + dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); + return -ENODEV; + } + + /* Get and request error IRQ resource */ + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n"); + return -ENODEV; + } + ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0, + "PCIv3 error", NULL); + if (ret < 0) { + dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret); + return ret; + } + + for_each_of_pci_range(&parser, &range) { + if (!range.flags) { + of_pci_range_to_resource(&range, np, &conf_mem); + conf_mem.name = "PCIv3 config"; + } + if (range.flags & IORESOURCE_IO) { + of_pci_range_to_resource(&range, np, &io_mem); + io_mem.name = "PCIv3 I/O"; + } + if ((range.flags & IORESOURCE_MEM) && + !(range.flags & IORESOURCE_PREFETCH)) { + non_mem_pci = range.pci_addr; + non_mem_pci_sz = range.size; + of_pci_range_to_resource(&range, np, &non_mem); + non_mem.name = "PCIv3 non-prefetched mem"; + } + if ((range.flags & IORESOURCE_MEM) && + (range.flags & IORESOURCE_PREFETCH)) { + pre_mem_pci = range.pci_addr; + pre_mem_pci_sz = range.size; + of_pci_range_to_resource(&range, np, &pre_mem); + pre_mem.name = "PCIv3 prefetched mem"; + } + } + + if (!conf_mem.start || !io_mem.start || + !non_mem.start || !pre_mem.start) { + dev_err(&pdev->dev, "missing ranges in device node\n"); + return -EINVAL; + } + + pci_v3.map_irq = pci_v3_map_irq_dt; + pci_common_init_dev(&pdev->dev, &pci_v3); + + return 0; +} + +#else + +static inline int pci_v3_dtprobe(struct platform_device *pdev, + struct device_node *np) +{ + return -EINVAL; +} + +#endif + +static int __init pci_v3_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int ret; + + /* Remap the Integrator system controller */ + ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); + if (!ap_syscon_base) { + dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); + return -ENODEV; + } + + /* Device tree probe path */ + if (np) + return pci_v3_dtprobe(pdev, np); + + pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); + if (!pci_v3_base) { + dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); + return -ENODEV; + } + + ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); + if (ret) { + dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", + ret); + return -ENODEV; + } + + conf_mem.name = "PCIv3 config"; + conf_mem.start = PHYS_PCI_CONFIG_BASE; + conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1; + conf_mem.flags = IORESOURCE_MEM; + + io_mem.name = "PCIv3 I/O"; + io_mem.start = PHYS_PCI_IO_BASE; + io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; + io_mem.flags = IORESOURCE_MEM; + + non_mem_pci = 0x00000000; + non_mem_pci_sz = SZ_256M; + non_mem.name = "PCIv3 non-prefetched mem"; + non_mem.start = PHYS_PCI_MEM_BASE; + non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1; + non_mem.flags = IORESOURCE_MEM; + + pre_mem_pci = 0x10000000; + pre_mem_pci_sz = SZ_256M; + pre_mem.name = "PCIv3 prefetched mem"; + pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M; + pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1; + pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + pci_v3.map_irq = pci_v3_map_irq; + + pci_common_init_dev(&pdev->dev, &pci_v3); + + return 0; +} + +static const struct of_device_id pci_ids[] = { + { .compatible = "v3,v360epc-pci", }, + {}, +}; + +static struct platform_driver pci_v3_driver = { + .driver = { + .name = "pci-v3", + .of_match_table = pci_ids, + }, +}; + +static int __init pci_v3_init(void) +{ + return platform_driver_probe(&pci_v3_driver, pci_v3_probe); +} + +subsys_initcall(pci_v3_init); + +/* + * Static mappings for the PCIv3 bridge + * + * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) + * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) + * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + */ +static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = { + { + .virtual = (unsigned long)PCI_MEMORY_VADDR, + .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)PCI_CONFIG_VADDR, + .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), + .length = SZ_16M, + .type = MT_DEVICE + } +}; + +int __init pci_v3_early_init(void) +{ + iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc)); + vga_base = (unsigned long)PCI_MEMORY_VADDR; + pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); + return 0; } diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h new file mode 100644 index 00000000000..755fd29fed4 --- /dev/null +++ b/arch/arm/mach-integrator/pci_v3.h @@ -0,0 +1,2 @@ +/* Simple oneliner include to the PCIv3 early init */ +extern int pci_v3_early_init(void); diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 73a2d905af8..30e1ebe3a89 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -235,7 +235,6 @@ config IXP4XX_QMGR config IXP4XX_NPE tristate "IXP4xx Network Processor Engine support" select FW_LOADER - select HOTPLUG help This driver supports IXP4xx built-in network coprocessors and is automatically selected by Ethernet and HSS drivers. diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig new file mode 100644 index 00000000000..51a50e99684 --- /dev/null +++ b/arch/arm/mach-keystone/Kconfig @@ -0,0 +1,15 @@ +config ARCH_KEYSTONE + bool "Texas Instruments Keystone Devices" + depends on ARCH_MULTI_V7 + select CPU_V7 + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + select CLKSRC_MMIO + select GENERIC_CLOCKEVENTS + select HAVE_SCHED_CLOCK + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_ERRATA_798181 if SMP + help + Support for boards based on the Texas Instruments Keystone family of + SoCs. diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile new file mode 100644 index 00000000000..ddc52b05dc8 --- /dev/null +++ b/arch/arm/mach-keystone/Makefile @@ -0,0 +1,6 @@ +obj-y := keystone.o smc.o + +plus_sec := $(call as-instr,.arch_extension sec,+sec) +AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) + +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot new file mode 100644 index 00000000000..f3835c43af6 --- /dev/null +++ b/arch/arm/mach-keystone/Makefile.boot @@ -0,0 +1 @@ +zreladdr-y := 0x80008000 diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c new file mode 100644 index 00000000000..fe4d9ff93a7 --- /dev/null +++ b/arch/arm/mach-keystone/keystone.c @@ -0,0 +1,75 @@ +/* + * Keystone2 based boards and SOC related code. + * + * Copyright 2013 Texas Instruments, Inc. + * Cyril Chemparathy <cyril@ti.com> + * Santosh Shilimkar <santosh.shillimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ +#include <linux/io.h> +#include <linux/of.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> + +#include <asm/setup.h> +#include <asm/mach/map.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/smp_plat.h> + +#include "keystone.h" + +#define PLL_RESET_WRITE_KEY_MASK 0xffff0000 +#define PLL_RESET_WRITE_KEY 0x5a69 +#define PLL_RESET BIT(16) + +static void __iomem *keystone_rstctrl; + +static void __init keystone_init(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "ti,keystone-reset"); + if (WARN_ON(!node)) + pr_warn("ti,keystone-reset node undefined\n"); + + keystone_rstctrl = of_iomap(node, 0); + if (WARN_ON(!keystone_rstctrl)) + pr_warn("ti,keystone-reset iomap error\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *keystone_match[] __initconst = { + "ti,keystone-evm", + NULL, +}; + +void keystone_restart(char mode, const char *cmd) +{ + u32 val; + + BUG_ON(!keystone_rstctrl); + + /* Enable write access to RSTCTRL */ + val = readl(keystone_rstctrl); + val &= PLL_RESET_WRITE_KEY_MASK; + val |= PLL_RESET_WRITE_KEY; + writel(val, keystone_rstctrl); + + /* Reset the SOC */ + val = readl(keystone_rstctrl); + val &= ~PLL_RESET; + writel(val, keystone_rstctrl); +} + +DT_MACHINE_START(KEYSTONE, "Keystone") + .smp = smp_ops(keystone_smp_ops), + .init_machine = keystone_init, + .dt_compat = keystone_match, + .restart = keystone_restart, +MACHINE_END diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h new file mode 100644 index 00000000000..60bef9dedb1 --- /dev/null +++ b/arch/arm/mach-keystone/keystone.h @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * Cyril Chemparathy <cyril@ti.com> + * Santosh Shilimkar <santosh.shillimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef __KEYSTONE_H__ +#define __KEYSTONE_H__ + +#define KEYSTONE_MON_CPU_UP_IDX 0x00 + +#ifndef __ASSEMBLER__ + +extern struct smp_operations keystone_smp_ops; +extern void secondary_startup(void); +extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr); + +#endif /* __ASSEMBLER__ */ +#endif /* __KEYSTONE_H__ */ diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c new file mode 100644 index 00000000000..1d4181e1daf --- /dev/null +++ b/arch/arm/mach-keystone/platsmp.c @@ -0,0 +1,43 @@ +/* + * Keystone SOC SMP platform code + * + * Copyright 2013 Texas Instruments, Inc. + * Cyril Chemparathy <cyril@ti.com> + * Santosh Shilimkar <santosh.shillimkar@ti.com> + * + * Based on platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/smp_plat.h> +#include <asm/prom.h> + +#include "keystone.h" + +static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + unsigned long start = virt_to_phys(&secondary_startup); + int error; + + pr_debug("keystone-smp: booting cpu %d, vector %08lx\n", + cpu, start); + + error = keystone_cpu_smc(KEYSTONE_MON_CPU_UP_IDX, cpu, start); + if (error) + pr_err("CPU %d bringup failed with %d\n", cpu, error); + + return error; +} + +struct smp_operations keystone_smp_ops __initdata = { + .smp_init_cpus = arm_dt_init_cpu_maps, + .smp_boot_secondary = keystone_smp_boot_secondary, +}; diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S new file mode 100644 index 00000000000..9b9e4f7b241 --- /dev/null +++ b/arch/arm/mach-keystone/smc.S @@ -0,0 +1,29 @@ +/* + * Keystone Secure APIs + * + * Copyright (C) 2013 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software,you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + +/** + * u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr) + * + * Low level CPU monitor API + * @command: Monitor command. + * @cpu: CPU Number + * @addr: Kernel jump address for boot CPU + * + * Return: Non zero value on failure + */ +ENTRY(keystone_cpu_smc) + stmfd sp!, {r4-r12, lr} + smc #0 + dsb + ldmfd sp!, {r4-r12, pc} +ENDPROC(keystone_cpu_smc) diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 7509a89af96..b634f9650a7 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -8,12 +8,6 @@ config MACH_D2NET_V2 Say 'Y' here if you want your kernel to support the LaCie d2 Network v2 NAS. -config MACH_DB88F6281_BP - bool "Marvell DB-88F6281-BP Development Board" - help - Say 'Y' here if you want your kernel to support the - Marvell DB-88F6281-BP Development Board. - config MACH_DOCKSTAR bool "Seagate FreeAgent DockStar" help @@ -134,13 +128,12 @@ comment "Device tree entries" config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select KIRKWOOD_CLK select POWER_SUPPLY select POWER_RESET select POWER_RESET_GPIO select REGULATOR select REGULATOR_FIXED_VOLTAGE - select MVEBU_CLK_CORE - select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the @@ -153,6 +146,13 @@ config MACH_CLOUDBOX_DT Say 'Y' here if you want your kernel to support the LaCie CloudBox NAS, using Flattened Device Tree. +config MACH_DB88F628X_BP_DT + bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)" + help + Say 'Y' here if you want your kernel to support the Marvell + DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened + Device Tree). + config MACH_DLINK_KIRKWOOD_DT bool "D-Link Kirkwood-based NAS (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -227,6 +227,7 @@ config MACH_KM_KIRKWOOD_DT config MACH_LSXL_DT bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)" select ARCH_KIRKWOOD_DT + select POWER_RESET_RESTART help Say 'Y' here if you want your kernel to support the Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using @@ -272,14 +273,6 @@ config MACH_NETSPACE_V2_DT Say 'Y' here if you want your kernel to support the LaCie Network Space v2 NAS, using Flattened Device Tree. -config MACH_NSA310_DT - bool "ZyXEL NSA-310 (Flattened Device Tree)" - select ARCH_KIRKWOOD_DT - select ARM_ATAG_DTB_COMPAT - help - Say 'Y' here if you want your kernel to support the - ZyXEL NSA-310 board (Flattened Device Tree). - config MACH_OPENBLOCKS_A6_DT bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -296,6 +289,13 @@ config MACH_READYNAS_DT Say 'Y' here if you want your kernel to support the NETGEAR ReadyNAS Duo v2 using Fattened Device Tree. +config MACH_SHEEVAPLUG_DT + bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)" + select ARCH_KIRKWOOD_DT + help + Say 'Y' here if you want your kernel to support the + Marvell (eSATA) SheevaPlug (Flattened Device Tree). + config MACH_TOPKICK_DT bool "USI Topkick (Flattened Device Tree)" select ARCH_KIRKWOOD_DT @@ -308,6 +308,7 @@ config MACH_TS219_DT select ARCH_KIRKWOOD_DT select ARM_APPENDED_DTB select ARM_ATAG_DTB_COMPAT + select POWER_RESET_QNAP help Say 'Y' here if you want your kernel to support the QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index e1f3735d341..ac4cd75dd49 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,7 +1,6 @@ obj-y += common.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o -obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o @@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o +obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o @@ -37,8 +37,8 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o -obj-$(CONFIG_MACH_NSA310_DT) += board-nsa310.o obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o +obj-$(CONFIG_MACH_SHEEVAPLUG_DT) += board-sheevaplug.o obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c new file mode 100644 index 00000000000..2f574bc8ed4 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c @@ -0,0 +1,24 @@ +/* + * Saeed Bishara <saeed@marvell.com> + * + * Marvell DB-88F628{1,2}-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/mv643xx_eth.h> +#include "common.h" + +static struct mv643xx_eth_platform_data db88f628x_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +void __init db88f628x_init(void) +{ + kirkwood_ge00_init(&db88f628x_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index e9647b80cb5..6e122ed3282 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -15,7 +15,6 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/clk-provider.h> -#include <linux/clk/mvebu.h> #include <linux/kexec.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -25,11 +24,6 @@ #include <plat/common.h> #include "common.h" -static struct of_device_id kirkwood_dt_match_table[] __initdata = { - { .compatible = "simple-bus", }, - { } -}; - /* * There are still devices that doesn't know about DT yet. Get clock * gates here and add a clock lookup alias, so that old platform @@ -77,7 +71,7 @@ static void __init kirkwood_legacy_clk_init(void) static void __init kirkwood_of_clk_init(void) { - mvebu_clocks_init(); + of_clk_init(NULL); kirkwood_legacy_clk_init(); } @@ -97,6 +91,8 @@ static void __init kirkwood_dt_init(void) kirkwood_l2_init(); + kirkwood_cpufreq_init(); + /* Setup root of clk tree */ kirkwood_of_clk_init(); @@ -112,6 +108,9 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("globalscale,guruplug")) guruplug_dt_init(); + if (of_machine_is_compatible("globalscale,sheevaplug")) + sheevaplug_dt_init(); + if (of_machine_is_compatible("dlink,dns-kirkwood")) dnskw_init(); @@ -147,6 +146,10 @@ static void __init kirkwood_dt_init(void) of_machine_is_compatible("lacie,netspace_v2")) ns2_init(); + if (of_machine_is_compatible("marvell,db-88f6281-bp") || + of_machine_is_compatible("marvell,db-88f6282-bp")) + db88f628x_init(); + if (of_machine_is_compatible("mpl,cec4")) mplcec4_init(); @@ -159,12 +162,13 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("usi,topkick")) usi_topkick_init(); - of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * const kirkwood_dt_board_compat[] = { "globalscale,dreamplug", "globalscale,guruplug", + "globalscale,sheevaplug", "dlink,dns-320", "dlink,dns-325", "iom,iconnect", @@ -181,6 +185,8 @@ static const char * const kirkwood_dt_board_compat[] = { "lacie,netspace_max_v2", "lacie,netspace_mini_v2", "lacie,netspace_v2", + "marvell,db-88f6281-bp", + "marvell,db-88f6282-bp", "mpl,cec4", "netgear,readynas-duo-v2", "plathome,openblocks-a6", diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c index c8ebde4919e..98b5ad1bba9 100644 --- a/arch/arm/mach-kirkwood/board-iconnect.c +++ b/arch/arm/mach-kirkwood/board-iconnect.c @@ -22,11 +22,3 @@ void __init iconnect_init(void) { kirkwood_ge00_init(&iconnect_ge00_data); } - -static int __init iconnect_pci_init(void) -{ - if (of_machine_is_compatible("iom,iconnect")) - kirkwood_pcie_init(KW_PCIE0); - return 0; -} -subsys_initcall(iconnect_pci_init); diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c index 4ec8b7ae784..348395238df 100644 --- a/arch/arm/mach-kirkwood/board-lsxl.c +++ b/arch/arm/mach-kirkwood/board-lsxl.c @@ -25,19 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -/* - * On the LS-XHL/LS-CHLv2, the shutdown process is following: - * - Userland monitors key events until the power switch goes to off position - * - The board reboots - * - U-boot starts and goes into an idle mode waiting for the user - * to move the switch to ON position - * - */ -static void lsxl_power_off(void) -{ - kirkwood_restart('h', NULL); -} - void __init lsxl_init(void) { /* @@ -46,7 +33,4 @@ void __init lsxl_init(void) kirkwood_ge00_init(&lsxl_ge00_data); kirkwood_ge01_init(&lsxl_ge01_data); - - /* register power-off method */ - pm_power_off = lsxl_power_off; } diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c index 7d6dc669e17..938712e248f 100644 --- a/arch/arm/mach-kirkwood/board-mplcec4.c +++ b/arch/arm/mach-kirkwood/board-mplcec4.c @@ -29,7 +29,6 @@ void __init mplcec4_init(void) */ kirkwood_ge00_init(&mplcec4_ge00_data); kirkwood_ge01_init(&mplcec4_ge01_data); - kirkwood_pcie_init(KW_PCIE0); } diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c deleted file mode 100644 index 55ade93b93b..00000000000 --- a/arch/arm/mach-kirkwood/board-nsa310.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-kirkwood/nsa-310-setup.c - * - * ZyXEL NSA-310 Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <mach/kirkwood.h> -#include <linux/of.h> -#include "common.h" - -static int __init nsa310_pci_init(void) -{ - if (of_machine_is_compatible("zyxel,nsa310")) - kirkwood_pcie_init(KW_PCIE0); - - return 0; -} - -subsys_initcall(nsa310_pci_init); diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c index fb42c20e273..341b82d9cad 100644 --- a/arch/arm/mach-kirkwood/board-readynas.c +++ b/arch/arm/mach-kirkwood/board-readynas.c @@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = { void __init netgear_readynas_init(void) { kirkwood_ge00_init(&netgear_readynas_ge00_data); - kirkwood_pcie_init(KW_PCIE0); } diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c new file mode 100644 index 00000000000..fa389373ca7 --- /dev/null +++ b/arch/arm/mach-kirkwood/board-sheevaplug.c @@ -0,0 +1,27 @@ +/* + * arch/arm/mach-kirkwood/board-sheevaplug.c + * + * Marvell Sheevaplug Reference Board Init for drivers not converted to + * flattened device tree yet. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mv643xx_eth.h> +#include "common.h" + +static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +void __init sheevaplug_dt_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_ge00_init(&sheevaplug_ge00_data); +} diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c index 4695d5f35fc..860f44ab457 100644 --- a/arch/arm/mach-kirkwood/board-ts219.c +++ b/arch/arm/mach-kirkwood/board-ts219.c @@ -23,7 +23,6 @@ #include <asm/mach/arch.h> #include <mach/kirkwood.h> #include "common.h" -#include "tsx1x-common.h" static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), @@ -38,6 +37,4 @@ void __init qnap_dt_ts219_init(void) qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); kirkwood_ge00_init(&qnap_ts219_ge00_data); - - pm_power_off = qnap_tsx1x_power_off; } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3892289756..7c72c725b71 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -598,6 +598,29 @@ void __init kirkwood_audio_init(void) } /***************************************************************************** + * CPU Frequency + ****************************************************************************/ +static struct resource kirkwood_cpufreq_resources[] = { + [0] = { + .start = CPU_CONTROL_PHYS, + .end = CPU_CONTROL_PHYS + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_cpufreq_device = { + .name = "kirkwood-cpufreq", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), + .resource = kirkwood_cpufreq_resources, +}; + +void __init kirkwood_cpufreq_init(void) +{ + platform_device_register(&kirkwood_cpufreq_device); +} + +/***************************************************************************** * General ****************************************************************************/ /* @@ -648,30 +671,6 @@ char * __init kirkwood_id(void) void __init kirkwood_setup_wins(void) { - /* - * The PCIe windows will no longer be statically allocated - * here once Kirkwood is migrated to the pci-mvebu driver. - */ - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_IO_PHYS_BASE, - KIRKWOOD_PCIE_IO_SIZE, - KIRKWOOD_PCIE_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_MEM_PHYS_BASE, - KIRKWOOD_PCIE_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_IO_PHYS_BASE, - KIRKWOOD_PCIE1_IO_SIZE, - KIRKWOOD_PCIE1_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_MEM_PHYS_BASE, - KIRKWOOD_PCIE1_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE); mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 21da3b1ebd7..1c09f3f93fb 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -51,6 +51,8 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); void kirkwood_audio_init(void); void kirkwood_cpuidle_init(void); +void kirkwood_cpufreq_init(void); + void kirkwood_restart(char, const char *); void kirkwood_clk_init(void); @@ -65,6 +67,11 @@ void guruplug_dt_init(void); #else static inline void guruplug_dt_init(void) {}; #endif +#ifdef CONFIG_MACH_SHEEVAPLUG_DT +void sheevaplug_dt_init(void); +#else +static inline void sheevaplug_dt_init(void) {}; +#endif #ifdef CONFIG_MACH_TS219_DT void qnap_dt_ts219_init(void); #else @@ -119,6 +126,12 @@ void km_kirkwood_init(void); static inline void km_kirkwood_init(void) {}; #endif +#ifdef CONFIG_MACH_DB88F628X_BP_DT +void db88f628x_init(void); +#else +static inline void db88f628x_init(void) {}; +#endif + #ifdef CONFIG_MACH_MPLCEC4_DT void mplcec4_init(void); #else diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c deleted file mode 100644 index 5a369fe7475..00000000000 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * arch/arm/mach-kirkwood/db88f6281-bp-setup.c - * - * Marvell DB-88F6281-BP Development Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/sizes.h> -#include <linux/platform_device.h> -#include <linux/mtd/partitions.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <linux/platform_data/mmc-mvsdio.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition db88f6281_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data db88f6281_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv_sata_platform_data db88f6281_sata_data = { - .n_ports = 2, -}; - -static struct mvsdio_platform_data db88f6281_mvsdio_data = { - .gpio_write_protect = 37, - .gpio_card_detect = 38, -}; - -static unsigned int db88f6281_mpp_config[] __initdata = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP37_GPIO, - MPP38_GPIO, - 0 -}; - -static void __init db88f6281_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(db88f6281_mpp_config); - - kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25); - kirkwood_ehci_init(); - kirkwood_ge00_init(&db88f6281_ge00_data); - kirkwood_sata_init(&db88f6281_sata_data); - kirkwood_uart0_init(); - kirkwood_sdio_init(&db88f6281_mvsdio_data); -} - -static int __init db88f6281_pci_init(void) -{ - if (machine_is_db88f6281_bp()) { - u32 dev, rev; - - kirkwood_pcie_id(&dev, &rev); - if (dev == MV88F6282_DEV_ID) - kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0); - else - kirkwood_pcie_init(KW_PCIE0); - } - return 0; -} -subsys_initcall(db88f6281_pci_init); - -MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") - /* Maintainer: Saeed Bishara <saeed@marvell.com> */ - .atag_offset = 0x100, - .init_machine = db88f6281_init, - .map_io = kirkwood_map_io, - .init_early = kirkwood_init_early, - .init_irq = kirkwood_init_irq, - .init_time = kirkwood_timer_init, - .restart = kirkwood_restart, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 5c82b7dce4e..d4cbe5e81bb 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -17,6 +17,7 @@ #define CPU_CONFIG_ERROR_PROP 0x00000004 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) #define CPU_RESET 0x00000002 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) @@ -69,6 +70,7 @@ #define CGC_RUNIT (1 << 7) #define CGC_XOR0 (1 << 8) #define CGC_AUDIO (1 << 9) +#define CGC_POWERSAVE (1 << 11) #define CGC_SATA0 (1 << 14) #define CGC_SATA1 (1 << 15) #define CGC_XOR1 (1 << 16) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 7f43e6c2f8c..ddcb09f5bdd 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -12,6 +12,7 @@ #include <linux/pci.h> #include <linux/slab.h> #include <linux/clk.h> +#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> @@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base) void __init kirkwood_pcie_init(unsigned int portmask) { + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_IO_PHYS_BASE, + KIRKWOOD_PCIE_IO_SIZE, + KIRKWOOD_PCIE_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie0.0", + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_IO_PHYS_BASE, + KIRKWOOD_PCIE1_IO_SIZE, + KIRKWOOD_PCIE1_IO_BUS_BASE, + MVEBU_MBUS_PCI_IO); + mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE, + MVEBU_MBUS_NO_REMAP, + MVEBU_MBUS_PCI_MEM); + vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; if (portmask & KW_PCIE0) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index fceb093b949..614e41e7881 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -48,9 +48,7 @@ config ARCH_MSM8X60 select CPU_V7 select GPIO_MSM_V2 select HAVE_SMP - select MSM_GPIOMUX select MSM_SCM if SMP - select MSM_V2_TLMM select USE_OF config ARCH_MSM8960 @@ -58,9 +56,8 @@ config ARCH_MSM8960 select ARM_GIC select CPU_V7 select HAVE_SMP - select MSM_GPIOMUX + select GPIO_MSM_V2 select MSM_SCM if SMP - select MSM_V2_TLMM select USE_OF config MSM_HAS_DEBUG_UART_HS @@ -124,10 +121,10 @@ config MSM_SMD bool config MSM_GPIOMUX - bool - -config MSM_V2_TLMM - bool + depends on !(ARCH_MSM8X60 || ARCH_MSM8960) + bool "MSM V1 TLMM GPIOMUX architecture" + help + Support for MSM V1 TLMM GPIOMUX architecture. config MSM_SCM bool diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 17519faf082..1a26d04c940 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -27,7 +27,5 @@ obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o - -obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o -obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o -obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o +obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o +obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c index 7dcfc5300bb..492f5cd87b0 100644 --- a/arch/arm/mach-msm/board-dt-8660.c +++ b/arch/arm/mach-msm/board-dt-8660.c @@ -11,7 +11,6 @@ */ #include <linux/init.h> -#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_platform.h> @@ -44,7 +43,6 @@ static const char *msm8x60_fluid_match[] __initdata = { DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8x60_io, - .init_irq = irqchip_init, .init_machine = msm8x60_dt_init, .init_late = msm8x60_init_late, .init_time = msm_dt_timer_init, diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c index 73019363ffa..bb5530957c4 100644 --- a/arch/arm/mach-msm/board-dt-8960.c +++ b/arch/arm/mach-msm/board-dt-8960.c @@ -11,7 +11,6 @@ */ #include <linux/init.h> -#include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> @@ -31,7 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = { DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8960_io, - .init_irq = irqchip_init, .init_time = msm_dt_timer_init, .init_machine = msm_dt_init, .dt_compat = msm8960_dt_match, diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c index 4886404d42f..b0fbdf1cbdd 100644 --- a/arch/arm/mach-msm/clock-debug.c +++ b/arch/arm/mach-msm/clock-debug.c @@ -104,7 +104,7 @@ int __init clock_debug_add(struct clk *clock) if (!debugfs_base) return -ENOMEM; - strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1); + strlcpy(temp, clock->dbg_name, ARRAY_SIZE(temp)); for (ptr = temp; *ptr; ptr++) *ptr = tolower(*ptr); diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h deleted file mode 100644 index a9bab53dddf..00000000000 --- a/arch/arm/mach-msm/core.h +++ /dev/null @@ -1,2 +0,0 @@ -extern struct smp_operations msm_smp_ops; -extern void msm_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c deleted file mode 100644 index 7b380b31bd0..00000000000 --- a/arch/arm/mach-msm/gpiomux-8x60.c +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ -#include "gpiomux.h" - -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c deleted file mode 100644 index 273396d2b12..00000000000 --- a/arch/arm/mach-msm/gpiomux-v2.c +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ -#include <linux/io.h> -#include <mach/msm_iomap.h> -#include "gpiomux.h" - -void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val) -{ - writel(val & ~GPIOMUX_CTL_MASK, - MSM_TLMM_BASE + 0x1000 + (0x10 * gpio)); -} diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h deleted file mode 100644 index 3bf10e7f038..00000000000 --- a/arch/arm/mach-msm/gpiomux-v2.h +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ -#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H -#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H - -#define GPIOMUX_NGPIOS 173 - -typedef u16 gpiomux_config_t; - -enum { - GPIOMUX_DRV_2MA = 0UL << 6, - GPIOMUX_DRV_4MA = 1UL << 6, - GPIOMUX_DRV_6MA = 2UL << 6, - GPIOMUX_DRV_8MA = 3UL << 6, - GPIOMUX_DRV_10MA = 4UL << 6, - GPIOMUX_DRV_12MA = 5UL << 6, - GPIOMUX_DRV_14MA = 6UL << 6, - GPIOMUX_DRV_16MA = 7UL << 6, -}; - -enum { - GPIOMUX_FUNC_GPIO = 0UL << 2, - GPIOMUX_FUNC_1 = 1UL << 2, - GPIOMUX_FUNC_2 = 2UL << 2, - GPIOMUX_FUNC_3 = 3UL << 2, - GPIOMUX_FUNC_4 = 4UL << 2, - GPIOMUX_FUNC_5 = 5UL << 2, - GPIOMUX_FUNC_6 = 6UL << 2, - GPIOMUX_FUNC_7 = 7UL << 2, - GPIOMUX_FUNC_8 = 8UL << 2, - GPIOMUX_FUNC_9 = 9UL << 2, - GPIOMUX_FUNC_A = 10UL << 2, - GPIOMUX_FUNC_B = 11UL << 2, - GPIOMUX_FUNC_C = 12UL << 2, - GPIOMUX_FUNC_D = 13UL << 2, - GPIOMUX_FUNC_E = 14UL << 2, - GPIOMUX_FUNC_F = 15UL << 2, -}; - -enum { - GPIOMUX_PULL_NONE = 0UL, - GPIOMUX_PULL_DOWN = 1UL, - GPIOMUX_PULL_KEEPER = 2UL, - GPIOMUX_PULL_UP = 3UL, -}; - -#endif diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c index 53af21abd15..2b8e2d21708 100644 --- a/arch/arm/mach-msm/gpiomux.c +++ b/arch/arm/mach-msm/gpiomux.c @@ -17,9 +17,24 @@ #include <linux/module.h> #include <linux/spinlock.h> #include "gpiomux.h" +#include "proc_comm.h" static DEFINE_SPINLOCK(gpiomux_lock); +static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val) +{ + unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) | + ((gpio & 0x3ff) << 4); + unsigned tlmm_disable = 0; + int rc; + + rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, + &tlmm_config, &tlmm_disable); + if (rc) + pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n", + __func__, rc, tlmm_config, tlmm_disable); +} + int msm_gpiomux_write(unsigned gpio, gpiomux_config_t active, gpiomux_config_t suspended) diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h index 00459f6ee13..8e82f41a892 100644 --- a/arch/arm/mach-msm/gpiomux.h +++ b/arch/arm/mach-msm/gpiomux.h @@ -20,12 +20,7 @@ #include <linux/bitops.h> #include <linux/errno.h> #include <mach/msm_gpiomux.h> - -#if defined(CONFIG_MSM_V2_TLMM) -#include "gpiomux-v2.h" -#else #include "gpiomux-v1.h" -#endif /** * struct msm_gpiomux_config: gpiomux settings for one gpio line. diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index 9819a556aca..7bca8d7108d 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -32,13 +32,6 @@ * */ - -#define MSM8960_QGIC_DIST_PHYS 0x02000000 -#define MSM8960_QGIC_DIST_SIZE SZ_4K - -#define MSM8960_QGIC_CPU_PHYS 0x02002000 -#define MSM8960_QGIC_CPU_SIZE SZ_4K - #define MSM8960_TMR_PHYS 0x0200A000 #define MSM8960_TMR_SIZE SZ_4K diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 199372e62de..75a7b62c1c7 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -35,12 +35,6 @@ * */ -#define MSM8X60_QGIC_DIST_PHYS 0x02080000 -#define MSM8X60_QGIC_DIST_SIZE SZ_4K - -#define MSM8X60_QGIC_CPU_PHYS 0x02081000 -#define MSM8X60_QGIC_CPU_SIZE SZ_4K - #define MSM_TLMM_BASE IOMEM(0xF0004000) #define MSM_TLMM_PHYS 0x00800000 #define MSM_TLMM_SIZE SZ_16K diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 2ab7cf0919b..c56e81ffdcd 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -62,8 +62,6 @@ /* Virtual addresses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) -#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) -#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) #define MSM_TMR_BASE IOMEM(0xF0200000) #define MSM_TMR0_BASE IOMEM(0xF0201000) #define MSM_GPIO1_BASE IOMEM(0xE0003000) diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 123ef9cbce1..efa113e4de8 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -107,8 +107,6 @@ void __init msm_map_qsd8x50_io(void) #ifdef CONFIG_ARCH_MSM8X60 static struct map_desc msm8x60_io_desc[] __initdata = { - MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), - MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), MSM_CHIP_DEVICE(TMR, MSM8X60), MSM_CHIP_DEVICE(TMR0, MSM8X60), #ifdef CONFIG_DEBUG_MSM8660_UART @@ -124,8 +122,6 @@ void __init msm_map_msm8x60_io(void) #ifdef CONFIG_ARCH_MSM8960 static struct map_desc msm8960_io_desc[] __initdata = { - MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), - MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), MSM_CHIP_DEVICE(TMR, MSM8960), MSM_CHIP_DEVICE(TMR0, MSM8960), #ifdef CONFIG_DEBUG_MSM8960_UART diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 80a8bcacd9d..9eb63d72460 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -10,12 +10,11 @@ config ARCH_MVEBU select PLAT_ORION select SPARSE_IRQ select CLKDEV_LOOKUP - select MVEBU_CLK_CORE - select MVEBU_CLK_CPU - select MVEBU_CLK_GATING select MVEBU_MBUS select ZONE_DMA if ARM_LPAE select ARCH_REQUIRE_GPIOLIB + select MIGHT_HAVE_PCI + select PCI_QUIRKS if PCI if ARCH_MVEBU @@ -30,6 +29,7 @@ config MACH_ARMADA_370_XP config MACH_ARMADA_370 bool "Marvell Armada 370 boards" + select ARMADA_370_CLK select MACH_ARMADA_370_XP select PINCTRL_ARMADA_370 help @@ -38,6 +38,7 @@ config MACH_ARMADA_370 config MACH_ARMADA_XP bool "Marvell Armada XP boards" + select ARMADA_XP_CLK select MACH_ARMADA_370_XP select PINCTRL_ARMADA_XP help diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 1c48890bb72..97cbb802191 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -14,13 +14,13 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/io.h> #include <linux/time-armada-370-xp.h> -#include <linux/clk/mvebu.h> #include <linux/dma-mapping.h> #include <linux/mbus.h> -#include <linux/irqchip.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -29,45 +29,49 @@ #include "common.h" #include "coherency.h" -static struct map_desc armada_370_xp_io_desc[] __initdata = { - { - .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE), - .length = ARMADA_370_XP_REGS_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init armada_370_xp_map_io(void) +static void __init armada_370_xp_map_io(void) { - iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); + debug_ll_io_init(); } -void __init armada_370_xp_timer_and_clk_init(void) -{ - mvebu_clocks_init(); - armada_370_xp_timer_init(); -} +/* + * This initialization will be replaced by a DT-based + * initialization once the mvebu-mbus driver gains DT support. + */ -void __init armada_370_xp_init_early(void) +#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000 +#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 +#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180 +#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 + +static void __init armada_370_xp_mbus_init(void) { char *mbus_soc_name; + struct device_node *dn; + const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS); + const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS); - /* - * This initialization will be replaced by a DT-based - * initialization once the mvebu-mbus driver gains DT support. - */ if (of_machine_is_compatible("marvell,armada370")) mbus_soc_name = "marvell,armada370-mbus"; else mbus_soc_name = "marvell,armadaxp-mbus"; + dn = of_find_node_by_name(NULL, "internal-regs"); + BUG_ON(!dn); + mvebu_mbus_init(mbus_soc_name, - ARMADA_370_XP_MBUS_WINS_BASE, + of_translate_address(dn, &mbus_wins_offs), ARMADA_370_XP_MBUS_WINS_SIZE, - ARMADA_370_XP_SDRAM_WINS_BASE, + of_translate_address(dn, &sdram_wins_offs), ARMADA_370_XP_SDRAM_WINS_SIZE); +} +static void __init armada_370_xp_timer_and_clk_init(void) +{ + of_clk_init(NULL); + armada_370_xp_timer_init(); + coherency_init(); + armada_370_xp_mbus_init(); #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif @@ -76,7 +80,6 @@ void __init armada_370_xp_init_early(void) static void __init armada_370_xp_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - coherency_init(); } static const char * const armada_370_xp_dt_compat[] = { @@ -88,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .smp = smp_ops(armada_xp_smp_ops), .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, - .init_early = armada_370_xp_init_early, - .init_irq = irqchip_init, .init_time = armada_370_xp_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index 2070e1b4f34..c612b2c4ed6 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -15,16 +15,6 @@ #ifndef __MACH_ARMADA_370_XP_H #define __MACH_ARMADA_370_XP_H -#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000) -#define ARMADA_370_XP_REGS_SIZE SZ_1M - -/* These defines can go away once mvebu-mbus has a DT binding */ -#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000) -#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100 -#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180) -#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20 - #ifdef CONFIG_SMP #include <linux/cpumask.h> diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 8278960066c..be117591f7f 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -25,16 +25,11 @@ #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <asm/smp_plat.h> +#include <asm/cacheflush.h> #include "armada-370-xp.h" -/* - * Some functions in this file are called very early during SMP - * initialization. At that time the device tree framework is not yet - * ready, and it is not possible to get the register address to - * ioremap it. That's why the pointer below is given with an initial - * value matching its virtual mapping - */ -static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200; +unsigned long __cpuinitdata coherency_phys_base; +static void __iomem *coherency_base; static void __iomem *coherency_cpu_base; /* Coherency fabric registers */ @@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = { { /* end of list */ }, }; -#ifdef CONFIG_SMP -int coherency_get_cpu_count(void) -{ - int reg, cnt; - - reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET); - cnt = (reg & 0xF) + 1; - - return cnt; -} -#endif - /* Function defined in coherency_ll.S */ int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id); @@ -143,13 +126,31 @@ int __init coherency_init(void) np = of_find_matching_node(NULL, of_coherency_table); if (np) { + struct resource res; pr_info("Initializing Coherency fabric\n"); + of_address_to_resource(np, 0, &res); + coherency_phys_base = res.start; + /* + * Ensure secondary CPUs will see the updated value, + * which they read before they join the coherency + * fabric, and therefore before they are coherent with + * the boot CPU cache. + */ + sync_cache_w(&coherency_phys_base); coherency_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 1); set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); - bus_register_notifier(&platform_bus_type, - &mvebu_hwcc_platform_nb); } return 0; } + +static int __init coherency_late_init(void) +{ + if (of_find_matching_node(NULL, of_coherency_table)) + bus_register_notifier(&platform_bus_type, + &mvebu_hwcc_platform_nb); + return 0; +} + +postcore_initcall(coherency_late_init); diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index 2f428137f6f..df33ad8a6c0 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -14,10 +14,6 @@ #ifndef __MACH_370_XP_COHERENCY_H #define __MACH_370_XP_COHERENCY_H -#ifdef CONFIG_SMP -int coherency_get_cpu_count(void); -#endif - int set_cpu_coherent(int cpu_id, int smp_group_id); int coherency_init(void); diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index aa27bc2ffb6..98defd5e92c 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -15,6 +15,8 @@ #ifndef __ARCH_MVEBU_COMMON_H #define __ARCH_MVEBU_COMMON_H +#define ARMADA_XP_MAX_CPUS 4 + void mvebu_restart(char mode, const char *cmd); void armada_370_xp_init_irq(void); diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index a06e0ede8c0..7147300c8af 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -21,12 +21,6 @@ #include <linux/linkage.h> #include <linux/init.h> -/* - * At this stage the secondary CPUs don't have acces yet to the MMU, so - * we have to provide physical addresses - */ -#define ARMADA_XP_CFB_BASE 0xD0020200 - __CPUINIT /* @@ -35,15 +29,21 @@ * startup */ ENTRY(armada_xp_secondary_startup) + /* Get coherency fabric base physical address */ + adr r0, 1f + ldr r1, [r0] + ldr r0, [r0, r1] /* Read CPU id */ mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF /* Add CPU to coherency fabric */ - ldr r0, =ARMADA_XP_CFB_BASE - bl ll_set_cpu_coherent b secondary_startup ENDPROC(armada_xp_secondary_startup) + + .align 2 +1: + .long coherency_phys_base - . diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 875ea748391..93f2f3ab45f 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu, static void __init armada_xp_smp_init_cpus(void) { + struct device_node *np; unsigned int i, ncores; - ncores = coherency_get_cpu_count(); + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) + panic("No 'cpus' node found\n"); + + ncores = of_get_child_count(np); + if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS) + panic("Invalid number of CPUs in DT\n"); /* Limit possible CPUs to defconfig */ if (ncores > nr_cpu_ids) { diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 59c30ef5679..616fe0210da 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -3,7 +3,6 @@ config SOC_IMX23 select ARM_AMBA select ARM_CPU_SUSPEND if PM select CPU_ARM926T - select HAVE_PWM select PINCTRL_IMX23 config SOC_IMX28 @@ -12,7 +11,6 @@ config SOC_IMX28 select ARM_CPU_SUSPEND if PM select CPU_ARM926T select HAVE_CAN_FLEXCAN if CAN - select HAVE_PWM select PINCTRL_IMX28 config ARCH_MXS diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index ba227cb2c93..7fa611c1b28 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -544,7 +544,6 @@ static const char *mxs_dt_compat[] __initdata = { }; DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") - .map_io = debug_ll_io_init, .handle_irq = icoll_handle_irq, .init_time = mxs_timer_init, .init_machine = mxs_machine_init, diff --git a/arch/arm/mach-mxs/pm.h b/arch/arm/mach-mxs/pm.h index f57e7cdece2..09d77b00a96 100644 --- a/arch/arm/mach-mxs/pm.h +++ b/arch/arm/mach-mxs/pm.h @@ -9,6 +9,10 @@ #ifndef __ARCH_MXS_PM_H #define __ARCH_MXS_PM_H +#ifdef CONFIG_PM void mxs_pm_init(void); +#else +#define mxs_pm_init NULL +#endif #endif diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 89e2c03db17..2df209ed1a0 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -25,7 +25,6 @@ #include <linux/slab.h> #include <linux/irq.h> #include <linux/dma-mapping.h> -#include <linux/irqchip.h> #include <linux/platform_data/clk-nomadik.h> #include <linux/clocksource.h> #include <linux/of_irq.h> @@ -260,7 +259,6 @@ static const char * cpu8815_board_compat[] = { DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815") .map_io = cpu8815_map_io, - .init_irq = irqchip_init, .init_time = cpu8815_timer_init_of, .init_machine = cpu8815_init_of, .restart = cpu8815_restart, diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 0dac3d239e3..fd90cafc2e3 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -41,7 +41,6 @@ #include <mach/mux.h> #include <linux/omap-dma.h> #include <mach/tc.h> -#include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> #include <mach/flash.h> @@ -50,7 +49,6 @@ #include "common.h" #include "board-h2.h" -#include "dma.h" /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ #define OMAP1610_ETHR_START 0x04000300 @@ -276,39 +274,6 @@ static struct platform_device h2_kp_device = { .resource = h2_kp_resources, }; -#define H2_IRDA_FIRSEL_GPIO_PIN 17 - -static struct omap_irda_config h2_irda_data = { - .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource h2_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 irda_dmamask = 0xffffffff; - -static struct platform_device h2_irda_device = { - .name = "omapirda", - .id = 0, - .dev = { - .platform_data = &h2_irda_data, - .dma_mask = &irda_dmamask, - }, - .num_resources = ARRAY_SIZE(h2_irda_resources), - .resource = h2_irda_resources, -}; - static struct gpio_led h2_gpio_led_pins[] = { { .name = "h2:red", @@ -339,7 +304,6 @@ static struct platform_device *h2_devices[] __initdata = { &h2_nor_device, &h2_nand_device, &h2_smc91x_device, - &h2_irda_device, &h2_kp_device, &h2_gpio_leds, }; diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 62a15e289c7..91449c5cb70 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -234,16 +234,26 @@ static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = { { I2C_BOARD_INFO("retu-mfd", 0x01), }, + { + I2C_BOARD_INFO("tahvo-mfd", 0x02), + }, }; static void __init nokia770_cbus_init(void) { const int retu_irq_gpio = 62; + const int tahvo_irq_gpio = 40; if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) return; + if (gpio_request_one(tahvo_irq_gpio, GPIOF_IN, "Tahvo IRQ")) { + gpio_free(retu_irq_gpio); + return; + } irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(tahvo_irq_gpio), IRQ_TYPE_EDGE_RISING); nokia770_i2c_board_info_2[0].irq = gpio_to_irq(retu_irq_gpio); + nokia770_i2c_board_info_2[1].irq = gpio_to_irq(tahvo_irq_gpio); i2c_register_board_info(2, nokia770_i2c_board_info_2, ARRAY_SIZE(nokia770_i2c_board_info_2)); platform_device_register(&nokia770_cbus_device); diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 845a1a7aef9..3b8e98f4353 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -38,14 +38,12 @@ #include <mach/mux.h> #include <mach/tc.h> #include <linux/omap-dma.h> -#include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> #include <mach/usb.h> #include "common.h" -#include "dma.h" #define PALMTE_USBDETECT_GPIO 0 #define PALMTE_USB_OR_DC_GPIO 1 @@ -167,40 +165,11 @@ static struct platform_device palmte_backlight_device = { }, }; -static struct omap_irda_config palmte_irda_config = { - .transceiver_cap = IR_SIRMODE, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource palmte_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device palmte_irda_device = { - .name = "omapirda", - .id = -1, - .dev = { - .platform_data = &palmte_irda_config, - }, - .num_resources = ARRAY_SIZE(palmte_irda_resources), - .resource = palmte_irda_resources, -}; - static struct platform_device *palmte_devices[] __initdata = { &palmte_rom_device, &palmte_kp_device, &palmte_lcd_device, &palmte_backlight_device, - &palmte_irda_device, }; static struct omap_usb_config palmte_usb_config __initdata = { diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 65a4a3e357f..ca501208825 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -38,14 +38,12 @@ #include <mach/mux.h> #include <linux/omap-dma.h> #include <mach/tc.h> -#include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> #include <mach/usb.h> #include "common.h" -#include "dma.h" #define PALMTT_USBDETECT_GPIO 0 #define PALMTT_CABLE_GPIO 1 @@ -163,33 +161,6 @@ static struct platform_device palmtt_lcd_device = { .name = "lcd_palmtt", .id = -1, }; -static struct omap_irda_config palmtt_irda_config = { - .transceiver_cap = IR_SIRMODE, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource palmtt_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device palmtt_irda_device = { - .name = "omapirda", - .id = -1, - .dev = { - .platform_data = &palmtt_irda_config, - }, - .num_resources = ARRAY_SIZE(palmtt_irda_resources), - .resource = palmtt_irda_resources, -}; static struct platform_device palmtt_spi_device = { .name = "spi_palmtt", @@ -234,7 +205,6 @@ static struct platform_device *palmtt_devices[] __initdata = { &palmtt_flash_device, &palmtt_kp_device, &palmtt_lcd_device, - &palmtt_irda_device, &palmtt_spi_device, &palmtt_backlight_device, &palmtt_led_device, diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 01c970071fd..470e12d6736 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -40,14 +40,12 @@ #include <mach/mux.h> #include <linux/omap-dma.h> #include <mach/tc.h> -#include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> #include <mach/usb.h> #include "common.h" -#include "dma.h" #define PALMZ71_USBDETECT_GPIO 0 #define PALMZ71_PENIRQ_GPIO 6 @@ -153,34 +151,6 @@ static struct platform_device palmz71_lcd_device = { .id = -1, }; -static struct omap_irda_config palmz71_irda_config = { - .transceiver_cap = IR_SIRMODE, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource palmz71_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device palmz71_irda_device = { - .name = "omapirda", - .id = -1, - .dev = { - .platform_data = &palmz71_irda_config, - }, - .num_resources = ARRAY_SIZE(palmz71_irda_resources), - .resource = palmz71_irda_resources, -}; - static struct platform_device palmz71_spi_device = { .name = "spi_palmz71", .id = -1, @@ -202,7 +172,6 @@ static struct platform_device *devices[] __initdata = { &palmz71_rom_device, &palmz71_kp_device, &palmz71_lcd_device, - &palmz71_irda_device, &palmz71_spi_device, &palmz71_backlight_device, }; diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 9732a98f3e0..0a8d3349149 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -37,7 +37,6 @@ #include <mach/flash.h> #include <mach/mux.h> #include <linux/omap-dma.h> -#include <mach/irda.h> #include <mach/tc.h> #include <mach/board-sx1.h> @@ -45,7 +44,6 @@ #include <mach/usb.h> #include "common.h" -#include "dma.h" /* Write to I2C device */ int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) @@ -228,39 +226,6 @@ static struct platform_device sx1_kp_device = { .resource = sx1_kp_resources, }; -/*----------- IRDA -------------------------*/ - -static struct omap_irda_config sx1_irda_data = { - .transceiver_cap = IR_SIRMODE, - .rx_channel = OMAP_DMA_UART3_RX, - .tx_channel = OMAP_DMA_UART3_TX, - .dest_start = UART3_THR, - .src_start = UART3_RHR, - .tx_trigger = 0, - .rx_trigger = 0, -}; - -static struct resource sx1_irda_resources[] = { - [0] = { - .start = INT_UART3, - .end = INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 irda_dmamask = 0xffffffff; - -static struct platform_device sx1_irda_device = { - .name = "omapirda", - .id = 0, - .dev = { - .platform_data = &sx1_irda_data, - .dma_mask = &irda_dmamask, - }, - .num_resources = ARRAY_SIZE(sx1_irda_resources), - .resource = sx1_irda_resources, -}; - /*----------- MTD -------------------------*/ static struct mtd_partition sx1_partitions[] = { @@ -366,7 +331,6 @@ static struct omap_lcd_config sx1_lcd_config __initdata = { static struct platform_device *sx1_devices[] __initdata = { &sx1_flash_device, &sx1_kp_device, - &sx1_irda_device, }; /*-----------------------------------------*/ diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 0af635205e8..325e6030095 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -30,7 +30,6 @@ #include "common.h" #include "clock.h" -#include "dma.h" #include "mmc.h" #include "sram.h" @@ -223,16 +222,16 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, case 0: base = OMAP1_MMC1_BASE; irq = INT_MMC; - rx_req = OMAP_DMA_MMC_RX; - tx_req = OMAP_DMA_MMC_TX; + rx_req = 22; + tx_req = 21; break; case 1: if (!cpu_is_omap16xx()) return; base = OMAP1_MMC2_BASE; irq = INT_1610_MMC2; - rx_req = OMAP_DMA_MMC2_RX; - tx_req = OMAP_DMA_MMC2_TX; + rx_req = 55; + tx_req = 54; break; default: continue; diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index a94b3a718d1..5bb8ce86d54 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -30,8 +30,6 @@ #include <mach/irqs.h> -#include "dma.h" - #define OMAP1_DMA_BASE (0xfffed800) #define OMAP1_LOGICAL_DMA_CH_COUNT 17 #define OMAP1_DMA_STRIDE 0x40 diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h deleted file mode 100644 index d05909c9671..00000000000 --- a/arch/arm/mach-omap1/dma.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * OMAP1 DMA channel definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __OMAP1_DMA_CHANNEL_H -#define __OMAP1_DMA_CHANNEL_H - -/* DMA channels for omap1 */ -#define OMAP_DMA_NO_DEVICE 0 -#define OMAP_DMA_MCBSP1_TX 8 -#define OMAP_DMA_MCBSP1_RX 9 -#define OMAP_DMA_MCBSP3_TX 10 -#define OMAP_DMA_MCBSP3_RX 11 -#define OMAP_DMA_MCBSP2_TX 16 -#define OMAP_DMA_MCBSP2_RX 17 -#define OMAP_DMA_UART3_TX 18 -#define OMAP_DMA_UART3_RX 19 -#define OMAP_DMA_CAMERA_IF_RX 20 -#define OMAP_DMA_MMC_TX 21 -#define OMAP_DMA_MMC_RX 22 -#define OMAP_DMA_USB_W2FC_RX0 26 -#define OMAP_DMA_USB_W2FC_TX0 29 - -/* These are only for 1610 */ -#define OMAP_DMA_MMC2_TX 54 -#define OMAP_DMA_MMC2_RX 55 - -#endif /* __OMAP1_DMA_CHANNEL_H */ diff --git a/arch/arm/mach-omap1/include/mach/irda.h b/arch/arm/mach-omap1/include/mach/irda.h deleted file mode 100644 index 40f60339d1c..00000000000 --- a/arch/arm/mach-omap1/include/mach/irda.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/irda.h - * - * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_ARCH_IRDA_H -#define ASMARM_ARCH_IRDA_H - -/* board specific transceiver capabilities */ - -#define IR_SEL 1 /* Selects IrDA */ -#define IR_SIRMODE 2 -#define IR_FIRMODE 4 -#define IR_MIRMODE 8 - -struct omap_irda_config { - int transceiver_cap; - int (*transceiver_mode)(struct device *dev, int mode); - int (*select_irda)(struct device *dev, int state); - int rx_channel; - int tx_channel; - unsigned long dest_start; - unsigned long src_start; - int tx_trigger; - int rx_trigger; - int mode; -}; - -#endif diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c index 77924be37d4..26a2b01c7c4 100644 --- a/arch/arm/mach-omap1/lcd_dma.c +++ b/arch/arm/mach-omap1/lcd_dma.c @@ -32,8 +32,6 @@ #include <mach/hardware.h> #include <mach/lcdc.h> -#include "dma.h" - int omap_lcd_dma_running(void) { /* diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index b0d4723c9a9..8ed67f8d176 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -27,7 +27,6 @@ #include <mach/irqs.h> #include "iomap.h" -#include "dma.h" #define DPS_RSTCT2_PER_EN (1 << 0) #define DSP_RSTCT2_WD_PER_EN (1 << 1) @@ -114,12 +113,12 @@ struct resource omap7xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP1_RX, + .start = 9, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP1_TX, + .start = 8, .flags = IORESOURCE_DMA, }, }, @@ -141,12 +140,12 @@ struct resource omap7xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP3_RX, + .start = 11, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP3_TX, + .start = 10, .flags = IORESOURCE_DMA, }, }, @@ -191,12 +190,12 @@ struct resource omap15xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP1_RX, + .start = 9, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP1_TX, + .start = 8, .flags = IORESOURCE_DMA, }, }, @@ -218,12 +217,12 @@ struct resource omap15xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP2_RX, + .start = 17, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP2_TX, + .start = 16, .flags = IORESOURCE_DMA, }, }, @@ -245,12 +244,12 @@ struct resource omap15xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP3_RX, + .start = 11, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP3_TX, + .start = 10, .flags = IORESOURCE_DMA, }, }, @@ -298,12 +297,12 @@ struct resource omap16xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP1_RX, + .start = 9, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP1_TX, + .start = 8, .flags = IORESOURCE_DMA, }, }, @@ -325,12 +324,12 @@ struct resource omap16xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP2_RX, + .start = 17, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP2_TX, + .start = 16, .flags = IORESOURCE_DMA, }, }, @@ -352,12 +351,12 @@ struct resource omap16xx_mcbsp_res[][6] = { }, { .name = "rx", - .start = OMAP_DMA_MCBSP3_RX, + .start = 11, .flags = IORESOURCE_DMA, }, { .name = "tx", - .start = OMAP_DMA_MCBSP3_TX, + .start = 10, .flags = IORESOURCE_DMA, }, }, diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index f49cd51e162..1fdb4621659 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -17,6 +17,7 @@ config ARCH_OMAP2PLUS select PROC_DEVICETREE if PROC_FS select SOC_BUS select SPARSE_IRQ + select TI_PRIV_EDMA select USE_OF help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 @@ -149,6 +150,14 @@ config SOC_AM33XX select MULTI_IRQ_HANDLER select COMMON_CLK +config SOC_AM43XX + bool "TI AM43x" + select CPU_V7 + select MULTI_IRQ_HANDLER + select ARM_GIC + select COMMON_CLK + select MACH_OMAP_GENERIC + config OMAP_PACKAGE_ZAF bool @@ -167,12 +176,6 @@ config OMAP_PACKAGE_CUS config OMAP_PACKAGE_CBP bool -config OMAP_PACKAGE_CBL - bool - -config OMAP_PACKAGE_CBS - bool - comment "OMAP Board Type" depends on ARCH_OMAP2PLUS @@ -378,22 +381,6 @@ config MACH_TI8148EVM depends on SOC_TI81XX default y -config MACH_OMAP_4430SDP - bool "OMAP 4430 SDP board" - default y - depends on ARCH_OMAP4 - select OMAP_PACKAGE_CBL - select OMAP_PACKAGE_CBS - select REGULATOR_FIXED_VOLTAGE if REGULATOR - -config MACH_OMAP4_PANDA - bool "OMAP4 Panda Board" - default y - depends on ARCH_OMAP4 - select OMAP_PACKAGE_CBL - select OMAP_PACKAGE_CBS - select REGULATOR_FIXED_VOLTAGE if REGULATOR - config OMAP3_EMU bool "OMAP3 debugging peripherals" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 55a9d677768..8e8c605ebef 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -34,10 +35,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o smp-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o smp-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -omap-4-5-common = omap4-common.o omap-wakeupgen.o \ - sleep44xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) -obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) +omap-4-5-common = omap4-common.o omap-wakeupgen.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o +obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -58,12 +59,13 @@ obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o +obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o +obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o # Pin multiplexing obj-$(CONFIG_SOC_OMAP2420) += mux2420.o obj-$(CONFIG_SOC_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o -obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o @@ -110,6 +112,7 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o +obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ prcm_mpu44xx.o prminst44xx.o \ vc44xx_data.o vp44xx_data.o @@ -125,8 +128,9 @@ obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) +obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -140,7 +144,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o +obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) +obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -155,7 +161,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o +obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) +obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o @@ -198,6 +206,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o +obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o @@ -251,8 +260,6 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o -obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o -obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h index 43296c1af9e..5eef093e673 100644 --- a/arch/arm/mach-omap2/am33xx.h +++ b/arch/arm/mach-omap2/am33xx.h @@ -21,6 +21,7 @@ #define AM33XX_SCM_BASE 0x44E10000 #define AM33XX_CTRL_BASE AM33XX_SCM_BASE #define AM33XX_PRCM_BASE 0x44E00000 +#define AM43XX_PRCM_BASE 0x44DF0000 #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC) #endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c deleted file mode 100644 index 56a9a4f855c..00000000000 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ /dev/null @@ -1,765 +0,0 @@ -/* - * Board support file for OMAP4430 SDP. - * - * Copyright (C) 2009 Texas Instruments - * - * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Based on mach-omap2/board-3430sdp.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> -#include <linux/spi/spi.h> -#include <linux/i2c/twl.h> -#include <linux/mfd/twl6040.h> -#include <linux/gpio_keys.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/pwm.h> -#include <linux/leds.h> -#include <linux/leds_pwm.h> -#include <linux/pwm_backlight.h> -#include <linux/irqchip/arm-gic.h> -#include <linux/platform_data/omap4-keypad.h> -#include <linux/usb/musb.h> -#include <linux/usb/phy.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "omap4-keypad.h" -#include <linux/wl12xx.h> -#include <linux/platform_data/omap-abe-twl6040.h> - -#include "soc.h" -#include "mux.h" -#include "mmc.h" -#include "hsmmc.h" -#include "control.h" -#include "common-board-devices.h" -#include "dss-common.h" - -#define ETH_KS8851_IRQ 34 -#define ETH_KS8851_POWER_ON 48 -#define ETH_KS8851_QUART 138 -#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 -#define OMAP4_SFH7741_ENABLE_GPIO 188 - -#define GPIO_WIFI_PMENA 54 -#define GPIO_WIFI_IRQ 53 - -static const int sdp4430_keymap[] = { - KEY(0, 0, KEY_E), - KEY(0, 1, KEY_R), - KEY(0, 2, KEY_T), - KEY(0, 3, KEY_HOME), - KEY(0, 4, KEY_F5), - KEY(0, 5, KEY_UNKNOWN), - KEY(0, 6, KEY_I), - KEY(0, 7, KEY_LEFTSHIFT), - - KEY(1, 0, KEY_D), - KEY(1, 1, KEY_F), - KEY(1, 2, KEY_G), - KEY(1, 3, KEY_SEND), - KEY(1, 4, KEY_F6), - KEY(1, 5, KEY_UNKNOWN), - KEY(1, 6, KEY_K), - KEY(1, 7, KEY_ENTER), - - KEY(2, 0, KEY_X), - KEY(2, 1, KEY_C), - KEY(2, 2, KEY_V), - KEY(2, 3, KEY_END), - KEY(2, 4, KEY_F7), - KEY(2, 5, KEY_UNKNOWN), - KEY(2, 6, KEY_DOT), - KEY(2, 7, KEY_CAPSLOCK), - - KEY(3, 0, KEY_Z), - KEY(3, 1, KEY_KPPLUS), - KEY(3, 2, KEY_B), - KEY(3, 3, KEY_F1), - KEY(3, 4, KEY_F8), - KEY(3, 5, KEY_UNKNOWN), - KEY(3, 6, KEY_O), - KEY(3, 7, KEY_SPACE), - - KEY(4, 0, KEY_W), - KEY(4, 1, KEY_Y), - KEY(4, 2, KEY_U), - KEY(4, 3, KEY_F2), - KEY(4, 4, KEY_VOLUMEUP), - KEY(4, 5, KEY_UNKNOWN), - KEY(4, 6, KEY_L), - KEY(4, 7, KEY_LEFT), - - KEY(5, 0, KEY_S), - KEY(5, 1, KEY_H), - KEY(5, 2, KEY_J), - KEY(5, 3, KEY_F3), - KEY(5, 4, KEY_F9), - KEY(5, 5, KEY_VOLUMEDOWN), - KEY(5, 6, KEY_M), - KEY(5, 7, KEY_RIGHT), - - KEY(6, 0, KEY_Q), - KEY(6, 1, KEY_A), - KEY(6, 2, KEY_N), - KEY(6, 3, KEY_BACK), - KEY(6, 4, KEY_BACKSPACE), - KEY(6, 5, KEY_UNKNOWN), - KEY(6, 6, KEY_P), - KEY(6, 7, KEY_UP), - - KEY(7, 0, KEY_PROG1), - KEY(7, 1, KEY_PROG2), - KEY(7, 2, KEY_PROG3), - KEY(7, 3, KEY_PROG4), - KEY(7, 4, KEY_F4), - KEY(7, 5, KEY_UNKNOWN), - KEY(7, 6, KEY_OK), - KEY(7, 7, KEY_DOWN), -}; -static struct omap_device_pad keypad_pads[] = { - { .name = "kpd_col1.kpd_col1", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "kpd_col1.kpd_col1", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "kpd_col2.kpd_col2", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "kpd_col3.kpd_col3", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "kpd_col4.kpd_col4", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "kpd_col5.kpd_col5", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "gpmc_a23.kpd_col7", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "gpmc_a22.kpd_col6", - .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1, - }, - { .name = "kpd_row0.kpd_row0", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "kpd_row1.kpd_row1", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "kpd_row2.kpd_row2", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "kpd_row3.kpd_row3", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "kpd_row4.kpd_row4", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "kpd_row5.kpd_row5", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "gpmc_a18.kpd_row6", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, - { .name = "gpmc_a19.kpd_row7", - .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN | - OMAP_MUX_MODE1 | OMAP_INPUT_EN, - }, -}; - -static struct matrix_keymap_data sdp4430_keymap_data = { - .keymap = sdp4430_keymap, - .keymap_size = ARRAY_SIZE(sdp4430_keymap), -}; - -static struct omap4_keypad_platform_data sdp4430_keypad_data = { - .keymap_data = &sdp4430_keymap_data, - .rows = 8, - .cols = 8, -}; - -static struct omap_board_data keypad_data = { - .id = 1, - .pads = keypad_pads, - .pads_cnt = ARRAY_SIZE(keypad_pads), -}; - -static struct gpio_led sdp4430_gpio_leds[] = { - { - .name = "omap4:green:debug0", - .gpio = 61, - }, - { - .name = "omap4:green:debug1", - .gpio = 30, - }, - { - .name = "omap4:green:debug2", - .gpio = 7, - }, - { - .name = "omap4:green:debug3", - .gpio = 8, - }, - { - .name = "omap4:green:debug4", - .gpio = 50, - }, - { - .name = "omap4:blue:user", - .gpio = 169, - }, - { - .name = "omap4:red:user", - .gpio = 170, - }, - { - .name = "omap4:green:user", - .gpio = 139, - }, - -}; - -static struct gpio_keys_button sdp4430_gpio_keys[] = { - { - .desc = "Proximity Sensor", - .type = EV_SW, - .code = SW_FRONT_PROXIMITY, - .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO, - .active_low = 0, - } -}; - -static struct gpio_led_platform_data sdp4430_led_data = { - .leds = sdp4430_gpio_leds, - .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), -}; - -static struct pwm_lookup sdp4430_pwm_lookup[] = { - PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"), - PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL), - PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"), -}; - -static struct led_pwm sdp4430_pwm_leds[] = { - { - .name = "omap4::keypad", - .max_brightness = 127, - .pwm_period_ns = 7812500, - }, - { - .name = "omap4:green:chrg", - .max_brightness = 255, - .pwm_period_ns = 7812500, - }, -}; - -static struct led_pwm_platform_data sdp4430_pwm_data = { - .num_leds = ARRAY_SIZE(sdp4430_pwm_leds), - .leds = sdp4430_pwm_leds, -}; - -static struct platform_device sdp4430_leds_pwm = { - .name = "leds_pwm", - .id = -1, - .dev = { - .platform_data = &sdp4430_pwm_data, - }, -}; - -/* Dummy regulator for pwm-backlight driver */ -static struct regulator_consumer_supply backlight_supply = - REGULATOR_SUPPLY("enable", "pwm-backlight"); - -static struct platform_pwm_backlight_data sdp4430_backlight_data = { - .max_brightness = 127, - .dft_brightness = 127, - .pwm_period_ns = 7812500, -}; - -static struct platform_device sdp4430_backlight_pwm = { - .name = "pwm-backlight", - .id = -1, - .dev = { - .platform_data = &sdp4430_backlight_data, - }, -}; - -static int omap_prox_activate(struct device *dev) -{ - gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); - return 0; -} - -static void omap_prox_deactivate(struct device *dev) -{ - gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0); -} - -static struct gpio_keys_platform_data sdp4430_gpio_keys_data = { - .buttons = sdp4430_gpio_keys, - .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys), - .enable = omap_prox_activate, - .disable = omap_prox_deactivate, -}; - -static struct platform_device sdp4430_gpio_keys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &sdp4430_gpio_keys_data, - }, -}; - -static struct platform_device sdp4430_leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &sdp4430_led_data, - }, -}; -static struct spi_board_info sdp4430_spi_board_info[] __initdata = { - { - .modalias = "ks8851", - .bus_num = 1, - .chip_select = 0, - .max_speed_hz = 24000000, - /* - * .irq is set to gpio_to_irq(ETH_KS8851_IRQ) - * in omap_4430sdp_init - */ - }, -}; - -static struct gpio sdp4430_eth_gpios[] __initdata = { - { ETH_KS8851_POWER_ON, GPIOF_OUT_INIT_HIGH, "eth_power" }, - { ETH_KS8851_QUART, GPIOF_OUT_INIT_HIGH, "quart" }, - { ETH_KS8851_IRQ, GPIOF_IN, "eth_irq" }, -}; - -static int __init omap_ethernet_init(void) -{ - int status; - - /* Request of GPIO lines */ - status = gpio_request_array(sdp4430_eth_gpios, - ARRAY_SIZE(sdp4430_eth_gpios)); - if (status) - pr_err("Cannot request ETH GPIOs\n"); - - return status; -} - -static struct regulator_consumer_supply sdp4430_vbat_supply[] = { - REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"), - REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"), -}; - -static struct regulator_init_data sdp4430_vbat_data = { - .constraints = { - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply), - .consumer_supplies = sdp4430_vbat_supply, -}; - -static struct fixed_voltage_config sdp4430_vbat_pdata = { - .supply_name = "VBAT", - .microvolts = 3750000, - .init_data = &sdp4430_vbat_data, - .gpio = -EINVAL, -}; - -static struct platform_device sdp4430_vbat = { - .name = "reg-fixed-voltage", - .id = -1, - .dev = { - .platform_data = &sdp4430_vbat_pdata, - }, -}; - -static struct platform_device sdp4430_dmic_codec = { - .name = "dmic-codec", - .id = -1, -}; - -static struct platform_device sdp4430_hdmi_audio_codec = { - .name = "hdmi-audio-codec", - .id = -1, -}; - -static struct omap_abe_twl6040_data sdp4430_abe_audio_data = { - .card_name = "SDP4430", - .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - .has_ep = 1, - .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - .has_vibra = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - - .has_dmic = 1, - .has_hsmic = 1, - .has_mainmic = 1, - .has_submic = 1, - .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - - .jack_detection = 1, - /* MCLK input is 38.4MHz */ - .mclk_freq = 38400000, -}; - -static struct platform_device sdp4430_abe_audio = { - .name = "omap-abe-twl6040", - .id = -1, - .dev = { - .platform_data = &sdp4430_abe_audio_data, - }, -}; - -static struct platform_device *sdp4430_devices[] __initdata = { - &sdp4430_gpio_keys_device, - &sdp4430_leds_gpio, - &sdp4430_leds_pwm, - &sdp4430_backlight_pwm, - &sdp4430_vbat, - &sdp4430_dmic_codec, - &sdp4430_abe_audio, - &sdp4430_hdmi_audio_codec, -}; - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_UTMI, - .mode = MUSB_OTG, - .power = 100, -}; - -static struct omap2_hsmmc_info mmc[] = { - { - .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .nonremovable = true, - .ocr_mask = MMC_VDD_29_30, - .no_off_init = true, - }, - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - }, - { - .mmc = 5, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, - .pm_caps = MMC_PM_KEEP_POWER, - .gpio_cd = -EINVAL, - .gpio_wp = -EINVAL, - .ocr_mask = MMC_VDD_165_195, - .nonremovable = true, - }, - {} /* Terminator */ -}; - -static struct regulator_consumer_supply sdp4430_vaux_supply[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), -}; - -static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = { - .supply = "vmmc", - .dev_name = "omap_hsmmc.4", -}; - -static struct regulator_init_data sdp4430_vmmc5 = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &omap4_sdp4430_vmmc5_supply, -}; - -static struct fixed_voltage_config sdp4430_vwlan = { - .supply_name = "vwl1271", - .microvolts = 1800000, /* 1.8V */ - .gpio = GPIO_WIFI_PMENA, - .startup_delay = 70000, /* 70msec */ - .enable_high = 1, - .enabled_at_boot = 0, - .init_data = &sdp4430_vmmc5, -}; - -static struct platform_device omap_vwlan_device = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &sdp4430_vwlan, - }, -}; - -static struct regulator_init_data sdp4430_vaux1 = { - .constraints = { - .min_uV = 1000000, - .max_uV = 3000000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply), - .consumer_supplies = sdp4430_vaux_supply, -}; - -static struct regulator_init_data sdp4430_vusim = { - .constraints = { - .min_uV = 1200000, - .max_uV = 2900000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -}; - -static struct twl6040_codec_data twl6040_codec = { - /* single-step ramp for headset and handsfree */ - .hs_left_step = 0x0f, - .hs_right_step = 0x0f, - .hf_left_step = 0x1d, - .hf_right_step = 0x1d, -}; - -static struct twl6040_vibra_data twl6040_vibra = { - .vibldrv_res = 8, - .vibrdrv_res = 3, - .viblmotor_res = 10, - .vibrmotor_res = 10, - .vddvibl_uV = 0, /* fixed volt supply - VBAT */ - .vddvibr_uV = 0, /* fixed volt supply - VBAT */ -}; - -static struct twl6040_platform_data twl6040_data = { - .codec = &twl6040_codec, - .vibra = &twl6040_vibra, - .audpwron_gpio = 127, -}; - -static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = { - { - I2C_BOARD_INFO("twl6040", 0x4b), - .irq = 119 + OMAP44XX_IRQ_GIC_START, - .platform_data = &twl6040_data, - }, -}; - -static struct twl4030_platform_data sdp4430_twldata = { - /* Regulators */ - .vusim = &sdp4430_vusim, - .vaux1 = &sdp4430_vaux1, -}; - -static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { - { - I2C_BOARD_INFO("tmp105", 0x48), - }, - { - I2C_BOARD_INFO("bh1780", 0x29), - }, -}; -static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { - { - I2C_BOARD_INFO("hmc5843", 0x1e), - }, -}; -static int __init omap4_i2c_init(void) -{ - omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB, - TWL_COMMON_REGULATOR_VDAC | - TWL_COMMON_REGULATOR_VAUX2 | - TWL_COMMON_REGULATOR_VAUX3 | - TWL_COMMON_REGULATOR_VMMC | - TWL_COMMON_REGULATOR_VPP | - TWL_COMMON_REGULATOR_VANA | - TWL_COMMON_REGULATOR_VCXIO | - TWL_COMMON_REGULATOR_VUSB | - TWL_COMMON_REGULATOR_CLK32KG | - TWL_COMMON_REGULATOR_V1V8 | - TWL_COMMON_REGULATOR_V2V1); - omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo, - ARRAY_SIZE(sdp4430_i2c_1_boardinfo)); - omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, - ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); - omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, - ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); - return 0; -} - -static void __init omap_sfh7741prox_init(void) -{ - int error; - - error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO, - GPIOF_OUT_INIT_LOW, "sfh7741"); - if (error < 0) - pr_err("%s:failed to request GPIO %d, error %d\n", - __func__, OMAP4_SFH7741_ENABLE_GPIO, error); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* NIRQ2 for twl6040 */ - OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 | - OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), - /* GPIO_127 for twl6040 */ - OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), - /* McPDM */ - OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - /* DMIC */ - OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), - OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - /* McBSP1 */ - OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | - OMAP_PULL_ENA), - OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - /* McBSP2 */ - OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | - OMAP_PULL_ENA), - OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -#else -#define board_mux NULL - #endif - -static void __init omap4_sdp4430_wifi_mux_init(void) -{ - omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | - OMAP_PIN_OFF_WAKEUPENABLE); - omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT); - - omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd", - OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk", - OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0", - OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1", - OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2", - OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3", - OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP); - -} - -static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = { - .board_ref_clock = WL12XX_REFCLOCK_26, - .board_tcxo_clock = WL12XX_TCXOCLOCK_26, -}; - -static void __init omap4_sdp4430_wifi_init(void) -{ - int ret; - - omap4_sdp4430_wifi_mux_init(); - omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ); - ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data); - if (ret) - pr_err("Error setting wl12xx data: %d\n", ret); - ret = platform_device_register(&omap_vwlan_device); - if (ret) - pr_err("Error registering wl12xx device: %d\n", ret); -} - -static void __init omap_4430sdp_init(void) -{ - int status; - int package = OMAP_PACKAGE_CBS; - - if (omap_rev() == OMAP4430_REV_ES1_0) - package = OMAP_PACKAGE_CBL; - omap4_mux_init(board_mux, NULL, package); - - omap4_i2c_init(); - omap_sfh7741prox_init(); - regulator_register_always_on(0, "backlight-enable", - &backlight_supply, 1, 0); - platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - omap4_sdp4430_wifi_init(); - omap4_twl6030_hsmmc_init(mmc); - - usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto"); - usb_musb_init(&musb_board_data); - - status = omap_ethernet_init(); - if (status) { - pr_err("Ethernet initialization failed: %d\n", status); - } else { - sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ); - spi_register_board_info(sdp4430_spi_board_info, - ARRAY_SIZE(sdp4430_spi_board_info)); - } - - pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup)); - status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data); - if (status) - pr_err("Keypad initialization failed: %d\n", status); - - omap_4430sdp_display_init(); -} - -MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") - /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ - .atag_offset = 0x100, - .smp = smp_ops(omap4_smp_ops), - .reserve = omap_reserve, - .map_io = omap4_map_io, - .init_early = omap4430_init_early, - .init_irq = gic_init_irq, - .init_machine = omap_4430sdp_init, - .init_late = omap4430_init_late, - .init_time = omap4_local_timer_init, - .restart = omap44xx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index ee6218c7480..d4622ed2625 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -293,7 +293,8 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = { static struct regulator_consumer_supply cm_t35_vio_supplies[] = { REGULATOR_SUPPLY("vcc", "spi1.0"), REGULATOR_SUPPLY("vdds_dsi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 57642054417..f1d91ba5d1a 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -222,6 +222,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"), REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 88aa6b1835c..e5fbfed69aa 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -185,3 +185,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .restart = omap44xx_restart, MACHINE_END #endif + +#ifdef CONFIG_SOC_AM43XX +static const char *am43_boards_compat[] __initdata = { + "ti,am43", + NULL, +}; + +DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") + .map_io = am33xx_map_io, + .init_early = am43xx_init_early, + .init_irq = omap_gic_of_init, + .init_machine = omap_generic_init, + .init_time = omap3_sync32k_timer_init, + .dt_compat = am43_boards_compat, +MACHINE_END +#endif diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index d0d17bc58d9..62e4f701b63 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -272,7 +272,8 @@ static struct regulator_init_data ldp_vaux1 = { static struct regulator_consumer_supply ldp_vpll2_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; static struct regulator_init_data ldp_vpll2 = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index f76d0de7b40..8c026269bac 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -174,6 +174,7 @@ static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = { .ud_gpio = OMAP3EVM_LCD_PANEL_UD, }; +#ifdef CONFIG_BROKEN static void __init omap3_evm_display_init(void) { int r; @@ -193,6 +194,7 @@ static void __init omap3_evm_display_init(void) else gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); } +#endif static struct omap_dss_device omap3_evm_lcd_device = { .name = "lcd", @@ -715,7 +717,9 @@ static void __init omap3_evm_init(void) omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); omap3evm_init_smsc911x(); +#ifdef CONFIG_BROKEN omap3_evm_display_init(); +#endif omap3_evm_wl12xx_init(); omap_twl4030_audio_init("omap3evm", NULL); } diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 28133d5b4fe..b1547a0edfc 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -343,6 +343,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = { static struct regulator_consumer_supply pandora_vdds_supplies[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"), REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c deleted file mode 100644 index 1e2c75eee91..00000000000 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ /dev/null @@ -1,455 +0,0 @@ -/* - * Board support file for OMAP4430 based PandaBoard. - * - * Copyright (C) 2010 Texas Instruments - * - * Author: David Anders <x0132446@ti.com> - * - * Based on mach-omap2/board-4430sdp.c - * - * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Based on mach-omap2/board-3430sdp.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/leds.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> -#include <linux/i2c/twl.h> -#include <linux/mfd/twl6040.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/ti_wilink_st.h> -#include <linux/usb/musb.h> -#include <linux/usb/phy.h> -#include <linux/usb/nop-usb-xceiv.h> -#include <linux/wl12xx.h> -#include <linux/irqchip/arm-gic.h> -#include <linux/platform_data/omap-abe-twl6040.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "soc.h" -#include "mmc.h" -#include "hsmmc.h" -#include "control.h" -#include "mux.h" -#include "common-board-devices.h" -#include "dss-common.h" - -#define GPIO_HUB_POWER 1 -#define GPIO_HUB_NRESET 62 -#define GPIO_WIFI_PMENA 43 -#define GPIO_WIFI_IRQ 53 - -/* wl127x BT, FM, GPS connectivity chip */ -static struct ti_st_plat_data wilink_platform_data = { - .nshutdown_gpio = 46, - .dev_name = "/dev/ttyO1", - .flow_cntrl = 1, - .baud_rate = 3000000, - .chip_enable = NULL, - .suspend = NULL, - .resume = NULL, -}; - -static struct platform_device wl1271_device = { - .name = "kim", - .id = -1, - .dev = { - .platform_data = &wilink_platform_data, - }, -}; - -static struct gpio_led gpio_leds[] = { - { - .name = "pandaboard::status1", - .default_trigger = "heartbeat", - .gpio = 7, - }, - { - .name = "pandaboard::status2", - .default_trigger = "mmc0", - .gpio = 8, - }, -}; - -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device leds_gpio = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - }, -}; - -static struct omap_abe_twl6040_data panda_abe_audio_data = { - /* Audio out */ - .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - /* HandsFree through expansion connector */ - .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */ - .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - /* PandaBoard: FM RX, PandaBoardES: audio in */ - .has_afm = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, - /* No jack detection. */ - .jack_detection = 0, - /* MCLK input is 38.4MHz */ - .mclk_freq = 38400000, - -}; - -static struct platform_device panda_abe_audio = { - .name = "omap-abe-twl6040", - .id = -1, - .dev = { - .platform_data = &panda_abe_audio_data, - }, -}; - -static struct platform_device panda_hdmi_audio_codec = { - .name = "hdmi-audio-codec", - .id = -1, -}; - -static struct platform_device btwilink_device = { - .name = "btwilink", - .id = -1, -}; - -/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */ -static struct nop_usb_xceiv_platform_data hsusb1_phy_data = { - /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ - .clk_rate = 19200000, -}; - -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = GPIO_HUB_NRESET, - .vcc_gpio = GPIO_HUB_POWER, - .vcc_polarity = 1, - .platform_data = &hsusb1_phy_data, - }, -}; - -static struct platform_device *panda_devices[] __initdata = { - &leds_gpio, - &wl1271_device, - &panda_abe_audio, - &panda_hdmi_audio_codec, - &btwilink_device, -}; - -static struct usbhs_omap_platform_data usbhs_bdata __initdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, -}; - -static void __init omap4_ehci_init(void) -{ - int ret; - - /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ - ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL); - if (ret) - pr_err("Failed to add main_clk alias to auxclk3_ck\n"); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); - usbhs_init(&usbhs_bdata); -} - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_UTMI, - .mode = MUSB_OTG, - .power = 100, -}; - -static struct omap2_hsmmc_info mmc[] = { - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - .gpio_wp = -EINVAL, - .gpio_cd = -EINVAL, - }, - { - .name = "wl1271", - .mmc = 5, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, - .gpio_wp = -EINVAL, - .gpio_cd = -EINVAL, - .ocr_mask = MMC_VDD_165_195, - .nonremovable = true, - }, - {} /* Terminator */ -}; - -static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = { - REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"), -}; - -static struct regulator_init_data panda_vmmc5 = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply), - .consumer_supplies = omap4_panda_vmmc5_supply, -}; - -static struct fixed_voltage_config panda_vwlan = { - .supply_name = "vwl1271", - .microvolts = 1800000, /* 1.8V */ - .gpio = GPIO_WIFI_PMENA, - .startup_delay = 70000, /* 70msec */ - .enable_high = 1, - .enabled_at_boot = 0, - .init_data = &panda_vmmc5, -}; - -static struct platform_device omap_vwlan_device = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &panda_vwlan, - }, -}; - -static struct wl12xx_platform_data omap_panda_wlan_data __initdata = { - .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ -}; - -static struct twl6040_codec_data twl6040_codec = { - /* single-step ramp for headset and handsfree */ - .hs_left_step = 0x0f, - .hs_right_step = 0x0f, - .hf_left_step = 0x1d, - .hf_right_step = 0x1d, -}; - -static struct twl6040_platform_data twl6040_data = { - .codec = &twl6040_codec, - .audpwron_gpio = 127, -}; - -static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = { - { - I2C_BOARD_INFO("twl6040", 0x4b), - .irq = 119 + OMAP44XX_IRQ_GIC_START, - .platform_data = &twl6040_data, - }, -}; - -/* Panda board uses the common PMIC configuration */ -static struct twl4030_platform_data omap4_panda_twldata; - -/* - * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM - * is connected as I2C slave device, and can be accessed at address 0x50 - */ -static struct i2c_board_info __initdata panda_i2c_eeprom[] = { - { - I2C_BOARD_INFO("eeprom", 0x50), - }, -}; - -static int __init omap4_panda_i2c_init(void) -{ - omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB, - TWL_COMMON_REGULATOR_VDAC | - TWL_COMMON_REGULATOR_VAUX2 | - TWL_COMMON_REGULATOR_VAUX3 | - TWL_COMMON_REGULATOR_VMMC | - TWL_COMMON_REGULATOR_VPP | - TWL_COMMON_REGULATOR_VANA | - TWL_COMMON_REGULATOR_VCXIO | - TWL_COMMON_REGULATOR_VUSB | - TWL_COMMON_REGULATOR_CLK32KG | - TWL_COMMON_REGULATOR_V1V8 | - TWL_COMMON_REGULATOR_V2V1); - omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo, - ARRAY_SIZE(panda_i2c_1_boardinfo)); - omap_register_i2c_bus(2, 400, NULL, 0); - /* - * Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz - */ - omap_register_i2c_bus(3, 100, panda_i2c_eeprom, - ARRAY_SIZE(panda_i2c_eeprom)); - omap_register_i2c_bus(4, 400, NULL, 0); - return 0; -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* WLAN IRQ - GPIO 53 */ - OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), - /* WLAN POWER ENABLE - GPIO 43 */ - OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), - /* WLAN SDIO: MMC5 CMD */ - OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC5 CLK */ - OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC5 DAT[0-3] */ - OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - /* gpio 0 - TFP410 PD */ - OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3), - /* dispc2_data23 */ - OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data22 */ - OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data21 */ - OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data20 */ - OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data19 */ - OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data18 */ - OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data15 */ - OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data14 */ - OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data13 */ - OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data12 */ - OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data11 */ - OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data10 */ - OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data9 */ - OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data16 */ - OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data17 */ - OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_hsync */ - OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_pclk */ - OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_vsync */ - OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_de */ - OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data8 */ - OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data7 */ - OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data6 */ - OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data5 */ - OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data4 */ - OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data3 */ - OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data2 */ - OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data1 */ - OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* dispc2_data0 */ - OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5), - /* NIRQ2 for twl6040 */ - OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 | - OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), - /* GPIO_127 for twl6040 */ - OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), - /* McPDM */ - OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - /* McBSP1 */ - OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), - OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | - OMAP_PULL_ENA), - OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), - - /* UART2 - BT/FM/GPS shared transport */ - OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0), - OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), - OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0), - OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), - - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -#else -#define board_mux NULL -#endif - - -static void omap4_panda_init_rev(void) -{ - if (cpu_is_omap443x()) { - /* PandaBoard 4430 */ - /* ASoC audio configuration */ - panda_abe_audio_data.card_name = "PandaBoard"; - panda_abe_audio_data.has_hsmic = 1; - } else { - /* PandaBoard ES */ - /* ASoC audio configuration */ - panda_abe_audio_data.card_name = "PandaBoardES"; - } -} - -static void __init omap4_panda_init(void) -{ - int package = OMAP_PACKAGE_CBS; - int ret; - - if (omap_rev() == OMAP4430_REV_ES1_0) - package = OMAP_PACKAGE_CBL; - omap4_mux_init(board_mux, NULL, package); - - omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ); - ret = wl12xx_set_platform_data(&omap_panda_wlan_data); - if (ret) - pr_err("error setting wl12xx data: %d\n", ret); - - omap4_panda_init_rev(); - omap4_panda_i2c_init(); - platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); - platform_device_register(&omap_vwlan_device); - omap_serial_init(); - omap_sdrc_init(NULL, NULL); - omap4_twl6030_hsmmc_init(mmc); - omap4_ehci_init(); - usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto"); - usb_musb_init(&musb_board_data); - omap4_panda_display_init(); -} - -MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") - /* Maintainer: David Anders - Texas Instruments Inc */ - .atag_offset = 0x100, - .smp = smp_ops(omap4_smp_ops), - .reserve = omap_reserve, - .map_io = omap4_map_io, - .init_early = omap4430_init_early, - .init_irq = gic_init_irq, - .init_machine = omap4_panda_init, - .init_late = omap4430_init_late, - .init_time = omap4_local_timer_init, - .restart = omap44xx_restart, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 4ca6b680aa7..5748b5d06c2 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -68,6 +68,7 @@ #define OVERO_SMSC911X_CS 5 #define OVERO_SMSC911X_GPIO 176 +#define OVERO_SMSC911X_NRESET 64 #define OVERO_SMSC911X2_CS 4 #define OVERO_SMSC911X2_GPIO 65 @@ -122,7 +123,7 @@ static struct omap_smsc911x_platform_data smsc911x_cfg = { .id = 0, .cs = OVERO_SMSC911X_CS, .gpio_irq = OVERO_SMSC911X_GPIO, - .gpio_reset = -EINVAL, + .gpio_reset = OVERO_SMSC911X_NRESET, .flags = SMSC911X_USE_32BIT, }; diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 18ca61e300b..9c2dd102fbb 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -553,6 +553,7 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = { static struct regulator_consumer_supply rx51_vaux1_consumers[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), + REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"), /* Si4713 supply */ REGULATOR_SUPPLY("vdd", "2-0063"), /* lis3lv02d */ diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index a8140b6885e..ba6534d7f15 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -858,6 +858,33 @@ static struct clk_hw_omap wdt1_fck_hw = { DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); +static const char *pwmss_clk_parents[] = { + "dpll_per_m2_ck", +}; + +static const struct clk_ops ehrpwm_tbclk_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, +}; + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS0_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS1_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", + NULL, NULL, 0, + AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), + AM33XX_PWMSS2_TBCLKEN_SHIFT, + NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); + /* * debugss optional clocks */ @@ -980,6 +1007,9 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), CLK(NULL, "clkout2_ck", &clkout2_ck), + CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), + CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), + CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), }; diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 45cd26430d1..334b7674590 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck), CLK(NULL, "ts_fck", &ts_fck), CLK(NULL, "usbtll_fck", &usbtll_fck), - CLK("usbhs_omap", "usbtll_fck", &usbtll_fck), - CLK("usbhs_tll", "usbtll_fck", &usbtll_fck), CLK(NULL, "usbtll_ick", &usbtll_ick), - CLK("usbhs_omap", "usbtll_ick", &usbtll_ick), - CLK("usbhs_tll", "usbtll_ick", &usbtll_ick), CLK("omap_hsmmc.2", "ick", &mmchs3_ick), CLK(NULL, "mmchs3_ick", &mmchs3_ick), CLK(NULL, "mmchs3_fck", &mmchs3_fck), @@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = { CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), CLK(NULL, "usbhost_ick", &usbhost_ick), - CLK("usbhs_omap", "usbhost_ick", &usbhost_ick), }; /* @@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "utmi_p2_gfclk", &dummy_ck), CLK(NULL, "xclk60mhsp1_ck", &dummy_ck), CLK(NULL, "xclk60mhsp2_ck", &dummy_ck), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck), - CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck), - CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck), - CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck), - CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck), CLK(NULL, "init_60m_fclk", &dummy_ck), CLK(NULL, "gpt1_fck", &gpt1_fck), CLK(NULL, "aes2_ick", &aes2_ick), diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 2da37656a69..daeecf1b89f 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); +extern void __init omap54xx_clockdomains_init(void); extern void clkdm_add_autodeps(struct clockdomain *clkdm); extern void clkdm_del_autodeps(struct clockdomain *clkdm); diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c new file mode 100644 index 00000000000..1a3c69d2e14 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains54xx_data.c @@ -0,0 +1,464 @@ +/* + * OMAP54XX Clock domains framework + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "cm1_54xx.h" +#include "cm2_54xx.h" + +#include "cm-regbits-54xx.h" +#include "prm54xx.h" +#include "prcm44xx.h" +#include "prcm_mpu54xx.h" + +/* Static Dependencies for OMAP4 Clock Domains */ + +static struct clkdm_dep c2c_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep cam_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dma_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dsp_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dss_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep gpu_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep ipu_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep iva_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l3init_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l4sec_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep mipiext_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep mpu_wkup_sleep_deps[] = { + { .clkdm_name = "abe_clkdm" }, + { .clkdm_name = "dsp_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l3main2_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clockdomain l4sec_54xx_clkdm = { + .name = "l4sec_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS, + .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT, + .wkdep_srcs = l4sec_wkup_sleep_deps, + .sleepdep_srcs = l4sec_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain iva_54xx_clkdm = { + .name = "iva_clkdm", + .pwrdm = { .name = "iva_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_IVA_INST, + .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS, + .dep_bit = OMAP54XX_IVA_STATDEP_SHIFT, + .wkdep_srcs = iva_wkup_sleep_deps, + .sleepdep_srcs = iva_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain mipiext_54xx_clkdm = { + .name = "mipiext_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS, + .wkdep_srcs = mipiext_wkup_sleep_deps, + .sleepdep_srcs = mipiext_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3main2_54xx_clkdm = { + .name = "l3main2_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS, + .dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3main1_54xx_clkdm = { + .name = "l3main1_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS, + .dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain custefuse_54xx_clkdm = { + .name = "custefuse_clkdm", + .pwrdm = { .name = "custefuse_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain ipu_54xx_clkdm = { + .name = "ipu_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS, + .dep_bit = OMAP54XX_IPU_STATDEP_SHIFT, + .wkdep_srcs = ipu_wkup_sleep_deps, + .sleepdep_srcs = ipu_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l4cfg_54xx_clkdm = { + .name = "l4cfg_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS, + .dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain abe_54xx_clkdm = { + .name = "abe_clkdm", + .pwrdm = { .name = "abe_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS, + .dep_bit = OMAP54XX_ABE_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dss_54xx_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "dss_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_DSS_INST, + .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS, + .dep_bit = OMAP54XX_DSS_STATDEP_SHIFT, + .wkdep_srcs = dss_wkup_sleep_deps, + .sleepdep_srcs = dss_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dsp_54xx_clkdm = { + .name = "dsp_clkdm", + .pwrdm = { .name = "dsp_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST, + .clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS, + .dep_bit = OMAP54XX_DSP_STATDEP_SHIFT, + .wkdep_srcs = dsp_wkup_sleep_deps, + .sleepdep_srcs = dsp_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain c2c_54xx_clkdm = { + .name = "c2c_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS, + .wkdep_srcs = c2c_wkup_sleep_deps, + .sleepdep_srcs = c2c_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l4per_54xx_clkdm = { + .name = "l4per_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS, + .dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain gpu_54xx_clkdm = { + .name = "gpu_clkdm", + .pwrdm = { .name = "gpu_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_GPU_INST, + .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS, + .dep_bit = OMAP54XX_GPU_STATDEP_SHIFT, + .wkdep_srcs = gpu_wkup_sleep_deps, + .sleepdep_srcs = gpu_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain wkupaon_54xx_clkdm = { + .name = "wkupaon_clkdm", + .pwrdm = { .name = "wkupaon_pwrdm" }, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST, + .clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS, + .dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain mpu0_54xx_clkdm = { + .name = "mpu0_clkdm", + .pwrdm = { .name = "cpu0_pwrdm" }, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST, + .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain mpu1_54xx_clkdm = { + .name = "mpu1_clkdm", + .pwrdm = { .name = "cpu1_pwrdm" }, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST, + .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain coreaon_54xx_clkdm = { + .name = "coreaon_clkdm", + .pwrdm = { .name = "coreaon_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_COREAON_INST, + .clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain mpu_54xx_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST, + .clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS, + .wkdep_srcs = mpu_wkup_sleep_deps, + .sleepdep_srcs = mpu_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3init_54xx_clkdm = { + .name = "l3init_clkdm", + .pwrdm = { .name = "l3init_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_L3INIT_INST, + .clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS, + .dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT, + .wkdep_srcs = l3init_wkup_sleep_deps, + .sleepdep_srcs = l3init_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dma_54xx_clkdm = { + .name = "dma_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS, + .wkdep_srcs = dma_wkup_sleep_deps, + .sleepdep_srcs = dma_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3instr_54xx_clkdm = { + .name = "l3instr_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS, +}; + +static struct clockdomain emif_54xx_clkdm = { + .name = "emif_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CORE_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS, + .dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain emu_54xx_clkdm = { + .name = "emu_clkdm", + .pwrdm = { .name = "emu_pwrdm" }, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .cm_inst = OMAP54XX_PRM_EMU_CM_INST, + .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain cam_54xx_clkdm = { + .name = "cam_clkdm", + .pwrdm = { .name = "cam_pwrdm" }, + .prcm_partition = OMAP54XX_CM_CORE_PARTITION, + .cm_inst = OMAP54XX_CM_CORE_CAM_INST, + .clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS, + .wkdep_srcs = cam_wkup_sleep_deps, + .sleepdep_srcs = cam_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +/* As clockdomains are added or removed above, this list must also be changed */ +static struct clockdomain *clockdomains_omap54xx[] __initdata = { + &l4sec_54xx_clkdm, + &iva_54xx_clkdm, + &mipiext_54xx_clkdm, + &l3main2_54xx_clkdm, + &l3main1_54xx_clkdm, + &custefuse_54xx_clkdm, + &ipu_54xx_clkdm, + &l4cfg_54xx_clkdm, + &abe_54xx_clkdm, + &dss_54xx_clkdm, + &dsp_54xx_clkdm, + &c2c_54xx_clkdm, + &l4per_54xx_clkdm, + &gpu_54xx_clkdm, + &wkupaon_54xx_clkdm, + &mpu0_54xx_clkdm, + &mpu1_54xx_clkdm, + &coreaon_54xx_clkdm, + &mpu_54xx_clkdm, + &l3init_54xx_clkdm, + &dma_54xx_clkdm, + &l3instr_54xx_clkdm, + &emif_54xx_clkdm, + &emu_54xx_clkdm, + &cam_54xx_clkdm, + NULL +}; + +void __init omap54xx_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&omap4_clkdm_operations); + clkdm_register_clkdms(clockdomains_omap54xx); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h new file mode 100644 index 00000000000..e83b8e352b6 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-54xx.h @@ -0,0 +1,1737 @@ +/* + * OMAP54xx Clock Management register bits + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H + +/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ +#define OMAP54XX_ABE_DYNDEP_SHIFT 3 +#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 +#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_ABE_STATDEP_SHIFT 3 +#define OMAP54XX_ABE_STATDEP_WIDTH 0x1 +#define OMAP54XX_ABE_STATDEP_MASK (1 << 3) + +/* + * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, + * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, + * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB + */ +#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 +#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 +#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_C2C_DYNDEP_SHIFT 18 +#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 +#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) + +/* Used by CM_MPU_STATICDEP */ +#define OMAP54XX_C2C_STATDEP_SHIFT 18 +#define OMAP54XX_C2C_STATDEP_WIDTH 0x1 +#define OMAP54XX_C2C_STATDEP_MASK (1 << 18) + +/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_CAM_DYNDEP_SHIFT 9 +#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 +#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) + +/* + * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, + * CM_MPU_STATICDEP + */ +#define OMAP54XX_CAM_STATDEP_SHIFT 9 +#define OMAP54XX_CAM_STATDEP_WIDTH 0x1 +#define OMAP54XX_CAM_STATDEP_MASK (1 << 9) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) + +/* Used by CM_C2C_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) + +/* Used by CM_CUSTEFUSE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) + +/* Used by CM_CUSTEFUSE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) + +/* Used by CM_DMA_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) + +/* Used by CM_DSP_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) + +/* Used by CM_EMIF_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) + +/* Used by CM_EMU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) + +/* Used by CM_CAM_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) + +/* Used by CM_GPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) + +/* Used by CM_DSS_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) + +/* Used by CM_IPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) + +/* Used by CM_IVA_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3INSTR_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) + +/* Used by CM_L3MAIN1_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L3MAIN2_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L4CFG_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) + +/* Used by CM_L4SEC_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) + +/* Used by CM_L4SEC_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) + +/* Used by CM_MPU_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) + +/* Used by CM_ABE_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) + +/* Used by CM_COREAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) + +/* Used by CM_L4PER_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) + +/* Used by CM_MIPIEXT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) + +/* Used by CM_L3INIT_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) + +/* Used by CM_WKUPAON_CLKSTCTRL */ +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 +#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) + +/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ +#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 +#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) + +/* + * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, + * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, + * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, + * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL + */ +#define OMAP54XX_CLKSEL_SHIFT 24 +#define OMAP54XX_CLKSEL_WIDTH 0x1 +#define OMAP54XX_CLKSEL_MASK (1 << 24) + +/* + * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, + * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON + */ +#define OMAP54XX_CLKSEL_0_0_SHIFT 0 +#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 +#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) + +/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ +#define OMAP54XX_CLKSEL_0_1_SHIFT 0 +#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 +#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) + +/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ +#define OMAP54XX_CLKSEL_24_25_SHIFT 24 +#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 +#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) + +/* Used by CM_MPU_MPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 +#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) + +/* Used by CM_ABE_AESS_CLKCTRL */ +#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) + +/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ +#define OMAP54XX_CLKSEL_DIV_SHIFT 25 +#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 +#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) + +/* Used by CM_MPU_MPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) + +/* Used by CM_CAM_FDIF_CLKCTRL */ +#define OMAP54XX_CLKSEL_FCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) + +/* Used by CM_GPU_GPU_CLKCTRL */ +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) + +/* + * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, + * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL + */ +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) + +/* Used by CM_CLKSEL_CORE */ +#define OMAP54XX_CLKSEL_L3_SHIFT 4 +#define OMAP54XX_CLKSEL_L3_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L3_MASK (1 << 4) + +/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 +#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) + +/* Used by CM_CLKSEL_CORE */ +#define OMAP54XX_CLKSEL_L4_SHIFT 8 +#define OMAP54XX_CLKSEL_L4_WIDTH 0x1 +#define OMAP54XX_CLKSEL_L4_MASK (1 << 8) + +/* Used by CM_EMIF_EMIF1_CLKCTRL */ +#define OMAP54XX_CLKSEL_LL_SHIFT 24 +#define OMAP54XX_CLKSEL_LL_WIDTH 0x1 +#define OMAP54XX_CLKSEL_LL_MASK (1 << 24) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_CLKSEL_OPP_SHIFT 0 +#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 +#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) + +/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ +#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 +#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 +#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) + +/* + * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, + * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL + */ +#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 +#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 +#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) + +/* + * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL + */ +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 +#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 +#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 +#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 +#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) + +/* + * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, + * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, + * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, + * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, + * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, + * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, + * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, + * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER + */ +#define OMAP54XX_CLKST_SHIFT 9 +#define OMAP54XX_CLKST_WIDTH 0x1 +#define OMAP54XX_CLKST_MASK (1 << 9) + +/* + * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, + * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, + * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, + * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, + * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, + * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, + * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL + */ +#define OMAP54XX_CLKTRCTRL_SHIFT 0 +#define OMAP54XX_CLKTRCTRL_WIDTH 0x2 +#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) + +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ +#define OMAP54XX_CLKX2ST_SHIFT 11 +#define OMAP54XX_CLKX2ST_WIDTH 0x1 +#define OMAP54XX_CLKX2ST_MASK (1 << 11) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_COREAON_DYNDEP_SHIFT 16 +#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 +#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) + +/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_COREAON_STATDEP_SHIFT 16 +#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 +#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 +#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 +#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) + +/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 +#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 +#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_CUSTOM_SHIFT 6 +#define OMAP54XX_CUSTOM_WIDTH 0x2 +#define OMAP54XX_CUSTOM_MASK (0x3 << 6) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DCC_EN_SHIFT 22 +#define OMAP54XX_DCC_EN_WIDTH 0x1 +#define OMAP54XX_DCC_EN_MASK (1 << 22) + +/* + * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, + * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, + * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS + */ +#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 +#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd +#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, + * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 +#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, + * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 +#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, + * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 +#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, + * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 +#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, + * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb +#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) + +/* + * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, + * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS + */ +#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 +#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 +#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa +#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b +#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe +#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) + +/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ +#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 +#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) + +/* + * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, + * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, + * CM_SSC_DELTAMSTEP_DPLL_PER + */ +#define OMAP54XX_DELTAMSTEP_SHIFT 0 +#define OMAP54XX_DELTAMSTEP_WIDTH 0x14 +#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) + +/* + * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, + * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB + */ +#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 +#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 +#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) + +/* + * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, + * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, + * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, + * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, + * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE + */ +#define OMAP54XX_DIVHS_SHIFT 0 +#define OMAP54XX_DIVHS_WIDTH 0x6 +#define OMAP54XX_DIVHS_MASK (0x3f << 0) + +/* + * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, + * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER + */ +#define OMAP54XX_DIVHS_0_4_SHIFT 0 +#define OMAP54XX_DIVHS_0_4_WIDTH 0x5 +#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) + +/* + * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, + * CM_DIV_M2_DPLL_USB + */ +#define OMAP54XX_DIVHS_0_6_SHIFT 0 +#define OMAP54XX_DIVHS_0_6_WIDTH 0x7 +#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) + +/* Used by CM_DLL_CTRL */ +#define OMAP54XX_DLL_OVERRIDE_SHIFT 0 +#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 +#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) + +/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 +#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 +#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DLL_RESET_SHIFT 3 +#define OMAP54XX_DLL_RESET_WIDTH 0x1 +#define OMAP54XX_DLL_RESET_MASK (1 << 3) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 +#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 +#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) + +/* Used by CM_CLKSEL_DPLL_CORE */ +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 +#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 +#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 +#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) + +/* Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 +#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 +#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 +#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 +#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER + */ +#define OMAP54XX_DPLL_DIV_SHIFT 0 +#define OMAP54XX_DPLL_DIV_WIDTH 0x7 +#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) + +/* + * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 +#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 +#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_EN_SHIFT 0 +#define OMAP54XX_DPLL_EN_WIDTH 0x3 +#define OMAP54XX_DPLL_EN_MASK (0x7 << 0) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 +#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) + +/* + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER + */ +#define OMAP54XX_DPLL_MULT_SHIFT 8 +#define OMAP54XX_DPLL_MULT_WIDTH 0xb +#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) + +/* + * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, + * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB + */ +#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 +#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc +#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 +#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 +#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) + +/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ +#define OMAP54XX_DPLL_SD_DIV_SHIFT 24 +#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 +#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) + +/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ +#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 +#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 +#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 +#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) + +/* + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, + * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB + */ +#define OMAP54XX_DPLL_SSC_EN_SHIFT 12 +#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_DSP_DYNDEP_SHIFT 1 +#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 +#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_DSP_STATDEP_SHIFT 1 +#define OMAP54XX_DSP_STATDEP_WIDTH 0x1 +#define OMAP54XX_DSP_STATDEP_MASK (1 << 1) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_DSS_DYNDEP_SHIFT 8 +#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 +#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) + +/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_DSS_STATDEP_SHIFT 8 +#define OMAP54XX_DSS_STATDEP_WIDTH 0x1 +#define OMAP54XX_DSS_STATDEP_MASK (1 << 8) + +/* + * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, + * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP + */ +#define OMAP54XX_EMIF_DYNDEP_SHIFT 4 +#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 +#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_EMIF_STATDEP_SHIFT 4 +#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 +#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) + +/* Used by CM_SHADOW_FREQ_CONFIG1 */ +#define OMAP54XX_FREQ_UPDATE_SHIFT 0 +#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 +#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_FUNC_SHIFT 16 +#define OMAP54XX_FUNC_WIDTH 0xc +#define OMAP54XX_FUNC_MASK (0xfff << 16) + +/* Used by CM_SHADOW_FREQ_CONFIG2 */ +#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 +#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 +#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_GPU_DYNDEP_SHIFT 10 +#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_GPU_STATDEP_SHIFT 10 +#define OMAP54XX_GPU_STATDEP_WIDTH 0x1 +#define OMAP54XX_GPU_STATDEP_MASK (1 << 10) + +/* + * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, + * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, + * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, + * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, + * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, + * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, + * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, + * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, + * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, + * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, + * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, + * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, + * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, + * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, + * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, + * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, + * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, + * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, + * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, + * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, + * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, + * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, + * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, + * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, + * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, + * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, + * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, + * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, + * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, + * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL + */ +#define OMAP54XX_IDLEST_SHIFT 16 +#define OMAP54XX_IDLEST_WIDTH 0x2 +#define OMAP54XX_IDLEST_MASK (0x3 << 16) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_IPU_DYNDEP_SHIFT 0 +#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) + +/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_IPU_STATDEP_SHIFT 0 +#define OMAP54XX_IPU_STATDEP_WIDTH 0x1 +#define OMAP54XX_IPU_STATDEP_MASK (1 << 0) + +/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_IVA_DYNDEP_SHIFT 2 +#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 +#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_IVA_STATDEP_SHIFT 2 +#define OMAP54XX_IVA_STATDEP_WIDTH 0x1 +#define OMAP54XX_IVA_STATDEP_MASK (1 << 2) + +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 +#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L3INIT_STATDEP_SHIFT 7 +#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) + +/* + * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, + * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP + */ +#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 +#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 +#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) + +/* + * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, + * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, + * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP + */ +#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 +#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) + +/* + * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, + * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, + * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 +#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 +#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) + +/* Used by CM_L3MAIN1_DYNAMICDEP */ +#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 +#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L4CFG_STATDEP_SHIFT 12 +#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) + +/* Used by CM_L3MAIN2_DYNAMICDEP */ +#define OMAP54XX_L4PER_DYNDEP_SHIFT 13 +#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) + +/* + * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, + * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, + * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_L4PER_STATDEP_SHIFT 13 +#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 +#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 +#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) + +/* + * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, + * CM_MPU_STATICDEP + */ +#define OMAP54XX_L4SEC_STATDEP_SHIFT 14 +#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 +#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) + +/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 +#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 +#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) + +/* Used by CM_MPU_STATICDEP */ +#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 +#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 +#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) + +/* + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, + * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB + */ +#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 +#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 +#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) + +/* + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, + * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB + */ +#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 +#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 +#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) + +/* + * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, + * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, + * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, + * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, + * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, + * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, + * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, + * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, + * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, + * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, + * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, + * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, + * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, + * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, + * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, + * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, + * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, + * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, + * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, + * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, + * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, + * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, + * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, + * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, + * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, + * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, + * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, + * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, + * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, + * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, + * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, + * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, + * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, + * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, + * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, + * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, + * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, + * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, + * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL + */ +#define OMAP54XX_MODULEMODE_SHIFT 0 +#define OMAP54XX_MODULEMODE_WIDTH 0x2 +#define OMAP54XX_MODULEMODE_MASK (0x3 << 0) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_MPU_DYNDEP_SHIFT 19 +#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 +#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) + +/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) + +/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) + +/* Used by CM_CAM_ISS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) + +/* + * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, + * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL + */ +#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) + +/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) + +/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) + +/* Used by CM_L3INIT_SATA_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) + +/* Used by CM_WKUPAON_SCRM_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) + +/* Used by CM_WKUPAON_SCRM_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) + +/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) + +/* Used by CM_DSS_DSS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) + +/* Used by CM_MIPIEXT_LLI_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) + +/* Used by CM_MIPIEXT_LLI_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 +#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) + +/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ +#define OMAP54XX_OUTPUT_SHIFT 0 +#define OMAP54XX_OUTPUT_WIDTH 0x20 +#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 +#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 +#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 +#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 +#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) + +/* Used by CM_RESTORE_ST */ +#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 +#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 +#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) + +/* Used by CM_DYN_DEP_PRESCAL */ +#define OMAP54XX_PRESCAL_SHIFT 0 +#define OMAP54XX_PRESCAL_WIDTH 0x6 +#define OMAP54XX_PRESCAL_MASK (0x3f << 0) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_R_RTL_SHIFT 11 +#define OMAP54XX_R_RTL_WIDTH 0x5 +#define OMAP54XX_R_RTL_MASK (0x1f << 11) + +/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ +#define OMAP54XX_SAR_MODE_SHIFT 4 +#define OMAP54XX_SAR_MODE_WIDTH 0x1 +#define OMAP54XX_SAR_MODE_MASK (1 << 4) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_SCHEME_SHIFT 30 +#define OMAP54XX_SCHEME_WIDTH 0x2 +#define OMAP54XX_SCHEME_MASK (0x3 << 30) + +/* Used by CM_L4CFG_DYNAMICDEP */ +#define OMAP54XX_SDMA_DYNDEP_SHIFT 11 +#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 +#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) + +/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ +#define OMAP54XX_SDMA_STATDEP_SHIFT 11 +#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 +#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL0_SHIFT 0 +#define OMAP54XX_SEL0_WIDTH 0x7 +#define OMAP54XX_SEL0_MASK (0x7f << 0) + +/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL0_0_7_SHIFT 0 +#define OMAP54XX_SEL0_0_7_WIDTH 0x8 +#define OMAP54XX_SEL0_0_7_MASK (0xff << 0) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL1_SHIFT 8 +#define OMAP54XX_SEL1_WIDTH 0x7 +#define OMAP54XX_SEL1_MASK (0x7f << 8) + +/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL2_SHIFT 16 +#define OMAP54XX_SEL2_WIDTH 0x7 +#define OMAP54XX_SEL2_MASK (0x7f << 16) + +/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) + +/* Used by CM_CORE_AON_DEBUG_CFG */ +#define OMAP54XX_SEL3_SHIFT 24 +#define OMAP54XX_SEL3_WIDTH 0x7 +#define OMAP54XX_SEL3_MASK (0x7f << 24) + +/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 +#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) + +/* Used by CM_CLKSEL_ABE */ +#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 +#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 +#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) + +/* + * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, + * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, + * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, + * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, + * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, + * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, + * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, + * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, + * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL + */ +#define OMAP54XX_STBYST_SHIFT 18 +#define OMAP54XX_STBYST_WIDTH 0x1 +#define OMAP54XX_STBYST_MASK (1 << 18) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, + * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_CLK_SHIFT 0 +#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) + +/* + * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, + * CM_CLKDCOLDO_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 +#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, + * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_INIT_SHIFT 4 +#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 +#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, + * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB + */ +#define OMAP54XX_ST_DPLL_MODE_SHIFT 1 +#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 +#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) + +/* Used by CM_CLKSEL_SYS */ +#define OMAP54XX_SYS_CLKSEL_SHIFT 0 +#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 +#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) + +/* + * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, + * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, + * CM_MPU_DYNAMICDEP + */ +#define OMAP54XX_WINDOWSIZE_SHIFT 24 +#define OMAP54XX_WINDOWSIZE_WIDTH 0x4 +#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) + +/* Used by CM_L3MAIN1_DYNAMICDEP */ +#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 +#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 +#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) + +/* + * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP + */ +#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 +#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 +#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_X_MAJOR_SHIFT 8 +#define OMAP54XX_X_MAJOR_WIDTH 0x3 +#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ +#define OMAP54XX_Y_MINOR_SHIFT 0 +#define OMAP54XX_Y_MINOR_WIDTH 0x6 +#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) +#endif diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h index 1bc00dc4876..5ae8fe39d6e 100644 --- a/arch/arm/mach-omap2/cm1_44xx.h +++ b/arch/arm/mach-omap2/cm1_44xx.h @@ -25,6 +25,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H +#include "cm_44xx_54xx.h" + /* CM1 base address */ #define OMAP4430_CM1_BASE 0x4a004000 @@ -217,9 +219,4 @@ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) -/* Function prototypes */ -extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); -extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); - #endif diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h new file mode 100644 index 00000000000..90b3348e667 --- /dev/null +++ b/arch/arm/mach-omap2/cm1_54xx.h @@ -0,0 +1,213 @@ +/* + * OMAP54xx CM1 instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H + +#include "cm_44xx_54xx.h" + +/* CM1 base address */ +#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 + +#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg)) + +/* CM_CORE_AON instances */ +#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100 +#define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300 +#define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400 +#define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500 +#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00 +#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00 + +/* CM_CORE_AON clockdomain register offsets (from instance start) */ +#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000 + +/* CM_CORE_AON */ + +/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ +#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000 +#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) +#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080 +#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084 +#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090 +#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094 +#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098 +#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c +#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0 +#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4 +#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8 +#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac +#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0 +#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4 +#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8 +#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc +#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0 +#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4 +#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc +#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8 +#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc +#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0 +#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4 +#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8 +#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec +#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0 + +/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000 +#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000) +#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008 +#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008) +#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010 +#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 +#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020) +#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 +#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024) +#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 +#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028) +#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c +#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c) +#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 +#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030) +#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 +#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034) +#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 +#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038) +#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c +#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c) +#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 +#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040) +#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 +#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c +#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 +#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050) +#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 +#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054) +#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 +#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058) +#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c +#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c) +#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 +#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060) +#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 +#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064) +#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 +#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068) +#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c +#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c) +#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 +#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c +#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c +#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c) +#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 +#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0) +#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 +#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4) +#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 +#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8) +#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac +#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac) +#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8 +#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8) +#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc +#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc +#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc +#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc) +#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 +#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0) +#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 +#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4) +#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 +#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8) +#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec +#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec) +#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 +#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0) +#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 +#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c +#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 +#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 +#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 +#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180 + +/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020) +#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028) + +/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020) + +/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */ +#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020) +#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028) +#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030) +#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038) +#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040) +#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 +#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048) +#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 +#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050) +#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 +#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058) +#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060 +#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060) +#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 +#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068) +#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 +#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070) +#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 +#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078) +#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 +#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080) +#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088 +#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088) + +#endif diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h index b9de72da1a8..ee5136d7cdd 100644 --- a/arch/arm/mach-omap2/cm2_44xx.h +++ b/arch/arm/mach-omap2/cm2_44xx.h @@ -25,6 +25,8 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H +#include "cm_44xx_54xx.h" + /* CM2 base address */ #define OMAP4430_CM2_BASE 0x4a008000 @@ -449,9 +451,4 @@ #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) -/* Function prototypes */ -extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); -extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); - #endif diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h new file mode 100644 index 00000000000..2683231b299 --- /dev/null +++ b/arch/arm/mach-omap2/cm2_54xx.h @@ -0,0 +1,389 @@ +/* + * OMAP54xx CM2 instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H + +#include "cm_44xx_54xx.h" + +/* CM2 base address */ +#define OMAP54XX_CM_CORE_BASE 0x4a008000 + +#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) + +/* CM_CORE instances */ +#define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 +#define OMAP54XX_CM_CORE_COREAON_INST 0x0600 +#define OMAP54XX_CM_CORE_CORE_INST 0x0700 +#define OMAP54XX_CM_CORE_IVA_INST 0x1200 +#define OMAP54XX_CM_CORE_CAM_INST 0x1300 +#define OMAP54XX_CM_CORE_DSS_INST 0x1400 +#define OMAP54XX_CM_CORE_GPU_INST 0x1500 +#define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 +#define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 +#define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 +#define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 + +/* CM_CORE clockdomain register offsets (from instance start) */ +#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 +#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 +#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 +#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 +#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 +#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 +#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 +#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 +#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 +#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 +#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 +#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 + +/* CM_CORE */ + +/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ +#define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 +#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) +#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 +#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 + +/* CM_CORE.CKGEN_CM_CORE register offsets */ +#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 +#define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) +#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 +#define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) +#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 +#define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) +#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 +#define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) +#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c +#define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) +#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 +#define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) +#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 +#define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) +#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 +#define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) +#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c +#define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) +#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 +#define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) +#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 +#define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c +#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 +#define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) +#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 +#define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) +#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 +#define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) +#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c +#define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) +#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 +#define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac +#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 +#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 +#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 +#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 +#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c +#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 +#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) +#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 +#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 +#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) + +/* CM_CORE.COREAON_CM_CORE register offsets */ +#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) +#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) +#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) +#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 +#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) + +/* CM_CORE.CORE_CM_CORE register offsets */ +#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) +#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 +#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 +#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 +#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) +#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 +#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) +#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 +#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) +#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 +#define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 +#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 +#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 +#define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) +#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 +#define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 +#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 +#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 +#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) +#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 +#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 +#define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) +#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 +#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) +#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 +#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) +#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 +#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) +#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 +#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) +#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 +#define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 +#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 +#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 +#define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) +#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 +#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) +#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 +#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) +#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 +#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 +#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 +#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) +#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 +#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) +#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 +#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) +#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 +#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) +#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 +#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) +#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 +#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 +#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) +#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 +#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) +#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 +#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) +#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 +#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) +#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 +#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) +#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 +#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 +#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 +#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 +#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) +#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 +#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) +#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 +#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) +#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 +#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 +#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 +#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) +#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 +#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) +#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 +#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) +#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 +#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) +#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 +#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) +#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 +#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) +#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 +#define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) +#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 +#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) +#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 +#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) +#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 +#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) +#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 +#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) +#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 +#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) +#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 +#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) +#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 +#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) +#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 +#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) +#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 +#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) +#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 +#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) +#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 +#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) +#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 +#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) +#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 +#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) +#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 +#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) +#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 +#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) +#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 +#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) +#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 +#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) +#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 +#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) +#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 +#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) +#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 +#define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) +#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 +#define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) +#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 +#define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) +#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 +#define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) +#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 +#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) +#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 +#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) +#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 +#define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) +#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 +#define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) +#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 +#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 +#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 +#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 +#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) +#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 +#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) +#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 +#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) +#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 +#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) +#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 +#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) +#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 +#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) +#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 +#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) + +/* CM_CORE.IVA_CM_CORE register offsets */ +#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) +#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) + +/* CM_CORE.CAM_CM_CORE register offsets */ +#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) +#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) +#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) + +/* CM_CORE.DSS_CM_CORE register offsets */ +#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) +#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) + +/* CM_CORE.GPU_CM_CORE register offsets */ +#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) + +/* CM_CORE.L3INIT_CM_CORE register offsets */ +#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 +#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) +#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) +#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) +#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) +#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 +#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) +#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 +#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) +#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 +#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) +#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 +#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) +#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 +#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) +#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 +#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) +#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 +#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) +#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 +#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) + +/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ +#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) + +#endif diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index 64f4bafe7bd..9d1f4fcdebb 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs); extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h new file mode 100644 index 00000000000..cbb21169032 --- /dev/null +++ b/arch/arm/mach-omap2/cm_44xx_54xx.h @@ -0,0 +1,36 @@ +/* + * OMAP44xx and OMAP54xx CM1/CM2 function prototypes + * + * Copyright (C) 2009-2013 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H + +/* CM1 Function prototypes */ +extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); +extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +/* CM2 Function prototypes */ +extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); +extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index d555cf2459e..72cab3f4f16 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -96,6 +96,7 @@ void am33xx_init_early(void); void am35xx_init_early(void); void ti81xx_init_early(void); void am33xx_init_early(void); +void am43xx_init_early(void); void omap4430_init_early(void); void omap5_init_early(void); void omap3_init_late(void); /* Do not use this one */ @@ -237,8 +238,8 @@ extern void omap_do_wfi(void); #ifdef CONFIG_SMP /* Needed for secondary core boot */ -extern void omap_secondary_startup(void); -extern void omap_secondary_startup_4460(void); +extern void omap4_secondary_startup(void); +extern void omap4460_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 2adb2683f07..31e0dfe4a4e 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -249,6 +249,7 @@ void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : + soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 0; if (!offset) { diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index e6c328128a0..f7d7c2ef1b4 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -358,6 +358,18 @@ #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) +/* AM33XX PWMSS Control register */ +#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664 + +/* AM33XX PWMSS Control bitfields */ +#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0 +#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1 +#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2 + +/* DEV Feature register to identify AM33XX features */ +#define AM33XX_DEV_FEATURE 0x604 +#define AM33XX_SGX_MASK BIT(29) + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 4269fc14569..403c211e35d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -15,12 +15,12 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/gpio.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/pinctrl/machine.h> #include <linux/platform_data/omap4-keypad.h> -#include <linux/platform_data/omap_ocp2scp.h> -#include <linux/usb/omap_control_usb.h> +#include <linux/wl12xx.h> #include <asm/mach-types.h> #include <asm/mach/map.h> @@ -37,7 +37,6 @@ #include "mux.h" #include "control.h" #include "devices.h" -#include "dma.h" #define L3_MODULES_MAX_LEN 12 #define L3_MODULES 3 @@ -253,49 +252,6 @@ static inline void omap_init_camera(void) #endif } -#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB) -static struct omap_control_usb_platform_data omap4_control_usb_pdata = { - .type = 1, -}; - -struct resource omap4_control_usb_res[] = { - { - .name = "control_dev_conf", - .start = 0x4a002300, - .end = 0x4a002303, - .flags = IORESOURCE_MEM, - }, - { - .name = "otghs_control", - .start = 0x4a00233c, - .end = 0x4a00233f, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap4_control_usb = { - .name = "omap-control-usb", - .id = -1, - .dev = { - .platform_data = &omap4_control_usb_pdata, - }, - .num_resources = 2, - .resource = omap4_control_usb_res, -}; - -static inline void __init omap_init_control_usb(void) -{ - if (!cpu_is_omap44xx()) - return; - - if (platform_device_register(&omap4_control_usb)) - pr_err("Error registering omap_control_usb device\n"); -} - -#else -static inline void omap_init_control_usb(void) { } -#endif /* CONFIG_OMAP_CONTROL_USB */ - int __init omap4_keyboard_init(struct omap4_keypad_platform_data *sdp4430_keypad_data, struct omap_board_data *bdata) { @@ -374,10 +330,8 @@ static void __init omap_init_mcpdm(void) struct platform_device *pdev; oh = omap_hwmod_lookup("mcpdm"); - if (!oh) { - printk(KERN_ERR "Could not look up mcpdm hw_mod\n"); + if (!oh) return; - } pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0); WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n"); @@ -395,10 +349,8 @@ static void __init omap_init_dmic(void) struct platform_device *pdev; oh = omap_hwmod_lookup("dmic"); - if (!oh) { - pr_err("Could not look up dmic hw_mod\n"); + if (!oh) return; - } pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0); WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); @@ -421,10 +373,8 @@ static void __init omap_init_hdmi_audio(void) struct platform_device *pdev; oh = omap_hwmod_lookup("dss_hdmi"); - if (!oh) { - printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n"); + if (!oh) return; - } pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0); WARN(IS_ERR(pdev), @@ -557,80 +507,38 @@ static void omap_init_vout(void) static inline void omap_init_vout(void) {} #endif -#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE) -static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev) -{ - int cnt = 0; +#if IS_ENABLED(CONFIG_WL12XX) - while (ocp2scp_dev->drv_name != NULL) { - cnt++; - ocp2scp_dev++; - } +static struct wl12xx_platform_data wl12xx __initdata; - return cnt; -} - -static void __init omap_init_ocp2scp(void) +void __init omap_init_wl12xx_of(void) { - struct omap_hwmod *oh; - struct platform_device *pdev; - int bus_id = -1, dev_cnt = 0, i; - struct omap_ocp2scp_dev *ocp2scp_dev; - const char *oh_name, *name; - struct omap_ocp2scp_platform_data *pdata; - - if (!cpu_is_omap44xx()) - return; - - oh_name = "ocp2scp_usb_phy"; - name = "omap-ocp2scp"; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("%s: could not find omap_hwmod for %s\n", __func__, - oh_name); - return; - } + int ret; - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) { - pr_err("%s: No memory for ocp2scp pdata\n", __func__); + if (!of_have_populated_dt()) return; - } - ocp2scp_dev = oh->dev_attr; - dev_cnt = count_ocp2scp_devices(ocp2scp_dev); - - if (!dev_cnt) { - pr_err("%s: No devices connected to ocp2scp\n", __func__); - kfree(pdata); + if (of_machine_is_compatible("ti,omap4-sdp")) { + wl12xx.board_ref_clock = WL12XX_REFCLOCK_26; + wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26; + wl12xx.irq = gpio_to_irq(53); + } else if (of_machine_is_compatible("ti,omap4-panda")) { + wl12xx.board_ref_clock = WL12XX_REFCLOCK_38; + wl12xx.irq = gpio_to_irq(53); + } else { return; } - pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *) - * dev_cnt, GFP_KERNEL); - if (!pdata->devices) { - pr_err("%s: No memory for ocp2scp pdata devices\n", __func__); - kfree(pdata); - return; - } - - for (i = 0; i < dev_cnt; i++, ocp2scp_dev++) - pdata->devices[i] = ocp2scp_dev; - - pdata->dev_cnt = dev_cnt; - - pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata)); - if (IS_ERR(pdev)) { - pr_err("Could not build omap_device for %s %s\n", - name, oh_name); - kfree(pdata->devices); - kfree(pdata); + ret = wl12xx_set_platform_data(&wl12xx); + if (ret) { + pr_err("error setting wl12xx data: %d\n", ret); return; } } #else -static inline void omap_init_ocp2scp(void) { } +static inline void omap_init_wl12xx_of(void) +{ +} #endif /*-------------------------------------------------------------------------*/ @@ -651,17 +559,18 @@ static int __init omap2_init_devices(void) omap_init_mbox(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { - omap_init_control_usb(); omap_init_dmic(); omap_init_mcpdm(); omap_init_mcspi(); omap_init_sham(); omap_init_aes(); + } else { + /* These can be removed when bindings are done */ + omap_init_wl12xx_of(); } omap_init_sti(); omap_init_rng(); omap_init_vout(); - omap_init_ocp2scp(); return 0; } diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h deleted file mode 100644 index 65f80cacf17..00000000000 --- a/arch/arm/mach-omap2/dma.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * OMAP2PLUS DMA channel definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __OMAP2PLUS_DMA_CHANNEL_H -#define __OMAP2PLUS_DMA_CHANNEL_H - - -/* DMA channels for 24xx */ -#define OMAP24XX_DMA_NO_DEVICE 0 -#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ -#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ -#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ -#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ -#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ -#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ -#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ -#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ -#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ -#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ -#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ -#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ -#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ -#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ -#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ -#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ -#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ -#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ -#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ -#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ -#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ -#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ -#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ -#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ -#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ -#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ -#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ - -#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ -#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ - -/* Only for AM35xx */ -#define AM35XX_DMA_UART4_TX 54 -#define AM35XX_DMA_UART4_RX 55 - -#endif /* __OMAP2PLUS_DMA_CHANNEL_H */ diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 2ef1f8714fc..07d4c7b3575 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -29,7 +29,6 @@ static u16 control_pbias_offset; static u16 control_devconf1_offset; -static u16 control_mmc1; #define HSMMC_NAME_LEN 9 @@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot, } } -static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, - int power_on, int vdd) -{ - u32 reg; - - /* - * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the - * card with Vcc regulator (from twl4030 or whatever). OMAP has both - * 1.8V and 3.0V modes, controlled by the PBIAS register. - */ - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK | - OMAP4_MMC1_PBIASLITE_VMODE_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); -} - -static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, - int power_on, int vdd) -{ - u32 reg; - unsigned long timeout; - - if (power_on) { - reg = omap4_ctrl_pad_readl(control_pbias_offset); - reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; - if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; - else - reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | - OMAP4_MMC1_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); - - timeout = jiffies + msecs_to_jiffies(5); - do { - reg = omap4_ctrl_pad_readl(control_pbias_offset); - if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK)) - break; - usleep_range(100, 200); - } while (!time_after(jiffies, timeout)); - - if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { - pr_err("Pbias Voltage is not same as LDO\n"); - /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ_MASK); - omap4_ctrl_pad_writel(reg, control_pbias_offset); - } - } -} - static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc) { u32 reg; @@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, mmc->slots[0].pm_caps = c->pm_caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->max_freq = c->max_freq; - if (cpu_is_omap44xx()) - mmc->reg_offset = OMAP4_MMC_REG_OFFSET; - else - mmc->reg_offset = 0; - + mmc->reg_offset = 0; mmc->get_context_loss_count = hsmmc_get_context_loss; mmc->slots[0].switch_pin = c->gpio_cd; @@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, if (!soc_is_am35xx()) mmc->slots[0].features |= HSMMC_HAS_PBIAS; - if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) - mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; - switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { /* on-chip level shifting via PBIAS0/PBIAS1 */ - if (cpu_is_omap44xx()) { - mmc->slots[0].before_set_reg = - omap4_hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = - omap4_hsmmc1_after_set_reg; - } else { - mmc->slots[0].before_set_reg = - omap_hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = - omap_hsmmc1_after_set_reg; - } + mmc->slots[0].before_set_reg = + omap_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap_hsmmc1_after_set_reg; } if (soc_is_am35xx()) @@ -563,34 +497,17 @@ free_mmc: void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers) { - u32 reg; - if (omap_hsmmc_done) return; omap_hsmmc_done = 1; - if (!cpu_is_omap44xx()) { - if (cpu_is_omap2430()) { - control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; - } else { - control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; - control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; - } + if (cpu_is_omap2430()) { + control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; } else { - control_pbias_offset = - OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; - control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; - reg = omap4_ctrl_pad_readl(control_mmc1); - reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | - OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); - reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | - OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); - reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK | - OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | - OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); - omap4_ctrl_pad_writel(reg, control_mmc1); + control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } for (; controllers->mmc; controllers++) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 1272c41d474..2dc62a25f2c 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -55,7 +55,7 @@ int omap_type(void) if (cpu_is_omap24xx()) { val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); - } else if (soc_is_am33xx()) { + } else if (soc_is_am33xx() || soc_is_am43xx()) { val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); @@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void) cpu_name = "TI816X"; } else if (soc_is_am335x()) { cpu_name = "AM335X"; + } else if (soc_is_am437x()) { + cpu_name = "AM437x"; } else if (cpu_is_ti814x()) { cpu_name = "TI814X"; } else if (omap3_has_iva() && omap3_has_sgx()) { @@ -302,6 +304,19 @@ void __init ti81xx_check_features(void) omap3_cpuinfo(); } +void __init am33xx_check_features(void) +{ + u32 status; + + omap_features = OMAP3_HAS_NEON; + + status = omap_ctrl_readl(AM33XX_DEV_FEATURE); + if (status & AM33XX_SGX_MASK) + omap_features |= OMAP3_HAS_SGX; + + omap3_cpuinfo(); +} + void __init omap3xxx_check_revision(void) { const char *cpu_rev; @@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void) cpu_rev = "1.0"; break; case 1: - /* FALLTHROUGH */ - default: omap_revision = TI8168_REV_ES1_1; cpu_rev = "1.1"; break; + case 2: + omap_revision = TI8168_REV_ES2_0; + cpu_rev = "2.0"; + break; + case 3: + /* FALLTHROUGH */ + default: + omap_revision = TI8168_REV_ES2_1; + cpu_rev = "2.1"; } break; case 0xb944: @@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void) break; } break; + case 0xb98c: + omap_revision = AM437X_REV_ES1_0; + cpu_rev = "1.0"; + break; case 0xb8f2: switch (rev) { case 0: @@ -601,7 +627,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap) #ifdef CONFIG_SOC_BUS -static const char const *omap_types[] = { +static const char * const omap_types[] = { [OMAP2_DEVICE_TYPE_TEST] = "TST", [OMAP2_DEVICE_TYPE_EMU] = "EMU", [OMAP2_DEVICE_TYPE_SEC] = "HS", diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 09abf99e9e5..fe3253a100e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = { }; #endif -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) static struct map_desc omapam33xx_io_desc[] __initdata = { { .virtual = L4_34XX_VIRT, @@ -318,7 +318,7 @@ void __init ti81xx_map_io(void) } #endif -#ifdef CONFIG_SOC_AM33XX +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) void __init am33xx_map_io(void) { iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); @@ -576,8 +576,7 @@ void __init am33xx_init_early(void) omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); omap3xxx_check_revision(); - ti81xx_check_features(); - am33xx_voltagedomains_init(); + am33xx_check_features(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); am33xx_hwmod_init(); @@ -586,6 +585,19 @@ void __init am33xx_init_early(void) } #endif +#ifdef CONFIG_SOC_AM43XX +void __init am43xx_init_early(void) +{ + omap2_set_globals_tap(AM335X_CLASS, + AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); + omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); + omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); + omap3xxx_check_revision(); +} +#endif + #ifdef CONFIG_ARCH_OMAP4 void __init omap4430_init_early(void) { @@ -631,7 +643,13 @@ void __init omap5_init_early(void) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap_prm_base_init(); omap_cm_base_init(); + omap44xx_prm_init(); omap5xxx_check_revision(); + omap54xx_voltagedomains_init(); + omap54xx_powerdomains_init(); + omap54xx_clockdomains_init(); + omap54xx_hwmod_init(); + omap_hwmod_init_postsetup(); } #endif diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index fdb22f14021..5d2080ef792 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -10,7 +10,6 @@ #include "mux2420.h" #include "mux2430.h" #include "mux34xx.h" -#include "mux44xx.h" #define OMAP_MUX_TERMINATOR 0xffff @@ -64,8 +63,6 @@ /* Flags for omapX_mux_init */ #define OMAP_PACKAGE_MASK 0xffff -#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */ -#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */ #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c deleted file mode 100644 index f5a74daab2f..00000000000 --- a/arch/arm/mach-omap2/mux44xx.c +++ /dev/null @@ -1,1356 +0,0 @@ -/* - * OMAP44xx ES1.0 pin mux definition - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * - * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com> - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/init.h> - -#include "mux.h" - -#ifdef CONFIG_OMAP_MUX - -#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ - .gpio = (g), \ - .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ -} - -#else - -#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ -{ \ - .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ - .gpio = (g), \ -} - -#endif - -#define _OMAP4_BALLENTRY(M0, bb, bt) \ -{ \ - .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ - .balls = { bb, bt }, \ -} - -/* - * Superset of all mux modes for omap4 ES1.0 - */ -static struct omap_mux __initdata omap4_core_muxmodes[] = { - _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", - "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", - "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", - "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", - "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", - "gpio_32", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", - "gpio_33", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", - "gpio_34", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", - "gpio_35", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", - "gpio_36", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", - "gpio_37", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", - "gpio_38", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", - "gpio_39", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", - "gpio_40", "venc_656_data0", NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", - "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", - "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", - "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", - "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", - "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", - "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", - "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0", - "gpio_48", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", - "gpio_49", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", - "sys_ndmareq0", NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", - "gpio_51", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7", - "gpio_52", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", - "c2c_dataout4", "gpio_53", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", - "sys_ndmareq1", NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", - "sys_ndmareq2", NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, - "gpio_56", "sys_ndmareq3", NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, - "gpio_59", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", - "gpio_60", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, - "gpio_61", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", - "gpio_62", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen", - "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0", - "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1", - "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0", - "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1", - "c2c_dataout1", "gpio_104", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, - "gpio_65", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, - "gpio_66", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, - "gpio_83", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", - "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", - NULL, "hw_dbg20", "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", - "hsi1_cadata", "mcbsp4_clkr", "gpio_85", - "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", - "hsi1_caflag", "mcbsp4_fsr", "gpio_86", - "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", - "hsi1_acready", "mcbsp4_fsx", "gpio_87", - "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", - "hsi1_acwake", "mcbsp4_clkx", "gpio_88", - "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", - "hsi1_acdata", "mcbsp4_dx", "gpio_89", - "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", - "hsi1_acflag", "mcbsp4_dr", "gpio_90", - "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", - "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", - "usbb1_mm_txen", "hw_dbg27", "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", - "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", - "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", - "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", - "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", - "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", - "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", - "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", - "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, - "gpio_96", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, - NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, - "gpio_98", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, - "gpio_99", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", - "gpio_100", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", - "gpio_101", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", - "gpio_102", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", - "gpio_103", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", - "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", - "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, - "gpio_106", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, - "gpio_107", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, - "gpio_108", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, - "gpio_109", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", - "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", - "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", - "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", - "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", - "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", - "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", - "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", - "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", - "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", - "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", - NULL, NULL, NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", - NULL, NULL, NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, - "gpio_119", "usbb2_mm_txse0", NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, - "gpio_120", "usbb2_mm_txdat", NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", - NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", - "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, - "gpio_123", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, - "gpio_124", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, - "gpio_125", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, - "gpio_126", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", - "gpio_127", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, - "gpio_128", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, - "gpio_129", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, - "gpio_135", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, - "gpio_136", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, - "gpio_138", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", - "slimbus2_clock", "gpio_139", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", - "slimbus2_data", "gpio_140", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", - NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, - "gpio_142", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", - "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", - "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", - "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", - "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", - "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, - "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, - "gpio_149", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, - "gpio_150", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL, - "gpio_151", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL, - "gpio_152", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL, - "gpio_153", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL, - "gpio_154", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL, - "gpio_155", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL, - "gpio_156", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", - "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", - "hsi2_cawake", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", - "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", - "hsi2_cadata", "dispc2_data23", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", - "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", - "hsi2_caflag", "dispc2_data22", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", - "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", - "hsi2_acready", "dispc2_data21", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", - "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", - "hsi2_acwake", "dispc2_data20", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", - "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", - "hsi2_acdata", "dispc2_data19", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", - "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", - "hsi2_acflag", "dispc2_data18", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", - "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", - "hsi2_caready", "dispc2_data15", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", - "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", - "mcspi3_somi", "dispc2_data14", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", - "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", - "mcspi3_cs0", "dispc2_data13", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", - "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", - "mcspi3_simo", "dispc2_data12", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", - "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", - "mcspi3_clk", "dispc2_data11", NULL, "reserved"), - _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, - "gpio_169", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, - NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL, - "gpio_171", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL, - "gpio_172", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL, - "gpio_173", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL, - "gpio_174", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL, - "gpio_0", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL, - "gpio_1", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL, - "gpi_175", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL, - "gpi_176", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL, - "gpi_177", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL, - "gpi_178", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL, - "gpi_2", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL, - "gpi_3", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx", - "uart2_rx", "gpio_179", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx", - "uart2_tx", "gpio_180", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, - "gpio_181", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, - "gpio_182", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, - NULL, "hw_dbg0", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, - NULL, "hw_dbg1", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, - "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, - "gpio_14", NULL, "dispc2_data10", "hw_dbg3", - "reserved"), - _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, - "gpio_15", NULL, "dispc2_data9", "hw_dbg4", - "reserved"), - _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, - "gpio_16", "rfbi_te_vsync0", "dispc2_data16", - "hw_dbg5", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", - "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", - "dispc2_data17", "hw_dbg6", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", - "uart3_rx_irrx", "gpio_18", "rfbi_cs0", - "dispc2_hsync", "hw_dbg7", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", - "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", - "hw_dbg8", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", - "uart3_cts_rctx", "gpio_20", "rfbi_we", - "dispc2_vsync", "hw_dbg9", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", - NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", - "reserved"), - _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", - NULL, "gpio_22", "rfbi_data8", "dispc2_data8", - "hw_dbg11", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", - NULL, "gpio_23", "rfbi_data7", "dispc2_data7", - "hw_dbg12", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", - NULL, "gpio_24", "rfbi_data6", "dispc2_data6", - "hw_dbg13", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", - "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", - "hw_dbg14", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", - NULL, "gpio_26", "rfbi_data4", "dispc2_data4", - "hw_dbg15", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", - "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", - "hw_dbg16", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", - "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", - "hw_dbg17", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", - "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", - "hw_dbg18", "reserved"), - _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", - "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", - "hw_dbg19", "reserved"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for 44XX CBL package - * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), - * 0.40mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CBL) -static struct omap_ball __initdata omap4_core_cbl_ball[] = { - _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), - _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), - _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), - _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), - _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), - _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), - _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), - _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), - _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), - _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), - _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), - _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), - _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), - _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), - _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), - _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), - _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), - _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), - _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), - _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), - _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), - _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), - _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), - _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), - _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), - _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), - _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), - _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), - _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), - _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), - _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), - _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), - _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), - _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), - _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), - _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), - _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), - _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), - _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), - _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL), - _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL), - _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL), - _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL), - _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL), - _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), - _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), - _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), - _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), - _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), - _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), - _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), - _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), - _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), - _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), - _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), - _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), - _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), - _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), - _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), - _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), - _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), - _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), - _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), - _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), - _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), - _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), - _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), - _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), - _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), - _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), - _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), - _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), - _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), - _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), - _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), - _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), - _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), - _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), - _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), - _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), - _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), - _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), - _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), - _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), - _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), - _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), - _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), - _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), - _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), - _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), - _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), - _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), - _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), - _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), - _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), - _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), - _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), - _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), - _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), - _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), - _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), - _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), - _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), - _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), - _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), - _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), - _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL), - _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL), - _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL), - _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL), - _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL), - _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL), - _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL), - _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL), - _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL), - _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL), - _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL), - _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL), - _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), - _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), - _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), - _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), - _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), - _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), - _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), - _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), - _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), - _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), - _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), - _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), - _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), - _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), - _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), - _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), - _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), - _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), - _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), - _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), - _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), - _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), - _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), - _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), - _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), - _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), - _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), - _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), - _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), - _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), - _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), - _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), - _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap4_core_cbl_ball NULL -#endif - -/* - * Signals different on ES2.0 compared to superset - */ -static struct omap_mux __initdata omap4_es2_core_subset[] = { - _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", - "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", - "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", - "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", - "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", - "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", - "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", - "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", - "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", - "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0", - "gpio_48", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8", - "c2c_dataout7", "gpio_52", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", - "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, - "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL), - _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen", - "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", - "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", - "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0", - "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1", - "c2c_dataout1", "gpio_104", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", - "hsi1_acwake", "mcbsp4_clkx", "gpio_88", - "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", - "hsi1_acdata", "mcbsp4_dx", "gpio_89", - "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", - "hsi1_acflag", "mcbsp4_dr", "gpio_90", - "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", - "safe_mode"), - _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", - "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", - "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, - "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, - "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, - "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", - "abe_mcasp_axr", "gpio_121", NULL, - "dmtimer11_pwm_evt", NULL, "safe_mode"), - _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", - "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", - NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", - "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", - NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", - "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", - NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", - "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", - NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, - "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", - NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, - "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"), - _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, - "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", - "kpd_col6", "gpio_151", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", - "kpd_col7", "gpio_152", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", - "kpd_row6", "gpio_153", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", - "kpd_row7", "gpio_154", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8", - "gpio_155", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8", - "gpio_156", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", - "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", - "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", - "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", - "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", - "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", - "hsi2_acready", "dispc2_data21", NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", - "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", - "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", - "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", - "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", - "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", - "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", - "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", - "hsi2_caready", "dispc2_data15", "rfbi_data15", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", - "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", - "mcspi3_somi", "dispc2_data14", "rfbi_data14", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", - "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", - "mcspi3_cs0", "dispc2_data13", "rfbi_data13", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", - "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", - "mcspi3_simo", "dispc2_data12", "rfbi_data12", - "safe_mode"), - _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", - "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", - "mcspi3_clk", "dispc2_data11", "rfbi_data11", - "safe_mode"), - _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL, - "gpio_171", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL, - "gpio_172", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL, - "gpio_173", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL, - "gpio_174", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL, - "gpio_175", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL, - "gpio_176", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL, - "gpio_177", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL, - "gpio_178", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx", - "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx", - "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, - "gpio_13", NULL, "dispc2_fid", "hw_dbg2", - "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, - "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", - "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, - "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", - "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, - "gpio_16", "rfbi_te_vsync0", "dispc2_data16", - "hw_dbg5", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", - "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", - "dispc2_data17", "hw_dbg6", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", - "uart3_rx_irrx", "gpio_18", "rfbi_cs0", - "dispc2_hsync", "hw_dbg7", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", - "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", - "hw_dbg8", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", - "uart3_cts_rctx", "gpio_20", "rfbi_we", - "dispc2_vsync", "hw_dbg9", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", - NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", - "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", - NULL, "gpio_22", "rfbi_data8", "dispc2_data8", - "hw_dbg11", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", - NULL, "gpio_23", "rfbi_data7", "dispc2_data7", - "hw_dbg12", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", - NULL, "gpio_24", "rfbi_data6", "dispc2_data6", - "hw_dbg13", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", - "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", - "hw_dbg14", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", - NULL, "gpio_26", "rfbi_data4", "dispc2_data4", - "hw_dbg15", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", - "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", - "hw_dbg16", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", - "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", - "hw_dbg17", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", - "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", - "hw_dbg18", "safe_mode"), - _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", - "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", - "hw_dbg19", "safe_mode"), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for 44XX CBS package - * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), - * 0.40mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CBS) -static struct omap_ball __initdata omap4_core_cbs_ball[] = { - _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), - _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), - _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), - _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), - _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), - _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), - _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), - _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), - _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), - _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), - _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), - _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), - _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), - _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), - _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), - _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), - _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), - _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), - _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), - _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), - _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), - _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), - _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), - _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), - _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), - _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), - _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), - _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), - _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), - _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), - _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), - _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), - _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), - _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), - _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), - _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), - _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), - _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), - _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), - _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL), - _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL), - _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL), - _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL), - _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL), - _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), - _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), - _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), - _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), - _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), - _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), - _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), - _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), - _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), - _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), - _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), - _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), - _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), - _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), - _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), - _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), - _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), - _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), - _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), - _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), - _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), - _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), - _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), - _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), - _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), - _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), - _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), - _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), - _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), - _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), - _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), - _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), - _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), - _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), - _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), - _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), - _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), - _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), - _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), - _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), - _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), - _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), - _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), - _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), - _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), - _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), - _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), - _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), - _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), - _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), - _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), - _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), - _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), - _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), - _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), - _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), - _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), - _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), - _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), - _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), - _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), - _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), - _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), - _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), - _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), - _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), - _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), - _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), - _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), - _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL), - _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL), - _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL), - _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL), - _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL), - _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL), - _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL), - _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL), - _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL), - _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL), - _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL), - _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL), - _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), - _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), - _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), - _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), - _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), - _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), - _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), - _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), - _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), - _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), - _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), - _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), - _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), - _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), - _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), - _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), - _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), - _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), - _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), - _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), - _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), - _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), - _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), - _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), - _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), - _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), - _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), - _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), - _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), - _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), - _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), - _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), - _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap4_core_cbs_ball NULL -#endif - -/* - * Superset of all mux modes for omap4 - */ -static struct omap_mux __initdata omap4_wkup_muxmodes[] = { - _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, - "c2c_wakereqin", NULL, NULL, NULL), - _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, - "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", - "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", - "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", - "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", - NULL, "gpio_wk7", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, - "gpio_wk8", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, - NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, - NULL, "gpio_wk29", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, - "gpio_wk9", "c2c_wakereqout", NULL, NULL, - "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, - "gpio_wk10", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, - NULL, NULL, NULL), - _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, - NULL, NULL, NULL), - _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for 44XX CBL & CBS package - wakeup partition - * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), - * 0.40mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CBL) -static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { - _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), - _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), - _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), - _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), - _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), - _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), - _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), - _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), - _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), - _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), - _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL), - _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL), - _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL), - _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL), - _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL), - _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL), - _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL), - _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL), - _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL), - _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL), - _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL), - _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL), - _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL), - _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL), - _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL), - _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL), - _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL), - _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define omap4_wkup_cbl_cbs_ball NULL -#endif - -int __init omap4_mux_init(struct omap_board_mux *board_subset, - struct omap_board_mux *board_wkup_subset, int flags) -{ - struct omap_ball *package_balls_core; - struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball; - struct omap_mux *core_muxmodes; - struct omap_mux *core_subset = NULL; - int ret; - - switch (flags & OMAP_PACKAGE_MASK) { - case OMAP_PACKAGE_CBL: - pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__); - package_balls_core = omap4_core_cbl_ball; - core_muxmodes = omap4_core_muxmodes; - break; - case OMAP_PACKAGE_CBS: - pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__); - package_balls_core = omap4_core_cbs_ball; - core_muxmodes = omap4_core_muxmodes; - core_subset = omap4_es2_core_subset; - break; - default: - pr_err("%s: Unknown omap package, mux disabled\n", __func__); - return -EINVAL; - } - - ret = omap_mux_init("core", - OMAP_MUX_GPIO_IN_MODE3, - OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE, - OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE, - core_muxmodes, core_subset, board_subset, - package_balls_core); - if (ret) - return ret; - - ret = omap_mux_init("wkup", - OMAP_MUX_GPIO_IN_MODE3, - OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE, - OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE, - omap4_wkup_muxmodes, NULL, board_wkup_subset, - package_balls_wkup); - - return ret; -} - diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h deleted file mode 100644 index c635026cd7e..00000000000 --- a/arch/arm/mach-omap2/mux44xx.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * OMAP44xx MUX registers and bitfields - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H -#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H - -#define OMAP4_MUX(M0, mux_value) \ -{ \ - .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ - .value = (mux_value), \ -} - -/* ctrl_module_pad_core base address */ -#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000 - -/* ctrl_module_pad_core registers offset */ -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058 -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c -#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e -#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060 -#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062 -#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064 -#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066 -#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068 -#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a -#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c -#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e -#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070 -#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a -#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c -#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e -#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088 -#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a -#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c -#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e -#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090 -#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092 -#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094 -#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096 -#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098 -#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a -#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c -#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e -#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0 -#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2 -#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4 -#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6 -#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8 -#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa -#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac -#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae -#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0 -#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2 -#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4 -#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6 -#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8 -#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba -#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc -#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be -#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6 -#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8 -#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da -#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc -#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de -#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2 -#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4 -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6 -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8 -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100 -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102 -#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104 -#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106 -#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108 -#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a -#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c -#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e -#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110 -#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112 -#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114 -#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116 -#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118 -#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a -#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c -#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e -#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120 -#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122 -#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124 -#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126 -#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128 -#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a -#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c -#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e -#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130 -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132 -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134 -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136 -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138 -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c -#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e -#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140 -#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142 -#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144 -#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146 -#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148 -#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a -#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c -#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e -#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150 -#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152 -#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154 -#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156 -#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158 -#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a -#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c -#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174 -#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176 -#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178 -#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180 -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182 -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184 -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186 -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188 -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190 -#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192 -#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194 -#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196 -#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198 -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c -#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e -#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 -#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 - -/* ES2.0 only */ -#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094 -#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096 - -#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c -#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e -#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180 -#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182 -#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184 -#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186 -#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188 -#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a -#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c -#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e -#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190 -#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192 - - -#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ - (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ - - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) - -/* ctrl_module_pad_wkup base address */ -#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000 - -/* ctrl_module_pad_wkup registers offset */ -#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040 -#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042 -#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044 -#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046 -#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048 -#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a -#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c -#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e -#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050 -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052 -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054 -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056 -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058 -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a -#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c -#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e -#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060 -#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062 -#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064 -#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068 -#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a -#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c -#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e -#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070 -#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072 -#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074 -#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076 - -#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \ - (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \ - - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2) - -#endif diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 0ea09faf327..4ea30811416 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -49,7 +49,7 @@ END(omap5_secondary_startup) * The primary core will update this flag using a hardware * register AuxCoreBoot0. */ -ENTRY(omap_secondary_startup) +ENTRY(omap4_secondary_startup) hold: ldr r12,=0x103 dsb smc #0 @ read from AuxCoreBoot0 @@ -64,9 +64,9 @@ hold: ldr r12,=0x103 * should now contain the SVC stack for this core */ b secondary_startup -ENDPROC(omap_secondary_startup) +ENDPROC(omap4_secondary_startup) -ENTRY(omap_secondary_startup_4460) +ENTRY(omap4460_secondary_startup) hold_2: ldr r12,=0x103 dsb smc #0 @ read from AuxCoreBoot0 @@ -101,4 +101,4 @@ hold_2: ldr r12,=0x103 * should now contain the SVC stack for this core */ b secondary_startup -ENDPROC(omap_secondary_startup_4460) +ENDPROC(omap4460_secondary_startup) diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index e80327b6c81..f993a418870 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -71,10 +71,43 @@ struct omap4_cpu_pm_info { void (*secondary_startup)(void); }; +/** + * struct cpu_pm_ops - CPU pm operations + * @finish_suspend: CPU suspend finisher function pointer + * @resume: CPU resume function pointer + * @scu_prepare: CPU Snoop Control program function pointer + * + * Structure holds functions pointer for CPU low power operations like + * suspend, resume and scu programming. + */ +struct cpu_pm_ops { + int (*finish_suspend)(unsigned long cpu_state); + void (*resume)(void); + void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state); +}; + static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); static struct powerdomain *mpuss_pd; static void __iomem *sar_base; +static int default_finish_suspend(unsigned long cpu_state) +{ + omap_do_wfi(); + return 0; +} + +static void dummy_cpu_resume(void) +{} + +static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state) +{} + +struct cpu_pm_ops omap_pm_ops = { + .finish_suspend = default_finish_suspend, + .resume = dummy_cpu_resume, + .scu_prepare = dummy_scu_prepare, +}; + /* * Program the wakeup routine address for the CPU0 and CPU1 * used for OFF or DORMANT wakeup. @@ -158,11 +191,12 @@ static void save_l2x0_context(void) { u32 val; void __iomem *l2x0_base = omap4_get_l2cache_base(); - - val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); - __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); - val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); - __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); + if (l2x0_base) { + val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); + __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); + val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); + __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); + } } #else static void save_l2x0_context(void) @@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) cpu_clear_prev_logic_pwrst(cpu); pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); - set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); - scu_pwrst_prepare(cpu, power_state); + set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume)); + omap_pm_ops.scu_prepare(cpu, power_state); l2x0_pwrst_prepare(cpu, save_state); /* * Call low level function with targeted low power state. */ - cpu_suspend(save_state, omap4_finish_suspend); + if (save_state) + cpu_suspend(save_state, omap_pm_ops.finish_suspend); + else + omap_pm_ops.finish_suspend(save_state); /* * Restore the CPUx power state to ON otherwise CPUx @@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); - scu_pwrst_prepare(cpu, power_state); + omap_pm_ops.scu_prepare(cpu, power_state); /* * CPU never retuns back if targeted power state is OFF mode. * CPU ONLINE follows normal CPU ONLINE ptah via - * omap_secondary_startup(). + * omap4_secondary_startup(). */ - omap4_finish_suspend(cpu_state); + omap_pm_ops.finish_suspend(cpu_state); pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); return 0; @@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void) pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; if (cpu_is_omap446x()) - pm_info->secondary_startup = omap_secondary_startup_4460; + pm_info->secondary_startup = omap4460_secondary_startup; else - pm_info->secondary_startup = omap_secondary_startup; + pm_info->secondary_startup = omap4_secondary_startup; pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); if (!pm_info->pwrdm) { @@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void) save_l2x0_context(); + if (cpu_is_omap44xx()) { + omap_pm_ops.finish_suspend = omap4_finish_suspend; + omap_pm_ops.resume = omap4_cpu_resume; + omap_pm_ops.scu_prepare = scu_pwrst_prepare; + } + return 0; } diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 2a551f997ae..98a11463a84 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * /* * Update the AuxCoreBoot0 with boot state for secondary core. - * omap_secondary_startup() routine will hold the secondary core till + * omap4_secondary_startup() routine will hold the secondary core till * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ @@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void) static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { - void *startup_addr = omap_secondary_startup; + void *startup_addr = omap4_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); /* @@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) scu_enable(scu_base); if (cpu_is_omap446x()) { - startup_addr = omap_secondary_startup_4460; + startup_addr = omap4460_secondary_startup; pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; } diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 13b27ffaf45..38cd3a69cff 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -339,19 +339,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } #endif - -/** - * omap44xx_restart - trigger a software restart of the SoC - * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c - * @cmd: passed from the userspace program rebooting the system (if provided) - * - * Resets the SoC. For @cmd, see the 'reboot' syscall in - * kernel/sys.c. No return value. - */ -void omap44xx_restart(char mode, const char *cmd) -{ - /* XXX Should save 'cmd' into scratchpad for use after reboot */ - omap4_prminst_global_warm_sw_reset(); /* never returns */ - while (1); -} - diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c new file mode 100644 index 00000000000..f90e02e1189 --- /dev/null +++ b/arch/arm/mach-omap2/omap4-restart.c @@ -0,0 +1,27 @@ +/* + * omap4-restart.c - Common to OMAP4 and OMAP5 + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/types.h> +#include "prminst44xx.h" + +/** + * omap44xx_restart - trigger a software restart of the SoC + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c + * @cmd: passed from the userspace program rebooting the system (if provided) + * + * Resets the SoC. For @cmd, see the 'reboot' syscall in + * kernel/sys.c. No return value. + */ +void omap44xx_restart(char mode, const char *cmd) +{ + /* XXX Should save 'cmd' into scratchpad for use after reboot */ + omap4_prminst_global_warm_sw_reset(); /* never returns */ + while (1) + ; +} diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index e6d230700b2..68be532f868 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -170,9 +170,6 @@ static int omap_device_build_from_dt(struct platform_device *pdev) r->name = dev_name(&pdev->dev); } - if (of_get_property(node, "ti,no_idle_on_suspend", NULL)) - omap_device_disable_idle_on_suspend(pdev); - pdev->dev.pm_domain = &omap_device_pm_domain; odbfd_exit1: @@ -621,8 +618,7 @@ static int _od_suspend_noirq(struct device *dev) if (!ret && !pm_runtime_status_suspended(dev)) { if (pm_generic_runtime_suspend(dev) == 0) { - if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)) - omap_device_idle(pdev); + omap_device_idle(pdev); od->flags |= OMAP_DEVICE_SUSPENDED; } } @@ -638,8 +634,7 @@ static int _od_resume_noirq(struct device *dev) if ((od->flags & OMAP_DEVICE_SUSPENDED) && !pm_runtime_status_suspended(dev)) { od->flags &= ~OMAP_DEVICE_SUSPENDED; - if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)) - omap_device_enable(pdev); + omap_device_enable(pdev); pm_generic_runtime_resume(dev); } diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h index 044c31d50e5..17ca1aec271 100644 --- a/arch/arm/mach-omap2/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h @@ -38,7 +38,6 @@ extern struct dev_pm_domain omap_device_pm_domain; /* omap_device.flags values */ #define OMAP_DEVICE_SUSPENDED BIT(0) -#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1) /** * struct omap_device - omap_device wrapper for platform_devices @@ -101,13 +100,4 @@ static inline struct omap_device *to_omap_device(struct platform_device *pdev) { return pdev ? pdev->archdata.od : NULL; } - -static inline -void omap_device_disable_idle_on_suspend(struct platform_device *pdev) -{ - struct omap_device *od = to_omap_device(pdev); - - od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND; -} - #endif diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0c898f58ac9..aab33fd814c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void); extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); +extern int omap54xx_hwmod_init(void); extern int am33xx_hwmod_init(void); extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 534974e08ad..5da7a42a6d9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -17,7 +17,6 @@ #include "hdq1w.h" #include "omap_hwmod_common_data.h" -#include "dma.h" /* UART */ @@ -89,32 +88,32 @@ struct omap_hwmod_class omap2_venc_hwmod_class = { /* Common DMA request line data */ struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, + { .name = "rx", .dma_req = 50, }, + { .name = "tx", .dma_req = 49, }, { .dma_req = -1 } }; struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, + { .name = "rx", .dma_req = 52, }, + { .name = "tx", .dma_req = 51, }, { .dma_req = -1 } }; struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, - { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, + { .name = "rx", .dma_req = 54, }, + { .name = "tx", .dma_req = 53, }, { .dma_req = -1 } }; struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, - { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, + { .name = "tx", .dma_req = 27 }, + { .name = "rx", .dma_req = 28 }, { .dma_req = -1 } }; struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, - { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, + { .name = "tx", .dma_req = 29 }, + { .name = "rx", .dma_req = 30 }, { .dma_req = -1 } }; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 69337af748c..28bbd56346a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -35,29 +35,6 @@ */ /* - * 'emif_fw' class - * instance(s): emif_fw - */ -static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = { - .name = "emif_fw", -}; - -/* emif_fw */ -static struct omap_hwmod am33xx_emif_fw_hwmod = { - .name = "emif_fw", - .class = &am33xx_emif_fw_hwmod_class, - .clkdm_name = "l4fw_clkdm", - .main_clk = "l4fw_gclk", - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'emif' class * instance(s): emif */ @@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = { .sysc = &am33xx_emif_sysc, }; -static struct omap_hwmod_irq_info am33xx_emif_irqs[] = { - { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - /* emif */ static struct omap_hwmod am33xx_emif_hwmod = { .name = "emif", .class = &am33xx_emif_hwmod_class, .clkdm_name = "l3_clkdm", .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = am33xx_emif_irqs, .main_clk = "dpll_ddr_m2_div2_ck", .prcm = { .omap4 = { @@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = { .name = "l3", }; -/* l3_main (l3_fast) */ -static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = { - { .name = "l3debug", .irq = 9 + OMAP_INTC_START, }, - { .name = "l3appint", .irq = 10 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_l3_main_hwmod = { .name = "l3_main", .class = &am33xx_l3_hwmod_class, .clkdm_name = "l3_clkdm", .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = am33xx_l3_main_irqs, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = { }, }; -/* l4_fw */ -static struct omap_hwmod am33xx_l4_fw_hwmod = { - .name = "l4_fw", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l4fw_clkdm", - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'mpu' class */ @@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = { .name = "mpu", }; -/* mpu */ -static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = { - { .name = "emuint", .irq = 0 + OMAP_INTC_START, }, - { .name = "commtx", .irq = 1 + OMAP_INTC_START, }, - { .name = "commrx", .irq = 2 + OMAP_INTC_START, }, - { .name = "bench", .irq = 3 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_mpu_hwmod = { .name = "mpu", .class = &am33xx_mpu_hwmod_class, .clkdm_name = "mpu_clkdm", .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = am33xx_mpu_irqs, .main_clk = "dpll_mpu_m2_ck", .prcm = { .omap4 = { @@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, }; -static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = { - { .name = "txev", .irq = 78 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - /* wkup_m3 */ static struct omap_hwmod am33xx_wkup_m3_hwmod = { .name = "wkup_m3", @@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = { .clkdm_name = "l4_wkup_aon_clkdm", /* Keep hardreset asserted */ .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, - .mpu_irqs = am33xx_wkup_m3_irqs, .main_clk = "dpll_core_m4_div2_ck", .prcm = { .omap4 = { @@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { { .name = "pruss", .rst_shift = 1 }, }; -static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = { - { .name = "evtout0", .irq = 20 + OMAP_INTC_START, }, - { .name = "evtout1", .irq = 21 + OMAP_INTC_START, }, - { .name = "evtout2", .irq = 22 + OMAP_INTC_START, }, - { .name = "evtout3", .irq = 23 + OMAP_INTC_START, }, - { .name = "evtout4", .irq = 24 + OMAP_INTC_START, }, - { .name = "evtout5", .irq = 25 + OMAP_INTC_START, }, - { .name = "evtout6", .irq = 26 + OMAP_INTC_START, }, - { .name = "evtout7", .irq = 27 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - /* pru-icss */ /* Pseudo hwmod for reset control purpose only */ static struct omap_hwmod am33xx_pruss_hwmod = { .name = "pruss", .class = &am33xx_pruss_hwmod_class, .clkdm_name = "pruss_ocp_clkdm", - .mpu_irqs = am33xx_pruss_irqs, .main_clk = "pruss_ocp_gclk", .prcm = { .omap4 = { @@ -329,24 +249,19 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = { }; static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { - { .name = "gfx", .rst_shift = 0 }, -}; - -static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { - { .name = "gfxint", .irq = 37 + OMAP_INTC_START, }, - { .irq = -1 }, + { .name = "gfx", .rst_shift = 0, .st_shift = 0}, }; static struct omap_hwmod am33xx_gfx_hwmod = { .name = "gfx", .class = &am33xx_gfx_hwmod_class, .clkdm_name = "gfx_l3_clkdm", - .mpu_irqs = am33xx_gfx_irqs, .main_clk = "gfx_fck_div_ck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, + .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, @@ -387,16 +302,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { .sysc = &am33xx_adc_tsc_sysc, }; -static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = { - { .irq = 16 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_adc_tsc_hwmod = { .name = "adc_tsc", .class = &am33xx_adc_tsc_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = am33xx_adc_tsc_irqs, .main_clk = "adc_tsc_fck", .prcm = { .omap4 = { @@ -515,23 +424,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = { .sysc = &am33xx_aes0_sysc, }; -static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { - { .irq = 103 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = { - { .name = "tx", .dma_req = 6, }, - { .name = "rx", .dma_req = 5, }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_aes0_hwmod = { .name = "aes", .class = &am33xx_aes0_hwmod_class, .clkdm_name = "l3_clkdm", - .mpu_irqs = am33xx_aes0_irqs, - .sdma_reqs = am33xx_aes0_edma_reqs, .main_clk = "aes0_fck", .prcm = { .omap4 = { @@ -554,22 +450,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = { .sysc = &am33xx_sha0_sysc, }; -static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { - { .irq = 109 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = { - { .name = "rx", .dma_req = 36, }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_sha0_hwmod = { .name = "sham", .class = &am33xx_sha0_hwmod_class, .clkdm_name = "l3_clkdm", - .mpu_irqs = am33xx_sha0_irqs, - .sdma_reqs = am33xx_sha0_edma_reqs, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -604,16 +488,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { }; /* smartreflex0 */ -static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = { - { .irq = 120 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_smartreflex0_hwmod = { .name = "smartreflex0", .class = &am33xx_smartreflex_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = am33xx_smartreflex0_irqs, .main_clk = "smartreflex0_fck", .prcm = { .omap4 = { @@ -624,16 +502,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = { }; /* smartreflex1 */ -static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = { - { .irq = 121 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_smartreflex1_hwmod = { .name = "smartreflex1", .class = &am33xx_smartreflex_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = am33xx_smartreflex1_irqs, .main_clk = "smartreflex1_fck", .prcm = { .omap4 = { @@ -650,17 +522,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = { .name = "control", }; -static struct omap_hwmod_irq_info am33xx_control_irqs[] = { - { .irq = 8 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_control_hwmod = { .name = "control", .class = &am33xx_control_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = am33xx_control_irqs, .main_clk = "dpll_core_m4_div2_ck", .prcm = { .omap4 = { @@ -690,20 +556,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { .sysc = &am33xx_cpgmac_sysc, }; -static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = { - { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, }, - { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, }, - { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, }, - { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_cpgmac0_hwmod = { .name = "cpgmac0", .class = &am33xx_cpgmac0_hwmod_class, .clkdm_name = "cpsw_125mhz_clkdm", .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), - .mpu_irqs = am33xx_cpgmac0_irqs, .main_clk = "cpsw_125mhz_gclk", .prcm = { .omap4 = { @@ -735,17 +592,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = { }; /* dcan0 */ -static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = { - { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, }, - { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_dcan0_hwmod = { .name = "d_can0", .class = &am33xx_dcan_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_dcan0_irqs, .main_clk = "dcan0_fck", .prcm = { .omap4 = { @@ -756,16 +606,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = { }; /* dcan1 */ -static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = { - { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, }, - { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, }, - { .irq = -1 }, -}; static struct omap_hwmod am33xx_dcan1_hwmod = { .name = "d_can1", .class = &am33xx_dcan_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_dcan1_irqs, .main_clk = "dcan1_fck", .prcm = { .omap4 = { @@ -792,16 +636,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = { .sysc = &am33xx_elm_sysc, }; -static struct omap_hwmod_irq_info am33xx_elm_irqs[] = { - { .irq = 4 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_elm_hwmod = { .name = "elm", .class = &am33xx_elm_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_elm_irqs, .main_clk = "l4ls_gclk", .prcm = { .omap4 = { @@ -854,45 +692,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = { }; /* ecap0 */ -static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { - { .irq = 31 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_ecap0_hwmod = { .name = "ecap0", .class = &am33xx_ecap_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_ecap0_irqs, .main_clk = "l4ls_gclk", }; /* eqep0 */ -static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = { - { .irq = 79 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_eqep0_hwmod = { .name = "eqep0", .class = &am33xx_eqep_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_eqep0_irqs, .main_clk = "l4ls_gclk", }; /* ehrpwm0 */ -static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { - { .name = "int", .irq = 86 + OMAP_INTC_START, }, - { .name = "tzint", .irq = 58 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_ehrpwm0_hwmod = { .name = "ehrpwm0", .class = &am33xx_ehrpwm_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_ehrpwm0_irqs, .main_clk = "l4ls_gclk", }; @@ -911,45 +730,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = { }; /* ecap1 */ -static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = { - { .irq = 47 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_ecap1_hwmod = { .name = "ecap1", .class = &am33xx_ecap_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_ecap1_irqs, .main_clk = "l4ls_gclk", }; /* eqep1 */ -static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = { - { .irq = 88 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_eqep1_hwmod = { .name = "eqep1", .class = &am33xx_eqep_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_eqep1_irqs, .main_clk = "l4ls_gclk", }; /* ehrpwm1 */ -static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { - { .name = "int", .irq = 87 + OMAP_INTC_START, }, - { .name = "tzint", .irq = 59 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_ehrpwm1_hwmod = { .name = "ehrpwm1", .class = &am33xx_ehrpwm_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_ehrpwm1_irqs, .main_clk = "l4ls_gclk", }; @@ -968,45 +768,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = { }; /* ecap2 */ -static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = { - { .irq = 61 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_ecap2_hwmod = { .name = "ecap2", .class = &am33xx_ecap_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_ecap2_irqs, .main_clk = "l4ls_gclk", }; /* eqep2 */ -static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = { - { .irq = 89 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_eqep2_hwmod = { .name = "eqep2", .class = &am33xx_eqep_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_eqep2_irqs, .main_clk = "l4ls_gclk", }; /* ehrpwm2 */ -static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { - { .name = "int", .irq = 39 + OMAP_INTC_START, }, - { .name = "tzint", .irq = 60 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_ehrpwm2_hwmod = { .name = "ehrpwm2", .class = &am33xx_ehrpwm_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_ehrpwm2_irqs, .main_clk = "l4ls_gclk", }; @@ -1041,17 +822,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { { .role = "dbclk", .clk = "gpio0_dbclk" }, }; -static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = { - { .irq = 96 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_gpio0_hwmod = { .name = "gpio1", .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = am33xx_gpio0_irqs, .main_clk = "dpll_core_m4_div2_ck", .prcm = { .omap4 = { @@ -1065,11 +840,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = { }; /* gpio1 */ -static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = { - { .irq = 98 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; @@ -1079,7 +849,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = am33xx_gpio1_irqs, .main_clk = "l4ls_gclk", .prcm = { .omap4 = { @@ -1093,11 +862,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = { }; /* gpio2 */ -static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = { - { .irq = 32 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; @@ -1107,7 +871,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = { .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = am33xx_gpio2_irqs, .main_clk = "l4ls_gclk", .prcm = { .omap4 = { @@ -1121,11 +884,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = { }; /* gpio3 */ -static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = { - { .irq = 62 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; @@ -1135,7 +893,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = { .class = &am33xx_gpio_hwmod_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = am33xx_gpio3_irqs, .main_clk = "l4ls_gclk", .prcm = { .omap4 = { @@ -1164,17 +921,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { .sysc = &gpmc_sysc, }; -static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = { - { .irq = 100 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_gpmc_hwmod = { .name = "gpmc", .class = &am33xx_gpmc_hwmod_class, .clkdm_name = "l3s_clkdm", .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), - .mpu_irqs = am33xx_gpmc_irqs, .main_clk = "l3s_gclk", .prcm = { .omap4 = { @@ -1208,23 +959,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* i2c1 */ -static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { - { .irq = 70 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info i2c1_edma_reqs[] = { - { .name = "tx", .dma_req = 0, }, - { .name = "rx", .dma_req = 0, }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_i2c1_hwmod = { .name = "i2c1", .class = &i2c_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = i2c1_mpu_irqs, - .sdma_reqs = i2c1_edma_reqs, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .main_clk = "dpll_per_m2_div4_wkupdm_ck", .prcm = { @@ -1237,23 +975,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = { }; /* i2c1 */ -static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { - { .irq = 71 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info i2c2_edma_reqs[] = { - { .name = "tx", .dma_req = 0, }, - { .name = "rx", .dma_req = 0, }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_i2c2_hwmod = { .name = "i2c2", .class = &i2c_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = i2c2_mpu_irqs, - .sdma_reqs = i2c2_edma_reqs, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { @@ -1266,23 +991,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = { }; /* i2c3 */ -static struct omap_hwmod_dma_info i2c3_edma_reqs[] = { - { .name = "tx", .dma_req = 0, }, - { .name = "rx", .dma_req = 0, }, - { .dma_req = -1 } -}; - -static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { - { .irq = 30 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_i2c3_hwmod = { .name = "i2c3", .class = &i2c_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = i2c3_mpu_irqs, - .sdma_reqs = i2c3_edma_reqs, .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { @@ -1309,16 +1021,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { .sysc = &lcdc_sysc, }; -static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = { - { .irq = 36 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_lcdc_hwmod = { .name = "lcdc", .class = &am33xx_lcdc_hwmod_class, .clkdm_name = "lcdc_clkdm", - .mpu_irqs = am33xx_lcdc_irqs, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .main_clk = "lcd_gclk", .prcm = { @@ -1348,16 +1054,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { .sysc = &am33xx_mailbox_sysc, }; -static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = { - { .irq = 77 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_mailbox_hwmod = { .name = "mailbox", .class = &am33xx_mailbox_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_mailbox_irqs, .main_clk = "l4ls_gclk", .prcm = { .omap4 = { @@ -1384,24 +1084,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { }; /* mcasp0 */ -static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = { - { .name = "ax", .irq = 80 + OMAP_INTC_START, }, - { .name = "ar", .irq = 81 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = { - { .name = "tx", .dma_req = 8, }, - { .name = "rx", .dma_req = 9, }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_mcasp0_hwmod = { .name = "mcasp0", .class = &am33xx_mcasp_hwmod_class, .clkdm_name = "l3s_clkdm", - .mpu_irqs = am33xx_mcasp0_irqs, - .sdma_reqs = am33xx_mcasp0_edma_reqs, .main_clk = "mcasp0_fck", .prcm = { .omap4 = { @@ -1412,24 +1098,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = { }; /* mcasp1 */ -static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = { - { .name = "ax", .irq = 82 + OMAP_INTC_START, }, - { .name = "ar", .irq = 83 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = { - { .name = "tx", .dma_req = 10, }, - { .name = "rx", .dma_req = 11, }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_mcasp1_hwmod = { .name = "mcasp1", .class = &am33xx_mcasp_hwmod_class, .clkdm_name = "l3s_clkdm", - .mpu_irqs = am33xx_mcasp1_irqs, - .sdma_reqs = am33xx_mcasp1_edma_reqs, .main_clk = "mcasp1_fck", .prcm = { .omap4 = { @@ -1457,17 +1129,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = { }; /* mmc0 */ -static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = { - { .irq = 64 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = { - { .name = "tx", .dma_req = 24, }, - { .name = "rx", .dma_req = 25, }, - { .dma_req = -1 } -}; - static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -1476,8 +1137,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = { .name = "mmc1", .class = &am33xx_mmc_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_mmc0_irqs, - .sdma_reqs = am33xx_mmc0_edma_reqs, .main_clk = "mmc_clk", .prcm = { .omap4 = { @@ -1489,17 +1148,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = { }; /* mmc1 */ -static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = { - { .irq = 28 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = { - { .name = "tx", .dma_req = 2, }, - { .name = "rx", .dma_req = 3, }, - { .dma_req = -1 } -}; - static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -1508,8 +1156,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = { .name = "mmc2", .class = &am33xx_mmc_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_mmc1_irqs, - .sdma_reqs = am33xx_mmc1_edma_reqs, .main_clk = "mmc_clk", .prcm = { .omap4 = { @@ -1521,17 +1167,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = { }; /* mmc2 */ -static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = { - { .irq = 29 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = { - { .name = "tx", .dma_req = 64, }, - { .name = "rx", .dma_req = 65, }, - { .dma_req = -1 } -}; - static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -1539,8 +1174,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = { .name = "mmc3", .class = &am33xx_mmc_hwmod_class, .clkdm_name = "l3s_clkdm", - .mpu_irqs = am33xx_mmc2_irqs, - .sdma_reqs = am33xx_mmc2_edma_reqs, .main_clk = "mmc_clk", .prcm = { .omap4 = { @@ -1569,17 +1202,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = { .sysc = &am33xx_rtc_sysc, }; -static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = { - { .name = "rtcint", .irq = 75 + OMAP_INTC_START, }, - { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_rtc_hwmod = { .name = "rtc", .class = &am33xx_rtc_hwmod_class, .clkdm_name = "l4_rtc_clkdm", - .mpu_irqs = am33xx_rtc_irqs, .main_clk = "clk_32768_ck", .prcm = { .omap4 = { @@ -1608,19 +1234,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = { }; /* spi0 */ -static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = { - { .irq = 65 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = { - { .name = "rx0", .dma_req = 17 }, - { .name = "tx0", .dma_req = 16 }, - { .name = "rx1", .dma_req = 19 }, - { .name = "tx1", .dma_req = 18 }, - { .dma_req = -1 } -}; - static struct omap2_mcspi_dev_attr mcspi_attrib = { .num_chipselect = 2, }; @@ -1628,8 +1241,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = { .name = "spi0", .class = &am33xx_spi_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_spi0_irqs, - .sdma_reqs = am33xx_mcspi0_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1641,25 +1252,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = { }; /* spi1 */ -static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = { - { .irq = 125 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - -static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = { - { .name = "rx0", .dma_req = 43 }, - { .name = "tx0", .dma_req = 42 }, - { .name = "rx1", .dma_req = 45 }, - { .name = "tx1", .dma_req = 44 }, - { .dma_req = -1 } -}; - static struct omap_hwmod am33xx_spi1_hwmod = { .name = "spi1", .class = &am33xx_spi_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_spi1_irqs, - .sdma_reqs = am33xx_mcspi1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1725,16 +1321,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { .sysc = &am33xx_timer1ms_sysc, }; -static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = { - { .irq = 67 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer1_hwmod = { .name = "timer1", .class = &am33xx_timer1ms_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = am33xx_timer1_irqs, .main_clk = "timer1_fck", .prcm = { .omap4 = { @@ -1744,16 +1334,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = { - { .irq = 68 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer2_hwmod = { .name = "timer2", .class = &am33xx_timer_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_timer2_irqs, .main_clk = "timer2_fck", .prcm = { .omap4 = { @@ -1763,16 +1347,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = { - { .irq = 69 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer3_hwmod = { .name = "timer3", .class = &am33xx_timer_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_timer3_irqs, .main_clk = "timer3_fck", .prcm = { .omap4 = { @@ -1782,16 +1360,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = { - { .irq = 92 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer4_hwmod = { .name = "timer4", .class = &am33xx_timer_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_timer4_irqs, .main_clk = "timer4_fck", .prcm = { .omap4 = { @@ -1801,16 +1373,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = { - { .irq = 93 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer5_hwmod = { .name = "timer5", .class = &am33xx_timer_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_timer5_irqs, .main_clk = "timer5_fck", .prcm = { .omap4 = { @@ -1820,16 +1386,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = { - { .irq = 94 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer6_hwmod = { .name = "timer6", .class = &am33xx_timer_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_timer6_irqs, .main_clk = "timer6_fck", .prcm = { .omap4 = { @@ -1839,16 +1399,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = { - { .irq = 95 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_timer7_hwmod = { .name = "timer7", .class = &am33xx_timer_hwmod_class, .clkdm_name = "l4ls_clkdm", - .mpu_irqs = am33xx_timer7_irqs, .main_clk = "timer7_fck", .prcm = { .omap4 = { @@ -1863,18 +1417,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { .name = "tpcc", }; -static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = { - { .name = "edma0", .irq = 12 + OMAP_INTC_START, }, - { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, }, - { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_tpcc_hwmod = { .name = "tpcc", .class = &am33xx_tpcc_hwmod_class, .clkdm_name = "l3_clkdm", - .mpu_irqs = am33xx_tpcc_irqs, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -1900,16 +1446,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = { }; /* tptc0 */ -static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = { - { .irq = 112 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_tptc0_hwmod = { .name = "tptc0", .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", - .mpu_irqs = am33xx_tptc0_irqs, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .main_clk = "l3_gclk", .prcm = { @@ -1921,16 +1461,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = { }; /* tptc1 */ -static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = { - { .irq = 113 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_tptc1_hwmod = { .name = "tptc1", .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", - .mpu_irqs = am33xx_tptc1_irqs, .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .main_clk = "l3_gclk", .prcm = { @@ -1942,16 +1476,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = { }; /* tptc2 */ -static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = { - { .irq = 114 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_tptc2_hwmod = { .name = "tptc2", .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", - .mpu_irqs = am33xx_tptc2_irqs, .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), .main_clk = "l3_gclk", .prcm = { @@ -1980,24 +1508,11 @@ static struct omap_hwmod_class uart_class = { }; /* uart1 */ -static struct omap_hwmod_dma_info uart1_edma_reqs[] = { - { .name = "tx", .dma_req = 26, }, - { .name = "rx", .dma_req = 27, }, - { .dma_req = -1 } -}; - -static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = { - { .irq = 72 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_uart1_hwmod = { .name = "uart1", .class = &uart_class, .clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = am33xx_uart1_irqs, - .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_wkupdm_ck", .prcm = { .omap4 = { @@ -2007,25 +1522,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = { }, }; -/* uart2 */ -static struct omap_hwmod_dma_info uart2_edma_reqs[] = { - { .name = "tx", .dma_req = 28, }, - { .name = "rx", .dma_req = 29, }, - { .dma_req = -1 } -}; - -static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { - { .irq = 73 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_uart2_hwmod = { .name = "uart2", .class = &uart_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = am33xx_uart2_irqs, - .sdma_reqs = uart2_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -2036,24 +1537,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = { }; /* uart3 */ -static struct omap_hwmod_dma_info uart3_edma_reqs[] = { - { .name = "tx", .dma_req = 30, }, - { .name = "rx", .dma_req = 31, }, - { .dma_req = -1 } -}; - -static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = { - { .irq = 74 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_uart3_hwmod = { .name = "uart3", .class = &uart_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = am33xx_uart3_irqs, - .sdma_reqs = uart3_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -2063,18 +1551,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = { - { .irq = 44 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_uart4_hwmod = { .name = "uart4", .class = &uart_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = am33xx_uart4_irqs, - .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -2084,18 +1565,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = { - { .irq = 45 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_uart5_hwmod = { .name = "uart5", .class = &uart_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = am33xx_uart5_irqs, - .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -2105,18 +1579,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = { }, }; -static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = { - { .irq = 46 + OMAP_INTC_START, }, - { .irq = -1 }, -}; - static struct omap_hwmod am33xx_uart6_hwmod = { .name = "uart6", .class = &uart_class, .clkdm_name = "l4ls_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = am33xx_uart6_irqs, - .sdma_reqs = uart1_edma_reqs, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -2180,18 +1647,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = { .sysc = &am33xx_usbhsotg_sysc, }; -static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = { - { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, }, - { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, }, - { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, }, - { .irq = -1, }, -}; - static struct omap_hwmod am33xx_usbss_hwmod = { .name = "usb_otg_hs", .class = &am33xx_usbotg_class, .clkdm_name = "l3s_clkdm", - .mpu_irqs = am33xx_usbss_mpu_irqs, .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .main_clk = "usbotg_fck", .prcm = { @@ -2207,14 +1666,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = { * Interfaces */ -/* l4 fw -> emif fw */ -static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = { - .master = &am33xx_l4_fw_hwmod, - .slave = &am33xx_emif_fw_hwmod, - .clk = "l4fw_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { { .pa_start = 0x4c000000, @@ -2272,14 +1723,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3 s -> l4 fw */ -static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l4_fw_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3 main -> l3 instr */ static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { .master = &am33xx_l3_main_hwmod, @@ -2329,261 +1772,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { }; /* l4 wkup -> wkup m3 */ -static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = { - { - .name = "umem", - .pa_start = 0x44d00000, - .pa_end = 0x44d00000 + SZ_16K - 1, - .flags = ADDR_TYPE_RT - }, - { - .name = "dmem", - .pa_start = 0x44d80000, - .pa_end = 0x44d80000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_wkup_m3_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_wkup_m3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4 hs -> pru-icss */ -static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = { - { - .pa_start = 0x4a300000, - .pa_end = 0x4a300000 + SZ_512K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { .master = &am33xx_l4_hs_hwmod, .slave = &am33xx_pruss_hwmod, .clk = "dpll_core_m4_ck", - .addr = am33xx_pruss_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l3 main -> gfx */ -static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = { - { - .pa_start = 0x56000000, - .pa_end = 0x56000000 + SZ_16M - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_gfx_hwmod, .clk = "dpll_core_m4_ck", - .addr = am33xx_gfx_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4 wkup -> smartreflex0 */ -static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = { - { - .pa_start = 0x44e37000, - .pa_end = 0x44e37000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_smartreflex0_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_smartreflex0_addrs, .user = OCP_USER_MPU, }; /* l4 wkup -> smartreflex1 */ -static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = { - { - .pa_start = 0x44e39000, - .pa_end = 0x44e39000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_smartreflex1_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_smartreflex1_addrs, .user = OCP_USER_MPU, }; /* l4 wkup -> control */ -static struct omap_hwmod_addr_space am33xx_control_addrs[] = { - { - .pa_start = 0x44e10000, - .pa_end = 0x44e10000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_control_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_control_addrs, .user = OCP_USER_MPU, }; /* l4 wkup -> rtc */ -static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = { - { - .pa_start = 0x44e3e000, - .pa_end = 0x44e3e000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_rtc_hwmod, .clk = "clkdiv32k_ick", - .addr = am33xx_rtc_addrs, .user = OCP_USER_MPU, }; /* l4 per/ls -> DCAN0 */ -static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = { - { - .pa_start = 0x481CC000, - .pa_end = 0x481CC000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_dcan0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_dcan0_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4 per/ls -> DCAN1 */ -static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = { - { - .pa_start = 0x481D0000, - .pa_end = 0x481D0000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_dcan1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_dcan1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4 per/ls -> GPIO2 */ -static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = { - { - .pa_start = 0x4804C000, - .pa_end = 0x4804C000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_gpio1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_gpio1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4 per/ls -> gpio3 */ -static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = { - { - .pa_start = 0x481AC000, - .pa_end = 0x481AC000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_gpio2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_gpio2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l4 per/ls -> gpio4 */ -static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = { - { - .pa_start = 0x481AE000, - .pa_end = 0x481AE000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_gpio3_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_gpio3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* L4 WKUP -> I2C1 */ -static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = { - { - .pa_start = 0x44E0B000, - .pa_end = 0x44E0B000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_i2c1_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_i2c1_addr_space, .user = OCP_USER_MPU, }; /* L4 WKUP -> GPIO1 */ -static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = { - { - .pa_start = 0x44E07000, - .pa_end = 0x44E07000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_gpio0_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_gpio0_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -2605,41 +1901,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = { - /* cpsw ss */ - { - .pa_start = 0x4a100000, - .pa_end = 0x4a100000 + SZ_2K - 1, - }, - /* cpsw wr */ - { - .pa_start = 0x4a101200, - .pa_end = 0x4a101200 + SZ_256 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { .master = &am33xx_l4_hs_hwmod, .slave = &am33xx_cpgmac0_hwmod, .clk = "cpsw_125mhz_gclk", - .addr = am33xx_cpgmac0_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = { - { - .pa_start = 0x4A101000, - .pa_end = 0x4A101000 + SZ_256 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { .master = &am33xx_cpgmac0_hwmod, .slave = &am33xx_mdio_hwmod, - .addr = am33xx_mdio_addr_space, .user = OCP_USER_MPU, }; @@ -2677,51 +1948,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { - { - .pa_start = 0x48300100, - .pa_end = 0x48300100 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { .master = &am33xx_epwmss0_hwmod, .slave = &am33xx_ecap0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_ecap0_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = { - { - .pa_start = 0x48300180, - .pa_end = 0x48300180 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { .master = &am33xx_epwmss0_hwmod, .slave = &am33xx_eqep0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_eqep0_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = { - { - .pa_start = 0x48300200, - .pa_end = 0x48300200 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { .master = &am33xx_epwmss0_hwmod, .slave = &am33xx_ehrpwm0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_ehrpwm0_addr_space, .user = OCP_USER_MPU, }; @@ -2743,51 +1987,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { - { - .pa_start = 0x48302100, - .pa_end = 0x48302100 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { .master = &am33xx_epwmss1_hwmod, .slave = &am33xx_ecap1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_ecap1_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = { - { - .pa_start = 0x48302180, - .pa_end = 0x48302180 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { .master = &am33xx_epwmss1_hwmod, .slave = &am33xx_eqep1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_eqep1_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = { - { - .pa_start = 0x48302200, - .pa_end = 0x48302200 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { .master = &am33xx_epwmss1_hwmod, .slave = &am33xx_ehrpwm1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_ehrpwm1_addr_space, .user = OCP_USER_MPU, }; @@ -2808,51 +2025,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { - { - .pa_start = 0x48304100, - .pa_end = 0x48304100 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { .master = &am33xx_epwmss2_hwmod, .slave = &am33xx_ecap2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_ecap2_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = { - { - .pa_start = 0x48304180, - .pa_end = 0x48304180 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { .master = &am33xx_epwmss2_hwmod, .slave = &am33xx_eqep2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_eqep2_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = { - { - .pa_start = 0x48304200, - .pa_end = 0x48304200 + SZ_128 - 1, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { .master = &am33xx_epwmss2_hwmod, .slave = &am33xx_ehrpwm2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_ehrpwm2_addr_space, .user = OCP_USER_MPU, }; @@ -2875,37 +2065,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { }; /* i2c2 */ -static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = { - { - .pa_start = 0x4802A000, - .pa_end = 0x4802A000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_i2c2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_i2c2_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = { - { - .pa_start = 0x4819C000, - .pa_end = 0x4819C000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_i2c3_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_i2c3_addr_space, .user = OCP_USER_MPU, }; @@ -2945,20 +2115,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { }; /* l4 ls -> spinlock */ -static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = { - { - .pa_start = 0x480Ca000, - .pa_end = 0x480Ca000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_spinlock_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_spinlock_addrs, .user = OCP_USER_MPU, }; @@ -2980,24 +2140,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { .user = OCP_USER_MPU, }; -/* l3 s -> mcasp0 data */ -static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = { - { - .pa_start = 0x46000000, - .pa_end = 0x46000000 + SZ_4M - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_mcasp0_hwmod, - .clk = "l3s_gclk", - .addr = am33xx_mcasp0_data_addr_space, - .user = OCP_USER_SDMA, -}; - /* l4 ls -> mcasp1 */ static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { { @@ -3016,24 +2158,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { .user = OCP_USER_MPU, }; -/* l3 s -> mcasp1 data */ -static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = { - { - .pa_start = 0x46400000, - .pa_end = 0x46400000 + SZ_4M - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_mcasp1_hwmod, - .clk = "l3s_gclk", - .addr = am33xx_mcasp1_data_addr_space, - .user = OCP_USER_SDMA, -}; - /* l4 ls -> mmc0 */ static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { { @@ -3089,182 +2213,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { }; /* l4 ls -> mcspi0 */ -static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = { - { - .pa_start = 0x48030000, - .pa_end = 0x48030000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_spi0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mcspi0_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> mcspi1 */ -static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = { - { - .pa_start = 0x481A0000, - .pa_end = 0x481A0000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_spi1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mcspi1_addr_space, .user = OCP_USER_MPU, }; /* l4 wkup -> timer1 */ -static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = { - { - .pa_start = 0x44E31000, - .pa_end = 0x44E31000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_timer1_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_timer1_addr_space, .user = OCP_USER_MPU, }; /* l4 per -> timer2 */ -static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = { - { - .pa_start = 0x48040000, - .pa_end = 0x48040000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_timer2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_timer2_addr_space, .user = OCP_USER_MPU, }; /* l4 per -> timer3 */ -static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = { - { - .pa_start = 0x48042000, - .pa_end = 0x48042000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_timer3_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_timer3_addr_space, .user = OCP_USER_MPU, }; /* l4 per -> timer4 */ -static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = { - { - .pa_start = 0x48044000, - .pa_end = 0x48044000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_timer4_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_timer4_addr_space, .user = OCP_USER_MPU, }; /* l4 per -> timer5 */ -static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = { - { - .pa_start = 0x48046000, - .pa_end = 0x48046000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_timer5_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_timer5_addr_space, .user = OCP_USER_MPU, }; /* l4 per -> timer6 */ -static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = { - { - .pa_start = 0x48048000, - .pa_end = 0x48048000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_timer6_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_timer6_addr_space, .user = OCP_USER_MPU, }; /* l4 per -> timer7 */ -static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = { - { - .pa_start = 0x4804A000, - .pa_end = 0x4804A000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_timer7_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_timer7_addr_space, .user = OCP_USER_MPU, }; /* l3 main -> tpcc */ -static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = { - { - .pa_start = 0x49000000, - .pa_end = 0x49000000 + SZ_32K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_tpcc_hwmod, .clk = "l3_gclk", - .addr = am33xx_tpcc_addr_space, .user = OCP_USER_MPU, }; @@ -3323,160 +2347,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { }; /* l4 wkup -> uart1 */ -static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = { - { - .pa_start = 0x44E09000, - .pa_end = 0x44E09000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_uart1_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_uart1_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> uart2 */ -static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = { - { - .pa_start = 0x48022000, - .pa_end = 0x48022000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_uart2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_uart2_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> uart3 */ -static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = { - { - .pa_start = 0x48024000, - .pa_end = 0x48024000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_uart3_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_uart3_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> uart4 */ -static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = { - { - .pa_start = 0x481A6000, - .pa_end = 0x481A6000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_uart4_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_uart4_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> uart5 */ -static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = { - { - .pa_start = 0x481A8000, - .pa_end = 0x481A8000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_uart5_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_uart5_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> uart6 */ -static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = { - { - .pa_start = 0x481aa000, - .pa_end = 0x481aa000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_uart6_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_uart6_addr_space, .user = OCP_USER_MPU, }; /* l4 wkup -> wd_timer1 */ -static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = { - { - .pa_start = 0x44e35000, - .pa_end = 0x44e35000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_wd_timer1_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_wd_timer1_addrs, .user = OCP_USER_MPU, }; /* usbss */ /* l3 s -> USBSS interface */ -static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = { - { - .name = "usbss", - .pa_start = 0x47400000, - .pa_end = 0x47400000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { - .name = "musb0", - .pa_start = 0x47401000, - .pa_end = 0x47401000 + SZ_2K - 1, - .flags = ADDR_TYPE_RT - }, - { - .name = "musb1", - .pa_start = 0x47401800, - .pa_end = 0x47401800 + SZ_2K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { .master = &am33xx_l3_s_hwmod, .slave = &am33xx_usbss_hwmod, .clk = "l3s_gclk", - .addr = am33xx_usbss_addr_space, .user = OCP_USER_MPU, .flags = OCPIF_SWSUP_IDLE, }; @@ -3525,13 +2456,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { }; static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_l4_fw__emif_fw, &am33xx_l3_main__emif, &am33xx_mpu__l3_main, &am33xx_mpu__prcm, &am33xx_l3_s__l4_ls, &am33xx_l3_s__l4_wkup, - &am33xx_l3_s__l4_fw, &am33xx_l3_main__l4_hs, &am33xx_l3_main__l3_s, &am33xx_l3_main__l3_instr, @@ -3561,9 +2490,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_per__i2c3, &am33xx_l4_per__mailbox, &am33xx_l4_ls__mcasp0, - &am33xx_l3_s__mcasp0_data, &am33xx_l4_ls__mcasp1, - &am33xx_l3_s__mcasp1_data, &am33xx_l4_ls__mmc0, &am33xx_l4_ls__mmc1, &am33xx_l3_s__mmc2, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 31c7126eb3b..fa991541144 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -35,7 +35,6 @@ #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" -#include "dma.h" #include "i2c.h" #include "mmc.h" #include "wd_timer.h" @@ -548,8 +547,8 @@ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { }; static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, + { .name = "rx", .dma_req = 82, }, + { .name = "tx", .dma_req = 81, }, { .dma_req = -1 } }; @@ -577,8 +576,8 @@ static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { }; static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { - { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, + { .name = "rx", .dma_req = 55, }, + { .name = "tx", .dma_req = 54, }, { .dma_req = -1 } }; @@ -857,8 +856,8 @@ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { }; static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, - { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, + { .name = "tx", .dma_req = 25 }, + { .name = "rx", .dma_req = 26 }, { .dma_req = -1 } }; @@ -3581,7 +3580,7 @@ static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { }; static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { - { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, }, + { .name = "rx", .dma_req = 69, }, { .dma_req = -1 } }; @@ -3642,8 +3641,8 @@ static struct omap_hwmod_class omap3xxx_aes_class = { }; static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { - { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, }, - { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, }, + { .name = "tx", .dma_req = 65, }, + { .name = "rx", .dma_req = 66, }, { .dma_req = -1 } }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 848b6dc6759..d04b5e60fdb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -12,6 +12,8 @@ * with the public linux-omap@vger.kernel.org mailing list and the * authors above to ensure that the autogeneration scripts are kept * up-to-date with the file contents. + * Note that this file is currently not in sync with autogeneration scripts. + * The above note to be removed, once it is synced up. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -21,7 +23,6 @@ #include <linux/io.h> #include <linux/platform_data/gpio-omap.h> #include <linux/power/smartreflex.h> -#include <linux/platform_data/omap_ocp2scp.h> #include <linux/i2c-omap.h> #include <linux/omap-dma.h> @@ -52,27 +53,6 @@ */ /* - * 'c2c_target_fw' class - * instance(s): c2c_target_fw - */ -static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { - .name = "c2c_target_fw", -}; - -/* c2c_target_fw */ -static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { - .name = "c2c_target_fw", - .class = &omap44xx_c2c_target_fw_hwmod_class, - .clkdm_name = "d2d_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, - }, - }, -}; - -/* * 'dmm' class * instance(s): dmm */ @@ -81,16 +61,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { }; /* dmm */ -static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { - { .irq = 113 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_dmm_hwmod = { .name = "dmm", .class = &omap44xx_dmm_hwmod_class, .clkdm_name = "l3_emif_clkdm", - .mpu_irqs = omap44xx_dmm_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, @@ -100,27 +74,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { }; /* - * 'emif_fw' class - * instance(s): emif_fw - */ -static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { - .name = "emif_fw", -}; - -/* emif_fw */ -static struct omap_hwmod omap44xx_emif_fw_hwmod = { - .name = "emif_fw", - .class = &omap44xx_emif_fw_hwmod_class, - .clkdm_name = "l3_emif_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, - }, - }, -}; - -/* * 'l3' class * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 */ @@ -143,17 +96,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { }; /* l3_main_1 */ -static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { - { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, - { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .name = "l3_main_1", .class = &omap44xx_l3_hwmod_class, .clkdm_name = "l3_1_clkdm", - .mpu_irqs = omap44xx_l3_main_1_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, @@ -326,29 +272,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = { }; /* aess */ -static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { - { .irq = 99 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { - { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, - { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_aess_hwmod = { .name = "aess", .class = &omap44xx_aess_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_aess_irqs, - .sdma_reqs = omap44xx_aess_sdma_reqs, .main_clk = "aess_fclk", .prcm = { .omap4 = { @@ -371,22 +298,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { }; /* c2c */ -static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { - { .irq = 88 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { - { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_c2c_hwmod = { .name = "c2c", .class = &omap44xx_c2c_hwmod_class, .clkdm_name = "d2d_clkdm", - .mpu_irqs = omap44xx_c2c_irqs, - .sdma_reqs = omap44xx_c2c_sdma_reqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, @@ -449,16 +364,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { }; /* ctrl_module_core */ -static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { - { .irq = 8 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { .name = "ctrl_module_core", .class = &omap44xx_ctrl_module_hwmod_class, .clkdm_name = "l4_cfg_clkdm", - .mpu_irqs = omap44xx_ctrl_module_core_irqs, .prcm = { .omap4 = { .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, @@ -601,22 +510,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { }; /* dmic */ -static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { - { .irq = 114 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { - { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_dmic_hwmod = { .name = "dmic", .class = &omap44xx_dmic_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_dmic_irqs, - .sdma_reqs = omap44xx_dmic_sdma_reqs, .main_clk = "func_dmic_abe_gfclk", .prcm = { .omap4 = { @@ -637,11 +534,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { }; /* dsp */ -static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { - { .irq = 28 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { { .name = "dsp", .rst_shift = 0 }, }; @@ -650,7 +542,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .name = "dsp", .class = &omap44xx_dsp_hwmod_class, .clkdm_name = "tesla_clkdm", - .mpu_irqs = omap44xx_dsp_irqs, .rst_lines = omap44xx_dsp_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), .main_clk = "dpll_iva_m4x2_ck", @@ -992,16 +883,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = { }; /* elm */ -static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { - { .irq = 4 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_elm_hwmod = { .name = "elm", .class = &omap44xx_elm_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_elm_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, @@ -1025,17 +910,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = { }; /* emif1 */ -static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { - { .irq = 110 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_emif1_hwmod = { .name = "emif1", .class = &omap44xx_emif_hwmod_class, .clkdm_name = "l3_emif_clkdm", .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_emif1_irqs, .main_clk = "ddrphy_ck", .prcm = { .omap4 = { @@ -1047,17 +926,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = { }; /* emif2 */ -static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { - { .irq = 111 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_emif2_hwmod = { .name = "emif2", .class = &omap44xx_emif_hwmod_class, .clkdm_name = "l3_emif_clkdm", .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_emif2_irqs, .main_clk = "ddrphy_ck", .prcm = { .omap4 = { @@ -1098,16 +971,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { }; /* fdif */ -static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { - { .irq = 69 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_fdif_hwmod = { .name = "fdif", .class = &omap44xx_fdif_hwmod_class, .clkdm_name = "iss_clkdm", - .mpu_irqs = omap44xx_fdif_irqs, .main_clk = "fdif_fck", .prcm = { .omap4 = { @@ -1148,11 +1015,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { }; /* gpio1 */ -static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { - { .irq = 29 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; @@ -1161,7 +1023,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .name = "gpio1", .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = omap44xx_gpio1_irqs, .main_clk = "l4_wkup_clk_mux_ck", .prcm = { .omap4 = { @@ -1176,11 +1037,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { }; /* gpio2 */ -static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { - { .irq = 30 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; @@ -1190,7 +1046,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap44xx_gpio2_irqs, .main_clk = "l4_div_ck", .prcm = { .omap4 = { @@ -1205,11 +1060,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { }; /* gpio3 */ -static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { - { .irq = 31 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; @@ -1219,7 +1069,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap44xx_gpio3_irqs, .main_clk = "l4_div_ck", .prcm = { .omap4 = { @@ -1234,11 +1083,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { }; /* gpio4 */ -static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { - { .irq = 32 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbclk" }, }; @@ -1248,7 +1092,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap44xx_gpio4_irqs, .main_clk = "l4_div_ck", .prcm = { .omap4 = { @@ -1263,11 +1106,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { }; /* gpio5 */ -static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { - { .irq = 33 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { { .role = "dbclk", .clk = "gpio5_dbclk" }, }; @@ -1277,7 +1115,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap44xx_gpio5_irqs, .main_clk = "l4_div_ck", .prcm = { .omap4 = { @@ -1292,11 +1129,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { }; /* gpio6 */ -static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { - { .irq = 34 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbclk" }, }; @@ -1306,7 +1138,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap44xx_gpio6_irqs, .main_clk = "l4_div_ck", .prcm = { .omap4 = { @@ -1341,16 +1172,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { }; /* gpmc */ -static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { - { .irq = 20 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { - { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_gpmc_hwmod = { .name = "gpmc", .class = &omap44xx_gpmc_hwmod_class, @@ -1364,8 +1185,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { * HWMOD_INIT_NO_RESET should be removed ASAP. */ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_gpmc_irqs, - .sdma_reqs = omap44xx_gpmc_sdma_reqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, @@ -1396,16 +1215,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { }; /* gpu */ -static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { - { .irq = 21 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_gpu_hwmod = { .name = "gpu", .class = &omap44xx_gpu_hwmod_class, .clkdm_name = "l3_gfx_clkdm", - .mpu_irqs = omap44xx_gpu_irqs, .main_clk = "sgx_clk_mux", .prcm = { .omap4 = { @@ -1436,17 +1249,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { }; /* hdq1w */ -static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { - { .irq = 58 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_hdq1w_hwmod = { .name = "hdq1w", .class = &omap44xx_hdq1w_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ - .mpu_irqs = omap44xx_hdq1w_irqs, .main_clk = "func_12m_fclk", .prcm = { .omap4 = { @@ -1482,18 +1289,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { }; /* hsi */ -static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { - { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, - { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, - { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_hsi_hwmod = { .name = "hsi", .class = &omap44xx_hsi_hwmod_class, .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_hsi_irqs, .main_clk = "hsi_fck", .prcm = { .omap4 = { @@ -1533,24 +1332,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* i2c1 */ -static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { - { .irq = 56 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { - { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_i2c1_irqs, - .sdma_reqs = omap44xx_i2c1_sdma_reqs, .main_clk = "func_96m_fclk", .prcm = { .omap4 = { @@ -1563,24 +1349,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { }; /* i2c2 */ -static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { - { .irq = 57 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { - { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_i2c2_irqs, - .sdma_reqs = omap44xx_i2c2_sdma_reqs, .main_clk = "func_96m_fclk", .prcm = { .omap4 = { @@ -1593,24 +1366,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { }; /* i2c3 */ -static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { - { .irq = 61 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { - { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_i2c3_irqs, - .sdma_reqs = omap44xx_i2c3_sdma_reqs, .main_clk = "func_96m_fclk", .prcm = { .omap4 = { @@ -1623,24 +1383,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { }; /* i2c4 */ -static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { - { .irq = 62 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { - { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_i2c4_irqs, - .sdma_reqs = omap44xx_i2c4_sdma_reqs, .main_clk = "func_96m_fclk", .prcm = { .omap4 = { @@ -1662,11 +1409,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { }; /* ipu */ -static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { - { .irq = 100 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "cpu0", .rst_shift = 0 }, { .name = "cpu1", .rst_shift = 1 }, @@ -1676,7 +1418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, .clkdm_name = "ducati_clkdm", - .mpu_irqs = omap44xx_ipu_irqs, .rst_lines = omap44xx_ipu_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), .main_clk = "ducati_clk_mux_ck", @@ -1721,19 +1462,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = { }; /* iss */ -static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { - { .irq = 24 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { - { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, - { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, - { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, - { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk iss_opt_clks[] = { { .role = "ctrlclk", .clk = "iss_ctrlclk" }, }; @@ -1742,8 +1470,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { .name = "iss", .class = &omap44xx_iss_hwmod_class, .clkdm_name = "iss_clkdm", - .mpu_irqs = omap44xx_iss_irqs, - .sdma_reqs = omap44xx_iss_sdma_reqs, .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { @@ -1766,13 +1492,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = { }; /* iva */ -static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { - { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, - { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, - { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { { .name = "seq0", .rst_shift = 0 }, { .name = "seq1", .rst_shift = 1 }, @@ -1783,7 +1502,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .name = "iva", .class = &omap44xx_iva_hwmod_class, .clkdm_name = "ivahd_clkdm", - .mpu_irqs = omap44xx_iva_irqs, .rst_lines = omap44xx_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), .main_clk = "dpll_iva_m5x2_ck", @@ -1820,16 +1538,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { }; /* kbd */ -static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { - { .irq = 120 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_kbd_hwmod = { .name = "kbd", .class = &omap44xx_kbd_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = omap44xx_kbd_irqs, .main_clk = "sys_32k_ck", .prcm = { .omap4 = { @@ -1861,16 +1573,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { }; /* mailbox */ -static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { - { .irq = 26 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_mailbox_hwmod = { .name = "mailbox", .class = &omap44xx_mailbox_hwmod_class, .clkdm_name = "l4_cfg_clkdm", - .mpu_irqs = omap44xx_mailbox_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, @@ -1903,24 +1609,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { }; /* mcasp */ -static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { - { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, - { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { - { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, - { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_mcasp_hwmod = { .name = "mcasp", .class = &omap44xx_mcasp_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_mcasp_irqs, - .sdma_reqs = omap44xx_mcasp_sdma_reqs, .main_clk = "func_mcasp_abe_gfclk", .prcm = { .omap4 = { @@ -1951,17 +1643,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { }; /* mcbsp1 */ -static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { - { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { - { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, @@ -1971,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_mcbsp1_irqs, - .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, .main_clk = "func_mcbsp1_gfclk", .prcm = { .omap4 = { @@ -1986,17 +1665,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { }; /* mcbsp2 */ -static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { - { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { - { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, @@ -2006,8 +1674,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_mcbsp2_irqs, - .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, .main_clk = "func_mcbsp2_gfclk", .prcm = { .omap4 = { @@ -2021,17 +1687,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { }; /* mcbsp3 */ -static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { - { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { - { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, @@ -2041,8 +1696,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_mcbsp3_irqs, - .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, .main_clk = "func_mcbsp3_gfclk", .prcm = { .omap4 = { @@ -2056,17 +1709,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { }; /* mcbsp4 */ -static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { - { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { - { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, @@ -2076,8 +1718,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap44xx_mcbsp_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mcbsp4_irqs, - .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, .main_clk = "per_mcbsp4_gfclk", .prcm = { .omap4 = { @@ -2112,17 +1752,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { }; /* mcpdm */ -static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { - { .irq = 112 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { - { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, - { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_mcpdm_hwmod = { .name = "mcpdm", .class = &omap44xx_mcpdm_hwmod_class, @@ -2139,8 +1768,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { * results 'slow motion' audio playback. */ .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, - .mpu_irqs = omap44xx_mcpdm_irqs, - .sdma_reqs = omap44xx_mcpdm_sdma_reqs, .main_clk = "pad_clks_ck", .prcm = { .omap4 = { @@ -2174,11 +1801,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { }; /* mcspi1 */ -static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { - { .irq = 65 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, @@ -2200,7 +1822,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mcspi1_irqs, .sdma_reqs = omap44xx_mcspi1_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2214,11 +1835,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { }; /* mcspi2 */ -static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { - { .irq = 66 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, @@ -2236,7 +1852,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mcspi2_irqs, .sdma_reqs = omap44xx_mcspi2_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2250,11 +1865,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { }; /* mcspi3 */ -static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { - { .irq = 91 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, @@ -2272,7 +1882,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mcspi3_irqs, .sdma_reqs = omap44xx_mcspi3_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2286,11 +1895,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { }; /* mcspi4 */ -static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { - { .irq = 48 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, @@ -2306,7 +1910,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mcspi4_irqs, .sdma_reqs = omap44xx_mcspi4_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2342,11 +1945,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { }; /* mmc1 */ -static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { - { .irq = 83 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, @@ -2362,7 +1960,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .name = "mmc1", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_mmc1_irqs, .sdma_reqs = omap44xx_mmc1_sdma_reqs, .main_clk = "hsmmc1_fclk", .prcm = { @@ -2376,11 +1973,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { }; /* mmc2 */ -static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { - { .irq = 86 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, @@ -2391,7 +1983,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .name = "mmc2", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_mmc2_irqs, .sdma_reqs = omap44xx_mmc2_sdma_reqs, .main_clk = "hsmmc2_fclk", .prcm = { @@ -2404,11 +1995,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { }; /* mmc3 */ -static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { - { .irq = 94 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, @@ -2419,7 +2005,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .name = "mmc3", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mmc3_irqs, .sdma_reqs = omap44xx_mmc3_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2432,11 +2017,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { }; /* mmc4 */ -static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { - { .irq = 96 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, @@ -2447,7 +2027,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .name = "mmc4", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mmc4_irqs, .sdma_reqs = omap44xx_mmc4_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2460,11 +2039,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { }; /* mmc5 */ -static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { - { .irq = 59 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, @@ -2475,7 +2049,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .name = "mmc5", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_mmc5_irqs, .sdma_reqs = omap44xx_mmc5_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { @@ -2517,11 +2090,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { }; static struct omap_hwmod omap44xx_mmu_ipu_hwmod; -static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { - { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, - { .irq = -1 } -}; - static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; @@ -2548,7 +2116,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { .name = "mmu_ipu", .class = &omap44xx_mmu_hwmod_class, .clkdm_name = "ducati_clkdm", - .mpu_irqs = omap44xx_mmu_ipu_irqs, .rst_lines = omap44xx_mmu_ipu_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), .main_clk = "ducati_clk_mux_ck", @@ -2572,11 +2139,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { }; static struct omap_hwmod omap44xx_mmu_dsp_hwmod; -static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { - { .irq = 28 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { { .name = "mmu_cache", .rst_shift = 1 }, }; @@ -2603,7 +2165,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { .name = "mmu_dsp", .class = &omap44xx_mmu_hwmod_class, .clkdm_name = "tesla_clkdm", - .mpu_irqs = omap44xx_mmu_dsp_irqs, .rst_lines = omap44xx_mmu_dsp_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), .main_clk = "dpll_iva_m4x2_ck", @@ -2628,21 +2189,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { }; /* mpu */ -static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { - { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START }, - { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START }, - { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, - { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, - { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_mpu_hwmod = { .name = "mpu", .class = &omap44xx_mpu_hwmod_class, .clkdm_name = "mpuss_clkdm", .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, - .mpu_irqs = omap44xx_mpu_irqs, .main_clk = "dpll_mpu_m2_ck", .prcm = { .omap4 = { @@ -2695,25 +2246,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { .sysc = &omap44xx_ocp2scp_sysc, }; -/* ocp2scp dev_attr */ -static struct resource omap44xx_usb_phy_and_pll_addrs[] = { - { - .name = "usb_phy", - .start = 0x4a0ad080, - .end = 0x4a0ae000, - .flags = IORESOURCE_MEM, - }, - { } -}; - -static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = { - { - .drv_name = "omap-usb2", - .res = omap44xx_usb_phy_and_pll_addrs, - }, - { } -}; - /* ocp2scp_usb_phy */ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", @@ -2737,7 +2269,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .dev_attr = ocp2scp_dev_attr, }; /* @@ -2788,11 +2319,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = { }; /* prm */ -static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { - { .irq = 11 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { { .name = "rst_global_warm_sw", .rst_shift = 0 }, { .name = "rst_global_cold_sw", .rst_shift = 1 }, @@ -2801,7 +2327,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { static struct omap_hwmod omap44xx_prm_hwmod = { .name = "prm", .class = &omap44xx_prcm_hwmod_class, - .mpu_irqs = omap44xx_prm_irqs, .rst_lines = omap44xx_prm_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), }; @@ -2872,23 +2397,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { }; /* slimbus1 */ -static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { - { .irq = 97 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { - { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, - { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, - { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, - { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, - { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, @@ -2900,8 +2408,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = { .name = "slimbus1", .class = &omap44xx_slimbus_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_slimbus1_irqs, - .sdma_reqs = omap44xx_slimbus1_sdma_reqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, @@ -2914,23 +2420,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = { }; /* slimbus2 */ -static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { - { .irq = 98 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { - { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, - { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, - { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, - { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, - { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, @@ -2941,8 +2430,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = { .name = "slimbus2", .class = &omap44xx_slimbus_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_slimbus2_irqs, - .sdma_reqs = omap44xx_slimbus2_sdma_reqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, @@ -2985,16 +2472,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { .sensor_voltdm_name = "core", }; -static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { - { .irq = 19 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .name = "smartreflex_core", .class = &omap44xx_smartreflex_hwmod_class, .clkdm_name = "l4_ao_clkdm", - .mpu_irqs = omap44xx_smartreflex_core_irqs, .main_clk = "smartreflex_core_fck", .prcm = { @@ -3012,16 +2493,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { .sensor_voltdm_name = "iva", }; -static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { - { .irq = 102 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .name = "smartreflex_iva", .class = &omap44xx_smartreflex_hwmod_class, .clkdm_name = "l4_ao_clkdm", - .mpu_irqs = omap44xx_smartreflex_iva_irqs, .main_clk = "smartreflex_iva_fck", .prcm = { .omap4 = { @@ -3038,16 +2513,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { .sensor_voltdm_name = "mpu", }; -static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { - { .irq = 18 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .name = "smartreflex_mpu", .class = &omap44xx_smartreflex_hwmod_class, .clkdm_name = "l4_ao_clkdm", - .mpu_irqs = omap44xx_smartreflex_mpu_irqs, .main_clk = "smartreflex_mpu_fck", .prcm = { .omap4 = { @@ -3155,17 +2624,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { }; /* timer1 */ -static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { - { .irq = 37 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_timer1_irqs, .main_clk = "dmt1_clk_mux", .prcm = { .omap4 = { @@ -3178,17 +2641,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { }; /* timer2 */ -static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { - { .irq = 38 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer2_hwmod = { .name = "timer2", .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_timer2_irqs, .main_clk = "cm2_dm2_mux", .prcm = { .omap4 = { @@ -3200,16 +2657,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { }; /* timer3 */ -static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { - { .irq = 39 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer3_hwmod = { .name = "timer3", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_timer3_irqs, .main_clk = "cm2_dm3_mux", .prcm = { .omap4 = { @@ -3221,16 +2672,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { }; /* timer4 */ -static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { - { .irq = 40 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer4_hwmod = { .name = "timer4", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_timer4_irqs, .main_clk = "cm2_dm4_mux", .prcm = { .omap4 = { @@ -3242,16 +2687,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { }; /* timer5 */ -static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { - { .irq = 41 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer5_hwmod = { .name = "timer5", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_timer5_irqs, .main_clk = "timer5_sync_mux", .prcm = { .omap4 = { @@ -3264,16 +2703,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { }; /* timer6 */ -static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { - { .irq = 42 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer6_hwmod = { .name = "timer6", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_timer6_irqs, .main_clk = "timer6_sync_mux", .prcm = { .omap4 = { @@ -3286,16 +2719,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { }; /* timer7 */ -static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { - { .irq = 43 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer7_hwmod = { .name = "timer7", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_timer7_irqs, .main_clk = "timer7_sync_mux", .prcm = { .omap4 = { @@ -3308,16 +2735,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { }; /* timer8 */ -static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { - { .irq = 44 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer8_hwmod = { .name = "timer8", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_timer8_irqs, .main_clk = "timer8_sync_mux", .prcm = { .omap4 = { @@ -3330,16 +2751,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { }; /* timer9 */ -static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { - { .irq = 45 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer9_hwmod = { .name = "timer9", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_timer9_irqs, .main_clk = "cm2_dm9_mux", .prcm = { .omap4 = { @@ -3352,17 +2767,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { }; /* timer10 */ -static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { - { .irq = 46 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer10_hwmod = { .name = "timer10", .class = &omap44xx_timer_1ms_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .mpu_irqs = omap44xx_timer10_irqs, .main_clk = "cm2_dm10_mux", .prcm = { .omap4 = { @@ -3375,16 +2784,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { }; /* timer11 */ -static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { - { .irq = 47 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_timer11_hwmod = { .name = "timer11", .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", - .mpu_irqs = omap44xx_timer11_irqs, .main_clk = "cm2_dm11_mux", .prcm = { .omap4 = { @@ -3419,24 +2822,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { }; /* uart1 */ -static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { - { .irq = 72 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { - { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = omap44xx_uart1_irqs, - .sdma_reqs = omap44xx_uart1_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -3448,24 +2838,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { }; /* uart2 */ -static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { - { .irq = 73 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { - { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_uart2_hwmod = { .name = "uart2", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = omap44xx_uart2_irqs, - .sdma_reqs = omap44xx_uart2_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -3477,25 +2854,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { }; /* uart3 */ -static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { - { .irq = 74 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { - { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = omap44xx_uart3_irqs, - .sdma_reqs = omap44xx_uart3_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -3507,24 +2871,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { }; /* uart4 */ -static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { - { .irq = 70 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { - { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SWSUP_SIDLE_ACT, - .mpu_irqs = omap44xx_uart4_irqs, - .sdma_reqs = omap44xx_uart4_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -3563,17 +2914,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { }; /* usb_host_fs */ -static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { - { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, - { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { .name = "usb_host_fs", .class = &omap44xx_usb_host_fs_hwmod_class, .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_usb_host_fs_irqs, .main_clk = "usb_host_fs_fck", .prcm = { .omap4 = { @@ -3607,12 +2951,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { }; /* usb_host_hs */ -static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, - { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { .name = "usb_host_hs", .class = &omap44xx_usb_host_hs_hwmod_class, @@ -3625,7 +2963,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .mpu_irqs = omap44xx_usb_host_hs_irqs, /* * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock @@ -3700,12 +3037,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { }; /* usb_otg_hs */ -static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { - { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, - { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { { .role = "xclk", .clk = "usb_otg_hs_xclk" }, }; @@ -3715,7 +3046,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { .class = &omap44xx_usb_otg_hs_hwmod_class, .clkdm_name = "l3_init_clkdm", .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .mpu_irqs = omap44xx_usb_otg_hs_irqs, .main_clk = "usb_otg_hs_ick", .prcm = { .omap4 = { @@ -3749,16 +3079,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { .sysc = &omap44xx_usb_tll_hs_sysc, }; -static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { .name = "usb_tll_hs", .class = &omap44xx_usb_tll_hs_hwmod_class, .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap44xx_usb_tll_hs_irqs, .main_clk = "usb_tll_hs_ick", .prcm = { .omap4 = { @@ -3794,16 +3118,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { }; /* wd_timer2 */ -static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { - { .irq = 80 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap44xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .mpu_irqs = omap44xx_wd_timer2_irqs, .main_clk = "sys_32k_ck", .prcm = { .omap4 = { @@ -3815,16 +3133,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { }; /* wd_timer3 */ -static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { - { .irq = 36 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .name = "wd_timer3", .class = &omap44xx_wd_timer_hwmod_class, .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_wd_timer3_irqs, .main_clk = "sys_32k_ck", .prcm = { .omap4 = { @@ -3840,32 +3152,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { * interfaces */ -static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { - { - .pa_start = 0x4a204000, - .pa_end = 0x4a2040ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* c2c -> c2c_target_fw */ -static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { - .master = &omap44xx_c2c_hwmod, - .slave = &omap44xx_c2c_target_fw_hwmod, - .clk = "div_core_ck", - .addr = omap44xx_c2c_target_fw_addrs, - .user = OCP_USER_MPU, -}; - -/* l4_cfg -> c2c_target_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_c2c_target_fw_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> dmm */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { .master = &omap44xx_l3_main_1_hwmod, @@ -3874,55 +3160,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { - { - .pa_start = 0x4e000000, - .pa_end = 0x4e0007ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* mpu -> dmm */ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { .master = &omap44xx_mpu_hwmod, .slave = &omap44xx_dmm_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dmm_addrs, - .user = OCP_USER_MPU, -}; - -/* c2c -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { - .master = &omap44xx_c2c_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "div_core_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dmm -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { - .master = &omap44xx_dmm_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { - { - .pa_start = 0x4a20c000, - .pa_end = 0x4a20c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_emif_fw_addrs, .user = OCP_USER_MPU, }; @@ -3998,32 +3240,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { - { - .pa_start = 0x44000000, - .pa_end = 0x44000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* mpu -> l3_main_1 */ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { .master = &omap44xx_mpu_hwmod, .slave = &omap44xx_l3_main_1_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_l3_main_1_addrs, .user = OCP_USER_MPU, }; -/* c2c_target_fw -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { - .master = &omap44xx_c2c_target_fw_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* debugss -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { .master = &omap44xx_debugss_hwmod, @@ -4088,21 +3312,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { - { - .pa_start = 0x44800000, - .pa_end = 0x44801fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_1 -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { .master = &omap44xx_l3_main_1_hwmod, .slave = &omap44xx_l3_main_2_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_l3_main_2_addrs, .user = OCP_USER_MPU, }; @@ -4138,21 +3352,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { - { - .pa_start = 0x45000000, - .pa_end = 0x45000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_1 -> l3_main_3 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { .master = &omap44xx_l3_main_1_hwmod, .slave = &omap44xx_l3_main_3_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_l3_main_3_addrs, .user = OCP_USER_MPU, }; @@ -4236,21 +3440,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { - { - .pa_start = 0x4a102000, - .pa_end = 0x4a10207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> ocp_wp_noc */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_ocp_wp_noc_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_ocp_wp_noc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4340,21 +3534,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { - { - .pa_start = 0x4a304000, - .pa_end = 0x4a30401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> counter_32k */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_counter_32k_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_counter_32k_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4430,21 +3614,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { - { - .pa_start = 0x54160000, - .pa_end = 0x54167fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_instr -> debugss */ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { .master = &omap44xx_l3_instr_hwmod, .slave = &omap44xx_debugss_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_debugss_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4466,41 +3640,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4012e000, - .pa_end = 0x4012e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> dmic */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_dmic_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x4902e000, - .pa_end = 0x4902e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> dmic (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_dmic_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_dma_addrs, .user = OCP_USER_SDMA, }; @@ -4798,42 +3950,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { - { - .pa_start = 0x4c000000, - .pa_end = 0x4c0000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* emif_fw -> emif1 */ -static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { - .master = &omap44xx_emif_fw_hwmod, - .slave = &omap44xx_emif1_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_emif1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { - { - .pa_start = 0x4d000000, - .pa_end = 0x4d0000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* emif_fw -> emif2 */ -static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { - .master = &omap44xx_emif_fw_hwmod, - .slave = &omap44xx_emif2_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_emif2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { { .pa_start = 0x4a10a000, @@ -4852,129 +3968,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { - { - .pa_start = 0x4a310000, - .pa_end = 0x4a3101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> gpio1 */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_gpio1_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_gpio1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { - { - .pa_start = 0x48055000, - .pa_end = 0x480551ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> gpio2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_gpio2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { - { - .pa_start = 0x48057000, - .pa_end = 0x480571ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> gpio3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio3_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_gpio3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { - { - .pa_start = 0x48059000, - .pa_end = 0x480591ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> gpio4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_gpio4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { - { - .pa_start = 0x4805b000, - .pa_end = 0x4805b1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> gpio5 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio5_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_gpio5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { - { - .pa_start = 0x4805d000, - .pa_end = 0x4805d1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> gpio6 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio6_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_gpio6_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { - { - .pa_start = 0x50000000, - .pa_end = 0x500003ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> gpmc */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_gpmc_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_gpmc_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5032,75 +4078,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { - { - .pa_start = 0x48070000, - .pa_end = 0x480700ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> i2c1 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_i2c1_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_i2c1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { - { - .pa_start = 0x48072000, - .pa_end = 0x480720ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> i2c2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_i2c2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_i2c2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x480600ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> i2c3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_i2c3_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_i2c3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { - { - .pa_start = 0x48350000, - .pa_end = 0x483500ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> i2c4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_i2c4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_i2c4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5138,39 +4144,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { .user = OCP_USER_IVA, }; -static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { - { - .pa_start = 0x5a000000, - .pa_end = 0x5a07ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> iva */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_iva_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_iva_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { - { - .pa_start = 0x4a31c000, - .pa_end = 0x4a31c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> kbd */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_kbd_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_kbd_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5228,335 +4214,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40122000, - .pa_end = 0x401220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcbsp1 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp1_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcbsp1 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp1_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40124000, - .pa_end = 0x401240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcbsp2 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp2_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcbsp2 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp2_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40126000, - .pa_end = 0x401260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcbsp3 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp3_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcbsp3 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcbsp3_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { - { - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mcbsp4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mcbsp4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mcbsp4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40132000, - .pa_end = 0x4013207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcpdm */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcpdm_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49032000, - .pa_end = 0x4903207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcpdm (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcpdm_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { - { - .pa_start = 0x48098000, - .pa_end = 0x480981ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mcspi1 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mcspi1_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mcspi1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { - { - .pa_start = 0x4809a000, - .pa_end = 0x4809a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mcspi2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mcspi2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mcspi2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { - { - .pa_start = 0x480b8000, - .pa_end = 0x480b81ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mcspi3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mcspi3_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mcspi3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mcspi4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mcspi4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mcspi4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mmc1 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mmc1_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmc1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { - { - .pa_start = 0x480b4000, - .pa_end = 0x480b43ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mmc2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mmc2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmc2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mmc3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mmc3_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmc3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { - { - .pa_start = 0x480d1000, - .pa_end = 0x480d13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mmc4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mmc4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmc4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { - { - .pa_start = 0x480d5000, - .pa_end = 0x480d53ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> mmc5 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_mmc5_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmc5_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5568,111 +4366,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { - { - .pa_start = 0x4a0ad000, - .pa_end = 0x4a0ad01f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> ocp2scp_usb_phy */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_ocp2scp_usb_phy_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_ocp2scp_usb_phy_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { - { - .pa_start = 0x48243000, - .pa_end = 0x48243fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* mpu_private -> prcm_mpu */ static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { .master = &omap44xx_mpu_private_hwmod, .slave = &omap44xx_prcm_mpu_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_prcm_mpu_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { - { - .pa_start = 0x4a004000, - .pa_end = 0x4a004fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> cm_core_aon */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_cm_core_aon_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_cm_core_aon_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { - { - .pa_start = 0x4a008000, - .pa_end = 0x4a009fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> cm_core */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_cm_core_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_cm_core_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { - { - .pa_start = 0x4a306000, - .pa_end = 0x4a307fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> prm */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_prm_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_prm_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { - { - .pa_start = 0x4a30a000, - .pa_end = 0x4a30a7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> scrm */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_scrm_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_scrm_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -5810,447 +4548,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { - { - .pa_start = 0x4a318000, - .pa_end = 0x4a31807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> timer1 */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_timer1_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { - { - .pa_start = 0x48032000, - .pa_end = 0x4803207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> timer2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_timer2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { - { - .pa_start = 0x48034000, - .pa_end = 0x4803407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> timer3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_timer3_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_timer3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { - { - .pa_start = 0x48036000, - .pa_end = 0x4803607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> timer4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_timer4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_timer4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { - { - .pa_start = 0x40138000, - .pa_end = 0x4013807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer5 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer5_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x4903807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer5 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer5_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { - { - .pa_start = 0x4013a000, - .pa_end = 0x4013a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer6 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer6_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { - { - .pa_start = 0x4903a000, - .pa_end = 0x4903a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer6 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer6_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { - { - .pa_start = 0x4013c000, - .pa_end = 0x4013c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer7 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer7_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { - { - .pa_start = 0x4903c000, - .pa_end = 0x4903c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer7 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer7_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { - { - .pa_start = 0x4013e000, - .pa_end = 0x4013e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer8 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer8_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { - { - .pa_start = 0x4903e000, - .pa_end = 0x4903e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> timer8 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_timer8_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { - { - .pa_start = 0x4803e000, - .pa_end = 0x4803e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> timer9 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_timer9_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_timer9_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { - { - .pa_start = 0x48086000, - .pa_end = 0x4808607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> timer10 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_timer10_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_timer10_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { - { - .pa_start = 0x48088000, - .pa_end = 0x4808807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> timer11 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_timer11_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_timer11_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { - { - .pa_start = 0x4806a000, - .pa_end = 0x4806a0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> uart1 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_uart1_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_uart1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { - { - .pa_start = 0x4806c000, - .pa_end = 0x4806c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> uart2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_uart2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_uart2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { - { - .pa_start = 0x48020000, - .pa_end = 0x480200ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> uart3 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_uart3_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_uart3_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { - { - .pa_start = 0x4806e000, - .pa_end = 0x4806e0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> uart4 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_uart4_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_uart4_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { - { - .pa_start = 0x4a0a9000, - .pa_end = 0x4a0a93ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> usb_host_fs */ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_host_fs_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_usb_host_fs_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { - { - .name = "uhh", - .pa_start = 0x4a064000, - .pa_end = 0x4a0647ff, - .flags = ADDR_TYPE_RT - }, - { - .name = "ohci", - .pa_start = 0x4a064800, - .pa_end = 0x4a064bff, - }, - { - .name = "ehci", - .pa_start = 0x4a064c00, - .pa_end = 0x4a064fff, - }, - {} -}; - /* l4_cfg -> usb_host_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_host_hs_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_usb_host_hs_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { - { - .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> usb_otg_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_otg_hs_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_usb_otg_hs_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { - { - .name = "tll", - .pa_start = 0x4a062000, - .pa_end = 0x4a063fff, - .flags = ADDR_TYPE_RT - }, - {} -}; - /* l4_cfg -> usb_tll_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_tll_hs_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_usb_tll_hs_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { - { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_wd_timer2_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -6290,14 +4776,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { .user = OCP_USER_SDMA, }; +/* mpu -> emif1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_emif1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> emif2 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_emif2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { - &omap44xx_c2c__c2c_target_fw, - &omap44xx_l4_cfg__c2c_target_fw, &omap44xx_l3_main_1__dmm, &omap44xx_mpu__dmm, - &omap44xx_c2c__emif_fw, - &omap44xx_dmm__emif_fw, - &omap44xx_l4_cfg__emif_fw, &omap44xx_iva__l3_instr, &omap44xx_l3_main_3__l3_instr, &omap44xx_ocp_wp_noc__l3_instr, @@ -6308,7 +4805,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mmc1__l3_main_1, &omap44xx_mmc2__l3_main_1, &omap44xx_mpu__l3_main_1, - &omap44xx_c2c_target_fw__l3_main_2, &omap44xx_debugss__l3_main_2, &omap44xx_dma_system__l3_main_2, &omap44xx_fdif__l3_main_2, @@ -6364,8 +4860,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_2__dss_venc, &omap44xx_l4_per__dss_venc, &omap44xx_l4_per__elm, - &omap44xx_emif_fw__emif1, - &omap44xx_emif_fw__emif2, &omap44xx_l4_cfg__fdif, &omap44xx_l4_wkup__gpio1, &omap44xx_l4_per__gpio2, @@ -6450,6 +4944,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_wkup__wd_timer2, &omap44xx_l4_abe__wd_timer3, &omap44xx_l4_abe__wd_timer3_dma, + &omap44xx_mpu__emif1, + &omap44xx_mpu__emif2, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c new file mode 100644 index 00000000000..f37ae96b70a --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -0,0 +1,2150 @@ +/* + * Hardware modules present on the OMAP54xx chips + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley + * Benoit Cousson + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/power/smartreflex.h> +#include <linux/i2c-omap.h> + +#include <linux/omap-dma.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <plat/dmtimer.h> + +#include "omap_hwmod.h" +#include "omap_hwmod_common_data.h" +#include "cm1_54xx.h" +#include "cm2_54xx.h" +#include "prm54xx.h" +#include "prm-regbits-54xx.h" +#include "i2c.h" +#include "mmc.h" +#include "wd_timer.h" + +/* Base offset for all OMAP5 interrupts external to MPUSS */ +#define OMAP54XX_IRQ_GIC_START 32 + +/* Base offset for all OMAP5 dma requests */ +#define OMAP54XX_DMA_REQ_START 1 + + +/* + * IP blocks + */ + +/* + * 'dmm' class + * instance(s): dmm + */ +static struct omap_hwmod_class omap54xx_dmm_hwmod_class = { + .name = "dmm", +}; + +/* dmm */ +static struct omap_hwmod omap54xx_dmm_hwmod = { + .name = "dmm", + .class = &omap54xx_dmm_hwmod_class, + .clkdm_name = "emif_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'l3' class + * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 + */ +static struct omap_hwmod_class omap54xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_instr */ +static struct omap_hwmod omap54xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* l3_main_1 */ +static struct omap_hwmod omap54xx_l3_main_1_hwmod = { + .name = "l3_main_1", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, + }, + }, +}; + +/* l3_main_2 */ +static struct omap_hwmod omap54xx_l3_main_2_hwmod = { + .name = "l3_main_2", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3main2_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET, + }, + }, +}; + +/* l3_main_3 */ +static struct omap_hwmod omap54xx_l3_main_3_hwmod = { + .name = "l3_main_3", + .class = &omap54xx_l3_hwmod_class, + .clkdm_name = "l3instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'l4' class + * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup + */ +static struct omap_hwmod_class omap54xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_abe */ +static struct omap_hwmod omap54xx_l4_abe_hwmod = { + .name = "l4_abe", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "abe_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* l4_cfg */ +static struct omap_hwmod omap54xx_l4_cfg_hwmod = { + .name = "l4_cfg", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, + }, + }, +}; + +/* l4_per */ +static struct omap_hwmod omap54xx_l4_per_hwmod = { + .name = "l4_per", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "l4per_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET, + }, + }, +}; + +/* l4_wkup */ +static struct omap_hwmod omap54xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &omap54xx_l4_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'mpu_bus' class + * instance(s): mpu_private + */ +static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = { + .name = "mpu_bus", +}; + +/* mpu_private */ +static struct omap_hwmod omap54xx_mpu_private_hwmod = { + .name = "mpu_private", + .class = &omap54xx_mpu_bus_hwmod_class, + .clkdm_name = "mpu_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* + * 'counter' class + * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock + */ + +static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_counter_hwmod_class = { + .name = "counter", + .sysc = &omap54xx_counter_sysc, +}; + +/* counter_32k */ +static struct omap_hwmod omap54xx_counter_32k_hwmod = { + .name = "counter_32k", + .class = &omap54xx_counter_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'dma' class + * dma controller for data exchange between memory to memory (i.e. internal or + * external memory) and gp peripherals to memory or memory to gp peripherals + */ + +static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_dma_hwmod_class = { + .name = "dma", + .sysc = &omap54xx_dma_sysc, +}; + +/* dma dev_attr */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = { + { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START }, + { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START }, + { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START }, + { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap54xx_dma_system_hwmod = { + .name = "dma_system", + .class = &omap54xx_dma_hwmod_class, + .clkdm_name = "dma_clkdm", + .mpu_irqs = omap54xx_dma_system_irqs, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, + }, + }, + .dev_attr = &dma_dev_attr, +}; + +/* + * 'dmic' class + * digital microphone controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_dmic_hwmod_class = { + .name = "dmic", + .sysc = &omap54xx_dmic_sysc, +}; + +/* dmic */ +static struct omap_hwmod omap54xx_dmic_hwmod = { + .name = "dmic", + .class = &omap54xx_dmic_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "dmic_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'emif' class + * external memory interface no1 (wrapper) + */ + +static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = { + .rev_offs = 0x0000, +}; + +static struct omap_hwmod_class omap54xx_emif_hwmod_class = { + .name = "emif", + .sysc = &omap54xx_emif_sysc, +}; + +/* emif1 */ +static struct omap_hwmod omap54xx_emif1_hwmod = { + .name = "emif1", + .class = &omap54xx_emif_hwmod_class, + .clkdm_name = "emif_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_core_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* emif2 */ +static struct omap_hwmod omap54xx_emif2_hwmod = { + .name = "emif2", + .class = &omap54xx_emif_hwmod_class, + .clkdm_name = "emif_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_core_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'gpio' class + * general purpose io module + */ + +static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &omap54xx_gpio_sysc, + .rev = 2, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio1_hwmod = { + .name = "gpio1", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio2_hwmod = { + .name = "gpio2", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio3_hwmod = { + .name = "gpio3", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio4 */ +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio4_hwmod = { + .name = "gpio4", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio5 */ +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio5_hwmod = { + .name = "gpio5", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio6 */ +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio6_hwmod = { + .name = "gpio6", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio7 */ +static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { + { .role = "dbclk", .clk = "gpio7_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio7_hwmod = { + .name = "gpio7", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio8 */ +static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { + { .role = "dbclk", .clk = "gpio8_dbclk" }, +}; + +static struct omap_hwmod omap54xx_gpio8_hwmod = { + .name = "gpio8", + .class = &omap54xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* + * 'i2c' class + * multimaster high-speed i2c controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_i2c_hwmod_class = { + .name = "i2c", + .sysc = &omap54xx_i2c_sysc, + .reset = &omap_i2c_reset, + .rev = OMAP_I2C_IP_VERSION_2, +}; + +/* i2c dev_attr */ +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, +}; + +/* i2c1 */ +static struct omap_hwmod omap54xx_i2c1_hwmod = { + .name = "i2c1", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c2 */ +static struct omap_hwmod omap54xx_i2c2_hwmod = { + .name = "i2c2", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c3 */ +static struct omap_hwmod omap54xx_i2c3_hwmod = { + .name = "i2c3", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c4 */ +static struct omap_hwmod omap54xx_i2c4_hwmod = { + .name = "i2c4", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c5 */ +static struct omap_hwmod omap54xx_i2c5_hwmod = { + .name = "i2c5", + .class = &omap54xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* + * 'kbd' class + * keyboard controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_kbd_hwmod_class = { + .name = "kbd", + .sysc = &omap54xx_kbd_sysc, +}; + +/* kbd */ +static struct omap_hwmod omap54xx_kbd_hwmod = { + .name = "kbd", + .class = &omap54xx_kbd_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap54xx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE4, +}; + +/* mcbsp1 */ +static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, +}; + +static struct omap_hwmod omap54xx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap54xx_mcbsp_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "mcbsp1_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcbsp1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), +}; + +/* mcbsp2 */ +static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, +}; + +static struct omap_hwmod omap54xx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap54xx_mcbsp_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "mcbsp2_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcbsp2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), +}; + +/* mcbsp3 */ +static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { + { .role = "pad_fck", .clk = "pad_clks_ck" }, + { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, +}; + +static struct omap_hwmod omap54xx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap54xx_mcbsp_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "mcbsp3_gfclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcbsp3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), +}; + +/* + * 'mcpdm' class + * multi channel pdm controller (proprietary interface with phoenix power + * ic) + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = { + .name = "mcpdm", + .sysc = &omap54xx_mcpdm_sysc, +}; + +/* mcpdm */ +static struct omap_hwmod omap54xx_mcpdm_hwmod = { + .name = "mcpdm", + .class = &omap54xx_mcpdm_hwmod_class, + .clkdm_name = "abe_clkdm", + /* + * It's suspected that the McPDM requires an off-chip main + * functional clock, controlled via I2C. This IP block is + * currently reset very early during boot, before I2C is + * available, so it doesn't seem that we have any choice in + * the kernel other than to avoid resetting it. XXX This is + * really a hardware issue workaround: every IP block should + * be able to source its main functional clock from either + * on-chip or off-chip sources. McPDM seems to be the only + * current exception. + */ + + .flags = HWMOD_EXT_OPT_MAIN_CLK, + .main_clk = "pad_clks_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = { + .name = "mcspi", + .sysc = &omap54xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, +}; + +/* mcspi1 */ +/* mcspi1 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap54xx_mcspi1_hwmod = { + .name = "mcspi1", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi1_dev_attr, +}; + +/* mcspi2 */ +/* mcspi2 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap54xx_mcspi2_hwmod = { + .name = "mcspi2", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi2_dev_attr, +}; + +/* mcspi3 */ +/* mcspi3 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap54xx_mcspi3_hwmod = { + .name = "mcspi3", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi3_dev_attr, +}; + +/* mcspi4 */ +/* mcspi4 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { + .num_chipselect = 1, +}; + +static struct omap_hwmod omap54xx_mcspi4_hwmod = { + .name = "mcspi4", + .class = &omap54xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi4_dev_attr, +}; + +/* + * 'mmc' class + * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &omap54xx_mmc_sysc, +}; + +/* mmc1 */ +static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { + { .role = "32khz_clk", .clk = "mmc1_32khz_clk" }, +}; + +/* mmc1 dev_attr */ +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod omap54xx_mmc1_hwmod = { + .name = "mmc1", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "mmc1_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), + .dev_attr = &mmc1_dev_attr, +}; + +/* mmc2 */ +static struct omap_hwmod omap54xx_mmc2_hwmod = { + .name = "mmc2", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "mmc2_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mmc3 */ +static struct omap_hwmod omap54xx_mmc3_hwmod = { + .name = "mmc3", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mmc4 */ +static struct omap_hwmod omap54xx_mmc4_hwmod = { + .name = "mmc4", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* mmc5 */ +static struct omap_hwmod omap54xx_mmc5_hwmod = { + .name = "mmc5", + .class = &omap54xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'mpu' class + * mpu sub-system + */ + +static struct omap_hwmod_class omap54xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod omap54xx_mpu_hwmod = { + .name = "mpu", + .class = &omap54xx_mpu_hwmod_class, + .clkdm_name = "mpu_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'timer' class + * general purpose timer module with accurate 1ms tick + * This class contains several variants: ['timer_1ms', 'timer'] + */ + +static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, + .clockact = CLOCKACT_TEST_ICLK, +}; + +static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &omap54xx_timer_1ms_sysc, +}; + +static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap54xx_timer_sysc, +}; + +/* timer1 */ +static struct omap_hwmod omap54xx_timer1_hwmod = { + .name = "timer1", + .class = &omap54xx_timer_1ms_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "timer1_gfclk_mux", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer2 */ +static struct omap_hwmod omap54xx_timer2_hwmod = { + .name = "timer2", + .class = &omap54xx_timer_1ms_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer2_gfclk_mux", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer3 */ +static struct omap_hwmod omap54xx_timer3_hwmod = { + .name = "timer3", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer3_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer4 */ +static struct omap_hwmod omap54xx_timer4_hwmod = { + .name = "timer4", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer4_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer5 */ +static struct omap_hwmod omap54xx_timer5_hwmod = { + .name = "timer5", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer5_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer6 */ +static struct omap_hwmod omap54xx_timer6_hwmod = { + .name = "timer6", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer6_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer7 */ +static struct omap_hwmod omap54xx_timer7_hwmod = { + .name = "timer7", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer7_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer8 */ +static struct omap_hwmod omap54xx_timer8_hwmod = { + .name = "timer8", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .main_clk = "timer8_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer9 */ +static struct omap_hwmod omap54xx_timer9_hwmod = { + .name = "timer9", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer9_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer10 */ +static struct omap_hwmod omap54xx_timer10_hwmod = { + .name = "timer10", + .class = &omap54xx_timer_1ms_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer10_gfclk_mux", + .flags = HWMOD_SET_DEFAULT_CLOCKACT, + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer11 */ +static struct omap_hwmod omap54xx_timer11_hwmod = { + .name = "timer11", + .class = &omap54xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer11_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'uart' class + * universal asynchronous receiver/transmitter (uart) + */ + +static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = { + .rev_offs = 0x0050, + .sysc_offs = 0x0054, + .syss_offs = 0x0058, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_uart_hwmod_class = { + .name = "uart", + .sysc = &omap54xx_uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod omap54xx_uart1_hwmod = { + .name = "uart1", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart2 */ +static struct omap_hwmod omap54xx_uart2_hwmod = { + .name = "uart2", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart3 */ +static struct omap_hwmod omap54xx_uart3_hwmod = { + .name = "uart3", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart4 */ +static struct omap_hwmod omap54xx_uart4_hwmod = { + .name = "uart4", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart5 */ +static struct omap_hwmod omap54xx_uart5_hwmod = { + .name = "uart5", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart6 */ +static struct omap_hwmod omap54xx_uart6_hwmod = { + .name = "uart6", + .class = &omap54xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'usb_otg_ss' class + * 2.0 super speed (usb_otg_ss) controller + */ + +static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = { + .name = "usb_otg_ss", + .sysc = &omap54xx_usb_otg_ss_sysc, +}; + +/* usb_otg_ss */ +static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = { + { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" }, +}; + +static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = { + .name = "usb_otg_ss", + .class = &omap54xx_usb_otg_ss_hwmod_class, + .clkdm_name = "l3init_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "dpll_core_h13x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = usb_otg_ss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks), +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap54xx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable, +}; + +/* wd_timer2 */ +static struct omap_hwmod omap54xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap54xx_wd_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * Interfaces + */ + +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_dmm_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_SDMA, +}; + +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = { + .master = &omap54xx_l3_main_3_hwmod, + .slave = &omap54xx_l3_instr_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l3_main_2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_l3_main_2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l3_main_3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_l3_main_3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_l3_main_3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l4_abe_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_l4_abe_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l4_cfg_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_l4_per_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_wkup */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = { + .master = &omap54xx_l3_main_1_hwmod, + .slave = &omap54xx_l4_wkup_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_mpu_private_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_counter_32k_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_dma_system_hwmod, + .clk = "l4_root_clk_div", + .addr = omap54xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_dmic_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* mpu -> emif1 */ +static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_emif1_hwmod, + .clk = "dpll_core_h11x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> emif2 */ +static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = { + .master = &omap54xx_mpu_hwmod, + .slave = &omap54xx_emif2_hwmod, + .clk = "dpll_core_h11x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_gpio1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio7 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio7_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio8 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_gpio8_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> i2c5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_i2c5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_kbd_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcbsp1_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcbsp2_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcbsp3_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_mcpdm_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mcspi4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_mmc5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> mpu */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_mpu_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_timer1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer5_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer6_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer7_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = { + .master = &omap54xx_l4_abe_hwmod, + .slave = &omap54xx_timer8_hwmod, + .clk = "abe_iclk", + .user = OCP_USER_MPU, +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer9_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer10_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_timer11_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart3_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart5 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> uart6 */ +static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = { + .master = &omap54xx_l4_per_hwmod, + .slave = &omap54xx_uart6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> usb_otg_ss */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_usb_otg_ss_hwmod, + .clk = "dpll_core_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = { + .master = &omap54xx_l4_wkup_hwmod, + .slave = &omap54xx_wd_timer2_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { + &omap54xx_l3_main_1__dmm, + &omap54xx_l3_main_3__l3_instr, + &omap54xx_l3_main_2__l3_main_1, + &omap54xx_l4_cfg__l3_main_1, + &omap54xx_mpu__l3_main_1, + &omap54xx_l3_main_1__l3_main_2, + &omap54xx_l4_cfg__l3_main_2, + &omap54xx_l3_main_1__l3_main_3, + &omap54xx_l3_main_2__l3_main_3, + &omap54xx_l4_cfg__l3_main_3, + &omap54xx_l3_main_1__l4_abe, + &omap54xx_mpu__l4_abe, + &omap54xx_l3_main_1__l4_cfg, + &omap54xx_l3_main_2__l4_per, + &omap54xx_l3_main_1__l4_wkup, + &omap54xx_mpu__mpu_private, + &omap54xx_l4_wkup__counter_32k, + &omap54xx_l4_cfg__dma_system, + &omap54xx_l4_abe__dmic, + &omap54xx_mpu__emif1, + &omap54xx_mpu__emif2, + &omap54xx_l4_wkup__gpio1, + &omap54xx_l4_per__gpio2, + &omap54xx_l4_per__gpio3, + &omap54xx_l4_per__gpio4, + &omap54xx_l4_per__gpio5, + &omap54xx_l4_per__gpio6, + &omap54xx_l4_per__gpio7, + &omap54xx_l4_per__gpio8, + &omap54xx_l4_per__i2c1, + &omap54xx_l4_per__i2c2, + &omap54xx_l4_per__i2c3, + &omap54xx_l4_per__i2c4, + &omap54xx_l4_per__i2c5, + &omap54xx_l4_wkup__kbd, + &omap54xx_l4_abe__mcbsp1, + &omap54xx_l4_abe__mcbsp2, + &omap54xx_l4_abe__mcbsp3, + &omap54xx_l4_abe__mcpdm, + &omap54xx_l4_per__mcspi1, + &omap54xx_l4_per__mcspi2, + &omap54xx_l4_per__mcspi3, + &omap54xx_l4_per__mcspi4, + &omap54xx_l4_per__mmc1, + &omap54xx_l4_per__mmc2, + &omap54xx_l4_per__mmc3, + &omap54xx_l4_per__mmc4, + &omap54xx_l4_per__mmc5, + &omap54xx_l4_cfg__mpu, + &omap54xx_l4_wkup__timer1, + &omap54xx_l4_per__timer2, + &omap54xx_l4_per__timer3, + &omap54xx_l4_per__timer4, + &omap54xx_l4_abe__timer5, + &omap54xx_l4_abe__timer6, + &omap54xx_l4_abe__timer7, + &omap54xx_l4_abe__timer8, + &omap54xx_l4_per__timer9, + &omap54xx_l4_per__timer10, + &omap54xx_l4_per__timer11, + &omap54xx_l4_per__uart1, + &omap54xx_l4_per__uart2, + &omap54xx_l4_per__uart3, + &omap54xx_l4_per__uart4, + &omap54xx_l4_per__uart5, + &omap54xx_l4_per__uart6, + &omap54xx_l4_cfg__usb_otg_ss, + &omap54xx_l4_wkup__wd_timer2, + NULL, +}; + +int __init omap54xx_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs); +} diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index a251f87fa2a..82f0698933d 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -1,7 +1,7 @@ /* - * OMAP4 Power Management Routines + * OMAP4+ Power Management Routines * - * Copyright (C) 2010-2011 Texas Instruments, Inc. + * Copyright (C) 2010-2013 Texas Instruments, Inc. * Rajendra Nayak <rnayak@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com> * @@ -135,16 +135,16 @@ static void omap_default_idle(void) } /** - * omap4_pm_init - Init routine for OMAP4 PM + * omap4_init_static_deps - Add OMAP4 static dependencies * - * Initializes all powerdomain and clockdomain target states - * and all PRCM settings. + * Add needed static clockdomain dependencies on OMAP4 devices. + * Return: 0 on success or 'err' on failures */ -int __init omap4_pm_init(void) +static inline int omap4_init_static_deps(void) { - int ret; struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; struct clockdomain *ducati_clkdm, *l3_2_clkdm; + int ret = 0; if (omap_rev() == OMAP4430_REV_ES1_0) { WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); @@ -163,7 +163,7 @@ int __init omap4_pm_init(void) ret = pwrdm_for_each(pwrdms_setup, NULL); if (ret) { pr_err("Failed to setup powerdomains\n"); - goto err2; + return ret; } /* @@ -171,6 +171,10 @@ int __init omap4_pm_init(void) * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as * expected. The hardware recommendation is to enable static * dependencies for these to avoid system lock ups or random crashes. + * The L4 wakeup depedency is added to workaround the OCP sync hardware + * BUG with 32K synctimer which lead to incorrect timer value read + * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which + * are part of L4 wakeup clockdomain. */ mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); emif_clkdm = clkdm_lookup("l3_emif_clkdm"); @@ -179,7 +183,7 @@ int __init omap4_pm_init(void) ducati_clkdm = clkdm_lookup("ducati_clkdm"); if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l3_2_clkdm) || (!ducati_clkdm)) - goto err2; + return -EINVAL; ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); @@ -188,9 +192,42 @@ int __init omap4_pm_init(void) ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); if (ret) { pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); + return -EINVAL; + } + + return ret; +} + +/** + * omap4_pm_init - Init routine for OMAP4+ devices + * + * Initializes all powerdomain and clockdomain target states + * and all PRCM settings. + * Return: Returns the error code returned by called functions. + */ +int __init omap4_pm_init(void) +{ + int ret = 0; + + if (omap_rev() == OMAP4430_REV_ES1_0) { + WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); + return -ENODEV; + } + + pr_info("Power Management for TI OMAP4+ devices.\n"); + + ret = pwrdm_for_each(pwrdms_setup, NULL); + if (ret) { + pr_err("Failed to setup powerdomains.\n"); goto err2; } + if (cpu_is_omap44xx()) { + ret = omap4_init_static_deps(); + if (ret) + goto err2; + } + ret = omap4_mpuss_init(); if (ret) { pr_err("Failed to initialise OMAP4 MPUSS\n"); @@ -206,7 +243,8 @@ int __init omap4_pm_init(void) /* Overwrite the default cpu_do_idle() */ arm_pm_idle = omap_default_idle; - omap4_idle_init(); + if (cpu_is_omap44xx()) + omap4_idle_init(); err2: return ret; diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 86babd740d4..e233dfcbc18 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -102,6 +102,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm) if (_pwrdm_lookup(pwrdm->name)) return -EEXIST; + if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm) + if (!arch_pwrdm->pwrdm_has_voltdm()) + goto skip_voltdm; + voltdm = voltdm_lookup(pwrdm->voltdm.name); if (!voltdm) { pr_err("powerdomain: %s: voltagedomain %s does not exist\n", @@ -111,6 +115,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm) pwrdm->voltdm.ptr = voltdm; INIT_LIST_HEAD(&pwrdm->voltdm_node); voltdm_add_pwrdm(voltdm, pwrdm); +skip_voltdm: spin_lock_init(&pwrdm->_lock); list_add(&pwrdm->node, &pwrdm_list); diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 140c36074fe..e4d7bd6f94b 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -166,6 +166,7 @@ struct powerdomain { * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep * @pwrdm_wait_transition: Wait for a pd state transition to complete + * @pwrdm_has_voltdm: Check if a voltdm association is needed * * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family * chips, a powerdomain's power state is not allowed to directly @@ -196,6 +197,7 @@ struct pwrdm_ops { int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); + int (*pwrdm_has_voltdm)(void); }; int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); @@ -253,6 +255,7 @@ extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); +extern void omap54xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index f0e14e9efe5..e2d4bd80452 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = { .voltdm = { .name = "core" }, }; +static struct powerdomain device_81xx_pwrdm = { + .name = "device_pwrdm", + .prcm_offs = TI81XX_PRM_DEVICE_MOD, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain active_816x_pwrdm = { + .name = "active_pwrdm", + .prcm_offs = TI816X_PRM_ACTIVE_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain default_816x_pwrdm = { + .name = "default_pwrdm", + .prcm_offs = TI81XX_PRM_DEFAULT_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + +static struct powerdomain ivahd0_816x_pwrdm = { + .name = "ivahd0_pwrdm", + .prcm_offs = TI816X_PRM_IVAHD0_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "mpu_iva" }, +}; + +static struct powerdomain ivahd1_816x_pwrdm = { + .name = "ivahd1_pwrdm", + .prcm_offs = TI816X_PRM_IVAHD1_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "mpu_iva" }, +}; + +static struct powerdomain ivahd2_816x_pwrdm = { + .name = "ivahd2_pwrdm", + .prcm_offs = TI816X_PRM_IVAHD2_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "mpu_iva" }, +}; + +static struct powerdomain sgx_816x_pwrdm = { + .name = "sgx_pwrdm", + .prcm_offs = TI816X_PRM_SGX_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + /* As powerdomains are added or removed above, this list must also be changed */ static struct powerdomain *powerdomains_omap3430_common[] __initdata = { &wkup_omap2_pwrdm, @@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = { NULL }; +static struct powerdomain *powerdomains_ti81xx[] __initdata = { + &device_81xx_pwrdm, + &active_816x_pwrdm, + &default_816x_pwrdm, + &ivahd0_816x_pwrdm, + &ivahd1_816x_pwrdm, + &ivahd2_816x_pwrdm, + &sgx_816x_pwrdm, + NULL +}; + void __init omap3xxx_powerdomains_init(void) { unsigned int rev; @@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void) if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { pwrdm_register_pwrdms(powerdomains_am35x); + } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1 + || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) { + pwrdm_register_pwrdms(powerdomains_ti81xx); } else { pwrdm_register_pwrdms(powerdomains_omap3430_common); diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c new file mode 100644 index 00000000000..81f8a7cc26e --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -0,0 +1,331 @@ +/* + * OMAP54XX Power domains framework + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "powerdomain.h" + +#include "prcm-common.h" +#include "prcm44xx.h" +#include "prm-regbits-54xx.h" +#include "prm54xx.h" +#include "prcm_mpu54xx.h" + +/* core_54xx_pwrdm: CORE power domain */ +static struct powerdomain core_54xx_pwrdm = { + .name = "core_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CORE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* abe_54xx_pwrdm: Audio back end power domain */ +static struct powerdomain abe_54xx_pwrdm = { + .name = "abe_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_ABE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ +static struct powerdomain coreaon_54xx_pwrdm = { + .name = "coreaon_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_COREAON_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, +}; + +/* dss_54xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_54xx_pwrdm = { + .name = "dss_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_DSS_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_54xx_pwrdm = { + .name = "cpu0_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_54xx_pwrdm = { + .name = "cpu1_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST, + .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu1_l1 */ + }, +}; + +/* emu_54xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_54xx_pwrdm = { + .name = "emu_pwrdm", + .voltdm = { .name = "wkup" }, + .prcm_offs = OMAP54XX_PRM_EMU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, +}; + +/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_54xx_pwrdm = { + .name = "mpu_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = OMAP54XX_PRM_MPU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_OFF_RET, /* mpu_ram */ + }, +}; + +/* custefuse_54xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain custefuse_54xx_pwrdm = { + .name = "custefuse_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* dsp_54xx_pwrdm: Tesla processor power domain */ +static struct powerdomain dsp_54xx_pwrdm = { + .name = "dsp_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_DSP_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dsp_edma */ + [1] = PWRSTS_OFF_RET, /* dsp_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dsp_edma */ + [1] = PWRSTS_OFF_RET, /* dsp_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp_l2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cam_54xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_54xx_pwrdm = { + .name = "cam_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_CAM_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cam_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* cam_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_54xx_pwrdm = { + .name = "l3init_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = OMAP54XX_PRM_L3INIT_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [1] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* gpu_54xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gpu_54xx_pwrdm = { + .name = "gpu_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_GPU_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* wkupaon_54xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkupaon_54xx_pwrdm = { + .name = "wkupaon_pwrdm", + .voltdm = { .name = "wkup" }, + .prcm_offs = OMAP54XX_PRM_WKUPAON_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, + .banks = 1, + .pwrsts_mem_ret = { + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* wkup_bank */ + }, +}; + +/* iva_54xx_pwrdm: IVA-HD power domain */ +static struct powerdomain iva_54xx_pwrdm = { + .name = "iva_pwrdm", + .voltdm = { .name = "mm" }, + .prcm_offs = OMAP54XX_PRM_IVA_INST, + .prcm_partition = OMAP54XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* + * The following power domains are not under SW control + * + * mpuaon + * mmaon + */ + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_omap54xx[] __initdata = { + &core_54xx_pwrdm, + &abe_54xx_pwrdm, + &coreaon_54xx_pwrdm, + &dss_54xx_pwrdm, + &cpu0_54xx_pwrdm, + &cpu1_54xx_pwrdm, + &emu_54xx_pwrdm, + &mpu_54xx_pwrdm, + &custefuse_54xx_pwrdm, + &dsp_54xx_pwrdm, + &cam_54xx_pwrdm, + &l3init_54xx_pwrdm, + &gpu_54xx_pwrdm, + &wkupaon_54xx_pwrdm, + &iva_54xx_pwrdm, + NULL +}; + +void __init omap54xx_powerdomains_init(void) +{ + pwrdm_register_platform_funcs(&omap4_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_omap54xx); + pwrdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index c7d355fafd2..ff1ac4a82a0 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -48,6 +48,17 @@ #define OMAP3430_NEON_MOD 0xb00 #define OMAP3430ES2_USBHOST_MOD 0xc00 +/* + * TI81XX PRM module offsets + */ +#define TI81XX_PRM_DEVICE_MOD 0x0000 +#define TI816X_PRM_ACTIVE_MOD 0x0a00 +#define TI81XX_PRM_DEFAULT_MOD 0x0b00 +#define TI816X_PRM_IVAHD0_MOD 0x0c00 +#define TI816X_PRM_IVAHD1_MOD 0x0d00 +#define TI816X_PRM_IVAHD2_MOD 0x0e00 +#define TI816X_PRM_SGX_MOD 0x0f00 + /* 24XX register bits shared between CM & PRM registers */ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h index 7334ffb9d2c..f429cdd5a11 100644 --- a/arch/arm/mach-omap2/prcm44xx.h +++ b/arch/arm/mach-omap2/prcm44xx.h @@ -32,6 +32,12 @@ #define OMAP4430_SCRM_PARTITION 4 #define OMAP4430_PRCM_MPU_PARTITION 5 +#define OMAP54XX_PRM_PARTITION 1 +#define OMAP54XX_CM_CORE_AON_PARTITION 2 +#define OMAP54XX_CM_CORE_PARTITION 3 +#define OMAP54XX_SCRM_PARTITION 4 +#define OMAP54XX_PRCM_MPU_PARTITION 5 + /* * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition * IDs, plus one diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index 884af7bb4af..059bd4f4903 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h @@ -25,12 +25,9 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H +#include "prcm_mpu_44xx_54xx.h" #include "common.h" -# ifndef __ASSEMBLER__ -extern void __iomem *prcm_mpu_base; -# endif - #define OMAP4430_PRCM_MPU_BASE 0x48243000 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ @@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base; #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) -/* Function prototypes */ -# ifndef __ASSEMBLER__ -extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); -extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, - s16 idx); -extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu); -# endif - #endif diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h new file mode 100644 index 00000000000..bc2ce328831 --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu54xx.h @@ -0,0 +1,87 @@ +/* + * OMAP54xx PRCM MPU instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H + +#include "prcm_mpu_44xx_54xx.h" +#include "common.h" + +#define OMAP54XX_PRCM_MPU_BASE 0x48243000 + +#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg)) + +/* PRCM_MPU instances */ +#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200 +#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400 +#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600 +#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800 +#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00 + +/* PRCM_MPU clockdomain register offsets (from instance start) */ +#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000 +#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000 + + +/* + * PRCM_MPU + * + * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) + * point of view the PRCM_MPU is a single entity. It shares the same + * programming model as the global PRCM and thus can be assimilate as two new + * MOD inside the PRCM + */ + +/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */ +#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000 + +/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */ +#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 +#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 +#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 +#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 + +/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */ +#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 + +/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */ +#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020) + +/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */ +#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 + +/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */ +#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020) + +#endif diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h new file mode 100644 index 00000000000..ca149e70bed --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h @@ -0,0 +1,36 @@ +/* + * OMAP44xx and OMAP54xx PRCM MPU function prototypes + * + * Copyright (C) 2010, 2013 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H + +#ifndef __ASSEMBLER__ +extern void __iomem *prcm_mpu_base; + +extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); +extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, + s16 idx); +extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu); +#endif + +#endif diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h new file mode 100644 index 00000000000..be31b21aa9c --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-54xx.h @@ -0,0 +1,2701 @@ +/* + * OMAP54xx Power Management register bits + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ABBOFF_ACT_SHIFT 1 +#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 +#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 +#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 +#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 +#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 +#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 +#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 +#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 +#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 +#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 +#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 +#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 +#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 +#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 +#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 +#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_ABE_PWRSTST */ +#define OMAP54XX_AESSMEM_STATEST_SHIFT 4 +#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 +#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_AIPOFF_SHIFT 8 +#define OMAP54XX_AIPOFF_WIDTH 0x1 +#define OMAP54XX_AIPOFF_MASK (1 << 8) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 +#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_RA_ERR_SHIFT 1 +#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_SA_ERR_SHIFT 0 +#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) + +/* Used by PRM_VC_BYPASS_ERRST */ +#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 +#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 +#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_C2C_RST_SHIFT 10 +#define OMAP54XX_C2C_RST_WIDTH 0x1 +#define OMAP54XX_C2C_RST_MASK (1 << 10) + +/* Used by PM_CAM_PWRSTCTRL */ +#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_CAM_PWRSTST */ +#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 +#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_CLKREQCTRL */ +#define OMAP54XX_CLKREQ_COND_SHIFT 0 +#define OMAP54XX_CLKREQ_COND_WIDTH 0x3 +#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 +#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 +#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 +#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 +#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 +#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 +#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 +#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 +#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 +#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) + +/* Used by REVISION_PRM */ +#define OMAP54XX_CUSTOM_SHIFT 6 +#define OMAP54XX_CUSTOM_WIDTH 0x2 +#define OMAP54XX_CUSTOM_MASK (0x3 << 6) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_DATA_SHIFT 16 +#define OMAP54XX_DATA_WIDTH 0x8 +#define OMAP54XX_DATA_MASK (0xff << 16) + +/* Used by PRM_DEBUG_CORE_RET_TRANS */ +#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 +#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c +#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa +#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 +#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 +#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) + +/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ +#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 +#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc +#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 +#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 +#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_DFILTEREN_SHIFT 6 +#define OMAP54XX_DFILTEREN_WIDTH 0x1 +#define OMAP54XX_DFILTEREN_MASK (1 << 6) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 +#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 +#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 +#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 +#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 +#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 +#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 +#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) + +/* Used by PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 +#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 +#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 +#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 +#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 +#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 +#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 +#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 +#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 +#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 +#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_L1_STATEST_SHIFT 4 +#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 +#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_DSP_PWRSTCTRL */ +#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 +#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) + +/* Used by PM_DSP_PWRSTST */ +#define OMAP54XX_DSP_L2_STATEST_SHIFT 6 +#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 +#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) + +/* Used by PM_DSS_PWRSTCTRL */ +#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_DSS_PWRSTCTRL */ +#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 +#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_DSS_PWRSTST */ +#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 +#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 +#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) + +/* Used by PRM_DEVICE_OFF_CTRL */ +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 +#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) + +/* Used by PM_EMU_PWRSTCTRL */ +#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 +#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_EMU_PWRSTST */ +#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 +#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) + +/* + * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, + * PRM_SRAM_WKUP_SETUP + */ +#define OMAP54XX_ENABLE_RTA_SHIFT 0 +#define OMAP54XX_ENABLE_RTA_WIDTH 0x1 +#define OMAP54XX_ENABLE_RTA_MASK (1 << 0) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC1_SHIFT 3 +#define OMAP54XX_ENFUNC1_WIDTH 0x1 +#define OMAP54XX_ENFUNC1_MASK (1 << 3) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC2_SHIFT 4 +#define OMAP54XX_ENFUNC2_WIDTH 0x1 +#define OMAP54XX_ENFUNC2_MASK (1 << 4) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC3_SHIFT 5 +#define OMAP54XX_ENFUNC3_WIDTH 0x1 +#define OMAP54XX_ENFUNC3_MASK (1 << 5) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC4_SHIFT 6 +#define OMAP54XX_ENFUNC4_WIDTH 0x1 +#define OMAP54XX_ENFUNC4_MASK (1 << 6) + +/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ +#define OMAP54XX_ENFUNC5_SHIFT 7 +#define OMAP54XX_ENFUNC5_WIDTH 0x1 +#define OMAP54XX_ENFUNC5_MASK (1 << 7) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_ERRORGAIN_SHIFT 16 +#define OMAP54XX_ERRORGAIN_WIDTH 0x8 +#define OMAP54XX_ERRORGAIN_MASK (0xff << 16) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_ERROROFFSET_SHIFT 24 +#define OMAP54XX_ERROROFFSET_WIDTH 0x8 +#define OMAP54XX_ERROROFFSET_MASK (0xff << 24) + +/* Used by PRM_RSTST */ +#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 +#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 +#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_FORCEUPDATE_SHIFT 1 +#define OMAP54XX_FORCEUPDATE_WIDTH 0x1 +#define OMAP54XX_FORCEUPDATE_MASK (1 << 1) + +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ +#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 +#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 +#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) + +/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ +#define OMAP54XX_FORCEWKUP_EN_SHIFT 10 +#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 +#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) + +/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ +#define OMAP54XX_FORCEWKUP_ST_SHIFT 10 +#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 +#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) + +/* Used by REVISION_PRM */ +#define OMAP54XX_FUNC_SHIFT 16 +#define OMAP54XX_FUNC_WIDTH 0xc +#define OMAP54XX_FUNC_MASK (0xfff << 16) + +/* Used by PRM_RSTST */ +#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 +#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 +#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) + +/* Used by PRM_RSTST */ +#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 +#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 +#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_GLOBAL_WUEN_SHIFT 16 +#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 +#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) + +/* Used by PM_GPU_PWRSTCTRL */ +#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_GPU_PWRSTST */ +#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 +#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_HSMCODE_SHIFT 0 +#define OMAP54XX_HSMCODE_WIDTH 0x3 +#define OMAP54XX_HSMCODE_MASK (0x7 << 0) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_HSMODEEN_SHIFT 3 +#define OMAP54XX_HSMODEEN_WIDTH 0x1 +#define OMAP54XX_HSMODEEN_MASK (1 << 3) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_HSSCLH_SHIFT 16 +#define OMAP54XX_HSSCLH_WIDTH 0x8 +#define OMAP54XX_HSSCLH_MASK (0xff << 16) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_HSSCLL_SHIFT 24 +#define OMAP54XX_HSSCLL_WIDTH 0x8 +#define OMAP54XX_HSSCLL_MASK (0xff << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 +#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 +#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 +#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_RSTST */ +#define OMAP54XX_ICEPICK_RST_SHIFT 9 +#define OMAP54XX_ICEPICK_RST_WIDTH 0x1 +#define OMAP54XX_ICEPICK_RST_MASK (1 << 9) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_INITVDD_SHIFT 2 +#define OMAP54XX_INITVDD_WIDTH 0x1 +#define OMAP54XX_INITVDD_MASK (1 << 2) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_INITVOLTAGE_SHIFT 8 +#define OMAP54XX_INITVOLTAGE_WIDTH 0x8 +#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, + * PRM_VOLTST_MM, PRM_VOLTST_MPU + */ +#define OMAP54XX_INTRANSITION_SHIFT 20 +#define OMAP54XX_INTRANSITION_WIDTH 0x1 +#define OMAP54XX_INTRANSITION_MASK (1 << 20) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_IO_EN_SHIFT 9 +#define OMAP54XX_IO_EN_WIDTH 0x1 +#define OMAP54XX_IO_EN_MASK (1 << 9) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_IO_ON_STATUS_SHIFT 5 +#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 +#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_IO_ST_SHIFT 9 +#define OMAP54XX_IO_ST_WIDTH 0x1 +#define OMAP54XX_IO_ST_MASK (1 << 9) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 +#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 +#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 +#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 +#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 +#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 +#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 +#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 +#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 +#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 +#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 +#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 +#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOCLK_STATUS_SHIFT 1 +#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 +#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 +#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 +#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) + +/* Used by PRM_IO_COUNT */ +#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 +#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 +#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 +#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 +#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 +#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) + +/* Used by PM_L3INIT_PWRSTST */ +#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 +#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 +#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_L3INIT_PWRSTCTRL */ +#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 +#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) + +/* Used by PM_L3INIT_PWRSTST */ +#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 +#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 +#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST + */ +#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 +#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 +#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) + +/* Used by PRM_RSTST */ +#define OMAP54XX_LLI_RST_SHIFT 14 +#define OMAP54XX_LLI_RST_WIDTH 0x1 +#define OMAP54XX_LLI_RST_MASK (1 << 14) + +/* + * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, + * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL + */ +#define OMAP54XX_LOGICRETSTATE_SHIFT 2 +#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 +#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST + */ +#define OMAP54XX_LOGICSTATEST_SHIFT 2 +#define OMAP54XX_LOGICSTATEST_WIDTH 0x1 +#define OMAP54XX_LOGICSTATEST_MASK (1 << 2) + +/* + * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, + * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, + * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, + * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, + * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, + * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, + * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, + * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, + * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, + * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, + * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, + * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, + * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, + * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, + * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, + * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, + * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, + * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, + * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, + * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, + * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, + * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, + * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, + * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, + * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, + * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, + * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, + * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, + * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, + * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, + * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, + * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, + * RM_WKUPAON_WD_TIMER2_CONTEXT + */ +#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 +#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 +#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) + +/* + * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, + * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, + * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, + * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, + * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, + * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, + * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, + * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, + * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, + * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, + * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, + * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, + * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, + * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, + * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, + * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, + * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, + * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, + * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT + */ +#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 +#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 +#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) + +/* Used by RM_ABE_AESS_CONTEXT */ +#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) + +/* Used by RM_CAM_CAL_CONTEXT */ +#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) + +/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ +#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) + +/* Used by RM_EMIF_DMM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) + +/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) + +/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) + +/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 +#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 +#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) + +/* Used by RM_DSP_DSP_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 +#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) + +/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ +#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) + +/* Used by RM_EMU_DEBUGSS_CONTEXT */ +#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) + +/* Used by RM_GPU_GPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 +#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) + +/* Used by RM_IPU_IPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 +#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) + +/* Used by RM_IPU_IPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) + +/* + * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, + * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, + * RM_L3INIT_USB_OTG_SS_CONTEXT + */ +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) + +/* Used by RM_MPU_MPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 +#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) + +/* Used by RM_MPU_MPU_CONTEXT */ +#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 +#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) + +/* + * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, + * RM_L4SEC_FPKA_CONTEXT + */ +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) + +/* + * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, + * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT + */ +#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) + +/* + * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, + * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, + * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT + */ +#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) + +/* Used by RM_IVA_SL2_CONTEXT */ +#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 +#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) + +/* Used by RM_IVA_IVA_CONTEXT */ +#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 +#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) + +/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ +#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 +#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 +#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) + +/* + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, + * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, + * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL + */ +#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 +#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 +#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) + +/* Used by PRM_DEBUG_TRANS_CFG */ +#define OMAP54XX_MODE_SHIFT 0 +#define OMAP54XX_MODE_WIDTH 0x2 +#define OMAP54XX_MODE_MASK (0x3 << 0) + +/* Used by PRM_MODEM_IF_CTRL */ +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 +#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) + +/* Used by PRM_MODEM_IF_CTRL */ +#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 +#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 +#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 +#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 +#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 +#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 +#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) + +/* Used by PM_MPU_PWRSTST */ +#define OMAP54XX_MPU_L2_STATEST_SHIFT 6 +#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 +#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 +#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_MPU_PWRSTCTRL */ +#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 +#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) + +/* Used by PM_MPU_PWRSTST */ +#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 +#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 +#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 +#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 +#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_MPU_WDT_RST_SHIFT 3 +#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 +#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_NOCAP_SHIFT 4 +#define OMAP54XX_NOCAP_WIDTH 0x1 +#define OMAP54XX_NOCAP_MASK (1 << 4) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 +#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) + +/* Used by PM_CORE_PWRSTCTRL */ +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 +#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) + +/* Used by PM_CORE_PWRSTST */ +#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 +#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 +#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_OFF_SHIFT 0 +#define OMAP54XX_OFF_WIDTH 0x8 +#define OMAP54XX_OFF_MASK (0xff << 0) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_ON_SHIFT 24 +#define OMAP54XX_ON_WIDTH 0x8 +#define OMAP54XX_ON_MASK (0xff << 24) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_ONLP_SHIFT 16 +#define OMAP54XX_ONLP_WIDTH 0x8 +#define OMAP54XX_ONLP_MASK (0xff << 16) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_OPP_CHANGE_SHIFT 2 +#define OMAP54XX_OPP_CHANGE_WIDTH 0x1 +#define OMAP54XX_OPP_CHANGE_MASK (1 << 2) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 +#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_OPP_SEL_SHIFT 0 +#define OMAP54XX_OPP_SEL_WIDTH 0x2 +#define OMAP54XX_OPP_SEL_MASK (0x3 << 0) + +/* Used by PRM_DEBUG_OUT */ +#define OMAP54XX_OUTPUT_SHIFT 0 +#define OMAP54XX_OUTPUT_WIDTH 0x20 +#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 +#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 +#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) + +/* Used by PRM_PSCON_COUNT */ +#define OMAP54XX_PCHARGE_TIME_SHIFT 0 +#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 +#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 +#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_ABE_PWRSTCTRL */ +#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 +#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) + +/* Used by PM_ABE_PWRSTST */ +#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 +#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 +#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) + +/* Used by PRM_PHASE1_CNDP */ +#define OMAP54XX_PHASE1_CNDP_SHIFT 0 +#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PHASE2A_CNDP */ +#define OMAP54XX_PHASE2A_CNDP_SHIFT 0 +#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PHASE2B_CNDP */ +#define OMAP54XX_PHASE2B_CNDP_SHIFT 0 +#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 +#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) + +/* Used by PRM_PSCON_COUNT */ +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 +#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) + +/* + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, + * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, + * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, + * PM_MPU_PWRSTCTRL + */ +#define OMAP54XX_POWERSTATE_SHIFT 0 +#define OMAP54XX_POWERSTATE_WIDTH 0x2 +#define OMAP54XX_POWERSTATE_MASK (0x3 << 0) + +/* + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, + * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, + * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST + */ +#define OMAP54XX_POWERSTATEST_SHIFT 0 +#define OMAP54XX_POWERSTATEST_WIDTH 0x2 +#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) + +/* Used by PRM_PWRREQCTRL */ +#define OMAP54XX_PWRREQ_COND_SHIFT 0 +#define OMAP54XX_PWRREQ_COND_WIDTH 0x2 +#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 +#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 +#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 +#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 +#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 +#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 +#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 +#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 +#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) + +/* + * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, + * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, + * PRM_VOLTSETUP_MPU_RET_SLEEP + */ +#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 +#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 +#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 +#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_REGADDR_SHIFT 8 +#define OMAP54XX_REGADDR_WIDTH 0x8 +#define OMAP54XX_REGADDR_MASK (0xff << 8) + +/* + * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, + * PRM_VC_VAL_CMD_VDD_MPU_L + */ +#define OMAP54XX_RET_SHIFT 8 +#define OMAP54XX_RET_WIDTH 0x8 +#define OMAP54XX_RET_MASK (0xff << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_RETMODE_ENABLE_SHIFT 0 +#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 +#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) + +/* Used by PRM_RSTTIME */ +#define OMAP54XX_RSTTIME1_SHIFT 0 +#define OMAP54XX_RSTTIME1_WIDTH 0xa +#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) + +/* Used by PRM_RSTTIME */ +#define OMAP54XX_RSTTIME2_SHIFT 10 +#define OMAP54XX_RSTTIME2_WIDTH 0x5 +#define OMAP54XX_RSTTIME2_MASK (0x1f << 10) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_CPU0_SHIFT 0 +#define OMAP54XX_RST_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_CPU0_MASK (1 << 0) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_CPU1_SHIFT 1 +#define OMAP54XX_RST_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_CPU1_MASK (1 << 1) + +/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_SHIFT 0 +#define OMAP54XX_RST_DSP_WIDTH 0x1 +#define OMAP54XX_RST_DSP_MASK (1 << 0) + +/* Used by RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_EMU_SHIFT 2 +#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 +#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) + +/* Used by RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 +#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 +#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) + +/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ +#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 +#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 +#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 +#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 +#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 +#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 +#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) + +/* Used by PRM_RSTCTRL */ +#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 +#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 +#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) + +/* Used by PRM_RSTCTRL */ +#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 +#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 +#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 +#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) + +/* Used by RM_IPU_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 +#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 +#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) + +/* Used by RM_IVA_RSTST */ +#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 +#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) + +/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ +#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 +#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 +#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_LOGIC_SHIFT 2 +#define OMAP54XX_RST_LOGIC_WIDTH 0x1 +#define OMAP54XX_RST_LOGIC_MASK (1 << 2) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_SEQ1_SHIFT 0 +#define OMAP54XX_RST_SEQ1_WIDTH 0x1 +#define OMAP54XX_RST_SEQ1_MASK (1 << 0) + +/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ +#define OMAP54XX_RST_SEQ2_SHIFT 1 +#define OMAP54XX_RST_SEQ2_WIDTH 0x1 +#define OMAP54XX_RST_SEQ2_MASK (1 << 1) + +/* Used by REVISION_PRM */ +#define OMAP54XX_R_RTL_SHIFT 11 +#define OMAP54XX_R_RTL_WIDTH 0x5 +#define OMAP54XX_R_RTL_MASK (0x1f << 11) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 +#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_SA_VDD_MM_L_SHIFT 0 +#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 +#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 +#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) + +/* Used by REVISION_PRM */ +#define OMAP54XX_SCHEME_SHIFT 30 +#define OMAP54XX_SCHEME_WIDTH 0x2 +#define OMAP54XX_SCHEME_MASK (0x3 << 30) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_SCLH_SHIFT 0 +#define OMAP54XX_SCLH_WIDTH 0x8 +#define OMAP54XX_SCLH_MASK (0xff << 0) + +/* Used by PRM_VC_CFG_I2C_CLK */ +#define OMAP54XX_SCLL_SHIFT 8 +#define OMAP54XX_SCLL_WIDTH 0x8 +#define OMAP54XX_SCLL_MASK (0xff << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_SECURE_WDT_RST_SHIFT 4 +#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 +#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 +#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 +#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 +#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 +#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 +#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_SLAVEADDR_SHIFT 0 +#define OMAP54XX_SLAVEADDR_WIDTH 0x7 +#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_SLPCNT_VALUE_SHIFT 16 +#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) + +/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ +#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 +#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 +#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) + +/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ +#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 +#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 +#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 +#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 +#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_SR2EN_SHIFT 0 +#define OMAP54XX_SR2EN_WIDTH 0x1 +#define OMAP54XX_SR2EN_MASK (1 << 0) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 +#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 +#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) + +/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ +#define OMAP54XX_SR2_STATUS_SHIFT 3 +#define OMAP54XX_SR2_STATUS_WIDTH 0x2 +#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) + +/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ +#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 +#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 +#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 +#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) + +/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ +#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 +#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 +#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) + +/* Used by PRM_VC_CFG_I2C_MODE */ +#define OMAP54XX_SRMODEEN_SHIFT 4 +#define OMAP54XX_SRMODEEN_WIDTH 0x1 +#define OMAP54XX_SRMODEEN_MASK (1 << 4) + +/* Used by PRM_VOLTSETUP_WARMRESET */ +#define OMAP54XX_STABLE_COUNT_SHIFT 0 +#define OMAP54XX_STABLE_COUNT_WIDTH 0x6 +#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) + +/* Used by PRM_VOLTSETUP_WARMRESET */ +#define OMAP54XX_STABLE_PRESCAL_SHIFT 8 +#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 +#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_BANDGAP_SETUP */ +#define OMAP54XX_STARTUP_COUNT_SHIFT 0 +#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 +#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) + +/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ +#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 +#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 +#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 +#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 +#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 +#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 +#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 +#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) + +/* Used by PM_IVA_PWRSTCTRL */ +#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 +#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 +#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) + +/* Used by PM_IVA_PWRSTST */ +#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 +#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 +#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_TIMEOUT_SHIFT 0 +#define OMAP54XX_TIMEOUT_WIDTH 0x10 +#define OMAP54XX_TIMEOUT_MASK (0xffff << 0) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_TIMEOUTEN_SHIFT 3 +#define OMAP54XX_TIMEOUTEN_WIDTH 0x1 +#define OMAP54XX_TIMEOUTEN_MASK (1 << 3) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_TRANSITION_EN_SHIFT 8 +#define OMAP54XX_TRANSITION_EN_WIDTH 0x1 +#define OMAP54XX_TRANSITION_EN_MASK (1 << 8) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_TRANSITION_ST_SHIFT 8 +#define OMAP54XX_TRANSITION_ST_WIDTH 0x1 +#define OMAP54XX_TRANSITION_ST_MASK (1 << 8) + +/* Used by PRM_DEBUG_TRANS_CFG */ +#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 +#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 +#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 +#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_MM_RST_SHIFT 12 +#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) + +/* Used by PRM_RSTST */ +#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 +#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 +#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) + +/* Used by PRM_VC_VAL_BYPASS */ +#define OMAP54XX_VALID_SHIFT 24 +#define OMAP54XX_VALID_WIDTH 0x1 +#define OMAP54XX_VALID_MASK (1 << 24) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 +#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 +#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 +#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 +#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 +#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 +#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 +#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 +#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 +#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 +#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_RAERR_EN_SHIFT 12 +#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_RAERR_ST_SHIFT 12 +#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_SAERR_EN_SHIFT 11 +#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_SAERR_ST_SHIFT 11 +#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VC_TOERR_EN_SHIFT 13 +#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 +#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VC_TOERR_ST_SHIFT 13 +#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 +#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_VDDMAX_SHIFT 24 +#define OMAP54XX_VDDMAX_WIDTH 0x8 +#define OMAP54XX_VDDMAX_MASK (0xff << 24) + +/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ +#define OMAP54XX_VDDMIN_SHIFT 16 +#define OMAP54XX_VDDMIN_WIDTH 0x8 +#define OMAP54XX_VDDMIN_MASK (0xff << 16) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 +#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 +#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 +#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 +#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 +#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) + +/* Used by PRM_VOLTCTRL */ +#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 +#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) + +/* Used by PRM_RSTST */ +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 +#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 +#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 +#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) + +/* Used by PRM_VC_CORE_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) + +/* Used by PRM_VC_MM_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) + +/* Used by PRM_VC_MPU_ERRST */ +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 +#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) + +/* Used by PRM_VC_SMPS_CORE_CONFIG */ +#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) + +/* Used by PRM_VC_SMPS_MM_CONFIG */ +#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) + +/* Used by PRM_VC_SMPS_MPU_CONFIG */ +#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 +#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 +#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) + +/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ +#define OMAP54XX_VOLTSTATEST_SHIFT 0 +#define OMAP54XX_VOLTSTATEST_WIDTH 0x2 +#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) + +/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ +#define OMAP54XX_VPENABLE_SHIFT 0 +#define OMAP54XX_VPENABLE_WIDTH 0x1 +#define OMAP54XX_VPENABLE_MASK (1 << 0) + +/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ +#define OMAP54XX_VPINIDLE_SHIFT 0 +#define OMAP54XX_VPINIDLE_WIDTH 0x1 +#define OMAP54XX_VPINIDLE_MASK (1 << 0) + +/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ +#define OMAP54XX_VPVOLTAGE_SHIFT 0 +#define OMAP54XX_VPVOLTAGE_WIDTH 0x8 +#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 +#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 +#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 +#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 +#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 +#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 +#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 +#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 +#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 +#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 +#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 +#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 +#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 +#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 +#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 +#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 +#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) + +/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ +#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 +#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) + +/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ +#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 +#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 +#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 +#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 +#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 +#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 +#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 +#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_MPU_2 */ +#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 +#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 +#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) + +/* Used by PRM_IRQSTATUS_MPU_2 */ +#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 +#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 +#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) + +/* Used by PRM_SRAM_COUNT */ +#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 +#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 +#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ +#define OMAP54XX_VSTEPMAX_SHIFT 0 +#define OMAP54XX_VSTEPMAX_WIDTH 0x8 +#define OMAP54XX_VSTEPMAX_MASK (0xff << 0) + +/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ +#define OMAP54XX_VSTEPMIN_SHIFT 0 +#define OMAP54XX_VSTEPMIN_WIDTH 0x8 +#define OMAP54XX_VSTEPMIN_MASK (0xff << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_DMIC_WKDEP */ +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_GPIO1_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO2_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO3_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO3_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO4_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO4_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO5_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO5_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO6_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO6_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) + +/* Used by PM_L4PER_GPIO7_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_GPIO8_WKDEP */ +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) + +/* Used by PM_DSS_DSS_WKDEP */ +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_HSI_WKDEP */ +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C1_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C2_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C3_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_I2C4_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_I2C5_WKDEP */ +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_KBD_WKDEP */ +#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCASP_WKDEP */ +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) + +/* Used by PM_ABE_MCBSP3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_MCPDM_WKDEP */ +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI1_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI2_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI3_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MCSPI4_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MCSPI4_WKDEP */ +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_MMC1_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_MMC2_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC3_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC4_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC4_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_MMC5_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_MMC5_WKDEP */ +#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_SATA_WKDEP */ +#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) + +/* Used by PM_ABE_SLIMBUS1_WKDEP */ +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) + +/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) + +/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER10_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER11_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER11_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_TIMER12_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_TIMER1_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER2_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER4_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER4_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER5_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER5_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER6_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER6_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER7_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER7_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) + +/* Used by PM_ABE_TIMER8_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) + +/* Used by PM_ABE_TIMER8_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_TIMER9_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_TIMER9_WKDEP */ +#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART1_WKDEP */ +#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART1_WKDEP */ +#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART2_WKDEP */ +#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART2_WKDEP */ +#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 +#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART3_WKDEP */ +#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART4_WKDEP */ +#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART4_WKDEP */ +#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART5_WKDEP */ +#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART5_WKDEP */ +#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) + +/* Used by PM_L4PER_UART6_WKDEP */ +#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) + +/* Used by PM_L4PER_UART6_WKDEP */ +#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 +#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) + +/* Used by PM_L3INIT_UNIPRO2_WKDEP */ +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) + +/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) + +/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) + +/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) + +/* Used by PM_ABE_WD_TIMER3_WKDEP */ +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 +#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_WUCLK_CTRL_SHIFT 8 +#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 +#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) + +/* Used by PRM_IO_PMCTRL */ +#define OMAP54XX_WUCLK_STATUS_SHIFT 9 +#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 +#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) + +/* Used by REVISION_PRM */ +#define OMAP54XX_X_MAJOR_SHIFT 8 +#define OMAP54XX_X_MAJOR_WIDTH 0x3 +#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_PRM */ +#define OMAP54XX_Y_MINOR_SHIFT 0 +#define OMAP54XX_Y_MINOR_WIDTH 0x6 +#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) +#endif diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index 44c0d7216aa..72044073774 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -320,6 +320,12 @@ static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) return 0; } +static int am33xx_check_vcvp(void) +{ + /* No VC/VP on am33xx devices */ + return 0; +} + struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, @@ -335,4 +341,5 @@ struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, + .pwrdm_has_voltdm = am33xx_check_vcvp, }; diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 8ee1fbdec56..7db2422faa1 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -25,6 +25,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H +#include "prm44xx_54xx.h" #include "prcm-common.h" #include "prm.h" @@ -744,36 +745,4 @@ #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) -/* Function prototypes */ -# ifndef __ASSEMBLER__ - -extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); -extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); -extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); - -/* OMAP4-specific VP functions */ -u32 omap4_prm_vp_check_txdone(u8 vp_id); -void omap4_prm_vp_clear_txdone(u8 vp_id); - -/* - * OMAP4 access functions for voltage controller (VC) and - * voltage proccessor (VP) in the PRM. - */ -extern u32 omap4_prm_vcvp_read(u8 offset); -extern void omap4_prm_vcvp_write(u32 val, u8 offset); -extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); - -extern void omap44xx_prm_reconfigure_io_chain(void); - -/* PRM interrupt-related functions */ -extern void omap44xx_prm_read_pending_irqs(unsigned long *events); -extern void omap44xx_prm_ocp_barrier(void); -extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); -extern void omap44xx_prm_restore_irqen(u32 *saved_mask); - -extern int __init omap44xx_prm_init(void); -extern u32 omap44xx_prm_get_reset_sources(void); - -# endif - #endif diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h new file mode 100644 index 00000000000..7cd22abb8f1 --- /dev/null +++ b/arch/arm/mach-omap2/prm44xx_54xx.h @@ -0,0 +1,58 @@ +/* + * OMAP44xx and 54xx PRM common functions + * + * Copyright (C) 2009-2013 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H + +/* Function prototypes */ +#ifndef __ASSEMBLER__ + +extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); +extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); +extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); + +/* OMAP4/OMAP5-specific VP functions */ +u32 omap4_prm_vp_check_txdone(u8 vp_id); +void omap4_prm_vp_clear_txdone(u8 vp_id); + +/* + * OMAP4/OMAP5 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap4_prm_vcvp_read(u8 offset); +extern void omap4_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); + +extern void omap44xx_prm_reconfigure_io_chain(void); + +/* PRM interrupt-related functions */ +extern void omap44xx_prm_read_pending_irqs(unsigned long *events); +extern void omap44xx_prm_ocp_barrier(void); +extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); +extern void omap44xx_prm_restore_irqen(u32 *saved_mask); + +extern int __init omap44xx_prm_init(void); +extern u32 omap44xx_prm_get_reset_sources(void); + +#endif + +#endif diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h new file mode 100644 index 00000000000..e4411010309 --- /dev/null +++ b/arch/arm/mach-omap2/prm54xx.h @@ -0,0 +1,421 @@ +/* + * OMAP54xx PRM instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H + +#include "prm44xx_54xx.h" +#include "prcm-common.h" +#include "prm.h" + +#define OMAP54XX_PRM_BASE 0x4ae06000 + +#define OMAP54XX_PRM_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg)) + + +/* PRM instances */ +#define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000 +#define OMAP54XX_PRM_CKGEN_INST 0x0100 +#define OMAP54XX_PRM_MPU_INST 0x0300 +#define OMAP54XX_PRM_DSP_INST 0x0400 +#define OMAP54XX_PRM_ABE_INST 0x0500 +#define OMAP54XX_PRM_COREAON_INST 0x0600 +#define OMAP54XX_PRM_CORE_INST 0x0700 +#define OMAP54XX_PRM_IVA_INST 0x1200 +#define OMAP54XX_PRM_CAM_INST 0x1300 +#define OMAP54XX_PRM_DSS_INST 0x1400 +#define OMAP54XX_PRM_GPU_INST 0x1500 +#define OMAP54XX_PRM_L3INIT_INST 0x1600 +#define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700 +#define OMAP54XX_PRM_WKUPAON_INST 0x1800 +#define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900 +#define OMAP54XX_PRM_EMU_INST 0x1a00 +#define OMAP54XX_PRM_EMU_CM_INST 0x1b00 +#define OMAP54XX_PRM_DEVICE_INST 0x1c00 +#define OMAP54XX_PRM_INSTR_INST 0x1f00 + +/* PRM clockdomain register offsets (from instance start) */ +#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 +#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 + +/* PRM */ + +/* PRM.OCP_SOCKET_PRM register offsets */ +#define OMAP54XX_REVISION_PRM_OFFSET 0x0000 +#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 +#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 +#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 +#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c +#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020 +#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028 +#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 +#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 +#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) +#define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 +#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 +#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 +#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098 +#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c +#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0 +#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4 + +/* PRM.CKGEN_PRM register offsets */ +#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 +#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) +#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 +#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) +#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c +#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) +#define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 +#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) + +/* PRM.MPU_PRM register offsets */ +#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 + +/* PRM.DSP_PRM register offsets */ +#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024 + +/* PRM.ABE_PRM register offsets */ +#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c +#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 +#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 +#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 +#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c +#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 +#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 +#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 +#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c +#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060 +#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064 +#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 +#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c +#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 +#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 +#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 +#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c +#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 +#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 +#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088 +#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c + +/* PRM.COREAON_PRM register offsets */ +#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028 +#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c + +/* PRM.CORE_PRM register offsets */ +#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124 +#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c +#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134 +#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210 +#define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214 +#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224 +#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 +#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 +#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c +#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 +#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c +#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 +#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524 +#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c +#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534 +#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 +#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c +#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 +#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c +#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 +#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724 +#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c +#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 +#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824 +#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c +#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834 +#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928 +#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c +#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930 +#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934 +#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938 +#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c +#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940 +#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944 +#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948 +#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c +#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950 +#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954 +#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c +#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960 +#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964 +#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968 +#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c +#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970 +#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974 +#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978 +#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c +#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980 +#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984 +#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c +#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0 +#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4 +#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8 +#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac +#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0 +#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4 +#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8 +#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc +#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0 +#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0 +#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4 +#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8 +#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc +#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00 +#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04 +#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08 +#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c +#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10 +#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14 +#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18 +#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c +#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20 +#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24 +#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28 +#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c +#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40 +#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44 +#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48 +#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c +#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50 +#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54 +#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58 +#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c +#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60 +#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64 +#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68 +#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c +#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70 +#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74 +#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78 +#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c +#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4 +#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac +#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4 +#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc +#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4 +#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc +#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc + +/* PRM.IVA_PRM register offsets */ +#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010 +#define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014 +#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c + +/* PRM.CAM_PRM register offsets */ +#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c +#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034 + +/* PRM.DSS_PRM register offsets */ +#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 +#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 + +/* PRM.GPU_PRM register offsets */ +#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 + +/* PRM.L3INIT_PRM register offsets */ +#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 +#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c +#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040 +#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044 +#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058 +#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c +#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068 +#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c +#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c +#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 +#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c +#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 +#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec +#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0 +#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4 + +/* PRM.CUSTEFUSE_PRM register offsets */ +#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 + +/* PRM.WKUPAON_PRM register offsets */ +#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024 +#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c +#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030 +#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034 +#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038 +#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c +#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040 +#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044 +#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048 +#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c +#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054 +#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064 +#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078 +#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c + +/* PRM.WKUPAON_CM register offsets */ +#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) +#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) +#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 +#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) +#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 +#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) +#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 +#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) +#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 +#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) +#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 +#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) +#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 +#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) +#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 +#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) +#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 +#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) +#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 +#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) + +/* PRM.EMU_PRM register offsets */ +#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004 +#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 + +/* PRM.EMU_CM register offsets */ +#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 +#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 +#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 +#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) +#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 +#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) + +/* PRM.DEVICE_PRM register offsets */ +#define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000 +#define OMAP54XX_PRM_RSTST_OFFSET 0x0004 +#define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008 +#define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c +#define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010 +#define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014 +#define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018 +#define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c +#define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020 +#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 +#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 +#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c +#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 +#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 +#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 +#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c +#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040 +#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044 +#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 +#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c +#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 +#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 +#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058 +#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c +#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 +#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 +#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 +#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c +#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070 +#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074 +#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078 +#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c +#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080 +#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084 +#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088 +#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c +#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090 +#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 +#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098 +#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c +#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 +#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4 +#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8 +#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac +#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0 +#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4 +#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8 +#define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc +#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 +#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 +#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 +#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc +#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 +#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4 +#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8 +#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc +#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 +#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4 +#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8 +#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec +#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 +#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 +#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 +#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc +#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 +#define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110 +#define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114 + +#endif diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h new file mode 100644 index 00000000000..57e86c8f823 --- /dev/null +++ b/arch/arm/mach-omap2/scrm54xx.h @@ -0,0 +1,231 @@ +/* + * OMAP54XX SCRM registers and bitfields + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H +#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H + +#define OMAP5_SCRM_BASE 0x4ae0a000 + +#define OMAP54XX_SCRM_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) + +/* SCRM */ + +/* SCRM.SCRM register offsets */ +#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 +#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) +#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 +#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) +#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 +#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) +#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 +#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) +#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 +#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) +#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c +#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) +#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 +#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) +#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 +#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) +#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 +#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) +#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 +#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) +#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 +#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) +#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 +#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) +#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c +#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) +#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 +#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) +#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 +#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) +#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 +#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) +#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 +#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) +#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 +#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) +#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 +#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) +#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c +#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) +#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 +#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) +#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 +#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) +#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 +#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) +#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 +#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) +#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c +#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) +#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 +#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) +#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 +#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) +#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 +#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) +#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 +#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) +#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c +#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) + +/* + * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, + * AUXCLKREQ5, D2DCLKREQ + */ +#define OMAP5_ACCURACY_SHIFT 1 +#define OMAP5_ACCURACY_WIDTH 0x1 +#define OMAP5_ACCURACY_MASK (1 << 1) + +/* Used by APEWARMRSTST */ +#define OMAP5_APEWARMRSTST_SHIFT 1 +#define OMAP5_APEWARMRSTST_WIDTH 0x1 +#define OMAP5_APEWARMRSTST_MASK (1 << 1) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_CLKDIV_SHIFT 16 +#define OMAP5_CLKDIV_WIDTH 0x4 +#define OMAP5_CLKDIV_MASK (0xf << 16) + +/* Used by D2DCLKM, MODEMCLKM */ +#define OMAP5_CLK_32KHZ_SHIFT 0 +#define OMAP5_CLK_32KHZ_WIDTH 0x1 +#define OMAP5_CLK_32KHZ_MASK (1 << 0) + +/* Used by D2DRSTCTRL, MODEMRSTCTRL */ +#define OMAP5_COLDRST_SHIFT 0 +#define OMAP5_COLDRST_WIDTH 0x1 +#define OMAP5_COLDRST_MASK (1 << 0) + +/* Used by D2DWARMRSTST */ +#define OMAP5_D2DWARMRSTST_SHIFT 3 +#define OMAP5_D2DWARMRSTST_WIDTH 0x1 +#define OMAP5_D2DWARMRSTST_MASK (1 << 3) + +/* Used by AUXCLK0 */ +#define OMAP5_DISABLECLK_SHIFT 9 +#define OMAP5_DISABLECLK_WIDTH 0x1 +#define OMAP5_DISABLECLK_MASK (1 << 9) + +/* Used by CLKSETUPTIME */ +#define OMAP5_DOWNTIME_SHIFT 16 +#define OMAP5_DOWNTIME_WIDTH 0x6 +#define OMAP5_DOWNTIME_MASK (0x3f << 16) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_ENABLE_SHIFT 8 +#define OMAP5_ENABLE_WIDTH 0x1 +#define OMAP5_ENABLE_MASK (1 << 8) + +/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ +#define OMAP5_ENABLE_0_0_SHIFT 0 +#define OMAP5_ENABLE_0_0_WIDTH 0x1 +#define OMAP5_ENABLE_0_0_MASK (1 << 0) + +/* Used by ALTCLKSRC */ +#define OMAP5_ENABLE_EXT_SHIFT 3 +#define OMAP5_ENABLE_EXT_WIDTH 0x1 +#define OMAP5_ENABLE_EXT_MASK (1 << 3) + +/* Used by ALTCLKSRC */ +#define OMAP5_ENABLE_INT_SHIFT 2 +#define OMAP5_ENABLE_INT_WIDTH 0x1 +#define OMAP5_ENABLE_INT_MASK (1 << 2) + +/* Used by EXTWARMRSTST */ +#define OMAP5_EXTWARMRSTST_SHIFT 0 +#define OMAP5_EXTWARMRSTST_WIDTH 0x1 +#define OMAP5_EXTWARMRSTST_MASK (1 << 0) + +/* + * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, + * AUXCLKREQ5 + */ +#define OMAP5_MAPPING_SHIFT 2 +#define OMAP5_MAPPING_WIDTH 0x3 +#define OMAP5_MAPPING_MASK (0x7 << 2) + +/* Used by ALTCLKSRC */ +#define OMAP5_MODE_SHIFT 0 +#define OMAP5_MODE_WIDTH 0x2 +#define OMAP5_MODE_MASK (0x3 << 0) + +/* Used by MODEMWARMRSTST */ +#define OMAP5_MODEMWARMRSTST_SHIFT 2 +#define OMAP5_MODEMWARMRSTST_WIDTH 0x1 +#define OMAP5_MODEMWARMRSTST_MASK (1 << 2) + +/* + * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, + * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, + * D2DCLKREQ, EXTCLKREQ, PWRREQ + */ +#define OMAP5_POLARITY_SHIFT 0 +#define OMAP5_POLARITY_WIDTH 0x1 +#define OMAP5_POLARITY_MASK (1 << 0) + +/* Used by EXTPWRONRSTCTRL */ +#define OMAP5_PWRONRST_SHIFT 1 +#define OMAP5_PWRONRST_WIDTH 0x1 +#define OMAP5_PWRONRST_MASK (1 << 1) + +/* Used by REVISION_SCRM */ +#define OMAP5_REV_SHIFT 0 +#define OMAP5_REV_WIDTH 0x8 +#define OMAP5_REV_MASK (0xff << 0) + +/* Used by RSTTIME */ +#define OMAP5_RSTTIME_SHIFT 0 +#define OMAP5_RSTTIME_WIDTH 0x4 +#define OMAP5_RSTTIME_MASK (0xf << 0) + +/* Used by CLKSETUPTIME */ +#define OMAP5_SETUPTIME_SHIFT 0 +#define OMAP5_SETUPTIME_WIDTH 0xc +#define OMAP5_SETUPTIME_MASK (0xfff << 0) + +/* Used by PMICSETUPTIME */ +#define OMAP5_SLEEPTIME_SHIFT 0 +#define OMAP5_SLEEPTIME_WIDTH 0x6 +#define OMAP5_SLEEPTIME_MASK (0x3f << 0) + +/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ +#define OMAP5_SRCSELECT_SHIFT 1 +#define OMAP5_SRCSELECT_WIDTH 0x2 +#define OMAP5_SRCSELECT_MASK (0x3 << 1) + +/* Used by D2DCLKM */ +#define OMAP5_SYSCLK_SHIFT 1 +#define OMAP5_SYSCLK_WIDTH 0x1 +#define OMAP5_SYSCLK_MASK (1 << 1) + +/* Used by PMICSETUPTIME */ +#define OMAP5_WAKEUPTIME_SHIFT 16 +#define OMAP5_WAKEUPTIME_WIDTH 0x6 +#define OMAP5_WAKEUPTIME_MASK (0x3f << 16) + +/* Used by D2DRSTCTRL, MODEMRSTCTRL */ +#define OMAP5_WARMRST_SHIFT 1 +#define OMAP5_WARMRST_WIDTH 0x1 +#define OMAP5_WARMRST_MASK (1 << 1) + +#endif diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index f6601563aa6..3a674de6cb6 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -63,7 +63,6 @@ struct omap_uart_state { static LIST_HEAD(uart_list); static u8 num_uarts; static u8 console_uart_id = -1; -static u8 no_console_suspend; static u8 uart_debug; #define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */ @@ -176,6 +175,9 @@ static char *cmdline_find_option(char *str) static int __init omap_serial_early_init(void) { + if (of_have_populated_dt()) + return -ENODEV; + do { char oh_name[MAX_UART_HWMOD_NAME_LEN]; struct omap_hwmod *oh; @@ -207,9 +209,6 @@ static int __init omap_serial_early_init(void) uart_name, uart->num); } - if (cmdline_find_option("no_console_suspend")) - no_console_suspend = true; - /* * omap-uart can be used for earlyprintk logs * So if omap-uart is used as console then prevent @@ -292,9 +291,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, return; } - if ((console_uart_id == bdata->id) && no_console_suspend) - omap_device_disable_idle_on_suspend(pdev); - oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); if (console_uart_id == bdata->id) { diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 197cc16870d..8c616e436bc 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -96,6 +96,15 @@ # endif #endif +#ifdef CONFIG_SOC_AM43XX +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME am43xx +# endif +#endif + /* * Omap device type i.e. EMU/HS/TST/GP/BAD */ @@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44) IS_AM_CLASS(35xx, 0x35) IS_OMAP_CLASS(54xx, 0x54) IS_AM_CLASS(33xx, 0x33) +IS_AM_CLASS(43xx, 0x43) IS_TI_CLASS(81xx, 0x81) @@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543) IS_TI_SUBCLASS(816x, 0x816) IS_TI_SUBCLASS(814x, 0x814) IS_AM_SUBCLASS(335x, 0x335) +IS_AM_SUBCLASS(437x, 0x437) #define cpu_is_omap24xx() 0 #define cpu_is_omap242x() 0 @@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335) #define soc_is_am35xx() 0 #define soc_is_am33xx() 0 #define soc_is_am335x() 0 +#define soc_is_am43xx() 0 +#define soc_is_am437x() 0 #define cpu_is_omap44xx() 0 #define cpu_is_omap443x() 0 #define cpu_is_omap446x() 0 @@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430) # define soc_is_am335x() is_am335x() #endif +#ifdef CONFIG_SOC_AM43XX +# undef soc_is_am43xx +# undef soc_is_am437x +# define soc_is_am43xx() is_am43xx() +# define soc_is_am437x() is_am437x() +#endif + # if defined(CONFIG_ARCH_OMAP4) # undef cpu_is_omap44xx # undef cpu_is_omap443x @@ -383,6 +403,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define TI816X_CLASS 0x81600034 #define TI8168_REV_ES1_0 TI816X_CLASS #define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) +#define TI8168_REV_ES2_0 (TI816X_CLASS | (0x2 << 8)) +#define TI8168_REV_ES2_1 (TI816X_CLASS | (0x3 << 8)) #define TI814X_CLASS 0x81400034 #define TI8148_REV_ES1_0 TI814X_CLASS @@ -398,6 +420,9 @@ IS_OMAP_TYPE(3430, 0x3430) #define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8)) #define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8)) +#define AM437X_CLASS 0x43700000 +#define AM437X_REV_ES1_0 AM437X_CLASS + #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) #define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) @@ -424,6 +449,7 @@ void omap4xxx_check_revision(void); void omap5xxx_check_revision(void); void omap3xxx_check_features(void); void ti81xx_check_features(void); +void am33xx_check_features(void); void omap4xxx_check_features(void); /* diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c index 0ff0f068bea..4bd09683623 100644 --- a/arch/arm/mach-omap2/sram.c +++ b/arch/arm/mach-omap2/sram.c @@ -119,6 +119,9 @@ static void __init omap_detect_sram(void) if (soc_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ + } else if (soc_is_am43xx()) { + omap_sram_start = AM33XX_SRAM_PA; + omap_sram_size = SZ_256K; } else if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index f8b23b8040d..3bdb0fb0202 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", 2, "timer_sys_ck", NULL); #endif /* CONFIG_ARCH_OMAP2 */ -#ifdef CONFIG_ARCH_OMAP3 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", 2, "timer_sys_ck", NULL); OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 51e138cc539..c05898fbd63 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -140,6 +140,7 @@ static struct regulator_init_data omap3_vdac_idata = { static struct regulator_consumer_supply omap3_vpll2_supplies[] = { REGULATOR_SUPPLY("vdds_dsi", "omapdss"), + REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"), REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"), }; diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index aa27d7f5cbb..2eb19d4d0aa 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -28,6 +28,7 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/usb/phy.h> +#include <linux/usb/nop-usb-xceiv.h> #include "soc.h" #include "omap_device.h" @@ -188,125 +189,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) return; } -static -void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) -{ - switch (port_mode[0]) { - case OMAP_EHCI_PORT_MODE_PHY: - omap_mux_init_signal("usbb1_ulpiphy_stp", - OMAP_PIN_OUTPUT); - omap_mux_init_signal("usbb1_ulpiphy_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpiphy_dat7", - OMAP_PIN_INPUT_PULLDOWN); - break; - case OMAP_EHCI_PORT_MODE_TLL: - omap_mux_init_signal("usbb1_ulpitll_stp", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("usbb1_ulpitll_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_ulpitll_dat7", - OMAP_PIN_INPUT_PULLDOWN); - break; - case OMAP_USBHS_PORT_MODE_UNUSED: - default: - break; - } - switch (port_mode[1]) { - case OMAP_EHCI_PORT_MODE_PHY: - omap_mux_init_signal("usbb2_ulpiphy_stp", - OMAP_PIN_OUTPUT); - omap_mux_init_signal("usbb2_ulpiphy_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpiphy_dat7", - OMAP_PIN_INPUT_PULLDOWN); - break; - case OMAP_EHCI_PORT_MODE_TLL: - omap_mux_init_signal("usbb2_ulpitll_stp", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("usbb2_ulpitll_clk", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dir", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_nxt", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat0", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat1", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat2", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat3", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat4", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat5", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat6", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_ulpitll_dat7", - OMAP_PIN_INPUT_PULLDOWN); - break; - case OMAP_USBHS_PORT_MODE_UNUSED: - default: - break; - } -} - static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { @@ -404,78 +286,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) } } -static -void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) -{ - switch (port_mode[0]) { - case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: - case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: - omap_mux_init_signal("usbb1_mm_rxdp", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_mm_rxdm", - OMAP_PIN_INPUT_PULLDOWN); - - case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: - case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: - omap_mux_init_signal("usbb1_mm_rxrcv", - OMAP_PIN_INPUT_PULLDOWN); - - case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: - omap_mux_init_signal("usbb1_mm_txen", - OMAP_PIN_INPUT_PULLDOWN); - - - case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: - omap_mux_init_signal("usbb1_mm_txdat", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb1_mm_txse0", - OMAP_PIN_INPUT_PULLDOWN); - break; - - case OMAP_USBHS_PORT_MODE_UNUSED: - default: - break; - } - - switch (port_mode[1]) { - case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: - case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: - omap_mux_init_signal("usbb2_mm_rxdp", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_mm_rxdm", - OMAP_PIN_INPUT_PULLDOWN); - - case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: - case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: - omap_mux_init_signal("usbb2_mm_rxrcv", - OMAP_PIN_INPUT_PULLDOWN); - - case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: - omap_mux_init_signal("usbb2_mm_txen", - OMAP_PIN_INPUT_PULLDOWN); - - - case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: - case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: - omap_mux_init_signal("usbb2_mm_txdat", - OMAP_PIN_INPUT_PULLDOWN); - omap_mux_init_signal("usbb2_mm_txse0", - OMAP_PIN_INPUT_PULLDOWN); - break; - - case OMAP_USBHS_PORT_MODE_UNUSED: - default: - break; - } -} - void __init usbhs_init(struct usbhs_omap_platform_data *pdata) { struct omap_hwmod *uhh_hwm, *tll_hwm; @@ -489,9 +299,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata) if (omap_rev() <= OMAP3430_REV_ES2_1) pdata->single_ulpi_bypass = true; - } else if (cpu_is_omap44xx()) { - setup_4430ehci_io_mux(pdata->port_mode); - setup_4430ohci_io_mux(pdata->port_mode); } uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME); @@ -560,7 +367,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply, struct regulator_init_data *reg_data; struct fixed_voltage_config *config; struct platform_device *pdev; - int ret; + struct platform_device_info pdevinfo; + int ret = -ENOMEM; supplies = kzalloc(sizeof(*supplies), GFP_KERNEL); if (!supplies) @@ -571,7 +379,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply, reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL); if (!reg_data) - return -ENOMEM; + goto err_data; reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; reg_data->consumer_supplies = supplies; @@ -580,39 +388,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply, config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config), GFP_KERNEL); if (!config) - return -ENOMEM; + goto err_config; + + config->supply_name = kstrdup(name, GFP_KERNEL); + if (!config->supply_name) + goto err_supplyname; - config->supply_name = name; config->gpio = gpio; config->enable_high = polarity; config->init_data = reg_data; /* create a regulator device */ - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.name = reg_name; + pdevinfo.id = PLATFORM_DEVID_AUTO; + pdevinfo.data = config; + pdevinfo.size_data = sizeof(*config); - pdev->id = PLATFORM_DEVID_AUTO; - pdev->name = reg_name; - pdev->dev.platform_data = config; + pdev = platform_device_register_full(&pdevinfo); + if (IS_ERR(pdev)) { + ret = PTR_ERR(pdev); + pr_err("%s: Failed registering regulator %s for %s : %d\n", + __func__, name, dev_id, ret); + goto err_register; + } - ret = platform_device_register(pdev); - if (ret) - pr_err("%s: Failed registering regulator %s for %s\n", - __func__, name, dev_id); + return 0; +err_register: + kfree(config->supply_name); +err_supplyname: + kfree(config); +err_config: + kfree(reg_data); +err_data: + kfree(supplies); return ret; } +#define MAX_STR 20 + int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) { - char *rail_name; - int i, len; + char rail_name[MAX_STR]; + int i; struct platform_device *pdev; char *phy_id; - - /* the phy_id will be something like "nop_usb_xceiv.1" */ - len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */ + struct platform_device_info pdevinfo; for (i = 0; i < num_phys; i++) { @@ -627,25 +449,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) !gpio_is_valid(phy->vcc_gpio)) continue; - /* create a NOP PHY device */ - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) + phy_id = kmalloc(MAX_STR, GFP_KERNEL); + if (!phy_id) { + pr_err("%s: kmalloc() failed\n", __func__); return -ENOMEM; + } - pdev->id = phy->port; - pdev->name = nop_name; - pdev->dev.platform_data = phy->platform_data; - - phy_id = kmalloc(len, GFP_KERNEL); - if (!phy_id) - return -ENOMEM; - - scnprintf(phy_id, len, "nop_usb_xceiv.%d\n", - pdev->id); - - if (platform_device_register(pdev)) { - pr_err("%s: Failed to register device %s\n", - __func__, phy_id); + /* create a NOP PHY device */ + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.name = nop_name; + pdevinfo.id = phy->port; + pdevinfo.data = phy->platform_data; + pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data); + + scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d", + phy->port); + pdev = platform_device_register_full(&pdevinfo); + if (IS_ERR(pdev)) { + pr_err("%s: Failed to register device %s : %ld\n", + __func__, phy_id, PTR_ERR(pdev)); + kfree(phy_id); continue; } @@ -653,26 +476,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) /* Do we need RESET regulator ? */ if (gpio_is_valid(phy->reset_gpio)) { - - rail_name = kmalloc(13, GFP_KERNEL); - if (!rail_name) - return -ENOMEM; - - scnprintf(rail_name, 13, "hsusb%d_reset", phy->port); - + scnprintf(rail_name, MAX_STR, + "hsusb%d_reset", phy->port); usbhs_add_regulator(rail_name, phy_id, "reset", phy->reset_gpio, 1); } /* Do we need VCC regulator ? */ if (gpio_is_valid(phy->vcc_gpio)) { - - rail_name = kmalloc(13, GFP_KERNEL); - if (!rail_name) - return -ENOMEM; - - scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port); - + scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port); usbhs_add_regulator(rail_name, phy_id, "vcc", phy->vcc_gpio, phy->vcc_polarity); } diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 3242a554ad6..8c4de2708cf 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) musb_plat.mode = board_data->mode; musb_plat.extvbus = board_data->extvbus; - if (cpu_is_omap44xx()) - musb_plat.has_mailbox = true; - if (soc_is_am35xx()) { oh_name = "am35x_otg_hs"; name = "musb-am35x"; diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index a0ce4f10ff1..f7f2879b31b 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -169,8 +169,8 @@ int omap_voltage_late_init(void); extern void omap2xxx_voltagedomains_init(void); extern void omap3xxx_voltagedomains_init(void); -extern void am33xx_voltagedomains_init(void); extern void omap44xx_voltagedomains_init(void); +extern void omap54xx_voltagedomains_init(void); struct voltagedomain *voltdm_lookup(const char *name); void voltdm_init(struct voltagedomain **voltdm_list); diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c deleted file mode 100644 index 965458dc0cb..00000000000 --- a/arch/arm/mach-omap2/voltagedomains33xx_data.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * AM33XX voltage domain data - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include "voltage.h" - -static struct voltagedomain am33xx_voltdm_mpu = { - .name = "mpu", -}; - -static struct voltagedomain am33xx_voltdm_core = { - .name = "core", -}; - -static struct voltagedomain am33xx_voltdm_rtc = { - .name = "rtc", -}; - -static struct voltagedomain *voltagedomains_am33xx[] __initdata = { - &am33xx_voltdm_mpu, - &am33xx_voltdm_core, - &am33xx_voltdm_rtc, - NULL, -}; - -void __init am33xx_voltagedomains_init(void) -{ - voltdm_init(voltagedomains_am33xx); -} diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c new file mode 100644 index 00000000000..33d22b87252 --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c @@ -0,0 +1,92 @@ +/* + * OMAP5 Voltage Management Routines + * + * Based on voltagedomains44xx_data.c + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/init.h> + +#include "common.h" + +#include "prm54xx.h" +#include "voltage.h" +#include "omap_opp_data.h" +#include "vc.h" +#include "vp.h" + +static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = { + .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET, +}; + +static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = { + .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET, +}; + +static const struct omap_vfsm_instance omap5_vdd_core_vfsm = { + .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET, +}; + +static struct voltagedomain omap5_voltdm_mpu = { + .name = "mpu", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_mpu, + .vfsm = &omap5_vdd_mpu_vfsm, + .vp = &omap4_vp_mpu, +}; + +static struct voltagedomain omap5_voltdm_mm = { + .name = "mm", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_iva, + .vfsm = &omap5_vdd_mm_vfsm, + .vp = &omap4_vp_iva, +}; + +static struct voltagedomain omap5_voltdm_core = { + .name = "core", + .scalable = true, + .read = omap4_prm_vcvp_read, + .write = omap4_prm_vcvp_write, + .rmw = omap4_prm_vcvp_rmw, + .vc = &omap4_vc_core, + .vfsm = &omap5_vdd_core_vfsm, + .vp = &omap4_vp_core, +}; + +static struct voltagedomain omap5_voltdm_wkup = { + .name = "wkup", +}; + +static struct voltagedomain *voltagedomains_omap5[] __initdata = { + &omap5_voltdm_mpu, + &omap5_voltdm_mm, + &omap5_voltdm_core, + &omap5_voltdm_wkup, + NULL, +}; + +static const char *sys_clk_name __initdata = "sys_clkin"; + +void __init omap54xx_voltagedomains_init(void) +{ + struct voltagedomain *voltdm; + int i; + + for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++) + voltdm->sys_clk.name = sys_clk_name; + + voltdm_init(voltagedomains_omap5); +}; diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig index 13bae78b215..b1022f4315f 100644 --- a/arch/arm/mach-picoxcell/Kconfig +++ b/arch/arm/mach-picoxcell/Kconfig @@ -4,7 +4,6 @@ config ARCH_PICOXCELL select ARM_PATCH_PHYS_VIRT select ARM_VIC select CPU_V6K - select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select HAVE_TCM diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index 70b441ad1d1..b13f51bc35c 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -8,20 +8,13 @@ * All enquiries to support@picochip.com */ #include <linux/delay.h> -#include <linux/irq.h> -#include <linux/irqchip.h> -#include <linux/irqdomain.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/dw_apb_timer.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include "common.h" - #define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000) #define PICOXCELL_PERIPH_BASE 0x80000000 #define PICOXCELL_PERIPH_LENGTH SZ_4M @@ -86,9 +79,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd) DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .map_io = picoxcell_map_io, - .nr_irqs = NR_IRQS_LEGACY, - .init_irq = irqchip_init, - .init_time = dw_apb_timer_init, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, .restart = picoxcell_wdt_restart, diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h deleted file mode 100644 index 481b42a4ef1..00000000000 --- a/arch/arm/mach-picoxcell/common.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2011 Picochip Ltd., Jamie Iles - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * All enquiries to support@picochip.com - */ -#ifndef __PICOXCELL_COMMON_H__ -#define __PICOXCELL_COMMON_H__ - -#include <asm/mach/time.h> - -extern void dw_apb_timer_init(void); - -#endif /* __PICOXCELL_COMMON_H__ */ diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 4f94cd87972..2c70f74fed5 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -9,7 +9,6 @@ #include <linux/clocksource.h> #include <linux/init.h> #include <linux/kernel.h> -#include <linux/irqchip.h> #include <asm/sizes.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -17,16 +16,6 @@ #include <linux/of_platform.h> #include "common.h" -static struct of_device_id sirfsoc_of_bus_ids[] __initdata = { - { .compatible = "simple-bus", }, - {}, -}; - -void __init sirfsoc_mach_init(void) -{ - of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL); -} - void __init sirfsoc_init_late(void) { sirfsoc_pm_init(); @@ -55,9 +44,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .nr_irqs = 128, .map_io = sirfsoc_map_io, - .init_irq = irqchip_init, .init_time = sirfsoc_init_time, - .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = atlas6_dt_match, .restart = sirfsoc_restart, @@ -66,18 +53,16 @@ MACHINE_END #ifdef CONFIG_ARCH_PRIMA2 static const char *prima2_dt_match[] __initdata = { - "sirf,prima2", - NULL + "sirf,prima2", + NULL }; DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .nr_irqs = 128, .map_io = sirfsoc_map_io, - .init_irq = irqchip_init, .init_time = sirfsoc_init_time, .dma_zone_size = SZ_256M, - .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = prima2_dt_match, .restart = sirfsoc_restart, @@ -94,9 +79,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ .smp = smp_ops(sirfsoc_smp_ops), .map_io = sirfsoc_map_io, - .init_irq = irqchip_init, .init_time = sirfsoc_init_time, - .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, .dt_compat = marco_dt_match, .restart = sirfsoc_restart, diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index 8f595c0cc8d..02cc34388b0 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c @@ -9,7 +9,7 @@ #include <linux/kernel.h> #include <linux/suspend.h> #include <linux/slab.h> -#include <linux/module.h> +#include <linux/export.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig new file mode 100644 index 00000000000..25ee12b21f0 --- /dev/null +++ b/arch/arm/mach-rockchip/Kconfig @@ -0,0 +1,16 @@ +config ARCH_ROCKCHIP + bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7 + select PINCTRL + select PINCTRL_ROCKCHIP + select ARCH_REQUIRE_GPIOLIB + select ARM_GIC + select CACHE_L2X0 + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP + select LOCAL_TIMERS if SMP + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select DW_APB_TIMER_OF + help + Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs + containing the RK2928, RK30xx and RK31xx series. diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile new file mode 100644 index 00000000000..1547d4fc920 --- /dev/null +++ b/arch/arm/mach-rockchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c new file mode 100644 index 00000000000..724d2d81f97 --- /dev/null +++ b/arch/arm/mach-rockchip/rockchip.c @@ -0,0 +1,52 @@ +/* + * Device Tree support for Rockchip SoCs + * + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/irqchip.h> +#include <linux/dw_apb_timer.h> +#include <linux/clk-provider.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +static void __init rockchip_timer_init(void) +{ + of_clk_init(NULL); + clocksource_of_init(); +} + +static void __init rockchip_dt_init(void) +{ + l2x0_of_init(0, ~0UL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const rockchip_board_dt_compat[] = { + "rockchip,rk2928", + "rockchip,rk3066a", + "rockchip,rk3066b", + "rockchip,rk3188", + NULL, +}; + +DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") + .init_machine = rockchip_dt_init, + .init_time = rockchip_timer_init, + .dt_compat = rockchip_board_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index e52d5e42af4..0adb2b85f83 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -31,6 +31,7 @@ config CPU_S3C2410 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX select S3C2410_PM if PM select SAMSUNG_HRT + select SAMSUNG_WDT_RESET help Support for S3C2410 and S3C2410A family from the S3C24XX line of Samsung Mobile CPUs. @@ -81,6 +82,7 @@ config CPU_S3C2442 config CPU_S3C244X def_bool y depends on CPU_S3C2440 || CPU_S3C2442 + select SAMSUNG_WDT_RESET config CPU_S3C2443 bool "SAMSUNG S3C2443" diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c index ab1700ec8e6..b7e09467152 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = { [DMACH_XD0] = { .name = "xdreq0", .channels = MAP(S3C2412_DMAREQSEL_XDREQ0), - .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0), }, [DMACH_XD1] = { .name = "xdreq1", .channels = MAP(S3C2412_DMAREQSEL_XDREQ1), - .channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1), }, [DMACH_SDI] = { .name = "sdi", .channels = MAP(S3C2412_DMAREQSEL_SDI), - .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), }, - [DMACH_SPI0] = { - .name = "spi0", + [DMACH_SPI0_RX] = { + .name = "spi0-rx", + .channels = MAP(S3C2412_DMAREQSEL_SPI0RX), + }, + [DMACH_SPI0_TX] = { + .name = "spi0-tx", .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), - .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), }, - [DMACH_SPI1] = { - .name = "spi1", + [DMACH_SPI1_RX] = { + .name = "spi1-rx", + .channels = MAP(S3C2412_DMAREQSEL_SPI1RX), + }, + [DMACH_SPI1_TX] = { + .name = "spi1-tx", .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), - .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), }, [DMACH_UART0] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), }, [DMACH_UART1] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), }, [DMACH_UART2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_0), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), }, [DMACH_UART0_SRC2] = { .name = "uart0", .channels = MAP(S3C2412_DMAREQSEL_UART0_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), }, [DMACH_UART1_SRC2] = { .name = "uart1", .channels = MAP(S3C2412_DMAREQSEL_UART1_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), }, [DMACH_UART2_SRC2] = { .name = "uart2", .channels = MAP(S3C2412_DMAREQSEL_UART2_1), - .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), }, [DMACH_TIMER] = { .name = "timer", .channels = MAP(S3C2412_DMAREQSEL_TIMER), - .channels_rx = MAP(S3C2412_DMAREQSEL_TIMER), }, [DMACH_I2S_IN] = { .name = "i2s-sdi", .channels = MAP(S3C2412_DMAREQSEL_I2SRX), - .channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX), }, [DMACH_I2S_OUT] = { .name = "i2s-sdo", .channels = MAP(S3C2412_DMAREQSEL_I2STX), - .channels_rx = MAP(S3C2412_DMAREQSEL_I2STX), }, [DMACH_USB_EP1] = { .name = "usb-ep1", .channels = MAP(S3C2412_DMAREQSEL_USBEP1), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1), }, [DMACH_USB_EP2] = { .name = "usb-ep2", .channels = MAP(S3C2412_DMAREQSEL_USBEP2), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2), }, [DMACH_USB_EP3] = { .name = "usb-ep3", .channels = MAP(S3C2412_DMAREQSEL_USBEP3), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3), }, [DMACH_USB_EP4] = { .name = "usb-ep4", .channels = MAP(S3C2412_DMAREQSEL_USBEP4), - .channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4), }, }; -static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map, - enum dma_data_direction dir) -{ - unsigned long chsel; - - if (dir == DMA_FROM_DEVICE) - chsel = map->channels_rx[0]; - else - chsel = map->channels[0]; - - chsel &= ~DMA_CH_VALID; - chsel |= S3C2412_DMAREQSEL_HW; - - writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL); -} - static void s3c2412_dma_select(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map) { - s3c2412_dma_direction(chan, map, chan->source); + unsigned long chsel = map->channels[0] & (~DMA_CH_VALID); + writel(chsel | S3C2412_DMAREQSEL_HW, + chan->regs + S3C2412_DMA_DMAREQSEL); } static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .select = s3c2412_dma_select, - .direction = s3c2412_dma_direction, .dcon_mask = 0, .map = s3c2412_dma_mappings, .map_size = ARRAY_SIZE(s3c2412_dma_mappings), diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index 5fe3539dc2b..95b9f759fe9 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = { static void s3c2443_dma_select(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map) { - writel(map->channels[0] | S3C2443_DMAREQSEL_HW, + unsigned long chsel = map->channels[0] & (~DMA_CH_VALID); + writel(chsel | S3C2443_DMAREQSEL_HW, chan->regs + S3C2443_DMA_DMAREQSEL); } diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c index aab64909e9a..4a65cba3295 100644 --- a/arch/arm/mach-s3c24xx/dma.c +++ b/arch/arm/mach-s3c24xx/dma.c @@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel, return -EINVAL; } - if (dma_sel.direction != NULL) - (dma_sel.direction)(chan, chan->map, source); - return 0; } diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h index 8b283f847da..7d2ce205dce 100644 --- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h +++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h @@ -49,6 +49,9 @@ static void arch_detect_cpu(void) fifo_mask = S3C2410_UFSTAT_TXMASK; fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; } + + uart_base = (volatile u8 *) S3C_PA_UART + + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c index d850ea5adac..ff384acc65b 100644 --- a/arch/arm/mach-s3c24xx/s3c2410.c +++ b/arch/arm/mach-s3c24xx/s3c2410.c @@ -138,6 +138,7 @@ void __init s3c2410_init_clocks(int xtal) s3c2410_baseclk_add(); s3c24xx_register_clock(&s3c2410_armclk); clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); + samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); } struct bus_type s3c2410_subsys = { @@ -201,7 +202,7 @@ void s3c2410_restart(char mode, const char *cmd) soft_restart(0); } - arch_wdt_reset(); + samsung_wdt_reset(); /* we'll take a jump through zero as a poor second */ soft_restart(0); diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index 2a35edb6735..d0423e2544c 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c @@ -133,6 +133,7 @@ void __init s3c244x_init_clocks(int xtal) s3c24xx_register_baseclocks(xtal); s3c244x_setup_clocks(); s3c2410_baseclk_add(); + samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); } /* Since the S3C2442 and S3C2440 share items, put both subsystems here */ @@ -202,7 +203,7 @@ void s3c244x_restart(char mode, const char *cmd) if (mode == 's') soft_restart(0); - arch_wdt_reset(); + samsung_wdt_reset(); /* we'll take a jump through zero as a poor second */ soft_restart(0); diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index 0b9c0ba4483..1aed6f4be1c 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -183,6 +183,12 @@ core_initcall(s3c64xx_dev_init); void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { + /* + * FIXME: there is no better place to put this at the moment + * (samsung_wdt_reset_init needs clocks) + */ + samsung_wdt_reset_init(S3C_VA_WATCHDOG); + printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ @@ -378,7 +384,7 @@ arch_initcall(s3c64xx_init_irq_eint); void s3c64xx_restart(char mode, const char *cmd) { if (mode != 's') - arch_wdt_reset(); + samsung_wdt_reset(); /* if all else fails, or mode was for soft, jump to 0 */ soft_restart(0); diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h index c6a82a20bf2..1c956738b42 100644 --- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h +++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h @@ -23,6 +23,9 @@ static void arch_detect_cpu(void) /* we do not need to do any cpu detection here at the moment. */ fifo_mask = S3C2440_UFSTAT_TXMASK; fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; + + uart_base = (volatile u8 *)S3C_PA_UART + + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c index 8ae5800e807..76d0053bf56 100644 --- a/arch/arm/mach-s5p64x0/common.c +++ b/arch/arm/mach-s5p64x0/common.c @@ -173,6 +173,8 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size) s5p_init_cpu(S5P64X0_SYS_ID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); + samsung_wdt_reset_init(S3C_VA_WATCHDOG); + } void __init s5p6440_map_io(void) @@ -440,7 +442,7 @@ arch_initcall(s5p64x0_init_irq_eint); void s5p64x0_restart(char mode, const char *cmd) { if (mode != 's') - arch_wdt_reset(); + samsung_wdt_reset(); soft_restart(0); } diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h index 19e0d64d78c..bbcc3f669ee 100644 --- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h +++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h @@ -14,171 +14,21 @@ #define __ASM_ARCH_UNCOMPRESS_H #include <mach/map.h> +#include <plat/uncompress.h> -/* - * cannot use commonly <plat/uncompress.h> - * because uart base of S5P6440 and S5P6450 is different - */ - -typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ - -/* uart setup */ - -unsigned int fifo_mask; -unsigned int fifo_max; - -/* forward declerations */ - -static void arch_detect_cpu(void); - -/* defines for UART registers */ - -#include <plat/regs-serial.h> -#include <plat/regs-watchdog.h> - -/* working in physical space... */ -#undef S3C2410_WDOGREG -#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) - -/* how many bytes we allow into the FIFO at a time in FIFO mode */ -#define FIFO_MAX (14) - -unsigned long uart_base; - -static __inline__ void get_uart_base(void) +static void arch_detect_cpu(void) { unsigned int chipid; chipid = *(const volatile unsigned int __force *) 0xE0100118; - uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT; - if ((chipid & 0xff000) == 0x50000) - uart_base += 0xEC800000; + uart_base = (volatile u8 *)S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); else - uart_base += 0xEC000000; -} - -static __inline__ void uart_wr(unsigned int reg, unsigned int val) -{ - volatile unsigned int *ptr; - - get_uart_base(); - ptr = (volatile unsigned int *)(reg + uart_base); - *ptr = val; -} - -static __inline__ unsigned int uart_rd(unsigned int reg) -{ - volatile unsigned int *ptr; - - get_uart_base(); - ptr = (volatile unsigned int *)(reg + uart_base); - return *ptr; -} - -/* - * we can deal with the case the UARTs are being run - * in FIFO mode, so that we don't hold up our execution - * waiting for tx to happen... - */ - -static void putc(int ch) -{ - if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { - int level; - - while (1) { - level = uart_rd(S3C2410_UFSTAT); - level &= fifo_mask; - - if (level < fifo_max) - break; - } - - } else { - /* not using fifos */ - - while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE) - barrier(); - } + uart_base = (volatile u8 *)S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); - /* write byte to transmission register */ - uart_wr(S3C2410_UTXH, ch); -} - -static inline void flush(void) -{ -} - -#define __raw_writel(d, ad) \ - do { \ - *((volatile unsigned int __force *)(ad)) = (d); \ - } while (0) - - -#ifdef CONFIG_S3C_BOOT_ERROR_RESET - -static void arch_decomp_error(const char *x) -{ - putstr("\n\n"); - putstr(x); - putstr("\n\n -- System resetting\n"); - - __raw_writel(0x4000, S3C2410_WTDAT); - __raw_writel(0x4000, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); - - while(1); -} - -#define arch_error arch_decomp_error -#endif - -#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO -static inline void arch_enable_uart_fifo(void) -{ - u32 fifocon = uart_rd(S3C2410_UFCON); - - if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { - fifocon |= S3C2410_UFCON_RESETBOTH; - uart_wr(S3C2410_UFCON, fifocon); - - /* wait for fifo reset to complete */ - while (1) { - fifocon = uart_rd(S3C2410_UFCON); - if (!(fifocon & S3C2410_UFCON_RESETBOTH)) - break; - } - } -} -#else -#define arch_enable_uart_fifo() do { } while(0) -#endif - -static void arch_decomp_setup(void) -{ - /* - * we may need to setup the uart(s) here if we are not running - * on an BAST... the BAST will have left the uarts configured - * after calling linux. - */ - - arch_detect_cpu(); - - /* - * Enable the UART FIFOs if they where not enabled and our - * configuration says we should turn them on. - */ - - arch_enable_uart_fifo(); -} - - - -static void arch_detect_cpu(void) -{ - /* we do not need to do any cpu detection here at the moment. */ + fifo_mask = S3C2440_UFSTAT_TXMASK; + fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c index cc6e561c995..511031564d3 100644 --- a/arch/arm/mach-s5pc100/common.c +++ b/arch/arm/mach-s5pc100/common.c @@ -178,6 +178,7 @@ void __init s5pc100_init_clocks(int xtal) s5p_register_clocks(xtal); s5pc100_register_clocks(); s5pc100_setup_clocks(); + samsung_wdt_reset_init(S3C_VA_WATCHDOG); } void __init s5pc100_init_irq(void) @@ -219,7 +220,7 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no) void s5pc100_restart(char mode, const char *cmd) { if (mode != 's') - arch_wdt_reset(); + samsung_wdt_reset(); soft_restart(0); } diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h index 01ccf535e76..720e1339425 100644 --- a/arch/arm/mach-s5pc100/include/mach/uncompress.h +++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h @@ -23,6 +23,8 @@ static void arch_detect_cpu(void) /* we do not need to do any cpu detection here at the moment. */ fifo_mask = S3C2440_UFSTAT_TXMASK; fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; + + uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h index ef977ea8546..231cb07de05 100644 --- a/arch/arm/mach-s5pv210/include/mach/uncompress.h +++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h @@ -21,6 +21,8 @@ static void arch_detect_cpu(void) /* we do not need to do any cpu detection here at the moment. */ fifo_mask = S5PV210_UFSTAT_TXMASK; fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT; + + uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT); } #endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index c6fb9ec8d15..db27e8eef19 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -36,10 +36,13 @@ config ARCH_R8A7740 select RENESAS_INTC_IRQPIN config ARCH_R8A7778 - bool "R-Car M1 (R8A77780)" + bool "R-Car M1A (R8A77781)" + select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_V7 select SH_CLK_CPG select ARM_GIC + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" @@ -68,27 +71,6 @@ config ARCH_EMEV2 comment "SH-Mobile Board Type" -config MACH_AP4EVB - bool "AP4EVB board" - depends on ARCH_SH7372 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select SH_LCD_MIPI_DSI - select SND_SOC_AK4642 if SND_SIMPLE_CARD - -choice - prompt "AP4EVB LCD panel selection" - default AP4EVB_QHD - depends on MACH_AP4EVB - -config AP4EVB_QHD - bool "MIPI-DSI QHD (960x540)" - -config AP4EVB_WVGA - bool "Parallel WVGA (800x480)" - -endchoice - config MACH_AG5EVM bool "AG5EVM board" depends on ARCH_SH73A0 @@ -115,12 +97,6 @@ config MACH_KOTA2 select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR -config MACH_BONITO - bool "bonito board" - depends on ARCH_R8A7740 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - config MACH_ARMADILLO800EVA bool "Armadillo-800 EVA board" depends on ARCH_R8A7740 @@ -183,6 +159,8 @@ config MACH_KZM9D config MACH_KZM9G bool "KZM-A9-GT board" depends on ARCH_SH73A0 + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR select SND_SOC_AK4642 if SND_SIMPLE_CARD @@ -208,37 +186,6 @@ config CPU_HAS_INTEVT bool default y -menu "Memory configuration" - -config MEMORY_START - hex "Physical memory start address" - default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \ - MACH_MACKEREL || MACH_BONITO || \ - MACH_ARMADILLO800EVA || MACH_APE6EVM || \ - MACH_LAGER - default "0x41000000" if MACH_KOTA2 - default "0x00000000" - ---help--- - Tweak this only when porting to a new machine which does not - already have a defconfig. Changing it from the known correct - value on any of the known systems will only lead to disaster. - -config MEMORY_SIZE - hex "Physical memory size" - default "0x80000000" if MACH_LAGER - default "0x40000000" if MACH_APE6EVM - default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \ - MACH_ARMADILLO800EVA - default "0x1e000000" if MACH_KOTA2 - default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL - default "0x04000000" - help - This sets the default memory size assumed by your kernel. It can - be overridden as normal by the 'mem=' argument on the kernel command - line. - -endmenu - menu "Timer and clock configuration" config SHMOBILE_TIMER_HZ diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 812de045230..6165a517f58 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -35,12 +35,10 @@ obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o # Board objects -obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_KOTA2) += board-kota2.o -obj-$(CONFIG_MACH_BONITO) += board-bonito.o obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 498efd99338..84c6868580f 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -1,6 +1,20 @@ -__ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ - $$[$(CONFIG_MEMORY_START) + 0x8000]') +# per-board load address for uImage +loadaddr-y := +loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000 +loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 +loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 +loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 +loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 +loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 +loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 +loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 +loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 +loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 +loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 +loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 +loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000 +__ZRELADDR := $(sort $(loadaddr-y)) zreladdr-y += $(__ZRELADDR) # Unsupported legacy stuff diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c deleted file mode 100644 index 45f78cadec1..00000000000 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ /dev/null @@ -1,1332 +0,0 @@ -/* - * AP4EVB board support - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <linux/clk.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/mfd/tmio.h> -#include <linux/mmc/host.h> -#include <linux/mmc/sh_mobile_sdhi.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/mmc/sh_mmcif.h> -#include <linux/i2c.h> -#include <linux/i2c/tsc2007.h> -#include <linux/io.h> -#include <linux/pinctrl/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/smsc911x.h> -#include <linux/sh_intc.h> -#include <linux/sh_clk.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/leds.h> -#include <linux/input/sh_keysc.h> -#include <linux/usb/r8a66597.h> -#include <linux/pm_clock.h> -#include <linux/dma-mapping.h> - -#include <media/sh_mobile_ceu.h> -#include <media/sh_mobile_csi2.h> -#include <media/soc_camera.h> - -#include <sound/sh_fsi.h> -#include <sound/simple_card.h> - -#include <video/sh_mobile_hdmi.h> -#include <video/sh_mobile_lcdc.h> -#include <video/sh_mipi_dsi.h> - -#include <mach/common.h> -#include <mach/irqs.h> -#include <mach/sh7372.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/setup.h> - -#include "sh-gpio.h" - -/* - * Address Interface BusWidth note - * ------------------------------------------------------------------ - * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON - * 0x0800_0000 user area - - * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF - * 0x1400_0000 Ether (LAN9220) 16bit - * 0x1600_0000 user area - cannot use with NAND - * 0x1800_0000 user area - - * 0x1A00_0000 - - * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit - */ - -/* - * NOR Flash ROM - * - * SW1 | SW2 | SW7 | NOR Flash ROM - * bit1 | bit1 bit2 | bit1 | Memory allocation - * ------+------------+------+------------------ - * OFF | ON OFF | ON | Area 0 - * OFF | ON OFF | OFF | Area 4 - */ - -/* - * NAND Flash ROM - * - * SW1 | SW2 | SW7 | NAND Flash ROM - * bit1 | bit1 bit2 | bit2 | Memory allocation - * ------+------------+------+------------------ - * OFF | ON OFF | ON | FCE 0 - * OFF | ON OFF | OFF | FCE 1 - */ - -/* - * SMSC 9220 - * - * SW1 SMSC 9220 - * ----------------------- - * ON access disable - * OFF access enable - */ - -/* - * LCD / IRQ / KEYSC / IrDA - * - * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen) - * LCD = 2nd LCDC (WVGA) - * - * | SW43 | - * SW3 | ON | OFF | - * -------------+-----------------------+---------------+ - * ON | KEY / IrDA | LCD | - * OFF | KEY / IrDA / IRQ | IRQ | - * - * - * QHD / WVGA display - * - * You can choice display type on menuconfig. - * Then, check above dip-switch. - */ - -/* - * USB - * - * J7 : 1-2 MAX3355E VBUS - * 2-3 DC 5.0V - * - * S39: bit2: off - */ - -/* - * FSI/FSMI - * - * SW41 : ON : SH-Mobile AP4 Audio Mode - * : OFF : Bluetooth Audio Mode - * - * it needs amixer settings for playing - * - * amixer set "Headphone Enable" on - */ - -/* - * MMC0/SDHI1 (CN7) - * - * J22 : select card voltage - * 1-2 pin : 1.8v - * 2-3 pin : 3.3v - * - * SW1 | SW33 - * | bit1 | bit2 | bit3 | bit4 - * ------------+------+------+------+------- - * MMC0 OFF | OFF | ON | ON | X - * SDHI1 OFF | ON | X | OFF | ON - * - * voltage lebel - * CN7 : 1.8v - * CN12: 3.3v - */ - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply fixed1v8_power_consumers[] = -{ - /* J22 default position: 1.8V */ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), - REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), -}; - -static struct regulator_consumer_supply fixed3v3_power_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), -}; - -/* MTD */ -static struct mtd_partition nor_flash_partitions[] = { - { - .name = "loader", - .offset = 0x00000000, - .size = 512 * 1024, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "bootenv", - .offset = MTDPART_OFS_APPEND, - .size = 512 * 1024, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel_ro", - .offset = MTDPART_OFS_APPEND, - .size = 8 * 1024 * 1024, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 8 * 1024 * 1024, - }, - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct physmap_flash_data nor_flash_data = { - .width = 2, - .parts = nor_flash_partitions, - .nr_parts = ARRAY_SIZE(nor_flash_partitions), -}; - -static struct resource nor_flash_resources[] = { - [0] = { - .start = 0x20000000, /* CS0 shadow instead of regular CS0 */ - .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */ - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device nor_flash_device = { - .name = "physmap-flash", - .dev = { - .platform_data = &nor_flash_data, - }, - .num_resources = ARRAY_SIZE(nor_flash_resources), - .resource = nor_flash_resources, -}; - -/* SMSC 9220 */ -static struct resource smc911x_resources[] = { - { - .start = 0x14000000, - .end = 0x16000000 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = evt2irq(0x02c0) /* IRQ6A */, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device smc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smc911x_resources), - .resource = smc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -/* - * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO 41). - */ -static int slot_cn7_get_cd(struct platform_device *pdev) -{ - return !gpio_get_value(41); -} -/* MERAM */ -static struct sh_mobile_meram_info meram_info = { - .addr_mode = SH_MOBILE_MERAM_MODE1, -}; - -static struct resource meram_resources[] = { - [0] = { - .name = "regs", - .start = 0xe8000000, - .end = 0xe807ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "meram", - .start = 0xe8080000, - .end = 0xe81fffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device meram_device = { - .name = "sh_mobile_meram", - .id = 0, - .num_resources = ARRAY_SIZE(meram_resources), - .resource = meram_resources, - .dev = { - .platform_data = &meram_info, - }, -}; - -/* SH_MMCIF */ -static struct resource sh_mmcif_resources[] = { - [0] = { - .name = "MMCIF", - .start = 0xE6BD0000, - .end = 0xE6BD00FF, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* MMC ERR */ - .start = evt2irq(0x1ac0), - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* MMC NOR */ - .start = evt2irq(0x1ae0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct sh_mmcif_plat_data sh_mmcif_plat = { - .sup_pclk = 0, - .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, - .caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_8_BIT_DATA | - MMC_CAP_NEEDS_POLL, - .get_cd = slot_cn7_get_cd, - .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, - .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, -}; - -static struct platform_device sh_mmcif_device = { - .name = "sh_mmcif", - .id = 0, - .dev = { - .dma_mask = NULL, - .coherent_dma_mask = 0xffffffff, - .platform_data = &sh_mmcif_plat, - }, - .num_resources = ARRAY_SIZE(sh_mmcif_resources), - .resource = sh_mmcif_resources, -}; - -/* SDHI0 */ -static struct sh_mobile_sdhi_info sdhi0_info = { - .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, - .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, - .tmio_caps = MMC_CAP_SDIO_IRQ, -}; - -static struct resource sdhi0_resources[] = { - [0] = { - .name = "SDHI0", - .start = 0xe6850000, - .end = 0xe68500ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi0_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi0_resources), - .resource = sdhi0_resources, - .id = 0, - .dev = { - .platform_data = &sdhi0_info, - }, -}; - -/* SDHI1 */ -static struct sh_mobile_sdhi_info sdhi1_info = { - .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, - .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_ocr_mask = MMC_VDD_165_195, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, - .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ, - .get_cd = slot_cn7_get_cd, -}; - -static struct resource sdhi1_resources[] = { - [0] = { - .name = "SDHI1", - .start = 0xe6860000, - .end = 0xe68600ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */ - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi1_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi1_resources), - .resource = sdhi1_resources, - .id = 1, - .dev = { - .platform_data = &sdhi1_info, - }, -}; - -/* USB1 */ -static void usb1_host_port_power(int port, int power) -{ - if (!power) /* only power-on supported for now */ - return; - - /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ - __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008)); -} - -static struct r8a66597_platdata usb1_host_data = { - .on_chip = 1, - .port_power = usb1_host_port_power, -}; - -static struct resource usb1_host_resources[] = { - [0] = { - .name = "USBHS", - .start = 0xE68B0000, - .end = 0xE68B00E6 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usb1_host_device = { - .name = "r8a66597_hcd", - .id = 1, - .dev = { - .dma_mask = NULL, /* not use dma */ - .coherent_dma_mask = 0xffffffff, - .platform_data = &usb1_host_data, - }, - .num_resources = ARRAY_SIZE(usb1_host_resources), - .resource = usb1_host_resources, -}; - -/* - * QHD display - */ -#ifdef CONFIG_AP4EVB_QHD - -/* KEYSC (Needs SW43 set to ON) */ -static struct sh_keysc_info keysc_info = { - .mode = SH_KEYSC_MODE_1, - .scan_timing = 3, - .delay = 2500, - .keycodes = { - KEY_0, KEY_1, KEY_2, KEY_3, KEY_4, - KEY_5, KEY_6, KEY_7, KEY_8, KEY_9, - KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, - KEY_F, KEY_G, KEY_H, KEY_I, KEY_J, - KEY_K, KEY_L, KEY_M, KEY_N, KEY_O, - }, -}; - -static struct resource keysc_resources[] = { - [0] = { - .name = "KEYSC", - .start = 0xe61b0000, - .end = 0xe61b0063, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x0be0), /* KEYSC_KEY */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device keysc_device = { - .name = "sh_keysc", - .id = 0, /* "keysc0" clock */ - .num_resources = ARRAY_SIZE(keysc_resources), - .resource = keysc_resources, - .dev = { - .platform_data = &keysc_info, - }, -}; - -/* MIPI-DSI */ -static int sh_mipi_set_dot_clock(struct platform_device *pdev, - void __iomem *base, - int enable) -{ - struct clk *pck = clk_get(&pdev->dev, "dsip_clk"); - - if (IS_ERR(pck)) - return PTR_ERR(pck); - - if (enable) { - /* - * DSIPCLK = 24MHz - * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl) - * HsByteCLK = D-PHY/8 = 39MHz - * - * X * Y * FPS = - * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz - */ - clk_set_rate(pck, clk_round_rate(pck, 24000000)); - clk_enable(pck); - } else { - clk_disable(pck); - } - - clk_put(pck); - - return 0; -} - -static struct resource mipidsi0_resources[] = { - [0] = { - .start = 0xffc60000, - .end = 0xffc63073, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xffc68000, - .end = 0xffc680ef, - .flags = IORESOURCE_MEM, - }, -}; - -static struct sh_mipi_dsi_info mipidsi0_info = { - .data_format = MIPI_RGB888, - .channel = LCDC_CHAN_MAINLCD, - .lane = 2, - .vsynw_offset = 17, - .phyctrl = 0x6 << 8, - .flags = SH_MIPI_DSI_SYNC_PULSES_MODE | - SH_MIPI_DSI_HSbyteCLK, - .set_dot_clock = sh_mipi_set_dot_clock, -}; - -static struct platform_device mipidsi0_device = { - .name = "sh-mipi-dsi", - .num_resources = ARRAY_SIZE(mipidsi0_resources), - .resource = mipidsi0_resources, - .id = 0, - .dev = { - .platform_data = &mipidsi0_info, - }, -}; - -static struct platform_device *qhd_devices[] __initdata = { - &mipidsi0_device, - &keysc_device, -}; -#endif /* CONFIG_AP4EVB_QHD */ - -/* LCDC0 */ -static const struct fb_videomode ap4evb_lcdc_modes[] = { - { -#ifdef CONFIG_AP4EVB_QHD - .name = "R63302(QHD)", - .xres = 544, - .yres = 961, - .left_margin = 72, - .right_margin = 600, - .hsync_len = 16, - .upper_margin = 8, - .lower_margin = 8, - .vsync_len = 2, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, -#else - .name = "WVGA Panel", - .xres = 800, - .yres = 480, - .left_margin = 220, - .right_margin = 110, - .hsync_len = 70, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .sync = 0, -#endif - }, -}; - -static const struct sh_mobile_meram_cfg lcd_meram_cfg = { - .icb[0] = { - .meram_size = 0x40, - }, - .icb[1] = { - .meram_size = 0x40, - }, -}; - -static struct sh_mobile_lcdc_info lcdc_info = { - .meram_dev = &meram_info, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .lcd_modes = ap4evb_lcdc_modes, - .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes), - .meram_cfg = &lcd_meram_cfg, -#ifdef CONFIG_AP4EVB_QHD - .tx_dev = &mipidsi0_device, -#endif - } -}; - -static struct resource lcdc_resources[] = { - [0] = { - .name = "LCDC", - .start = 0xfe940000, /* P4-only space */ - .end = 0xfe943fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x580), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device lcdc_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(lcdc_resources), - .resource = lcdc_resources, - .dev = { - .platform_data = &lcdc_info, - .coherent_dma_mask = ~0, - }, -}; - -/* FSI */ -#define IRQ_FSI evt2irq(0x1840) -static struct sh_fsi_platform_info fsi_info = { - .port_b = { - .flags = SH_FSI_CLK_CPG | - SH_FSI_FMT_SPDIF, - }, -}; - -static struct resource fsi_resources[] = { - [0] = { - .name = "FSI", - .start = 0xFE3C0000, - .end = 0xFE3C0400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FSI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device fsi_device = { - .name = "sh_fsi2", - .id = -1, - .num_resources = ARRAY_SIZE(fsi_resources), - .resource = fsi_resources, - .dev = { - .platform_data = &fsi_info, - }, -}; - -static struct asoc_simple_card_info fsi2_ak4643_info = { - .name = "AK4643", - .card = "FSI2A-AK4643", - .codec = "ak4642-codec.0-0013", - .platform = "sh_fsi2", - .daifmt = SND_SOC_DAIFMT_LEFT_J, - .cpu_dai = { - .name = "fsia-dai", - .fmt = SND_SOC_DAIFMT_CBS_CFS, - }, - .codec_dai = { - .name = "ak4642-hifi", - .fmt = SND_SOC_DAIFMT_CBM_CFM, - .sysclk = 11289600, - }, -}; - -static struct platform_device fsi_ak4643_device = { - .name = "asoc-simple-card", - .dev = { - .platform_data = &fsi2_ak4643_info, - }, -}; - -/* LCDC1 */ -static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, - unsigned long *parent_freq); - -static struct sh_mobile_hdmi_info hdmi_info = { - .flags = HDMI_SND_SRC_SPDIF, - .clk_optimize_parent = ap4evb_clk_optimize, -}; - -static struct resource hdmi_resources[] = { - [0] = { - .name = "HDMI", - .start = 0xe6be0000, - .end = 0xe6be00ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ - .start = evt2irq(0x17e0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device hdmi_device = { - .name = "sh-mobile-hdmi", - .num_resources = ARRAY_SIZE(hdmi_resources), - .resource = hdmi_resources, - .id = -1, - .dev = { - .platform_data = &hdmi_info, - }, -}; - -static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, - unsigned long *parent_freq) -{ - struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); - long error; - - if (IS_ERR(hdmi_ick)) { - int ret = PTR_ERR(hdmi_ick); - pr_err("Cannot get HDMI ICK: %d\n", ret); - return ret; - } - - error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64); - - clk_put(hdmi_ick); - - return error; -} - -static const struct sh_mobile_meram_cfg hdmi_meram_cfg = { - .icb[0] = { - .meram_size = 0x100, - }, - .icb[1] = { - .meram_size = 0x100, - }, -}; - -static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { - .clock_source = LCDC_CLK_EXTERNAL, - .meram_dev = &meram_info, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .interface_type = RGB24, - .clock_divider = 1, - .flags = LCDC_FLAGS_DWPOL, - .meram_cfg = &hdmi_meram_cfg, - .tx_dev = &hdmi_device, - } -}; - -static struct resource lcdc1_resources[] = { - [0] = { - .name = "LCDC1", - .start = 0xfe944000, - .end = 0xfe947fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x1780), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device lcdc1_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(lcdc1_resources), - .resource = lcdc1_resources, - .id = 1, - .dev = { - .platform_data = &sh_mobile_lcdc1_info, - .coherent_dma_mask = ~0, - }, -}; - -static struct asoc_simple_card_info fsi2_hdmi_info = { - .name = "HDMI", - .card = "FSI2B-HDMI", - .codec = "sh-mobile-hdmi", - .platform = "sh_fsi2", - .cpu_dai = { - .name = "fsib-dai", - .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF, - }, - .codec_dai = { - .name = "sh_mobile_hdmi-hifi", - }, -}; - -static struct platform_device fsi_hdmi_device = { - .name = "asoc-simple-card", - .id = 1, - .dev = { - .platform_data = &fsi2_hdmi_info, - }, -}; - -static struct gpio_led ap4evb_leds[] = { - { - .name = "led4", - .gpio = 185, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "led2", - .gpio = 186, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "led3", - .gpio = 187, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "led1", - .gpio = 188, - .default_state = LEDS_GPIO_DEFSTATE_ON, - } -}; - -static struct gpio_led_platform_data ap4evb_leds_pdata = { - .num_leds = ARRAY_SIZE(ap4evb_leds), - .leds = ap4evb_leds, -}; - -static struct platform_device leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &ap4evb_leds_pdata, - }, -}; - -static struct i2c_board_info imx074_info = { - I2C_BOARD_INFO("imx074", 0x1a), -}; - -static struct soc_camera_link imx074_link = { - .bus_id = 0, - .board_info = &imx074_info, - .i2c_adapter_id = 0, - .module_name = "imx074", -}; - -static struct platform_device ap4evb_camera = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &imx074_link, - }, -}; - -static struct sh_csi2_client_config csi2_clients[] = { - { - .phy = SH_CSI2_PHY_MAIN, - .lanes = 0, /* default: 2 lanes */ - .channel = 0, - .pdev = &ap4evb_camera, - }, -}; - -static struct sh_csi2_pdata csi2_info = { - .type = SH_CSI2C, - .clients = csi2_clients, - .num_clients = ARRAY_SIZE(csi2_clients), - .flags = SH_CSI2_ECC | SH_CSI2_CRC, -}; - -static struct resource csi2_resources[] = { - [0] = { - .name = "CSI2", - .start = 0xffc90000, - .end = 0xffc90fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x17a0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct sh_mobile_ceu_companion csi2 = { - .id = 0, - .num_resources = ARRAY_SIZE(csi2_resources), - .resource = csi2_resources, - .platform_data = &csi2_info, -}; - -static struct sh_mobile_ceu_info sh_mobile_ceu_info = { - .flags = SH_CEU_FLAG_USE_8BIT_BUS, - .max_width = 8188, - .max_height = 8188, - .csi2 = &csi2, -}; - -static struct resource ceu_resources[] = { - [0] = { - .name = "CEU", - .start = 0xfe910000, - .end = 0xfe91009f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x880), - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* place holder for contiguous memory */ - }, -}; - -static struct platform_device ceu_device = { - .name = "sh_mobile_ceu", - .id = 0, /* "ceu0" clock */ - .num_resources = ARRAY_SIZE(ceu_resources), - .resource = ceu_resources, - .dev = { - .platform_data = &sh_mobile_ceu_info, - .coherent_dma_mask = 0xffffffff, - }, -}; - -static struct platform_device *ap4evb_devices[] __initdata = { - &leds_device, - &nor_flash_device, - &smc911x_device, - &sdhi0_device, - &sdhi1_device, - &usb1_host_device, - &fsi_device, - &fsi_ak4643_device, - &fsi_hdmi_device, - &sh_mmcif_device, - &hdmi_device, - &lcdc_device, - &lcdc1_device, - &ceu_device, - &ap4evb_camera, - &meram_device, -}; - -static void __init hdmi_init_pm_clock(void) -{ - struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); - int ret; - long rate; - - if (IS_ERR(hdmi_ick)) { - ret = PTR_ERR(hdmi_ick); - pr_err("Cannot get HDMI ICK: %d\n", ret); - goto out; - } - - ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); - if (ret < 0) { - pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount); - goto out; - } - - pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk)); - - rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); - if (rate < 0) { - pr_err("Cannot get suitable rate: %ld\n", rate); - ret = rate; - goto out; - } - - ret = clk_set_rate(&sh7372_pllc2_clk, rate); - if (ret < 0) { - pr_err("Cannot set rate %ld: %d\n", rate, ret); - goto out; - } - - pr_debug("PLLC2 set frequency %lu\n", rate); - - ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); - if (ret < 0) - pr_err("Cannot set HDMI parent: %d\n", ret); - -out: - if (!IS_ERR(hdmi_ick)) - clk_put(hdmi_ick); -} - -/* TouchScreen */ -#ifdef CONFIG_AP4EVB_QHD -# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 -# define GPIO_TSC_PORT 123 -#else /* WVGA */ -# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 -# define GPIO_TSC_PORT 40 -#endif - -#define IRQ28 evt2irq(0x3380) /* IRQ28A */ -#define IRQ7 evt2irq(0x02e0) /* IRQ7A */ -static int ts_get_pendown_state(void) -{ - int val; - - gpio_free(GPIO_TSC_IRQ); - - gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL); - - val = gpio_get_value(GPIO_TSC_PORT); - - gpio_request(GPIO_TSC_IRQ, NULL); - - return !val; -} - -static int ts_init(void) -{ - gpio_request(GPIO_TSC_IRQ, NULL); - - return 0; -} - -static struct tsc2007_platform_data tsc2007_info = { - .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = ts_get_pendown_state, - .init_platform_hw = ts_init, -}; - -static struct i2c_board_info tsc_device = { - I2C_BOARD_INFO("tsc2007", 0x48), - .type = "tsc2007", - .platform_data = &tsc2007_info, - /*.irq is selected on ap4evb_init */ -}; - -/* I2C */ -static struct i2c_board_info i2c0_devices[] = { - { - I2C_BOARD_INFO("ak4643", 0x13), - }, -}; - -static struct i2c_board_info i2c1_devices[] = { - { - I2C_BOARD_INFO("r2025sd", 0x32), - }, -}; - - -static const struct pinctrl_map ap4evb_pinctrl_map[] = { - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_ctrl_0", "mmc0"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_wp", "sdhi0"), - /* SDHI1 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_ctrl", "sdhi1"), -}; - -#define GPIO_PORT9CR IOMEM(0xE6051009) -#define GPIO_PORT10CR IOMEM(0xE605100A) -#define USCCR1 IOMEM(0xE6058144) -static void __init ap4evb_init(void) -{ - struct pm_domain_device domain_devices[] = { - { "A4LC", &lcdc1_device, }, - { "A4LC", &lcdc_device, }, - { "A4MP", &fsi_device, }, - { "A3SP", &sh_mmcif_device, }, - { "A3SP", &sdhi0_device, }, - { "A3SP", &sdhi1_device, }, - { "A4R", &ceu_device, }, - }; - u32 srcr4; - struct clk *clk; - - regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, - ARRAY_SIZE(fixed1v8_power_consumers), 1800000); - regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, - ARRAY_SIZE(fixed3v3_power_consumers), 3300000); - regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - /* External clock source */ - clk_set_rate(&sh7372_dv_clki_clk, 27000000); - - pinctrl_register_mappings(ap4evb_pinctrl_map, - ARRAY_SIZE(ap4evb_pinctrl_map)); - sh7372_pinmux_init(); - - /* enable SCIFA0 */ - gpio_request(GPIO_FN_SCIFA0_TXD, NULL); - gpio_request(GPIO_FN_SCIFA0_RXD, NULL); - - /* enable SMSC911X */ - gpio_request(GPIO_FN_CS5A, NULL); - gpio_request(GPIO_FN_IRQ6_39, NULL); - - /* enable Debug switch (S6) */ - gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); - - /* USB enable */ - gpio_request(GPIO_FN_VBUS0_1, NULL); - gpio_request(GPIO_FN_IDIN_1_18, NULL); - gpio_request(GPIO_FN_PWEN_1_115, NULL); - gpio_request(GPIO_FN_OVCN_1_114, NULL); - gpio_request(GPIO_FN_EXTLP_1, NULL); - gpio_request(GPIO_FN_OVCN2_1, NULL); - - /* setup USB phy */ - __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */ - - /* enable FSI2 port A (ak4643) */ - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAISLD, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ - - gpio_request(9, NULL); - gpio_request(10, NULL); - gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ - gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ - - /* card detect pin for MMC slot (CN7) */ - gpio_request_one(41, GPIOF_IN, NULL); - - /* setup FSI2 port B (HDMI) */ - gpio_request(GPIO_FN_FSIBCK, NULL); - __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ - - /* set SPU2 clock to 119.6 MHz */ - clk = clk_get(NULL, "spu_clk"); - if (!IS_ERR(clk)) { - clk_set_rate(clk, clk_round_rate(clk, 119600000)); - clk_put(clk); - } - - /* - * set irq priority, to avoid sound chopping - * when NFS rootfs is used - * FSI(3) > SMSC911X(2) - */ - intc_set_priority(IRQ_FSI, 3); - - i2c_register_board_info(0, i2c0_devices, - ARRAY_SIZE(i2c0_devices)); - - i2c_register_board_info(1, i2c1_devices, - ARRAY_SIZE(i2c1_devices)); - -#ifdef CONFIG_AP4EVB_QHD - - /* - * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and - * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON. - */ - - /* enable KEYSC */ - gpio_request(GPIO_FN_KEYOUT0, NULL); - gpio_request(GPIO_FN_KEYOUT1, NULL); - gpio_request(GPIO_FN_KEYOUT2, NULL); - gpio_request(GPIO_FN_KEYOUT3, NULL); - gpio_request(GPIO_FN_KEYOUT4, NULL); - gpio_request(GPIO_FN_KEYIN0_136, NULL); - gpio_request(GPIO_FN_KEYIN1_135, NULL); - gpio_request(GPIO_FN_KEYIN2_134, NULL); - gpio_request(GPIO_FN_KEYIN3_133, NULL); - gpio_request(GPIO_FN_KEYIN4, NULL); - - /* enable TouchScreen */ - irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); - - tsc_device.irq = IRQ28; - i2c_register_board_info(1, &tsc_device, 1); - - /* LCDC0 */ - lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; - lcdc_info.ch[0].interface_type = RGB24; - lcdc_info.ch[0].clock_divider = 1; - lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; - lcdc_info.ch[0].panel_cfg.width = 44; - lcdc_info.ch[0].panel_cfg.height = 79; - - platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices)); - -#else - /* - * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and - * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF. - */ - - gpio_request(GPIO_FN_LCDD17, NULL); - gpio_request(GPIO_FN_LCDD16, NULL); - gpio_request(GPIO_FN_LCDD15, NULL); - gpio_request(GPIO_FN_LCDD14, NULL); - gpio_request(GPIO_FN_LCDD13, NULL); - gpio_request(GPIO_FN_LCDD12, NULL); - gpio_request(GPIO_FN_LCDD11, NULL); - gpio_request(GPIO_FN_LCDD10, NULL); - gpio_request(GPIO_FN_LCDD9, NULL); - gpio_request(GPIO_FN_LCDD8, NULL); - gpio_request(GPIO_FN_LCDD7, NULL); - gpio_request(GPIO_FN_LCDD6, NULL); - gpio_request(GPIO_FN_LCDD5, NULL); - gpio_request(GPIO_FN_LCDD4, NULL); - gpio_request(GPIO_FN_LCDD3, NULL); - gpio_request(GPIO_FN_LCDD2, NULL); - gpio_request(GPIO_FN_LCDD1, NULL); - gpio_request(GPIO_FN_LCDD0, NULL); - gpio_request(GPIO_FN_LCDDISP, NULL); - gpio_request(GPIO_FN_LCDDCK, NULL); - - gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ - gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ - - lcdc_info.clock_source = LCDC_CLK_BUS; - lcdc_info.ch[0].interface_type = RGB18; - lcdc_info.ch[0].clock_divider = 3; - lcdc_info.ch[0].flags = 0; - lcdc_info.ch[0].panel_cfg.width = 152; - lcdc_info.ch[0].panel_cfg.height = 91; - - /* enable TouchScreen */ - irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); - - tsc_device.irq = IRQ7; - i2c_register_board_info(0, &tsc_device, 1); -#endif /* CONFIG_AP4EVB_QHD */ - - /* CEU */ - - /* - * TODO: reserve memory for V4L2 DMA buffers, when a suitable API - * becomes available - */ - - /* MIPI-CSI stuff */ - gpio_request(GPIO_FN_VIO_CKO, NULL); - - clk = clk_get(NULL, "vck1_clk"); - if (!IS_ERR(clk)) { - clk_set_rate(clk, clk_round_rate(clk, 13000000)); - clk_enable(clk); - clk_put(clk); - } - - sh7372_add_standard_devices(); - - /* HDMI */ - gpio_request(GPIO_FN_HDMI_HPD, NULL); - gpio_request(GPIO_FN_HDMI_CEC, NULL); - - /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ -#define SRCR4 IOMEM(0xe61580bc) - srcr4 = __raw_readl(SRCR4); - __raw_writel(srcr4 | (1 << 13), SRCR4); - udelay(50); - __raw_writel(srcr4 & ~(1 << 13), SRCR4); - - platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); - - rmobile_add_devices_to_domains(domain_devices, - ARRAY_SIZE(domain_devices)); - - hdmi_init_pm_clock(); - sh7372_pm_init(); - pm_clk_add(&fsi_device.dev, "spu2"); - pm_clk_add(&lcdc1_device.dev, "hdmi"); -} - -MACHINE_START(AP4EVB, "ap4evb") - .map_io = sh7372_map_io, - .init_early = sh7372_add_early_devices, - .init_irq = sh7372_init_irq, - .handle_irq = shmobile_handle_irq_intc, - .init_machine = ap4evb_init, - .init_late = sh7372_pm_init_late, - .init_time = sh7372_earlytimer_init, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 55b8c9fef95..5eb0caa6a7d 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -26,6 +26,7 @@ #include <linux/platform_device.h> #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> +#include <linux/sh_clk.h> #include <linux/smsc911x.h> #include <mach/common.h> #include <mach/irqs.h> @@ -65,7 +66,21 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = { static void __init ape6evm_add_standard_devices(void) { + + struct clk *parent; + struct clk *mp; + r8a73a4_clock_init(); + + /* MP clock parent = extal2 */ + parent = clk_get(NULL, "extal2"); + mp = clk_get(NULL, "mp"); + BUG_ON(IS_ERR(parent) || IS_ERR(mp)); + + clk_set_parent(mp, parent); + clk_put(parent); + clk_put(mp); + pinctrl_register_mappings(ape6evm_pinctrl_map, ARRAY_SIZE(ape6evm_pinctrl_map)); r8a73a4_pinmux_init(); diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index b85b2882dbd..44a621505ee 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = { static struct fixed_voltage_config vcc_sdhi0_info = { .supply_name = "SDHI0 Vcc", .microvolts = 3300000, - .gpio = GPIO_PORT75, + .gpio = 75, .enable_high = 1, .init_data = &vcc_sdhi0_init_data, }; @@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = { }; static struct gpio vccq_sdhi0_gpios[] = { - {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, + {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" }, }; static struct gpio_regulator_state vccq_sdhi0_states[] = { @@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = { static struct gpio_regulator_config vccq_sdhi0_info = { .supply_name = "vqmmc", - .enable_gpio = GPIO_PORT74, + .enable_gpio = 74, .enable_high = 1, .enabled_at_boot = 0, @@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = { static struct fixed_voltage_config vcc_sdhi1_info = { .supply_name = "SDHI1 Vcc", .microvolts = 3300000, - .gpio = GPIO_PORT16, + .gpio = 16, .enable_high = 1, .init_data = &vcc_sdhi1_init_data, }; @@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, - .cd_gpio = GPIO_PORT167, + .cd_gpio = 167, }; static struct resource sdhi0_resources[] = { @@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = { MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, /* Port72 cannot generate IRQs, will be used in polling mode. */ - .cd_gpio = GPIO_PORT72, + .cd_gpio = 72, }; static struct resource sdhi1_resources[] = { @@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = { }; static const struct pinctrl_map eva_pinctrl_map[] = { + /* CEU0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_data_0_7", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_clk_0", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_sync", "ceu0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740", + "ceu0_field", "ceu0"), + /* FSIA */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_mclk_out", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_data_in_1", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740", + "fsia_data_out_0", "fsia"), + /* FSIB */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740", + "fsib_mclk_in", "fsib"), + /* GETHER */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_mii", "gether"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740", + "gether_int", "gether"), + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740", + "hdmi", "hdmi"), /* LCD0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", "lcd0_data24_0", "lcd0"), @@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = { "mmc0_data8_1", "mmc0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", "mmc0_ctrl_1", "mmc0"), + /* SCIFA1 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", + "scifa1_data", "scifa1"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", "sdhi0_data4", "sdhi0"), @@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = { "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", "sdhi0_wp", "sdhi0"), + /* ST1232 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", + "intc_irq10", "intc"), + /* USBHS */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", + "intc_irq7_1", "intc"), }; static void __init eva_clock_init(void) @@ -1119,40 +1157,14 @@ static void __init eva_init(void) r8a7740_pinmux_init(); r8a7740_meram_workaround(); - /* SCIFA1 */ - gpio_request(GPIO_FN_SCIFA1_RXD, NULL); - gpio_request(GPIO_FN_SCIFA1_TXD, NULL); - /* LCDC0 */ - gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ /* Touchscreen */ - gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ + gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ /* GETHER */ - gpio_request(GPIO_FN_ET_CRS, NULL); - gpio_request(GPIO_FN_ET_MDC, NULL); - gpio_request(GPIO_FN_ET_MDIO, NULL); - gpio_request(GPIO_FN_ET_TX_ER, NULL); - gpio_request(GPIO_FN_ET_RX_ER, NULL); - gpio_request(GPIO_FN_ET_ERXD0, NULL); - gpio_request(GPIO_FN_ET_ERXD1, NULL); - gpio_request(GPIO_FN_ET_ERXD2, NULL); - gpio_request(GPIO_FN_ET_ERXD3, NULL); - gpio_request(GPIO_FN_ET_TX_CLK, NULL); - gpio_request(GPIO_FN_ET_TX_EN, NULL); - gpio_request(GPIO_FN_ET_ETXD0, NULL); - gpio_request(GPIO_FN_ET_ETXD1, NULL); - gpio_request(GPIO_FN_ET_ETXD2, NULL); - gpio_request(GPIO_FN_ET_ETXD3, NULL); - gpio_request(GPIO_FN_ET_PHY_INT, NULL); - gpio_request(GPIO_FN_ET_COL, NULL); - gpio_request(GPIO_FN_ET_RX_DV, NULL); - gpio_request(GPIO_FN_ET_RX_CLK, NULL); - gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ /* USB */ @@ -1163,34 +1175,17 @@ static void __init eva_init(void) } else { /* USB Func */ /* - * A1 chip has 2 IRQ7 pin and it was controled by MSEL register. - * OTOH, usbhs interrupt needs its value (HI/LOW) to decide - * USB connection/disconnection (usbhsf_get_vbus()). - * This means we needs to select GPIO_FN_IRQ7_PORT209 first, - * and select GPIO 209 here + * The USBHS interrupt handlers needs to read the IRQ pin value + * (HI/LOW) to diffentiate USB connection and disconnection + * events (usbhsf_get_vbus()). We thus need to select both the + * intc_irq7_1 pin group and GPIO 209 here. */ - gpio_request(GPIO_FN_IRQ7_PORT209, NULL); gpio_request_one(209, GPIOF_IN, NULL); platform_device_register(&usbhsf_device); usb = &usbhsf_device; } - /* CEU0 */ - gpio_request(GPIO_FN_VIO0_D7, NULL); - gpio_request(GPIO_FN_VIO0_D6, NULL); - gpio_request(GPIO_FN_VIO0_D5, NULL); - gpio_request(GPIO_FN_VIO0_D4, NULL); - gpio_request(GPIO_FN_VIO0_D3, NULL); - gpio_request(GPIO_FN_VIO0_D2, NULL); - gpio_request(GPIO_FN_VIO0_D1, NULL); - gpio_request(GPIO_FN_VIO0_D0, NULL); - gpio_request(GPIO_FN_VIO0_CLK, NULL); - gpio_request(GPIO_FN_VIO0_HD, NULL); - gpio_request(GPIO_FN_VIO0_VD, NULL); - gpio_request(GPIO_FN_VIO0_FIELD, NULL); - gpio_request(GPIO_FN_VIO_CKO, NULL); - /* CON1/CON15 Camera */ gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ @@ -1198,24 +1193,11 @@ static void __init eva_init(void) gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ /* FSI-WM8978 */ - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAOMC, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); - gpio_request(7, NULL); gpio_request(8, NULL); gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ - /* FSI-HDMI */ - gpio_request(GPIO_FN_FSIBCK, NULL); - - /* HDMI */ - gpio_request(GPIO_FN_HDMI_HPD, NULL); - gpio_request(GPIO_FN_HDMI_CEC, NULL); - /* * CAUTION * diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 38e5e50fb31..d5554646916 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -18,13 +18,52 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/mfd/tmio.h> +#include <linux/mmc/host.h> +#include <linux/mtd/partitions.h> +#include <linux/pinctrl/machine.h> #include <linux/platform_device.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> #include <linux/smsc911x.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> #include <mach/common.h> #include <mach/irqs.h> #include <mach/r8a7778.h> #include <asm/mach/arch.h> +/* + * CN9(Upper side) SCIF/RCAN selection + * + * 1,4 3,6 + * SW40 SCIF RCAN + * SW41 SCIF RCAN + */ + +/* + * MMC (CN26) pin + * + * SW6 (D2) 3 pin + * SW7 (D5) ON + * SW8 (D3) 3 pin + * SW10 (D4) 1 pin + * SW12 (CLK) 1 pin + * SW13 (D6) 3 pin + * SW14 (CMD) ON + * SW15 (D6) 1 pin + * SW16 (D0) ON + * SW17 (D1) ON + * SW18 (D7) 3 pin + * SW19 (MMC) 1 pin + */ + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + static struct smsc911x_platform_config smsc911x_data = { .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, @@ -37,17 +76,128 @@ static struct resource smsc911x_resources[] = { DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ }; +/* USB */ +static struct rcar_phy_platform_data usb_phy_platform_data __initdata; + +/* SDHI */ +static struct sh_mobile_sdhi_info sdhi0_info = { + .tmio_caps = MMC_CAP_SD_HIGHSPEED, + .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, +}; + +static struct sh_eth_plat_data ether_platform_data __initdata = { + .phy = 0x01, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_RCAR, + .phy_interface = PHY_INTERFACE_MODE_RMII, + /* + * Although the LINK signal is available on the board, it's connected to + * the link/activity LED output of the PHY, thus the link disappears and + * reappears after each packet. We'd be better off ignoring such signal + * and getting the link state from the PHY indirectly. + */ + .no_ether_link = 1, +}; + +/* I2C */ +static struct i2c_board_info i2c0_devices[] = { + { + I2C_BOARD_INFO("rx8581", 0x51), + }, +}; + +/* HSPI*/ +static struct mtd_partition m25p80_spi_flash_partitions[] = { + { + .name = "data(spi)", + .size = 0x0100000, + .offset = 0, + }, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .type = "s25fl008k", + .parts = m25p80_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions), +}; + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "m25p80", + .max_speed_hz = 104000000, + .chip_select = 0, + .bus_num = 0, + .mode = SPI_MODE_0, + .platform_data = &spi_flash_data, + }, +}; + +/* MMC */ +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0, + .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, + .caps = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NEEDS_POLL, +}; + +static const struct pinctrl_map bockw_pinctrl_map[] = { + /* Ether */ + PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", + "ether_rmii", "ether"), + /* HSPI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778", + "hspi0_a", "hspi0"), + /* MMC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778", + "mmc_data8", "mmc"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778", + "mmc_ctrl", "mmc"), + /* SCIF0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_data_a", "scif0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", + "scif0_ctrl", "scif0"), + /* USB */ + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", + "usb0", "usb0"), + PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", + "usb1", "usb1"), + /* SDHI0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", + "sdhi0", "sdhi0"), +}; + +#define FPGA 0x18200000 #define IRQ0MR 0x30 +#define PFC 0xfffc0000 +#define PUPR4 0x110 static void __init bockw_init(void) { - void __iomem *fpga; + void __iomem *base; r8a7778_clock_init(); r8a7778_init_irq_extpin(1); r8a7778_add_standard_devices(); + r8a7778_add_usb_phy_device(&usb_phy_platform_data); + r8a7778_add_ether_device(ðer_platform_data); + r8a7778_add_i2c_device(0); + r8a7778_add_hspi_device(0); + r8a7778_add_mmc_device(&sh_mmcif_plat); - fpga = ioremap_nocache(0x18200000, SZ_1M); - if (fpga) { + i2c_register_board_info(0, i2c0_devices, + ARRAY_SIZE(i2c0_devices)); + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + pinctrl_register_mappings(bockw_pinctrl_map, + ARRAY_SIZE(bockw_pinctrl_map)); + r8a7778_pinmux_init(); + + /* for SMSC */ + base = ioremap_nocache(FPGA, SZ_1M); + if (base) { /* * CAUTION * @@ -55,16 +205,33 @@ static void __init bockw_init(void) * it should be cared in the future * Now, it is assuming IRQ0 was used only from SMSC. */ - u16 val = ioread16(fpga + IRQ0MR); + u16 val = ioread16(base + IRQ0MR); val &= ~(1 << 4); /* enable SMSC911x */ - iowrite16(val, fpga + IRQ0MR); - iounmap(fpga); + iowrite16(val, base + IRQ0MR); + iounmap(base); + + regulator_register_fixed(0, dummy_supplies, + ARRAY_SIZE(dummy_supplies)); platform_device_register_resndata( &platform_bus, "smsc911x", -1, smsc911x_resources, ARRAY_SIZE(smsc911x_resources), &smsc911x_data, sizeof(smsc911x_data)); } + + /* for SDHI */ + base = ioremap_nocache(PFC, 0x200); + if (base) { + /* + * FIXME + * + * SDHI CD/WP pin needs pull-up + */ + iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4); + iounmap(base); + + r8a7778_sdhi_init(0, &sdhi0_info); + } } static const char *bockw_boards_compat_dt[] __initdata = { @@ -78,4 +245,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw") .init_machine = bockw_init, .init_time = shmobile_timer_init, .dt_compat = bockw_boards_compat_dt, + .init_late = r8a7778_init_late, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c deleted file mode 100644 index 70d992c540a..00000000000 --- a/arch/arm/mach-shmobile/board-bonito.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * bonito board support - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include <linux/kernel.h> -#include <linux/i2c.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/pinctrl/machine.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/smsc911x.h> -#include <linux/videodev2.h> -#include <mach/common.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <asm/hardware/cache-l2x0.h> -#include <mach/r8a7740.h> -#include <mach/irqs.h> -#include <video/sh_mobile_lcdc.h> - -/* - * CS Address device note - *---------------------------------------------------------------- - * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF - * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF - * 4 - - * 5A - - * 5B 0x1600_0000 SRAM (8MB) - * 6 0x1800_0000 FPGA (64K) - * 0x1801_0000 Ether (4KB) - * 0x1801_1000 USB (4KB) - */ - -/* - * SW12 - * - * bit1 bit2 bit3 - *---------------------------------------------------------------------------- - * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR - * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR - */ - -/* - * SCIFA5 (CN42) - * - * S38.3 = ON - * S39.6 = ON - * S43.1 = ON - */ - -/* - * LCDC0 (CN3/CN4/CN7) - * - * S38.1 = OFF - * S38.2 = OFF - */ - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), -}; - -/* - * FPGA - */ -#define IRQSR0 0x0020 -#define IRQSR1 0x0022 -#define IRQMR0 0x0030 -#define IRQMR1 0x0032 -#define BUSSWMR1 0x0070 -#define BUSSWMR2 0x0072 -#define BUSSWMR3 0x0074 -#define BUSSWMR4 0x0076 - -#define LCDCR 0x10B4 -#define DEVRSTCR1 0x10D0 -#define DEVRSTCR2 0x10D2 -#define A1MDSR 0x10E0 -#define BVERR 0x1100 - -/* FPGA IRQ */ -#define FPGA_IRQ_BASE (512) -#define FPGA_IRQ0 (FPGA_IRQ_BASE) -#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16) -#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15) -static u16 bonito_fpga_read(u32 offset) -{ - return __raw_readw(IOMEM(0xf0003000) + offset); -} - -static void bonito_fpga_write(u32 offset, u16 val) -{ - __raw_writew(val, IOMEM(0xf0003000) + offset); -} - -static void bonito_fpga_irq_disable(struct irq_data *data) -{ - unsigned int irq = data->irq; - u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1; - int shift = irq % 16; - - bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift)); -} - -static void bonito_fpga_irq_enable(struct irq_data *data) -{ - unsigned int irq = data->irq; - u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1; - int shift = irq % 16; - - bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift)); -} - -static struct irq_chip bonito_fpga_irq_chip __read_mostly = { - .name = "bonito FPGA", - .irq_mask = bonito_fpga_irq_disable, - .irq_unmask = bonito_fpga_irq_enable, -}; - -static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc) -{ - u32 val = bonito_fpga_read(IRQSR1) << 16 | - bonito_fpga_read(IRQSR0); - u32 mask = bonito_fpga_read(IRQMR1) << 16 | - bonito_fpga_read(IRQMR0); - - int i; - - val &= ~mask; - - for (i = 0; i < 32; i++) { - if (!(val & (1 << i))) - continue; - - generic_handle_irq(FPGA_IRQ_BASE + i); - } -} - -static void bonito_fpga_init(void) -{ - int i; - - bonito_fpga_write(IRQMR0, 0xffff); /* mask all */ - bonito_fpga_write(IRQMR1, 0xffff); /* mask all */ - - /* Device reset */ - bonito_fpga_write(DEVRSTCR1, - (1 << 2)); /* Eth */ - - /* FPGA irq require special handling */ - for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) { - irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip, - handle_level_irq, "level"); - set_irq_flags(i, IRQF_VALID); /* yuck */ - } - - irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux); - irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW); -} - -/* -* PMIC settings -* -* FIXME -* -* bonito board needs some settings by pmic which use i2c access. -* pmic settings use device_initcall() here for use it. -*/ -static __u8 *pmic_settings = NULL; -static __u8 pmic_do_2A[] = { - 0x1C, 0x09, - 0x1A, 0x80, - 0xff, 0xff, -}; - -static int __init pmic_init(void) -{ - struct i2c_adapter *a = i2c_get_adapter(0); - struct i2c_msg msg; - __u8 buf[2]; - int i, ret; - - if (!pmic_settings) - return 0; - if (!a) - return 0; - - msg.addr = 0x46; - msg.buf = buf; - msg.len = 2; - msg.flags = 0; - - for (i = 0; ; i += 2) { - buf[0] = pmic_settings[i + 0]; - buf[1] = pmic_settings[i + 1]; - - if ((0xff == buf[0]) && (0xff == buf[1])) - break; - - ret = i2c_transfer(a, &msg, 1); - if (ret < 0) { - pr_err("i2c transfer fail\n"); - break; - } - } - - return 0; -} -device_initcall(pmic_init); - -/* - * LCDC0 - */ -static const struct fb_videomode lcdc0_mode = { - .name = "WVGA Panel", - .xres = 800, - .yres = 480, - .left_margin = 88, - .right_margin = 40, - .hsync_len = 128, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .sync = 0, -}; - -static struct sh_mobile_lcdc_info lcdc0_info = { - .clock_source = LCDC_CLK_BUS, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .interface_type = RGB24, - .clock_divider = 5, - .flags = 0, - .lcd_modes = &lcdc0_mode, - .num_modes = 1, - .panel_cfg = { - .width = 152, - .height = 91, - }, - }, -}; - -static struct resource lcdc0_resources[] = { - [0] = { - .name = "LCDC0", - .start = 0xfe940000, - .end = 0xfe943fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x0580), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device lcdc0_device = { - .name = "sh_mobile_lcdc_fb", - .id = 0, - .resource = lcdc0_resources, - .num_resources = ARRAY_SIZE(lcdc0_resources), - .dev = { - .platform_data = &lcdc0_info, - .coherent_dma_mask = ~0, - }, -}; - -static const struct pinctrl_map lcdc0_pinctrl_map[] = { - /* LCD0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_data24_1", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_lclk_1", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_sync", "lcd0"), -}; - -/* - * SMSC 9221 - */ -static struct resource smsc_resources[] = { - [0] = { - .start = 0x18010000, - .end = 0x18011000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = FPGA_ETH_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config smsc_platdata = { - .flags = SMSC911X_USE_16BIT, - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device smsc_device = { - .name = "smsc911x", - .dev = { - .platform_data = &smsc_platdata, - }, - .resource = smsc_resources, - .num_resources = ARRAY_SIZE(smsc_resources), -}; - -/* - * core board devices - */ -static struct platform_device *bonito_core_devices[] __initdata = { -}; - -/* - * base board devices - */ -static struct platform_device *bonito_base_devices[] __initdata = { - &lcdc0_device, - &smsc_device, -}; - -/* - * map I/O - */ -static struct map_desc bonito_io_desc[] __initdata = { - /* - * for FPGA (0x1800000-0x19ffffff) - * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000 - */ - { - .virtual = 0xf0003000, - .pfn = __phys_to_pfn(0x18000000), - .length = PAGE_SIZE * 2, - .type = MT_DEVICE_NONSHARED - } -}; - -static void __init bonito_map_io(void) -{ - r8a7740_map_io(); - iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc)); -} - -/* - * board init - */ -#define BIT_ON(sw, bit) (sw & (1 << bit)) -#define BIT_OFF(sw, bit) (!(sw & (1 << bit))) - -#define VCCQ1CR IOMEM(0xE6058140) -#define VCCQ1LCDCR IOMEM(0xE6058186) - -static void __init bonito_init(void) -{ - u16 val; - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - r8a7740_pinmux_init(); - bonito_fpga_init(); - - pmic_settings = pmic_do_2A; - - /* - * core board settings - */ - -#ifdef CONFIG_CACHE_L2X0 - /* Early BRESP enable, Shared attribute override enable, 32K*8way */ - l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); -#endif - - r8a7740_add_standard_devices(); - - platform_add_devices(bonito_core_devices, - ARRAY_SIZE(bonito_core_devices)); - - /* - * base board settings - */ - gpio_request_one(176, GPIOF_IN, NULL); - if (!gpio_get_value(176)) { - u16 bsw2; - u16 bsw3; - u16 bsw4; - - /* - * FPGA - */ - gpio_request(GPIO_FN_CS5B, NULL); - gpio_request(GPIO_FN_CS6A, NULL); - gpio_request(GPIO_FN_CS5A_PORT105, NULL); - gpio_request(GPIO_FN_IRQ10, NULL); - - val = bonito_fpga_read(BVERR); - pr_info("bonito version: cpu %02x, base %02x\n", - ((val >> 8) & 0xFF), - ((val >> 0) & 0xFF)); - - bsw2 = bonito_fpga_read(BUSSWMR2); - bsw3 = bonito_fpga_read(BUSSWMR3); - bsw4 = bonito_fpga_read(BUSSWMR4); - - /* - * SCIFA5 (CN42) - */ - if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */ - BIT_OFF(bsw3, 9) && /* S39.6 = ON */ - BIT_OFF(bsw4, 4)) { /* S43.1 = ON */ - gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL); - gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL); - } - - /* - * LCDC0 (CN3) - */ - if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ - BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ - pinctrl_register_mappings(lcdc0_pinctrl_map, - ARRAY_SIZE(lcdc0_pinctrl_map)); - gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - - gpio_request_one(61, GPIOF_OUT_INIT_HIGH, - NULL); /* LCDDON */ - - /* backlight on */ - bonito_fpga_write(LCDCR, 1); - - /* drivability Max */ - __raw_writew(0x00FF , VCCQ1LCDCR); - __raw_writew(0xFFFF , VCCQ1CR); - } - - platform_add_devices(bonito_base_devices, - ARRAY_SIZE(bonito_base_devices)); - } -} - -static void __init bonito_earlytimer_init(void) -{ - u16 val; - u8 md_ck = 0; - - /* read MD_CK value */ - val = bonito_fpga_read(A1MDSR); - if (val & (1 << 10)) - md_ck |= MD_CK2; - if (val & (1 << 9)) - md_ck |= MD_CK1; - if (val & (1 << 8)) - md_ck |= MD_CK0; - - r8a7740_clock_init(md_ck); - shmobile_earlytimer_init(); -} - -static void __init bonito_add_early_devices(void) -{ - r8a7740_add_early_devices(); -} - -MACHINE_START(BONITO, "bonito") - .map_io = bonito_map_io, - .init_early = bonito_add_early_devices, - .init_irq = r8a7740_init_irq, - .handle_irq = shmobile_handle_irq_intc, - .init_machine = bonito_init, - .init_late = shmobile_init_late, - .init_time = bonito_earlytimer_init, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c index c016ccd9243..4368000e112 100644 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ b/arch/arm/mach-shmobile/board-kzm9d.c @@ -56,7 +56,7 @@ static struct smsc911x_platform_config smsc911x_platdata = { static struct platform_device smsc91x_device = { .name = "smsc911x", - .id = 0, + .id = -1, .dev = { .platform_data = &smsc911x_platdata, }, diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index aefa50d385b..44055fe8a45 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c @@ -79,7 +79,6 @@ static void __init kzm_init(void) sh73a0_pinmux_init(); /* enable SD */ - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index e6b775a10aa..165483c9bee 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -29,6 +29,7 @@ #include <linux/mmc/host.h> #include <linux/mmc/sh_mmcif.h> #include <linux/mmc/sh_mobile_sdhi.h> +#include <linux/mfd/as3711.h> #include <linux/mfd/tmio.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> @@ -606,6 +607,140 @@ static struct platform_device fsi_ak4648_device = { }; /* I2C */ + +/* StepDown1 is used to supply 1.315V to the CPU */ +static struct regulator_init_data as3711_sd1 = { + .constraints = { + .name = "1.315V CPU", + .boot_on = 1, + .always_on = 1, + .min_uV = 1315000, + .max_uV = 1335000, + }, +}; + +/* StepDown2 is used to supply 1.8V to the CPU and to the board */ +static struct regulator_init_data as3711_sd2 = { + .constraints = { + .name = "1.8V", + .boot_on = 1, + .always_on = 1, + .min_uV = 1800000, + .max_uV = 1800000, + }, +}; + +/* + * StepDown3 is switched in parallel with StepDown2, seems to be off, + * according to read-back pre-set register values + */ + +/* StepDown4 is used to supply 1.215V to the CPU and to the board */ +static struct regulator_init_data as3711_sd4 = { + .constraints = { + .name = "1.215V", + .boot_on = 1, + .always_on = 1, + .min_uV = 1215000, + .max_uV = 1235000, + }, +}; + +/* LDO1 is unused and unconnected */ + +/* LDO2 is used to supply 2.8V to the CPU */ +static struct regulator_init_data as3711_ldo2 = { + .constraints = { + .name = "2.8V CPU", + .boot_on = 1, + .always_on = 1, + .min_uV = 2800000, + .max_uV = 2800000, + }, +}; + +/* LDO3 is used to supply 3.0V to the CPU */ +static struct regulator_init_data as3711_ldo3 = { + .constraints = { + .name = "3.0V CPU", + .boot_on = 1, + .always_on = 1, + .min_uV = 3000000, + .max_uV = 3000000, + }, +}; + +/* LDO4 is used to supply 2.8V to the board */ +static struct regulator_init_data as3711_ldo4 = { + .constraints = { + .name = "2.8V", + .boot_on = 1, + .always_on = 1, + .min_uV = 2800000, + .max_uV = 2800000, + }, +}; + +/* LDO5 is switched parallel to LDO4, also set to 2.8V */ +static struct regulator_init_data as3711_ldo5 = { + .constraints = { + .name = "2.8V #2", + .boot_on = 1, + .always_on = 1, + .min_uV = 2800000, + .max_uV = 2800000, + }, +}; + +/* LDO6 is unused and unconnected */ + +/* LDO7 is used to supply 1.15V to the CPU */ +static struct regulator_init_data as3711_ldo7 = { + .constraints = { + .name = "1.15V CPU", + .boot_on = 1, + .always_on = 1, + .min_uV = 1150000, + .max_uV = 1150000, + }, +}; + +/* LDO8 is switched parallel to LDO7, also set to 1.15V */ +static struct regulator_init_data as3711_ldo8 = { + .constraints = { + .name = "1.15V CPU #2", + .boot_on = 1, + .always_on = 1, + .min_uV = 1150000, + .max_uV = 1150000, + }, +}; + +static struct as3711_platform_data as3711_pdata = { + .regulator = { + .init_data = { + [AS3711_REGULATOR_SD_1] = &as3711_sd1, + [AS3711_REGULATOR_SD_2] = &as3711_sd2, + [AS3711_REGULATOR_SD_4] = &as3711_sd4, + [AS3711_REGULATOR_LDO_2] = &as3711_ldo2, + [AS3711_REGULATOR_LDO_3] = &as3711_ldo3, + [AS3711_REGULATOR_LDO_4] = &as3711_ldo4, + [AS3711_REGULATOR_LDO_5] = &as3711_ldo5, + [AS3711_REGULATOR_LDO_7] = &as3711_ldo7, + [AS3711_REGULATOR_LDO_8] = &as3711_ldo8, + }, + }, + .backlight = { + .su2_fb = "sh_mobile_lcdc_fb.0", + .su2_max_uA = 36000, + .su2_feedback = AS3711_SU2_CURR_AUTO, + .su2_fbprot = AS3711_SU2_GPIO4, + .su2_auto_curr1 = true, + .su2_auto_curr2 = true, + .su2_auto_curr3 = true, + }, +}; + static struct pcf857x_platform_data pcf8575_pdata = { .gpio_base = GPIO_PCF8575_BASE, }; @@ -625,6 +760,11 @@ static struct i2c_board_info i2c0_devices[] = { I2C_BOARD_INFO("adxl34x", 0x1d), .irq = irq_pin(26), /* IRQ26 */ }, + { + I2C_BOARD_INFO("as3711", 0x40), + .irq = intcs_evt2irq(0x3300), /* IRQ24 */ + .platform_data = &as3711_pdata, + }, }; static struct i2c_board_info i2c1_devices[] = { @@ -663,13 +803,13 @@ static unsigned long pin_pullup_conf[] = { static const struct pinctrl_map kzm_pinctrl_map[] = { /* FSIA (AK4648) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_mclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_data_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", + PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0", "fsia_data_out", "fsia"), /* I2C3 */ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", @@ -715,59 +855,6 @@ static const struct pinctrl_map kzm_pinctrl_map[] = { "usb_vbus", "usb"), }; -/* - * FIXME - * - * This is quick hack for enabling LCDC backlight - */ -static int __init as3711_enable_lcdc_backlight(void) -{ - struct i2c_adapter *a = i2c_get_adapter(0); - struct i2c_msg msg; - int i, ret; - __u8 magic[] = { - 0x40, 0x2a, - 0x43, 0x3c, - 0x44, 0x3c, - 0x45, 0x3c, - 0x54, 0x03, - 0x51, 0x00, - 0x51, 0x01, - 0xff, 0x00, /* wait */ - 0x43, 0xf0, - 0x44, 0xf0, - 0x45, 0xf0, - }; - - if (!of_machine_is_compatible("renesas,kzm9g")) - return 0; - - if (!a) - return 0; - - msg.addr = 0x40; - msg.len = 2; - msg.flags = 0; - - for (i = 0; i < ARRAY_SIZE(magic); i += 2) { - msg.buf = magic + i; - - if (0xff == msg.buf[0]) { - udelay(500); - continue; - } - - ret = i2c_transfer(a, &msg, 1); - if (ret < 0) { - pr_err("i2c transfer fail\n"); - break; - } - } - - return 0; -} -device_initcall(as3711_enable_lcdc_backlight); - static void __init kzm_init(void) { regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers, @@ -788,9 +875,6 @@ static void __init kzm_init(void) /* Touchscreen */ gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ - /* enable SD */ - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index f587187a860..d73e21d3ea8 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -18,19 +18,83 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> #include <linux/interrupt.h> #include <linux/irqchip.h> #include <linux/kernel.h> +#include <linux/leds.h> +#include <linux/pinctrl/machine.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/platform_device.h> #include <mach/common.h> #include <mach/r8a7790.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +/* LEDS */ +static struct gpio_led lager_leds[] = { + { + .name = "led8", + .gpio = RCAR_GP_PIN(5, 17), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led7", + .gpio = RCAR_GP_PIN(4, 23), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, { + .name = "led6", + .gpio = RCAR_GP_PIN(4, 22), + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, +}; + +static __initdata struct gpio_led_platform_data lager_leds_pdata = { + .leds = lager_leds, + .num_leds = ARRAY_SIZE(lager_leds), +}; + +/* GPIO KEY */ +#define GPIO_KEY(c, g, d, ...) \ + { .code = c, .gpio = g, .desc = d, .active_low = 1 } + +static __initdata struct gpio_keys_button gpio_buttons[] = { + GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"), + GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"), + GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"), + GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"), +}; + +static __initdata struct gpio_keys_platform_data lager_keys_pdata = { + .buttons = gpio_buttons, + .nbuttons = ARRAY_SIZE(gpio_buttons), +}; + +static const struct pinctrl_map lager_pinctrl_map[] = { + /* SCIF0 (CN19: DEBUG SERIAL0) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", + "scif0_data", "scif0"), + /* SCIF1 (CN20: DEBUG SERIAL1) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", + "scif1_data", "scif1"), +}; + static void __init lager_add_standard_devices(void) { r8a7790_clock_init(); + + pinctrl_register_mappings(lager_pinctrl_map, + ARRAY_SIZE(lager_pinctrl_map)); + r8a7790_pinmux_init(); + r8a7790_add_standard_devices(); + platform_device_register_data(&platform_bus, "leds-gpio", -1, + &lager_leds_pdata, + sizeof(lager_leds_pdata)); + platform_device_register_data(&platform_bus, "gpio-keys", -1, + &lager_keys_pdata, + sizeof(lager_keys_pdata)); } static const char *lager_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index fa3407da682..85f51a849a5 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = { }; static const struct pinctrl_map mackerel_pinctrl_map[] = { + /* ADXL34X */ + PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372", + "intc_irq21", "intc"), + /* CEU */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_data_0_7", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_clk_0", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_sync", "ceu"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", + "ceu_field", "ceu"), + /* FLCTL */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_data", "flctl"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_ce0", "flctl"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", + "flctl_ctrl", "flctl"), + /* FSIA (AK4643) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_sclk_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_data_in", "fsia"), + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", + "fsia_data_out", "fsia"), + /* FSIB (HDMI) */ + PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", + "fsib_mclk_in", "fsib"), + /* HDMI */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", + "hdmi", "hdmi"), + /* LCDC */ + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_data24", "lcd"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", + "lcd_sync", "lcd"), + /* SCIFA0 */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", + "scifa0_data", "scifa0"), + /* SCIFA2 (GT-720F GPS module) */ + PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372", + "scifa2_data", "scifa2"), /* SDHI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_data4", "sdhi0"), @@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", "sdhi0_wp", "sdhi0"), + PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", + "intc_irq26_1", "intc"), /* SDHI1 */ #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", @@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = { "sdhi2_data4", "sdhi2"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", "sdhi2_ctrl", "sdhi2"), + /* SMSC911X */ + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "bsc_cs5a", "bsc"), + PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", + "intc_irq6_0", "intc"), + /* ST1232 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372", + "intc_irq7_0", "intc"), + /* TCA6416 */ + PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372", + "intc_irq9_0", "intc"), + /* USBHS0 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", + "usb0_vbus", "usb0"), + /* USBHS1 */ + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", + "usb1_vbus", "usb1"), + PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", + "usb1_otg_id_0", "usb1"), }; #define GPIO_PORT9CR IOMEM(0xE6051009) @@ -1377,61 +1441,18 @@ static void __init mackerel_init(void) ARRAY_SIZE(mackerel_pinctrl_map)); sh7372_pinmux_init(); - /* enable SCIFA0 */ - gpio_request(GPIO_FN_SCIFA0_TXD, NULL); - gpio_request(GPIO_FN_SCIFA0_RXD, NULL); - - /* enable SMSC911X */ - gpio_request(GPIO_FN_CS5A, NULL); - gpio_request(GPIO_FN_IRQ6_39, NULL); - - /* LCDC */ - gpio_request(GPIO_FN_LCDD23, NULL); - gpio_request(GPIO_FN_LCDD22, NULL); - gpio_request(GPIO_FN_LCDD21, NULL); - gpio_request(GPIO_FN_LCDD20, NULL); - gpio_request(GPIO_FN_LCDD19, NULL); - gpio_request(GPIO_FN_LCDD18, NULL); - gpio_request(GPIO_FN_LCDD17, NULL); - gpio_request(GPIO_FN_LCDD16, NULL); - gpio_request(GPIO_FN_LCDD15, NULL); - gpio_request(GPIO_FN_LCDD14, NULL); - gpio_request(GPIO_FN_LCDD13, NULL); - gpio_request(GPIO_FN_LCDD12, NULL); - gpio_request(GPIO_FN_LCDD11, NULL); - gpio_request(GPIO_FN_LCDD10, NULL); - gpio_request(GPIO_FN_LCDD9, NULL); - gpio_request(GPIO_FN_LCDD8, NULL); - gpio_request(GPIO_FN_LCDD7, NULL); - gpio_request(GPIO_FN_LCDD6, NULL); - gpio_request(GPIO_FN_LCDD5, NULL); - gpio_request(GPIO_FN_LCDD4, NULL); - gpio_request(GPIO_FN_LCDD3, NULL); - gpio_request(GPIO_FN_LCDD2, NULL); - gpio_request(GPIO_FN_LCDD1, NULL); - gpio_request(GPIO_FN_LCDD0, NULL); - gpio_request(GPIO_FN_LCDDISP, NULL); - gpio_request(GPIO_FN_LCDDCK, NULL); - /* backlight, off by default */ gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ /* USBHS0 */ - gpio_request(GPIO_FN_VBUS0_0, NULL); gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */ /* USBHS1 */ - gpio_request(GPIO_FN_VBUS0_1, NULL); gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */ - gpio_request(GPIO_FN_IDIN_1_113, NULL); - /* enable FSI2 port A (ak4643) */ - gpio_request(GPIO_FN_FSIAIBT, NULL); - gpio_request(GPIO_FN_FSIAILR, NULL); - gpio_request(GPIO_FN_FSIAISLD, NULL); - gpio_request(GPIO_FN_FSIAOSLD, NULL); + /* FSI2 port A (ak4643) */ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ gpio_request(9, NULL); @@ -1441,8 +1462,7 @@ static void __init mackerel_init(void) intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ - /* setup FSI2 port B (HDMI) */ - gpio_request(GPIO_FN_FSIBCK, NULL); + /* FSI2 port B (HDMI) */ __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ /* set SPU2 clock to 119.6 MHz */ @@ -1452,68 +1472,15 @@ static void __init mackerel_init(void) clk_put(clk); } - /* enable Keypad */ - gpio_request(GPIO_FN_IRQ9_42, NULL); + /* Keypad */ irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); - /* enable Touchscreen */ - gpio_request(GPIO_FN_IRQ7_40, NULL); + /* Touchscreen */ irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); - /* enable Accelerometer */ - gpio_request(GPIO_FN_IRQ21, NULL); + /* Accelerometer */ irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); - /* SDHI0 PORT172 card-detect IRQ26 */ - gpio_request(GPIO_FN_IRQ26_172, NULL); - - /* FLCTL */ - gpio_request(GPIO_FN_D0_NAF0, NULL); - gpio_request(GPIO_FN_D1_NAF1, NULL); - gpio_request(GPIO_FN_D2_NAF2, NULL); - gpio_request(GPIO_FN_D3_NAF3, NULL); - gpio_request(GPIO_FN_D4_NAF4, NULL); - gpio_request(GPIO_FN_D5_NAF5, NULL); - gpio_request(GPIO_FN_D6_NAF6, NULL); - gpio_request(GPIO_FN_D7_NAF7, NULL); - gpio_request(GPIO_FN_D8_NAF8, NULL); - gpio_request(GPIO_FN_D9_NAF9, NULL); - gpio_request(GPIO_FN_D10_NAF10, NULL); - gpio_request(GPIO_FN_D11_NAF11, NULL); - gpio_request(GPIO_FN_D12_NAF12, NULL); - gpio_request(GPIO_FN_D13_NAF13, NULL); - gpio_request(GPIO_FN_D14_NAF14, NULL); - gpio_request(GPIO_FN_D15_NAF15, NULL); - gpio_request(GPIO_FN_FCE0, NULL); - gpio_request(GPIO_FN_WE0_FWE, NULL); - gpio_request(GPIO_FN_FRB, NULL); - gpio_request(GPIO_FN_A4_FOE, NULL); - gpio_request(GPIO_FN_A5_FCDE, NULL); - gpio_request(GPIO_FN_RD_FSC, NULL); - - /* enable GPS module (GT-720F) */ - gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); - gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); - - /* CEU */ - gpio_request(GPIO_FN_VIO_CLK, NULL); - gpio_request(GPIO_FN_VIO_VD, NULL); - gpio_request(GPIO_FN_VIO_HD, NULL); - gpio_request(GPIO_FN_VIO_FIELD, NULL); - gpio_request(GPIO_FN_VIO_CKO, NULL); - gpio_request(GPIO_FN_VIO_D7, NULL); - gpio_request(GPIO_FN_VIO_D6, NULL); - gpio_request(GPIO_FN_VIO_D5, NULL); - gpio_request(GPIO_FN_VIO_D4, NULL); - gpio_request(GPIO_FN_VIO_D3, NULL); - gpio_request(GPIO_FN_VIO_D2, NULL); - gpio_request(GPIO_FN_VIO_D1, NULL); - gpio_request(GPIO_FN_VIO_D0, NULL); - - /* HDMI */ - gpio_request(GPIO_FN_HDMI_HPD, NULL); - gpio_request(GPIO_FN_HDMI_CEC, NULL); - /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ srcr4 = __raw_readl(SRCR4); __raw_writel(srcr4 | (1 << 13), SRCR4); diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index b9594e911ce..a7d1010505b 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -28,6 +28,7 @@ #include <linux/leds.h> #include <linux/dma-mapping.h> #include <linux/pinctrl/machine.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> #include <linux/smsc911x.h> @@ -36,10 +37,6 @@ #include <linux/mmc/host.h> #include <linux/mmc/sh_mobile_sdhi.h> #include <linux/mfd/tmio.h> -#include <linux/usb/otg.h> -#include <linux/usb/ehci_pdriver.h> -#include <linux/usb/ohci_pdriver.h> -#include <linux/pm_runtime.h> #include <mach/hardware.h> #include <mach/r8a7779.h> #include <mach/common.h> @@ -60,6 +57,8 @@ static struct regulator_consumer_supply dummy_supplies[] = { REGULATOR_SUPPLY("vdd33a", "smsc911x"), }; +static struct rcar_phy_platform_data usb_phy_platform_data __initdata; + /* SMSC LAN89218 */ static struct resource smsc911x_resources[] = { [0] = { @@ -68,7 +67,7 @@ static struct resource smsc911x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_iid(0x3c), /* IRQ 1 */ + .start = irq_pin(1), /* IRQ 1 */ .flags = IORESOURCE_IRQ, }, }; @@ -149,39 +148,19 @@ static struct platform_device hspi_device = { .num_resources = ARRAY_SIZE(hspi_resources), }; -/* USB PHY */ -static struct resource usb_phy_resources[] = { - [0] = { - .start = 0xffe70000, - .end = 0xffe70900 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xfff70000, - .end = 0xfff70900 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device usb_phy_device = { - .name = "rcar_usb_phy", - .resource = usb_phy_resources, - .num_resources = ARRAY_SIZE(usb_phy_resources), -}; - /* LEDS */ static struct gpio_led marzen_leds[] = { { .name = "led2", - .gpio = 157, + .gpio = RCAR_GP_PIN(4, 29), .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led3", - .gpio = 158, + .gpio = RCAR_GP_PIN(4, 30), .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led4", - .gpio = 159, + .gpio = RCAR_GP_PIN(4, 31), .default_state = LEDS_GPIO_DEFSTATE_ON, }, }; @@ -204,161 +183,9 @@ static struct platform_device *marzen_devices[] __initdata = { &sdhi0_device, &thermal_device, &hspi_device, - &usb_phy_device, &leds_device, }; -/* USB */ -static struct usb_phy *phy; -static int usb_power_on(struct platform_device *pdev) -{ - if (IS_ERR(phy)) - return PTR_ERR(phy); - - pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - - usb_phy_init(phy); - - return 0; -} - -static void usb_power_off(struct platform_device *pdev) -{ - if (IS_ERR(phy)) - return; - - usb_phy_shutdown(phy); - - pm_runtime_put_sync(&pdev->dev); - pm_runtime_disable(&pdev->dev); -} - -static struct usb_ehci_pdata ehcix_pdata = { - .power_on = usb_power_on, - .power_off = usb_power_off, - .power_suspend = usb_power_off, -}; - -static struct resource ehci0_resources[] = { - [0] = { - .start = 0xffe70000, - .end = 0xffe70400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4c), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ehci0_device = { - .name = "ehci-platform", - .id = 0, - .dev = { - .dma_mask = &ehci0_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ehcix_pdata, - }, - .num_resources = ARRAY_SIZE(ehci0_resources), - .resource = ehci0_resources, -}; - -static struct resource ehci1_resources[] = { - [0] = { - .start = 0xfff70000, - .end = 0xfff70400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4d), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ehci1_device = { - .name = "ehci-platform", - .id = 1, - .dev = { - .dma_mask = &ehci1_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ehcix_pdata, - }, - .num_resources = ARRAY_SIZE(ehci1_resources), - .resource = ehci1_resources, -}; - -static struct usb_ohci_pdata ohcix_pdata = { - .power_on = usb_power_on, - .power_off = usb_power_off, - .power_suspend = usb_power_off, -}; - -static struct resource ohci0_resources[] = { - [0] = { - .start = 0xffe70400, - .end = 0xffe70800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4c), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci0_device = { - .name = "ohci-platform", - .id = 0, - .dev = { - .dma_mask = &ohci0_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ohcix_pdata, - }, - .num_resources = ARRAY_SIZE(ohci0_resources), - .resource = ohci0_resources, -}; - -static struct resource ohci1_resources[] = { - [0] = { - .start = 0xfff70400, - .end = 0xfff70800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x4d), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ohci1_device = { - .name = "ohci-platform", - .id = 1, - .dev = { - .dma_mask = &ohci1_device.dev.coherent_dma_mask, - .coherent_dma_mask = 0xffffffff, - .platform_data = &ohcix_pdata, - }, - .num_resources = ARRAY_SIZE(ohci1_resources), - .resource = ohci1_resources, -}; - -static struct platform_device *marzen_late_devices[] __initdata = { - &ehci0_device, - &ehci1_device, - &ohci0_device, - &ohci1_device, -}; - -void __init marzen_init_late(void) -{ - /* get usb phy */ - phy = usb_get_phy(USB_PHY_TYPE_USB2); - - shmobile_init_late(); - platform_add_devices(marzen_late_devices, - ARRAY_SIZE(marzen_late_devices)); -} - static const struct pinctrl_map marzen_pinctrl_map[] = { /* HSPI0 */ PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", @@ -404,8 +231,10 @@ static void __init marzen_init(void) pinctrl_register_mappings(marzen_pinctrl_map, ARRAY_SIZE(marzen_pinctrl_map)); r8a7779_pinmux_init(); + r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ r8a7779_add_standard_devices(); + r8a7779_add_usb_phy_device(&usb_phy_platform_data); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } @@ -416,6 +245,6 @@ MACHINE_START(MARZEN, "marzen") .nr_irqs = NR_IRQS_LEGACY, .init_irq = r8a7779_init_irq, .init_machine = marzen_init, - .init_late = marzen_init_late, + .init_late = r8a7779_init_late, .init_time = r8a7779_earlytimer_init, MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index e710c00c382..5f7fe628b8a 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -22,15 +22,44 @@ #include <linux/kernel.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> #define CPG_BASE 0xe6150000 #define CPG_LEN 0x270 -#define MPCKCR 0xe6150080 #define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c #define SMSTPCR5 0xe6150144 +#define FRQCRA 0xE6150000 +#define FRQCRB 0xE6150004 +#define VCLKCR1 0xE6150008 +#define VCLKCR2 0xE615000C +#define VCLKCR3 0xE615001C +#define VCLKCR4 0xE6150014 +#define VCLKCR5 0xE6150034 +#define ZBCKCR 0xE6150010 +#define SD0CKCR 0xE6150074 +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615007C +#define MMC0CKCR 0xE6150240 +#define MMC1CKCR 0xE6150244 +#define FSIACKCR 0xE6150018 +#define FSIBCKCR 0xE6150090 +#define MPCKCR 0xe6150080 +#define SPUVCKCR 0xE6150094 +#define HSICKCR 0xE615026C +#define M4CKCR 0xE6150098 +#define PLLECR 0xE61500D0 +#define PLL1CR 0xE6150028 +#define PLL2CR 0xE615002C +#define PLL2SCR 0xE61501F4 +#define PLL2HCR 0xE61501E4 +#define CKSCR 0xE61500C0 + +#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, @@ -51,29 +80,327 @@ static struct clk extal2_clk = { .mapping = &cpg_mapping, }; +static struct sh_clk_ops followparent_clk_ops = { + .recalc = followparent_recalc, +}; + +static struct clk main_clk = { + /* .parent will be set r8a73a4_clock_init */ + .ops = &followparent_clk_ops, +}; + +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div4, 1, 4); + +SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); + +/* External FSIACK/FSIBCK clock */ +static struct clk fsiack_clk = { +}; + +static struct clk fsibck_clk = { +}; + +/* + * PLL clocks + */ +static struct clk *pll_parent_main[] = { + [0] = &main_clk, + [1] = &main_div2_clk +}; + +static struct clk *pll_parent_main_extal[8] = { + [0] = &main_div2_clk, + [1] = &extal2_div2_clk, + [3] = &extal2_div4_clk, + [4] = &main_clk, + [5] = &extal2_clk, +}; + +static unsigned long pll_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit)) + mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1); + + return clk->parent->rate * mult; +} + +static int pll_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + int i, ret; + + if (!clk->parent_table || !clk->parent_num) + return -EINVAL; + + /* Search the parent */ + for (i = 0; i < clk->parent_num; i++) + if (clk->parent_table[i] == parent) + break; + + if (i == clk->parent_num) + return -ENODEV; + + ret = clk_reparent(clk, parent); + if (ret < 0) + return ret; + + val = ioread32(clk->mapped_reg) & + ~(((1 << clk->src_width) - 1) << clk->src_shift); + + iowrite32(val | i << clk->src_shift, clk->mapped_reg); + + return 0; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, + .set_parent = pll_set_parent, +}; + +#define PLL_CLOCK(name, p, pt, w, s, reg, e) \ + static struct clk name = { \ + .ops = &pll_clk_ops, \ + .flags = CLK_ENABLE_ON_INIT, \ + .parent = p, \ + .parent_table = pt, \ + .parent_num = ARRAY_SIZE(pt), \ + .src_width = w, \ + .src_shift = s, \ + .enable_reg = (void __iomem *)reg, \ + .enable_bit = e, \ + .mapping = &cpg_mapping, \ + } + +PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); +PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); +PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); +PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); + +SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); + static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, + &extal1_div2_clk, &extal2_clk, + &extal2_div2_clk, + &extal2_div4_clk, + &main_clk, + &main_div2_clk, + &fsiack_clk, + &fsibck_clk, + &pll1_clk, + &pll1_div2_clk, + &pll2_clk, + &pll2s_clk, + &pll2h_clk, +}; + +/* DIV4 */ +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = ioread32(CPG_MAP(FRQCRB)); + value |= (1 << 31); + iowrite32(value, CPG_MAP(FRQCRB)); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { + DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, + DIV4_ZX, DIV4_ZS, DIV4_HP, + DIV4_NR }; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0), + [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0), + [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0), + [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0), + [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), }; enum { + DIV6_ZB, + DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, + DIV6_MMC0, DIV6_MMC1, + DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5, + DIV6_FSIA, DIV6_FSIB, + DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV, + DIV6_NR }; + +static struct clk *div6_parents[8] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [3] = &extal2_clk, + [4] = &main_div2_clk, + [6] = &extalr_clk, +}; + +static struct clk *fsia_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &fsiack_clk, +}; + +static struct clk *fsib_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &fsibck_clk, +}; + +static struct clk *mp_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &extal2_clk, + [3] = &extal2_clk, +}; + +static struct clk *m4_parents[2] = { + [0] = &pll2s_clk, +}; + +static struct clk *hsi_parents[4] = { + [0] = &pll2h_clk, + [1] = &pll1_div2_clk, + [3] = &pll2s_clk, +}; + +/*** FIXME *** + * SH_CLK_DIV6_EXT() macro doesn't care .mapping + * but, it is necessary on R-Car (= ioremap() base CPG) + * The difference between + * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT() + * is only .mapping + */ +#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \ + _num_parents, _src_shift, _src_width) \ +{ \ + .enable_reg = (void __iomem *)_reg, \ + .enable_bit = 0, /* unused */ \ + .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ + .div_mask = SH_CLK_DIV6_MSK, \ + .parent_table = _parents, \ + .parent_num = _num_parents, \ + .src_shift = _src_shift, \ + .src_width = _src_width, \ + .mapping = &cpg_mapping, \ +} + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, + div6_parents, 2, 7, 1), + [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0, + fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), + [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0, + fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), + [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */ + mp_parents, ARRAY_SIZE(mp_parents), 6, 2), + /* pll2s will be selected always for M4 */ + [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */ + m4_parents, ARRAY_SIZE(m4_parents), 6, 1), + [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */ + hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2), + [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0, + mp_parents, ARRAY_SIZE(mp_parents), 6, 2), +}; + +/* MSTP */ +enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP522, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ + [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ + [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ }; static struct clk_lookup lookups[] = { + /* main clock */ + CLKDEV_CON_ID("extal1", &extal1_clk), + CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), + CLKDEV_CON_ID("extal2", &extal2_clk), + CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), + CLKDEV_CON_ID("fsiack", &fsiack_clk), + CLKDEV_CON_ID("fsibck", &fsibck_clk), + + /* pll clock */ + CLKDEV_CON_ID("pll1", &pll1_clk), + CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), + CLKDEV_CON_ID("pll2", &pll2_clk), + CLKDEV_CON_ID("pll2s", &pll2s_clk), + CLKDEV_CON_ID("pll2h", &pll2h_clk), + + /* DIV6 */ + CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), + CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]), + CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]), + CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]), + CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]), + CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]), + CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]), + CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]), + CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]), + CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]), + + /* MSTP */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -81,6 +408,16 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), + CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), /* for DT */ CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), @@ -88,22 +425,40 @@ static struct clk_lookup lookups[] = { void __init r8a73a4_clock_init(void) { - void __iomem *cpg_base, *reg; + void __iomem *reg; int k, ret = 0; + u32 ckscr; + + reg = ioremap_nocache(CKSCR, PAGE_SIZE); + BUG_ON(!reg); + ckscr = ioread32(reg); + iounmap(reg); - /* fix MPCLK to EXTAL2 for now. - * this is needed until more detailed clock topology is supported - */ - cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); - BUG_ON(!cpg_base); - reg = cpg_base + (MPCKCR - CPG_BASE); - iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ - iounmap(cpg_base); + switch ((ckscr >> 28) & 0x3) { + case 0: + main_clk.parent = &extal1_clk; + break; + case 1: + main_clk.parent = &extal1_div2_clk; + break; + case 2: + main_clk.parent = &extal2_clk; + break; + case 3: + main_clk.parent = &extal2_div2_clk; + break; + } for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); + + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index c0d39aa6de5..7fd32d604e3 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -266,7 +266,7 @@ static struct clk fsiack_clk = { static struct clk fsibck_clk = { }; -struct clk *main_clks[] = { +static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, &extal2_clk, @@ -317,7 +317,7 @@ enum { DIV4_NR }; -struct clk div4_clks[DIV4_NR] = { +static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), @@ -461,7 +461,7 @@ enum { MSTP329, MSTP328, MSTP323, MSTP320, MSTP314, MSTP313, MSTP312, - MSTP309, + MSTP309, MSTP304, MSTP416, MSTP415, MSTP407, MSTP406, @@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */ + [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */ [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */ [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ @@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]), CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]), CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), + CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), @@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), + CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), @@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), + CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index cd6855290b1..53798e5037d 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -23,9 +23,23 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/* + * MD MD MD MD PLLA PLLB EXTAL clki clkz + * 19 18 12 11 (HMz) (MHz) (MHz) + *---------------------------------------------------------------------------- + * 1 0 0 0 x21 x21 38.00 800 800 + * 1 0 0 1 x24 x24 33.33 800 800 + * 1 0 1 0 x28 x28 28.50 800 800 + * 1 0 1 1 x32 x32 25.00 800 800 + * 1 1 0 1 x24 x21 33.33 800 700 + * 1 1 1 0 x28 x21 28.50 800 600 + * 1 1 1 1 x32 x24 25.00 800 600 + */ + #include <linux/io.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> #define MSTPCR0 IOMEM(0xffc80030) @@ -37,6 +51,9 @@ #define MSTPCR4 IOMEM(0xffc80050) #define MSTPCR5 IOMEM(0xffc80054) #define MSTPCR6 IOMEM(0xffc80058) +#define MODEMR 0xFFCC0020 + +#define MD(nr) BIT(nr) /* ioremap() through clock mapping mandatory to avoid * collision with ARM coherent DMA virtual memory range. @@ -47,37 +64,94 @@ static struct clk_mapping cpg_mapping = { .len = 0x80, }; -static struct clk clkp = { - .rate = 62500000, /* FIXME: shortcut */ - .flags = CLK_ENABLE_ON_INIT, +static struct clk extal_clk = { + /* .rate will be updated on r8a7778_clock_init() */ .mapping = &cpg_mapping, }; +/* + * clock ratio of these clock will be updated + * on r8a7778_clock_init() + */ +SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1); + static struct clk *main_clks[] = { - &clkp, + &extal_clk, + &plla_clk, + &pllb_clk, + &i_clk, + &s_clk, + &s1_clk, + &s3_clk, + &s4_clk, + &b_clk, + &out_clk, + &p_clk, + &g_clk, + &z_clk, }; enum { + MSTP331, + MSTP323, MSTP322, MSTP321, MSTP114, - MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, + MSTP100, + MSTP030, + MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, + MSTP007, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */ - [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ + [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ + [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */ + [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */ + [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */ + [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */ + [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ + [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ }; static struct clk_lookup lookups[] = { + /* main */ + CLKDEV_CON_ID("shyway_clk", &s_clk), + CLKDEV_CON_ID("peripheral_clk", &p_clk), + /* MSTP32 clocks */ + CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ + CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ + CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ + CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ + CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ + CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ @@ -86,12 +160,93 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ + CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ + CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ + CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ }; void __init r8a7778_clock_init(void) { + void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); + u32 mode; int k, ret = 0; + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) { + case MD(19): + extal_clk.rate = 38000000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); + break; + case MD(19) | MD(11): + extal_clk.rate = 33333333; + SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); + break; + case MD(19) | MD(12): + extal_clk.rate = 28500000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1); + break; + case MD(19) | MD(12) | MD(11): + extal_clk.rate = 25000000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1); + break; + case MD(19) | MD(18) | MD(11): + extal_clk.rate = 33333333; + SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); + break; + case MD(19) | MD(18) | MD(12): + extal_clk.rate = 28500000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); + break; + case MD(19) | MD(18) | MD(12) | MD(11): + extal_clk.rate = 25000000; + SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); + SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); + break; + default: + BUG(); + } + + if (mode & MD(1)) { + SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); + SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3); + SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6); + SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); + SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18); + } else { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); + } + } else { + SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); + SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4); + SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); + SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); + SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); + if (mode & MD(2)) { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16); + } else { + SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); + SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); + } + } + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 31d5cd4d978..9daeb8c3748 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -112,7 +112,7 @@ static struct clk *main_clks[] = { }; enum { MSTP323, MSTP322, MSTP321, MSTP320, - MSTP115, MSTP114, + MSTP116, MSTP115, MSTP114, MSTP103, MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, @@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */ [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ @@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("peripheral_clk", &clkp_clk), /* MSTP32 clocks */ + CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */ CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index bad9bf2e34d..5d71313df52 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -22,48 +22,228 @@ #include <linux/kernel.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> +/* + * MD EXTAL PLL0 PLL1 PLL3 + * 14 13 19 (MHz) *1 *1 + *--------------------------------------------------- + * 0 0 0 15 x 1 x172/2 x208/2 x106 + * 0 0 1 15 x 1 x172/2 x208/2 x88 + * 0 1 0 20 x 1 x130/2 x156/2 x80 + * 0 1 1 20 x 1 x130/2 x156/2 x66 + * 1 0 0 26 / 2 x200/2 x240/2 x122 + * 1 0 1 26 / 2 x200/2 x240/2 x102 + * 1 1 0 30 / 2 x172/2 x208/2 x106 + * 1 1 1 30 / 2 x172/2 x208/2 x88 + * + * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2) + * see "p1 / 2" on R8A7790_CLOCK_ROOT() below + */ + +#define MD(nr) (1 << nr) + #define CPG_BASE 0xe6150000 #define CPG_LEN 0x1000 #define SMSTPCR2 0xe6150138 +#define SMSTPCR3 0xe615013c #define SMSTPCR7 0xe615014c +#define MODEMR 0xE6160060 +#define SDCKCR 0xE6150074 +#define SD2CKCR 0xE6150078 +#define SD3CKCR 0xE615007C +#define MMC0CKCR 0xE6150240 +#define MMC1CKCR 0xE6150244 +#define SSPCKCR 0xE6150248 +#define SSPRSCKCR 0xE615024C + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, }; -static struct clk p_clk = { - .rate = 65000000, /* shortcut for now */ +static struct clk extal_clk = { + /* .rate will be updated on r8a7790_clock_init() */ .mapping = &cpg_mapping, }; -static struct clk mp_clk = { - .rate = 52000000, /* shortcut for now */ - .mapping = &cpg_mapping, +static struct sh_clk_ops followparent_clk_ops = { + .recalc = followparent_recalc, +}; + +static struct clk main_clk = { + /* .parent will be set r8a73a4_clock_init */ + .ops = &followparent_clk_ops, }; +/* + * clock ratio of these clock will be updated + * on r8a7790_clock_init() + */ +SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1); +SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1); + +/* fixed ratio clock */ +SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2); +SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2); + +SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2); +SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3); +SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); +SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6); +SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); +SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2); +SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12); +SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); +SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48); +SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8); +SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4); +SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); +SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024)); + +SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4); +SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8); +SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8); +SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); + static struct clk *main_clks[] = { + &extal_clk, + &extal_div2_clk, + &main_clk, + &pll1_clk, + &pll1_div2_clk, + &pll3_clk, + &lb_clk, + &qspi_clk, + &zg_clk, + &zx_clk, + &zs_clk, + &hp_clk, + &i_clk, + &b_clk, &p_clk, + &cl_clk, + &m2_clk, + &imp_clk, + &rclk_clk, + &oscclk_clk, + &zb3_clk, + &zb3d2_clk, + &ddr_clk, &mp_clk, + &cp_clk, +}; + +/* SDHI (DIV4) clock */ +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { + DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR +}; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), + [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), +}; + +/* DIV6 clocks */ +enum { + DIV6_SD2, DIV6_SD3, + DIV6_MMC0, DIV6_MMC1, + DIV6_SSP, DIV6_SSPRS, + DIV6_NR +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), + [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0), + [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0), + [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0), + [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0), + [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0), +}; + +/* MSTP */ +enum { + MSTP721, MSTP720, + MSTP717, MSTP716, + MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, + MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, + MSTP_NR }; -enum { MSTP721, MSTP720, - MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ + [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ + [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ + [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ + [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */ + [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */ + [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */ + [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */ [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ + [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ + [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ }; static struct clk_lookup lookups[] = { + + /* main clocks */ + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("extal_div2", &extal_div2_clk), + CLKDEV_CON_ID("main", &main_clk), + CLKDEV_CON_ID("pll1", &pll1_clk), + CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), + CLKDEV_CON_ID("pll3", &pll3_clk), + CLKDEV_CON_ID("zg", &zg_clk), + CLKDEV_CON_ID("zx", &zx_clk), + CLKDEV_CON_ID("zs", &zs_clk), + CLKDEV_CON_ID("hp", &hp_clk), + CLKDEV_CON_ID("i", &i_clk), + CLKDEV_CON_ID("b", &b_clk), + CLKDEV_CON_ID("lb", &lb_clk), + CLKDEV_CON_ID("p", &p_clk), + CLKDEV_CON_ID("cl", &cl_clk), + CLKDEV_CON_ID("m2", &m2_clk), + CLKDEV_CON_ID("imp", &imp_clk), + CLKDEV_CON_ID("rclk", &rclk_clk), + CLKDEV_CON_ID("oscclk", &oscclk_clk), + CLKDEV_CON_ID("zb3", &zb3_clk), + CLKDEV_CON_ID("zb3d2", &zb3d2_clk), + CLKDEV_CON_ID("ddr", &ddr_clk), + CLKDEV_CON_ID("mp", &mp_clk), + CLKDEV_CON_ID("qspi", &qspi_clk), + CLKDEV_CON_ID("cp", &cp_clk), + + /* DIV4 */ + CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]), + + /* DIV6 */ + CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]), + CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), + + /* MSTP */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -72,16 +252,77 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), + CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), + CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), + CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), }; +#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ + extal_clk.rate = e * 1000 * 1000; \ + main_clk.parent = m; \ + SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \ + if (mode & MD(19)) \ + SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \ + else \ + SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1) + + void __init r8a7790_clock_init(void) { + void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); + u32 mode; int k, ret = 0; + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + + switch (mode & (MD(14) | MD(13))) { + case 0: + R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); + break; + case MD(13): + R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); + break; + case MD(14): + R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); + break; + case MD(13) | MD(14): + R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); + break; + } + + if (mode & (MD(18))) + SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36); + else + SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24); + + if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2)) + SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); + else + SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) + ret = sh_clk_div6_register(div6_clks, DIV6_NR); + + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 784fbaa4cc5..d9fd0336b91 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), + /* + * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to + * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and + * 239.2MHz for VDD_DVFS=1.315V. + */ [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), @@ -252,6 +257,101 @@ static struct clk twd_clk = { .ops = &twd_clk_ops, }; +static struct sh_clk_ops zclk_ops, kicker_ops; +static const struct sh_clk_ops *div4_clk_ops; + +static int zclk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret; + + if (!clk->parent || !__clk_get(clk->parent)) + return -ENODEV; + + if (readl(FRQCRB) & (1 << 31)) + return -EBUSY; + + if (rate == clk_get_rate(clk->parent)) { + /* 1:1 - switch off divider */ + __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); + /* nullify the divider to prepare for the next time */ + ret = div4_clk_ops->set_rate(clk, rate / 2); + if (!ret) + ret = frqcr_kick(); + if (ret > 0) + ret = 0; + } else { + /* Enable the divider */ + __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); + + ret = frqcr_kick(); + if (ret >= 0) + /* + * set the divider - call the DIV4 method, it will kick + * FRQCRB too + */ + ret = div4_clk_ops->set_rate(clk, rate); + if (ret < 0) + goto esetrate; + } + +esetrate: + __clk_put(clk->parent); + return ret; +} + +static long zclk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div_freq = div4_clk_ops->round_rate(clk, rate), + parent_freq = clk_get_rate(clk->parent); + + if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq) + return parent_freq; + + return div_freq; +} + +static unsigned long zclk_recalc(struct clk *clk) +{ + /* + * Must recalculate frequencies in case PLL0 has been changed, even if + * the divisor is unused ATM! + */ + unsigned long div_freq = div4_clk_ops->recalc(clk); + + if (__raw_readl(FRQCRB) & (1 << 28)) + return div_freq; + + return clk_get_rate(clk->parent); +} + +static int kicker_set_rate(struct clk *clk, unsigned long rate) +{ + if (__raw_readl(FRQCRB) & (1 << 31)) + return -EBUSY; + + return div4_clk_ops->set_rate(clk, rate); +} + +static void div4_clk_extend(void) +{ + int i; + + div4_clk_ops = div4_clks[0].ops; + + /* Add a kicker-busy check before changing the rate */ + kicker_ops = *div4_clk_ops; + /* We extend the DIV4 clock with a 1:1 pass-through case */ + zclk_ops = *div4_clk_ops; + + kicker_ops.set_rate = kicker_set_rate; + zclk_ops.set_rate = zclk_set_rate; + zclk_ops.round_rate = zclk_round_rate; + zclk_ops.recalc = zclk_recalc; + + for (i = 0; i < DIV4_NR; i++) + div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops; +} + enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, DIV6_FSIA, DIV6_FSIB, DIV6_SUB, @@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = { }; enum { MSTP001, - MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, + MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100, MSTP219, MSTP218, MSTP217, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, @@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */ [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ + [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */ [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ @@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("r_clk", &r_clk), CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ + /* DIV4 clocks */ + CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]), + /* DIV6 clocks */ CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), @@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void) for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); - if (!ret) + if (!ret) { ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + if (!ret) + div4_clk_extend(); + } if (!ret) ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 7d113f898e7..6f986546725 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -25,31 +25,24 @@ __CPUINIT /* - * Reset vector for secondary CPUs. + * Boot code for secondary CPUs. * * First we turn on L1 cache coherency for our CPU. Then we jump to * shmobile_invalidate_start that invalidates the cache and hands over control * to the common ARM startup code. - * This function will be mapped to address 0 by the SBAR register. - * A normal branch is out of range here so we need a long jump. We jump to - * the physical address as the MMU is still turned off. */ - .align 12 -ENTRY(shmobile_secondary_vector_scu) - mrc p15, 0, r0, c0, c0, 5 @ read MIPDR - and r0, r0, #3 @ mask out cpu ID - lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - ldr r1, 2f - ldr r1, [r1] @ SCU base address - ldr r2, [r1, #8] @ SCU Power Status Register +ENTRY(shmobile_boot_scu) + @ r0 = SCU base address + mrc p15, 0, r1, c0, c0, 5 @ read MIPDR + and r1, r1, #3 @ mask out cpu ID + lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits + ldr r2, [r0, #8] @ SCU Power Status Register mov r3, #3 - bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) - str r2, [r1, #8] @ write back + bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode) + str r2, [r0, #8] @ write back - ldr pc, 1f -1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET -2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET -ENDPROC(shmobile_secondary_vector_scu) + b shmobile_invalidate_start +ENDPROC(shmobile_boot_scu) .text .globl shmobile_scu_base diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 96001fd49b6..559d1ce5f57 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -27,7 +27,14 @@ ENDPROC(shmobile_invalidate_start) * We need _long_ jump to the physical address. */ .align 12 -ENTRY(shmobile_secondary_vector) +ENTRY(shmobile_boot_vector) + ldr r0, 2f ldr pc, 1f -1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET -ENDPROC(shmobile_secondary_vector) +ENDPROC(shmobile_boot_vector) + + .globl shmobile_boot_fn +shmobile_boot_fn: +1: .space 4 + .globl shmobile_boot_arg +shmobile_boot_arg: +2: .space 4 diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h index 76ac61292e4..03e56074928 100644 --- a/arch/arm/mach-shmobile/include/mach/clock.h +++ b/arch/arm/mach-shmobile/include/mach/clock.h @@ -24,16 +24,16 @@ struct clk name = { \ } #define SH_FIXED_RATIO_CLK(name, p, r) \ -static SH_FIXED_RATIO_CLKg(name, p, r); +static SH_FIXED_RATIO_CLKg(name, p, r) #define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ SH_CLK_RATIO(name, m, d); \ - SH_FIXED_RATIO_CLK(name, p, name); + SH_FIXED_RATIO_CLK(name, p, name) #define SH_CLK_SET_RATIO(p, m, d) \ -{ \ +do { \ (p)->mul = m; \ (p)->div = d; \ -} +} while (0) #endif diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 4634a5d4b63..e818f029d8e 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -7,8 +7,10 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, unsigned int mult, unsigned int div); struct twd_local_timer; extern void shmobile_setup_console(void); -extern void shmobile_secondary_vector(void); -extern void shmobile_secondary_vector_scu(void); +extern void shmobile_boot_vector(void); +extern unsigned long shmobile_boot_fn; +extern unsigned long shmobile_boot_arg; +extern void shmobile_boot_scu(void); struct clk; extern int shmobile_clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt deleted file mode 100644 index 9f134dfeffd..00000000000 --- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt +++ /dev/null @@ -1,93 +0,0 @@ -LIST "partner-jet-setup.txt" -LIST "(C) Copyright 2010 Renesas Solutions Corp" -LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" - -LIST "RWT Setting" -EW 0xE6020004, 0xA500 -EW 0xE6030004, 0xA500 - -LIST "GPIO Setting" -EB 0xE6051013, 0xA2 - -LIST "CPG" -ED 0xE61500C0, 0x00000002 - -WAIT 1, 0xFE40009C - -LIST "FRQCR" -ED 0xE6150000, 0x2D1305C3 -ED 0xE61500E0, 0x9E40358E -ED 0xE6150004, 0x80331050 - -WAIT 1, 0xFE40009C - -ED 0xE61500E4, 0x00002000 - -WAIT 1, 0xFE40009C - -LIST "PLL" -ED 0xE6150028, 0x00004000 - -WAIT 1, 0xFE40009C - -ED 0xE615002C, 0x93000040 - -WAIT 1, 0xFE40009C - -LIST "SUB/USBClk" -ED 0xE6150080, 0x00000180 - -LIST "BSC" -ED 0xFEC10000, 0x00E0001B - -LIST "SBSC1" -ED 0xFE400354, 0x01AD8000 -ED 0xFE400354, 0x01AD8001 - -WAIT 5, 0xFE40009C - -ED 0xFE400008, 0xBCC90151 -ED 0xFE400040, 0x41774113 -ED 0xFE400044, 0x2712E229 -ED 0xFE400048, 0x20C18505 -ED 0xFE40004C, 0x00110209 -ED 0xFE400010, 0x00000087 - -WAIT 30, 0xFE40009C - -ED 0xFE400084, 0x0000003F -EB 0xFE500000, 0x00 - -WAIT 5, 0xFE40009C - -ED 0xFE400084, 0x0000FF0A -EB 0xFE500000, 0x00 - -WAIT 1, 0xFE40009C - -ED 0xFE400084, 0x00002201 -EB 0xFE500000, 0x00 -ED 0xFE400084, 0x00000302 -EB 0xFE500000, 0x00 -EB 0xFE5C0000, 0x00 -ED 0xFE400008, 0xBCC90159 -ED 0xFE40008C, 0x88800004 -ED 0xFE400094, 0x00000004 -ED 0xFE400028, 0xA55A0032 -ED 0xFE40002C, 0xA55A000C -ED 0xFE400020, 0xA55A2048 -ED 0xFE400008, 0xBCC90959 - -LIST "Change CPGA setting" -ED 0xE61500E0, 0x9E40352E -ED 0xE6150004, 0x80331050 - -WAIT 1, 0xFE40009C - -ED 0xFE400354, 0x01AD8002 - -LIST "SCIF0 - Serial port for earlyprintk" -EB 0xE6053098, 0xe1 -EW 0xE6C40000, 0x0000 -EB 0xE6C40004, 0x19 -EW 0xE6C40008, 0x0030 diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index b2074e2acb1..d241bfd6926 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -16,4 +16,9 @@ #define IRQPIN_BASE 2000 #define irq_pin(nr) ((nr) + IRQPIN_BASE) +/* GPIO IRQ */ +#define _GPIO_IRQ_BASE 2500 +#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) +#define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y) + #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h deleted file mode 100644 index 0ffbe8155c7..00000000000 --- a/arch/arm/mach-shmobile/include/mach/memory.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_MACH_MEMORY_H -#define __ASM_MACH_MEMORY_H - -#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START) -#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) - -#endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h deleted file mode 100644 index db59fdbda86..00000000000 --- a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef MMC_AP4EB_H -#define MMC_AP4EB_H - -#define PORT185CR (void __iomem *)0xe60520b9 -#define PORT186CR (void __iomem *)0xe60520ba -#define PORT187CR (void __iomem *)0xe60520bb -#define PORT188CR (void __iomem *)0xe60520bc - -#define PORTR191_160DR (void __iomem *)0xe6056014 - -static inline void mmc_init_progress(void) -{ - /* Initialise LEDS1-4 - * registers: PORT185CR-PORT188CR (LED1-LED4 Control) - * value: 0x10 - enable output - */ - __raw_writeb(0x10, PORT185CR); - __raw_writeb(0x10, PORT186CR); - __raw_writeb(0x10, PORT187CR); - __raw_writeb(0x10, PORT188CR); -} - -static inline void mmc_update_progress(int n) -{ - __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) | - (1 << (25 + n)), PORTR191_160DR); -} - -#endif /* MMC_AP4EB_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h index 21a59db638b..e979b8fc1da 100644 --- a/arch/arm/mach-shmobile/include/mach/mmc.h +++ b/arch/arm/mach-shmobile/include/mach/mmc.h @@ -7,9 +7,7 @@ * **************************************************/ -#ifdef CONFIG_MACH_AP4EVB -#include "mach/mmc-ap4eb.h" -#elif defined(CONFIG_MACH_MACKEREL) +#ifdef CONFIG_MACH_MACKEREL #include "mach/mmc-mackerel.h" #else #error "unsupported board." diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index 1cf6869b656..b34d19b5ca5 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -28,494 +28,6 @@ #define MD_CK1 (1 << 1) #define MD_CK0 (1 << 0) -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, - - GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, - GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, - - GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, - - /* IRQ */ - GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, - GPIO_FN_IRQ1, - GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, - GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, - GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, - GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, - GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, - GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, - GPIO_FN_IRQ8, - GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, - GPIO_FN_IRQ10, - GPIO_FN_IRQ11, - GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, - GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, - GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, - GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, - GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, - GPIO_FN_IRQ17, - GPIO_FN_IRQ18, - GPIO_FN_IRQ19, - GPIO_FN_IRQ20, - GPIO_FN_IRQ21, - GPIO_FN_IRQ22, - GPIO_FN_IRQ23, - GPIO_FN_IRQ24, - GPIO_FN_IRQ25, - GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, - GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, - GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, - GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, - GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, - GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, - - /* Function */ - - /* DBGT */ - GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, - GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, - GPIO_FN_DBGMD21, - - /* FSI-A */ - GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ - GPIO_FN_FSIAISLD_PORT5, - GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ - GPIO_FN_FSIASPDIF_PORT18, - GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, - GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, - GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, - GPIO_FN_FSIACK, GPIO_FN_FSIAILR, - GPIO_FN_FSIAIBT, - - /* FSI-B */ - GPIO_FN_FSIBCK, - - /* FMSI */ - GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ - GPIO_FN_FMSISLD_PORT6, - GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, - GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, - GPIO_FN_FMSICK, GPIO_FN_FMSOILR, - GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, - GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, - GPIO_FN_FMSOCK, - - /* SCIFA0 */ - GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, - GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_TXD, - - /* SCIFA1 */ - GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, - GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, - GPIO_FN_SCIFA1_RTS, - - /* SCIFA2 */ - GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ - GPIO_FN_SCIFA2_SCK_PORT199, - GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, - GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, - - /* SCIFA3 */ - GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ - GPIO_FN_SCIFA3_SCK_PORT116, - GPIO_FN_SCIFA3_CTS_PORT117, - GPIO_FN_SCIFA3_RXD_PORT174, - GPIO_FN_SCIFA3_TXD_PORT175, - - GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ - GPIO_FN_SCIFA3_SCK_PORT158, - GPIO_FN_SCIFA3_CTS_PORT162, - GPIO_FN_SCIFA3_RXD_PORT159, - GPIO_FN_SCIFA3_TXD_PORT160, - - /* SCIFA4 */ - GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ - GPIO_FN_SCIFA4_TXD_PORT13, - - GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ - GPIO_FN_SCIFA4_TXD_PORT203, - - GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ - GPIO_FN_SCIFA4_TXD_PORT93, - - GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ - GPIO_FN_SCIFA4_SCK_PORT205, - - /* SCIFA5 */ - GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ - GPIO_FN_SCIFA5_RXD_PORT10, - - GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ - GPIO_FN_SCIFA5_TXD_PORT208, - - GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ - GPIO_FN_SCIFA5_RXD_PORT92, - - GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ - GPIO_FN_SCIFA5_SCK_PORT206, - - /* SCIFA6 */ - GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, - - /* SCIFA7 */ - GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, - - /* SCIFAB */ - GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ - GPIO_FN_SCIFB_RXD_PORT191, - GPIO_FN_SCIFB_TXD_PORT192, - GPIO_FN_SCIFB_RTS_PORT186, - GPIO_FN_SCIFB_CTS_PORT187, - - GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ - GPIO_FN_SCIFB_RXD_PORT3, - GPIO_FN_SCIFB_TXD_PORT4, - GPIO_FN_SCIFB_RTS_PORT172, - GPIO_FN_SCIFB_CTS_PORT173, - - /* LCD0 */ - GPIO_FN_LCDC0_SELECT, - - /* LCD1 */ - GPIO_FN_LCDC1_SELECT, - - /* RSPI */ - GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, - GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, - GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, - GPIO_FN_RSPI_CK_A, - - /* VIO CKO */ - GPIO_FN_VIO_CKO1, - GPIO_FN_VIO_CKO2, - GPIO_FN_VIO_CKO_1, - GPIO_FN_VIO_CKO, - - /* VIO0 */ - GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, - GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, - GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, - GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, - GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, - GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, - - GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ - GPIO_FN_VIO0_D14_PORT25, - GPIO_FN_VIO0_D15_PORT24, - - GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ - GPIO_FN_VIO0_D14_PORT95, - GPIO_FN_VIO0_D15_PORT96, - - /* VIO1 */ - GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, - GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, - GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, - GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, - - /* TPU0 */ - GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, - GPIO_FN_TPU0TO3, - GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ - GPIO_FN_TPU0TO2_PORT202, - - /* SSP1 0 */ - GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, - GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, - GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, - GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, - - /* SSP1 1 */ - GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, - GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, - GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, - - GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ - GPIO_FN_STP1_IPEN_PORT187, - - GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ - GPIO_FN_STP1_IPEN_PORT193, - - /* SIM */ - GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, - GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ - GPIO_FN_SIM_D_PORT199, - - /* MSIOF2 */ - GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, - GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_MSIOF2_RSCK, - - /* KEYSC */ - GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, - GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, - GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, - GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, - GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, - - GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ - GPIO_FN_KEYIN1_PORT44, - GPIO_FN_KEYIN2_PORT45, - GPIO_FN_KEYIN3_PORT46, - - GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ - GPIO_FN_KEYIN1_PORT57, - GPIO_FN_KEYIN2_PORT56, - GPIO_FN_KEYIN3_PORT55, - - /* VOU */ - GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, - GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, - GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, - GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, - GPIO_FN_DV_CLK, - GPIO_FN_DV_VSYNC, - GPIO_FN_DV_HSYNC, - - /* MEMC */ - GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, - GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, - GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, - GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, - GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, - GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, - GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, - - GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ - GPIO_FN_MEMC_ADV, - GPIO_FN_MEMC_WAIT, - GPIO_FN_MEMC_BUSCLK, - - GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ - GPIO_FN_MEMC_DREQ0, - GPIO_FN_MEMC_DREQ1, - GPIO_FN_MEMC_A0, - - /* MSIOF0 */ - GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, - GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, - GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, - - /* MSIOF1 */ - GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, - - GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, - GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, - GPIO_FN_MSIOF1_TSYNC_PORT120, - GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ - - GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, - GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, - GPIO_FN_MSIOF1_RXD_PORT75, - GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN_GPO0, GPIO_FN_GPI0, - GPIO_FN_GPO1, GPIO_FN_GPI1, - - /* USB0 */ - GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, - - /* USB1 */ - GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, - - /* BBIF1 */ - GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, - GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, - - /* BBIF2 */ - GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ - GPIO_FN_BBIF2_RXD2_PORT60, - GPIO_FN_BBIF2_TSYNC2_PORT6, - GPIO_FN_BBIF2_TSCK2_PORT59, - - GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ - GPIO_FN_BBIF2_TXD2_PORT183, - GPIO_FN_BBIF2_TSCK2_PORT89, - GPIO_FN_BBIF2_TSYNC2_PORT184, - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, - GPIO_FN_CS5B, GPIO_FN_CS6A, - GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ - GPIO_FN_CS5A_PORT19, - GPIO_FN_IOIS16, /* ? */ - - GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, - GPIO_FN_A4_FOE, /* share with FLCTL */ - GPIO_FN_A5_FCDE, /* share with FLCTL */ - GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, - GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, - GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, - GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, - GPIO_FN_A26, - - GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ - GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ - GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ - GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ - GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ - GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ - GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ - GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ - - GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, - GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, - GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, - GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, - - GPIO_FN_WE0_FWE, /* share with FLCTL */ - GPIO_FN_WE1, - GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ - GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ - GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, - GPIO_FN_RD_FSC, /* share with FLCTL */ - GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ - GPIO_FN_WAIT_PORT90, - - GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ - - /* IRDA */ - GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, - - /* ATAPI */ - GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, - GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, - GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, - GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, - GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, - GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, - GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, - GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, - GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, - GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, - - /* RMII */ - GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, - GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, - GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, - GPIO_FN_RMII_REF50CK, /* for RMII */ - GPIO_FN_RMII_REF125CK, /* for GMII */ - - /* GEther */ - GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, - GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, - GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ - GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ - GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, - GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, - GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, - GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, - GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ - GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ - GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, - GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, - GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, - GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, - - /* DMA0 */ - GPIO_FN_DREQ0, GPIO_FN_DACK0, - - /* DMA1 */ - GPIO_FN_DREQ1, GPIO_FN_DACK1, - - /* SYSC */ - GPIO_FN_RESETOUTS, - GPIO_FN_RESETP_PULLUP, - GPIO_FN_RESETP_PLAIN, - - /* HDMI */ - GPIO_FN_HDMI_HPD, - GPIO_FN_HDMI_CEC, - - /* SDENC */ - GPIO_FN_SDENC_CPG, - GPIO_FN_SDENC_DV_CLKI, - - /* IRREM */ - GPIO_FN_IROUT, - - /* DEBUG */ - GPIO_FN_EDEBGREQ_PULLDOWN, - GPIO_FN_EDEBGREQ_PULLUP, - - GPIO_FN_TRACEAUD_FROM_VIO, - GPIO_FN_TRACEAUD_FROM_LCDC0, - GPIO_FN_TRACEAUD_FROM_MEMC, -}; - /* DMA slave IDs */ enum { SHDMA_SLAVE_INVALID, diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 951149e6bcc..851d027a2f0 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -18,15 +18,26 @@ #ifndef __ASM_R8A7778_H__ #define __ASM_R8A7778_H__ +#include <linux/mmc/sh_mmcif.h> +#include <linux/mmc/sh_mobile_sdhi.h> #include <linux/sh_eth.h> +#include <linux/platform_data/usb-rcar-phy.h> extern void r8a7778_add_standard_devices(void); extern void r8a7778_add_standard_devices_dt(void); extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata); +extern void r8a7778_add_i2c_device(int id); +extern void r8a7778_add_hspi_device(int id); +extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info); + +extern void r8a7778_init_late(void); extern void r8a7778_init_delay(void); extern void r8a7778_init_irq(void); extern void r8a7778_init_irq_dt(void); extern void r8a7778_clock_init(void); extern void r8a7778_init_irq_extpin(int irlm); +extern void r8a7778_pinmux_init(void); +extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info); #endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 188b295938a..fc47073c7ba 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -4,6 +4,7 @@ #include <linux/sh_clk.h> #include <linux/pm_domain.h> #include <linux/sh_eth.h> +#include <linux/platform_data/usb-rcar-phy.h> struct platform_device; @@ -33,6 +34,8 @@ extern void r8a7779_add_early_devices(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); +extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata); +extern void r8a7779_init_late(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index fd7cba024c3..854a9f0ca04 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -15,397 +15,6 @@ #include <linux/pm_domain.h> #include <mach/pm-rmobile.h> -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, - - GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, - GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, - - GPIO_PORT190, - - /* IRQ */ - GPIO_FN_IRQ0_6, /* PORT 6 */ - GPIO_FN_IRQ0_162, /* PORT 162 */ - GPIO_FN_IRQ1, /* PORT 12 */ - GPIO_FN_IRQ2_4, /* PORT 4 */ - GPIO_FN_IRQ2_5, /* PORT 5 */ - GPIO_FN_IRQ3_8, /* PORT 8 */ - GPIO_FN_IRQ3_16, /* PORT 16 */ - GPIO_FN_IRQ4_17, /* PORT 17 */ - GPIO_FN_IRQ4_163, /* PORT 163 */ - GPIO_FN_IRQ5, /* PORT 18 */ - GPIO_FN_IRQ6_39, /* PORT 39 */ - GPIO_FN_IRQ6_164, /* PORT 164 */ - GPIO_FN_IRQ7_40, /* PORT 40 */ - GPIO_FN_IRQ7_167, /* PORT 167 */ - GPIO_FN_IRQ8_41, /* PORT 41 */ - GPIO_FN_IRQ8_168, /* PORT 168 */ - GPIO_FN_IRQ9_42, /* PORT 42 */ - GPIO_FN_IRQ9_169, /* PORT 169 */ - GPIO_FN_IRQ10, /* PORT 65 */ - GPIO_FN_IRQ11, /* PORT 67 */ - GPIO_FN_IRQ12_80, /* PORT 80 */ - GPIO_FN_IRQ12_137, /* PORT 137 */ - GPIO_FN_IRQ13_81, /* PORT 81 */ - GPIO_FN_IRQ13_145, /* PORT 145 */ - GPIO_FN_IRQ14_82, /* PORT 82 */ - GPIO_FN_IRQ14_146, /* PORT 146 */ - GPIO_FN_IRQ15_83, /* PORT 83 */ - GPIO_FN_IRQ15_147, /* PORT 147 */ - GPIO_FN_IRQ16_84, /* PORT 84 */ - GPIO_FN_IRQ16_170, /* PORT 170 */ - GPIO_FN_IRQ17, /* PORT 85 */ - GPIO_FN_IRQ18, /* PORT 86 */ - GPIO_FN_IRQ19, /* PORT 87 */ - GPIO_FN_IRQ20, /* PORT 92 */ - GPIO_FN_IRQ21, /* PORT 93 */ - GPIO_FN_IRQ22, /* PORT 94 */ - GPIO_FN_IRQ23, /* PORT 95 */ - GPIO_FN_IRQ24, /* PORT 112 */ - GPIO_FN_IRQ25, /* PORT 119 */ - GPIO_FN_IRQ26_121, /* PORT 121 */ - GPIO_FN_IRQ26_172, /* PORT 172 */ - GPIO_FN_IRQ27_122, /* PORT 122 */ - GPIO_FN_IRQ27_180, /* PORT 180 */ - GPIO_FN_IRQ28_123, /* PORT 123 */ - GPIO_FN_IRQ28_181, /* PORT 181 */ - GPIO_FN_IRQ29_129, /* PORT 129 */ - GPIO_FN_IRQ29_182, /* PORT 182 */ - GPIO_FN_IRQ30_130, /* PORT 130 */ - GPIO_FN_IRQ30_183, /* PORT 183 */ - GPIO_FN_IRQ31_138, /* PORT 138 */ - GPIO_FN_IRQ31_184, /* PORT 184 */ - - /* - * MSIOF0 (PORT 36, 37, 38, 39 - * 40, 41, 42, 43, 44, 45) - */ - GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_TSCK, - GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_MCK0, - GPIO_FN_MSIOF0_MCK1, GPIO_FN_MSIOF0_SS1, - GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TXD, - - /* - * MSIOF1 (PORT 39, 40, 41, 42, 43, 44 - * 84, 85, 86, 87, 88, 89, 90, 91, 92, 93) - */ - GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40, - GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89, - GPIO_FN_MSIOF1_TXD_41, GPIO_FN_MSIOF1_RXD_42, - GPIO_FN_MSIOF1_TXD_90, GPIO_FN_MSIOF1_RXD_91, - GPIO_FN_MSIOF1_SS1_43, GPIO_FN_MSIOF1_SS2_44, - GPIO_FN_MSIOF1_SS1_92, GPIO_FN_MSIOF1_SS2_93, - GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, - - /* - * MSIOF2 (PORT 134, 135, 136, 137, 138, 139 - * 148, 149, 150, 151) - */ - GPIO_FN_MSIOF2_RSCK, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_MCK1, - GPIO_FN_MSIOF2_SS1, GPIO_FN_MSIOF2_SS2, - GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TXD, - - /* MSIOF3 (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ - GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_TXD, - GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, - GPIO_FN_BBIF1_FLOW, GPIO_FN_BB_RX_FLOW_N, - - /* MSIOF4 (PORT 0, 1, 2, 3) */ - GPIO_FN_BBIF2_TSCK1, GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_BBIF2_TXD1, GPIO_FN_BBIF2_RXD, - - /* FSI (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */ - GPIO_FN_FSIACK, GPIO_FN_FSIBCK, - GPIO_FN_FSIAILR, GPIO_FN_FSIAIBT, - GPIO_FN_FSIAISLD, GPIO_FN_FSIAOMC, - GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, - GPIO_FN_FSIAOSLD, GPIO_FN_FSIASPDIF_11, - GPIO_FN_FSIASPDIF_15, - - /* FMSI (PORT 12, 13, 14, 15, 16, 17, 18, 65) */ - GPIO_FN_FMSOCK, GPIO_FN_FMSOOLR, - GPIO_FN_FMSIOLR, GPIO_FN_FMSOOBT, - GPIO_FN_FMSIOBT, GPIO_FN_FMSOSLD, - GPIO_FN_FMSOILR, GPIO_FN_FMSIILR, - GPIO_FN_FMSOIBT, GPIO_FN_FMSIIBT, - GPIO_FN_FMSISLD, GPIO_FN_FMSICK, - - /* SCIFA0 (PORT 152, 153, 156, 157, 158) */ - GPIO_FN_SCIFA0_TXD, GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_RTS, - GPIO_FN_SCIFA0_CTS, - - /* SCIFA1 (PORT 154, 155, 159, 160, 161) */ - GPIO_FN_SCIFA1_TXD, GPIO_FN_SCIFA1_RXD, - GPIO_FN_SCIFA1_SCK, GPIO_FN_SCIFA1_RTS, - GPIO_FN_SCIFA1_CTS, - - /* SCIFA2 (PORT 94, 95, 96, 97, 98) */ - GPIO_FN_SCIFA2_CTS1, GPIO_FN_SCIFA2_RTS1, - GPIO_FN_SCIFA2_TXD1, GPIO_FN_SCIFA2_RXD1, - GPIO_FN_SCIFA2_SCK1, - - /* SCIFA3 (PORT 43, 44, - 140, 141, 142, 143, 144) */ - GPIO_FN_SCIFA3_CTS_43, GPIO_FN_SCIFA3_CTS_140, - GPIO_FN_SCIFA3_RTS_44, GPIO_FN_SCIFA3_RTS_141, - GPIO_FN_SCIFA3_SCK, GPIO_FN_SCIFA3_TXD, - GPIO_FN_SCIFA3_RXD, - - /* SCIFA4 (PORT 5, 6) */ - GPIO_FN_SCIFA4_RXD, GPIO_FN_SCIFA4_TXD, - - /* SCIFA5 (PORT 8, 12) */ - GPIO_FN_SCIFA5_RXD, GPIO_FN_SCIFA5_TXD, - - /* SCIFB (PORT 162, 163, 164, 165, 166) */ - GPIO_FN_SCIFB_SCK, GPIO_FN_SCIFB_RTS, - GPIO_FN_SCIFB_CTS, GPIO_FN_SCIFB_TXD, - GPIO_FN_SCIFB_RXD, - - /* - * CEU (PORT 16, 17, - * 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, - * 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, - * 120) - */ - GPIO_FN_VIO_HD, GPIO_FN_VIO_CKO1, GPIO_FN_VIO_CKO2, - GPIO_FN_VIO_VD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD, - GPIO_FN_VIO_CKO, - GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2, - GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5, - GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8, - GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11, - GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14, - GPIO_FN_VIO_D15, - - /* USB0 (PORT 113, 114, 115, 116, 117, 167) */ - GPIO_FN_IDIN_0, GPIO_FN_EXTLP_0, - GPIO_FN_OVCN2_0, GPIO_FN_PWEN_0, - GPIO_FN_OVCN_0, GPIO_FN_VBUS0_0, - - /* USB1 (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */ - GPIO_FN_IDIN_1_18, GPIO_FN_IDIN_1_113, - GPIO_FN_PWEN_1_115, GPIO_FN_PWEN_1_138, - GPIO_FN_OVCN_1_114, GPIO_FN_OVCN_1_162, - GPIO_FN_EXTLP_1, GPIO_FN_OVCN2_1, - GPIO_FN_VBUS0_1, - - /* GPIO (PORT 41, 42, 43, 44) */ - GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPO0, GPIO_FN_GPO1, - - /* - * BSC (PORT 19, - * 20, 21, 22, 25, 26, 27, 28, 29, - * 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, - * 40, 41, 42, 43, 44, 45, - * 62, 63, 64, 65, 66, 67, - * 71, 72, 74, 75) - */ - GPIO_FN_BS, GPIO_FN_WE1, - GPIO_FN_CKO, GPIO_FN_WAIT, GPIO_FN_RDWR, - - GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, - GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, - GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, - GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, - GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, - GPIO_FN_A26, - - GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, - GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_CS6A, - - /* - * BSC/FLCTL (PORT 23, 24, - * 46, 47, 48, 49, - * 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, - * 60, 61, 69, 70) - */ - GPIO_FN_RD_FSC, GPIO_FN_WE0_FWE, - GPIO_FN_A4_FOE, GPIO_FN_A5_FCDE, - GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2, - GPIO_FN_D3_NAF3, GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, - GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, GPIO_FN_D8_NAF8, - GPIO_FN_D9_NAF9, GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, - GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, - GPIO_FN_D15_NAF15, - - /* SPU2 (PORT 65) */ - GPIO_FN_VINT_I, - - /* FLCTL (PORT 66, 68, 73) */ - GPIO_FN_FCE1, GPIO_FN_FCE0, GPIO_FN_FRB, - - /* HSI (PORT 76, 77, 78, 79, 80, 81, 82, 83) */ - GPIO_FN_GP_RX_FLAG, GPIO_FN_GP_RX_DATA, GPIO_FN_GP_TX_READY, - GPIO_FN_GP_RX_WAKE, GPIO_FN_MP_TX_FLAG, GPIO_FN_MP_TX_DATA, - GPIO_FN_MP_RX_READY, GPIO_FN_MP_TX_WAKE, - - /* - * MFI (PORT 76, 77, 78, 79, - * 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, - * 90, 91, 92, 93, 94, 95, 96, 97, 98, 99) - */ - GPIO_FN_MFIv6, /* see MSEL4CR 6 */ - GPIO_FN_MFIv4, /* see MSEL4CR 6 */ - - GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_BUSCLK_MEMC_A0, - GPIO_FN_MEMC_CS1_MEMC_A1, GPIO_FN_MEMC_ADV_MEMC_DREQ0, - GPIO_FN_MEMC_WAIT_MEMC_DREQ1, GPIO_FN_MEMC_NOE, - GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_INT, - - GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, - GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, - GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, - GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, - GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, - GPIO_FN_MEMC_AD15, - - /* SIM (PORT 94, 95, 98) */ - GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, GPIO_FN_SIM_D, - - /* TPU (PORT 93, 99, 112, 160, 161) */ - GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, - GPIO_FN_TPU0TO2_93, GPIO_FN_TPU0TO2_99, - GPIO_FN_TPU0TO3, - - /* I2C2 (PORT 110, 111) */ - GPIO_FN_I2C_SCL2, GPIO_FN_I2C_SDA2, - - /* I2C3(1) (PORT 114, 115) */ - GPIO_FN_I2C_SCL3, GPIO_FN_I2C_SDA3, - - /* I2C3(2) (PORT 137, 145) */ - GPIO_FN_I2C_SCL3S, GPIO_FN_I2C_SDA3S, - - /* I2C4(2) (PORT 116, 117) */ - GPIO_FN_I2C_SCL4, GPIO_FN_I2C_SDA4, - - /* I2C4(2) (PORT 146, 147) */ - GPIO_FN_I2C_SCL4S, GPIO_FN_I2C_SDA4S, - - /* - * KEYSC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, - * 130, 131, 132, 133, 134, 135, 136) - */ - GPIO_FN_KEYOUT0, GPIO_FN_KEYIN0_121, GPIO_FN_KEYIN0_136, - GPIO_FN_KEYOUT1, GPIO_FN_KEYIN1_122, GPIO_FN_KEYIN1_135, - GPIO_FN_KEYOUT2, GPIO_FN_KEYIN2_123, GPIO_FN_KEYIN2_134, - GPIO_FN_KEYOUT3, GPIO_FN_KEYIN3_124, GPIO_FN_KEYIN3_133, - GPIO_FN_KEYOUT4, GPIO_FN_KEYIN4, - GPIO_FN_KEYOUT5, GPIO_FN_KEYIN5, - GPIO_FN_KEYOUT6, GPIO_FN_KEYIN6, - GPIO_FN_KEYOUT7, GPIO_FN_KEYIN7, - - /* - * LCDC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129, - * 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, - * 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, - * 150, 151) - */ - GPIO_FN_LCDC0_SELECT, /* LCDC 0 */ - GPIO_FN_LCDC1_SELECT, /* LCDC 1 */ - GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDVSYN, - GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDRD, - GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDLCLK, - GPIO_FN_LCDDON, - - GPIO_FN_LCDD0, GPIO_FN_LCDD1, GPIO_FN_LCDD2, GPIO_FN_LCDD3, - GPIO_FN_LCDD4, GPIO_FN_LCDD5, GPIO_FN_LCDD6, GPIO_FN_LCDD7, - GPIO_FN_LCDD8, GPIO_FN_LCDD9, GPIO_FN_LCDD10, GPIO_FN_LCDD11, - GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15, - GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19, - GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23, - - /* IRDA (PORT 139, 140, 141, 142) */ - GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL, - GPIO_FN_IROUT_139, GPIO_FN_IROUT_140, - - /* TSIF1 (PORT 156, 157, 158, 159) */ - GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */ - GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */ - GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */ - GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */ - - GPIO_FN_TS_SPSYNC1, GPIO_FN_TS_SDAT1, - GPIO_FN_TS_SDEN1, GPIO_FN_TS_SCK1, - - /* TSIF2 (PORT 137, 145, 146, 147) */ - GPIO_FN_TS_SPSYNC2, GPIO_FN_TS_SDAT2, - GPIO_FN_TS_SDEN2, GPIO_FN_TS_SCK2, - - /* HDMI (PORT 169, 170) */ - GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, - - /* SDENC see MSEL4CR 19 */ - GPIO_FN_SDENC_CPG, - GPIO_FN_SDENC_DV_CLKI, -}; - /* DMA slave IDs */ enum { SHDMA_SLAVE_INVALID, @@ -466,6 +75,8 @@ extern void sh7372_intcs_resume(void); extern void sh7372_intca_suspend(void); extern void sh7372_intca_resume(void); +extern unsigned long sh7372_cpu_resume; + #ifdef CONFIG_PM extern void __init sh7372_init_pm_domains(void); #else diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h index 9320aff0a20..f2d8744c1f1 100644 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -10,11 +10,9 @@ * **************************************************/ -#ifdef CONFIG_MACH_AP4EVB -#define MACH_TYPE MACH_TYPE_AP4EVB -#include "mach/head-ap4evb.txt" -#elif defined(CONFIG_MACH_MACKEREL) +#ifdef CONFIG_MACH_MACKEREL #define MACH_TYPE MACH_TYPE_MACKEREL +#define MEMORY_START 0x40000000 #include "mach/head-mackerel.txt" #else #error "unsupported board." diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index dec9293bb90..0de75fd394b 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c @@ -351,6 +351,9 @@ static void sh7372_enter_a4s_common(int pllc0_on) static void sh7372_pm_setup_smfram(void) { + /* pass physical address of cpu_resume() to assembly resume code */ + sh7372_cpu_resume = virt_to_phys(cpu_resume); + memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); } #else diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 9284e6fdb0c..00c5a707238 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -70,29 +70,15 @@ void __init r8a7740_map_io(void) } /* PFC */ -static struct resource r8a7740_pfc_resources[] = { - [0] = { - .start = 0xe6050000, - .end = 0xe6057fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xe605800c, - .end = 0xe605802b, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device r8a7740_pfc_device = { - .name = "pfc-r8a7740", - .id = -1, - .resource = r8a7740_pfc_resources, - .num_resources = ARRAY_SIZE(r8a7740_pfc_resources), +static const struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xe6050000, 0x8000), + DEFINE_RES_MEM(0xe605800c, 0x0020), }; void __init r8a7740_pinmux_init(void) { - platform_device_register(&r8a7740_pfc_device); + platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, + ARRAY_SIZE(pfc_resources)); } static struct renesas_intc_irqpin_config irqpin0_platform_data = { diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 30b4a336308..80c20392ad7 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -24,11 +24,18 @@ #include <linux/irqchip/arm-gic.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <linux/platform_device.h> #include <linux/irqchip.h> #include <linux/serial_sci.h> #include <linux/sh_timer.h> +#include <linux/pm_runtime.h> +#include <linux/usb/phy.h> +#include <linux/usb/hcd.h> +#include <linux/usb/ehci_pdriver.h> +#include <linux/usb/ohci_pdriver.h> +#include <linux/dma-mapping.h> #include <mach/irqs.h> #include <mach/r8a7778.h> #include <mach/common.h> @@ -80,12 +87,6 @@ static struct sh_timer_config sh_tmu1_platform_data = { .clocksource_rating = 200, }; -/* Ether */ -static struct resource ether_resources[] = { - DEFINE_RES_MEM(0xfde00000, 0x400), - DEFINE_RES_IRQ(gic_iid(0x89)), -}; - #define r8a7778_register_tmu(idx) \ platform_device_register_resndata( \ &platform_bus, "sh_tmu", idx, \ @@ -94,6 +95,244 @@ static struct resource ether_resources[] = { &sh_tmu##idx##_platform_data, \ sizeof(sh_tmu##idx##_platform_data)) +/* USB PHY */ +static struct resource usb_phy_resources[] __initdata = { + DEFINE_RES_MEM(0xffe70800, 0x100), + DEFINE_RES_MEM(0xffe76000, 0x100), +}; + +void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, + usb_phy_resources, + ARRAY_SIZE(usb_phy_resources), + pdata, sizeof(*pdata)); +} + +/* USB */ +static struct usb_phy *phy; + +static int usb_power_on(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return PTR_ERR(phy); + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + usb_phy_init(phy); + + return 0; +} + +static void usb_power_off(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return; + + usb_phy_shutdown(phy); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); +} + +static int ehci_init_internal_buffer(struct usb_hcd *hcd) +{ + /* + * Below are recommended values from the datasheet; + * see [USB :: Setting of EHCI Internal Buffer]. + */ + /* EHCI IP internal buffer setting */ + iowrite32(0x00ff0040, hcd->regs + 0x0094); + /* EHCI IP internal buffer enable */ + iowrite32(0x00000001, hcd->regs + 0x009C); + + return 0; +} + +static struct usb_ehci_pdata ehci_pdata __initdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, + .pre_setup = ehci_init_internal_buffer, +}; + +static struct resource ehci_resources[] __initdata = { + DEFINE_RES_MEM(0xffe70000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x4c)), +}; + +static struct usb_ohci_pdata ohci_pdata __initdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, +}; + +static struct resource ohci_resources[] __initdata = { + DEFINE_RES_MEM(0xffe70400, 0x400), + DEFINE_RES_IRQ(gic_iid(0x4c)), +}; + +#define USB_PLATFORM_INFO(hci) \ +static struct platform_device_info hci##_info __initdata = { \ + .parent = &platform_bus, \ + .name = #hci "-platform", \ + .id = -1, \ + .res = hci##_resources, \ + .num_res = ARRAY_SIZE(hci##_resources), \ + .data = &hci##_pdata, \ + .size_data = sizeof(hci##_pdata), \ + .dma_mask = DMA_BIT_MASK(32), \ +} + +USB_PLATFORM_INFO(ehci); +USB_PLATFORM_INFO(ohci); + +/* Ether */ +static struct resource ether_resources[] = { + DEFINE_RES_MEM(0xfde00000, 0x400), + DEFINE_RES_IRQ(gic_iid(0x89)), +}; + +void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, + ether_resources, + ARRAY_SIZE(ether_resources), + pdata, sizeof(*pdata)); +} + +/* PFC/GPIO */ +static struct resource pfc_resources[] = { + DEFINE_RES_MEM(0xfffc0000, 0x118), +}; + +#define R8A7778_GPIO(idx) \ +static struct resource r8a7778_gpio##idx##_resources[] = { \ + DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ + DEFINE_RES_IRQ(gic_iid(0x87)), \ +}; \ + \ +static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ + .gpio_base = 32 * (idx), \ + .irq_base = GPIO_IRQ_BASE(idx), \ + .number_of_pins = 32, \ + .pctl_name = "pfc-r8a7778", \ +} + +R8A7778_GPIO(0); +R8A7778_GPIO(1); +R8A7778_GPIO(2); +R8A7778_GPIO(3); +R8A7778_GPIO(4); + +#define r8a7778_register_gpio(idx) \ + platform_device_register_resndata( \ + &platform_bus, "gpio_rcar", idx, \ + r8a7778_gpio##idx##_resources, \ + ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ + &r8a7778_gpio##idx##_platform_data, \ + sizeof(r8a7778_gpio##idx##_platform_data)) + +void __init r8a7778_pinmux_init(void) +{ + platform_device_register_simple( + "pfc-r8a7778", -1, + pfc_resources, + ARRAY_SIZE(pfc_resources)); + + r8a7778_register_gpio(0); + r8a7778_register_gpio(1); + r8a7778_register_gpio(2); + r8a7778_register_gpio(3); + r8a7778_register_gpio(4); +}; + +/* SDHI */ +static struct resource sdhi_resources[] = { + /* SDHI0 */ + DEFINE_RES_MEM(0xFFE4C000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x77)), + /* SDHI1 */ + DEFINE_RES_MEM(0xFFE4D000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x78)), + /* SDHI2 */ + DEFINE_RES_MEM(0xFFE4F000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x76)), +}; + +void __init r8a7778_sdhi_init(int id, + struct sh_mobile_sdhi_info *info) +{ + BUG_ON(id < 0 || id > 2); + + platform_device_register_resndata( + &platform_bus, "sh_mobile_sdhi", id, + sdhi_resources + (2 * id), 2, + info, sizeof(*info)); +} + +/* I2C */ +static struct resource i2c_resources[] __initdata = { + /* I2C0 */ + DEFINE_RES_MEM(0xffc70000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x63)), + /* I2C1 */ + DEFINE_RES_MEM(0xffc71000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x6e)), + /* I2C2 */ + DEFINE_RES_MEM(0xffc72000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x6c)), + /* I2C3 */ + DEFINE_RES_MEM(0xffc73000, 0x1000), + DEFINE_RES_IRQ(gic_iid(0x6d)), +}; + +void __init r8a7778_add_i2c_device(int id) +{ + BUG_ON(id < 0 || id > 3); + + platform_device_register_simple( + "i2c-rcar", id, + i2c_resources + (2 * id), 2); +} + +/* HSPI */ +static struct resource hspi_resources[] __initdata = { + /* HSPI0 */ + DEFINE_RES_MEM(0xfffc7000, 0x18), + DEFINE_RES_IRQ(gic_iid(0x5f)), + /* HSPI1 */ + DEFINE_RES_MEM(0xfffc8000, 0x18), + DEFINE_RES_IRQ(gic_iid(0x74)), + /* HSPI2 */ + DEFINE_RES_MEM(0xfffc6000, 0x18), + DEFINE_RES_IRQ(gic_iid(0x75)), +}; + +void __init r8a7778_add_hspi_device(int id) +{ + BUG_ON(id < 0 || id > 2); + + platform_device_register_simple( + "sh-hspi", id, + hspi_resources + (2 * id), 2); +} + +/* MMC */ +static struct resource mmc_resources[] __initdata = { + DEFINE_RES_MEM(0xffe4e000, 0x100), + DEFINE_RES_IRQ(gic_iid(0x5d)), +}; + +void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info) +{ + platform_device_register_resndata( + &platform_bus, "sh_mmcif", -1, + mmc_resources, ARRAY_SIZE(mmc_resources), + info, sizeof(*info)); +} + void __init r8a7778_add_standard_devices(void) { int i; @@ -118,12 +357,12 @@ void __init r8a7778_add_standard_devices(void) r8a7778_register_tmu(1); } -void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) +void __init r8a7778_init_late(void) { - platform_device_register_resndata(&platform_bus, "sh_eth", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); + phy = usb_get_phy(USB_PHY_TYPE_USB2); + + platform_device_register_full(&ehci_info); + platform_device_register_full(&ohci_info); } static struct renesas_intc_irqpin_config irqpin_platform_data = { @@ -239,6 +478,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") .init_machine = r8a7778_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = r8a7778_compat_dt, + .init_late = r8a7778_init_late, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index b0b394842ea..398687761f5 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -32,6 +32,11 @@ #include <linux/sh_intc.h> #include <linux/sh_timer.h> #include <linux/dma-mapping.h> +#include <linux/usb/otg.h> +#include <linux/usb/hcd.h> +#include <linux/usb/ehci_pdriver.h> +#include <linux/usb/ohci_pdriver.h> +#include <linux/pm_runtime.h> #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/r8a7779.h> @@ -65,11 +70,7 @@ void __init r8a7779_map_io(void) } static struct resource r8a7779_pfc_resources[] = { - [0] = { - .start = 0xfffc0000, - .end = 0xfffc023b, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(0xfffc0000, 0x023c), }; static struct platform_device r8a7779_pfc_device = { @@ -81,15 +82,8 @@ static struct platform_device r8a7779_pfc_device = { #define R8A7779_GPIO(idx, npins) \ static struct resource r8a7779_gpio##idx##_resources[] = { \ - [0] = { \ - .start = 0xffc40000 + 0x1000 * (idx), \ - .end = 0xffc4002b + 0x1000 * (idx), \ - .flags = IORESOURCE_MEM, \ - }, \ - [1] = { \ - .start = gic_iid(0xad + (idx)), \ - .flags = IORESOURCE_IRQ, \ - } \ + DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ + DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ }; \ \ static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ @@ -394,6 +388,165 @@ static struct platform_device sata_device = { }, }; +/* USB PHY */ +static struct resource usb_phy_resources[] __initdata = { + [0] = { + .start = 0xffe70800, + .end = 0xffe70900 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +/* USB */ +static struct usb_phy *phy; + +static int usb_power_on(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return PTR_ERR(phy); + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + usb_phy_init(phy); + + return 0; +} + +static void usb_power_off(struct platform_device *pdev) +{ + if (IS_ERR(phy)) + return; + + usb_phy_shutdown(phy); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); +} + +static int ehci_init_internal_buffer(struct usb_hcd *hcd) +{ + /* + * Below are recommended values from the datasheet; + * see [USB :: Setting of EHCI Internal Buffer]. + */ + /* EHCI IP internal buffer setting */ + iowrite32(0x00ff0040, hcd->regs + 0x0094); + /* EHCI IP internal buffer enable */ + iowrite32(0x00000001, hcd->regs + 0x009C); + + return 0; +} + +static struct usb_ehci_pdata ehcix_pdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, + .pre_setup = ehci_init_internal_buffer, +}; + +static struct resource ehci0_resources[] = { + [0] = { + .start = 0xffe70000, + .end = 0xffe70400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4c), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ehci0_device = { + .name = "ehci-platform", + .id = 0, + .dev = { + .dma_mask = &ehci0_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ehcix_pdata, + }, + .num_resources = ARRAY_SIZE(ehci0_resources), + .resource = ehci0_resources, +}; + +static struct resource ehci1_resources[] = { + [0] = { + .start = 0xfff70000, + .end = 0xfff70400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4d), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ehci1_device = { + .name = "ehci-platform", + .id = 1, + .dev = { + .dma_mask = &ehci1_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ehcix_pdata, + }, + .num_resources = ARRAY_SIZE(ehci1_resources), + .resource = ehci1_resources, +}; + +static struct usb_ohci_pdata ohcix_pdata = { + .power_on = usb_power_on, + .power_off = usb_power_off, + .power_suspend = usb_power_off, +}; + +static struct resource ohci0_resources[] = { + [0] = { + .start = 0xffe70400, + .end = 0xffe70800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4c), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci0_device = { + .name = "ohci-platform", + .id = 0, + .dev = { + .dma_mask = &ohci0_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ohcix_pdata, + }, + .num_resources = ARRAY_SIZE(ohci0_resources), + .resource = ohci0_resources, +}; + +static struct resource ohci1_resources[] = { + [0] = { + .start = 0xfff70400, + .end = 0xfff70800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gic_iid(0x4d), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci1_device = { + .name = "ohci-platform", + .id = 1, + .dev = { + .dma_mask = &ohci1_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &ohcix_pdata, + }, + .num_resources = ARRAY_SIZE(ohci1_resources), + .resource = ohci1_resources, +}; + /* Ether */ static struct resource ether_resources[] = { { @@ -417,7 +570,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { &tmu01_device, }; -static struct platform_device *r8a7779_late_devices[] __initdata = { +static struct platform_device *r8a7779_standard_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, @@ -437,18 +590,26 @@ void __init r8a7779_add_standard_devices(void) platform_add_devices(r8a7779_devices_dt, ARRAY_SIZE(r8a7779_devices_dt)); - platform_add_devices(r8a7779_late_devices, - ARRAY_SIZE(r8a7779_late_devices)); + platform_add_devices(r8a7779_standard_devices, + ARRAY_SIZE(r8a7779_standard_devices)); } void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) { - platform_device_register_resndata(&platform_bus, "sh_eth", -1, + platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, ether_resources, ARRAY_SIZE(ether_resources), pdata, sizeof(*pdata)); } +void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata) +{ + platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1, + usb_phy_resources, + ARRAY_SIZE(usb_phy_resources), + pdata, sizeof(*pdata)); +} + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } @@ -481,6 +642,23 @@ void __init r8a7779_add_early_devices(void) */ } +static struct platform_device *r8a7779_late_devices[] __initdata = { + &ehci0_device, + &ehci1_device, + &ohci0_device, + &ohci1_device, +}; + +void __init r8a7779_init_late(void) +{ + /* get USB PHY */ + phy = usb_get_phy(USB_PHY_TYPE_USB2); + + shmobile_init_late(); + platform_add_devices(r8a7779_late_devices, + ARRAY_SIZE(r8a7779_late_devices)); +} + #ifdef CONFIG_USE_OF void __init r8a7779_init_delay(void) { @@ -514,6 +692,7 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .init_irq = r8a7779_init_irq_dt, .init_machine = r8a7779_add_standard_devices_dt, .init_time = shmobile_timer_init, + .init_late = r8a7779_init_late, .dt_compat = r8a7779_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 49de2d56f86..b461d93431e 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -23,6 +23,7 @@ #include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/serial_sci.h> +#include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-irqc.h> #include <mach/common.h> #include <mach/irqs.h> @@ -31,13 +32,46 @@ static const struct resource pfc_resources[] = { DEFINE_RES_MEM(0xe6060000, 0x250), - DEFINE_RES_MEM(0xe6050000, 0x5050), }; +#define R8A7790_GPIO(idx) \ +static struct resource r8a7790_gpio##idx##_resources[] = { \ + DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ + DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ +}; \ + \ +static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = { \ + .gpio_base = 32 * (idx), \ + .irq_base = 0, \ + .number_of_pins = 32, \ + .pctl_name = "pfc-r8a7790", \ + .has_both_edge_trigger = 1, \ +}; \ + +R8A7790_GPIO(0); +R8A7790_GPIO(1); +R8A7790_GPIO(2); +R8A7790_GPIO(3); +R8A7790_GPIO(4); +R8A7790_GPIO(5); + +#define r8a7790_register_gpio(idx) \ + platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ + r8a7790_gpio##idx##_resources, \ + ARRAY_SIZE(r8a7790_gpio##idx##_resources), \ + &r8a7790_gpio##idx##_platform_data, \ + sizeof(r8a7790_gpio##idx##_platform_data)) + void __init r8a7790_pinmux_init(void) { platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, ARRAY_SIZE(pfc_resources)); + r8a7790_register_gpio(0); + r8a7790_register_gpio(1); + r8a7790_register_gpio(2); + r8a7790_register_gpio(3); + r8a7790_register_gpio(4); + r8a7790_register_gpio(5); } #define SCIF_COMMON(scif_type, baseaddr, irq) \ diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 9696f364686..96e7ca1e4e1 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = { }; static struct resource tmu00_resources[] = { - [0] = { - .name = "TMU00", - .start = 0xfff60008, - .end = 0xfff60013, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), [1] = { .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ .flags = IORESOURCE_IRQ, @@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = { }; static struct resource tmu01_resources[] = { - [0] = { - .name = "TMU01", - .start = 0xfff60014, - .end = 0xfff6001f, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), [1] = { .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ .flags = IORESOURCE_IRQ, @@ -341,12 +331,7 @@ static struct platform_device tmu01_device = { }; static struct resource i2c0_resources[] = { - [0] = { - .name = "IIC0", - .start = 0xe6820000, - .end = 0xe6820425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), [1] = { .start = gic_spi(167), .end = gic_spi(170), @@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = { }; static struct resource i2c1_resources[] = { - [0] = { - .name = "IIC1", - .start = 0xe6822000, - .end = 0xe6822425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), [1] = { .start = gic_spi(51), .end = gic_spi(54), @@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = { }; static struct resource i2c2_resources[] = { - [0] = { - .name = "IIC2", - .start = 0xe6824000, - .end = 0xe6824425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), [1] = { .start = gic_spi(171), .end = gic_spi(174), @@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = { }; static struct resource i2c3_resources[] = { - [0] = { - .name = "IIC3", - .start = 0xe6826000, - .end = 0xe6826425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), [1] = { .start = gic_spi(183), .end = gic_spi(186), @@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = { }; static struct resource i2c4_resources[] = { - [0] = { - .name = "IIC4", - .start = 0xe6828000, - .end = 0xe6828425 - 1, - .flags = IORESOURCE_MEM, - }, + [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), [1] = { .start = gic_spi(187), .end = gic_spi(190), @@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = { }; static struct resource sh73a0_dmae_resources[] = { - { - /* Registers including DMAOR and channels including DMARSx */ - .start = 0xfe000020, - .end = 0xfe008a00 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(0xfe000020, 0x89e0), { .name = "error_irq", .start = gic_spi(129), @@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { /* Resource order important! */ static struct resource sh73a0_mpdma_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xec618020, - .end = 0xec61828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xec619000, - .end = 0xec61900b, - .flags = IORESOURCE_MEM, - }, + /* Channel registers and DMAOR */ + DEFINE_RES_MEM(0xec618020, 0x270), + /* DMARSx */ + DEFINE_RES_MEM(0xec619000, 0xc), { .name = "error_irq", .start = gic_spi(181), @@ -785,12 +737,7 @@ static struct platform_device pmu_device = { /* an IPMMU module for ICB */ static struct resource ipmmu_resources[] = { - [0] = { - .name = "IPMMU", - .start = 0xfe951000, - .end = 0xfe9510ff, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), }; static const char * const ipmmu_dev_names[] = { @@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void) ARRAY_SIZE(sh73a0_late_devices)); } +void __init sh73a0_init_delay(void) +{ + shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ +} + /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak sh73a0_register_twd(void) { } void __init sh73a0_earlytimer_init(void) { + sh73a0_init_delay(); sh73a0_clock_init(); shmobile_earlytimer_init(); sh73a0_register_twd(); @@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init sh73a0_init_delay(void) -{ - shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ -} - static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { {}, }; void __init sh73a0_add_standard_devices_dt(void) { + struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; + /* clocks are setup late during boot in the case of DT */ sh73a0_clock_init(); @@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void) ARRAY_SIZE(sh73a0_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, sh73a0_auxdata_lookup, NULL); + + /* Instantiate cpufreq-cpu0 */ + platform_device_register_full(&devinfo); } static const char *sh73a0_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index a9df53b69ab..53f4840e494 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -40,7 +40,10 @@ .global sh7372_resume_core_standby_sysc sh7372_resume_core_standby_sysc: ldr pc, 1f -1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET + + .globl sh7372_cpu_resume +sh7372_cpu_resume: +1: .space 4 #define SPDCR 0xe6180008 diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index e38691b4d0d..80991b35f4a 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -40,8 +40,10 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(shmobile_scu_base); - /* Tell ROM loader about our vector (in headsmp-scu.S) */ - emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); + /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */ + emev2_set_boot_vector(__pa(shmobile_boot_vector)); + shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); + shmobile_boot_arg = (unsigned long)shmobile_scu_base; /* enable cache coherency on booting CPU */ scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index a853bf182ed..526cfaae81c 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -101,8 +101,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(shmobile_scu_base); - /* Map the reset vector (in headsmp-scu.S) */ - __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ + __raw_writel(__pa(shmobile_boot_vector), AVECR); + shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); + shmobile_boot_arg = (unsigned long)shmobile_scu_base; /* enable cache coherency on booting CPU */ scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 496592b6c76..d613113a04b 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -64,9 +64,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { scu_enable(shmobile_scu_base); - /* Map the reset vector (in headsmp-scu.S) */ + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); + __raw_writel(__pa(shmobile_boot_vector), SBAR); + shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); + shmobile_boot_arg = (unsigned long)shmobile_scu_base; /* enable cache coherency on booting CPU */ scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 566e804d403..dd86db46752 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -7,11 +7,11 @@ config ARCH_SOCFPGA select CLKDEV_LOOKUP select COMMON_CLK select CPU_V7 - select DW_APB_TIMER select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select GPIO_PL061 if GPIOLIB select HAVE_ARM_SCU select HAVE_SMP + select MFD_SYSCON select SPARSE_IRQ select USE_OF diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 46a051359f0..8ea11b472b9 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -14,7 +14,6 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <linux/dw_apb_timer.h> #include <linux/clk-provider.h> #include <linux/irqchip.h> #include <linux/of_address.h> @@ -120,7 +119,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .smp = smp_ops(socfpga_smp_ops), .map_io = socfpga_map_io, .init_irq = socfpga_init_irq, - .init_time = dw_apb_timer_init, .init_machine = socfpga_cyclone5_init, .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c index 9eaac2c881e..7ad003001ab 100644 --- a/arch/arm/mach-spear/spear1310.c +++ b/arch/arm/mach-spear/spear1310.c @@ -14,7 +14,6 @@ #define pr_fmt(fmt) "SPEAr1310: " fmt #include <linux/amba/pl022.h> -#include <linux/irqchip.h> #include <linux/of_platform.h> #include <linux/pata_arasan_cf_data.h> #include <asm/mach/arch.h> @@ -60,7 +59,6 @@ static void __init spear1310_map_io(void) DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") .smp = smp_ops(spear13xx_smp_ops), .map_io = spear1310_map_io, - .init_irq = irqchip_init, .init_time = spear13xx_timer_init, .init_machine = spear1310_dt_init, .restart = spear_restart, diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c index a04a7fe76f7..3fb68342472 100644 --- a/arch/arm/mach-spear/spear1340.c +++ b/arch/arm/mach-spear/spear1340.c @@ -17,7 +17,6 @@ #include <linux/amba/serial.h> #include <linux/delay.h> #include <linux/of_platform.h> -#include <linux/irqchip.h> #include <asm/mach/arch.h> #include "generic.h" #include <mach/spear.h> @@ -155,7 +154,6 @@ static const char * const spear1340_dt_board_compat[] = { DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") .smp = smp_ops(spear13xx_smp_ops), .map_io = spear13xx_map_io, - .init_irq = irqchip_init, .init_time = spear13xx_timer_init, .init_machine = spear1340_dt_init, .restart = spear_restart, diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c index bac56e845f7..b52e48f342f 100644 --- a/arch/arm/mach-spear/spear300.c +++ b/arch/arm/mach-spear/spear300.c @@ -14,7 +14,6 @@ #define pr_fmt(fmt) "SPEAr300: " fmt #include <linux/amba/pl08x.h> -#include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include "generic.h" @@ -212,7 +211,6 @@ static void __init spear300_map_io(void) DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") .map_io = spear300_map_io, - .init_irq = irqchip_init, .init_time = spear3xx_timer_init, .init_machine = spear300_dt_init, .restart = spear_restart, diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c index 6ffbc63d516..ed2029db391 100644 --- a/arch/arm/mach-spear/spear310.c +++ b/arch/arm/mach-spear/spear310.c @@ -15,7 +15,6 @@ #include <linux/amba/pl08x.h> #include <linux/amba/serial.h> -#include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include "generic.h" @@ -254,7 +253,6 @@ static void __init spear310_map_io(void) DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") .map_io = spear310_map_io, - .init_irq = irqchip_init, .init_time = spear3xx_timer_init, .init_machine = spear310_dt_init, .restart = spear_restart, diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c index 6eb3eec65f9..bf634b32a93 100644 --- a/arch/arm/mach-spear/spear320.c +++ b/arch/arm/mach-spear/spear320.c @@ -16,7 +16,6 @@ #include <linux/amba/pl022.h> #include <linux/amba/pl08x.h> #include <linux/amba/serial.h> -#include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -269,7 +268,6 @@ static void __init spear320_map_io(void) DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") .map_io = spear320_map_io, - .init_irq = irqchip_init, .init_time = spear3xx_timer_init, .init_machine = spear320_dt_init, .restart = spear_restart, diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c index ec8eefbbdfa..8b0295a4122 100644 --- a/arch/arm/mach-spear/spear6xx.c +++ b/arch/arm/mach-spear/spear6xx.c @@ -16,7 +16,6 @@ #include <linux/amba/pl08x.h> #include <linux/clk.h> #include <linux/err.h> -#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_platform.h> @@ -423,7 +422,6 @@ static const char *spear600_dt_board_compat[] = { DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)") .map_io = spear6xx_map_io, - .init_irq = irqchip_init, .init_time = spear6xx_timer_init, .init_machine = spear600_dt_init, .restart = spear_restart, diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 706ce35396b..84485a10fc3 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -14,7 +14,6 @@ #include <linux/delay.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> @@ -26,8 +25,6 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> -#include "sunxi.h" - #define SUN4I_WATCHDOG_CTRL_REG 0x00 #define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) #define SUN4I_WATCHDOG_MODE_REG 0x04 @@ -81,20 +78,6 @@ static void sunxi_setup_restart(void) arm_pm_restart = of_id->data; } -static struct map_desc sunxi_io_desc[] __initdata = { - { - .virtual = (unsigned long) SUNXI_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE), - .length = SUNXI_REGS_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init sunxi_map_io(void) -{ - iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc)); -} - static void __init sunxi_timer_init(void) { sunxi_init_clocks(); @@ -110,14 +93,13 @@ static void __init sunxi_dt_init(void) static const char * const sunxi_board_dt_compat[] = { "allwinner,sun4i-a10", + "allwinner,sun5i-a10s", "allwinner,sun5i-a13", NULL, }; DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") .init_machine = sunxi_dt_init, - .map_io = sunxi_map_io, - .init_irq = irqchip_init, .init_time = sunxi_timer_init, .dt_compat = sunxi_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h deleted file mode 100644 index 33b58712ade..00000000000 --- a/arch/arm/mach-sunxi/sunxi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Generic definitions for Allwinner SunXi SoCs - * - * Copyright (C) 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_SUNXI_H -#define __MACH_SUNXI_H - -#define SUNXI_REGS_PHYS_BASE 0x01c00000 -#define SUNXI_REGS_VIRT_BASE IOMEM(0xf1c00000) -#define SUNXI_REGS_SIZE (SZ_2M + SZ_1M) - -#endif /* __MACH_SUNXI_H */ diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index d011f0ad49c..98b184efc11 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 9f852c6fe5b..ec5836b1e71 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -29,6 +29,7 @@ #include "board.h" #include "common.h" +#include "cpuidle.h" #include "fuse.h" #include "iomap.h" #include "irq.h" @@ -108,5 +109,6 @@ void __init tegra_init_early(void) void __init tegra_init_late(void) { tegra_init_suspend(); + tegra_cpuidle_init(); tegra_powergate_debugfs_init(); } diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 5900cc44f78..32f8eb3fe34 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops; extern int tegra_cpu_kill(unsigned int cpu); extern void tegra_cpu_die(unsigned int cpu); +extern int tegra_cpu_disable(unsigned int cpu); diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index 0cdba8de8c7..706aa4215c3 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -177,7 +177,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; bool entered_lp2 = false; if (tegra_pending_sgi()) @@ -193,16 +192,16 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, local_fiq_disable(); - tegra_set_cpu_in_lp2(cpu); + tegra_set_cpu_in_lp2(); cpu_pm_enter(); - if (cpu == 0) + if (dev->cpu == 0) entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); else entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); cpu_pm_exit(); - tegra_clear_cpu_in_lp2(cpu); + tegra_clear_cpu_in_lp2(); local_fiq_enable(); @@ -214,8 +213,5 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, int __init tegra20_cpuidle_init(void) { -#ifdef CONFIG_PM_SLEEP - tegra_tear_down_cpu = tegra20_tear_down_cpu; -#endif return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); } diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 3cf9aca5f3e..ed2a2a7bae4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -114,16 +114,15 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; bool entered_lp2 = false; bool last_cpu; local_fiq_disable(); - last_cpu = tegra_set_cpu_in_lp2(cpu); + last_cpu = tegra_set_cpu_in_lp2(); cpu_pm_enter(); - if (cpu == 0) { + if (dev->cpu == 0) { if (last_cpu) entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index); @@ -134,7 +133,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, } cpu_pm_exit(); - tegra_clear_cpu_in_lp2(cpu); + tegra_clear_cpu_in_lp2(); local_fiq_enable(); @@ -146,8 +145,5 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev, int __init tegra30_cpuidle_init(void) { -#ifdef CONFIG_PM_SLEEP - tegra_tear_down_cpu = tegra30_tear_down_cpu; -#endif return cpuidle_register(&tegra_idle_driver, NULL); } diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 4b744c4661e..e85973cef03 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -27,25 +27,20 @@ #include "fuse.h" #include "cpuidle.h" -static int __init tegra_cpuidle_init(void) +void __init tegra_cpuidle_init(void) { - int ret; - switch (tegra_chip_id) { case TEGRA20: - ret = tegra20_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra20_cpuidle_init(); break; case TEGRA30: - ret = tegra30_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) + tegra30_cpuidle_init(); break; case TEGRA114: - ret = tegra114_cpuidle_init(); - break; - default: - ret = -ENODEV; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) + tegra114_cpuidle_init(); break; } - - return ret; } -device_initcall(tegra_cpuidle_init); diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index d733f75d020..9ec2c1ab0fa 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -17,22 +17,13 @@ #ifndef __MACH_TEGRA_CPUIDLE_H #define __MACH_TEGRA_CPUIDLE_H -#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#ifdef CONFIG_CPU_IDLE int tegra20_cpuidle_init(void); -#else -static inline int tegra20_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC int tegra30_cpuidle_init(void); -#else -static inline int tegra30_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_ARCH_TEGRA_114_SOC int tegra114_cpuidle_init(void); +void tegra_cpuidle_init(void); #else -static inline int tegra114_cpuidle_init(void) { return -ENODEV; } +static inline void tegra_cpuidle_init(void) {} #endif #endif diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 67eab56699b..7a29bae799a 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -25,6 +25,7 @@ #define FLOW_CTRL_WAITEVENT (2 << 29) #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) #define FLOW_CTRL_JTAG_RESUME (1 << 28) +#define FLOW_CTRL_SCLK_RESUME (1 << 27) #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) #define FLOW_CTRL_CPU0_CSR 0x8 diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index aacc00d0598..def79683bef 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -19,16 +19,6 @@ #ifndef __MACH_TEGRA_FUSE_H #define __MACH_TEGRA_FUSE_H -enum tegra_revision { - TEGRA_REVISION_UNKNOWN = 0, - TEGRA_REVISION_A01, - TEGRA_REVISION_A02, - TEGRA_REVISION_A03, - TEGRA_REVISION_A03p, - TEGRA_REVISION_A04, - TEGRA_REVISION_MAX, -}; - #define SKU_ID_T20 8 #define SKU_ID_T25SE 20 #define SKU_ID_AP25 23 @@ -40,6 +30,17 @@ enum tegra_revision { #define TEGRA30 0x30 #define TEGRA114 0x35 +#ifndef __ASSEMBLY__ +enum tegra_revision { + TEGRA_REVISION_UNKNOWN = 0, + TEGRA_REVISION_A01, + TEGRA_REVISION_A02, + TEGRA_REVISION_A03, + TEGRA_REVISION_A03p, + TEGRA_REVISION_A04, + TEGRA_REVISION_MAX, +}; + extern int tegra_sku_id; extern int tegra_cpu_process_id; extern int tegra_core_process_id; @@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void); #else static inline void tegra114_init_speedo_data(void) {} #endif +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index 184914a68d7..a52c10e0a85 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -46,6 +46,17 @@ void __ref tegra_cpu_die(unsigned int cpu) BUG(); } +int tegra_cpu_disable(unsigned int cpu) +{ + switch (tegra_chip_id) { + case TEGRA20: + case TEGRA30: + return cpu == 0 ? -EPERM : 0; + default: + return 0; + } +} + void __init tegra_hotplug_init(void) { if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) @@ -55,4 +66,6 @@ void __init tegra_hotplug_init(void) tegra_hotplug_shutdown = tegra20_hotplug_shutdown; if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) tegra_hotplug_shutdown = tegra30_hotplug_shutdown; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) + tegra_hotplug_shutdown = tegra30_hotplug_shutdown; } diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index fad4226ef71..24db4ac428a 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -140,8 +140,31 @@ remove_clamps: static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) { + int ret = 0; + cpu = cpu_logical_map(cpu); - return tegra_pmc_cpu_power_on(cpu); + + if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { + /* + * Warm boot flow + * The flow controller in charge of the power state and + * control for each CPU. + */ + /* set SCLK as event trigger for flow controller */ + flowctrl_write_cpu_csr(cpu, 1); + flowctrl_write_cpu_halt(cpu, + FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME); + } else { + /* + * Cold boot flow + * The CPU is powered up by toggling PMC directly. It will + * also initial power state in flow controller. After that, + * the CPU's power state is maintained by flow controller. + */ + ret = tegra_pmc_cpu_power_on(cpu); + } + + return ret; } static int __cpuinit tegra_boot_secondary(unsigned int cpu, @@ -173,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = { #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = tegra_cpu_kill, .cpu_die = tegra_cpu_die, + .cpu_disable = tegra_cpu_disable, #endif }; diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 45cf52c7e52..94e69bee3da 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -44,6 +44,20 @@ static DEFINE_SPINLOCK(tegra_lp2_lock); void (*tegra_tear_down_cpu)(void); +static void tegra_tear_down_cpu_init(void) +{ + switch (tegra_chip_id) { + case TEGRA20: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra_tear_down_cpu = tegra20_tear_down_cpu; + break; + case TEGRA30: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) + tegra_tear_down_cpu = tegra30_tear_down_cpu; + break; + } +} + /* * restore_cpu_complex * @@ -91,8 +105,9 @@ static void suspend_cpu_complex(void) flowctrl_cpu_suspend_enter(cpu); } -void tegra_clear_cpu_in_lp2(int phy_cpu_id) +void tegra_clear_cpu_in_lp2(void) { + int phy_cpu_id = cpu_logical_map(smp_processor_id()); u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; spin_lock(&tegra_lp2_lock); @@ -103,8 +118,9 @@ void tegra_clear_cpu_in_lp2(int phy_cpu_id) spin_unlock(&tegra_lp2_lock); } -bool tegra_set_cpu_in_lp2(int phy_cpu_id) +bool tegra_set_cpu_in_lp2(void) { + int phy_cpu_id = cpu_logical_map(smp_processor_id()); bool last_cpu = false; cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -192,7 +208,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state) suspend_cpu_complex(); switch (mode) { case TEGRA_SUSPEND_LP2: - tegra_set_cpu_in_lp2(0); + tegra_set_cpu_in_lp2(); break; default: break; @@ -202,7 +218,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state) switch (mode) { case TEGRA_SUSPEND_LP2: - tegra_clear_cpu_in_lp2(0); + tegra_clear_cpu_in_lp2(); break; default: break; @@ -224,6 +240,7 @@ void __init tegra_init_suspend(void) if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) return; + tegra_tear_down_cpu_init(); tegra_pmc_suspend_init(); suspend_set_ops(&tegra_suspend_ops); diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 778a4aa7c3f..94c4b9d9077 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -28,8 +28,8 @@ extern unsigned long l2x0_saved_regs_addr; void save_cpu_arch_register(void); void restore_cpu_arch_register(void); -void tegra_clear_cpu_in_lp2(int phy_cpu_id); -bool tegra_set_cpu_in_lp2(int phy_cpu_id); +void tegra_clear_cpu_in_lp2(void); +bool tegra_set_cpu_in_lp2(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void); diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 32360e540ce..eb3fa4aee0e 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -234,7 +234,7 @@ static const struct of_device_id matches[] __initconst = { { } }; -static void tegra_pmc_parse_dt(void) +static void __init tegra_pmc_parse_dt(void) { struct device_node *np; u32 prop; diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e6de88a2ea0..39dc9e7834f 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -22,11 +22,11 @@ #include <asm/hardware/cache-l2x0.h> #include "flowctrl.h" +#include "fuse.h" #include "iomap.h" #include "reset.h" #include "sleep.h" -#define APB_MISC_GP_HIDREV 0x804 #define PMC_SCRATCH41 0x140 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) @@ -38,34 +38,40 @@ * CPU boot vector when restarting the a CPU following * an LP2 transition. Also branched to by LP0 and LP1 resume after * re-enabling sdram. + * + * r6: SoC ID */ ENTRY(tegra_resume) bl v7_invalidate_l1 cpu_id r0 + tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + cmp r6, #TEGRA114 + beq no_cpu0_chk + cmp r0, #0 @ CPU0? THUMB( it ne ) bne cpu_resume @ no +no_cpu0_chk: -#ifdef CONFIG_ARCH_TEGRA_3x_SOC /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) + cmp r6, #TEGRA20 beq 1f @ Yes /* Clear the flow controller flags for this CPU. */ - mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR - ldr r1, [r2] + cpu_to_csr_reg r1, r0 + mov32 r2, TEGRA_FLOW_CTRL_BASE + ldr r1, [r2, r1] /* Clear event & intr flag */ orr r1, r1, \ #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps + movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps + @ & ext flags for CPU power mgnt bic r1, r1, r0 str r1, [r2] 1: -#endif + check_cpu_part_num 0xc09, r8, r9 + bne not_ca9 #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ mov32 r0, TEGRA_ARM_PERIF_BASE @@ -76,6 +82,7 @@ ENTRY(tegra_resume) /* L2 cache resume & re-enable */ l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr +not_ca9: b cpu_resume ENDPROC(tegra_resume) @@ -98,7 +105,7 @@ ENTRY(__tegra_cpu_reset_handler_start) * Register usage within the reset handler: * * Others: scratch - * R6 = SoC ID << 8 + * R6 = SoC ID * R7 = CPU present (to the OS) mask * R8 = CPU in LP1 state mask * R9 = CPU in LP2 state mask @@ -115,12 +122,10 @@ ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled - mov32 r6, TEGRA_APB_MISC_BASE - ldr r6, [r6, #APB_MISC_GP_HIDREV] - and r6, r6, #0xff00 + tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 #ifdef CONFIG_ARCH_TEGRA_2x_SOC t20_check: - cmp r6, #(0x20 << 8) + cmp r6, #TEGRA20 bne after_t20_check t20_errata: # Tegra20 is a Cortex-A9 r1p1 @@ -136,7 +141,7 @@ after_t20_check: #endif #ifdef CONFIG_ARCH_TEGRA_3x_SOC t30_check: - cmp r6, #(0x30 << 8) + cmp r6, #TEGRA30 bne after_t30_check t30_errata: # Tegra30 is a Cortex-A9 r2p9 @@ -163,7 +168,7 @@ after_errata: #ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Are we on Tegra20? */ - cmp r6, #(0x20 << 8) + cmp r6, #TEGRA20 bne 1f /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ mov32 r5, TEGRA_PMC_BASE @@ -186,11 +191,14 @@ __is_not_lp2: #ifdef CONFIG_SMP /* - * Can only be secondary boot (initial or hotplug) but CPU 0 - * cannot be here. + * Can only be secondary boot (initial or hotplug) + * CPU0 can't be here for Tegra20/30 */ + cmp r6, #TEGRA114 + beq __no_cpu0_chk cmp r10, #0 bleq __die @ CPU0 cannot be here +__no_cpu0_chk: ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] cmp lr, #0 bleq __die @ no secondary startup handler @@ -210,10 +218,7 @@ __die: mov32 r7, TEGRA_CLK_RESET_BASE /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) + cmp r6, #TEGRA20 bne 1f #ifdef CONFIG_ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index d29dfcce948..ada8821b48b 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -19,6 +19,7 @@ #include <asm/assembler.h> #include <asm/asm-offsets.h> +#include "fuse.h" #include "sleep.h" #include "flowctrl.h" @@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown) * * Puts the current CPU in wait-for-event mode on the flow controller * and powergates it -- flags (in R0) indicate the request type. - * Must never be called for CPU 0. * - * corrupts r0-r4, r12 + * r10 = SoC ID + * corrupts r0-r4, r10-r12 */ ENTRY(tegra30_cpu_shutdown) cpu_id r3 + tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10 + cmp r10, #TEGRA30 + bne _no_cpu0_chk @ It's not Tegra30 + cmp r3, #0 moveq pc, lr @ Must never be called for CPU 0 +_no_cpu0_chk: ldr r12, =TEGRA_FLOW_CTRL_VIRT cpu_to_csr_reg r1, r3 @@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown) movw r12, \ FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ FLOW_CTRL_CSR_ENABLE - mov r4, #(1 << 4) + cmp r10, #TEGRA30 + moveq r4, #(1 << 4) @ wfe bitmap + movne r4, #(1 << 8) @ wfi bitmap ARM( orr r12, r12, r4, lsl r3 ) THUMB( lsl r4, r4, r3 ) THUMB( orr r12, r12, r4 ) @@ -79,9 +87,20 @@ delay_1: cpsid a @ disable imprecise aborts. ldr r3, [r1] @ read CSR str r3, [r1] @ clear CSR + tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN + beq flow_ctrl_setting_for_lp2 + + /* flow controller set up for hotplug */ + mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug + b flow_ctrl_done +flow_ctrl_setting_for_lp2: + /* flow controller set up for LP2 */ + cmp r10, #TEGRA30 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 - movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug + movne r3, #FLOW_CTRL_WAITEVENT +flow_ctrl_done: + cmp r10, #TEGRA30 str r3, [r2] ldr r0, [r2] b wfe_war @@ -89,7 +108,8 @@ delay_1: __cpu_reset_again: dsb .align 5 - wfe @ CPU should be power gated here + wfeeq @ CPU should be power gated here + wfine wfe_war: b __cpu_reset_again diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 364d84523fb..9daaef26b0f 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu) isb #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ - mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 - mov r5, #0 - str r5, [r4, #L2X0_CTRL] + check_cpu_part_num 0xc09, r9, r10 + movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) + movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) + moveq r5, #0 + streq r5, [r4, #L2X0_CTRL] #endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 2080fb12ce2..98b7da698f2 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -25,6 +25,8 @@ + IO_PPSB_VIRT) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ + IO_PPSB_VIRT) +#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \ + + IO_APB_VIRT) #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */ @@ -70,19 +72,40 @@ movt \reg, #:upper16:\val .endm +/* Marco to check CPU part num */ +.macro check_cpu_part_num part_num, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 0 + ubfx \tmp1, \tmp1, #4, #12 + mov32 \tmp2, \part_num + cmp \tmp1, \tmp2 +.endm + /* Macro to exit SMP coherency. */ .macro exit_smp, tmp1, tmp2 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR isb - cpu_id \tmp1 - mov \tmp1, \tmp1, lsl #2 - mov \tmp2, #0xf - mov \tmp2, \tmp2, lsl \tmp1 - mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC - str \tmp2, [\tmp1] @ invalidate SCU tags for CPU +#ifdef CONFIG_HAVE_ARM_SCU + check_cpu_part_num 0xc09, \tmp1, \tmp2 + mrceq p15, 0, \tmp1, c0, c0, 5 + andeq \tmp1, \tmp1, #0xF + moveq \tmp1, \tmp1, lsl #2 + moveq \tmp2, #0xf + moveq \tmp2, \tmp2, lsl \tmp1 + ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC) + streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU dsb +#endif +.endm + +/* Macro to check Tegra revision */ +#define APB_MISC_GP_HIDREV 0x804 +.macro tegra_get_soc_id base, tmp1 + mov32 \tmp1, \base + ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV] + and \tmp1, \tmp1, #0xff00 + mov \tmp1, \tmp1, lsr #8 .endm /* Macro to resume & re-enable L2 cache */ diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c index 31e69a019bd..3ae4a7f1a2f 100644 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ b/arch/arm/mach-tegra/tegra2_emc.c @@ -183,7 +183,7 @@ static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np) u32 reg; for_each_child_of_node(np, iter) { - if (of_property_read_u32(np, "nvidia,ram-code", ®)) + if (of_property_read_u32(iter, "nvidia,ram-code", ®)) continue; if (reg == tegra_bct_strapping) return of_node_get(iter); diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index 1f597647d43..a85adcd0088 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -1,24 +1,46 @@ -if ARCH_U300 - menu "ST-Ericsson AB U300/U335 Platform" comment "ST-Ericsson Mobile Platform Products" -config MACH_U300 - bool "U300" +config ARCH_U300 + bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5 + depends on MMU + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select ARM_PATCH_PHYS_VIRT + select ARM_VIC + select CLKDEV_LOOKUP + select CLKSRC_MMIO + select CLKSRC_OF + select COMMON_CLK + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_TCM select PINCTRL select PINCTRL_COH901 select PINCTRL_U300 + select SPARSE_IRQ + select MFD_SYSCON + select USE_OF + help + Support for ST-Ericsson U300 series mobile platforms. comment "ST-Ericsson U300/U335 Feature Selections" +config MACH_U300 + depends on ARCH_U300 + bool "U300" + default y + config U300_DEBUG + depends on ARCH_U300 bool "Debug support for U300" depends on PM help Debug support for U300 in sysfs, procfs etc. config MACH_U300_SPIDUMMY + depends on ARCH_U300 bool "SSP/SPI dummy chip" select SPI select SPI_MASTER @@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY SPI framework and ARM PL022 support. endmenu - -endif diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile index 5a86c58da39..0f362b64fb8 100644 --- a/arch/arm/mach-u300/Makefile +++ b/arch/arm/mach-u300/Makefile @@ -7,7 +7,5 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_SPI_PL022) += spi.o obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o -obj-$(CONFIG_I2C_STU300) += i2c.o obj-$(CONFIG_REGULATOR_AB3100) += regulator.o diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index a683d17b2ce..4f7ac2a1145 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -9,46 +9,157 @@ * Author: Linus Walleij <linus.walleij@stericsson.com> */ #include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/termios.h> -#include <linux/dmaengine.h> -#include <linux/amba/bus.h> -#include <linux/amba/mmci.h> -#include <linux/amba/serial.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/fsmc.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/dma-mapping.h> #include <linux/platform_data/clk-u300.h> -#include <linux/platform_data/pinctrl-coh901.h> -#include <linux/platform_data/dma-coh901318.h> -#include <linux/irqchip/arm-vic.h> +#include <linux/irqchip.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/clocksource.h> +#include <linux/clk.h> -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> #include <asm/mach/map.h> -#include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/hardware.h> -#include <mach/syscon.h> -#include <mach/irqs.h> +/* + * These are the large blocks of memory allocated for I/O. + * the defines are used for setting up the I/O memory mapping. + */ + +/* NAND Flash CS0 */ +#define U300_NAND_CS0_PHYS_BASE 0x80000000 +/* NFIF */ +#define U300_NAND_IF_PHYS_BASE 0x9f800000 +/* ALE, CLE offset for FSMC NAND */ +#define PLAT_NAND_CLE (1 << 16) +#define PLAT_NAND_ALE (1 << 17) +/* AHB Peripherals */ +#define U300_AHB_PER_PHYS_BASE 0xa0000000 +#define U300_AHB_PER_VIRT_BASE 0xff010000 +/* FAST Peripherals */ +#define U300_FAST_PER_PHYS_BASE 0xc0000000 +#define U300_FAST_PER_VIRT_BASE 0xff020000 +/* SLOW Peripherals */ +#define U300_SLOW_PER_PHYS_BASE 0xc0010000 +#define U300_SLOW_PER_VIRT_BASE 0xff000000 +/* Boot ROM */ +#define U300_BOOTROM_PHYS_BASE 0xffff0000 +#define U300_BOOTROM_VIRT_BASE 0xffff0000 +/* SEMI config base */ +#define U300_SEMI_CONFIG_BASE 0x2FFE0000 + +/* + * AHB peripherals + */ + +/* AHB Peripherals Bridge Controller */ +#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) +/* Vectored Interrupt Controller 0, servicing 32 interrupts */ +#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) +#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) +/* Vectored Interrupt Controller 1, servicing 32 interrupts */ +#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) +#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) +/* Memory Stick Pro (MSPRO) controller */ +#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) +/* EMIF Configuration Area */ +#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) + +/* + * FAST peripherals + */ + +/* FAST bridge control */ +#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) +/* MMC/SD controller */ +#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) +/* PCM I2S0 controller */ +#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) +/* PCM I2S1 controller */ +#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) +/* I2C0 controller */ +#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) +/* I2C1 controller */ +#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) +/* SPI controller */ +#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) +/* Fast UART1 on U335 only */ +#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000) + +/* + * SLOW peripherals + */ + +/* SLOW bridge control */ +#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) +/* SYSCON */ +#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) +#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) +/* Watchdog */ +#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) +/* UART0 */ +#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) +/* APP side special timer */ +#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) +#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) +/* Keypad */ +#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) +/* GPIO */ +#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) +/* RTC */ +#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) +/* Bus tracer */ +#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) +/* Event handler (hardware queue) */ +#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) +/* Genric Timer */ +#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) +/* PPM */ +#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) + +/* + * REST peripherals + */ + +/* ISP (image signal processor) */ +#define U300_ISP_BASE (0xA0008000) +/* DMA Controller base */ +#define U300_DMAC_BASE (0xC0020000) +/* MSL Base */ +#define U300_MSL_BASE (0xc0022000) +/* APEX Base */ +#define U300_APEX_BASE (0xc0030000) +/* Video Encoder Base */ +#define U300_VIDEOENC_BASE (0xc0080000) +/* XGAM Base */ +#define U300_XGAM_BASE (0xd0000000) + +/* + * SYSCON addresses applicable to the core machine. + */ -#include "timer.h" -#include "spi.h" -#include "i2c.h" -#include "u300-gpio.h" +/* Chip ID register 16bit (R/-) */ +#define U300_SYSCON_CIDR (0x400) +/* SMCR */ +#define U300_SYSCON_SMCR (0x4d0) +#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) +#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) +#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) +#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) +/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ +#define U300_SYSCON_CSDR (0x4f0) +#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) +/* PRINT_CONTROL Print Control 16bit (R/-) */ +#define U300_SYSCON_PCR (0x4f8) +#define U300_SYSCON_PCR_SERV_IND (0x0001) +/* BOOT_CONTROL 16bit (R/-) */ +#define U300_SYSCON_BCR (0x4fc) +#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) +#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) +#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) +#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) + +static void __iomem *syscon_base; /* * Static I/O mappings that are needed for booting the U300 platforms. The @@ -82,365 +193,6 @@ static void __init u300_map_io(void) iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); } -/* - * Declaration of devices found on the U300 board and - * their respective memory locations. - */ - -static struct amba_pl011_data uart0_plat_data = { -#ifdef CONFIG_COH901318 - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_UART0_RX, - .dma_tx_param = (void *) U300_DMA_UART0_TX, -#endif -}; - -/* Slow device at 0x3000 offset */ -static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE, - { IRQ_U300_UART0 }, &uart0_plat_data); - -/* The U335 have an additional UART1 on the APP CPU */ -static struct amba_pl011_data uart1_plat_data = { -#ifdef CONFIG_COH901318 - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_UART1_RX, - .dma_tx_param = (void *) U300_DMA_UART1_TX, -#endif -}; - -/* Fast device at 0x7000 offset */ -static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE, - { IRQ_U300_UART1 }, &uart1_plat_data); - -/* AHB device at 0x4000 offset */ -static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL); - -/* Fast device at 0x6000 offset */ -static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE, - { IRQ_U300_SPI }, NULL); - -/* Fast device at 0x1000 offset */ -#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 } - -static struct mmci_platform_data mmcsd_platform_data = { - /* - * Do not set ocr_mask or voltage translation function, - * we have a regulator we can control instead. - */ - .f_max = 24000000, - .gpio_wp = -1, - .gpio_cd = U300_GPIO_PIN_MMC_CD, - .cd_invert = true, - .capabilities = MMC_CAP_MMC_HIGHSPEED | - MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, -#ifdef CONFIG_COH901318 - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX, - /* Don't specify a TX channel, this RX channel is bidirectional */ -#endif -}; - -static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE, - U300_MMCSD_IRQS, &mmcsd_platform_data); - -/* - * The order of device declaration may be important, since some devices - * have dependencies on other devices being initialized first. - */ -static struct amba_device *amba_devs[] __initdata = { - &uart0_device, - &uart1_device, - &pl022_device, - &pl172_device, - &mmcsd_device, -}; - -/* Here follows a list of all hw resources that the platform devices - * allocate. Note, clock dependencies are not included - */ - -static struct resource gpio_resources[] = { - { - .start = U300_GPIO_BASE, - .end = (U300_GPIO_BASE + SZ_4K - 1), - .flags = IORESOURCE_MEM, - }, - { - .name = "gpio0", - .start = IRQ_U300_GPIO_PORT0, - .end = IRQ_U300_GPIO_PORT0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio1", - .start = IRQ_U300_GPIO_PORT1, - .end = IRQ_U300_GPIO_PORT1, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio2", - .start = IRQ_U300_GPIO_PORT2, - .end = IRQ_U300_GPIO_PORT2, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio3", - .start = IRQ_U300_GPIO_PORT3, - .end = IRQ_U300_GPIO_PORT3, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio4", - .start = IRQ_U300_GPIO_PORT4, - .end = IRQ_U300_GPIO_PORT4, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio5", - .start = IRQ_U300_GPIO_PORT5, - .end = IRQ_U300_GPIO_PORT5, - .flags = IORESOURCE_IRQ, - }, - { - .name = "gpio6", - .start = IRQ_U300_GPIO_PORT6, - .end = IRQ_U300_GPIO_PORT6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource keypad_resources[] = { - { - .start = U300_KEYPAD_BASE, - .end = U300_KEYPAD_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "coh901461-press", - .start = IRQ_U300_KEYPAD_KEYBF, - .end = IRQ_U300_KEYPAD_KEYBF, - .flags = IORESOURCE_IRQ, - }, - { - .name = "coh901461-release", - .start = IRQ_U300_KEYPAD_KEYBR, - .end = IRQ_U300_KEYPAD_KEYBR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource rtc_resources[] = { - { - .start = U300_RTC_BASE, - .end = U300_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_RTC, - .end = IRQ_U300_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -/* - * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2) - * but these are not yet used by the driver. - */ -static struct resource fsmc_resources[] = { - { - .name = "nand_addr", - .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE, - .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "nand_cmd", - .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE, - .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "nand_data", - .start = U300_NAND_CS0_PHYS_BASE, - .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fsmc_regs", - .start = U300_NAND_IF_PHYS_BASE, - .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource i2c0_resources[] = { - { - .start = U300_I2C0_BASE, - .end = U300_I2C0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_I2C0, - .end = IRQ_U300_I2C0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource i2c1_resources[] = { - { - .start = U300_I2C1_BASE, - .end = U300_I2C1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_I2C1, - .end = IRQ_U300_I2C1, - .flags = IORESOURCE_IRQ, - }, - -}; - -static struct resource wdog_resources[] = { - { - .start = U300_WDOG_BASE, - .end = U300_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_WDOG, - .end = IRQ_U300_WDOG, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource dma_resource[] = { - { - .start = U300_DMAC_BASE, - .end = U300_DMAC_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_U300_DMA, - .end = IRQ_U300_DMA, - .flags = IORESOURCE_IRQ, - } -}; - - -static struct resource pinctrl_resources[] = { - { - .start = U300_SYSCON_BASE, - .end = U300_SYSCON_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device wdog_device = { - .name = "coh901327_wdog", - .id = -1, - .num_resources = ARRAY_SIZE(wdog_resources), - .resource = wdog_resources, -}; - -static struct platform_device i2c0_device = { - .name = "stu300", - .id = 0, - .num_resources = ARRAY_SIZE(i2c0_resources), - .resource = i2c0_resources, -}; - -static struct platform_device i2c1_device = { - .name = "stu300", - .id = 1, - .num_resources = ARRAY_SIZE(i2c1_resources), - .resource = i2c1_resources, -}; - -static struct platform_device pinctrl_device = { - .name = "pinctrl-u300", - .id = -1, - .num_resources = ARRAY_SIZE(pinctrl_resources), - .resource = pinctrl_resources, -}; - -/* - * The different variants have a few different versions of the - * GPIO block, with different number of ports. - */ -static struct u300_gpio_platform u300_gpio_plat = { - .ports = 7, - .gpio_base = 0, -}; - -static struct platform_device gpio_device = { - .name = "u300-gpio", - .id = -1, - .num_resources = ARRAY_SIZE(gpio_resources), - .resource = gpio_resources, - .dev = { - .platform_data = &u300_gpio_plat, - }, -}; - -static struct platform_device keypad_device = { - .name = "keypad", - .id = -1, - .num_resources = ARRAY_SIZE(keypad_resources), - .resource = keypad_resources, -}; - -static struct platform_device rtc_device = { - .name = "rtc-coh901331", - .id = -1, - .num_resources = ARRAY_SIZE(rtc_resources), - .resource = rtc_resources, -}; - -static struct mtd_partition u300_partitions[] = { - { - .name = "bootrecords", - .offset = 0, - .size = SZ_128K, - }, - { - .name = "free", - .offset = SZ_128K, - .size = 8064 * SZ_1K, - }, - { - .name = "platform", - .offset = 8192 * SZ_1K, - .size = 253952 * SZ_1K, - }, -}; - -static struct fsmc_nand_platform_data nand_platform_data = { - .partitions = u300_partitions, - .nr_partitions = ARRAY_SIZE(u300_partitions), - .options = NAND_SKIP_BBTSCAN, - .width = FSMC_NAND_BW8, -}; - -static struct platform_device nand_device = { - .name = "fsmc-nand", - .id = -1, - .resource = fsmc_resources, - .num_resources = ARRAY_SIZE(fsmc_resources), - .dev = { - .platform_data = &nand_platform_data, - }, -}; - -static struct platform_device dma_device = { - .name = "coh901318", - .id = -1, - .resource = dma_resource, - .num_resources = ARRAY_SIZE(dma_resource), - .dev = { - .coherent_dma_mask = ~0, - }, -}; - static unsigned long pin_pullup_conf[] = { PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1), }; @@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = { pin_highz_conf), }; -/* - * Notice that AMBA devices are initialized before platform devices. - * - */ -static struct platform_device *platform_devs[] __initdata = { - &dma_device, - &i2c0_device, - &i2c1_device, - &keypad_device, - &rtc_device, - &pinctrl_device, - &gpio_device, - &nand_device, - &wdog_device, -}; - -/* - * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected - * together so some interrupts are connected to the first one and some - * to the second one. - */ -static void __init u300_init_irq(void) -{ - u32 mask[2] = {0, 0}; - struct clk *clk; - int i; - - /* initialize clocking early, we want to clock the INTCON */ - u300_clk_init(U300_SYSCON_VBASE); - - /* Bootstrap EMIF and SEMI clocks */ - clk = clk_get_sys("pl172", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - clk = clk_get_sys("semi", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - - /* Clock the interrupt controller */ - clk = clk_get_sys("intcon", NULL); - BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); - - for (i = 0; i < U300_VIC_IRQS_END; i++) - set_bit(i, (unsigned long *) &mask[0]); - vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START, - mask[0], mask[0]); - vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START, - mask[1], mask[1]); -} - - -/* - * U300 platforms peripheral handling - */ struct db_chip { u16 chipid; const char *name; @@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void) const char unknown[] = "UNKNOWN"; /* Read out and print chip ID */ - val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); + val = readw(syscon_base + U300_SYSCON_CIDR); /* This is in funky bigendian order... */ val = (val & 0xFFU) << 8 | (val >> 8); chip = db_chips; @@ -600,74 +297,6 @@ static void __init u300_init_check_chip(void) } } -/* - * Some devices and their resources require reserved physical memory from - * the end of the available RAM. This function traverses the list of devices - * and assigns actual addresses to these. - */ -static void __init u300_assign_physmem(void) -{ - unsigned long curr_start = __pa(high_memory); - int i, j; - - for (i = 0; i < ARRAY_SIZE(platform_devs); i++) { - for (j = 0; j < platform_devs[i]->num_resources; j++) { - struct resource *const res = - &platform_devs[i]->resource[j]; - - if (IORESOURCE_MEM == res->flags && - 0 == res->start) { - res->start = curr_start; - res->end += curr_start; - curr_start += resource_size(res); - - printk(KERN_INFO "core.c: Mapping RAM " \ - "%#x-%#x to device %s:%s\n", - res->start, res->end, - platform_devs[i]->name, res->name); - } - } - } -} - -static void __init u300_init_machine(void) -{ - int i; - u16 val; - - /* Check what platform we run and print some status information */ - u300_init_check_chip(); - - /* Initialize SPI device with some board specifics */ - u300_spi_init(&pl022_device); - - /* Register the AMBA devices in the AMBA bus abstraction layer */ - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { - struct amba_device *d = amba_devs[i]; - amba_device_register(d, &iomem_resource); - } - - u300_assign_physmem(); - - /* Initialize pinmuxing */ - pinctrl_register_mappings(u300_pinmux_map, - ARRAY_SIZE(u300_pinmux_map)); - - /* Register subdevices on the I2C buses */ - u300_i2c_register_board_devices(); - - /* Register the platform devices */ - platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); - - /* Register subdevices on the SPI bus */ - u300_spi_register_board_devices(); - - /* Enable SEMI self refresh */ - val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | - U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); -} - /* Forward declare this function from the watchdog */ void coh901327_watchdog_reset(void); @@ -688,13 +317,99 @@ static void u300_restart(char mode, const char *cmd) while (1); } -MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") - /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ - .atag_offset = 0x100, +/* These are mostly to get the right device names for the clock lookups */ +static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE, + "pinctrl-u300", NULL), + OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE, + "u300-gpio", NULL), + OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE, + "coh901327_wdog", NULL), + OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE, + "rtc-coh901331", NULL), + OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE, + "coh901318", NULL), + OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE, + "fsmc-nand", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE, + "uart0", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE, + "uart1", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE, + "pl022", NULL), + OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE, + "stu300.0", NULL), + OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE, + "stu300.1", NULL), + OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE, + "mmci", NULL), + { /* sentinel */ }, +}; + +static void __init u300_init_irq_dt(void) +{ + struct device_node *syscon; + struct clk *clk; + + syscon = of_find_node_by_path("/syscon@c0011000"); + if (!syscon) { + pr_crit("could not find syscon node\n"); + return; + } + syscon_base = of_iomap(syscon, 0); + if (!syscon_base) { + pr_crit("could not remap syscon\n"); + return; + } + /* initialize clocking early, we want to clock the INTCON */ + u300_clk_init(syscon_base); + + /* Bootstrap EMIF and SEMI clocks */ + clk = clk_get_sys("pl172", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + clk = clk_get_sys("semi", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + + /* Clock the interrupt controller */ + clk = clk_get_sys("intcon", NULL); + BUG_ON(IS_ERR(clk)); + clk_prepare_enable(clk); + + irqchip_init(); +} + +static void __init u300_init_machine_dt(void) +{ + u16 val; + + /* Check what platform we run and print some status information */ + u300_init_check_chip(); + + /* Initialize pinmuxing */ + pinctrl_register_mappings(u300_pinmux_map, + ARRAY_SIZE(u300_pinmux_map)); + + of_platform_populate(NULL, of_default_bus_match_table, + u300_auxdata_lookup, NULL); + + /* Enable SEMI self refresh */ + val = readw(syscon_base + U300_SYSCON_SMCR) | + U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; + writew(val, syscon_base + U300_SYSCON_SMCR); +} + +static const char * u300_board_compat[] = { + "stericsson,u300", + NULL, +}; + +DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)") .map_io = u300_map_io, - .nr_irqs = 0, - .init_irq = u300_init_irq, - .init_time = u300_timer_init, - .init_machine = u300_init_machine, + .init_irq = u300_init_irq_dt, + .init_time = clocksource_of_init, + .init_machine = u300_init_machine_dt, .restart = u300_restart, + .dt_compat = u300_board_compat, MACHINE_END diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c index 2785cb67b5e..ec0283cf9a3 100644 --- a/arch/arm/mach-u300/dummyspichip.c +++ b/arch/arm/mach-u300/dummyspichip.c @@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi) return 0; } +static const struct of_device_id pl022_dummy_dt_match[] = { + { .compatible = "arm,pl022-dummy" }, + {}, +}; + static struct spi_driver pl022_dummy_driver = { .driver = { .name = "spi-dummy", .owner = THIS_MODULE, + .of_match_table = pl022_dummy_dt_match, }, .probe = pl022_dummy_probe, .remove = pl022_dummy_remove, }; -static int __init pl022_init_dummy(void) -{ - return spi_register_driver(&pl022_dummy_driver); -} - -static void __exit pl022_exit_dummy(void) -{ - spi_unregister_driver(&pl022_dummy_driver); -} - -module_init(pl022_init_dummy); -module_exit(pl022_exit_dummy); - +module_spi_driver(pl022_dummy_driver); MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver"); MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c deleted file mode 100644 index 96800aa1316..00000000000 --- a/arch/arm/mach-u300/i2c.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * arch/arm/mach-u300/i2c.c - * - * Copyright (C) 2009-2012 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Register board i2c devices - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#include <linux/kernel.h> -#include <linux/i2c.h> -#include <linux/mfd/ab3100.h> -#include <linux/regulator/machine.h> -#include <linux/amba/bus.h> -#include <mach/irqs.h> - -/* - * Initial settings of ab3100 registers. - * Common for below LDO regulator settings are that - * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0). - * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode. - */ - -/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */ -#define LDO_A_SETTING 0x16 -/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */ -#define LDO_C_SETTING 0x10 -/* LDO_D 0x10: 2.65V, ON, sleep mode not used */ -#define LDO_D_SETTING 0x10 -/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */ -#define LDO_E_SETTING 0x10 -/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */ -#define LDO_E_SLEEP_SETTING 0x00 -/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */ -#define LDO_F_SETTING 0xD0 -/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */ -#define LDO_G_SETTING 0x00 -/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */ -#define LDO_H_SETTING 0x18 -/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */ -#define LDO_K_SETTING 0x00 -/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */ -#define LDO_EXT_SETTING 0x00 -/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */ -#define BUCK_SETTING 0x7D -/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */ -#define BUCK_SLEEP_SETTING 0xAC - -#ifdef CONFIG_AB3100_CORE -static struct regulator_consumer_supply supply_ldo_c[] = { - { - .dev_name = "ab3100-codec", - .supply = "vaudio", /* Powers the codec */ - }, -}; - -/* - * This one needs to be a supply so we can turn it off - * in order to shut down the system. - */ -static struct regulator_consumer_supply supply_ldo_d[] = { - { - .supply = "vana15", /* Powers the SoC (CPU etc) */ - }, -}; - -static struct regulator_consumer_supply supply_ldo_g[] = { - { - .dev_name = "mmci", - .supply = "vmmc", /* Powers MMC/SD card */ - }, -}; - -static struct regulator_consumer_supply supply_ldo_h[] = { - { - .dev_name = "xgam_pdi", - .supply = "vdisp", /* Powers camera, display etc */ - }, -}; - -static struct regulator_consumer_supply supply_ldo_k[] = { - { - .dev_name = "irda", - .supply = "vir", /* Power IrDA */ - }, -}; - -/* - * This is a placeholder for whoever wish to use the - * external power. - */ -static struct regulator_consumer_supply supply_ldo_ext[] = { - { - .supply = "vext", /* External power */ - }, -}; - -/* Preset (hardware defined) voltages for these regulators */ -#define LDO_A_VOLTAGE 2750000 -#define LDO_C_VOLTAGE 2650000 -#define LDO_D_VOLTAGE 2650000 - -static struct ab3100_platform_data ab3100_plf_data = { - .reg_constraints = { - /* LDO A routing and constraints */ - { - .constraints = { - .name = "vrad", - .min_uV = LDO_A_VOLTAGE, - .max_uV = LDO_A_VOLTAGE, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .boot_on = 1, - }, - }, - /* LDO C routing and constraints */ - { - .constraints = { - .min_uV = LDO_C_VOLTAGE, - .max_uV = LDO_C_VOLTAGE, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c), - .consumer_supplies = supply_ldo_c, - }, - /* LDO D routing and constraints */ - { - .constraints = { - .min_uV = LDO_D_VOLTAGE, - .max_uV = LDO_D_VOLTAGE, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - /* - * Actually this is boot_on but we need - * to reference count it externally to - * be able to shut down the system. - */ - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d), - .consumer_supplies = supply_ldo_d, - }, - /* LDO E routing and constraints */ - { - .constraints = { - .name = "vio", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .boot_on = 1, - }, - }, - /* LDO F routing and constraints */ - { - .constraints = { - .name = "vana25", - .min_uV = 2500000, - .max_uV = 2500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .always_on = 1, - .boot_on = 1, - }, - }, - /* LDO G routing and constraints */ - { - .constraints = { - .min_uV = 1500000, - .max_uV = 2850000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g), - .consumer_supplies = supply_ldo_g, - }, - /* LDO H routing and constraints */ - { - .constraints = { - .min_uV = 1200000, - .max_uV = 2750000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h), - .consumer_supplies = supply_ldo_h, - }, - /* LDO K routing and constraints */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 2750000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k), - .consumer_supplies = supply_ldo_k, - }, - /* External regulator interface. No fixed voltage specified. - * If we knew the voltage of the external regulator and it - * was connected on the board, we could add the (fixed) - * voltage for it here. - */ - { - .constraints = { - .min_uV = 0, - .max_uV = 0, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext), - .consumer_supplies = supply_ldo_ext, - }, - /* Buck converter routing and constraints */ - { - .constraints = { - .name = "vcore", - .min_uV = 1200000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, - }, - }, - }, - .reg_initvals = { - LDO_A_SETTING, - LDO_C_SETTING, - LDO_E_SETTING, - LDO_E_SLEEP_SETTING, - LDO_F_SETTING, - LDO_G_SETTING, - LDO_H_SETTING, - LDO_K_SETTING, - LDO_EXT_SETTING, - BUCK_SETTING, - BUCK_SLEEP_SETTING, - LDO_D_SETTING, - }, -}; -#endif - -static struct i2c_board_info __initdata bus0_i2c_board_info[] = { -#ifdef CONFIG_AB3100_CORE - { - .type = "ab3100", - .addr = 0x48, - .irq = IRQ_U300_IRQ0_EXT, - .platform_data = &ab3100_plf_data, - }, -#else - { }, -#endif -}; - -static struct i2c_board_info __initdata bus1_i2c_board_info[] = { - { - .type = "fwcam", - .addr = 0x10, - }, - { - .type = "fwcam", - .addr = 0x5d, - }, -}; - -void __init u300_i2c_register_board_devices(void) -{ - i2c_register_board_info(0, bus0_i2c_board_info, - ARRAY_SIZE(bus0_i2c_board_info)); - /* - * This makes the core shut down all unused regulators - * after all the initcalls have completed. - */ - regulator_has_full_constraints(); - i2c_register_board_info(1, bus1_i2c_board_info, - ARRAY_SIZE(bus1_i2c_board_info)); -} diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h deleted file mode 100644 index 485c02e5c06..00000000000 --- a/arch/arm/mach-u300/i2c.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-u300/i2c.h - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Register board i2c devices - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef MACH_U300_I2C_H -#define MACH_U300_I2C_H - -#ifdef CONFIG_I2C_STU300 -void __init u300_i2c_register_board_devices(void); -#else -/* Compile out this stuff if no I2C adapter is available */ -static inline void __init u300_i2c_register_board_devices(void) -{ -} -#endif - -#endif diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h deleted file mode 100644 index b99d4ce0ac2..00000000000 --- a/arch/arm/mach-u300/include/mach/hardware.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * arch/arm/mach-u300/include/mach/hardware.h - */ -#include <asm/sizes.h> -#include <mach/u300-regs.h> diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h deleted file mode 100644 index 21d5e76a6cd..00000000000 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/irqs.h - * - * - * Copyright (C) 2006-2012 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * IRQ channel definitions for the U300 platforms. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#define IRQ_U300_INTCON0_START 32 -#define IRQ_U300_INTCON1_START 64 -/* These are on INTCON0 - 30 lines */ -#define IRQ_U300_IRQ0_EXT 32 -#define IRQ_U300_IRQ1_EXT 33 -#define IRQ_U300_DMA 34 -#define IRQ_U300_VIDEO_ENC_0 35 -#define IRQ_U300_VIDEO_ENC_1 36 -#define IRQ_U300_AAIF_RX 37 -#define IRQ_U300_AAIF_TX 38 -#define IRQ_U300_AAIF_VGPIO 39 -#define IRQ_U300_AAIF_WAKEUP 40 -#define IRQ_U300_PCM_I2S0_FRAME 41 -#define IRQ_U300_PCM_I2S0_FIFO 42 -#define IRQ_U300_PCM_I2S1_FRAME 43 -#define IRQ_U300_PCM_I2S1_FIFO 44 -#define IRQ_U300_XGAM_GAMCON 45 -#define IRQ_U300_XGAM_CDI 46 -#define IRQ_U300_XGAM_CDICON 47 -#define IRQ_U300_XGAM_PDI 49 -#define IRQ_U300_XGAM_PDICON 50 -#define IRQ_U300_XGAM_GAMEACC 51 -#define IRQ_U300_XGAM_MCIDCT 52 -#define IRQ_U300_APEX 53 -#define IRQ_U300_UART0 54 -#define IRQ_U300_SPI 55 -#define IRQ_U300_TIMER_APP_OS 56 -#define IRQ_U300_TIMER_APP_DD 57 -#define IRQ_U300_TIMER_APP_GP1 58 -#define IRQ_U300_TIMER_APP_GP2 59 -#define IRQ_U300_TIMER_OS 60 -#define IRQ_U300_TIMER_MS 61 -#define IRQ_U300_KEYPAD_KEYBF 62 -#define IRQ_U300_KEYPAD_KEYBR 63 -/* These are on INTCON1 - 32 lines */ -#define IRQ_U300_GPIO_PORT0 64 -#define IRQ_U300_GPIO_PORT1 65 -#define IRQ_U300_GPIO_PORT2 66 - -/* These are for DB3150, DB3200 and DB3350 */ -#define IRQ_U300_WDOG 67 -#define IRQ_U300_EVHIST 68 -#define IRQ_U300_MSPRO 69 -#define IRQ_U300_MMCSD_MCIINTR0 70 -#define IRQ_U300_MMCSD_MCIINTR1 71 -#define IRQ_U300_I2C0 72 -#define IRQ_U300_I2C1 73 -#define IRQ_U300_RTC 74 -#define IRQ_U300_NFIF 75 -#define IRQ_U300_NFIF2 76 - -/* The DB3350-specific interrupt lines */ -#define IRQ_U300_ISP_F0 77 -#define IRQ_U300_ISP_F1 78 -#define IRQ_U300_ISP_F2 79 -#define IRQ_U300_ISP_F3 80 -#define IRQ_U300_ISP_F4 81 -#define IRQ_U300_GPIO_PORT3 82 -#define IRQ_U300_SYSCON_PLL_LOCK 83 -#define IRQ_U300_UART1 84 -#define IRQ_U300_GPIO_PORT4 85 -#define IRQ_U300_GPIO_PORT5 86 -#define IRQ_U300_GPIO_PORT6 87 -#define U300_VIC_IRQS_END 88 - -#endif diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h deleted file mode 100644 index 10bdd0be977..00000000000 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ /dev/null @@ -1,592 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/syscon.h - * - * - * Copyright (C) 2008-2012 ST-Ericsson AB - * - * Author: Rickard Andersson <rickard.andersson@stericsson.com> - */ - -#ifndef __MACH_SYSCON_H -#define __MACH_SYSCON_H - -/* - * All register defines for SYSCON registers that concerns individual - * block clocks and reset lines are registered here. This is because - * we don't want any other file to try to fool around with this stuff. - */ - -/* APP side SYSCON registers */ -/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */ -/* CLK Control Register 16bit (R/W) */ -#define U300_SYSCON_CCR (0x0000) -#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) -#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) -#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) -/* CLK Status Register 16bit (R/W) */ -#define U300_SYSCON_CSR (0x0004) -#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) -#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) -/* Reset lines for SLOW devices 16bit (R/W) */ -#define U300_SYSCON_RSR (0x0014) -#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) -#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) -#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) -#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) -#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) -#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) -#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) -#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) -#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) -#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) -/* Reset lines for FAST devices 16bit (R/W) */ -#define U300_SYSCON_RFR (0x0018) -#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) -#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) -#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) -#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) -#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) -#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) -#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) -#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) -/* Reset lines for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_RRR (0x001c) -#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) -#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) -#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) -#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) -#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) -#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) -#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) -#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) -#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) -#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) -#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) -#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) -#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) -/* Clock enable for SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CESR (0x0020) -#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) -#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) -#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) -#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) -#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) -#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) -#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) -#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) -#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) -/* Clock enable for FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CEFR (0x0024) -#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) -#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) -#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) -#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) -#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) -#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) -#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) -#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) -#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) -#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) -/* Clock enable for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CERR (0x0028) -#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) -#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) -#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) -#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) -#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) -#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) -#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) -#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) -#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) -#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) -#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) -#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) -#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) -#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) -/* Single block clock enable 16bit (-/W) */ -#define U300_SYSCON_SBCER (0x002c) -#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) -#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) -#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) -#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) -#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) -#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) -#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) -#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) -#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) -#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) -#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) -#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) -#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) -#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) -#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) -#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) -#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) -#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) -#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) -#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) -#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) -#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) -#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) -#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) -#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) -#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) -#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) -#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) -#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) -#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) -#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) -#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) -#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) -/* Single block clock disable 16bit (-/W) */ -#define U300_SYSCON_SBCDR (0x0030) -/* Same values as above for SBCER */ -/* Clock force SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CFSR (0x003c) -#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) -/* Clock force FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CFFR (0x40) -/* Values not defined. Define if you want to use them. */ -/* Clock force the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CFRR (0x44) -#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) -#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) -#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) -#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) -#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) -#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) -/* PLL208 Frequency Control 16bit (R/W) */ -#define U300_SYSCON_PFCR (0x48) -#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) -/* Power Management Control 16bit (R/W) */ -#define U300_SYSCON_PMCR (0x50) -#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) -#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) -/* - * All other clocking registers moved to clock.c! - */ -/* Reset Out 16bit (R/W) */ -#define U300_SYSCON_RCR (0x6c) -#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) -/* EMIF Slew Rate Control 16bit (R/W) */ -#define U300_SYSCON_SRCLR (0x70) -#define U300_SYSCON_SRCLR_MASK (0x03FF) -#define U300_SYSCON_SRCLR_VALUE (0x03FF) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) -/* EMIF Clock Control Register 16bit (R/W) */ -#define U300_SYSCON_ECCR (0x0078) -#define U300_SYSCON_ECCR_MASK (0x000F) -#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) -#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) -#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) -#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) -/* Step one for killing the applications system 16bit (-/W) */ -#define U300_SYSCON_KA1R (0x0080) -#define U300_SYSCON_KA1R_MASK (0xFFFF) -#define U300_SYSCON_KA1R_VALUE (0xFFFF) -/* Step two for killing the application system 16bit (-/W) */ -#define U300_SYSCON_KA2R (0x0084) -#define U300_SYSCON_KA2R_MASK (0xFFFF) -#define U300_SYSCON_KA2R_VALUE (0xFFFF) -/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ -#define U300_SYSCON_MMF0R (0x90) -#define U300_SYSCON_MMF0R_MASK (0x00FF) -#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) -/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ -#define U300_SYSCON_MMF1R (0x94) -#define U300_SYSCON_MMF1R_MASK (0x00FF) -#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) -/* AAIF control register 16 bit (R/W) */ -#define U300_SYSCON_AAIFCR (0x98) -#define U300_SYSCON_AAIFCR_MASK (0x0003) -#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003) -#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000) -#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001) -#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002) -#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003) -/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ -#define U300_SYSCON_MMCR (0x9C) -#define U300_SYSCON_MMCR_MASK (0x0003) -#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) -#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) -/* Pull up/down control (R/W) */ -#define U300_SYSCON_PUCR (0x104) -#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200) -#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100) -#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) -#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) -#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) -/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ -#define U300_SYSCON_S0CCR (0x120) -#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ -#define U300_SYSCON_S1CCR (0x124) -#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ -#define U300_SYSCON_S2CCR (0x128) -#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) -#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) -#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */ -#define U300_SYSCON_MCR (0x12c) -#define U300_SYSCON_MCR_FIELD_MASK (0x00FF) -#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0) -#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040) -#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0) -#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030) -#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010) -#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020) -#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030) -#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C) -#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002) -#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001) -/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ -#define U300_SYSCON_PICR (0x0130) -#define U300_SYSCON_PICR_MASK (0x00FF) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) -#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) -#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) -#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) -#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) -/* SC_PLL_IRQ_STATUS 16 bit (R/-) */ -#define U300_SYSCON_PISR (0x0134) -#define U300_SYSCON_PISR_MASK (0x000F) -#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) -#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) -#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) -#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) -/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ -#define U300_SYSCON_PICLR (0x0138) -#define U300_SYSCON_PICLR_MASK (0x000F) -#define U300_SYSCON_PICLR_RWMASK (0x0000) -#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) -#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) -#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) -#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) -/* CAMIF_CONTROL 16 bit (-/W) */ -#define U300_SYSCON_CICR (0x013C) -#define U300_SYSCON_CICR_MASK (0x0FFF) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003) -/* Clock activity observability register 0 */ -#define U300_SYSCON_C0OAR (0x140) -#define U300_SYSCON_C0OAR_MASK (0xFFFF) -#define U300_SYSCON_C0OAR_VALUE (0xFFFF) -#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) -#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) -#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) -#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) -#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) -#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) -#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) -#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) -#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) -#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) -#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) -#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) -#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) -#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) -#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) -#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) -/* Clock activity observability register 1 */ -#define U300_SYSCON_C1OAR (0x144) -#define U300_SYSCON_C1OAR_MASK (0x3FFE) -#define U300_SYSCON_C1OAR_VALUE (0x3FFE) -#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) -#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) -#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) -#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) -#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) -#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) -#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) -#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) -#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) -#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) -#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) -#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) -#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) -/* Clock activity observability register 2 */ -#define U300_SYSCON_C2OAR (0x148) -#define U300_SYSCON_C2OAR_MASK (0x0FFF) -#define U300_SYSCON_C2OAR_VALUE (0x0FFF) -#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) -#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) -#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) -#define U300_SYSCON_C2OAR_VC_CLK (0x0100) -#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) -#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) -#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) -#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) -#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) -#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) -#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) -#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) - -/* Chip ID register 16bit (R/-) */ -#define U300_SYSCON_CIDR (0x400) -/* Video IRQ clear 16bit (R/W) */ -#define U300_SYSCON_VICR (0x404) -#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002) -#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001) -/* SMCR */ -#define U300_SYSCON_SMCR (0x4d0) -#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) -#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) -#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) -#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) -/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ -#define U300_SYSCON_CSDR (0x4f0) -#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) -/* PRINT_CONTROL Print Control 16bit (R/-) */ -#define U300_SYSCON_PCR (0x4f8) -#define U300_SYSCON_PCR_SERV_IND (0x0001) -/* BOOT_CONTROL 16bit (R/-) */ -#define U300_SYSCON_BCR (0x4fc) -#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) -#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) -#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) -#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) - - -/* CPU clock defines */ -/** - * CPU high frequency in MHz - */ -#define SYSCON_CPU_CLOCK_HIGH 208 -/** - * CPU medium frequency in MHz - */ -#define SYSCON_CPU_CLOCK_MEDIUM 52 -/** - * CPU low frequency in MHz - */ -#define SYSCON_CPU_CLOCK_LOW 13 - -/* EMIF clock defines */ -/** - * EMIF high frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_HIGH 104 -/** - * EMIF medium frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_MEDIUM 52 -/** - * EMIF low frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_LOW 13 - -/* AHB clock defines */ -/** - * AHB high frequency in MHz - */ -#define SYSCON_AHB_CLOCK_HIGH 52 -/** - * AHB medium frequency in MHz - */ -#define SYSCON_AHB_CLOCK_MEDIUM 26 -/** - * AHB low frequency in MHz - */ -#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */ - -enum syscon_busmaster { - SYSCON_BM_DMAC, - SYSCON_BM_XGAM, - SYSCON_BM_VIDEO_ENC -}; - -/* Selectr a resistor or a set of resistors */ -enum syscon_pull_up_down { - SYSCON_PU_KEY_IN_EN, - SYSCON_PU_EMIF_1_8_BIT_EN, - SYSCON_PU_EMIF_1_16_BIT_EN, - SYSCON_PU_EMIF_1_NFIF_READY_EN, - SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN, -}; - -/* - * Note that this array must match the order of the array "clk_reg" - * in syscon.c - */ -enum syscon_clk { - SYSCON_CLKCONTROL_SLOW_BRIDGE, - SYSCON_CLKCONTROL_UART, - SYSCON_CLKCONTROL_BTR, - SYSCON_CLKCONTROL_EH, - SYSCON_CLKCONTROL_GPIO, - SYSCON_CLKCONTROL_KEYPAD, - SYSCON_CLKCONTROL_APP_TIMER, - SYSCON_CLKCONTROL_ACC_TIMER, - SYSCON_CLKCONTROL_FAST_BRIDGE, - SYSCON_CLKCONTROL_I2C0, - SYSCON_CLKCONTROL_I2C1, - SYSCON_CLKCONTROL_I2S0, - SYSCON_CLKCONTROL_I2S1, - SYSCON_CLKCONTROL_MMC, - SYSCON_CLKCONTROL_SPI, - SYSCON_CLKCONTROL_I2S0_CORE, - SYSCON_CLKCONTROL_I2S1_CORE, - SYSCON_CLKCONTROL_UART1, - SYSCON_CLKCONTROL_AAIF, - SYSCON_CLKCONTROL_AHB, - SYSCON_CLKCONTROL_APEX, - SYSCON_CLKCONTROL_CPU, - SYSCON_CLKCONTROL_DMA, - SYSCON_CLKCONTROL_EMIF, - SYSCON_CLKCONTROL_NAND_IF, - SYSCON_CLKCONTROL_VIDEO_ENC, - SYSCON_CLKCONTROL_XGAM, - SYSCON_CLKCONTROL_SEMI, - SYSCON_CLKCONTROL_AHB_SUBSYS, - SYSCON_CLKCONTROL_MSPRO -}; - -enum syscon_sysclk_mode { - SYSCON_SYSCLK_DISABLED, - SYSCON_SYSCLK_M_CLK, - SYSCON_SYSCLK_ACC_FSM, - SYSCON_SYSCLK_PLL60_48, - SYSCON_SYSCLK_PLL60_60, - SYSCON_SYSCLK_ACC_PLL208, - SYSCON_SYSCLK_APP_PLL13, - SYSCON_SYSCLK_APP_FSM, - SYSCON_SYSCLK_RTC, - SYSCON_SYSCLK_APP_PLL208 -}; - -enum syscon_sysclk_req { - SYSCON_SYSCLKREQ_DISABLED, - SYSCON_SYSCLKREQ_ACTIVE_LOW, - SYSCON_SYSCLKREQ_MONITOR -}; - -enum syscon_clk_mode { - SYSCON_CLKMODE_OFF, - SYSCON_CLKMODE_DEFAULT, - SYSCON_CLKMODE_LOW, - SYSCON_CLKMODE_MEDIUM, - SYSCON_CLKMODE_HIGH, - SYSCON_CLKMODE_PERMANENT, - SYSCON_CLKMODE_ON, -}; - -enum syscon_call_mode { - SYSCON_CLKCALL_NOWAIT, - SYSCON_CLKCALL_WAIT, -}; - -int syscon_dc_on(bool keep_power_on); -int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster, - bool active); -bool syscon_get_busmaster_active_state(void); -int syscon_set_sleep_mask(enum syscon_clk, - bool sleep_ctrl); -int syscon_config_sysclk(u32 sysclk, - enum syscon_sysclk_mode sysclkmode, - bool inverse, - u32 divisor, - enum syscon_sysclk_req sysclkreq); -bool syscon_can_turn_off_semi_clock(void); - -/* This function is restricted to core.c */ -int syscon_request_normal_power(bool req); - -/* This function is restricted to be used by platform_speed.c */ -int syscon_speed_request(enum syscon_call_mode wait_mode, - enum syscon_clk_mode req_clk_mode); -#endif /* __MACH_SYSCON_H */ diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h deleted file mode 100644 index f233b72633f..00000000000 --- a/arch/arm/mach-u300/include/mach/timex.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/timex.h - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Platform tick rate definition. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#ifndef __MACH_TIMEX_H -#define __MACH_TIMEX_H - -/* This is for the APP OS GP1 (General Purpose 1) timer */ -#define CLOCK_TICK_RATE 1000000 - -#endif diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h deleted file mode 100644 index 0320495efc4..00000000000 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/u300-regs.h - * - * - * Copyright (C) 2006-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * Basic register address definitions in physical memory and - * some block definitions for core devices like the timer. - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ - -#ifndef __MACH_U300_REGS_H -#define __MACH_U300_REGS_H - -/* - * These are the large blocks of memory allocated for I/O. - * the defines are used for setting up the I/O memory mapping. - */ - -/* NAND Flash CS0 */ -#define U300_NAND_CS0_PHYS_BASE 0x80000000 - -/* NFIF */ -#define U300_NAND_IF_PHYS_BASE 0x9f800000 - -/* ALE, CLE offset for FSMC NAND */ -#define PLAT_NAND_CLE (1 << 16) -#define PLAT_NAND_ALE (1 << 17) - -/* AHB Peripherals */ -#define U300_AHB_PER_PHYS_BASE 0xa0000000 -#define U300_AHB_PER_VIRT_BASE 0xff010000 - -/* FAST Peripherals */ -#define U300_FAST_PER_PHYS_BASE 0xc0000000 -#define U300_FAST_PER_VIRT_BASE 0xff020000 - -/* SLOW Peripherals */ -#define U300_SLOW_PER_PHYS_BASE 0xc0010000 -#define U300_SLOW_PER_VIRT_BASE 0xff000000 - -/* Boot ROM */ -#define U300_BOOTROM_PHYS_BASE 0xffff0000 -#define U300_BOOTROM_VIRT_BASE 0xffff0000 - -/* SEMI config base */ -#define U300_SEMI_CONFIG_BASE 0x2FFE0000 - -/* - * AHB peripherals - */ - -/* AHB Peripherals Bridge Controller */ -#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) - -/* Vectored Interrupt Controller 0, servicing 32 interrupts */ -#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) -#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) - -/* Vectored Interrupt Controller 1, servicing 32 interrupts */ -#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) -#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) - -/* Memory Stick Pro (MSPRO) controller */ -#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) - -/* EMIF Configuration Area */ -#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) - - -/* - * FAST peripherals - */ - -/* FAST bridge control */ -#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) - -/* MMC/SD controller */ -#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) - -/* PCM I2S0 controller */ -#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) - -/* PCM I2S1 controller */ -#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) - -/* I2C0 controller */ -#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) - -/* I2C1 controller */ -#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) - -/* SPI controller */ -#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) - -/* Fast UART1 on U335 only */ -#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000) - -/* - * SLOW peripherals - */ - -/* SLOW bridge control */ -#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) - -/* SYSCON */ -#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) -#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) - -/* Watchdog */ -#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) - -/* UART0 */ -#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) - -/* APP side special timer */ -#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) -#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) - -/* Keypad */ -#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) - -/* GPIO */ -#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) - -/* RTC */ -#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) - -/* Bus tracer */ -#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) - -/* Event handler (hardware queue) */ -#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) - -/* Genric Timer */ -#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) - -/* PPM */ -#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) - - -/* - * REST peripherals - */ - -/* ISP (image signal processor) */ -#define U300_ISP_BASE (0xA0008000) - -/* DMA Controller base */ -#define U300_DMAC_BASE (0xC0020000) - -/* MSL Base */ -#define U300_MSL_BASE (0xc0022000) - -/* APEX Base */ -#define U300_APEX_BASE (0xc0030000) - -/* Video Encoder Base */ -#define U300_VIDEOENC_BASE (0xc0080000) - -/* XGAM Base */ -#define U300_XGAM_BASE (0xd0000000) - -#endif diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h deleted file mode 100644 index 783e7e60101..00000000000 --- a/arch/arm/mach-u300/include/mach/uncompress.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-u300/include/mach/uncompress.h - * - * Copyright (C) 2003 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000) -#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C) -#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030) -#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018) - -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - while (AMBA_UART_FR & (1 << 5)) - barrier(); - - AMBA_UART_DR = c; -} - -static inline void flush(void) -{ - while (AMBA_UART_FR & (1 << 3)) - barrier(); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c index 9c53f01c62e..bf40cd478fe 100644 --- a/arch/arm/mach-u300/regulator.c +++ b/arch/arm/mach-u300/regulator.c @@ -10,11 +10,18 @@ #include <linux/device.h> #include <linux/signal.h> #include <linux/err.h> +#include <linux/of.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> -/* Those are just for writing in syscon */ -#include <linux/io.h> -#include <mach/hardware.h> -#include <mach/syscon.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +/* Power Management Control 16bit (R/W) */ +#define U300_SYSCON_PMCR (0x50) +#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) +#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) /* * Regulators that power the board and chip and which are @@ -47,13 +54,28 @@ void u300_pm_poweroff(void) /* * Hog the regulators needed to power up the board. */ -static int __init u300_init_boardpower(void) +static int __init __u300_init_boardpower(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; + struct device_node *syscon_np; + struct regmap *regmap; int err; - u32 val; pr_info("U300: setting up board power\n"); - main_power_15 = regulator_get(NULL, "vana15"); + + syscon_np = of_parse_phandle(np, "syscon", 0); + if (!syscon_np) { + pr_crit("U300: no syscon node\n"); + return -ENODEV; + } + regmap = syscon_node_to_regmap(syscon_np); + if (!regmap) { + pr_crit("U300: could not locate syscon regmap\n"); + return -ENODEV; + } + + main_power_15 = regulator_get(&pdev->dev, "vana15"); + if (IS_ERR(main_power_15)) { pr_err("could not get vana15"); return PTR_ERR(main_power_15); @@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void) * the rest of the U300 power management is implemented. */ pr_info("U300: disable system controller pull-up\n"); - val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); - val &= ~U300_SYSCON_PMCR_DCON_ENABLE; - writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR); + regmap_update_bits(regmap, U300_SYSCON_PMCR, + U300_SYSCON_PMCR_DCON_ENABLE, 0); /* Register globally exported PM poweroff hook */ pm_power_off = u300_pm_poweroff; @@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void) return 0; } +static int __init s365_board_probe(struct platform_device *pdev) +{ + return __u300_init_boardpower(pdev); +} + +static const struct of_device_id s365_board_match[] = { + { .compatible = "stericsson,s365" }, + {}, +}; + +static struct platform_driver s365_board_driver = { + .driver = { + .name = "s365-board", + .owner = THIS_MODULE, + .of_match_table = s365_board_match, + }, +}; + /* * So at module init time we hog the regulator! */ -module_init(u300_init_boardpower); +static int __init u300_init_boardpower(void) +{ + return platform_driver_probe(&s365_board_driver, + s365_board_probe); +} + +device_initcall(u300_init_boardpower); diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c deleted file mode 100644 index 910698293d6..00000000000 --- a/arch/arm/mach-u300/spi.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * arch/arm/mach-u300/spi.c - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#include <linux/device.h> -#include <linux/amba/bus.h> -#include <linux/spi/spi.h> -#include <linux/amba/pl022.h> -#include <linux/platform_data/dma-coh901318.h> -#include <linux/err.h> - -/* - * The following is for the actual devices on the SSP/SPI bus - */ -#ifdef CONFIG_MACH_U300_SPIDUMMY -static void select_dummy_chip(u32 chipselect) -{ - pr_debug("CORE: %s called with CS=0x%x (%s)\n", - __func__, - chipselect, - chipselect ? "unselect chip" : "select chip"); - /* - * Here you would write the chip select value to the GPIO pins if - * this was a real chip (but this is a loopback dummy). - */ -} - -struct pl022_config_chip dummy_chip_info = { - /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */ - .com_mode = DMA_TRANSFER, - .iface = SSP_INTERFACE_MOTOROLA_SPI, - /* We can only act as master but SSP_SLAVE is possible in theory */ - .hierarchy = SSP_MASTER, - /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ - .slave_tx_disable = 0, - .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, - .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, - .ctrl_len = SSP_BITS_12, - .wait_state = SSP_MWIRE_WAIT_ZERO, - .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, - /* - * This is where you insert a call to a function to enable CS - * (usually GPIO) for a certain chip. - */ - .cs_control = select_dummy_chip, -}; -#endif - -static struct spi_board_info u300_spi_devices[] = { -#ifdef CONFIG_MACH_U300_SPIDUMMY - { - /* A dummy chip used for loopback tests */ - .modalias = "spi-dummy", - /* Really dummy, pass in additional chip config here */ - .platform_data = NULL, - /* This defines how the controller shall handle the device */ - .controller_data = &dummy_chip_info, - /* .irq - no external IRQ routed from this device */ - .max_speed_hz = 1000000, - .bus_num = 0, /* Only one bus on this chip */ - .chip_select = 0, - /* Means SPI_CS_HIGH, change if e.g low CS */ - .mode = SPI_MODE_1 | SPI_LOOP, - }, -#endif -}; - -static struct pl022_ssp_controller ssp_platform_data = { - /* If you have several SPI buses this varies, we have only bus 0 */ - .bus_id = 0, - /* - * On the APP CPU GPIO 4, 5 and 6 are connected as generic - * chip selects for SPI. (Same on U330, U335 and U365.) - * TODO: make sure the GPIO driver can select these properly - * and do padmuxing accordingly too. - */ - .num_chipselect = 3, -#ifdef CONFIG_COH901318 - .enable_dma = 1, - .dma_filter = coh901318_filter_id, - .dma_rx_param = (void *) U300_DMA_SPI_RX, - .dma_tx_param = (void *) U300_DMA_SPI_TX, -#else - .enable_dma = 0, -#endif -}; - - -void __init u300_spi_init(struct amba_device *adev) -{ - adev->dev.platform_data = &ssp_platform_data; -} - -void __init u300_spi_register_board_devices(void) -{ - /* Register any SPI devices */ - spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices)); -} diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h deleted file mode 100644 index bd3d867e240..00000000000 --- a/arch/arm/mach-u300/spi.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-u300/spi.h - * - * Copyright (C) 2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * - * Author: Linus Walleij <linus.walleij@stericsson.com> - */ -#ifndef SPI_H -#define SPI_H -#include <linux/amba/bus.h> - -#ifdef CONFIG_SPI_PL022 -void __init u300_spi_init(struct amba_device *adev); -void __init u300_spi_register_board_devices(void); -#else -/* Compile out SPI support if PL022 is not selected */ -static inline void __init u300_spi_init(struct amba_device *adev) -{ -} -static inline void __init u300_spi_register_board_devices(void) -{ -} -#endif - -#endif diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index d9e73209c9b..390ae5feb1d 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -18,17 +18,15 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/irq.h> - -#include <mach/hardware.h> -#include <mach/irqs.h> +#include <linux/delay.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> /* Generic stuff */ #include <asm/sched_clock.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include "timer.h" - /* * APP side special timer registers * This timer contains four timers which can fire an interrupt each. @@ -189,6 +187,8 @@ #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) #define US_PER_TICK ((1000000 + (HZ/2)) / HZ) +static void __iomem *u300_timer_base; + /* * The u300_set_mode() function is always called first, if we * have oneshot timer active, the oneshot scheduling function @@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_PERIODIC: /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* * Set the periodic mode to a certain number of ticks per * jiffy. */ writel(TICKS_PER_JIFFY, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + u300_timer_base + U300_TIMER_APP_GPT1TC); /* * Set continuous mode, so the timer keeps triggering * interrupts. */ writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable timer interrupts */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Then enable the OS timer again */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); break; case CLOCK_EVT_MODE_ONESHOT: /* Just break; here? */ @@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode, */ /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* * Expire far in the future, u300_set_next_event() will be * called soon... */ - writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); /* We run one shot per tick here! */ writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable interrupts for this timer */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Enable timer */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: /* Disable interrupts on GP1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); break; case CLOCK_EVT_MODE_RESUME: /* Ignore this call */ @@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles, { /* Disable interrupts on GPT1 */ writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Disable GP1 while we're reprogramming it. */ writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); + u300_timer_base + U300_TIMER_APP_DGPT1); /* Reset the General Purpose timer 1. */ writel(U300_TIMER_APP_RGPT1_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + u300_timer_base + U300_TIMER_APP_RGPT1); /* IRQ in n * cycles */ - writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); + writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC); /* * We run one shot per tick here! (This is necessary to reconfigure, * the timer will tilt if you don't!) */ writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); + u300_timer_base + U300_TIMER_APP_SGPT1M); /* Enable timer interrupts */ writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); + u300_timer_base + U300_TIMER_APP_GPT1IE); /* Then enable the OS timer again */ writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); + u300_timer_base + U300_TIMER_APP_EGPT1); return 0; } @@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_u300_1mhz; /* ACK/Clear timer IRQ for the APP GPT1 Timer */ + writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); + u300_timer_base + U300_TIMER_APP_GPT1IA); evt->event_handler(evt); return IRQ_HANDLED; } @@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = { static u32 notrace u300_read_sched_clock(void) { - return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); + return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); +} + +static unsigned long u300_read_current_timer(void) +{ + return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); } +static struct delay_timer u300_delay_timer; /* * This sets up the system timers, clock source and clock event. */ -void __init u300_timer_init(void) +static void __init u300_timer_init_of(struct device_node *np) { + struct resource irq_res; + int irq; struct clk *clk; unsigned long rate; + u300_timer_base = of_iomap(np, 0); + if (!u300_timer_base) + panic("could not ioremap system timer\n"); + + /* Get the IRQ for the GP1 timer */ + irq = of_irq_to_resource(np, 2, &irq_res); + if (irq <= 0) + panic("no IRQ for system timer\n"); + + pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq); + /* Clock the interrupt controller */ - clk = clk_get_sys("apptimer", NULL); + clk = of_clk_get(np, 0); BUG_ON(IS_ERR(clk)); clk_prepare_enable(clk); rate = clk_get_rate(clk); setup_sched_clock(u300_read_sched_clock, 32, rate); + u300_delay_timer.read_current_timer = &u300_read_current_timer; + u300_delay_timer.freq = rate; + register_current_timer_delay(&u300_delay_timer); + /* * Disable the "OS" and "DD" timers - these are designed for Symbian! * Example usage in cnh1601578 cpu subsystem pd_timer_app.c */ writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); + u300_timer_base + U300_TIMER_APP_CRC); writel(U300_TIMER_APP_ROST_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); + u300_timer_base + U300_TIMER_APP_ROST); writel(U300_TIMER_APP_DOST_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); + u300_timer_base + U300_TIMER_APP_DOST); writel(U300_TIMER_APP_RDDT_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); + u300_timer_base + U300_TIMER_APP_RDDT); writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); + u300_timer_base + U300_TIMER_APP_DDDT); /* Reset the General Purpose timer 1. */ writel(U300_TIMER_APP_RGPT1_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); + u300_timer_base + U300_TIMER_APP_RGPT1); /* Set up the IRQ handler */ - setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); + setup_irq(irq, &u300_timer_irq); /* Reset the General Purpose timer 2 */ writel(U300_TIMER_APP_RGPT2_TIMER_RESET, - U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); + u300_timer_base + U300_TIMER_APP_RGPT2); /* Set this timer to run around forever */ - writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); + writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC); /* Set continuous mode so it wraps around */ writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, - U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); + u300_timer_base + U300_TIMER_APP_SGPT2M); /* Disable timer interrupts */ writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); + u300_timer_base + U300_TIMER_APP_GPT2IE); /* Then enable the GP2 timer to use as a free running us counter */ writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, - U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); + u300_timer_base + U300_TIMER_APP_EGPT2); /* Use general purpose timer 2 as clock source */ - if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, + if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC, "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) pr_err("timer: failed to initialize U300 clock source\n"); @@ -413,3 +437,6 @@ void __init u300_timer_init(void) * used by hrtimers! */ } + +CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer", + u300_timer_init_of); diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h deleted file mode 100644 index d34287bc34f..00000000000 --- a/arch/arm/mach-u300/timer.h +++ /dev/null @@ -1 +0,0 @@ -extern void u300_timer_init(void); diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h deleted file mode 100644 index 83f50772e16..00000000000 --- a/arch/arm/mach-u300/u300-gpio.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Individual pin assignments for the B335/S335. - * Notice that the actual usage of these pins depends on the - * PAD MUX settings, that is why the same number can potentially - * appear several times. In the reference design each pin is only - * used for one purpose. These were determined by inspecting the - * S365 schematic. - */ -#define U300_GPIO_PIN_UART_RX 0 -#define U300_GPIO_PIN_UART_TX 1 -#define U300_GPIO_PIN_UART_CTS 2 -#define U300_GPIO_PIN_UART_RTS 3 -#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */ -#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */ -#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */ -#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */ - -#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */ -#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */ -#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */ -#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */ -#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */ -#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */ -#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */ -#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */ -#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */ -#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */ -#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */ -#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */ -#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */ -#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */ -#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */ -#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */ -#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */ -#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */ -#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */ -#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */ -#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */ -#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */ -#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */ -#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */ -#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */ -#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */ -#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */ -#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */ -#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */ -#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */ -#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */ -#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */ -#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */ -#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */ -#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */ -#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */ - -#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */ -#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */ -#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */ -#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */ -#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */ -#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */ -#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */ -#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */ diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 947bd9eca07..7936d40a5c3 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -9,6 +9,7 @@ #include <linux/bug.h> #include <linux/string.h> #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> #include <linux/platform_data/pinctrl-nomadik.h> #include <asm/mach-types.h> @@ -34,6 +35,11 @@ BIAS(in_pd, PIN_INPUT_PULLDOWN); BIAS(out_hi, PIN_OUTPUT_HIGH); BIAS(out_lo, PIN_OUTPUT_LOW); BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE); + +BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); +BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); +BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); + /* These also force them into GPIO mode */ BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED); @@ -42,8 +48,6 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); /* Sleep modes */ -BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE); BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| @@ -54,8 +58,6 @@ BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE); BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH| @@ -97,6 +99,252 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| #define DB8500_PIN_STATE(pin, conf, dev, state) \ PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf) +#define AB8500_MUX_HOG(group, func) \ + PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func) +#define AB8500_PIN_HOG(pin, conf) \ + PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf) + +#define AB8500_MUX_STATE(group, func, dev, state) \ + PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func) +#define AB8500_PIN_STATE(pin, conf, dev, state) \ + PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf) + +#define AB8505_MUX_HOG(group, func) \ + PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func) +#define AB8505_PIN_HOG(pin, conf) \ + PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf) + +#define AB8505_MUX_STATE(group, func, dev, state) \ + PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func) +#define AB8505_PIN_STATE(pin, conf, dev, state) \ + PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf) + +static struct pinctrl_map __initdata ab8500_pinmap[] = { + /* Sysclkreq2 */ + AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT), + AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT), + /* sysclkreq2 disable, mux in gpio configured in input pulldown */ + AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP), + AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP), + + /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */ + AB8500_MUX_HOG("gpio2_a_1", "gpio"), + AB8500_PIN_HOG("GPIO2_T9", in_pd), + + /* Sysclkreq4 */ + AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT), + AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT), + /* sysclkreq4 disable, mux in gpio configured in input pulldown */ + AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), + AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), + + /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */ + AB8500_MUX_HOG("gpio4_a_1", "gpio"), + AB8500_PIN_HOG("GPIO4_W2", in_pd), + + /* + * pins 6,7,8 and 9 are muxed in YCBCR0123 + * configured in INPUT PULL UP + */ + AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"), + AB8500_PIN_HOG("GPIO6_Y18", in_nopull), + AB8500_PIN_HOG("GPIO7_AA20", in_nopull), + AB8500_PIN_HOG("GPIO8_W18", in_nopull), + AB8500_PIN_HOG("GPIO9_AA19", in_nopull), + + /* + * pins 10,11,12 and 13 are muxed in GPIO + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("gpio10_d_1", "gpio"), + AB8500_PIN_HOG("GPIO10_U17", in_pd), + + AB8500_MUX_HOG("gpio11_d_1", "gpio"), + AB8500_PIN_HOG("GPIO11_AA18", in_pd), + + AB8500_MUX_HOG("gpio12_d_1", "gpio"), + AB8500_PIN_HOG("GPIO12_U16", in_pd), + + AB8500_MUX_HOG("gpio13_d_1", "gpio"), + AB8500_PIN_HOG("GPIO13_W17", in_pd), + + /* + * pins 14,15 are muxed in PWM1 and PWM2 + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("pwmout1_d_1", "pwmout"), + AB8500_PIN_HOG("GPIO14_F14", in_pd), + + AB8500_MUX_HOG("pwmout2_d_1", "pwmout"), + AB8500_PIN_HOG("GPIO15_B17", in_pd), + + /* + * pins 16 is muxed in GPIO + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("gpio16_a_1", "gpio"), + AB8500_PIN_HOG("GPIO14_F14", in_pd), + + /* + * pins 17,18,19 and 20 are muxed in AUDIO interface 1 + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("adi1_d_1", "adi1"), + AB8500_PIN_HOG("GPIO17_P5", in_pd), + AB8500_PIN_HOG("GPIO18_R5", in_pd), + AB8500_PIN_HOG("GPIO19_U5", in_pd), + AB8500_PIN_HOG("GPIO20_T5", in_pd), + + /* + * pins 21,22 and 23 are muxed in USB UICC + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"), + AB8500_PIN_HOG("GPIO21_H19", in_pd), + AB8500_PIN_HOG("GPIO22_G20", in_pd), + AB8500_PIN_HOG("GPIO23_G19", in_pd), + + /* + * pins 24,25 are muxed in GPIO + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("gpio24_a_1", "gpio"), + AB8500_PIN_HOG("GPIO24_T14", in_pd), + + AB8500_MUX_HOG("gpio25_a_1", "gpio"), + AB8500_PIN_HOG("GPIO25_R16", in_pd), + + /* + * pins 26 is muxed in GPIO + * configured in OUTPUT LOW + */ + AB8500_MUX_HOG("gpio26_d_1", "gpio"), + AB8500_PIN_HOG("GPIO26_M16", out_lo), + + /* + * pins 27,28 are muxed in DMIC12 + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("dmic12_d_1", "dmic"), + AB8500_PIN_HOG("GPIO27_J6", in_pd), + AB8500_PIN_HOG("GPIO28_K6", in_pd), + + /* + * pins 29,30 are muxed in DMIC34 + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("dmic34_d_1", "dmic"), + AB8500_PIN_HOG("GPIO29_G6", in_pd), + AB8500_PIN_HOG("GPIO30_H6", in_pd), + + /* + * pins 31,32 are muxed in DMIC56 + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("dmic56_d_1", "dmic"), + AB8500_PIN_HOG("GPIO31_F5", in_pd), + AB8500_PIN_HOG("GPIO32_G5", in_pd), + + /* + * pins 34 is muxed in EXTCPENA + * configured INPUT PULL DOWN + */ + AB8500_MUX_HOG("extcpena_d_1", "extcpena"), + AB8500_PIN_HOG("GPIO34_R17", in_pd), + + /* + * pins 35 is muxed in GPIO + * configured in OUTPUT LOW + */ + AB8500_MUX_HOG("gpio35_d_1", "gpio"), + AB8500_PIN_HOG("GPIO35_W15", in_pd), + + /* + * pins 36,37,38 and 39 are muxed in GPIO + * configured in INPUT PULL DOWN + */ + AB8500_MUX_HOG("gpio36_a_1", "gpio"), + AB8500_PIN_HOG("GPIO36_A17", in_pd), + + AB8500_MUX_HOG("gpio37_a_1", "gpio"), + AB8500_PIN_HOG("GPIO37_E15", in_pd), + + AB8500_MUX_HOG("gpio38_a_1", "gpio"), + AB8500_PIN_HOG("GPIO38_C17", in_pd), + + AB8500_MUX_HOG("gpio39_a_1", "gpio"), + AB8500_PIN_HOG("GPIO39_E16", in_pd), + + /* + * pins 40 and 41 are muxed in MODCSLSDA + * configured INPUT PULL DOWN + */ + AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"), + AB8500_PIN_HOG("GPIO40_T19", in_pd), + AB8500_PIN_HOG("GPIO41_U19", in_pd), + + /* + * pins 42 is muxed in GPIO + * configured INPUT PULL DOWN + */ + AB8500_MUX_HOG("gpio42_a_1", "gpio"), + AB8500_PIN_HOG("GPIO42_U2", in_pd), +}; + +static struct pinctrl_map __initdata ab8505_pinmap[] = { + /* Sysclkreq2 */ + AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT), + AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT), + /* sysclkreq2 disable, mux in gpio configured in input pulldown */ + AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP), + AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP), + + /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */ + AB8505_MUX_HOG("gpio2_a_1", "gpio"), + AB8505_PIN_HOG("GPIO2_R5", in_pd), + + /* Sysclkreq4 */ + AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT), + AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT), + /* sysclkreq4 disable, mux in gpio configured in input pulldown */ + AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP), + AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP), + + AB8505_MUX_HOG("gpio10_d_1", "gpio"), + AB8505_PIN_HOG("GPIO10_B16", in_pd), + + AB8505_MUX_HOG("gpio11_d_1", "gpio"), + AB8505_PIN_HOG("GPIO11_B17", in_pd), + + AB8505_MUX_HOG("gpio13_d_1", "gpio"), + AB8505_PIN_HOG("GPIO13_D17", in_nopull), + + AB8505_MUX_HOG("pwmout1_d_1", "pwmout"), + AB8505_PIN_HOG("GPIO14_C16", in_pd), + + AB8505_MUX_HOG("adi2_d_1", "adi2"), + AB8505_PIN_HOG("GPIO17_P2", in_pd), + AB8505_PIN_HOG("GPIO18_N3", in_pd), + AB8505_PIN_HOG("GPIO19_T1", in_pd), + AB8505_PIN_HOG("GPIO20_P3", in_pd), + + AB8505_MUX_HOG("gpio34_a_1", "gpio"), + AB8505_PIN_HOG("GPIO34_H14", in_pd), + + AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"), + AB8505_PIN_HOG("GPIO40_J15", in_pd), + AB8505_PIN_HOG("GPIO41_J14", in_pd), + + AB8505_MUX_HOG("gpio50_d_1", "gpio"), + AB8505_PIN_HOG("GPIO50_L4", in_nopull), + + AB8505_MUX_HOG("resethw_d_1", "resethw"), + AB8505_PIN_HOG("GPIO52_D16", in_pd), + + AB8505_MUX_HOG("service_d_1", "service"), + AB8505_PIN_HOG("GPIO53_D15", in_pd), +}; + /* Pin control settings */ static struct pinctrl_map __initdata mop500_family_pinmap[] = { /* @@ -174,17 +422,12 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"), DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"), /* MSP1 for ALSA codec */ - DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"), - DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"), - DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"), - DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"), - DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"), - DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"), - /* MSP1 sleep state */ - DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"), - DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"), - DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"), - DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"), + DB8500_MUX_HOG("msp1txrx_a_1", "msp1"), + DB8500_MUX_HOG("msp1_a_1", "msp1"), + DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup), + DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup), + DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup), + DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup), /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), @@ -821,6 +1064,12 @@ void __init mop500_pinmaps_init(void) pinctrl_register_mappings(mop500_pinmap, ARRAY_SIZE(mop500_pinmap)); mop500_href_family_pinmaps_init(); + if (machine_is_u8520()) + pinctrl_register_mappings(ab8505_pinmap, + ARRAY_SIZE(ab8505_pinmap)); + else + pinctrl_register_mappings(ab8500_pinmap, + ARRAY_SIZE(ab8500_pinmap)); } void __init snowball_pinmaps_init(void) @@ -831,6 +1080,8 @@ void __init snowball_pinmaps_init(void) ARRAY_SIZE(snowball_pinmap)); pinctrl_register_mappings(u8500_pinmap, ARRAY_SIZE(u8500_pinmap)); + pinctrl_register_mappings(ab8500_pinmap, + ARRAY_SIZE(ab8500_pinmap)); } void __init hrefv60_pinmaps_init(void) @@ -840,4 +1091,6 @@ void __init hrefv60_pinmaps_init(void) pinctrl_register_mappings(hrefv60_pinmap, ARRAY_SIZE(hrefv60_pinmap)); mop500_href_family_pinmaps_init(); + pinctrl_register_mappings(ab8500_pinmap, + ARRAY_SIZE(ab8500_pinmap)); } diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index d6b7c8556fa..0dc44c68342 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -999,7 +999,6 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = { .num_ext_regulator = ARRAY_SIZE(ab8500_ext_regulators), }; -/* Use the AB8500 init settings for AB8505 as they are the same right now */ struct ab8500_regulator_platform_data ab8505_regulator_plat_data = { .reg_init = ab8505_reg_init, .num_reg_init = ARRAY_SIZE(ab8505_reg_init), diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 0ef38775a0c..43be3e0d4e3 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -52,11 +52,13 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { #endif struct mmci_platform_data mop500_sdi0_data = { - .ocr_mask = MMC_VDD_29_30, - .f_max = 50000000, + .f_max = 100000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | - MMC_CAP_MMC_HIGHSPEED, + MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | + MMC_CAP_UHS_SDR12 | + MMC_CAP_UHS_SDR25, .gpio_wp = -1, .sigdir = MCI_ST_FBCLKEN | MCI_ST_CMDDIREN | @@ -106,8 +108,9 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { struct mmci_platform_data mop500_sdi1_data = { .ocr_mask = MMC_VDD_29_30, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA, + .f_max = 100000000, + .capabilities = MMC_CAP_4_BIT_DATA | + MMC_CAP_NONREMOVABLE, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 @@ -143,9 +146,13 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { struct mmci_platform_data mop500_sdi2_data = { .ocr_mask = MMC_VDD_165_195, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, + .f_max = 100000000, + .capabilities = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NONREMOVABLE | + MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | + MMC_CAP_CMD23, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 @@ -180,10 +187,13 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { #endif struct mmci_platform_data mop500_sdi4_data = { - .ocr_mask = MMC_VDD_29_30, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, + .f_max = 100000000, + .capabilities = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_NONREMOVABLE | + MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | + MMC_CAP_CMD23, .gpio_cd = -1, .gpio_wp = -1, #ifdef CONFIG_STE_DMA40 diff --git a/arch/arm/mach-ux500/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h index b2d7a0b9862..27399553c84 100644 --- a/arch/arm/mach-ux500/db8500-regs.h +++ b/arch/arm/mach-ux500/db8500-regs.h @@ -102,7 +102,6 @@ #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) #define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000) #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) -#define U9540_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x6A000) #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) @@ -184,7 +183,7 @@ #define U8500_IO_VIRTUAL 0xf0000000 #define U8500_IO_PHYSICAL 0xa0000000 /* This is where we map in the ROM to check ASIC IDs */ -#define UX500_VIRT_ROM 0xf0000000 +#define UX500_VIRT_ROM IOMEM(0xf0000000) /* This macro is used in assembly, so no cast */ #define IO_ADDRESS(x) \ diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 1cf94ce0fee..ddbdcda8306 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -227,7 +227,7 @@ static struct resource db8500_prcmu_res[] = { { .name = "prcmu-tcpm", .start = U8500_PRCMU_TCPM_BASE, - .end = U8500_PRCMU_TCPM_BASE + SZ_4K - 1, + .end = U8500_PRCMU_TCPM_BASE + SZ_32K - 1, .flags = IORESOURCE_MEM, }, }; diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index 0d33d1a0695..392f2fdb37d 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -21,11 +21,11 @@ struct dbx500_asic_id dbx500_id; -static unsigned int ux500_read_asicid(phys_addr_t addr) +static unsigned int __init ux500_read_asicid(phys_addr_t addr) { phys_addr_t base = addr & ~0xfff; struct map_desc desc = { - .virtual = UX500_VIRT_ROM, + .virtual = (unsigned long)UX500_VIRT_ROM, .pfn = __phys_to_pfn(base), .length = SZ_16K, .type = MT_DEVICE, @@ -37,7 +37,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr) local_flush_tlb_all(); flush_cache_all(); - return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff))); + return readl(UX500_VIRT_ROM + (addr & 0xfff)); } static void ux500_print_soc_info(unsigned int asicid) diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 5907e10c37f..b8bbabec631 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -57,4 +57,13 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" +config ARCH_VEXPRESS_DCSCB + bool "Dual Cluster System Control Block (DCSCB) support" + depends on MCPM + select ARM_CCI + help + Support for the Dual Cluster System Configuration Block (DCSCB). + This is needed to provide CPU and cluster power management + on RTSM implementing big.LITTLE. + endmenu diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 42703e8b4d3..48ba89a8149 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ obj-y := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h index f134cd4a85f..bde4374ab6d 100644 --- a/arch/arm/mach-vexpress/core.h +++ b/arch/arm/mach-vexpress/core.h @@ -6,6 +6,8 @@ void vexpress_dt_smp_map_io(void); +bool vexpress_smp_init_ops(void); + extern struct smp_operations vexpress_smp_ops; extern void vexpress_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c new file mode 100644 index 00000000000..16d57a8a9d5 --- /dev/null +++ b/arch/arm/mach-vexpress/dcscb.c @@ -0,0 +1,253 @@ +/* + * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block + * + * Created by: Nicolas Pitre, May 2012 + * Copyright: (C) 2012-2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/spinlock.h> +#include <linux/errno.h> +#include <linux/of_address.h> +#include <linux/vexpress.h> +#include <linux/arm-cci.h> + +#include <asm/mcpm.h> +#include <asm/proc-fns.h> +#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <asm/cp15.h> + + +#define RST_HOLD0 0x0 +#define RST_HOLD1 0x4 +#define SYS_SWRESET 0x8 +#define RST_STAT0 0xc +#define RST_STAT1 0x10 +#define EAG_CFG_R 0x20 +#define EAG_CFG_W 0x24 +#define KFC_CFG_R 0x28 +#define KFC_CFG_W 0x2c +#define DCS_CFG_R 0x30 + +/* + * We can't use regular spinlocks. In the switcher case, it is possible + * for an outbound CPU to call power_down() while its inbound counterpart + * is already live using the same logical CPU number which trips lockdep + * debugging. + */ +static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED; + +static void __iomem *dcscb_base; +static int dcscb_use_count[4][2]; +static int dcscb_allcpus_mask[2]; + +static int dcscb_power_up(unsigned int cpu, unsigned int cluster) +{ + unsigned int rst_hold, cpumask = (1 << cpu); + unsigned int all_mask = dcscb_allcpus_mask[cluster]; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + if (cpu >= 4 || cluster >= 2) + return -EINVAL; + + /* + * Since this is called with IRQs enabled, and no arch_spin_lock_irq + * variant exists, we need to disable IRQs manually here. + */ + local_irq_disable(); + arch_spin_lock(&dcscb_lock); + + dcscb_use_count[cpu][cluster]++; + if (dcscb_use_count[cpu][cluster] == 1) { + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + if (rst_hold & (1 << 8)) { + /* remove cluster reset and add individual CPU's reset */ + rst_hold &= ~(1 << 8); + rst_hold |= all_mask; + } + rst_hold &= ~(cpumask | (cpumask << 4)); + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + } else if (dcscb_use_count[cpu][cluster] != 2) { + /* + * The only possible values are: + * 0 = CPU down + * 1 = CPU (still) up + * 2 = CPU requested to be up before it had a chance + * to actually make itself down. + * Any other value is a bug. + */ + BUG(); + } + + arch_spin_unlock(&dcscb_lock); + local_irq_enable(); + + return 0; +} + +static void dcscb_power_down(void) +{ + unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask; + bool last_man = false, skip_wfi = false; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + cpumask = (1 << cpu); + all_mask = dcscb_allcpus_mask[cluster]; + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= 4 || cluster >= 2); + + __mcpm_cpu_going_down(cpu, cluster); + + arch_spin_lock(&dcscb_lock); + BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); + dcscb_use_count[cpu][cluster]--; + if (dcscb_use_count[cpu][cluster] == 0) { + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); + rst_hold |= cpumask; + if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) { + rst_hold |= (1 << 8); + last_man = true; + } + writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); + } else if (dcscb_use_count[cpu][cluster] == 1) { + /* + * A power_up request went ahead of us. + * Even if we do not want to shut this CPU down, + * the caller expects a certain state as if the WFI + * was aborted. So let's continue with cache cleaning. + */ + skip_wfi = true; + } else + BUG(); + + if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { + arch_spin_unlock(&dcscb_lock); + + /* + * Flush all cache levels for this cluster. + * + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need + * a preliminary flush here for those CPUs. At least, that's + * the theory -- without the extra flush, Linux explodes on + * RTSM (to be investigated). + */ + flush_cache_all(); + set_cr(get_cr() & ~CR_C); + flush_cache_all(); + + /* + * This is a harmless no-op. On platforms with a real + * outer cache this might either be needed or not, + * depending on where the outer cache sits. + */ + outer_flush_all(); + + /* Disable local coherency by clearing the ACTLR "SMP" bit: */ + set_auxcr(get_auxcr() & ~(1 << 6)); + + /* + * Disable cluster-level coherency by masking + * incoming snoops and DVM messages: + */ + cci_disable_port_by_cpu(mpidr); + + __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN); + } else { + arch_spin_unlock(&dcscb_lock); + + /* + * Flush the local CPU cache. + * + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need + * a preliminary flush here for those CPUs. At least, that's + * the theory -- without the extra flush, Linux explodes on + * RTSM (to be investigated). + */ + flush_cache_louis(); + set_cr(get_cr() & ~CR_C); + flush_cache_louis(); + + /* Disable local coherency by clearing the ACTLR "SMP" bit: */ + set_auxcr(get_auxcr() & ~(1 << 6)); + } + + __mcpm_cpu_down(cpu, cluster); + + /* Now we are prepared for power-down, do it: */ + dsb(); + if (!skip_wfi) + wfi(); + + /* Not dead at this point? Let our caller cope. */ +} + +static const struct mcpm_platform_ops dcscb_power_ops = { + .power_up = dcscb_power_up, + .power_down = dcscb_power_down, +}; + +static void __init dcscb_usage_count_init(void) +{ + unsigned int mpidr, cpu, cluster; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); + BUG_ON(cpu >= 4 || cluster >= 2); + dcscb_use_count[cpu][cluster] = 1; +} + +extern void dcscb_power_up_setup(unsigned int affinity_level); + +static int __init dcscb_init(void) +{ + struct device_node *node; + unsigned int cfg; + int ret; + + if (!cci_probed()) + return -ENODEV; + + node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); + if (!node) + return -ENODEV; + dcscb_base = of_iomap(node, 0); + if (!dcscb_base) + return -EADDRNOTAVAIL; + cfg = readl_relaxed(dcscb_base + DCS_CFG_R); + dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; + dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; + dcscb_usage_count_init(); + + ret = mcpm_platform_register(&dcscb_power_ops); + if (!ret) + ret = mcpm_sync_init(dcscb_power_up_setup); + if (ret) { + iounmap(dcscb_base); + return ret; + } + + pr_info("VExpress DCSCB support installed\n"); + + /* + * Future entries into the kernel can now go + * through the cluster entry vectors. + */ + vexpress_flags_set(virt_to_phys(mcpm_entry_point)); + + return 0; +} + +early_initcall(dcscb_init); diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S new file mode 100644 index 00000000000..4bb7fbe0f62 --- /dev/null +++ b/arch/arm/mach-vexpress/dcscb_setup.S @@ -0,0 +1,38 @@ +/* + * arch/arm/include/asm/dcscb_setup.S + * + * Created by: Dave Martin, 2012-06-22 + * Copyright: (C) 2012-2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + + +ENTRY(dcscb_power_up_setup) + + cmp r0, #0 @ check affinity level + beq 2f + +/* + * Enable cluster-level coherency, in preparation for turning on the MMU. + * The ACTLR SMP bit does not need to be set here, because cpu_resume() + * already restores that. + * + * A15/A7 may not require explicit L2 invalidation on reset, dependent + * on hardware integration decisions. + * For now, this code assumes that L2 is either already invalidated, + * or invalidation is not required. + */ + + b cci_enable_port_for_self + +2: @ Implementation-specific local CPU setup operations should go here, + @ if any. In this case, there is nothing to do. + + bx lr + +ENDPROC(dcscb_power_up_setup) diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index dc1ace55d55..993c9ae5dc5 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -12,9 +12,11 @@ #include <linux/errno.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/of.h> #include <linux/of_fdt.h> #include <linux/vexpress.h> +#include <asm/mcpm.h> #include <asm/smp_scu.h> #include <asm/mach/map.h> @@ -203,3 +205,21 @@ struct smp_operations __initdata vexpress_smp_ops = { .cpu_die = vexpress_cpu_die, #endif }; + +bool __init vexpress_smp_init_ops(void) +{ +#ifdef CONFIG_MCPM + /* + * The best way to detect a multi-cluster configuration at the moment + * is to look for the presence of a CCI in the system. + * Override the default vexpress_smp_ops if so. + */ + struct device_node *node; + node = of_find_compatible_node(NULL, NULL, "arm,cci-400"); + if (node && of_device_is_available(node)) { + mcpm_smp_set_ops(); + return true; + } +#endif + return false; +} diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 8802030df98..95a469e23e3 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -9,7 +9,6 @@ #include <linux/clocksource.h> #include <linux/smp.h> #include <linux/init.h> -#include <linux/irqchip.h> #include <linux/of_address.h> #include <linux/of_fdt.h> #include <linux/of_irq.h> @@ -456,9 +455,9 @@ static const char * const v2m_dt_match[] __initconst = { DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") .dt_compat = v2m_dt_match, .smp = smp_ops(vexpress_smp_ops), + .smp_init = smp_init_ops(vexpress_smp_init_ops), .map_io = v2m_dt_map_io, .init_early = v2m_dt_init_early, - .init_irq = irqchip_init, .init_time = v2m_dt_timer_init, .init_machine = v2m_dt_init, MACHINE_END diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile index 042afc1f8c4..7ddbfa60227 100644 --- a/arch/arm/mach-virt/Makefile +++ b/arch/arm/mach-virt/Makefile @@ -3,4 +3,3 @@ # obj-y := virt.o -obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c deleted file mode 100644 index f4143f5bfa5..00000000000 --- a/arch/arm/mach-virt/platsmp.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Dummy Virtual Machine - does what it says on the tin. - * - * Copyright (C) 2012 ARM Ltd - * Author: Will Deacon <will.deacon@arm.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/init.h> -#include <linux/smp.h> -#include <linux/of.h> - -#include <asm/psci.h> -#include <asm/smp_plat.h> - -extern void secondary_startup(void); - -static void __init virt_smp_init_cpus(void) -{ -} - -static void __init virt_smp_prepare_cpus(unsigned int max_cpus) -{ -} - -static int __cpuinit virt_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - if (psci_ops.cpu_on) - return psci_ops.cpu_on(cpu_logical_map(cpu), - __pa(secondary_startup)); - return -ENODEV; -} - -struct smp_operations __initdata virt_smp_ops = { - .smp_init_cpus = virt_smp_init_cpus, - .smp_prepare_cpus = virt_smp_prepare_cpus, - .smp_boot_secondary = virt_boot_secondary, -}; diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c index 061f283f579..b184e57d185 100644 --- a/arch/arm/mach-virt/virt.c +++ b/arch/arm/mach-virt/virt.c @@ -18,7 +18,6 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <linux/irqchip.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/smp.h> @@ -36,11 +35,7 @@ static const char *virt_dt_match[] = { NULL }; -extern struct smp_operations virt_smp_ops; - DT_MACHINE_START(VIRT, "Dummy Virtual Machine") - .init_irq = irqchip_init, .init_machine = virt_init, - .smp = smp_ops(virt_smp_ops), .dt_compat = virt_dt_match, MACHINE_END diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index f5c33df7a59..f8f2f00856e 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -20,7 +20,6 @@ #include <linux/clocksource.h> #include <linux/io.h> -#include <linux/irqchip.h> #include <linux/pm.h> #include <asm/mach-types.h> @@ -179,7 +178,6 @@ static const char * const vt8500_dt_compat[] = { DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") .dt_compat = vt8500_dt_compat, .map_io = vt8500_map_io, - .init_irq = irqchip_init, .init_machine = vt8500_init, .init_time = clocksource_of_init, .restart = vt8500_restart, diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 7e3d5f400aa..4130e65a0e3 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -25,7 +25,6 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/of.h> -#include <linux/irqchip.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -105,7 +104,6 @@ static const char * const zynq_dt_match[] = { MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, - .init_irq = irqchip_init, .init_machine = zynq_init_machine, .init_time = zynq_timer_init, .dt_compat = zynq_dt_match, diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index 5fc167e0761..023f225493f 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -53,34 +53,34 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu) &zynq_secondary_trampoline; zynq_slcr_cpu_stop(cpu); - - if (__pa(PAGE_OFFSET)) { - zero = ioremap(0, trampoline_code_size); - if (!zero) { - pr_warn("BOOTUP jump vectors not accessible\n"); - return -1; + if (address) { + if (__pa(PAGE_OFFSET)) { + zero = ioremap(0, trampoline_code_size); + if (!zero) { + pr_warn("BOOTUP jump vectors not accessible\n"); + return -1; + } + } else { + zero = (__force u8 __iomem *)PAGE_OFFSET; } - } else { - zero = (__force u8 __iomem *)PAGE_OFFSET; - } - - /* - * This is elegant way how to jump to any address - * 0x0: Load address at 0x8 to r0 - * 0x4: Jump by mov instruction - * 0x8: Jumping address - */ - memcpy((__force void *)zero, &zynq_secondary_trampoline, - trampoline_size); - writel(address, zero + trampoline_size); - - flush_cache_all(); - outer_flush_range(0, trampoline_code_size); - smp_wmb(); - - if (__pa(PAGE_OFFSET)) - iounmap(zero); + /* + * This is elegant way how to jump to any address + * 0x0: Load address at 0x8 to r0 + * 0x4: Jump by mov instruction + * 0x8: Jumping address + */ + memcpy((__force void *)zero, &zynq_secondary_trampoline, + trampoline_size); + writel(address, zero + trampoline_size); + + flush_cache_all(); + outer_flush_range(0, trampoline_code_size); + smp_wmb(); + + if (__pa(PAGE_OFFSET)) + iounmap(zero); + } zynq_slcr_cpu_start(cpu); return 0; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 35955b54944..9e8101ecd63 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -397,6 +397,15 @@ config CPU_V7 select CPU_PABRT_V7 select CPU_TLB_V7 if MMU +# ARMv7M +config CPU_V7M + bool + select CPU_32v7M + select CPU_ABRT_NOMMU + select CPU_CACHE_NOP + select CPU_PABRT_LEGACY + select CPU_THUMBONLY + config CPU_THUMBONLY bool # There are no CPUs available with MMU that don't implement an ARM ISA: @@ -441,6 +450,9 @@ config CPU_32v6K config CPU_32v7 bool +config CPU_32v7M + bool + # The abort model config CPU_ABRT_NOMMU bool @@ -491,6 +503,9 @@ config CPU_CACHE_V6 config CPU_CACHE_V7 bool +config CPU_CACHE_NOP + bool + config CPU_CACHE_VIVT bool @@ -613,7 +628,11 @@ config ARCH_DMA_ADDR_T_64BIT config ARM_THUMB bool "Support Thumb user binaries" if !CPU_THUMBONLY - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ + CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ + CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ + CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ + CPU_V7 || CPU_FEROCEON || CPU_V7M default y help Say Y if you want to include kernel support for running user space diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 9e51be96f63..ee558a01f39 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o +obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o AFLAGS_cache-v6.o :=-Wa,-march=armv6 AFLAGS_cache-v7.o :=-Wa,-march=armv7-a @@ -87,6 +88,7 @@ obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6K) += proc-v6.o obj-$(CONFIG_CPU_V7) += proc-v7.o +obj-$(CONFIG_CPU_V7M) += proc-v7m.o AFLAGS_proc-v6.o :=-Wa,-march=armv6 AFLAGS_proc-v7.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S new file mode 100644 index 00000000000..8e12ddca003 --- /dev/null +++ b/arch/arm/mm/cache-nop.S @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + +#include "proc-macros.S" + +ENTRY(nop_flush_icache_all) + mov pc, lr +ENDPROC(nop_flush_icache_all) + + .globl nop_flush_kern_cache_all + .equ nop_flush_kern_cache_all, nop_flush_icache_all + + .globl nop_flush_kern_cache_louis + .equ nop_flush_kern_cache_louis, nop_flush_icache_all + + .globl nop_flush_user_cache_all + .equ nop_flush_user_cache_all, nop_flush_icache_all + + .globl nop_flush_user_cache_range + .equ nop_flush_user_cache_range, nop_flush_icache_all + + .globl nop_coherent_kern_range + .equ nop_coherent_kern_range, nop_flush_icache_all + +ENTRY(nop_coherent_user_range) + mov r0, 0 + mov pc, lr +ENDPROC(nop_coherent_user_range) + + .globl nop_flush_kern_dcache_area + .equ nop_flush_kern_dcache_area, nop_flush_icache_all + + .globl nop_dma_flush_range + .equ nop_dma_flush_range, nop_flush_icache_all + + .globl nop_dma_map_area + .equ nop_dma_map_area, nop_flush_icache_all + + .globl nop_dma_unmap_area + .equ nop_dma_unmap_area, nop_flush_icache_all + + __INITDATA + + @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) + define_cache_functions nop diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 15451ee4acc..515b00064da 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -92,6 +92,14 @@ ENTRY(v7_flush_dcache_louis) mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr +#ifdef CONFIG_ARM_ERRATA_643719 + ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register + ALT_UP(moveq pc, lr) @ LoUU is zero, so nothing to do + ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p? + biceq r2, r2, #0x0000000f @ clear minor revision number + teqeq r2, r1 @ test for errata affected core and if so... + orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne') +#endif ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2 ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2 moveq pc, lr @ return if level == 0 diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 0d473cce501..32aa5861119 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -301,6 +301,39 @@ void flush_dcache_page(struct page *page) EXPORT_SYMBOL(flush_dcache_page); /* + * Ensure cache coherency for the kernel mapping of this page. We can + * assume that the page is pinned via kmap. + * + * If the page only exists in the page cache and there are no user + * space mappings, this is a no-op since the page was already marked + * dirty at creation. Otherwise, we need to flush the dirty kernel + * cache lines directly. + */ +void flush_kernel_dcache_page(struct page *page) +{ + if (cache_is_vivt() || cache_is_vipt_aliasing()) { + struct address_space *mapping; + + mapping = page_mapping(page); + + if (!mapping || mapping_mapped(mapping)) { + void *addr; + + addr = page_address(page); + /* + * kmap_atomic() doesn't set the page virtual + * address for highmem pages, and + * kunmap_atomic() takes care of cache + * flushing already. + */ + if (!IS_ENABLED(CONFIG_HIGHMEM) || addr) + __cpuc_flush_dcache_area(addr, PAGE_SIZE); + } + } +} +EXPORT_SYMBOL(flush_kernel_dcache_page); + +/* * Flush an anonymous page so that users of get_user_pages() * can safely access the data. The expected sequence is: * diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e0d8565671a..d1d1cefa1f9 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -616,10 +616,12 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, } while (pte++, addr += PAGE_SIZE, addr != end); } -static void __init map_init_section(pmd_t *pmd, unsigned long addr, +static void __init __map_init_section(pmd_t *pmd, unsigned long addr, unsigned long end, phys_addr_t phys, const struct mem_type *type) { + pmd_t *p = pmd; + #ifndef CONFIG_ARM_LPAE /* * In classic MMU format, puds and pmds are folded in to @@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr, phys += SECTION_SIZE; } while (pmd++, addr += SECTION_SIZE, addr != end); - flush_pmd_entry(pmd); + flush_pmd_entry(p); } static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, @@ -661,7 +663,7 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, */ if (type->prot_sect && ((addr | next | phys) & ~SECTION_MASK) == 0) { - map_init_section(pmd, addr, next, phys, type); + __map_init_section(pmd, addr, next, phys, type); } else { alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys), type); @@ -1232,6 +1234,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc) */ if (mdesc->map_io) mdesc->map_io(); + else + debug_ll_io_init(); fill_pmd_gaps(); /* Reserve fixed i/o space in VMALLOC region */ diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index d51225f90ae..5a3aba614a4 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -20,12 +20,19 @@ void __init arm_mm_memblock_reserve(void) { +#ifndef CONFIG_CPU_V7M /* * Register the exception vector page. * some architectures which the DRAM is the exception vector to trap, * alloc_page breaks with error, although it is not NULL, but "0." */ memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); +#else /* ifndef CONFIG_CPU_V7M */ + /* + * There is no dedicated vector page on V7-M. So nothing needs to be + * reserved here. + */ +#endif } void __init sanity_check_meminfo(void) @@ -57,6 +64,12 @@ void flush_dcache_page(struct page *page) } EXPORT_SYMBOL(flush_dcache_page); +void flush_kernel_dcache_page(struct page *page) +{ + __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); +} +EXPORT_SYMBOL(flush_kernel_dcache_page); + void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long uaddr, void *dst, const void *src, unsigned long len) diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index d217e9795d7..aaeb6c127c7 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -81,7 +81,6 @@ ENDPROC(cpu_fa526_reset) */ .align 4 ENTRY(cpu_fa526_do_idle) - mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt mov pc, lr diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index f9a0aa725ea..e3c48a3fe06 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -333,3 +333,8 @@ ENTRY(\name\()_tlb_fns) .endif .size \name\()_tlb_fns, . - \name\()_tlb_fns .endm + +.macro globl_equ x, y + .globl \x + .equ \x, \y +.endm diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 2c73a7301ff..e35fec34453 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -140,6 +140,29 @@ ENTRY(cpu_v7_do_resume) ENDPROC(cpu_v7_do_resume) #endif +#ifdef CONFIG_CPU_PJ4B + globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm + globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext + globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init + globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin + globl_equ cpu_pj4b_reset, cpu_v7_reset +#ifdef CONFIG_PJ4B_ERRATA_4742 +ENTRY(cpu_pj4b_do_idle) + dsb @ WFI may enter a low-power mode + wfi + dsb @barrier + mov pc, lr +ENDPROC(cpu_pj4b_do_idle) +#else + globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle +#endif + globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area + globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend + globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume + globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + +#endif + __CPUINIT /* @@ -350,6 +373,9 @@ __v7_setup_stack: @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 +#ifdef CONFIG_CPU_PJ4B + define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 +#endif .section ".rodata" @@ -362,7 +388,7 @@ __v7_setup_stack: /* * Standard v7 proc info content */ -.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 +.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ @@ -375,7 +401,7 @@ __v7_setup_stack: .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ HWCAP_EDSP | HWCAP_TLS | \hwcaps .long cpu_v7_name - .long v7_processor_functions + .long \proc_fns .long v7wbi_tlb_fns .long v6_user_fns .long v7_cache_fns @@ -407,12 +433,14 @@ __v7_ca9mp_proc_info: /* * Marvell PJ4B processor. */ +#ifdef CONFIG_CPU_PJ4B .type __v7_pj4b_proc_info, #object __v7_pj4b_proc_info: - .long 0x562f5840 - .long 0xfffffff0 - __v7_proc __v7_pj4b_setup + .long 0x560f5800 + .long 0xff0fff00 + __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info +#endif /* * ARM Ltd. Cortex A7 processor. diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S new file mode 100644 index 00000000000..0c93588fcb9 --- /dev/null +++ b/arch/arm/mm/proc-v7m.S @@ -0,0 +1,157 @@ +/* + * linux/arch/arm/mm/proc-v7m.S + * + * Copyright (C) 2008 ARM Ltd. + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This is the "shell" of the ARMv7-M processor support. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/v7m.h> +#include "proc-macros.S" + +ENTRY(cpu_v7m_proc_init) + mov pc, lr +ENDPROC(cpu_v7m_proc_init) + +ENTRY(cpu_v7m_proc_fin) + mov pc, lr +ENDPROC(cpu_v7m_proc_fin) + +/* + * cpu_v7m_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * - loc - location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_v7m_reset) + mov pc, r0 +ENDPROC(cpu_v7m_reset) + +/* + * cpu_v7m_do_idle() + * + * Idle the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_v7m_do_idle) + wfi + mov pc, lr +ENDPROC(cpu_v7m_do_idle) + +ENTRY(cpu_v7m_dcache_clean_area) + mov pc, lr +ENDPROC(cpu_v7m_dcache_clean_area) + +/* + * There is no MMU, so here is nothing to do. + */ +ENTRY(cpu_v7m_switch_mm) + mov pc, lr +ENDPROC(cpu_v7m_switch_mm) + +.globl cpu_v7m_suspend_size +.equ cpu_v7m_suspend_size, 0 + +#ifdef CONFIG_ARM_CPU_SUSPEND +ENTRY(cpu_v7m_do_suspend) + mov pc, lr +ENDPROC(cpu_v7m_do_suspend) + +ENTRY(cpu_v7m_do_resume) + mov pc, lr +ENDPROC(cpu_v7m_do_resume) +#endif + + .section ".text.init", #alloc, #execinstr + +/* + * __v7m_setup + * + * This should be able to cover all ARMv7-M cores. + */ +__v7m_setup: + @ Configure the vector table base address + ldr r0, =BASEADDR_V7M_SCB + ldr r12, =vector_table + str r12, [r0, V7M_SCB_VTOR] + + @ enable UsageFault, BusFault and MemManage fault. + ldr r5, [r0, #V7M_SCB_SHCSR] + orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA) + str r5, [r0, #V7M_SCB_SHCSR] + + @ Lower the priority of the SVC and PendSV exceptions + mov r5, #0x80000000 + str r5, [r0, V7M_SCB_SHPR2] @ set SVC priority + mov r5, #0x00800000 + str r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority + + @ SVC to run the kernel in this mode + adr r1, BSYM(1f) + ldr r5, [r12, #11 * 4] @ read the SVC vector entry + str r1, [r12, #11 * 4] @ write the temporary SVC vector entry + mov r6, lr @ save LR + mov r7, sp @ save SP + ldr sp, =__v7m_setup_stack_top + cpsie i + svc #0 +1: cpsid i + str r5, [r12, #11 * 4] @ restore the original SVC vector entry + mov lr, r6 @ restore LR + mov sp, r7 @ restore SP + + @ Special-purpose control register + mov r1, #1 + msr control, r1 @ Thread mode has unpriviledged access + + @ Configure the System Control Register to ensure 8-byte stack alignment + @ Note the STKALIGN bit is either RW or RAO. + ldr r12, [r0, V7M_SCB_CCR] @ system control register + orr r12, #V7M_SCB_CCR_STKALIGN + str r12, [r0, V7M_SCB_CCR] + mov pc, lr +ENDPROC(__v7m_setup) + + define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1 + + .section ".rodata" + string cpu_arch_name, "armv7m" + string cpu_elf_name "v7m" + string cpu_v7m_name "ARMv7-M" + + .section ".proc.info.init", #alloc, #execinstr + + /* + * Match any ARMv7-M processor core. + */ + .type __v7m_proc_info, #object +__v7m_proc_info: + .long 0x000f0000 @ Required ID value + .long 0x000f0000 @ Mask for ID + .long 0 @ proc_info_list.__cpu_mm_mmu_flags + .long 0 @ proc_info_list.__cpu_io_mmu_flags + b __v7m_setup @ proc_info_list.__cpu_flush + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT + .long cpu_v7m_name + .long v7m_processor_functions @ proc_info_list.proc + .long 0 @ proc_info_list.tlb + .long 0 @ proc_info_list.user + .long nop_cache_fns @ proc_info_list.cache + .size __v7m_proc_info, . - __v7m_proc_info + +__v7m_setup_stack: + .space 4 * 8 @ 8 registers +__v7m_setup_stack_top: diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index e06c34bdc34..4d463ca6821 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -701,8 +701,8 @@ int omap_request_dma(int dev_id, const char *dev_name, for (ch = 0; ch < dma_chan_count; ch++) { if (free_ch == -1 && dma_chan[ch].dev_id == -1) { free_ch = ch; - if (dev_id == 0) - break; + /* Exit after first free channel found */ + break; } } if (free_ch == -1) { @@ -894,11 +894,12 @@ void omap_start_dma(int lch) int next_lch, cur_lch; char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; - dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ enable_lnk(lch); memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); + dma_chan_link_map[lch] = 1; + cur_lch = dma_chan[lch].next_lch; do { next_lch = dma_chan[cur_lch].next_lch; @@ -2110,8 +2111,6 @@ exit_dma_irq_fail: } exit_dma_lch_fail: - kfree(p); - kfree(d); kfree(dma_chan); return ret; } @@ -2132,8 +2131,6 @@ static int omap_system_dma_remove(struct platform_device *pdev) free_irq(dma_irq, (void *)(irq_rel + 1)); } } - kfree(p); - kfree(d); kfree(dma_chan); return 0; } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index f8ed2de0a67..3dc5cbea86c 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -6,7 +6,7 @@ config PLAT_SAMSUNG bool - depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P + depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS default y select GENERIC_IRQ_CHIP select NO_IOPORT @@ -15,12 +15,10 @@ config PLAT_SAMSUNG config PLAT_S5P bool - depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) default y select ARCH_REQUIRE_GPIOLIB - select ARM_GIC if ARCH_EXYNOS - select ARM_VIC if !ARCH_EXYNOS - select GIC_NON_BANKED if ARCH_EXYNOS4 + select ARM_VIC select NO_IOPORT select PLAT_SAMSUNG select S3C_GPIO_TRACK @@ -60,6 +58,20 @@ config S3C_LOWLEVEL_UART_PORT this configuration should be between zero and two. The port must have been initialised by the boot-loader before use. +config SAMSUNG_ATAGS + def_bool n + depends on !ARCH_MULTIPLATFORM + depends on ATAGS + help + This option enables ATAGS based boot support code for + Samsung platforms, including static platform devices, legacy + clock, timer and interrupt initialization, etc. + + Platforms that support only DT based boot need not to select + this option. + +if SAMSUNG_ATAGS + # timer options config SAMSUNG_HRT @@ -367,11 +379,6 @@ config S5P_DEV_JPEG help Compile in platform device definitions for JPEG codec -config S5P_DEV_MFC - bool - help - Compile in setup memory (init) code for MFC - config S5P_DEV_ONENAND bool help @@ -412,6 +419,21 @@ config S3C_DMA help Internal configuration for S3C DMA core +config S5P_IRQ_PM + bool + default y if S5P_PM + help + Legacy IRQ power management for S5P platforms + +config SAMSUNG_PM_GPIO + bool + default y if GPIO_SAMSUNG && PM + help + Include legacy GPIO power management code for platforms not using + pinctrl-samsung driver. + +endif + config SAMSUNG_DMADEV bool select ARM_AMBA @@ -421,6 +443,11 @@ config SAMSUNG_DMADEV help Use DMA device engine for PL330 DMAC. +config S5P_DEV_MFC + bool + help + Compile in setup memory (init) code for MFC + comment "Power management" config SAMSUNG_PM_DEBUG @@ -475,6 +502,12 @@ config SAMSUNG_WAKEMASK and above. This code allows a set of interrupt to wakeup-mask mappings. See <plat/wakeup-mask.h> +config SAMSUNG_WDT_RESET + bool + help + Compile support for system restart by triggering watchdog reset. + Used on SoCs that do not provide dedicated reset control. + config S5P_PM bool help diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index a23c460299a..98d07d8fc7a 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -31,10 +31,10 @@ obj-$(CONFIG_S3C_ADC) += adc.o # devices -obj-y += platformdata.o +obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o -obj-y += devs.o -obj-y += dev-uart.o +obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o +obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o @@ -52,10 +52,12 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o # PM support obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm-gpio.o +obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o +obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o -obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o +obj-$(CONFIG_S5P_PM) += s5p-pm.o +obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h index d01576318b2..bd3a6db14cb 100644 --- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h +++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h @@ -28,7 +28,6 @@ struct s3c24xx_dma_map { const char *name; unsigned long channels[S3C_DMA_CHANNELS]; - unsigned long channels_rx[S3C_DMA_CHANNELS]; }; struct s3c24xx_dma_selection { @@ -38,10 +37,6 @@ struct s3c24xx_dma_selection { void (*select)(struct s3c2410_dma_chan *chan, struct s3c24xx_dma_map *map); - - void (*direction)(struct s3c2410_dma_chan *chan, - struct s3c24xx_dma_map *map, - enum dma_data_direction dir); }; extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6fcadeee96..5d47ca35cab 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void); */ extern void s3c_pm_configure_extint(void); +#ifdef CONFIG_GPIO_SAMSUNG /** * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. * @@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void); * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). */ extern void samsung_pm_save_gpios(void); +#else +static inline void samsung_pm_restore_gpios(void) {} +static inline void samsung_pm_save_gpios(void) {} +#endif extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h deleted file mode 100644 index 4938492470f..00000000000 --- a/arch/arm/plat-samsung/include/plat/regs-watchdog.h +++ /dev/null @@ -1,41 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 Watchdog timer control -*/ - - -#ifndef __ASM_ARCH_REGS_WATCHDOG_H -#define __ASM_ARCH_REGS_WATCHDOG_H - -#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) - -#define S3C2410_WTCON S3C_WDOGREG(0x00) -#define S3C2410_WTDAT S3C_WDOGREG(0x04) -#define S3C2410_WTCNT S3C_WDOGREG(0x08) - -/* the watchdog can either generate a reset pulse, or an - * interrupt. - */ - -#define S3C2410_WTCON_RSTEN (0x01) -#define S3C2410_WTCON_INTEN (1<<2) -#define S3C2410_WTCON_ENABLE (1<<5) - -#define S3C2410_WTCON_DIV16 (0<<3) -#define S3C2410_WTCON_DIV32 (1<<3) -#define S3C2410_WTCON_DIV64 (2<<3) -#define S3C2410_WTCON_DIV128 (3<<3) - -#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) -#define S3C2410_WTCON_PRESCALE_MASK (0xff00) - -#endif /* __ASM_ARCH_REGS_WATCHDOG_H */ - - diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h index 02b66d723d1..4afc32f90b6 100644 --- a/arch/arm/plat-samsung/include/plat/uncompress.h +++ b/arch/arm/plat-samsung/include/plat/uncompress.h @@ -21,6 +21,8 @@ typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ unsigned int fifo_mask; unsigned int fifo_max; +volatile u8 *uart_base; + /* forward declerations */ static void arch_detect_cpu(void); @@ -28,19 +30,24 @@ static void arch_detect_cpu(void); /* defines for UART registers */ #include <plat/regs-serial.h> -#include <plat/regs-watchdog.h> /* working in physical space... */ -#undef S3C2410_WDOGREG -#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x))) +#define S3C_WDOGREG(x) ((S3C_PA_WDT + (x))) + +#define S3C2410_WTCON S3C_WDOGREG(0x00) +#define S3C2410_WTDAT S3C_WDOGREG(0x04) +#define S3C2410_WTCNT S3C_WDOGREG(0x08) + +#define S3C2410_WTCON_RSTEN (1 << 0) +#define S3C2410_WTCON_ENABLE (1 << 5) + +#define S3C2410_WTCON_DIV128 (3 << 3) + +#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) /* how many bytes we allow into the FIFO at a time in FIFO mode */ #define FIFO_MAX (14) -#ifdef S3C_PA_UART -#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) -#endif - static __inline__ void uart_wr(unsigned int reg, unsigned int val) { diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index bc4db9b04e3..0386b8f7662 100644 --- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h @@ -10,37 +10,11 @@ * published by the Free Software Foundation. */ -#include <plat/clock.h> -#include <plat/regs-watchdog.h> -#include <mach/map.h> +#ifndef __PLAT_SAMSUNG_WATCHDOG_RESET_H +#define __PLAT_SAMSUNG_WATCHDOG_RESET_H -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/delay.h> +extern void samsung_wdt_reset(void); +extern void samsung_wdt_reset_of_init(void); +extern void samsung_wdt_reset_init(void __iomem *base); -static inline void arch_wdt_reset(void) -{ - printk("arch_reset: attempting watchdog reset\n"); - - __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - - if (!IS_ERR(s3c2410_wdtclk)) - clk_enable(s3c2410_wdtclk); - - /* put initial values into count and data */ - __raw_writel(0x80, S3C2410_WTCNT); - __raw_writel(0x80, S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); -} +#endif /* __PLAT_SAMSUNG_WATCHDOG_RESET_H */ diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c index 79d10fca909..3e5c4619caa 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/plat-samsung/init.c @@ -87,7 +87,7 @@ void __init s3c24xx_init_clocks(int xtal) } /* uart management */ - +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) static int nr_uarts __initdata = 0; static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; @@ -134,11 +134,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) if (cpu == NULL) return; - if (cpu->init_uarts == NULL) { + if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) { printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); } else (cpu->init_uarts)(cfg, no); } +#endif static int __init s3c_arch_init(void) { @@ -152,8 +153,9 @@ static int __init s3c_arch_init(void) ret = (cpu->init)(); if (ret != 0) return ret; - +#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS) ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); +#endif return ret; } diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index c2ff92c30bd..a8de3cfe2ee 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -192,7 +192,8 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = { .resume = samsung_gpio_pm_2bit_resume, }; -#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \ + || defined(CONFIG_ARCH_EXYNOS) static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) { chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); @@ -302,7 +303,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = { .save = samsung_gpio_pm_4bit_save, .resume = samsung_gpio_pm_4bit_resume, }; -#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */ /** * samsung_pm_save_gpio() - save gpio chip data for suspend diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index bd7124c87fe..ea361364245 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -22,13 +22,17 @@ #include <asm/cacheflush.h> #include <asm/suspend.h> -#include <mach/hardware.h> -#include <mach/map.h> #include <plat/regs-serial.h> + +#ifdef CONFIG_SAMSUNG_ATAGS +#include <mach/hardware.h> +#include <mach/map.h> #include <mach/regs-clock.h> #include <mach/regs-irq.h> #include <mach/irqs.h> +#endif + #include <asm/irq.h> #include <plat/pm.h> diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index a93fb6fb660..ad51f85fbd0 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -17,10 +17,12 @@ #include <linux/of_fdt.h> #include <linux/of.h> +#include <plat/mfc.h> + +#ifdef CONFIG_SAMSUNG_ATAGS #include <mach/map.h> #include <mach/irqs.h> #include <plat/devs.h> -#include <plat/mfc.h> static struct resource s5p_mfc_resource[] = { [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), @@ -61,6 +63,10 @@ struct platform_device s5p_device_mfc_r = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; +#else +static struct platform_device s5p_device_mfc_l; +static struct platform_device s5p_device_mfc_r; +#endif struct s5p_mfc_reserved_mem { phys_addr_t base; @@ -70,6 +76,7 @@ struct s5p_mfc_reserved_mem { static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; + void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize) { @@ -93,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, } } +#ifdef CONFIG_SAMSUNG_ATAGS static int __init s5p_mfc_memory_init(void) { int i; @@ -111,6 +119,7 @@ static int __init s5p_mfc_memory_init(void) return 0; } device_initcall(s5p_mfc_memory_init); +#endif #ifdef CONFIG_OF int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname, diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c new file mode 100644 index 00000000000..2ecb50bea04 --- /dev/null +++ b/arch/arm/plat-samsung/watchdog-reset.c @@ -0,0 +1,97 @@ +/* arch/arm/plat-samsung/watchdog-reset.c + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Coyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> + * + * Watchdog reset support for Samsung SoCs. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#define S3C2410_WTCON 0x00 +#define S3C2410_WTDAT 0x04 +#define S3C2410_WTCNT 0x08 + +#define S3C2410_WTCON_ENABLE (1 << 5) +#define S3C2410_WTCON_DIV16 (0 << 3) +#define S3C2410_WTCON_RSTEN (1 << 0) +#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) + +static void __iomem *wdt_base; +static struct clk *wdt_clock; + +void samsung_wdt_reset(void) +{ + if (!wdt_base) { + pr_err("%s: wdt reset not initialized\n", __func__); + /* delay to allow the serial port to show the message */ + mdelay(50); + return; + } + + if (!IS_ERR(wdt_clock)) + clk_prepare_enable(wdt_clock); + + /* disable watchdog, to be safe */ + __raw_writel(0, wdt_base + S3C2410_WTCON); + + /* put initial values into count and data */ + __raw_writel(0x80, wdt_base + S3C2410_WTCNT); + __raw_writel(0x80, wdt_base + S3C2410_WTDAT); + + /* set the watchdog to go and reset... */ + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | + S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), + wdt_base + S3C2410_WTCON); + + /* wait for reset to assert... */ + mdelay(500); + + pr_err("Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); +} + +#ifdef CONFIG_OF +static const struct of_device_id s3c2410_wdt_match[] = { + { .compatible = "samsung,s3c2410-wdt" }, + {}, +}; + +void __init samsung_wdt_reset_of_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, s3c2410_wdt_match); + if (!np) { + pr_err("%s: failed to find watchdog node\n", __func__); + return; + } + + wdt_base = of_iomap(np, 0); + if (!wdt_base) { + pr_err("%s: failed to map watchdog registers\n", __func__); + return; + } + + wdt_clock = of_clk_get(np, 0); +} +#endif + +void __init samsung_wdt_reset_init(void __iomem *base) +{ + wdt_base = base; + wdt_clock = clk_get(NULL, "watchdog"); +} |