diff options
Diffstat (limited to 'arch/blackfin/include/asm')
| -rw-r--r-- | arch/blackfin/include/asm/bfin-global.h | 8 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/bfin_crc.h | 14 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/bfin_serial.h | 2 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/bfin_simple_timer.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/bfin_twi.h | 10 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/context.S | 9 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/dpmc.h | 2 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/gpio.h | 2 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/irq.h | 10 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mem_init.h | 212 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/traps.h | 2 |
11 files changed, 255 insertions, 22 deletions
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 608be5e6d25..dc47d79287f 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h @@ -14,7 +14,13 @@ #include <linux/linkage.h> #include <linux/types.h> -#if defined(CONFIG_DMA_UNCACHED_4M) +#if defined(CONFIG_DMA_UNCACHED_32M) +# define DMA_UNCACHED_REGION (32 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_16M) +# define DMA_UNCACHED_REGION (16 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_8M) +# define DMA_UNCACHED_REGION (8 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_4M) # define DMA_UNCACHED_REGION (4 * 1024 * 1024) #elif defined(CONFIG_DMA_UNCACHED_2M) # define DMA_UNCACHED_REGION (2 * 1024 * 1024) diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h index 3deb4452cee..75cef4dc85a 100644 --- a/arch/blackfin/include/asm/bfin_crc.h +++ b/arch/blackfin/include/asm/bfin_crc.h @@ -79,20 +79,6 @@ struct crc_register { u32 revid; }; -struct bfin_crc { - struct miscdevice mdev; - struct list_head list; - int irq; - int dma_ch_src; - int dma_ch_dest; - volatile struct crc_register *regs; - struct crc_info *info; - struct mutex mutex; - struct completion c; - unsigned short opmode; - char name[20]; -}; - /* CRC_STATUS Masks */ #define CMPERR 0x00000002 /* Compare error */ #define DCNTEXP 0x00000010 /* datacnt register expired */ diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h index 8597158010b..2d90d62edc9 100644 --- a/arch/blackfin/include/asm/bfin_serial.h +++ b/arch/blackfin/include/asm/bfin_serial.h @@ -282,7 +282,7 @@ struct bfin_uart_regs { #define UART_GET_GCTL(p) UART_GET_CTL(p) #define UART_GET_LCR(p) UART_GET_CTL(p) #define UART_GET_MCR(p) UART_GET_CTL(p) -#if ANOMALY_05001001 +#if ANOMALY_16000030 #define UART_GET_STAT(p) \ ({ \ u32 __ret; \ diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h index aadfb1ad1fa..b2d5e733079 100644 --- a/arch/blackfin/include/asm/bfin_simple_timer.h +++ b/arch/blackfin/include/asm/bfin_simple_timer.h @@ -17,5 +17,11 @@ #define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) #define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) #define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) +#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11) + +#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0 +#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1 +#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2 +#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3 #endif diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h index 2f3339a4762..f4a07278743 100644 --- a/arch/blackfin/include/asm/bfin_twi.h +++ b/arch/blackfin/include/asm/bfin_twi.h @@ -66,9 +66,9 @@ struct bfin_twi_iface { #define DEFINE_TWI_REG(reg_name, reg) \ static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ - { return iface->regs_base->reg; } \ + { return bfin_read16(&iface->regs_base->reg); } \ static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ - { iface->regs_base->reg = v; } + { bfin_write16(&iface->regs_base->reg, v); } DEFINE_TWI_REG(CLKDIV, clkdiv) DEFINE_TWI_REG(CONTROL, control) @@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl) DEFINE_TWI_REG(FIFO_STAT, fifo_stat) DEFINE_TWI_REG(XMT_DATA8, xmt_data8) DEFINE_TWI_REG(XMT_DATA16, xmt_data16) -#if !ANOMALY_05001001 +#if !ANOMALY_16000030 DEFINE_TWI_REG(RCV_DATA8, rcv_data8) DEFINE_TWI_REG(RCV_DATA16, rcv_data16) #else @@ -94,7 +94,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) unsigned long flags; flags = hard_local_irq_save(); - ret = iface->regs_base->rcv_data8; + ret = bfin_read16(&iface->regs_base->rcv_data8); hard_local_irq_restore(flags); return ret; @@ -106,7 +106,7 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) unsigned long flags; flags = hard_local_irq_save(); - ret = iface->regs_base->rcv_data16; + ret = bfin_read16(&iface->regs_base->rcv_data16); hard_local_irq_restore(flags); return ret; diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S index 1f9060395a0..507e7aa6a56 100644 --- a/arch/blackfin/include/asm/context.S +++ b/arch/blackfin/include/asm/context.S @@ -396,3 +396,12 @@ call \func; #endif .endm + +#if defined(CONFIG_BFIN_SCRATCH_REG_RETN) +# define EX_SCRATCH_REG RETN +#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE) +# define EX_SCRATCH_REG RETE +#else +# define EX_SCRATCH_REG CYCLES +#endif + diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h index e91eae8330a..2673b11376f 100644 --- a/arch/blackfin/include/asm/dpmc.h +++ b/arch/blackfin/include/asm/dpmc.h @@ -280,7 +280,7 @@ PM_POP_SYNC(9) #endif -#ifdef EBIU_AMBCTL +#ifdef EBIU_AMGCTL PM_SYS_POP(9, EBIU_AMBCTL1) PM_SYS_POP(8, EBIU_AMBCTL0) PM_SYS_POP16(7, EBIU_AMGCTL) diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 3d84d96f7c2..98d0133346b 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -141,6 +141,8 @@ static inline void bfin_pm_standby_restore(void) void bfin_gpio_pm_hibernate_restore(void); void bfin_gpio_pm_hibernate_suspend(void); +void bfin_pint_suspend(void); +void bfin_pint_resume(void); # if !BFIN_GPIO_PINT int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 89de539ed01..4ae1144a457 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h @@ -20,6 +20,16 @@ /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ #include <mach/irq.h> +/* + * pm save bfin pint registers + */ +struct bfin_pm_pint_save { + u32 mask_set; + u32 assign; + u32 edge_set; + u32 invert_set; +}; + #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) # define NOP_PAD_ANOMALY_05000244 "nop; nop;" #else diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 237579935e2..f019e9bcefe 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -6,6 +6,9 @@ * Licensed under the GPL-2 or later. */ +#ifndef __MEM_INIT_H__ +#define __MEM_INIT_H__ + #if defined(EBIU_SDGCTL) #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ @@ -277,3 +280,212 @@ #else #define PLL_BYPASS 0 #endif + +#ifdef CONFIG_BF60x + +/* DMC status bits */ +#define IDLE 0x1 +#define MEMINITDONE 0x4 +#define SRACK 0x8 +#define PDACK 0x10 +#define DPDACK 0x20 +#define DLLCALDONE 0x2000 +#define PENDREF 0xF0000 +#define PHYRDPHASE 0xF00000 +#define PHYRDPHASE_OFFSET 20 + +/* DMC control bits */ +#define LPDDR 0x2 +#define INIT 0x4 +#define SRREQ 0x8 +#define PDREQ 0x10 +#define DPDREQ 0x20 +#define PREC 0x40 +#define ADDRMODE 0x100 +#define RDTOWR 0xE00 +#define PPREF 0x1000 +#define DLLCAL 0x2000 + +/* DMC DLL control bits */ +#define DLLCALRDCNT 0xFF +#define DATACYC 0xF00 +#define DATACYC_OFFSET 8 + +/* CGU Divisor bits */ +#define CSEL_OFFSET 0 +#define S0SEL_OFFSET 5 +#define SYSSEL_OFFSET 8 +#define S1SEL_OFFSET 13 +#define DSEL_OFFSET 16 +#define OSEL_OFFSET 22 +#define ALGN 0x20000000 +#define UPDT 0x40000000 +#define LOCK 0x80000000 + +/* CGU Status bits */ +#define PLLEN 0x1 +#define PLLBP 0x2 +#define PLOCK 0x4 +#define CLKSALGN 0x8 + +/* CGU Control bits */ +#define MSEL_MASK 0x7F00 +#define DF_MASK 0x1 + +struct ddr_config { + u32 ddr_clk; + u32 dmc_ddrctl; + u32 dmc_ddrcfg; + u32 dmc_ddrtr0; + u32 dmc_ddrtr1; + u32 dmc_ddrtr2; + u32 dmc_ddrmr; + u32 dmc_ddrmr1; +}; + +#if defined(CONFIG_MEM_MT47H64M16) +static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { + [0] = { + .ddr_clk = 125, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20705212, + .dmc_ddrtr1 = 0x201003CF, + .dmc_ddrtr2 = 0x00320107, + .dmc_ddrmr = 0x00000422, + .dmc_ddrmr1 = 0x4, + }, + [1] = { + .ddr_clk = 133, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20806313, + .dmc_ddrtr1 = 0x2013040D, + .dmc_ddrtr2 = 0x00320108, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [2] = { + .ddr_clk = 150, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x20160492, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [3] = { + .ddr_clk = 166, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x2016050E, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [4] = { + .ddr_clk = 200, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20a07323, + .dmc_ddrtr1 = 0x2016050f, + .dmc_ddrtr2 = 0x00320509, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [5] = { + .ddr_clk = 225, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x302006DB, + .dmc_ddrtr2 = 0x0032020D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, + [6] = { + .ddr_clk = 250, + .dmc_ddrctl = 0x00000904, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x3020079E, + .dmc_ddrtr2 = 0x0032020D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, +}; +#endif + +static inline void dmc_enter_self_refresh(void) +{ + if (bfin_read_DMC0_STAT() & MEMINITDONE) { + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); + while (!(bfin_read_DMC0_STAT() & SRACK)) + continue; + } +} + +static inline void dmc_exit_self_refresh(void) +{ + if (bfin_read_DMC0_STAT() & MEMINITDONE) { + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); + while (bfin_read_DMC0_STAT() & SRACK) + continue; + } +} + +static inline void init_cgu(u32 cgu_div, u32 cgu_ctl) +{ + dmc_enter_self_refresh(); + + /* Don't set the same value of MSEL and DF to CGU_CTL */ + if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) + != cgu_ctl) { + bfin_write32(CGU0_DIV, cgu_div); + bfin_write32(CGU0_CTL, cgu_ctl); + while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || + !(bfin_read32(CGU0_STAT) & PLOCK)) + continue; + } + + bfin_write32(CGU0_DIV, cgu_div | UPDT); + while (bfin_read32(CGU0_STAT) & CLKSALGN) + continue; + + dmc_exit_self_refresh(); +} + +static inline void init_dmc(u32 dmc_clk) +{ + int i, dlldatacycle, dll_ctl; + + for (i = 0; i < 7; i++) { + if (ddr_config_table[i].ddr_clk == dmc_clk) { + bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); + bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); + bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); + bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); + bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); + bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); + bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); + break; + } + } + + while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) + continue; + + dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; + dll_ctl = bfin_read_DMC0_DLLCTL(); + dll_ctl &= ~DATACYC; + bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); + + while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) + continue; +} +#endif + +#endif /*__MEM_INIT_H__*/ + diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 70c4e511cae..cec771b8100 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -125,5 +125,7 @@ level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ level " only instructions.\n" +extern void double_fault_c(struct pt_regs *fp); + #endif /* __ASSEMBLY__ */ #endif /* _BFIN_TRAPS_H */ |