diff options
Diffstat (limited to 'arch/blackfin/kernel/cplb-nompu')
| -rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinfo.c | 15 | ||||
| -rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinit.c | 31 |
2 files changed, 32 insertions, 14 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c index a4f0b428a34..1e74f0b9799 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c @@ -33,9 +33,7 @@ #include <linux/proc_fs.h> #include <linux/uaccess.h> -#include <asm/current.h> -#include <asm/system.h> -#include <asm/cplb.h> +#include <asm/cplbinit.h> #include <asm/blackfin.h> #define CPLB_I 1 @@ -174,16 +172,6 @@ static int cplbinfo_read_proc(char *page, char **start, off_t off, return len; } -static int cplbinfo_write_proc(struct file *file, const char __user *buffer, - unsigned long count, void *data) -{ - printk(KERN_INFO "Reset the CPLB swap in/out counts.\n"); - memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long)); - memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long)); - - return count; -} - static int __init cplbinfo_init(void) { struct proc_dir_entry *entry; @@ -193,7 +181,6 @@ static int __init cplbinfo_init(void) return -ENOMEM; entry->read_proc = cplbinfo_read_proc; - entry->write_proc = cplbinfo_write_proc; entry->data = NULL; return 0; diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 6320bc45fbb..917325bfbd8 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -26,6 +26,35 @@ #include <asm/cplb.h> #include <asm/cplbinit.h> +#ifdef CONFIG_MAX_MEM_SIZE +# define CPLB_MEM CONFIG_MAX_MEM_SIZE +#else +# define CPLB_MEM CONFIG_MEM_SIZE +#endif + +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* possibly 1 for L2 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ +#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \ + + ASYNC_MEMORY_CPLB_COVERAGE) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* possibly 1 for L2 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ +#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2) + + u_long icplb_table[MAX_CPLBS + 1]; u_long dcplb_table[MAX_CPLBS + 1]; @@ -295,6 +324,8 @@ void __init generate_cpl_tables(void) struct cplb_tab *t_d = NULL; struct s_cplb cplb; + printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n"); + cplb.init_i.size = MAX_CPLBS; cplb.init_d.size = MAX_CPLBS; cplb.switch_i.size = MAX_SWITCH_I_CPLBS; |