diff options
Diffstat (limited to 'arch/blackfin/mach-bf537')
| -rw-r--r-- | arch/blackfin/mach-bf537/Kconfig | 4 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/boards/cm_bf537e.c | 10 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/boards/cm_bf537u.c | 10 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/boards/pnav10.c | 12 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/boards/stamp.c | 598 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/boards/tcm_bf537.c | 10 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/cdefBF534.h | 44 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 124 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/pll.h | 57 |
9 files changed, 595 insertions, 274 deletions
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig index d81224f9d72..08b2b343cce 100644 --- a/arch/blackfin/mach-bf537/Kconfig +++ b/arch/blackfin/mach-bf537/Kconfig @@ -14,8 +14,8 @@ config IRQ_DMA_ERROR int "IRQ_DMA_ERROR Generic" default 7 config IRQ_ERROR - int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1" - default 7 + int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1" + default 11 config IRQ_RTC int "IRQ_RTC" default 8 diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index d35fc5fe4c2..e2e7be40ef4 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -73,7 +73,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -112,12 +112,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -229,7 +229,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index d464ad5b72b..752c833f7ca 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 812e8f99160..6b03808800a 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -175,8 +175,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -238,13 +238,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index b342e1d144a..cd2c797c8c9 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -35,12 +35,10 @@ #include <asm/reboot.h> #include <asm/portmux.h> #include <asm/dpmc.h> -#ifdef CONFIG_REGULATOR_ADP_SWITCH -#include <linux/regulator/adp_switch.h> -#endif -#ifdef CONFIG_REGULATOR_AD5398 -#include <linux/regulator/ad5398.h> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE +#include <linux/regulator/fixed.h> #endif +#include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> #include <linux/regulator/userspace-consumer.h> @@ -264,7 +262,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF3, .end = IRQ_PF3, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -400,6 +398,7 @@ static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) static struct platform_nand_data bfin_plat_nand_data = { .chip = { + .nr_chips = 1, .chip_delay = 30, #ifdef CONFIG_MTD_PARTITIONS .part_probe_types = part_probes, @@ -417,7 +416,7 @@ static struct platform_nand_data bfin_plat_nand_data = { static struct resource bfin_plat_nand_resources = { .start = 0x20212000, .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, + .flags = IORESOURCE_MEM, }; static struct platform_device bfin_async_nand_device = { @@ -544,6 +543,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = { }; #endif +#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \ + || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) +static struct bfin5xx_spi_chip adav801_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) #include <linux/input/ad714x.h> static struct bfin5xx_spi_chip ad7147_spi_chip_info = { @@ -692,6 +699,65 @@ static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = { }; #endif +#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE) +static struct bfin5xx_spi_chip ad7314_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE) +static unsigned short ad7816_platform_data[] = { + GPIO_PF4, /* rdwr_pin */ + GPIO_PF5, /* convert_pin */ + GPIO_PF7, /* busy_pin */ + 0, +}; + +static struct bfin5xx_spi_chip ad7816_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE) +static unsigned long adt7310_platform_data[3] = { +/* INT bound temperature alarm event. line 1 */ + IRQ_PG4, IRQF_TRIGGER_LOW, +/* CT bound temperature alarm event irq_flags. line 0 */ + IRQF_TRIGGER_LOW, +}; + +static struct bfin5xx_spi_chip adt7310_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE) +static unsigned short ad7298_platform_data[] = { + GPIO_PF7, /* busy_pin */ + 0, +}; + +static struct bfin5xx_spi_chip ad7298_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE) +static unsigned long adt7316_spi_data[2] = { + IRQF_TRIGGER_LOW, /* interrupt flags */ + GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ +}; + +static struct bfin5xx_spi_chip adt7316_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 @@ -823,14 +889,12 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { .enable_dma = 1, .bits_per_word = 8, - .cs_gpio = GPIO_PF10, }; #endif #if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) static struct bfin5xx_spi_chip adf7021_spi_chip_info = { .bits_per_word = 16, - .cs_gpio = GPIO_PF10, }; #include <linux/spi/adf702x.h> @@ -937,6 +1001,13 @@ static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { }; #endif +#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE) +static struct bfin5xx_spi_chip spi_ad7476_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -981,7 +1052,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = 4,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ + .chip_select = 4, .platform_data = "ad1836", /* only includes chip name for the moment */ .controller_data = &ad1836_spi_chip_info, .mode = SPI_MODE_3, @@ -999,6 +1070,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif +#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) + { + .modalias = "adav80x", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, + .controller_data = &adav801_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) { .modalias = "ad714x_captouch", @@ -1017,6 +1099,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .modalias = "ad2s90", .bus_num = 0, .chip_select = 3, /* change it for your board */ + .mode = SPI_MODE_3, .platform_data = NULL, .controller_data = &ad2s90_spi_chip_info, }, @@ -1043,6 +1126,67 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif +#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE) + { + .modalias = "ad7314", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .controller_data = &ad7314_spi_chip_info, + .mode = SPI_MODE_1, + }, +#endif + +#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE) + { + .modalias = "ad7818", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad7816_platform_data, + .controller_data = &ad7816_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE) + { + .modalias = "adt7310", + .max_speed_hz = 1000000, + .irq = IRQ_PG5, /* CT alarm event. Line 0 */ + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = adt7310_platform_data, + .controller_data = &adt7310_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE) + { + .modalias = "ad7298", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad7298_platform_data, + .controller_data = &ad7298_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE) + { + .modalias = "adt7316", + .max_speed_hz = 1000000, + .irq = IRQ_PG5, /* interrupt line */ + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = adt7316_spi_data, + .controller_data = &adt7316_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) { .modalias = "mmc_spi", @@ -1102,7 +1246,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .irq = IRQ_PF6, .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ .controller_data = &enc28j60_spi_chip_info, .mode = SPI_MODE_0, }, @@ -1124,7 +1268,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .modalias = "adf702x", .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ .controller_data = &adf7021_spi_chip_info, .platform_data = &adf7021_platform_data, .mode = SPI_MODE_0, @@ -1142,12 +1286,239 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_0, }, #endif +#if defined(CONFIG_AD7476) \ + || defined(CONFIG_AD7476_MODULE) + { + .modalias = "ad7476", /* Name of spi_driver for this device */ + .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. */ + .platform_data = NULL, /* No spi_driver specific config */ + .controller_data = &spi_ad7476_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADE7753) \ + || defined(CONFIG_ADE7753_MODULE) + { + .modalias = "ade7753", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7754) \ + || defined(CONFIG_ADE7754_MODULE) + { + .modalias = "ade7754", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7758) \ + || defined(CONFIG_ADE7758_MODULE) + { + .modalias = "ade7758", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7759) \ + || defined(CONFIG_ADE7759_MODULE) + { + .modalias = "ade7759", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7854_SPI) \ + || defined(CONFIG_ADE7854_SPI_MODULE) + { + .modalias = "ade7854", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADIS16060) \ + || defined(CONFIG_ADIS16060_MODULE) + { + .modalias = "adis16060_r", + .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_0, + }, + { + .modalias = "adis16060_w", + .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 2, /* CS for write, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADIS16130) \ + || defined(CONFIG_ADIS16130_MODULE) + { + .modalias = "adis16130", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS for read, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADIS16201) \ + || defined(CONFIG_ADIS16201_MODULE) + { + .modalias = "adis16201", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16203) \ + || defined(CONFIG_ADIS16203_MODULE) + { + .modalias = "adis16203", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16204) \ + || defined(CONFIG_ADIS16204_MODULE) + { + .modalias = "adis16204", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16209) \ + || defined(CONFIG_ADIS16209_MODULE) + { + .modalias = "adis16209", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16220) \ + || defined(CONFIG_ADIS16220_MODULE) + { + .modalias = "adis16220", + .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16240) \ + || defined(CONFIG_ADIS16240_MODULE) + { + .modalias = "adis16240", + .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16260) \ + || defined(CONFIG_ADIS16260_MODULE) + { + .modalias = "adis16260", + .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16261) \ + || defined(CONFIG_ADIS16261_MODULE) + { + .modalias = "adis16261", + .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADIS16300) \ + || defined(CONFIG_ADIS16300_MODULE) + { + .modalias = "adis16300", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16350) \ + || defined(CONFIG_ADIS16350_MODULE) + { + .modalias = "adis16364", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16400) \ + || defined(CONFIG_ADIS16400_MODULE) + { + .modalias = "adis16400", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif }; #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* SPI controller data */ static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, + .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; @@ -1772,12 +2143,6 @@ static struct regulator_init_data ad5398_regulator_data = { .consumer_supplies = &ad5398_consumer, }; -static struct ad5398_platform_data ad5398_i2c_platform_data = { - .current_bits = 10, - .current_offset = 4, - .regulator_data = &ad5398_regulator_data, -}; - #if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \ defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE) static struct platform_device ad5398_virt_consumer_device = { @@ -1810,7 +2175,34 @@ static struct platform_device ad5398_userspace_consumer_device = { #endif #endif +#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE) +/* INT bound temperature alarm event. line 1 */ +static unsigned long adt7410_platform_data[2] = { + IRQ_PG4, IRQF_TRIGGER_LOW, +}; +#endif + +#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE) +/* INT bound temperature alarm event. line 1 */ +static unsigned long adt7316_i2c_data[2] = { + IRQF_TRIGGER_LOW, /* interrupt flags */ + GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ +}; +#endif + static struct i2c_board_info __initdata bfin_i2c_board_info[] = { +#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE) + { + I2C_BOARD_INFO("ad1937", 0x04), + }, +#endif + +#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) + { + I2C_BOARD_INFO("adav803", 0x10), + }, +#endif + #if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) { I2C_BOARD_INFO("ad7142_captouch", 0x2C), @@ -1842,12 +2234,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { { I2C_BOARD_INFO("ad7414", 0x9), .irq = IRQ_PG5, - /* - * platform_data pointer is borrwoed by the driver to - * store custimer defined IRQ ALART level mode. - * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid. - */ - .platform_data = (void *)IRQF_TRIGGER_LOW, + .irq_flags = IRQF_TRIGGER_LOW, }, #endif @@ -1855,12 +2242,56 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { { I2C_BOARD_INFO("ad7417", 0xb), .irq = IRQ_PG5, - /* - * platform_data pointer is borrwoed by the driver to - * store custimer defined IRQ ALART level mode. - * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid. - */ - .platform_data = (void *)IRQF_TRIGGER_LOW, + .irq_flags = IRQF_TRIGGER_LOW, + .platform_data = (void *)GPIO_PF4, + }, +#endif + +#if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE) + { + I2C_BOARD_INFO("ade7854", 0x38), + }, +#endif + +#if defined(CONFIG_ADT75) || defined(CONFIG_ADT75_MODULE) + { + I2C_BOARD_INFO("adt75", 0x9), + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + }, +#endif + +#if defined(CONFIG_ADT7408) || defined(CONFIG_ADT7408_MODULE) + { + I2C_BOARD_INFO("adt7408", 0x18), + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + }, +#endif + +#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE) + { + I2C_BOARD_INFO("adt7410", 0x48), + /* CT critical temperature event. line 0 */ + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + .platform_data = (void *)&adt7410_platform_data, + }, +#endif + +#if defined(CONFIG_AD7291) || defined(CONFIG_AD7291_MODULE) + { + I2C_BOARD_INFO("ad7291", 0x20), + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + }, +#endif + +#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE) + { + I2C_BOARD_INFO("adt7316", 0x48), + .irq = IRQ_PG6, + .platform_data = (void *)&adt7316_i2c_data, }, #endif @@ -1916,7 +2347,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { #endif #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) { - I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C), + I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F), }, #endif #if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) @@ -1953,7 +2384,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { #if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE) { I2C_BOARD_INFO("ad5398", 0xC), - .platform_data = (void *)&ad5398_i2c_platform_data, + .platform_data = (void *)&ad5398_regulator_data, }, #endif #if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE) @@ -1962,6 +2393,16 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { .platform_data = (void *)&adp8860_pdata, }, #endif +#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE) + { + I2C_BOARD_INFO("adau1373", 0x1A), + }, +#endif +#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("ad5252", 0x2e), + }, +#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) @@ -2146,50 +2587,38 @@ static struct platform_device bfin_ac97 = { }; #endif -#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) -#define REGULATOR_ADP122 "adp122" -#define REGULATOR_ADP150 "adp150" +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) +#define REGULATOR_ADP122 "adp122" +#define REGULATOR_ADP122_UV 2500000 static struct regulator_consumer_supply adp122_consumers = { .supply = REGULATOR_ADP122, }; -static struct regulator_consumer_supply adp150_consumers = { - .supply = REGULATOR_ADP150, -}; - -static struct regulator_init_data adp_switch_regulator_data[] = { - { - .constraints = { - .name = REGULATOR_ADP122, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .min_uA = 0, - .max_uA = 300000, - }, - .num_consumer_supplies = 1, /* only 1 */ - .consumer_supplies = &adp122_consumers, - .driver_data = (void *)GPIO_PF2, /* gpio port only */ - }, - { - .constraints = { - .name = REGULATOR_ADP150, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .min_uA = 0, - .max_uA = 150000, - }, - .num_consumer_supplies = 1, /* only 1 */ - .consumer_supplies = &adp150_consumers, - .driver_data = (void *)GPIO_PF3, /* gpio port only */ +static struct regulator_init_data adp_switch_regulator_data = { + .constraints = { + .name = REGULATOR_ADP122, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .min_uV = REGULATOR_ADP122_UV, + .max_uV = REGULATOR_ADP122_UV, + .min_uA = 0, + .max_uA = 300000, }, + .num_consumer_supplies = 1, /* only 1 */ + .consumer_supplies = &adp122_consumers, }; -static struct adp_switch_platform_data adp_switch_pdata = { - .regulator_num = ARRAY_SIZE(adp_switch_regulator_data), - .regulator_data = adp_switch_regulator_data, +static struct fixed_voltage_config adp_switch_pdata = { + .supply_name = REGULATOR_ADP122, + .microvolts = REGULATOR_ADP122_UV, + .gpio = GPIO_PF2, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &adp_switch_regulator_data, }; static struct platform_device adp_switch_device = { - .name = "adp_switch", + .name = "reg-fixed-voltage", .id = 0, .dev = { .platform_data = &adp_switch_pdata, @@ -2215,27 +2644,26 @@ static struct platform_device adp122_userspace_consumer_device = { .platform_data = &adp122_userspace_comsumer_data, }, }; +#endif +#endif -static struct regulator_bulk_data adp150_bulk_data = { - .supply = REGULATOR_ADP150, -}; +#if defined(CONFIG_IIO_GPIO_TRIGGER) || \ + defined(CONFIG_IIO_GPIO_TRIGGER_MODULE) -static struct regulator_userspace_consumer_data adp150_userspace_comsumer_data = { - .name = REGULATOR_ADP150, - .num_supplies = 1, - .supplies = &adp150_bulk_data, +static struct resource iio_gpio_trigger_resources[] = { + [0] = { + .start = IRQ_PF5, + .end = IRQ_PF5, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, + }, }; -static struct platform_device adp150_userspace_consumer_device = { - .name = "reg-userspace-consumer", - .id = 1, - .dev = { - .platform_data = &adp150_userspace_comsumer_data, - }, +static struct platform_device iio_gpio_trigger = { + .name = "iio_gpio_trigger", + .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources), + .resource = iio_gpio_trigger_resources, }; #endif -#endif - static struct platform_device *stamp_devices[] __initdata = { @@ -2368,14 +2796,18 @@ static struct platform_device *stamp_devices[] __initdata = { #endif #endif -#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) &adp_switch_device, #if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \ defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE) &adp122_userspace_consumer_device, - &adp150_userspace_consumer_device, #endif #endif + +#if defined(CONFIG_IIO_GPIO_TRIGGER) || \ + defined(CONFIG_IIO_GPIO_TRIGGER_MODULE) + &iio_gpio_trigger, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 4f0a2e72ce4..a4d62b5fc7b 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h index 91825c9bd22..fbeb35e1413 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h @@ -1750,48 +1750,4 @@ /* These need to be last due to the cdef/linux inter-dependencies */ #include <asm/irq.h> -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SIC_IWR); - /* Only allow PPL Wakeup) */ - bfin_write32(SIC_IWR, IWR_ENABLE(0)); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SIC_IWR, iwr); - local_irq_restore_hw(flags); -} - #endif /* _CDEF_BF534_H */ diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index aad61b88737..0323e6bacda 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1071,50 +1071,6 @@ #define FPE 0x10 /* Force Parity Error On Transmit */ #define FFE 0x20 /* Force Framing Error On Transmit */ -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ -#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ -#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ -#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ -#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ -#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ -#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ -#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - /* **************** GENERAL PURPOSE TIMER MASKS **********************/ /* TIMER_ENABLE Masks */ #define TIMEN0 0x0001 /* Enable Timer 0 */ @@ -1241,86 +1197,6 @@ #define PH14 0x4000 #define PH15 0x8000 -/* ******************* SERIAL PORT MASKS **************************************/ -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 /* Transmit Enable */ -#define ITCLK 0x0002 /* Internal Transmit Clock Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* Transmit Bit Order */ -#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ -#define TFSR 0x0400 /* Transmit Frame Sync Required Select */ -#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ -#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define LATFS 0x2000 /* Late Transmit Frame Sync Select */ -#define TCKFE 0x4000 /* Clock Falling Edge Select */ - -/* SPORTx_TCR2 Masks and Macro */ -#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 /* Receive Enable */ -#define IRCLK 0x0002 /* Internal Receive Clock Select */ -#define DTYPE_NORM 0x0004 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define RLSBIT 0x0010 /* Receive Bit Order */ -#define IRFS 0x0200 /* Internal Receive Frame Sync Select */ -#define RFSR 0x0400 /* Receive Frame Sync Required Select */ -#define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define LARFS 0x2000 /* Late Receive Frame Sync Select */ -#define RCKFE 0x4000 /* Clock Falling Edge Select */ - -/* SPORTx_RCR2 Masks */ -#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 /* Receive FIFO Not Empty Status */ -#define RUVF 0x0002 /* Sticky Receive Underflow Status */ -#define ROVF 0x0004 /* Sticky Receive Overflow Status */ -#define TXF 0x0008 /* Transmit FIFO Full Status */ -#define TUVF 0x0010 /* Sticky Transmit Underflow Status */ -#define TOVF 0x0020 /* Sticky Transmit Overflow Status */ -#define TXHRE 0x0040 /* Transmit Hold Register Empty */ - -/* SPORTx_MCMC1 Macros */ -#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ - -/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ -#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ - -/* SPORTx_MCMC2 Masks */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ -#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ -#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ -#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ -#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ -#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ -#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ -#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ -#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ -#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ -#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ -#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ -#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ -#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ -#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ -#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ /* EBIU_AMGCTL Masks */ #define AMCKEN 0x0001 /* Enable CLKOUT */ diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h new file mode 100644 index 00000000000..169c106d0ed --- /dev/null +++ b/arch/blackfin/mach-bf537/include/mach/pll.h @@ -0,0 +1,57 @@ +/* + * Copyright 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PLL_H +#define _MACH_PLL_H + +#include <asm/blackfin.h> +#include <asm/irqflags.h> + +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_PLL_CTL()) + return; + + flags = hard_local_irq_save(); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + hard_local_irq_restore(flags); +} + +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_VR_CTL()) + return; + + flags = hard_local_irq_save(); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + hard_local_irq_restore(flags); +} + +#endif /* _MACH_PLL_H */ |