diff options
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/anomaly.h | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 52b116ae522..7d08c752449 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf548/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -24,6 +28,8 @@ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) +/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ +#define ANOMALY_05000220 (1) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ @@ -200,6 +206,14 @@ #define ANOMALY_05000466 (1) /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ #define ANOMALY_05000467 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ +#define ANOMALY_05000474 (1) +/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -215,7 +229,6 @@ #define ANOMALY_05000198 (0) #define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) -#define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) |