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-rw-r--r--arch/blackfin/mach-bf561/head.S34
1 files changed, 8 insertions, 26 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 96a3d456fb6..5b8bd40851d 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -37,9 +37,6 @@
#include <asm/mach/mem_init.h>
#endif
-.global __rambase
-.global __ramstart
-.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem
@@ -139,26 +136,26 @@ ENTRY(__start)
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
- p0.h = hi(UART_LCR);
- p0.l = lo(UART_LCR);
+ p0.h = hi(BFIN_UART_LCR);
+ p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
- p0.h = hi(UART_DLL);
- p0.l = lo(UART_DLL);
+ p0.h = hi(BFIN_UART_DLL);
+ p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_DLH);
- p0.l = lo(UART_DLH);
+ p0.h = hi(BFIN_UART_DLH);
+ p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_GCTL);
- p0.l = lo(UART_GCTL);
+ p0.h = hi(BFIN_UART_GCTL);
+ p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
@@ -411,18 +408,3 @@ ENTRY(_start_dma_code)
RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-.data
-
-/*
- * Set up the usable of RAM stuff. Size of RAM is determined then
- * an initial stack set up at the end.
- */
-
-.align 4
-__rambase:
-.long 0
-__ramstart:
-.long 0
-__ramend:
-.long 0