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-rw-r--r--arch/blackfin/mach-bf609/Kconfig1697
-rw-r--r--arch/blackfin/mach-bf609/Makefile1
-rw-r--r--arch/blackfin/mach-bf609/boards/ezkit.c563
-rw-r--r--arch/blackfin/mach-bf609/clock.c17
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF60x_base.h10
-rw-r--r--arch/blackfin/mach-bf609/include/mach/gpio.h8
-rw-r--r--arch/blackfin/mach-bf609/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf609/include/mach/portmux.h6
-rw-r--r--arch/blackfin/mach-bf609/scb.c363
9 files changed, 2575 insertions, 92 deletions
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index 95a4f1b676c..b0fca44110b 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -9,48 +9,6 @@ source "arch/blackfin/mach-bf609/boards/Kconfig"
menu "BF609 Specific Configuration"
-comment "Pin Interrupt to Port Assignment"
-menu "Assignment"
-
-config PINTx_REASSIGN
- bool "Reprogram PINT Assignment"
- default y
- help
- The interrupt assignment registers controls the pin-to-interrupt
- assignment in a byte-wide manner. Each option allows you to select
- a set of pins (High/Low Byte) of an specific Port being mapped
- to one of the four PIN Interrupts IRQ_PINTx.
-
- You shouldn't change any of these unless you know exactly what you're doing.
- Please consult the Blackfin BF60x Processor Hardware Reference Manual.
-
-config PINT0_ASSIGN
- hex "PINT0_ASSIGN"
- depends on PINTx_REASSIGN
- default 0x00000101
-config PINT1_ASSIGN
- hex "PINT1_ASSIGN"
- depends on PINTx_REASSIGN
- default 0x00000101
-config PINT2_ASSIGN
- hex "PINT2_ASSIGN"
- depends on PINTx_REASSIGN
- default 0x00000101
-config PINT3_ASSIGN
- hex "PINT3_ASSIGN"
- depends on PINTx_REASSIGN
- default 0x00000101
-config PINT4_ASSIGN
- hex "PINT3_ASSIGN"
- depends on PINTx_REASSIGN
- default 0x00000101
-config PINT5_ASSIGN
- hex "PINT3_ASSIGN"
- depends on PINTx_REASSIGN
- default 0x00000101
-
-endmenu
-
config SEC_IRQ_PRIORITY_LEVELS
int "SEC interrupt priority levels"
default 7
@@ -59,6 +17,1661 @@ config SEC_IRQ_PRIORITY_LEVELS
Divide the total number of interrupt priority levels into sub-levels.
There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
+
+comment "System Cross Bar Priority Assignment"
+
+config SCB_PRIORITY
+ bool "Init System Cross Bar Priority"
+ default n
+
+menuconfig SCB0_MI0
+ bool "SCB0 Master Interface 0 (DDR)"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ Core 0 -- 0
+ Core 1 -- 2
+ SCB1 -- 9
+ SCB2 -- 10
+ SCB3 -- 11
+ SCB4 -- 12
+ SCB5 -- 5
+ SCB6 -- 6
+ SCB7 -- 8
+ SCB8 -- 7
+ SCB9 -- 4
+ USB -- 13
+
+if SCB0_MI0
+
+config SCB0_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 13
+
+config SCB0_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 2
+ range 0 13
+
+config SCB0_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI0_SLOT8
+ int "Slot 8 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI0_SLOT9
+ int "Slot 9 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI0_SLOT10
+ int "Slot 10 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI0_SLOT11
+ int "Slot 11 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI0_SLOT12
+ int "Slot 12 slave interface id"
+ default 0
+ range 0 13
+
+config SCB0_MI0_SLOT13
+ int "Slot 13 slave interface id"
+ default 2
+ range 0 13
+
+config SCB0_MI0_SLOT14
+ int "Slot 14 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI0_SLOT15
+ int "Slot 15 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI0_SLOT16
+ int "Slot 16 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI0_SLOT17
+ int "Slot 17 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI0_SLOT18
+ int "Slot 18 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI0_SLOT19
+ int "Slot 19 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI0_SLOT20
+ int "Slot 20 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI0_SLOT21
+ int "Slot 21 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI0_SLOT22
+ int "Slot 22 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI0_SLOT23
+ int "Slot 23 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI0_SLOT24
+ int "Slot 24 slave interface id"
+ default 0
+ range 0 13
+
+config SCB0_MI0_SLOT25
+ int "Slot 25 slave interface id"
+ default 2
+ range 0 13
+
+config SCB0_MI0_SLOT26
+ int "Slot 26 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI0_SLOT27
+ int "Slot 27 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI0_SLOT28
+ int "Slot 28 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI0_SLOT29
+ int "Slot 29 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI0_SLOT30
+ int "Slot 30 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI0_SLOT31
+ int "Slot 31 slave interface id"
+ default 13
+ range 0 13
+
+endif # SCB0_MI0
+
+menuconfig SCB0_MI1
+ bool "SCB0 Master Interface 1 (SMC)"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ Core 0 -- 0
+ Core 1 -- 2
+ SCB1 -- 9
+ SCB2 -- 10
+ SCB3 -- 11
+ SCB4 -- 12
+ SCB5 -- 5
+ SCB6 -- 6
+ SCB7 -- 8
+ SCB8 -- 7
+ SCB9 -- 4
+ USB -- 13
+
+if SCB0_MI1
+
+config SCB0_MI1_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 13
+
+config SCB0_MI1_SLOT1
+ int "Slot 1 slave interface id"
+ default 2
+ range 0 13
+
+config SCB0_MI1_SLOT2
+ int "Slot 2 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI1_SLOT3
+ int "Slot 3 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI1_SLOT4
+ int "Slot 4 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI1_SLOT5
+ int "Slot 5 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI1_SLOT6
+ int "Slot 6 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI1_SLOT7
+ int "Slot 7 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI1_SLOT8
+ int "Slot 8 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI1_SLOT9
+ int "Slot 9 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI1_SLOT10
+ int "Slot 10 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI1_SLOT11
+ int "Slot 11 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI1_SLOT12
+ int "Slot 12 slave interface id"
+ default 0
+ range 0 13
+
+config SCB0_MI1_SLOT13
+ int "Slot 13 slave interface id"
+ default 2
+ range 0 13
+
+config SCB0_MI1_SLOT14
+ int "Slot 14 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI1_SLOT15
+ int "Slot 15 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI1_SLOT16
+ int "Slot 16 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI1_SLOT17
+ int "Slot 17 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI1_SLOT18
+ int "Slot 18 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI1_SLOT19
+ int "Slot 19 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI1_SLOT20
+ int "Slot 20 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI1_SLOT21
+ int "Slot 21 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI1_SLOT22
+ int "Slot 22 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI1_SLOT23
+ int "Slot 23 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI1_SLOT24
+ int "Slot 24 slave interface id"
+ default 0
+ range 0 13
+
+config SCB0_MI1_SLOT25
+ int "Slot 25 slave interface id"
+ default 2
+ range 0 13
+
+config SCB0_MI1_SLOT26
+ int "Slot 26 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI1_SLOT27
+ int "Slot 27 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI1_SLOT28
+ int "Slot 28 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI1_SLOT29
+ int "Slot 29 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI1_SLOT30
+ int "Slot 30 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI1_SLOT31
+ int "Slot 31 slave interface id"
+ default 13
+ range 0 13
+
+endif # SCB0_MI1
+
+menuconfig SCB0_MI2
+ bool "SCB0 Master Interface 2 (Data L2)"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ Core 0 -- 0
+ Core 1 -- 2
+ SCB1 -- 9
+ SCB2 -- 10
+ SCB3 -- 11
+ SCB4 -- 12
+ SCB5 -- 5
+ SCB6 -- 6
+ SCB7 -- 8
+ SCB8 -- 7
+ SCB9 -- 4
+ USB -- 13
+
+if SCB0_MI2
+
+config SCB0_MI2_SLOT0
+ int "Slot 0 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI2_SLOT1
+ int "Slot 1 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI2_SLOT2
+ int "Slot 2 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI2_SLOT3
+ int "Slot 3 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI2_SLOT4
+ int "Slot 4 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI2_SLOT5
+ int "Slot 5 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI2_SLOT6
+ int "Slot 6 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI2_SLOT7
+ int "Slot 7 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI2_SLOT8
+ int "Slot 8 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI2_SLOT9
+ int "Slot 9 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI2_SLOT10
+ int "Slot 10 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI2_SLOT11
+ int "Slot 11 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI2_SLOT12
+ int "Slot 12 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI2_SLOT13
+ int "Slot 13 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI2_SLOT14
+ int "Slot 14 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI2_SLOT15
+ int "Slot 15 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI2_SLOT16
+ int "Slot 16 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI2_SLOT17
+ int "Slot 17 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI2_SLOT18
+ int "Slot 18 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI2_SLOT19
+ int "Slot 19 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI2_SLOT20
+ int "Slot 20 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI2_SLOT21
+ int "Slot 21 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI2_SLOT22
+ int "Slot 22 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI2_SLOT23
+ int "Slot 23 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI2_SLOT24
+ int "Slot 24 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI2_SLOT25
+ int "Slot 25 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI2_SLOT26
+ int "Slot 26 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI2_SLOT27
+ int "Slot 27 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI2_SLOT28
+ int "Slot 28 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI2_SLOT29
+ int "Slot 29 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI2_SLOT30
+ int "Slot 30 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI2_SLOT31
+ int "Slot 31 slave interface id"
+ default 7
+ range 0 13
+
+endif # SCB0_MI2
+
+menuconfig SCB0_MI3
+ bool "SCB0 Master Interface 3 (L1A)"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ Core 0 -- 0
+ Core 1 -- 2
+ SCB1 -- 9
+ SCB2 -- 10
+ SCB3 -- 11
+ SCB4 -- 12
+ SCB5 -- 5
+ SCB6 -- 6
+ SCB7 -- 8
+ SCB8 -- 7
+ SCB9 -- 4
+ USB -- 13
+
+if SCB0_MI3
+
+config SCB0_MI3_SLOT0
+ int "Slot 0 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI3_SLOT1
+ int "Slot 1 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI3_SLOT2
+ int "Slot 2 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI3_SLOT3
+ int "Slot 3 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI3_SLOT4
+ int "Slot 4 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI3_SLOT5
+ int "Slot 5 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI3_SLOT6
+ int "Slot 6 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI3_SLOT7
+ int "Slot 7 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI3_SLOT8
+ int "Slot 8 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI3_SLOT9
+ int "Slot 9 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI3_SLOT10
+ int "Slot 10 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI3_SLOT11
+ int "Slot 11 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI3_SLOT12
+ int "Slot 12 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI3_SLOT13
+ int "Slot 13 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI3_SLOT14
+ int "Slot 14 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI3_SLOT15
+ int "Slot 15 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI3_SLOT16
+ int "Slot 16 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI3_SLOT17
+ int "Slot 17 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI3_SLOT18
+ int "Slot 18 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI3_SLOT19
+ int "Slot 19 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI3_SLOT20
+ int "Slot 20 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI3_SLOT21
+ int "Slot 21 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI3_SLOT22
+ int "Slot 22 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI3_SLOT23
+ int "Slot 23 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI3_SLOT24
+ int "Slot 24 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI3_SLOT25
+ int "Slot 25 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI3_SLOT26
+ int "Slot 26 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI3_SLOT27
+ int "Slot 27 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI3_SLOT28
+ int "Slot 28 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI3_SLOT29
+ int "Slot 29 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI3_SLOT30
+ int "Slot 30 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI3_SLOT31
+ int "Slot 31 slave interface id"
+ default 7
+ range 0 13
+
+endif # SCB0_MI3
+
+menuconfig SCB0_MI4
+ bool "SCB0 Master Interface 4 (L1B)"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ Core 0 -- 0
+ Core 1 -- 2
+ SCB1 -- 9
+ SCB2 -- 10
+ SCB3 -- 11
+ SCB4 -- 12
+ SCB5 -- 5
+ SCB6 -- 6
+ SCB7 -- 8
+ SCB8 -- 7
+ SCB9 -- 4
+ USB -- 13
+
+if SCB0_MI4
+
+config SCB0_MI4_SLOT0
+ int "Slot 0 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI4_SLOT1
+ int "Slot 1 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI4_SLOT2
+ int "Slot 2 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI4_SLOT3
+ int "Slot 3 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI4_SLOT4
+ int "Slot 4 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI4_SLOT5
+ int "Slot 5 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI4_SLOT6
+ int "Slot 6 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI4_SLOT7
+ int "Slot 7 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI4_SLOT8
+ int "Slot 8 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI4_SLOT9
+ int "Slot 9 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI4_SLOT10
+ int "Slot 10 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI4_SLOT11
+ int "Slot 11 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI4_SLOT12
+ int "Slot 12 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI4_SLOT13
+ int "Slot 13 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI4_SLOT14
+ int "Slot 14 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI4_SLOT15
+ int "Slot 15 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI4_SLOT16
+ int "Slot 16 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI4_SLOT17
+ int "Slot 17 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI4_SLOT18
+ int "Slot 18 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI4_SLOT19
+ int "Slot 19 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI4_SLOT20
+ int "Slot 20 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI4_SLOT21
+ int "Slot 21 slave interface id"
+ default 5
+ range 0 13
+
+config SCB0_MI4_SLOT22
+ int "Slot 22 slave interface id"
+ default 6
+ range 0 13
+
+config SCB0_MI4_SLOT23
+ int "Slot 23 slave interface id"
+ default 7
+ range 0 13
+
+config SCB0_MI4_SLOT24
+ int "Slot 24 slave interface id"
+ default 8
+ range 0 13
+
+config SCB0_MI4_SLOT25
+ int "Slot 25 slave interface id"
+ default 9
+ range 0 13
+
+config SCB0_MI4_SLOT26
+ int "Slot 26 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI4_SLOT27
+ int "Slot 27 slave interface id"
+ default 11
+ range 0 13
+
+config SCB0_MI4_SLOT28
+ int "Slot 28 slave interface id"
+ default 13
+ range 0 13
+
+config SCB0_MI4_SLOT29
+ int "Slot 29 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI4_SLOT30
+ int "Slot 30 slave interface id"
+ default 4
+ range 0 13
+
+config SCB0_MI4_SLOT31
+ int "Slot 31 slave interface id"
+ default 7
+ range 0 13
+
+endif # SCB0_MI4
+
+menuconfig SCB0_MI5
+ bool "SCB0 Master Interface 5 (SMMR)"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ MMR0 -- 1
+ MMR1 -- 3
+ SCB2 -- 10
+ SCB4 -- 12
+
+if SCB0_MI5
+
+config SCB0_MI5_SLOT0
+ int "Slot 0 slave interface id"
+ default 1
+ range 0 13
+
+config SCB0_MI5_SLOT1
+ int "Slot 1 slave interface id"
+ default 3
+ range 0 13
+
+config SCB0_MI5_SLOT2
+ int "Slot 2 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI5_SLOT3
+ int "Slot 3 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI5_SLOT4
+ int "Slot 4 slave interface id"
+ default 1
+ range 0 13
+
+config SCB0_MI5_SLOT5
+ int "Slot 5 slave interface id"
+ default 3
+ range 0 13
+
+config SCB0_MI5_SLOT6
+ int "Slot 6 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI5_SLOT7
+ int "Slot 7 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI5_SLOT8
+ int "Slot 8 slave interface id"
+ default 1
+ range 0 13
+
+config SCB0_MI5_SLOT9
+ int "Slot 9 slave interface id"
+ default 3
+ range 0 13
+
+config SCB0_MI5_SLOT10
+ int "Slot 10 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI5_SLOT11
+ int "Slot 11 slave interface id"
+ default 12
+ range 0 13
+
+config SCB0_MI5_SLOT12
+ int "Slot 12 slave interface id"
+ default 1
+ range 0 13
+
+config SCB0_MI5_SLOT13
+ int "Slot 13 slave interface id"
+ default 3
+ range 0 13
+
+config SCB0_MI5_SLOT14
+ int "Slot 14 slave interface id"
+ default 10
+ range 0 13
+
+config SCB0_MI5_SLOT15
+ int "Slot 15 slave interface id"
+ default 12
+ range 0 13
+
+endif # SCB0_MI5
+
+menuconfig SCB1_MI0
+ bool "SCB1 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ SPORT0A -- 0
+ SPORT0B -- 1
+ SPORT1A -- 2
+ SPORT1B -- 3
+ SPORT2A -- 4
+ SPORT2B -- 5
+ SPI0TX -- 6
+ SPI0RX -- 7
+ SPI1TX -- 8
+ SPI1RX -- 9
+
+if SCB1_MI0
+
+config SCB1_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 9
+
+config SCB1_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 9
+
+config SCB1_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 9
+
+config SCB1_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 9
+
+config SCB1_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 4
+ range 0 9
+
+config SCB1_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 5
+ range 0 9
+
+config SCB1_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 6
+ range 0 9
+
+config SCB1_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 7
+ range 0 9
+
+config SCB1_MI0_SLOT8
+ int "Slot 8 slave interface id"
+ default 8
+ range 0 9
+
+config SCB1_MI0_SLOT9
+ int "Slot 9 slave interface id"
+ default 9
+ range 0 9
+
+config SCB1_MI0_SLOT10
+ int "Slot 10 slave interface id"
+ default 0
+ range 0 9
+
+config SCB1_MI0_SLOT11
+ int "Slot 11 slave interface id"
+ default 1
+ range 0 9
+
+config SCB1_MI0_SLOT12
+ int "Slot 12 slave interface id"
+ default 2
+ range 0 9
+
+config SCB1_MI0_SLOT13
+ int "Slot 13 slave interface id"
+ default 3
+ range 0 9
+
+config SCB1_MI0_SLOT14
+ int "Slot 14 slave interface id"
+ default 4
+ range 0 9
+
+config SCB1_MI0_SLOT15
+ int "Slot 15 slave interface id"
+ default 5
+ range 0 9
+
+config SCB1_MI0_SLOT16
+ int "Slot 16 slave interface id"
+ default 6
+ range 0 13
+
+config SCB1_MI0_SLOT17
+ int "Slot 17 slave interface id"
+ default 7
+ range 0 13
+
+config SCB1_MI0_SLOT18
+ int "Slot 18 slave interface id"
+ default 8
+ range 0 13
+
+config SCB1_MI0_SLOT19
+ int "Slot 19 slave interface id"
+ default 9
+ range 0 13
+
+endif # SCB1_MI0
+
+menuconfig SCB2_MI0
+ bool "SCB2 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ RSI -- 0
+ SDU DMA -- 1
+ SDU -- 2
+ EMAC0 -- 3
+ EMAC1 -- 4
+
+if SCB2_MI0
+
+config SCB2_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 4
+
+config SCB2_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 4
+
+config SCB2_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 4
+
+config SCB2_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 4
+
+config SCB2_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 4
+ range 0 4
+
+config SCB2_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 0
+ range 0 4
+
+config SCB2_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 1
+ range 0 4
+
+config SCB2_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 2
+ range 0 4
+
+config SCB2_MI0_SLOT8
+ int "Slot 8 slave interface id"
+ default 3
+ range 0 4
+
+config SCB2_MI0_SLOT9
+ int "Slot 9 slave interface id"
+ default 4
+ range 0 4
+
+endif # SCB2_MI0
+
+menuconfig SCB3_MI0
+ bool "SCB3 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ LP0 -- 0
+ LP1 -- 1
+ LP2 -- 2
+ LP3 -- 3
+ UART0TX -- 4
+ UART0RX -- 5
+ UART1TX -- 4
+ UART1RX -- 5
+
+if SCB3_MI0
+
+config SCB3_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 7
+
+config SCB3_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 7
+
+config SCB3_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 7
+
+config SCB3_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 7
+
+config SCB3_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 4
+ range 0 7
+
+config SCB3_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 5
+ range 0 7
+
+config SCB3_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 6
+ range 0 7
+
+config SCB3_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 7
+ range 0 7
+
+config SCB3_MI0_SLOT8
+ int "Slot 8 slave interface id"
+ default 0
+ range 0 7
+
+config SCB3_MI0_SLOT9
+ int "Slot 9 slave interface id"
+ default 1
+ range 0 7
+
+config SCB3_MI0_SLOT10
+ int "Slot 10 slave interface id"
+ default 2
+ range 0 7
+
+config SCB3_MI0_SLOT11
+ int "Slot 11 slave interface id"
+ default 3
+ range 0 7
+
+config SCB3_MI0_SLOT12
+ int "Slot 12 slave interface id"
+ default 4
+ range 0 7
+
+config SCB3_MI0_SLOT13
+ int "Slot 13 slave interface id"
+ default 5
+ range 0 7
+
+config SCB3_MI0_SLOT14
+ int "Slot 14 slave interface id"
+ default 6
+ range 0 7
+
+config SCB3_MI0_SLOT15
+ int "Slot 15 slave interface id"
+ default 7
+ range 0 7
+
+endif # SCB3_MI0
+
+menuconfig SCB4_MI0
+ bool "SCB4 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ MDA21 -- 0
+ MDA22 -- 1
+ MDA23 -- 2
+ MDA24 -- 3
+ MDA25 -- 4
+ MDA26 -- 5
+ MDA27 -- 6
+ MDA28 -- 7
+
+if SCB4_MI0
+
+config SCB4_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 7
+
+config SCB4_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 7
+
+config SCB4_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 7
+
+config SCB4_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 7
+
+config SCB4_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 4
+ range 0 7
+
+config SCB4_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 5
+ range 0 7
+
+config SCB4_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 6
+ range 0 7
+
+config SCB4_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 7
+ range 0 7
+
+config SCB4_MI0_SLOT8
+ int "Slot 8 slave interface id"
+ default 0
+ range 0 7
+
+config SCB4_MI0_SLOT9
+ int "Slot 9 slave interface id"
+ default 1
+ range 0 7
+
+config SCB4_MI0_SLOT10
+ int "Slot 10 slave interface id"
+ default 2
+ range 0 7
+
+config SCB4_MI0_SLOT11
+ int "Slot 11 slave interface id"
+ default 3
+ range 0 7
+
+config SCB4_MI0_SLOT12
+ int "Slot 12 slave interface id"
+ default 4
+ range 0 7
+
+config SCB4_MI0_SLOT13
+ int "Slot 13 slave interface id"
+ default 5
+ range 0 7
+
+config SCB4_MI0_SLOT14
+ int "Slot 14 slave interface id"
+ default 6
+ range 0 7
+
+config SCB4_MI0_SLOT15
+ int "Slot 15 slave interface id"
+ default 7
+ range 0 7
+
+endif # SCB4_MI0
+
+menuconfig SCB5_MI0
+ bool "SCB5 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ PPI0 MDA29 -- 0
+ PPI0 MDA30 -- 1
+ PPI2 MDA31 -- 2
+ PPI2 MDA32 -- 3
+
+if SCB5_MI0
+
+config SCB5_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 3
+
+config SCB5_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 3
+
+config SCB5_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 3
+
+config SCB5_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 3
+
+config SCB5_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 0
+ range 0 3
+
+config SCB5_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 1
+ range 0 3
+
+config SCB5_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 2
+ range 0 3
+
+config SCB5_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 3
+ range 0 3
+
+endif # SCB5_MI0
+
+menuconfig SCB6_MI0
+ bool "SCB6 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ PPI1 MDA33 -- 0
+ PPI1 MDA34 -- 1
+
+if SCB6_MI0
+
+config SCB6_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 1
+
+config SCB6_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 1
+
+config SCB6_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 0
+ range 0 1
+
+config SCB6_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 1
+ range 0 1
+
+endif # SCB6_MI0
+
+menuconfig SCB7_MI0
+ bool "SCB7 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ PIXC0 -- 0
+ PIXC1 -- 1
+ PIXC2 -- 2
+
+if SCB7_MI0
+
+config SCB7_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 2
+
+config SCB7_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 2
+
+config SCB7_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 2
+
+config SCB7_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 0
+ range 0 2
+
+config SCB7_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 1
+ range 0 2
+
+config SCB7_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 2
+ range 0 2
+
+endif # SCB7_MI0
+
+menuconfig SCB8_MI0
+ bool "SCB8 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ PVP CPDOB -- 0
+ PVP CPDOC -- 1
+ PVP CPCO -- 2
+ PVP CPCI -- 3
+
+if SCB8_MI0
+
+config SCB8_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 3
+
+config SCB8_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 3
+
+config SCB8_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 3
+
+config SCB8_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 3
+
+config SCB8_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 0
+ range 0 3
+
+config SCB8_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 1
+ range 0 3
+
+config SCB8_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 2
+ range 0 3
+
+config SCB8_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 3
+ range 0 3
+
+endif # SCB8_MI0
+
+menuconfig SCB9_MI0
+ bool "SCB9 Master Interface 0"
+ default n
+ depends on SCB_PRIORITY
+ help
+ The slave interface id of each slot should be set according following table.
+ PVP MPDO -- 0
+ PVP MPDI -- 1
+ PVP MPCO -- 2
+ PVP MPCI -- 3
+ PVP CPDOA -- 4
+
+if SCB9_MI0
+
+config SCB9_MI0_SLOT0
+ int "Slot 0 slave interface id"
+ default 0
+ range 0 4
+
+config SCB9_MI0_SLOT1
+ int "Slot 1 slave interface id"
+ default 1
+ range 0 4
+
+config SCB9_MI0_SLOT2
+ int "Slot 2 slave interface id"
+ default 2
+ range 0 4
+
+config SCB9_MI0_SLOT3
+ int "Slot 3 slave interface id"
+ default 3
+ range 0 4
+
+config SCB9_MI0_SLOT4
+ int "Slot 4 slave interface id"
+ default 4
+ range 0 4
+
+config SCB9_MI0_SLOT5
+ int "Slot 5 slave interface id"
+ default 0
+ range 0 4
+
+config SCB9_MI0_SLOT6
+ int "Slot 6 slave interface id"
+ default 1
+ range 0 4
+
+config SCB9_MI0_SLOT7
+ int "Slot 7 slave interface id"
+ default 2
+ range 0 4
+
+config SCB9_MI0_SLOT8
+ int "Slot 8 slave interface id"
+ default 3
+ range 0 4
+
+config SCB9_MI0_SLOT9
+ int "Slot 9 slave interface id"
+ default 4
+ range 0 4
+
+endif # SCB9_MI0
+
endmenu
endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
index 234fe1b4bb0..60ffaf85d30 100644
--- a/arch/blackfin/mach-bf609/Makefile
+++ b/arch/blackfin/mach-bf609/Makefile
@@ -4,3 +4,4 @@
obj-y := dma.o clock.o ints-priority.o
obj-$(CONFIG_PM) += pm.o dpm.o
+obj-$(CONFIG_SCB_PRIORITY) += scb.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index 0bc47231540..82beedd953f 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -17,6 +17,9 @@
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/usb/musb.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_data/pinctrl-adi2.h>
#include <asm/bfin_spi3.h>
#include <asm/dma.h>
#include <asm/gpio.h>
@@ -104,18 +107,32 @@ static struct platform_device bfin_rotary_device = {
#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
#include <linux/stmmac.h>
-
-static unsigned short pins[] = P_RMII0;
+#include <linux/phy.h>
static struct stmmac_mdio_bus_data phy_private_data = {
.phy_mask = 1,
};
+static struct stmmac_dma_cfg eth_dma_cfg = {
+ .pbl = 2,
+};
+
+int stmmac_ptp_clk_init(struct platform_device *pdev)
+{
+ bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
+ return 0;
+}
+
static struct plat_stmmacenet_data eth_private_data = {
+ .has_gmac = 1,
.bus_id = 0,
.enh_desc = 1,
.phy_addr = 1,
.mdio_bus_data = &phy_private_data,
+ .dma_cfg = &eth_dma_cfg,
+ .force_thresh_dma_mode = 1,
+ .interface = PHY_INTERFACE_MODE_RMII,
+ .init = stmmac_ptp_clk_init,
};
static struct platform_device bfin_eth_device = {
@@ -196,6 +213,18 @@ static struct resource bfin_uart0_resources[] = {
.end = UART0_RXDIV+4,
.flags = IORESOURCE_MEM,
},
+#ifdef CONFIG_EARLY_PRINTK
+ {
+ .start = PORTD_FER,
+ .end = PORTD_FER+2,
+ .flags = IORESOURCE_REG,
+ },
+ {
+ .start = PORTD_MUX,
+ .end = PORTD_MUX+3,
+ .flags = IORESOURCE_REG,
+ },
+#endif
{
.start = IRQ_UART0_TX,
.end = IRQ_UART0_TX,
@@ -260,6 +289,13 @@ static struct resource bfin_uart1_resources[] = {
.end = UART1_RXDIV+4,
.flags = IORESOURCE_MEM,
},
+#ifdef CONFIG_EARLY_PRINTK
+ {
+ .start = PORTG_FER_SET,
+ .end = PORTG_FER_SET+2,
+ .flags = IORESOURCE_REG,
+ },
+#endif
{
.start = IRQ_UART1_TX,
.end = IRQ_UART1_TX,
@@ -658,17 +694,12 @@ static struct mtd_partition ezkit_partitions[] = {
},
};
-int bf609_nor_flash_init(struct platform_device *dev)
+int bf609_nor_flash_init(struct platform_device *pdev)
{
#define CONFIG_SMC_GCTL_VAL 0x00000010
- const unsigned short pins[] = {
- P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
- P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
- };
-
- peripheral_request_list(pins, "smc0");
+ if (!devm_pinctrl_get_select_default(&pdev->dev))
+ return -EBUSY;
bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
bfin_write32(SMC_B0CTL, 0x01002011);
bfin_write32(SMC_B0TIM, 0x08170977);
@@ -676,16 +707,9 @@ int bf609_nor_flash_init(struct platform_device *dev)
return 0;
}
-void bf609_nor_flash_exit(struct platform_device *dev)
+void bf609_nor_flash_exit(struct platform_device *pdev)
{
- const unsigned short pins[] = {
- P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
- P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
- };
-
- peripheral_free_list(pins);
-
+ devm_pinctrl_put(pdev->dev.pins->p);
bfin_write32(SMC_GCTL, 0);
}
@@ -1107,6 +1131,81 @@ static struct bfin_display_config bfin_display_data = {
};
#endif
+#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
+#include <media/adv7343.h>
+
+static struct v4l2_output adv7343_outputs[] = {
+ {
+ .index = 0,
+ .name = "Composite",
+ .type = V4L2_OUTPUT_TYPE_ANALOG,
+ .std = V4L2_STD_ALL,
+ .capabilities = V4L2_OUT_CAP_STD,
+ },
+ {
+ .index = 1,
+ .name = "S-Video",
+ .type = V4L2_OUTPUT_TYPE_ANALOG,
+ .std = V4L2_STD_ALL,
+ .capabilities = V4L2_OUT_CAP_STD,
+ },
+ {
+ .index = 2,
+ .name = "Component",
+ .type = V4L2_OUTPUT_TYPE_ANALOG,
+ .std = V4L2_STD_ALL,
+ .capabilities = V4L2_OUT_CAP_STD,
+ },
+
+};
+
+static struct disp_route adv7343_routes[] = {
+ {
+ .output = ADV7343_COMPOSITE_ID,
+ },
+ {
+ .output = ADV7343_SVIDEO_ID,
+ },
+ {
+ .output = ADV7343_COMPONENT_ID,
+ },
+};
+
+static struct adv7343_platform_data adv7343_data = {
+ .mode_config = {
+ .sleep_mode = false,
+ .pll_control = false,
+ .dac_1 = true,
+ .dac_2 = true,
+ .dac_3 = true,
+ .dac_4 = true,
+ .dac_5 = true,
+ .dac_6 = true,
+ },
+ .sd_config = {
+ .sd_dac_out1 = false,
+ .sd_dac_out2 = false,
+ },
+};
+
+static struct bfin_display_config bfin_display_data = {
+ .card_name = "BF609",
+ .outputs = adv7343_outputs,
+ .num_outputs = ARRAY_SIZE(adv7343_outputs),
+ .routes = adv7343_routes,
+ .i2c_adapter_id = 0,
+ .board_info = {
+ .type = "adv7343",
+ .addr = 0x2b,
+ .platform_data = (void *)&adv7343_data,
+ },
+ .ppi_info = &ppi_info_disp,
+ .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
+ | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
+ | EPPI_CTL_NON656 | EPPI_CTL_DIR),
+};
+#endif
+
static struct platform_device bfin_display_device = {
.name = "bfin_display",
.dev = {
@@ -1228,6 +1327,356 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
+#ifdef CONFIG_PINCTRL_ADI2
+
+# define ADI_PINT_DEVNAME "adi-gpio-pint"
+# define ADI_GPIO_DEVNAME "adi-gpio"
+# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
+
+static struct platform_device bfin_pinctrl_device = {
+ .name = ADI_PINCTRL_DEVNAME,
+ .id = 0,
+};
+
+static struct resource bfin_pint0_resources[] = {
+ {
+ .start = PINT0_MASK_SET,
+ .end = PINT0_LATCH + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PINT0,
+ .end = IRQ_PINT0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pint0_device = {
+ .name = ADI_PINT_DEVNAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_pint0_resources),
+ .resource = bfin_pint0_resources,
+};
+
+static struct resource bfin_pint1_resources[] = {
+ {
+ .start = PINT1_MASK_SET,
+ .end = PINT1_LATCH + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PINT1,
+ .end = IRQ_PINT1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pint1_device = {
+ .name = ADI_PINT_DEVNAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(bfin_pint1_resources),
+ .resource = bfin_pint1_resources,
+};
+
+static struct resource bfin_pint2_resources[] = {
+ {
+ .start = PINT2_MASK_SET,
+ .end = PINT2_LATCH + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PINT2,
+ .end = IRQ_PINT2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pint2_device = {
+ .name = ADI_PINT_DEVNAME,
+ .id = 2,
+ .num_resources = ARRAY_SIZE(bfin_pint2_resources),
+ .resource = bfin_pint2_resources,
+};
+
+static struct resource bfin_pint3_resources[] = {
+ {
+ .start = PINT3_MASK_SET,
+ .end = PINT3_LATCH + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PINT3,
+ .end = IRQ_PINT3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pint3_device = {
+ .name = ADI_PINT_DEVNAME,
+ .id = 3,
+ .num_resources = ARRAY_SIZE(bfin_pint3_resources),
+ .resource = bfin_pint3_resources,
+};
+
+static struct resource bfin_pint4_resources[] = {
+ {
+ .start = PINT4_MASK_SET,
+ .end = PINT4_LATCH + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PINT4,
+ .end = IRQ_PINT4,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pint4_device = {
+ .name = ADI_PINT_DEVNAME,
+ .id = 4,
+ .num_resources = ARRAY_SIZE(bfin_pint4_resources),
+ .resource = bfin_pint4_resources,
+};
+
+static struct resource bfin_pint5_resources[] = {
+ {
+ .start = PINT5_MASK_SET,
+ .end = PINT5_LATCH + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PINT5,
+ .end = IRQ_PINT5,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pint5_device = {
+ .name = ADI_PINT_DEVNAME,
+ .id = 5,
+ .num_resources = ARRAY_SIZE(bfin_pint5_resources),
+ .resource = bfin_pint5_resources,
+};
+
+static struct resource bfin_gpa_resources[] = {
+ {
+ .start = PORTA_FER,
+ .end = PORTA_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ { /* optional */
+ .start = IRQ_PA0,
+ .end = IRQ_PA0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
+ .port_pin_base = GPIO_PA0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 0, /* PINT0 */
+ .pint_assign = true, /* PINT upper 16 bit */
+ .pint_map = 0, /* mapping mask in PINT */
+};
+
+static struct platform_device bfin_gpa_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_gpa_resources),
+ .resource = bfin_gpa_resources,
+ .dev = {
+ .platform_data = &bfin_gpa_pdata, /* Passed to driver */
+ },
+};
+
+static struct resource bfin_gpb_resources[] = {
+ {
+ .start = PORTB_FER,
+ .end = PORTB_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PB0,
+ .end = IRQ_PB0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
+ .port_pin_base = GPIO_PB0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 0,
+ .pint_assign = false,
+ .pint_map = 1,
+};
+
+static struct platform_device bfin_gpb_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(bfin_gpb_resources),
+ .resource = bfin_gpb_resources,
+ .dev = {
+ .platform_data = &bfin_gpb_pdata, /* Passed to driver */
+ },
+};
+
+static struct resource bfin_gpc_resources[] = {
+ {
+ .start = PORTC_FER,
+ .end = PORTC_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PC0,
+ .end = IRQ_PC0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
+ .port_pin_base = GPIO_PC0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 1,
+ .pint_assign = false,
+ .pint_map = 1,
+};
+
+static struct platform_device bfin_gpc_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 2,
+ .num_resources = ARRAY_SIZE(bfin_gpc_resources),
+ .resource = bfin_gpc_resources,
+ .dev = {
+ .platform_data = &bfin_gpc_pdata, /* Passed to driver */
+ },
+};
+
+static struct resource bfin_gpd_resources[] = {
+ {
+ .start = PORTD_FER,
+ .end = PORTD_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PD0,
+ .end = IRQ_PD0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
+ .port_pin_base = GPIO_PD0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 2,
+ .pint_assign = false,
+ .pint_map = 1,
+};
+
+static struct platform_device bfin_gpd_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 3,
+ .num_resources = ARRAY_SIZE(bfin_gpd_resources),
+ .resource = bfin_gpd_resources,
+ .dev = {
+ .platform_data = &bfin_gpd_pdata, /* Passed to driver */
+ },
+};
+
+static struct resource bfin_gpe_resources[] = {
+ {
+ .start = PORTE_FER,
+ .end = PORTE_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PE0,
+ .end = IRQ_PE0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
+ .port_pin_base = GPIO_PE0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 3,
+ .pint_assign = false,
+ .pint_map = 1,
+};
+
+static struct platform_device bfin_gpe_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 4,
+ .num_resources = ARRAY_SIZE(bfin_gpe_resources),
+ .resource = bfin_gpe_resources,
+ .dev = {
+ .platform_data = &bfin_gpe_pdata, /* Passed to driver */
+ },
+};
+
+static struct resource bfin_gpf_resources[] = {
+ {
+ .start = PORTF_FER,
+ .end = PORTF_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PF0,
+ .end = IRQ_PF0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
+ .port_pin_base = GPIO_PF0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 4,
+ .pint_assign = false,
+ .pint_map = 1,
+};
+
+static struct platform_device bfin_gpf_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 5,
+ .num_resources = ARRAY_SIZE(bfin_gpf_resources),
+ .resource = bfin_gpf_resources,
+ .dev = {
+ .platform_data = &bfin_gpf_pdata, /* Passed to driver */
+ },
+};
+
+static struct resource bfin_gpg_resources[] = {
+ {
+ .start = PORTG_FER,
+ .end = PORTG_MUX + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_PG0,
+ .end = IRQ_PG0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
+ .port_pin_base = GPIO_PG0,
+ .port_width = GPIO_BANKSIZE,
+ .pint_id = 5,
+ .pint_assign = false,
+ .pint_map = 1,
+};
+
+static struct platform_device bfin_gpg_device = {
+ .name = ADI_GPIO_DEVNAME,
+ .id = 6,
+ .num_resources = ARRAY_SIZE(bfin_gpg_resources),
+ .resource = bfin_gpg_resources,
+ .dev = {
+ .platform_data = &bfin_gpg_pdata, /* Passed to driver */
+ },
+};
+
+#endif
+
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/input.h>
#include <linux/gpio_keys.h>
@@ -1258,7 +1707,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "m25p80", /* Name of spi_driver for this device */
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
+ .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
.platform_data = &bfin_spi_flash_data,
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
@@ -1271,7 +1720,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.irq = IRQ_PD9,
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
- .chip_select = 4,
+ .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1279,7 +1728,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
- .chip_select = 1,
+ .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
.controller_data = &spidev_chip_info,
},
#endif
@@ -1474,6 +1923,22 @@ static struct platform_device bfin_dpmc = {
static struct platform_device *ezkit_devices[] __initdata = {
&bfin_dpmc,
+#if defined(CONFIG_PINCTRL_ADI2)
+ &bfin_pinctrl_device,
+ &bfin_pint0_device,
+ &bfin_pint1_device,
+ &bfin_pint2_device,
+ &bfin_pint3_device,
+ &bfin_pint4_device,
+ &bfin_pint5_device,
+ &bfin_gpa_device,
+ &bfin_gpb_device,
+ &bfin_gpc_device,
+ &bfin_gpd_device,
+ &bfin_gpe_device,
+ &bfin_gpf_device,
+ &bfin_gpg_device,
+#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
@@ -1590,20 +2055,52 @@ static struct platform_device *ezkit_devices[] __initdata = {
};
+/* Pin control settings */
+static struct pinctrl_map __initdata bfin_pinmux_map[] = {
+ /* per-device maps */
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
+#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
+#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
+#else
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
+#endif
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
+};
+
static int __init ezkit_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __func__);
+ /* Initialize pinmuxing */
+ pinctrl_register_mappings(bfin_pinmux_map,
+ ARRAY_SIZE(bfin_pinmux_map));
+
i2c_register_board_info(0, bfin_i2c_board_info0,
ARRAY_SIZE(bfin_i2c_board_info0));
i2c_register_board_info(1, bfin_i2c_board_info1,
ARRAY_SIZE(bfin_i2c_board_info1));
-#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
- if (!peripheral_request_list(pins, "emac0"))
- printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
-#endif
-
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
@@ -1622,18 +2119,6 @@ static struct platform_device *ezkit_early_devices[] __initdata = {
&bfin_uart1_device,
#endif
#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#endif
};
void __init native_machine_early_platform_add_devices(void)
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
index 437d56c8228..dab8849af88 100644
--- a/arch/blackfin/mach-bf609/clock.c
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -220,6 +220,12 @@ unsigned long sys_clk_get_rate(struct clk *clk)
}
}
+unsigned long dummy_get_rate(struct clk *clk)
+{
+ clk->parent->rate = clk_get_rate(clk->parent);
+ return clk->parent->rate;
+}
+
unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long max_rate;
@@ -283,6 +289,10 @@ static struct clk_ops sys_clk_ops = {
.round_rate = sys_clk_round_rate,
};
+static struct clk_ops dummy_clk_ops = {
+ .get_rate = dummy_get_rate,
+};
+
static struct clk sys_clkin = {
.name = "SYS_CLKIN",
.rate = CONFIG_CLKIN_HZ,
@@ -364,6 +374,12 @@ static struct clk oclk = {
.parent = &pll_clk,
};
+static struct clk ethclk = {
+ .name = "stmmaceth",
+ .parent = &sclk0,
+ .ops = &dummy_clk_ops,
+};
+
static struct clk_lookup bf609_clks[] = {
CLK(sys_clkin, NULL, "SYS_CLKIN"),
CLK(pll_clk, NULL, "PLLCLK"),
@@ -375,6 +391,7 @@ static struct clk_lookup bf609_clks[] = {
CLK(sclk1, NULL, "SCLK1"),
CLK(dclk, NULL, "DCLK"),
CLK(oclk, NULL, "OCLK"),
+ CLK(ethclk, NULL, "stmmaceth"),
};
int __init clk_init(void)
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
index f1a6afae1a7..35caa7bc192 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -839,6 +839,16 @@
#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
+/* ==================================================
+ Pads Controller Registers
+ ================================================== */
+
+/* =========================
+ PADS0
+ ========================= */
+#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
+#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
+#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
/* =========================
PINT Registers
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
index c32c8cc8db2..07182513e79 100644
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -152,14 +152,6 @@ struct gpio_port_t {
unsigned long revid;
};
-struct gpio_port_s {
- unsigned short fer;
- unsigned short data;
- unsigned short dir;
- unsigned short inen;
- unsigned int mux;
-};
-
#endif
#include <mach-common/ports-a.h>
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
index fa0843d5d77..d1cb6a86f80 100644
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -298,7 +298,7 @@
extern u8 sec_int_priority[];
/*
- * bfin pint registers layout
+ * gpio pint registers layout
*/
struct bfin_pint_regs {
u32 mask_set;
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
index 2e1a51c2509..c48bb71a55c 100644
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -7,8 +7,6 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
/* EMAC RMII Port Mux */
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
@@ -21,6 +19,7 @@
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
#define P_RMII0 {\
P_MII0_ETxD0, \
@@ -32,6 +31,7 @@
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_CRS, \
+ P_MII0_PTPPPS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
@@ -46,6 +46,7 @@
#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
#define P_RMII1 {\
P_MII1_ETxD0, \
@@ -57,6 +58,7 @@
P_MII1_TxCLK, \
P_MII1_PHYINT, \
P_MII1_CRS, \
+ P_MII1_PTPPPS, \
P_MII1_MDC, \
P_MII1_MDIO, 0}
diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c
new file mode 100644
index 00000000000..ac1f07c3359
--- /dev/null
+++ b/arch/blackfin/mach-bf609/scb.c
@@ -0,0 +1,363 @@
+/*
+ * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
+ *
+ * Copyright 2012 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/blackfin.h>
+#include <asm/scb.h>
+
+struct scb_mi_prio scb_data[] = {
+#ifdef CONFIG_SCB0_MI0
+ { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
+ CONFIG_SCB0_MI0_SLOT0,
+ CONFIG_SCB0_MI0_SLOT1,
+ CONFIG_SCB0_MI0_SLOT2,
+ CONFIG_SCB0_MI0_SLOT3,
+ CONFIG_SCB0_MI0_SLOT4,
+ CONFIG_SCB0_MI0_SLOT5,
+ CONFIG_SCB0_MI0_SLOT6,
+ CONFIG_SCB0_MI0_SLOT7,
+ CONFIG_SCB0_MI0_SLOT8,
+ CONFIG_SCB0_MI0_SLOT9,
+ CONFIG_SCB0_MI0_SLOT10,
+ CONFIG_SCB0_MI0_SLOT11,
+ CONFIG_SCB0_MI0_SLOT12,
+ CONFIG_SCB0_MI0_SLOT13,
+ CONFIG_SCB0_MI0_SLOT14,
+ CONFIG_SCB0_MI0_SLOT15,
+ CONFIG_SCB0_MI0_SLOT16,
+ CONFIG_SCB0_MI0_SLOT17,
+ CONFIG_SCB0_MI0_SLOT18,
+ CONFIG_SCB0_MI0_SLOT19,
+ CONFIG_SCB0_MI0_SLOT20,
+ CONFIG_SCB0_MI0_SLOT21,
+ CONFIG_SCB0_MI0_SLOT22,
+ CONFIG_SCB0_MI0_SLOT23,
+ CONFIG_SCB0_MI0_SLOT24,
+ CONFIG_SCB0_MI0_SLOT25,
+ CONFIG_SCB0_MI0_SLOT26,
+ CONFIG_SCB0_MI0_SLOT27,
+ CONFIG_SCB0_MI0_SLOT28,
+ CONFIG_SCB0_MI0_SLOT29,
+ CONFIG_SCB0_MI0_SLOT30,
+ CONFIG_SCB0_MI0_SLOT31
+ },
+ },
+#endif
+#ifdef CONFIG_SCB0_MI1
+ { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
+ CONFIG_SCB0_MI1_SLOT0,
+ CONFIG_SCB0_MI1_SLOT1,
+ CONFIG_SCB0_MI1_SLOT2,
+ CONFIG_SCB0_MI1_SLOT3,
+ CONFIG_SCB0_MI1_SLOT4,
+ CONFIG_SCB0_MI1_SLOT5,
+ CONFIG_SCB0_MI1_SLOT6,
+ CONFIG_SCB0_MI1_SLOT7,
+ CONFIG_SCB0_MI1_SLOT8,
+ CONFIG_SCB0_MI1_SLOT9,
+ CONFIG_SCB0_MI1_SLOT10,
+ CONFIG_SCB0_MI1_SLOT11,
+ CONFIG_SCB0_MI1_SLOT12,
+ CONFIG_SCB0_MI1_SLOT13,
+ CONFIG_SCB0_MI1_SLOT14,
+ CONFIG_SCB0_MI1_SLOT15,
+ CONFIG_SCB0_MI1_SLOT16,
+ CONFIG_SCB0_MI1_SLOT17,
+ CONFIG_SCB0_MI1_SLOT18,
+ CONFIG_SCB0_MI1_SLOT19,
+ CONFIG_SCB0_MI1_SLOT20,
+ CONFIG_SCB0_MI1_SLOT21,
+ CONFIG_SCB0_MI1_SLOT22,
+ CONFIG_SCB0_MI1_SLOT23,
+ CONFIG_SCB0_MI1_SLOT24,
+ CONFIG_SCB0_MI1_SLOT25,
+ CONFIG_SCB0_MI1_SLOT26,
+ CONFIG_SCB0_MI1_SLOT27,
+ CONFIG_SCB0_MI1_SLOT28,
+ CONFIG_SCB0_MI1_SLOT29,
+ CONFIG_SCB0_MI1_SLOT30,
+ CONFIG_SCB0_MI1_SLOT31
+ },
+ },
+#endif
+#ifdef CONFIG_SCB0_MI2
+ { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
+ CONFIG_SCB0_MI2_SLOT0,
+ CONFIG_SCB0_MI2_SLOT1,
+ CONFIG_SCB0_MI2_SLOT2,
+ CONFIG_SCB0_MI2_SLOT3,
+ CONFIG_SCB0_MI2_SLOT4,
+ CONFIG_SCB0_MI2_SLOT5,
+ CONFIG_SCB0_MI2_SLOT6,
+ CONFIG_SCB0_MI2_SLOT7,
+ CONFIG_SCB0_MI2_SLOT8,
+ CONFIG_SCB0_MI2_SLOT9,
+ CONFIG_SCB0_MI2_SLOT10,
+ CONFIG_SCB0_MI2_SLOT11,
+ CONFIG_SCB0_MI2_SLOT12,
+ CONFIG_SCB0_MI2_SLOT13,
+ CONFIG_SCB0_MI2_SLOT14,
+ CONFIG_SCB0_MI2_SLOT15,
+ CONFIG_SCB0_MI2_SLOT16,
+ CONFIG_SCB0_MI2_SLOT17,
+ CONFIG_SCB0_MI2_SLOT18,
+ CONFIG_SCB0_MI2_SLOT19,
+ CONFIG_SCB0_MI2_SLOT20,
+ CONFIG_SCB0_MI2_SLOT21,
+ CONFIG_SCB0_MI2_SLOT22,
+ CONFIG_SCB0_MI2_SLOT23,
+ CONFIG_SCB0_MI2_SLOT24,
+ CONFIG_SCB0_MI2_SLOT25,
+ CONFIG_SCB0_MI2_SLOT26,
+ CONFIG_SCB0_MI2_SLOT27,
+ CONFIG_SCB0_MI2_SLOT28,
+ CONFIG_SCB0_MI2_SLOT29,
+ CONFIG_SCB0_MI2_SLOT30,
+ CONFIG_SCB0_MI2_SLOT31
+ },
+ },
+#endif
+#ifdef CONFIG_SCB0_MI3
+ { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
+ CONFIG_SCB0_MI3_SLOT0,
+ CONFIG_SCB0_MI3_SLOT1,
+ CONFIG_SCB0_MI3_SLOT2,
+ CONFIG_SCB0_MI3_SLOT3,
+ CONFIG_SCB0_MI3_SLOT4,
+ CONFIG_SCB0_MI3_SLOT5,
+ CONFIG_SCB0_MI3_SLOT6,
+ CONFIG_SCB0_MI3_SLOT7,
+ CONFIG_SCB0_MI3_SLOT8,
+ CONFIG_SCB0_MI3_SLOT9,
+ CONFIG_SCB0_MI3_SLOT10,
+ CONFIG_SCB0_MI3_SLOT11,
+ CONFIG_SCB0_MI3_SLOT12,
+ CONFIG_SCB0_MI3_SLOT13,
+ CONFIG_SCB0_MI3_SLOT14,
+ CONFIG_SCB0_MI3_SLOT15,
+ CONFIG_SCB0_MI3_SLOT16,
+ CONFIG_SCB0_MI3_SLOT17,
+ CONFIG_SCB0_MI3_SLOT18,
+ CONFIG_SCB0_MI3_SLOT19,
+ CONFIG_SCB0_MI3_SLOT20,
+ CONFIG_SCB0_MI3_SLOT21,
+ CONFIG_SCB0_MI3_SLOT22,
+ CONFIG_SCB0_MI3_SLOT23,
+ CONFIG_SCB0_MI3_SLOT24,
+ CONFIG_SCB0_MI3_SLOT25,
+ CONFIG_SCB0_MI3_SLOT26,
+ CONFIG_SCB0_MI3_SLOT27,
+ CONFIG_SCB0_MI3_SLOT28,
+ CONFIG_SCB0_MI3_SLOT29,
+ CONFIG_SCB0_MI3_SLOT30,
+ CONFIG_SCB0_MI3_SLOT31
+ },
+ },
+#endif
+#ifdef CONFIG_SCB0_MI4
+ { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
+ CONFIG_SCB0_MI4_SLOT0,
+ CONFIG_SCB0_MI4_SLOT1,
+ CONFIG_SCB0_MI4_SLOT2,
+ CONFIG_SCB0_MI4_SLOT3,
+ CONFIG_SCB0_MI4_SLOT4,
+ CONFIG_SCB0_MI4_SLOT5,
+ CONFIG_SCB0_MI4_SLOT6,
+ CONFIG_SCB0_MI4_SLOT7,
+ CONFIG_SCB0_MI4_SLOT8,
+ CONFIG_SCB0_MI4_SLOT9,
+ CONFIG_SCB0_MI4_SLOT10,
+ CONFIG_SCB0_MI4_SLOT11,
+ CONFIG_SCB0_MI4_SLOT12,
+ CONFIG_SCB0_MI4_SLOT13,
+ CONFIG_SCB0_MI4_SLOT14,
+ CONFIG_SCB0_MI4_SLOT15,
+ CONFIG_SCB0_MI4_SLOT16,
+ CONFIG_SCB0_MI4_SLOT17,
+ CONFIG_SCB0_MI4_SLOT18,
+ CONFIG_SCB0_MI4_SLOT19,
+ CONFIG_SCB0_MI4_SLOT20,
+ CONFIG_SCB0_MI4_SLOT21,
+ CONFIG_SCB0_MI4_SLOT22,
+ CONFIG_SCB0_MI4_SLOT23,
+ CONFIG_SCB0_MI4_SLOT24,
+ CONFIG_SCB0_MI4_SLOT25,
+ CONFIG_SCB0_MI4_SLOT26,
+ CONFIG_SCB0_MI4_SLOT27,
+ CONFIG_SCB0_MI4_SLOT28,
+ CONFIG_SCB0_MI4_SLOT29,
+ CONFIG_SCB0_MI4_SLOT30,
+ CONFIG_SCB0_MI4_SLOT31
+ },
+ },
+#endif
+#ifdef CONFIG_SCB0_MI5
+ { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
+ CONFIG_SCB0_MI5_SLOT0,
+ CONFIG_SCB0_MI5_SLOT1,
+ CONFIG_SCB0_MI5_SLOT2,
+ CONFIG_SCB0_MI5_SLOT3,
+ CONFIG_SCB0_MI5_SLOT4,
+ CONFIG_SCB0_MI5_SLOT5,
+ CONFIG_SCB0_MI5_SLOT6,
+ CONFIG_SCB0_MI5_SLOT7,
+ CONFIG_SCB0_MI5_SLOT8,
+ CONFIG_SCB0_MI5_SLOT9,
+ CONFIG_SCB0_MI5_SLOT10,
+ CONFIG_SCB0_MI5_SLOT11,
+ CONFIG_SCB0_MI5_SLOT12,
+ CONFIG_SCB0_MI5_SLOT13,
+ CONFIG_SCB0_MI5_SLOT14,
+ CONFIG_SCB0_MI5_SLOT15
+ },
+ },
+#endif
+#ifdef CONFIG_SCB1_MI0
+ { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
+ CONFIG_SCB1_MI0_SLOT0,
+ CONFIG_SCB1_MI0_SLOT1,
+ CONFIG_SCB1_MI0_SLOT2,
+ CONFIG_SCB1_MI0_SLOT3,
+ CONFIG_SCB1_MI0_SLOT4,
+ CONFIG_SCB1_MI0_SLOT5,
+ CONFIG_SCB1_MI0_SLOT6,
+ CONFIG_SCB1_MI0_SLOT7,
+ CONFIG_SCB1_MI0_SLOT8,
+ CONFIG_SCB1_MI0_SLOT9,
+ CONFIG_SCB1_MI0_SLOT10,
+ CONFIG_SCB1_MI0_SLOT11,
+ CONFIG_SCB1_MI0_SLOT12,
+ CONFIG_SCB1_MI0_SLOT13,
+ CONFIG_SCB1_MI0_SLOT14,
+ CONFIG_SCB1_MI0_SLOT15,
+ CONFIG_SCB1_MI0_SLOT16,
+ CONFIG_SCB1_MI0_SLOT17,
+ CONFIG_SCB1_MI0_SLOT18,
+ CONFIG_SCB1_MI0_SLOT19
+ },
+ },
+#endif
+#ifdef CONFIG_SCB2_MI0
+ { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
+ CONFIG_SCB2_MI0_SLOT0,
+ CONFIG_SCB2_MI0_SLOT1,
+ CONFIG_SCB2_MI0_SLOT2,
+ CONFIG_SCB2_MI0_SLOT3,
+ CONFIG_SCB2_MI0_SLOT4,
+ CONFIG_SCB2_MI0_SLOT5,
+ CONFIG_SCB2_MI0_SLOT6,
+ CONFIG_SCB2_MI0_SLOT7,
+ CONFIG_SCB2_MI0_SLOT8,
+ CONFIG_SCB2_MI0_SLOT9
+ },
+ },
+#endif
+#ifdef CONFIG_SCB3_MI0
+ { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
+ CONFIG_SCB3_MI0_SLOT0,
+ CONFIG_SCB3_MI0_SLOT1,
+ CONFIG_SCB3_MI0_SLOT2,
+ CONFIG_SCB3_MI0_SLOT3,
+ CONFIG_SCB3_MI0_SLOT4,
+ CONFIG_SCB3_MI0_SLOT5,
+ CONFIG_SCB3_MI0_SLOT6,
+ CONFIG_SCB3_MI0_SLOT7,
+ CONFIG_SCB3_MI0_SLOT8,
+ CONFIG_SCB3_MI0_SLOT9,
+ CONFIG_SCB3_MI0_SLOT10,
+ CONFIG_SCB3_MI0_SLOT11,
+ CONFIG_SCB3_MI0_SLOT12,
+ CONFIG_SCB3_MI0_SLOT13,
+ CONFIG_SCB3_MI0_SLOT14,
+ CONFIG_SCB3_MI0_SLOT15
+ },
+ },
+#endif
+#ifdef CONFIG_SCB4_MI0
+ { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
+ CONFIG_SCB4_MI0_SLOT0,
+ CONFIG_SCB4_MI0_SLOT1,
+ CONFIG_SCB4_MI0_SLOT2,
+ CONFIG_SCB4_MI0_SLOT3,
+ CONFIG_SCB4_MI0_SLOT4,
+ CONFIG_SCB4_MI0_SLOT5,
+ CONFIG_SCB4_MI0_SLOT6,
+ CONFIG_SCB4_MI0_SLOT7,
+ CONFIG_SCB4_MI0_SLOT8,
+ CONFIG_SCB4_MI0_SLOT9,
+ CONFIG_SCB4_MI0_SLOT10,
+ CONFIG_SCB4_MI0_SLOT11,
+ CONFIG_SCB4_MI0_SLOT12,
+ CONFIG_SCB4_MI0_SLOT13,
+ CONFIG_SCB4_MI0_SLOT14,
+ CONFIG_SCB4_MI0_SLOT15
+ },
+ },
+#endif
+#ifdef CONFIG_SCB5_MI0
+ { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
+ CONFIG_SCB5_MI0_SLOT0,
+ CONFIG_SCB5_MI0_SLOT1,
+ CONFIG_SCB5_MI0_SLOT2,
+ CONFIG_SCB5_MI0_SLOT3,
+ CONFIG_SCB5_MI0_SLOT4,
+ CONFIG_SCB5_MI0_SLOT5,
+ CONFIG_SCB5_MI0_SLOT6,
+ CONFIG_SCB5_MI0_SLOT7
+ },
+ },
+#endif
+#ifdef CONFIG_SCB6_MI0
+ { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
+ CONFIG_SCB6_MI0_SLOT0,
+ CONFIG_SCB6_MI0_SLOT1,
+ CONFIG_SCB6_MI0_SLOT2,
+ CONFIG_SCB6_MI0_SLOT3
+ },
+ },
+#endif
+#ifdef CONFIG_SCB7_MI0
+ { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
+ CONFIG_SCB7_MI0_SLOT0,
+ CONFIG_SCB7_MI0_SLOT1,
+ CONFIG_SCB7_MI0_SLOT2,
+ CONFIG_SCB7_MI0_SLOT3,
+ CONFIG_SCB7_MI0_SLOT4,
+ CONFIG_SCB7_MI0_SLOT5
+ },
+ },
+#endif
+#ifdef CONFIG_SCB8_MI0
+ { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
+ CONFIG_SCB8_MI0_SLOT0,
+ CONFIG_SCB8_MI0_SLOT1,
+ CONFIG_SCB8_MI0_SLOT2,
+ CONFIG_SCB8_MI0_SLOT3,
+ CONFIG_SCB8_MI0_SLOT4,
+ CONFIG_SCB8_MI0_SLOT5,
+ CONFIG_SCB8_MI0_SLOT6,
+ CONFIG_SCB8_MI0_SLOT7
+ },
+ },
+#endif
+#ifdef CONFIG_SCB9_MI0
+ { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
+ CONFIG_SCB9_MI0_SLOT0,
+ CONFIG_SCB9_MI0_SLOT1,
+ CONFIG_SCB9_MI0_SLOT2,
+ CONFIG_SCB9_MI0_SLOT3,
+ CONFIG_SCB9_MI0_SLOT4,
+ CONFIG_SCB9_MI0_SLOT5,
+ CONFIG_SCB9_MI0_SLOT6,
+ CONFIG_SCB9_MI0_SLOT7,
+ CONFIG_SCB9_MI0_SLOT8,
+ CONFIG_SCB9_MI0_SLOT9
+ },
+ },
+#endif
+ { 0, }
+};
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-01-01 08:25:52 +0000