diff options
Diffstat (limited to 'arch/m68k/include/asm')
| -rw-r--r-- | arch/m68k/include/asm/m532xsim.h | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 38333703a56..d4092fa7e5f 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -393,32 +393,32 @@ #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) #define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) #define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) -#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) -#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) -#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) -#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) -#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) -#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) -#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) -#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) -#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) -#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) -#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) -#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) -#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) -#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) -#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) -#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) -#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) -#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) -#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) -#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) -#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) -#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) -#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) -#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) -#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) -#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) +#define MCFGPIO_PAR_FEC (0xFC0A4050) +#define MCFGPIO_PAR_PWM (0xFC0A4051) +#define MCFGPIO_PAR_BUSCTL (0xFC0A4052) +#define MCFGPIO_PAR_FECI2C (0xFC0A4053) +#define MCFGPIO_PAR_BE (0xFC0A4054) +#define MCFGPIO_PAR_CS (0xFC0A4055) +#define MCFGPIO_PAR_SSI (0xFC0A4056) +#define MCFGPIO_PAR_UART (0xFC0A4058) +#define MCFGPIO_PAR_QSPI (0xFC0A405A) +#define MCFGPIO_PAR_TIMER (0xFC0A405C) +#define MCFGPIO_PAR_LCDDATA (0xFC0A405D) +#define MCFGPIO_PAR_LCDCTL (0xFC0A405E) +#define MCFGPIO_PAR_IRQ (0xFC0A4060) +#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064) +#define MCFGPIO_MSCR_SDRAM (0xFC0A4065) +#define MCFGPIO_DSCR_I2C (0xFC0A4068) +#define MCFGPIO_DSCR_PWM (0xFC0A4069) +#define MCFGPIO_DSCR_FEC (0xFC0A406A) +#define MCFGPIO_DSCR_UART (0xFC0A406B) +#define MCFGPIO_DSCR_QSPI (0xFC0A406C) +#define MCFGPIO_DSCR_TIMER (0xFC0A406D) +#define MCFGPIO_DSCR_SSI (0xFC0A406E) +#define MCFGPIO_DSCR_LCD (0xFC0A406F) +#define MCFGPIO_DSCR_DEBUG (0xFC0A4070) +#define MCFGPIO_DSCR_CLKRST (0xFC0A4071) +#define MCFGPIO_DSCR_IRQ (0xFC0A4072) /* Bit definitions and macros for MCF_GPIO_PODR_FECH */ #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) |