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-rw-r--r--arch/m68k/include/asm/m5206sim.h10
-rw-r--r--arch/m68k/include/asm/m520xsim.h33
-rw-r--r--arch/m68k/include/asm/m523xsim.h42
-rw-r--r--arch/m68k/include/asm/m5249sim.h18
-rw-r--r--arch/m68k/include/asm/m5272sim.h17
-rw-r--r--arch/m68k/include/asm/m527xsim.h53
-rw-r--r--arch/m68k/include/asm/m528xsim.h40
-rw-r--r--arch/m68k/include/asm/m5307sim.h10
-rw-r--r--arch/m68k/include/asm/m532xsim.h35
-rw-r--r--arch/m68k/include/asm/m5407sim.h6
-rw-r--r--arch/m68k/include/asm/m54xxsim.h16
-rw-r--r--arch/m68k/include/asm/machdep.h5
-rw-r--r--arch/m68k/include/asm/mcfqspi.h11
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
-rw-r--r--arch/m68k/include/asm/socket.h4
-rw-r--r--arch/m68k/include/asm/system.h1
16 files changed, 237 insertions, 69 deletions
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 9015eadd5c0..69722366b08 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -100,11 +100,11 @@
#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
#if defined(CONFIG_NETtel)
-#define MCFUART_BASE1 0x180 /* Base address of UART1 */
-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
#else
-#define MCFUART_BASE1 0x140 /* Base address of UART1 */
-#define MCFUART_BASE2 0x180 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
#endif
/*
@@ -112,6 +112,8 @@
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
/*
* Generic GPIO
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index eda62de7e60..17f2aab9cf9 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -48,8 +48,21 @@
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
+#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
+#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+
/*
* SDRAM configuration registers.
*/
@@ -144,15 +157,25 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
-#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
-#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
+#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
+#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
/*
* FEC module.
*/
-#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
-#define MCFFEC_SIZE 0x800 /* Register set size */
+#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
+#define MCFFEC_SIZE0 0x800 /* Register set size */
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
+#define MCFQSPI_SIZE 0x40 /* Register set size */
+
+#define MCFQSPI_CS0 46
+#define MCFQSPI_CS1 47
+#define MCFQSPI_CS2 27
/*
* Reset Control Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 6235921eca4..075062d4eec 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -35,8 +35,23 @@
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
-#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
+#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
/*
* SDRAM configuration registers.
@@ -50,8 +65,8 @@
/*
* Reset Control Unit (relative to IPSBAR).
*/
-#define MCF_RCR 0x110000
-#define MCF_RSR 0x110001
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
@@ -59,15 +74,26 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
-#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
-#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
*/
-#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
-#define MCFFEC_SIZE 0x800
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0 0x800
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#define MCFQSPI_CS0 91
+#define MCFQSPI_CS1 92
+#define MCFQSPI_CS2 103
+#define MCFQSPI_CS3 99
/*
* GPIO module.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 805714ca8d7..7f0c2c3660f 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -76,8 +76,19 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
+#define MCFQSPI_SIZE 0x40 /* Register set size */
+
+#define MCFQSPI_CS0 29
+#define MCFQSPI_CS1 24
+#define MCFQSPI_CS2 21
+#define MCFQSPI_CS3 22
/*
* DMA unit base addresses.
@@ -108,6 +119,9 @@
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
+
/*
* General purpose IO registers (in MBAR2).
*/
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 759c2b07a99..a58f1760d85 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -68,8 +68,8 @@
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
-#define MCFUART_BASE1 0x100 /* Base address of UART1 */
-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
@@ -88,6 +88,9 @@
#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
+#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
+#define MCFFEC_SIZE0 0x1d0
+
/*
* Define system peripheral IRQ usage.
*/
@@ -101,8 +104,8 @@
#define MCF_IRQ_TIMER2 70 /* Timer 2 */
#define MCF_IRQ_TIMER3 71 /* Timer 3 */
#define MCF_IRQ_TIMER4 72 /* Timer 4 */
-#define MCF_IRQ_UART1 73 /* UART 1 */
-#define MCF_IRQ_UART2 74 /* UART 2 */
+#define MCF_IRQ_UART0 73 /* UART 0 */
+#define MCF_IRQ_UART1 74 /* UART 1 */
#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
@@ -114,9 +117,9 @@
#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
#define MCF_IRQ_DMA 85 /* DMA Controller */
-#define MCF_IRQ_ERX 86 /* Ethernet Receiver */
-#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */
-#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */
+#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
+#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
+#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 758810ef91e..83db8106f50 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -38,8 +38,29 @@
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+#define MCFINT2_VECBASE 128 /* Vector base number 2 */
+#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
+#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
+#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
+#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
+#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+
/*
* SDRAM configuration registers.
*/
@@ -72,9 +93,9 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
-#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
-#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
@@ -84,6 +105,28 @@
#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
#define MCFFEC_SIZE1 0x800
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#ifdef CONFIG_M5271
+#define MCFQSPI_CS0 91
+#define MCFQSPI_CS1 92
+#define MCFQSPI_CS2 99
+#define MCFQSPI_CS3 103
+#endif
+#ifdef CONFIG_M5275
+#define MCFQSPI_CS0 59
+#define MCFQSPI_CS1 60
+#define MCFQSPI_CS2 61
+#define MCFQSPI_CS3 62
+#endif
+
+/*
+ * GPIO module.
+ */
#ifdef CONFIG_M5271
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
@@ -285,8 +328,8 @@
/*
* Reset Control Unit (relative to IPSBAR).
*/
-#define MCF_RCR 0x110000
-#define MCF_RSR 0x110001
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index d798bd5df56..569476fba18 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -35,9 +35,24 @@
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+
/*
* SDRAM configuration registers.
*/
@@ -58,15 +73,26 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
-#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
-#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
/*
* FEC ethernet module.
*/
-#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
-#define MCFFEC_SIZE 0x800
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
+#define MCFFEC_SIZE0 0x800
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#define MCFQSPI_CS0 147
+#define MCFQSPI_CS1 148
+#define MCFQSPI_CS2 149
+#define MCFQSPI_CS3 150
/*
* GPIO registers
@@ -246,8 +272,8 @@
/*
* Reset Control Unit (relative to IPSBAR).
*/
-#define MCF_RCR 0x110000
-#define MCF_RSR 0x110001
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 8f8609fcc9b..3bc3adaa7ee 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -117,11 +117,11 @@
* UART module.
*/
#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */
#else
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
#endif
/*
@@ -176,6 +176,8 @@
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
/****************************************************************************/
#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index ba4cc784f57..29b66e21413 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -24,6 +24,19 @@
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
+#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
+#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_WTM_WCR MCF_REG16(0xFC098000)
@@ -82,9 +95,25 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
-#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
-#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
+#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
+#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
+#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
+
+/*
+ * FEC module.
+ */
+#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
+#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
+#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
+
+#define MCFQSPI_CS0 84
+#define MCFQSPI_CS1 85
+#define MCFQSPI_CS2 86
/*
* Timer module.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 51e00b00b8a..79f58dd6a83 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -85,8 +85,8 @@
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
-#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
-#define MCFUART_BASE2 0x200 /* Base address of UART2 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
@@ -139,6 +139,8 @@
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
/****************************************************************************/
#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 1ed8bfb0277..ae56b8848a9 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -31,16 +31,20 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 0x8600 /* Base address of UART1 */
-#define MCFUART_BASE2 0x8700 /* Base address of UART2 */
-#define MCFUART_BASE3 0x8800 /* Base address of UART3 */
-#define MCFUART_BASE4 0x8900 /* Base address of UART4 */
+#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
+#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
+#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
/*
* Define system peripheral IRQ usage.
*/
-#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
-#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
+#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
+#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
+#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
/*
* Generic GPIO support
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
index 789f3b2de0e..825c1c81319 100644
--- a/arch/m68k/include/asm/machdep.h
+++ b/arch/m68k/include/asm/machdep.h
@@ -22,8 +22,6 @@ extern unsigned int (*mach_get_ss)(void);
extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_clock_mmss)(unsigned long);
-extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
- int *min, int *sec);
extern void (*mach_reset)( void );
extern void (*mach_halt)( void );
extern void (*mach_power_off)( void );
@@ -35,9 +33,8 @@ extern void (*mach_l2_flush) (int);
extern void (*mach_beep) (unsigned int, unsigned int);
/* Hardware clock functions */
-extern void hw_timer_init(void);
+extern void hw_timer_init(irq_handler_t handler);
extern unsigned long hw_timer_offset(void);
-extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
extern void config_BSP(char *command, int len);
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
index 7fe631972f1..7b51416ccae 100644
--- a/arch/m68k/include/asm/mcfqspi.h
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -21,17 +21,6 @@
#ifndef mcfqspi_h
#define mcfqspi_h
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
-#elif defined(CONFIG_M5249)
-#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
-#elif defined(CONFIG_M520x)
-#define MCFQSPI_IOBASE 0xFC05C000
-#elif defined(CONFIG_M532x)
-#define MCFQSPI_IOBASE 0xFC058000
-#endif
-#define MCFQSPI_IOSIZE 0x40
-
/**
* struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
* @setup: setup the control; allocate gpio's, etc. May be NULL.
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2abedff0a69..2d3bc774b3c 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -41,7 +41,10 @@ struct mcf_platform_uart {
#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
-#else
+#endif
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5249) || defined(CONFIG_M5307) || \
+ defined(CONFIG_M5407)
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
#endif
#define MCFUART_UIPR 0x34 /* Input Port (r) */
diff --git a/arch/m68k/include/asm/socket.h b/arch/m68k/include/asm/socket.h
index d4708ce466e..d1be684edf9 100644
--- a/arch/m68k/include/asm/socket.h
+++ b/arch/m68k/include/asm/socket.h
@@ -64,5 +64,9 @@
#define SO_WIFI_STATUS 41
#define SCM_WIFI_STATUS SO_WIFI_STATUS
+#define SO_PEEK_OFF 42
+
+/* Instruct lower device to use last 4-bytes of skb data as FCS */
+#define SO_NOFCS 43
#endif /* _ASM_SOCKET_H */
diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h
index 47b01f4726b..8dc68178716 100644
--- a/arch/m68k/include/asm/system.h
+++ b/arch/m68k/include/asm/system.h
@@ -3,6 +3,7 @@
#include <linux/linkage.h>
#include <linux/kernel.h>
+#include <linux/bug.h>
#include <linux/irqflags.h>
#include <asm/segment.h>
#include <asm/entry.h>
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-22 04:49:03 +0000