diff options
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 166 |
1 files changed, 140 insertions, 26 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dcae3a7035d..16d5ab1615b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -10,6 +10,7 @@ config MIPS select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_ARCH_KGDB + select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK select ARCH_HAVE_CUSTOM_GPIO_H select HAVE_FUNCTION_TRACER @@ -62,13 +63,12 @@ config MIPS_ALCHEMY select CEVT_R4K select CSRC_R4K select IRQ_CPU + select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select ARCH_REQUIRE_GPIOLIB select SYS_SUPPORTS_ZBOOT - select USB_ARCH_HAS_OHCI - select USB_ARCH_HAS_EHCI config AR7 bool "Texas Instruments AR7" @@ -123,7 +123,7 @@ config BCM47XX select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK - select EARLY_PRINTK_8250 if EARLY_PRINTK + select USE_GENERIC_EARLY_PRINTK_8250 help Support for BCM47XX based boards @@ -150,7 +150,6 @@ config MIPS_COBALT select CSRC_R4K select CEVT_GT641XX select DMA_NONCOHERENT - select EARLY_PRINTK_8250 if EARLY_PRINTK select HW_HAS_PCI select I8253 select I8259 @@ -163,6 +162,7 @@ config MIPS_COBALT select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN + select USE_GENERIC_EARLY_PRINTK_8250 config MACH_DECSTATION bool "DECstations" @@ -235,7 +235,6 @@ config MACH_JZ4740 select IRQ_CPU select ARCH_REQUIRE_GPIOLIB select SYS_HAS_EARLY_PRINTK - select HAVE_PWM select HAVE_CLK select GENERIC_IRQ_CHIP @@ -320,6 +319,7 @@ config MIPS_MALTA select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS32_R3_5 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_NEVADA @@ -329,6 +329,7 @@ config MIPS_MALTA select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MIPS_CMP + select SYS_SUPPORTS_MIPS_CPS select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_SMARTMIPS select SYS_SUPPORTS_ZBOOT @@ -360,7 +361,6 @@ config MIPS_SEAD3 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_SMARTMIPS select SYS_SUPPORTS_MICROMIPS - select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO select USE_OF @@ -674,6 +674,7 @@ config SNI_RM select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN + select USE_GENERIC_EARLY_PRINTK_8250 help The SNI RM200/300/400 are MIPS-based machines manufactured by Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid @@ -718,8 +719,6 @@ config CAVIUM_OCTEON_SOC select SWAP_IO_SPACE select HW_HAS_PCI select ZONE_DMA32 - select USB_ARCH_HAS_OHCI - select USB_ARCH_HAS_EHCI select HOLES_IN_ZONE select ARCH_REQUIRE_GPIOLIB help @@ -756,8 +755,6 @@ config NLM_XLR_BOARD select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK - select USB_ARCH_HAS_OHCI if USB_SUPPORT - select USB_ARCH_HAS_EHCI if USB_SUPPORT select SYS_SUPPORTS_ZBOOT select SYS_SUPPORTS_ZBOOT_UART16550 help @@ -782,7 +779,6 @@ config NLM_XLP_BOARD select CEVT_R4K select CSRC_R4K select IRQ_CPU - select ARCH_SUPPORTS_MSI select ZONE_DMA32 if 64BIT select SYNC_R4K select SYS_HAS_EARLY_PRINTK @@ -868,6 +864,7 @@ config CEVT_R4K bool config CEVT_GIC + select MIPS_CM bool config CEVT_SB1250 @@ -886,6 +883,7 @@ config CSRC_R4K bool config CSRC_GIC + select MIPS_CM bool config CSRC_SB1250 @@ -1030,6 +1028,7 @@ config IRQ_GT641XX bool config IRQ_GIC + select MIPS_CM bool config PCI_GT64XXX_PCI0 @@ -1148,6 +1147,18 @@ choice prompt "CPU type" default CPU_R4X00 +config CPU_LOONGSON3 + bool "Loongson 3 CPU" + depends on SYS_HAS_CPU_LOONGSON3 + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + select CPU_SUPPORTS_HUGEPAGES + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + help + The Loongson 3 processor implements the MIPS64R2 instruction + set with many extensions. + config CPU_LOONGSON2E bool "Loongson 2E" depends on SYS_HAS_CPU_LOONGSON2E @@ -1203,6 +1214,7 @@ config CPU_MIPS32_R2 select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_HIGHMEM + select CPU_SUPPORTS_MSA select HAVE_KVM help Choose this option to build a kernel for release 2 or later of the @@ -1238,6 +1250,7 @@ config CPU_MIPS64_R2 select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select CPU_SUPPORTS_MSA help Choose this option to build a kernel for release 2 or later of the MIPS64 architecture. Many modern embedded systems with a 64-bit @@ -1396,7 +1409,6 @@ config CPU_CAVIUM_OCTEON select LIBFDT select USE_OF select USB_EHCI_BIG_ENDIAN_MMIO - select SYS_HAS_DMA_OPS select MIPS_L1_CACHE_SHIFT_7 help The Cavium Octeon processor is a highly integrated chip containing @@ -1448,6 +1460,26 @@ config CPU_XLP Netlogic Microsystems XLP processors. endchoice +config CPU_MIPS32_3_5_FEATURES + bool "MIPS32 Release 3.5 Features" + depends on SYS_HAS_CPU_MIPS32_R3_5 + depends on CPU_MIPS32_R2 + help + Choose this option to build a kernel for release 2 or later of the + MIPS32 architecture including features from the 3.5 release such as + support for Enhanced Virtual Addressing (EVA). + +config CPU_MIPS32_3_5_EVA + bool "Enhanced Virtual Addressing (EVA)" + depends on CPU_MIPS32_3_5_FEATURES + select EVA + default y + help + Choose this option if you want to enable the Enhanced Virtual + Addressing (EVA) on your MIPS32 core (such as proAptiv). + One of its primary benefits is an increase in the maximum size + of lowmem (up to 3GB). If unsure, say 'N' here. + if CPU_LOONGSON2F config CPU_NOP_WORKAROUNDS bool @@ -1523,6 +1555,10 @@ config CPU_BMIPS5000 select SYS_SUPPORTS_SMP select SYS_SUPPORTS_HOTPLUG_CPU +config SYS_HAS_CPU_LOONGSON3 + bool + select CPU_SUPPORTS_CPUFREQ + config SYS_HAS_CPU_LOONGSON2E bool @@ -1541,6 +1577,9 @@ config SYS_HAS_CPU_MIPS32_R1 config SYS_HAS_CPU_MIPS32_R2 bool +config SYS_HAS_CPU_MIPS32_R3_5 + bool + config SYS_HAS_CPU_MIPS64_R1 bool @@ -1657,6 +1696,9 @@ config CPU_MIPSR2 bool default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON +config EVA + bool + config SYS_SUPPORTS_32BIT_KERNEL bool config SYS_SUPPORTS_64BIT_KERNEL @@ -1729,7 +1771,7 @@ choice config PAGE_SIZE_4KB bool "4kB" - depends on !CPU_LOONGSON2 + depends on !CPU_LOONGSON2 && !CPU_LOONGSON3 help This option select the standard 4kB Linux page size. On some R3000-family processors this is the only available page size. Using @@ -1776,12 +1818,12 @@ endchoice config FORCE_MAX_ZONEORDER int "Maximum zone order" - range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB - default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB - range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB - default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB - range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB - default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB + range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB + default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB + range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB + default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB + range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB + default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB range 11 64 default "11" help @@ -1870,6 +1912,7 @@ config MIPS_MT_SMP select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select SYNC_R4K + select MIPS_GIC_IPI select MIPS_MT select SMP select SMP_UP @@ -1887,6 +1930,7 @@ config MIPS_MT_SMTC bool "Use all TCs on all VPEs for SMP (DEPRECATED)" depends on CPU_MIPS32_R2 depends on SYS_SUPPORTS_MULTITHREADING + depends on !MIPS_CPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT @@ -1994,13 +2038,45 @@ config MIPS_VPE_APSP_API_MT depends on MIPS_VPE_APSP_API && !MIPS_CMP config MIPS_CMP - bool "MIPS CMP support" - depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP + bool "MIPS CMP framework support (DEPRECATED)" + depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC + select MIPS_GIC_IPI select SYNC_R4K select WEAK_ORDERING default n help - Enable Coherency Manager processor (CMP) support. + Select this if you are using a bootloader which implements the "CMP + framework" protocol (ie. YAMON) and want your kernel to make use of + its ability to start secondary CPUs. + + Unless you have a specific need, you should use CONFIG_MIPS_CPS + instead of this. + +config MIPS_CPS + bool "MIPS Coherent Processing System support" + depends on SYS_SUPPORTS_MIPS_CPS + select MIPS_CM + select MIPS_CPC + select MIPS_GIC_IPI + select SMP + select SYNC_R4K if (CEVT_R4K || CSRC_R4K) + select SYS_SUPPORTS_SMP + select WEAK_ORDERING + help + Select this if you wish to run an SMP kernel across multiple cores + within a MIPS Coherent Processing System. When this option is + enabled the kernel will probe for other cores and boot them with + no external assistance. It is safe to enable this when hardware + support is unavailable. + +config MIPS_GIC_IPI + bool + +config MIPS_CM + bool + +config MIPS_CPC + bool config SB1_PASS_1_WORKAROUNDS bool @@ -2043,6 +2119,21 @@ config CPU_MICROMIPS When this option is enabled the kernel will be built using the microMIPS ISA +config CPU_HAS_MSA + bool "Support for the MIPS SIMD Architecture" + depends on CPU_SUPPORTS_MSA + default y + help + MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers + and a set of SIMD instructions to operate on them. When this option + is enabled the kernel will support allocating & switching MSA + vector register contexts. If you know that your kernel will only be + running on CPUs which do not support MSA or that your userland will + not be making use of it then you may wish to say N here to reduce + the size & complexity of your kernel. + + If unsure, say Y. + config CPU_HAS_WB bool @@ -2094,7 +2185,7 @@ config CPU_R4400_WORKAROUNDS # config HIGHMEM bool "High Memory Support" - depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM + depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA config CPU_SUPPORTS_HIGHMEM bool @@ -2108,6 +2199,9 @@ config SYS_SUPPORTS_SMARTMIPS config SYS_SUPPORTS_MICROMIPS bool +config CPU_SUPPORTS_MSA + bool + config ARCH_FLATMEM_ENABLE def_bool y depends on !NUMA && !CPU_LOONGSON2 @@ -2181,6 +2275,9 @@ config SMP_UP config SYS_SUPPORTS_MIPS_CMP bool +config SYS_SUPPORTS_MIPS_CPS + bool + config SYS_SUPPORTS_SMP bool @@ -2353,9 +2450,8 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. config MIPS_O32_FP64_SUPPORT - bool "Support for O32 binaries using 64-bit FP" + bool "Support for O32 binaries using 64-bit FP (EXPERIMENTAL)" depends on 32BIT || MIPS32_O32 - default y help When this is enabled, the kernel will support use of 64-bit floating point registers with binaries using the O32 ABI along with the @@ -2367,7 +2463,14 @@ config MIPS_O32_FP64_SUPPORT of your kernel & potentially improve FP emulation performance by saying N here. - If unsure, say Y. + Although binutils currently supports use of this flag the details + concerning its effect upon the O32 ABI in userland are still being + worked on. In order to avoid userland becoming dependant upon current + behaviour before the details have been finalised, this option should + be considered experimental and only enabled by those working upon + said details. + + If unsure, say N. config USE_OF bool @@ -2407,6 +2510,17 @@ config PCI your box. Other bus systems are ISA, EISA, or VESA. If you have PCI, say Y, otherwise N. +config HT_PCI + bool "Support for HT-linked PCI" + default y + depends on CPU_LOONGSON3 + select PCI + select PCI_DOMAINS + help + Loongson family machines use Hyper-Transport bus for inter-core + connection and device connection. The PCI bus is a subordinate + linked at HT. Choose Y for Loongson-3 based machines. + config PCI_DOMAINS bool |