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-rw-r--r--arch/mips/alchemy/common/power.c68
1 files changed, 14 insertions, 54 deletions
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 647e518c90b..bdd6651e9a4 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -37,8 +37,6 @@
#include <asm/uaccess.h>
#include <asm/mach-au1x00/au1000.h>
-#ifdef CONFIG_PM
-
/*
* We need to save/restore a bunch of core registers that are
* either volatile or reset to some state across a processor sleep.
@@ -49,7 +47,6 @@
* We only have to save/restore registers that aren't otherwise
* done as part of a driver pm_* function.
*/
-static unsigned int sleep_usb[2];
static unsigned int sleep_sys_clocks[5];
static unsigned int sleep_sys_pinfunc;
static unsigned int sleep_static_memctlr[4][3];
@@ -57,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
static void save_core_regs(void)
{
-#ifndef CONFIG_SOC_AU1200
- /* Shutdown USB host/device. */
- sleep_usb[0] = au_readl(USB_HOST_CONFIG);
-
- /* There appears to be some undocumented reset register.... */
- au_writel(0, 0xb0100004);
- au_sync();
- au_writel(0, USB_HOST_CONFIG);
- au_sync();
-
- sleep_usb[1] = au_readl(USBD_ENABLE);
- au_writel(0, USBD_ENABLE);
- au_sync();
-
-#else /* AU1200 */
-
- /* enable access to OTG mmio so we can save OTG CAP/MUX.
- * FIXME: write an OTG driver and move this stuff there!
- */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
- sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
- sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
-#endif
-
/* Clocks and PLLs. */
sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -125,22 +97,6 @@ static void restore_core_regs(void)
au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
au_sync();
-#ifndef CONFIG_SOC_AU1200
- au_writel(sleep_usb[0], USB_HOST_CONFIG);
- au_writel(sleep_usb[1], USBD_ENABLE);
- au_sync();
-#else
- /* enable access to OTG memory */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
-
- /* restore OTG caps and port mux. */
- au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
- au_sync();
- au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
- au_sync();
-#endif
-
/* Restore the static memory controller configuration. */
au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
@@ -158,15 +114,19 @@ static void restore_core_regs(void)
void au_sleep(void)
{
- int cpuid = alchemy_get_cputype();
- if (cpuid != ALCHEMY_CPU_UNKNOWN) {
- save_core_regs();
- if (cpuid <= ALCHEMY_CPU_AU1500)
- alchemy_sleep_au1000();
- else if (cpuid <= ALCHEMY_CPU_AU1200)
- alchemy_sleep_au1550();
- restore_core_regs();
+ save_core_regs();
+
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ alchemy_sleep_au1000();
+ break;
+ case ALCHEMY_CPU_AU1550:
+ case ALCHEMY_CPU_AU1200:
+ alchemy_sleep_au1550();
+ break;
}
-}
-#endif /* CONFIG_PM */
+ restore_core_regs();
+}