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-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h15
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h66
2 files changed, 8 insertions, 73 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bbf05404239..b952fc7215e 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -61,21 +61,18 @@
#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
-#define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
#define spin_lock_prefetch(x) prefetch(x)
#define PREFETCH_STRIDE 128
-static inline int read_current_timer(unsigned long *result)
-{
- asm volatile ("rdhwr %0,$31\n"
-#ifndef CONFIG_64BIT
- "\tsll %0, 0"
+#ifdef __OCTEON__
+/*
+ * All gcc versions that have OCTEON support define __OCTEON__ and have the
+ * __builtin_popcount support.
+ */
+#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
#endif
- : "=r" (*result));
- return 0;
-}
static inline int octeon_has_saa(void)
{
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index d32220fbf4f..6ddab8aef64 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,71 +172,9 @@
#ifdef CONFIG_PCI_MSI
/* 152 - 215 represent the MSI interrupts 0-63 */
#define OCTEON_IRQ_MSI_BIT0 152
-#define OCTEON_IRQ_MSI_BIT1 153
-#define OCTEON_IRQ_MSI_BIT2 154
-#define OCTEON_IRQ_MSI_BIT3 155
-#define OCTEON_IRQ_MSI_BIT4 156
-#define OCTEON_IRQ_MSI_BIT5 157
-#define OCTEON_IRQ_MSI_BIT6 158
-#define OCTEON_IRQ_MSI_BIT7 159
-#define OCTEON_IRQ_MSI_BIT8 160
-#define OCTEON_IRQ_MSI_BIT9 161
-#define OCTEON_IRQ_MSI_BIT10 162
-#define OCTEON_IRQ_MSI_BIT11 163
-#define OCTEON_IRQ_MSI_BIT12 164
-#define OCTEON_IRQ_MSI_BIT13 165
-#define OCTEON_IRQ_MSI_BIT14 166
-#define OCTEON_IRQ_MSI_BIT15 167
-#define OCTEON_IRQ_MSI_BIT16 168
-#define OCTEON_IRQ_MSI_BIT17 169
-#define OCTEON_IRQ_MSI_BIT18 170
-#define OCTEON_IRQ_MSI_BIT19 171
-#define OCTEON_IRQ_MSI_BIT20 172
-#define OCTEON_IRQ_MSI_BIT21 173
-#define OCTEON_IRQ_MSI_BIT22 174
-#define OCTEON_IRQ_MSI_BIT23 175
-#define OCTEON_IRQ_MSI_BIT24 176
-#define OCTEON_IRQ_MSI_BIT25 177
-#define OCTEON_IRQ_MSI_BIT26 178
-#define OCTEON_IRQ_MSI_BIT27 179
-#define OCTEON_IRQ_MSI_BIT28 180
-#define OCTEON_IRQ_MSI_BIT29 181
-#define OCTEON_IRQ_MSI_BIT30 182
-#define OCTEON_IRQ_MSI_BIT31 183
-#define OCTEON_IRQ_MSI_BIT32 184
-#define OCTEON_IRQ_MSI_BIT33 185
-#define OCTEON_IRQ_MSI_BIT34 186
-#define OCTEON_IRQ_MSI_BIT35 187
-#define OCTEON_IRQ_MSI_BIT36 188
-#define OCTEON_IRQ_MSI_BIT37 189
-#define OCTEON_IRQ_MSI_BIT38 190
-#define OCTEON_IRQ_MSI_BIT39 191
-#define OCTEON_IRQ_MSI_BIT40 192
-#define OCTEON_IRQ_MSI_BIT41 193
-#define OCTEON_IRQ_MSI_BIT42 194
-#define OCTEON_IRQ_MSI_BIT43 195
-#define OCTEON_IRQ_MSI_BIT44 196
-#define OCTEON_IRQ_MSI_BIT45 197
-#define OCTEON_IRQ_MSI_BIT46 198
-#define OCTEON_IRQ_MSI_BIT47 199
-#define OCTEON_IRQ_MSI_BIT48 200
-#define OCTEON_IRQ_MSI_BIT49 201
-#define OCTEON_IRQ_MSI_BIT50 202
-#define OCTEON_IRQ_MSI_BIT51 203
-#define OCTEON_IRQ_MSI_BIT52 204
-#define OCTEON_IRQ_MSI_BIT53 205
-#define OCTEON_IRQ_MSI_BIT54 206
-#define OCTEON_IRQ_MSI_BIT55 207
-#define OCTEON_IRQ_MSI_BIT56 208
-#define OCTEON_IRQ_MSI_BIT57 209
-#define OCTEON_IRQ_MSI_BIT58 210
-#define OCTEON_IRQ_MSI_BIT59 211
-#define OCTEON_IRQ_MSI_BIT60 212
-#define OCTEON_IRQ_MSI_BIT61 213
-#define OCTEON_IRQ_MSI_BIT62 214
-#define OCTEON_IRQ_MSI_BIT63 215
+#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
-#define OCTEON_IRQ_LAST 216
+#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
#else
#define OCTEON_IRQ_LAST 152
#endif