diff options
Diffstat (limited to 'arch/mips/include/asm/mips-boards/maltaint.h')
| -rw-r--r-- | arch/mips/include/asm/mips-boards/maltaint.h | 55 |
1 files changed, 7 insertions, 48 deletions
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index 5447d9fc421..66924481575 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -1,31 +1,16 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the Malta interrupt controller. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * + * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. + * Carsten Langgaard <carstenl@mips.com> + * Steven J. Hill <sjhill@mips.com> */ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -#include <irq.h> +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) /* * Interrupts 0..15 are used for Malta ISA compatible interrupts @@ -78,26 +63,6 @@ #define MSC01E_INT_PERFCTR 10 #define MSC01E_INT_CPUCTR 11 -/* GIC's Nomenclature for Core Interrupt Pins on the Malta */ -#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ -#define GIC_CPU_INT1 1 /* . */ -#define GIC_CPU_INT2 2 /* . */ -#define GIC_CPU_INT3 3 /* . */ -#define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 5 */ - -/* MALTA GIC local interrupts */ -#define GIC_INT_TMR (GIC_CPU_INT5) -#define GIC_INT_PERFCTR (GIC_CPU_INT5) - -/* GIC constants */ -/* Add 2 to convert non-eic hw int # to eic vector # */ -#define GIC_CPU_TO_VEC_OFFSET (2) -/* If we map an intr to pin X, GIC will actually generate vector X+1 */ -#define GIC_PIN_TO_VEC_OFFSET (1) - -#define GIC_EXT_INTR(x) x - /* External Interrupts used for IPI */ #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 @@ -108,10 +73,4 @@ #define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 #define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) - -#ifndef __ASSEMBLY__ -extern void maltaint_init(void); -#endif - #endif /* !(_MIPS_MALTAINT_H) */ |